FEATURES
q35ns maximum (3.3 volt supply) address access time
qMCM contains four (4) 512K x 8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24, or 32-bit data width
qTTL compatible inputs and output levels, three-state
bidirectional data bus
qTypical radiation performance
- Total dose
- Solution #1: Up to 30krads
- Solution #2: Up to 300krads
- SEL Immune >100 MeV-cm2/mg
- LETTH(0.25) = 40 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 10E-9
- 3.8E-11errors/bit-day, Adams 90% geosynchronous
heavy ion
- Inherent Neutron Hardness: 1.0E14n/cm2
- Nominal Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
qPackaging options:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
qStandard Microcircuit Drawing pending
- QML T and Q compliant part
INTRODUCTION
The UT8Q512K32 is a high-performance 2M byte (16Mbit)
CMOS static RAM multi-chip module (MCM), organized
as four individual 524,288 x 8 bit SRAMs with a common
output enable. Memory expansion is provided by an active
LOW chip enable (En), an active LOW output enable (G),
and three-state drivers. This device has a power-down
feature that reduces power consumption by more than 90%
when deselected.
Writing to each memory is accomplished by taking the chip
enable (En) input LOW and write enable (Wn) inputs LOW.
Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking the chip enable
(En) and output enable (G) LOW while forcing write enable
(Wn) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear
on the I/O pins.
The input/output pins are placed in a high impedance state
when the device is deselected (En HIGH), the outputs are
disabled (G HIGH), or during a write operation (En LOW
and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by
making Wn along with G a common input to any
combination of the discrete memory die.
Figure 1. UT8Q512K32 SRAM Block Diagram
512K x 8 512K x 8 512K x 8 512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:3)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
G
A(18:0)
W3
E3E2E1E0
W2W1W0
Standard Products
UT8Q512K32 16Megabit SRAM MCM
Preliminary Data Sheet
August 3, 2000
2
PIN NAMES
DEVICE OPERATION
Each die in the UT8Q512K32 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die by selecting the 2,048,000 byte of
memory. Wn controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) with En and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQn(7:0)
after the specified tAVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0) Address WnWriteEnable
DQ(7:0) Data Input/Output GOutput Enable
EnDevice Enable VDD Power
VSS Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Top View
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
NC
A0
A1
A2
A3
A4
A5
E2
VSS
E3
W1
A6
A7
A8
A9
A10
VDD
VDD
A11
A12
A13
A14
A15
A16
E0
G
E1
A17
W2
W3
W4
A18
NC
NC
Figure 2. 25ns SRAM Pinout (68)
GWnEnI/O Mode Mode
X1X13-state Standby
X0 0 Data in Write
1103-state Read2
010Data out Read
3
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated by Wn, and by tETWH when the write is initiated by En.
Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the eight bidirectional pins DQn(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQn(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q512K32 SRAM incorporates features which allow
operation in a limited radiation environment.
Table 2. Typical Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose 30 krad(Si) nominal
Heavy Ion
Error Rate23.8E-11 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 4.6V
VI/O Voltage on any pin -0.5 to 4.6V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.0W (per byte)
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-55°C to +125°C) (VDD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (CMOS) 2.0 V
VIL Low-level input voltage (CMOS) 0.8 V
VOL1 Low-level output voltage IOL = 8mA, VDD =3.0V 0.4 V
VOL2 Low-level output voltage IOL = 200µA,VDD =3.0V 0.08V
VOH1High-level output voltage IOH = -4mA,VDD =3.0V 2.4 V
VOH2High-level output voltage IOH = -200µA,VDD =3.0V VDD-0.10 V
CIN1Input capacitance ƒ = 1MHz @ 0V 10 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF
IIN Input leakage current VSS < VIN < VDD, VDD = VDD (max) -2 2µA
IOZ Three-state output leakage current 0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
-2 2µA
IOS2, 3 Short-circuit output current 0V < VO < VDD -90 90 mA
IDD(OP) Supply current operating
@ 1MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
125 mA
IDD1(OP) Supply current operating
@40MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
180 mA
IDD2(SB) Nominal standby supply current
@0MHz
25°C
3.6V pre-radiation
(per byte)
Inputs: VIL = VSS
IOUT = 0mA
En = VDD - 0.5, VDD = VDD (max)
VIH = VDD - 0.5V
6mA
6
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-55°C to +125°C) (VDD = 3.3V + 0.3)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Read cycle time 35 ns
tAVQV Read access time 35 ns
tAXQX2Output hold time 3ns
tGLQX2G-controlled Output Enable time 3ns
tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns
tGHQZ2G-controlled output three-state time 10 ns
tETQX2,3 En-controlled Output Enable time 3ns
tETQV3En-controlled access time 25 ns
tEFQZ1,2,4En-controlled output three-state time 10 ns
{
{}
}
VLOAD + 300mV
VLOAD - 300mV
VLOAD
VH - 300mV
VL + 300mV
Active to High Z LevelsHigh Z to Active Levels
Figure 3. 3-Volt SRAM Loading
7
Assumptions:
1. En and G < VIL (max) and Wn > VIH (min)
A(18:0)
DQn(7:0)
Figure 4a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < VIL (max) and Wn > VIH (min)
A(18:0)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
En
DATA VALID
tEFQZ
tETQX
tETQV
DQn(7:0)
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
A(18:0)
DQn(7:0)
GtGHQZ
Assumptions:
1. En < VIL (max) and Wn > VIH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-55°C to +125°C) (VDD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Write cycle time 35 ns
tETWH Device Enable to end of write 20 ns
tAVET Address setup time for write (En - controlled) 0ns
tAVWL Address setup time for write (Wn - controlled) 0ns
tWLWH Write pulse width 20 ns
tWHAX Address hold time for write (Wn - controlled) 2ns
tEFAX Address hold time for Device Enable (En - controlled) 2ns
tWLQZ2Wn- controlled three-state time 10 ns
tWHQX2Wn - controlled Output Enable time 5ns
tETEF Device Enable pulse width (En - controlled) 20 ns
tDVWH Data setup time 15 ns
tWHDX2Data hold time 2ns
tWLEF Device Enable controlled write pulse width 20 ns
tDVEF2Data setup time 15 ns
tEFDX Data hold time 2ns
tAVWH Address valid to end of write 20 ns
tWHWL1Write disable time 5ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
Wn
tAVWL
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Qn(7:0)
En
tAVAV2
Dn(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
10
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Qn(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for tAVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
Wn
En
Dn(7:0) APPLIED DATA
En
Qn(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tAVET
tETEF
tEFAX
tEFAX
or
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
VLOAD = 1.55
680 ohms
50pF
CMOS
0.5V
90%
VDD-0.05V
10%
11
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(TC = 25°°C, 1 Second Data Rentention Test)
Notes:
1. En = VDD - .2V, all other inputs = VDR or VSS.
2. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(TC = 25°°C, 10 Second Data Retention Test)
Notes:
1. Performed at VDD (min) and VDD (max).
2. En = VSS, all other inputs = VDR or VSS.
3. Not guaranteed or tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDR VDD for data retention 2.0 -- V
IDDR 1 Data retention current (per byte) -- 2.0mA
tEFR1,2 Chip select to data retention time 0ns
tR1,2 Operation recovery time tAVAV ns
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDD1VDD for data retention 4.5 5.5 V
tEFR2, 3 Chip select to data retention time 0ns
tR2, 3 Operation recovery time tAVAV ns
VDD
DATA RETENTION MODE
tR
50%
50% VDR > 2.0V
Figure 7. Low VDD Data Retention Waveform
tEFR
En
12
PACKAGING
Figure 8. 68-pin Ceramic FLATPACK
13
ORDERING INFORMATION
512K32 16Megabit SRAM MCM:
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.
4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125 °C. Radiation neither
tested nor guaranteed.
Device Type:
(8Q512K32) = 16Megabit SRAM MCM
Package Type:
(S) = 68-lead dual cavity CQFP
Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
UT ***** -* * *
14
512K32 16Megabit SRAM MCM: SMD
5962 - **TBD** **
* * *
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML T not available without radiation hardening
Federal Stock Class Designator: No Options
Total Dose
(D) = 1E4 (10krad(Si))
(P) = 3E4 (30krad(Si)) (contact factory)
Drawing Number: TBD
Device Type
01 = 35ns access time, 3.3V operation
Class Designator:
(T) = QML Class T
(Q) = QML Class Q
Case Outline:
(S) = 68-lead dual cavity CQFP
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
