MC34071,2,4,A MC33071,2,4,A Single Supply 3.0 V to 44 V Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/s slew rate and fast settling time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (VEE). With a Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33071/72/74, MC34071/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC and TSSOP surface mount packages. * Wide Bandwidth: 4.5 MHz * High Slew Rate: 13 V/s * Fast Settling Time: 1.1 s to 0.1% * Wide Single Supply Operation: 3.0 V to 44 V * Wide Input Common Mode Voltage Range: Includes Ground (VEE) * Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) * Large Output Voltage Swing: -14.7 V to +14 V (with 15 V Supplies) * Large Capacitance Drive Capability: 0 pF to 10,000 pF * Low Total Harmonic Distortion: 0.02% * Excellent Phase Margin: 60 * Excellent Gain Margin: 12 dB * Output Short Circuit Protection * ESD Diodes/Clamps Provide Input Protection for Dual and Quad Semiconductor Components Industries, LLC, 2002 January, 2002 - Rev. 5 1 http://onsemi.com PDIP-8 P SUFFIX CASE 626 8 1 SO-8 D SUFFIX CASE 751 8 1 PDIP-14 P SUFFIX CASE 646 14 1 SO-14 D SUFFIX CASE 751A 14 1 14 1 TSSOP-14 DTB SUFFIX CASE 948G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 18 of this data sheet. Publication Order Number: MC34071/D MC34071,2,4,A MC33071,2,4,A PIN CONNECTIONS CASE 646/CASE 751A/CASE 948G CASE 626/CASE 751 Offset Null Inputs VEE 1 8 NC 2 - 7 VCC 3 + 6 Output 5 Offset Null 4 Output 1 Inputs 1 1 8 2 Inputs 1 VEE 7 + 3 + VCC 4 Inputs 2 VCC Output 2 6 5 14 2 13 + 3 (Single, Top View) Output 1 1 Output 2 4 1 + 12 4 11 5 + - 6 2 3 10 + - 9 7 8 Inputs 2 Output 4 Inputs 4 VEE Inputs 3 Output 3 (Quad, Top View) (Dual, Top View) VCC Q3 Q1 Q4 Q6 Q5 Q7 Q17 Q2 R1 Bias Q8 - C1 Q9 R2 D2 Q11 Q10 Q18 R6 R7 Output R8 Inputs + C2 Base Current Cancellation Q13 Q15 Q14 D3 Q19 Q16 Q12 D1 R3 Current Limit R5 R4 VEE/Gnd Offset Null (MC33071, MC34071 only) Figure 1. Representative Schematic Diagram (Each Amplifier) MAXIMUM RATINGS Rating Symbol Value Unit VS +44 V Input Differential Voltage Range VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Operating Junction Temperature TJ +150 C Storage Temperature Range Tstg -60 to +150 C Supply Voltage (from VEE to VCC) 1. Either or both input voltages should not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2). http://onsemi.com 2 MC34071,2,4,A MC33071,2,4,A ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground, unless otherwise noted. See Note 3 for TA = Tlow to Thigh) A Suffix Characteristics Symbol Input Offset Voltage (RS = 100 , VCM = 0 V, VO = 0 V) VCC = +15 V, VEE = -15 V, TA = +25C VCC = +5.0 V, VEE = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh VIO Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = Tlow to Thigh IIB Input Offset Current (VCM = 0 V, VO = 0V) TA = +25C TA = Tlow to Thigh IIO Input Common Mode Voltage Range TA = +25C TA = Tlow to Thigh VICR Large Signal Voltage Gain (VO = 10 V, RL = 2.0 k) TA = +25C TA = Tlow to Thigh AVOL Output Voltage Swing (VID = 1.0 V) VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 k, TA = Tlow to Thigh VOH VCC = +5.0 V, VEE = 0 V, RL = 2.0 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 k, TA = Tlow to Thigh VOL Typ Max 0.5 0.5 - 3.0 3.0 5.0 - 10 - - - 100 - - - 6.0 - - - - VIO/T Average Temperature Coefficient of Input Offset Voltage RS = 10 , VCM = 0 V, VO = 0 V, TA = Tlow to Thigh Min Non-Suffix Min Typ Max 1.0 1.5 - 5.0 5.0 7.0 - 10 - 500 700 - - 100 - 500 700 50 300 - - 6.0 - 75 300 - - - mV V/C nA nA V VEE to (VCC -1.8) VEE to (VCC -2.2) Output Short Circuit Current (VID = 1.0 V, VO = 0 V, TA = 25C) Source Sink Unit VEE to (VCC -1.8) VEE to (VCC -2.2) V/mV 50 25 100 - - - 25 20 100 - - - 3.7 13.6 13.4 4.0 14 - - - - 3.7 13.6 13.4 4.0 14 - - - - 0.1 -14.7 - 0.3 -14.3 -13.5 - - - 0.1 -14.7 - 0.3 -14.3 -13.5 V - - - ISC V mA 10 20 30 30 - - 10 20 30 30 - - Common Mode Rejection RS 10 k, VCM = VICR, TA = 25C CMR 80 97 - 70 97 - dB Power Supply Rejection (RS = 100 ) VCC/VEE = +16.5 V/-16.5 V to +13.5 V/-13.5 V, TA = 25C PSR 80 97 - 70 97 - dB - - - 1.6 1.9 - 2.0 2.5 2.8 - - - 1.6 1.9 - 2.0 2.5 2.8 Power Supply Current (Per Amplifier, No Load) VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = Tlow to Thigh 3. Tlow = -40C for MC33071, 2, 4, /A = 0C for MC34071, 2, 4, /A = -40C for MC34072, 4/V ID Thigh mA = +85C for MC33071, 2, 4, /A = +70C for MC34071, 2, 4, /A = +125C for MC34072, 4/V http://onsemi.com 3 MC34071,2,4,A MC33071,2,4,A AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground. TA = +25C, unless otherwise noted.) A Suffix Characteristics Symbol Slew Rate (Vin = -10 V to +10 V, RL = 2.0 k, CL = 500 pF) AV = +1.0 AV = -1.0 Non-Suffix Min Typ Max Min Typ Max 8.0 - 10 13 - - 8.0 - 10 13 - - - - 1.1 2.2 - - - - 1.1 2.2 - - GBW 3.5 4.5 - 3.5 4.5 - MHz BW - 160 - - 160 - kHz - - 60 40 - - - - 60 40 - - - - 12 4.0 - - - - 12 4.0 - - SR Setting Time (10 V Step, AV = -1.0) To 0.1% (+1/2 LSB of 9-Bits) To 0.01% (+1/2 LSB of 12-Bits) V/s s ts Gain Bandwidth Product (f = 100 kHz) Power Bandwidth AV = +1.0, RL = 2.0 k, VO = 20 Vpp, THD = 5.0% Unit Phase margin RL = 2.0 k RL = 2.0 k, CL = 300 pF fm Gain Margin RL = 2.0 k RL = 2.0 k, CL = 300 pF Am Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz en - 32 - - 32 - nV/ Hz Equivalent Input Noise Current f = 1.0 kHz in - 0.22 - - 0.22 - pA/ Hz Differential Input Resistance VCM = 0 V Rin - 150 - - 150 - M Differential Input Capacitance VCM = 0 V Cin - 2.5 - - 2.5 - pF THD - 0.02 - - 0.02 - % - - 120 - - 120 - dB |ZO| - 30 - - 30 - W Total Harmonic Distortion AV = +10, RL = 2.0 k, 2.0 Vpp VO 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Single Supply Deg dB Split Supplies VCC+|VEE|44 V 3.0 V to 44 V VCC VCC VCC 2 1 VCC 1 2 2 3 3 VEE 4 3 6 + 4 1 5 10 k 4 VEE 7 - VEE Offset nulling range is approximately 80 mV with a 10 k potentiometer (MC33071, MC34071 only). VEE Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit http://onsemi.com 4 V IO INPUT OFFSET VOLTAGE (mV) V, 2400 2000 1600 8 & 14 Pin Plastic Pkg SO-14 Pkg 1200 800 400 0 0 20 40 60 80 100 120 140 160 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 4. Maximum Power Dissipation versus Temperature for Package Types Figure 5. Input Offset Voltage versus Temperature for Representative Units VCC VCC VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V VCC -0.8 VCC -1.6 VCC -2.4 VEE +0.01 VEE VEE -55 -25 0 25 50 75 100 125 125 1.3 VCC = +15 V VEE = -15 V VCM = 0 1.2 1.1 1.0 0.9 0.8 0.7 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 6. Input Common Mode Voltage Range versus Temperature Figure 7. Normalized Input Bias Current versus Temperature 125 50 1.4 VCC = +15 V VEE = -15 V TA = 25C 1.2 VO, OUTPUT VOLTAGE SWING (Vpp ) I, IB INPUT BIAS CURRENT (NORMALIZED) 2.0 -4.0 0 -55 -40 -20 1.0 0.8 0.6 VCC = +15 V VEE = -15 V VCM = 0 4.0 -2.0 SO-8 Pkg V, ICR INPUT COMMON MODE VOLTAGE RANGE (V) I, IB INPUT BIAS CURRENT (NORMALIZED) P, D MAXIMUM POWER DISSIPATION (mW) MC34071,2,4,A MC33071,2,4,A -12 -8.0 -4.0 0 4.0 8.0 40 30 RL = 10 k RL = 2.0 k 20 10 0 12 RL Connected to Ground TA = 25C 0 5.0 10 15 20 VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V) Figure 8. Normalized Input Bias Current versus Input Common Mode Voltage Figure 9. Split Supply Output Voltage Swing versus Supply Voltage http://onsemi.com 5 25 VCC/VEE = +5.0 V/ -5.0 V to +22 V/ -22 V TA = 25C VCC VCC -1.0 Source VCC -2.0 VEE +1.0 Sink VEE VCC-2.0 0 5.0 10 15 0.1 Gnd 0 100 20 100 k Figure 10. Single Supply Output Saturation versus Load Resistance to VCC Figure 11. Split Supply Output Saturation versus Load Current I, SC OUTPUT CURRENT (mA) VCC 2.0 VCC = +15 V RL to VCC TA = 25C 1.0 Gnd 100 Z, O OUTPUT IMPEDANCE () 10 k RL, LOAD RESISTANCE TO GROUND () -0.8 30 1.0 k IL, LOAD CURRENT (mA) 60 -0.4 40 VCC = +15 V RL = Gnd TA = 25C 0.2 0 50 VCC VCC-4.0 VEE +2.0 VEE VCC 1.0 k 10 k Sink 40 Source 30 20 VCC = +15 V VEE = -15 V RL 0.1 Vin = 1.0 V 10 -25 0 25 50 75 100 RL, LOAD RESISTANCE TO VCC () TA, AMBIENT TEMPERATURE (C) Figure 12. Single Supply Output Saturation versus Load Resistance to Ground Figure 13. Output Short Circuit Current versus Temperature 20 AV = 1000 AV = 100 AV = 10 AV = 1.0 10 10 k 125 28 VCC = +15 V VEE = -15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C 0 1.0 k 50 0 -55 100 k VO, OUTPUT VOLTAGE SWING (Vpp ) Vsat , OUTPUT SATURATION VOLTAGE (V) Vsat , OUTPUT SATURATION VOLTAGE (V) VCC Vsat , OUTPUT SATURATION VOLTAGE (V) MC34071,2,4,A MC33071,2,4,A 100 f, FREQUENCY (Hz) 1.0 M 10 M VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k THD 1.0% TA = 25C 24 20 16 12 8.0 4.0 0 3.0 k Figure 14. Output Impedance versus Frequency 10 k 30 k 100 k 300 k f, FREQUENCY (Hz) 1.0 M Figure 15. Output Voltage Swing versus Frequency http://onsemi.com 6 3.0 M MC34071,2,4,A MC33071,2,4,A THD, TOTAL HARMONIC DISTORTION (%) AV = 1000 0.3 VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 2.0 k TA = 25C 0.2 AV = 100 0.1 AV = 10 10 100 1.0 k 10 k 108 AV = 1000 2.0 AV = 100 1.0 AV = 10 AV = 1.0 0 0 4.0 20 100 VCC = +15 V VEE = -15 V VO= -10 V to +10 V RL = 10 k f 10Hz -25 0 25 50 75 100 125 0 80 40 20 0 1.0 120 140 -10 1. Phase RL = 2.0 k 2. Phase RL = 2.0 k, CL = 300 pF -20 3. Gain RL = 2.0 k 4. Gain RL = 2.0 k, CL = 300 pF -30 VCC = +15 V VEE = 15 V VO = 0 VTA = 25C -40 1.0 2.0 3.0 5.0 7.0 GBW, GAIN BANDWIDTH PRODUCT (NORMALIED) Gain Margin = 12 dB 0 3 4 160 180 2 10 Phase Margin = 60 VCC = +15 V VEE = -15 V VO = 0 V RL = 2.0 k TA = 25C 10 90 135 180 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M Figure 19. Open Loop Voltage Gain and Phase versus Frequency 100 Phase Margin = 60 45 60 f, FREQUENCY (Hz) 20 , EXCESS PHASE (DEGREES) 1 Gain Phase Figure 18. Open Loop Voltage Gain versus Temperature A, VOL OPEN LOOP VOLTAGE GAIN (dB) 16 Figure 17. Total Harmonic Distortion versus Output Voltage Swing TA, AMBIENT TEMPERATURE (C) 10 12 Figure 16. Total Harmonic Distortion versus Frequency 100 20 8.0 VO, OUTPUT VOLTAGE SWING (Vpp) 104 96 -55 VCC = +15 V VEE = -15 V RL = 2.0 k TA = 25C f, FREQUENCY (Hz) 116 112 3.0 100 k A, VOL OPEN LOOP VOLTAGE GAIN (dB) A, VOL OPEN LOOP VOLTAGE GAIN (dB) 0 AV = 1.0 4.0 , EXCESS PHASE (DEGREES) THD, TOTAL HARMONIC DISTORTION (%) 0.4 30 1.15 VCC = +15 V VEE = -15 V RL = 2.0 k 1.1 1.05 1.0 0.95 0.9 0.85 -55 -25 0 25 50 75 100 f, FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (C) Figure 20. Open Loop Voltage Gain and Phase versus Frequency Figure 21. Normalized Gain Bandwidth Product versus Temperature http://onsemi.com 7 125 MC34071,2,4,A MC33071,2,4,A 70 VCC = +15 V VEE = -15 V RL = 2.0 k VO = -10 V to +10 V TA = 25C 80 60 m , PHASE MARGIN (DEGREES) 40 20 0 10 100 1.0 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V TA = 25C 60 50 40 30 20 10 0 10 10 k 100 CL, LOAD CAPACITANCE (pF) Figure 23. Phase Margin versus Load Capacitance 14 80 A, m GAIN MARGIN (dB) 10 8.0 m , PHASE MARGIN (DEGREES) VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V TA = 25C 12 6.0 4.0 2.0 10 100 1.0 k CL = 100 pF 60 CL = 10 pF 40 CL = 1,000 pF 20 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V CL = 10,000 pF 0 -55 10 k -25 0 25 50 75 100 125 CL, LOAD CAPACITANCE (pF) TA, AMBIENT TEMPERATURE (C) Figure 24. Gain Margin versus Load Capacitance Figure 25. Phase Margin versus Temperature 16 8.0 4.0 10 CL = 10 pF VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V A, m GAIN MARGIN (dB) 12 CL = 100 pF CL = 10,000 pF CL = 1,000 pF -25 0 25 50 75 100 125 R1 6.0 4.0 2.0 60 Gain 8.0 0 0 -55 70 12 VCC = +15 V A, m GAIN MARGIN (dB) 10 k CL, LOAD CAPACITANCE (pF) Figure 22. Percent Overshoot versus Load Capacitance 0 1.0 k 50 - VO 40 + R2 30 VCC = +15 V VEE = -15 V RT = R1 + R2 AV = +100 VO = 0 V TA = 25C 1.0 10 20 Phase 10 100 1.0 k 10 k TA, AMBIENT TEMPERATURE (C) RT, DIFFERENTIAL SOURCE RESISTANCE () Figure 26. Gain Margin versus Temperature Figure 27. Phase Margin and Gain Margin versus Differential Source Resistance http://onsemi.com 8 0 100 k m , PHASE MARGIN (DEGREES) PERCENT OVERSHOOT 100 MC34071,2,4,A MC33071,2,4,A V, O OUTPUT VOLTAGE SWING FROM 0 V (V) SR, SLEW RATE (NORMALIZED) 1.15 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 500 pF 1.1 1.05 1.0 0.95 10 5.0 0.85 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) -10 Compensated Uncompensated 0 1.0 mV 0.5 1.0 1.5 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C 0 100 VCC = +15 V VEE = -15 V VCM = 0 V VCM = 1.5 V TA = 25C 60 ADM VCM 20 VCM CMR = 20 Log 0 0.1 1.0 VO + VO 10 100 x ADM 1.0 k 3.5 Figure 31. Large Signal Transient Response PSR, POWER SUPPLY REJECTION (dB) CMR, COMMON MODE REJECTION (dB) TA = 125C TA = -55C 40 3.0 1.0 s/DIV Figure 30. Small Signal Transient Response 80 2.5 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C 2.0 s/DIV 100 2.0 ts, SETTLING TIME (s) Figure 29. Output Settling Time 5.0 V/DIV 50 mV/DIV 1.0 mV 10 mV Figure 28. Normalized Slew Rate versus Temperature 0 VCC = +15 V VEE = -15 V AV = -1.0 TA = 25C 1.0 mV 0 -5.0 0.9 1.0 mV 10 mV 10 k 100 k 1.0 M 10 M VCC = +15 V VEE = -15 V TA = 25C 80 VCC 60 40 ADM VEE +PSR = 20 Log 20 1.0 +PSR VO/ADM VCC VO/ADM -PSR = 20 Log 0 0.1 (VCC = +1.5 V) VO + -PSR (VEE = +1.5 V) VEE 10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 32. Common Mode Rejection versus Frequency Figure 33. Power Supply Rejection versus Frequency http://onsemi.com 9 MC34071,2,4,A MC33071,2,4,A 105 TA = -55C 8.0 7.0 TA = 25C 6.0 TA = 125C 5.0 4.0 0 5.0 10 15 20 25 85 +PSR = 20 Log 75 -PSR = 20 Log 65 -55 -25 0 VO/ADM ADM VCC VO + VO/ADM VEE VEE 25 VCC 50 75 100 Figure 35. Power Supply Rejection versus Temperature VCC = +15 V VEE = -15 V TA = 25C 40 20 10 +PSR (VCC = +1.5 V) Figure 34. Supply Current versus Supply Voltage 60 0 95 TA, AMBIENT TEMPERATURE (C) e, n INPUT NOICE VOLTAGE ( nV Hz) CHANNEL SEPARATION (dB) 80 VCC = +15 V VEE = -15 V VCC, |VEE|, SUPPLY VOLTAGE (V) 120 100 -PSR (VEE = +1.5 V) 20 30 50 70 100 200 300 2.8 70 VCC = +15 V VEE = -15 V VCM = 0 TA = 25C 60 50 40 2.4 2.0 1.6 Voltage 30 1.2 Current 20 0.8 10 0 125 0.4 10 100 1.0 k 10 k 0 100 k i, n INPUT NOISE CURRENT (pA Hz ) PSR, POWER SUPPLY REJECTION (dB) I CC , SUPPLY CURRENT (mA) 9.0 f, FREQUENCY (kHz) f, FREQUENCY (kHz) Figure 36. Channel Separation versus Frequency Figure 37. Input Noise versus Frequency APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the MC34071 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to 44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VEE and VCC supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the VCC voltage by approximately 3.0 V and decrease below the VEE voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to approximately 5.0 mA of current from VEE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pF) than the typical JFET input gate capacitance (5.0 pF), better frequency response for a given input source resistance can be achieved using the MC34071 series of amplifiers. This performance feature becomes evident, for example, in fast settling D-to-A current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher http://onsemi.com 10 MC34071,2,4,A MC33071,2,4,A minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier's high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (30 typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 10,000 pF without oscillation in the unity closed loop gain configuration. The 60 phase margin and 12 dB gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5.0 V, these amplifiers are functional to 3.0 V @ 25C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for 15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating. values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2.0 k of feedback resistance, the MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0 s, and within 1/2 LSB of 12-bits in 2.2 s for a 10 V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is 13 V/s. In the classic noninverting unity gain configuration, the output positive slew rate is +10 V/s, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3.0 mV prime and 5.0 mV downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 k load resistance can swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 Vpp swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q7, and VBE of the NPN pull up transistor Q17, and the voltage drop associated with the short circuit resistance, R7. The negative swing is limited by the saturation voltage of the pull-down transistor Q16, the voltage drop ILR6, and the voltage drop associated with resistance R7, where IL is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For large valued sink currents (>5.0 mA), diode D3 clamps the voltage across R6, thus limiting the negative swing to the saturation voltage of Q16, plus the forward diode drop of D3 (VEE +1.0 V). Thus for a given supply voltage, unprecedented peak-to-peak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitter-follower transistor has been eliminated, the MC34071 series offers a 20 mA http://onsemi.com 11 MC34071,2,4,A MC33071,2,4,A (Typical Single Supply Applications VCC = 5.0 V) VCC 5.1 M VO 0 3.7 Vpp 0 VCC 20 k 100 k 1.0 M Cin CO + VO MC34071 36.6 mVpp 68 k Cin 100 k Vin 1.0 k 10 k RL AV = 101 MC34071 - VO CO 10 k RL 100 k AV = 10 BW (-3.0 dB) = 450 kHz Figure 38. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier VCC 4.75 Vpp 2.63 V + 10 k Vin 370 mVpp BW (-3.0 dB) = 45 kHz VO 3.7 Vpp 91 k 5.1 k RL 5.1 k 2.5 V + VO MC34071 100 k - 0 1.0 M Vin - Vin R 16 k C 0.01 32 k R 16 k R1 MC34071 + TTL Gate R3 2.2 k MC34071 C 0.047 VO + VCC 0.4 VCC VO fo = 30 kHz Ho = 10 Ho = 1.0 Given fo = Center Frequency AO = Gain at Center Frequency Choose Value fo, Q, Ao, C fo = 1.0 kHz fo = 2.0 C 0.02 C 0.047 1.1 k R2 5.6 k Then: 2.0 R Cable Figure 41. Unity Gain Buffer TTL Driver Vin - MC54/74XX MC34071 AV = 10 BW (-3.0 dB) = 450 kHz Figure 40. DC Coupled Inverting Amplifier Maximum Output Swing Vin 0.2 Vdc 0 to 10,000 pF + Vin 1 4RC R3 = Q R3 R1 = foC 2Ho R2 = R1 R3 4Q2R1-R3 For less than 10% error from operational amplifier Qofo GBW < 0.1 where fo and GBW are expressed in Hz. GBW = 4.5 MHz Typ. 2.0 C 0.02 Figure 43. Active Bandpass Filter Figure 42. Active High-Q Notch Filter http://onsemi.com 12 MC34071,2,4,A MC33071,2,4,A Vin CF 2.0 V RF 5.0 k 5.0 k 5.0 k Vin - VO MC34071 10 k 10 k + 10 k VO + MC34071 - VCC 1.0 V t 2.0 k RL VO 0.2 s Delay 4.0 V Bit Switches 13 V/s (R-2R) Ladder Network 25 V/s 0.1 t Delay 1.0 s Settling Time 1.0 s (8-Bits, 1/2 LSB) Figure 44. Low Voltage Fast D/A Converter VCC Figure 45. High Speed Low Voltage Comparator ON" Vin < Vref VCC VCC + Vin RL MC34071 - Vref + + MC34071 MC34071 - - ON" Vin > Vref RL (A) PNP Figure 46. LED Driver (B) NPN Figure 47. Transistor Driver ILoad RF + MC34071 Ground Current Sense Resistor VO - RS R2 - ICell R1 MC34071 + VO = ILoad RS 1+ VO R1 R2 For VO > 0.1V BW ( -3.0 dB) = GBW VCell = 0 V R2 R1+R2 Figure 48. AC/DC Ground Current Monitor VO = ICell RF VO > 0.1 V Figure 49. Photovoltaic Cell Amplifier http://onsemi.com 13 MC34071,2,4,A MC33071,2,4,A Hysteresis VO R2 Vref R1 VOH + MC34071 - Vin VinL = R1 (VOL-Vref)+Vref R1+R2 VinH = R1 (VOH-Vref)+Vref R1+R2 VH = R1 (VOH -VOL) R1+R Iout VOL VinL VinH Vref Vin Vin - Iout = Figure 50. Low Input Voltage Comparator with Hysteresis R1 R2 +Vref - 1/2 MC34072 + R VO R - + +V2 For (V2 V1), V > 0 Figure 52. High Input Impedance Differential Amplifier VO = Vref 2R2 (VO 0.1 V) 0.85 RC + IB V VO = Vin (pk) MC34071 R RF Figure 53. Bridge Current Amplifier fOSC + + RF R < < R RF > > R VO MC34071 R R = R R2 R4 = (Critical to CMRR) R1 R3 R4 R4 VO = 1 + V2-V1 R3 R3 Vin R RF R3 MC34072 R VinVIO Figure 51. High Compliance Voltage to Sink Current Converter R4 - 1/2 +V1 + MC34071 VP 0 t - + ISC t Base Charge Removal - Iout RL VP + - 1/2 10,000 pF + 1/2 MC34072 MC34072 C + V+ IB - 100 k 100 k Vin R 47 k VP Pulse Width Control Group VP OSC t Figure 54. Low Voltage Peak Detector Comparator High Current Output Figure 55. High Frequency Pulse Width Modulation http://onsemi.com 14 MC34071,2,4,A MC33071,2,4,A GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = 15.0 V C2 0.02 R1 560 C2 0.05 - R2 5.6 k R3 510 C1 1.0 MC34071 C1 0.44 R1 46.1 k C1 1.0 fo = 1.0 kHz Ho = 10 + MC34071 R2 1.1 k Then: R1 = Choose: fo, Ho, C1 Choose: fo, Ho, C2 Then: C1 = 2C2 (Ho+1) R2 = 2 R3 = 4foC2 R2 Ho+1 R1 = R2 = R2 Ho C2 = Figure 56. Second Order Low-Pass Active Filter fo = 100 Hz Ho = 20 + Ho+0.5 foC1 2 2 2foC1 (1/Ho+2) C Ho Figure 57. Second Order High-Pass Active Filter CF* VO = 10 V Step RF 2.0 k + MC34071 - + I High Speed DAC Vin ts = 1.0 s Uncompensated RL R2 to 1/2 LSB (8-Bits) ts = 2.2 s Compensated VO to 1/2 LSB (12-Bits) Vin = R2 BW (-3.0 dB) = GBW R1 SR = 13 V/s *Optional Compensation VO MC34071 R1 VO R1 R1 +R2 SR = 13 V/s Figure 58. Fast Settling Inverter Figure 59. Basic Inverting Amplifier + VO MC34071 - Vin Vin R2 RL R1 VO Vin = 1+ MC34071 - R2 R1 BW (-3.0 dB) = GBW + VO BWp = 200 kHz VO = 20 Vpp SR = 10 V/s R1 R1 +R2 Figure 60. Basic Noninverting Amplifier Figure 61. Unity Gain Buffer (AV = +1.0) http://onsemi.com 15 MC34071,2,4,A MC33071,2,4,A + R R MC34074 R VO MC34074 RE + R - R MC34074 + Example: Let: R = RE = 12 k Then: AV = 3.0 BW = 1.5 MHz R AV = 1 +2 R RE Figure 62. High Impedance Differential Amplifier +VO + + MC34074 100 k - 10 + 10 RL +10 MC34074 + 220 pF -10 100 k + + RL +VO -VO 18.93 -18.78 10 k 5.0 k 18 15.4 -18 -15.4 + MC34074 100 k - 10 RL 10 -VO Figure 63. Dual Voltage Doubler http://onsemi.com 16 MC34071,2,4,A MC33071,2,4,A ORDERING INFORMATION Op Amp Function Single Dual Quad Device Operating Temperature Range Package Shipping TA = 0 to +70C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC33071P, MC33071AP MC33071D, MC33071AD MC33071DR2, MC33071ADR2 TA = -40 to +85C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC34072P, MC34072AP MC34072D, MC34072AD MC34072DR2, MC34072ADR2 TA = 0 to +70C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC33072P, MC33072AP MC33072D, MC33072AD MC33072DR2, MC33072ADR2 TA = -40 to +85C DIP-8 SO-8 SO-8 / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel MC34072VD MC34072VDR2 MC34072VP TA = -40 to +125C SO-8 SO-8 / Tape & Reel DIP-8 98 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail TA = 0 to +70C DIP-14 SO-14 SO-14 / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel MC33074P, MC33074AP MC33074D, MC33074AD MC33074DR2, MC33074ADR2 MC33074DTB, MC33074ADTB MC33074DTBR2, MC33074ADTBR2 TA = -40 to +85C DIP-14 SO-14 SO-14 / Tape & Reel TSSOP-14 TSSOP-14 / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel MC34074VD MC34074VDR2 MC34074VP TA = -40 to +125C SO-14 SO-14 / Tape & Reel DIP-14 55 Units / Rail 2500 Units / Tape & Reel 25 Units / Rail MC34071P, MC34071AP MC34071D, MC34071AD MC34071DR2, MC34071ADR2 MC34074P, MC34074AP MC34074D, MC34074AD MC34074DR2, MC34074ADR2 http://onsemi.com 17 MC34071,2,4,A MC33071,2,4,A MARKING DIAGRAMS PDIP-8 P SUFFIX CASE 626 8 8 MC3x071P AWL YYWW 8 MC3x071AP AWL YYWW 1 1 8 MC3x072P AWL YYWW 1 8 MC3x072AP AWL YYWW MC34072VP AWL YYWW 1 1 8 8 SO-8 D SUFFIX CASE 751 8 8 8 3x071 ALYWA 3x071 ALYW 1 1 3x072 ALYWA 3x072 ALYW 3x072 ALYWV 1 1 1 PDIP-14 P SUFFIX CASE 646 14 14 MC3x074P AWLYYWW 1 14 MC3x074AP AWLYYWW 1 MC34074VP AWLYYWW 1 SO-14 D SUFFIX CASE 751A 14 14 1 14 14 MC3x074AD AWLYWW MC3x074D AWLYWW 1 TSSOP-14 DTB SUFFIX CASE 948G MC33 074 ALYW MC34074VD AWLYWW 1 1 x = 3 or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week http://onsemi.com 18 14 MC33 074A ALYW 1 MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS PDIP-8 P SUFFIX CASE 626-05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 -B- 1 4 DIM A B C D F G H J K L M N F -A- NOTE 2 L C J -T- MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10 0.030 0.040 N SEATING PLANE D M K G H 0.13 (0.005) M T A M B M SO-8 D SUFFIX CASE 751-07 ISSUE W -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A 8 5 0.25 (0.010) S B 1 M Y M 4 K -Y- G C N X 45 SEATING PLANE -Z- 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S http://onsemi.com 19 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS PDIP-14 P SUFFIX CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L N C -T- SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --10 0.38 1.01 M SO-14 D SUFFIX CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C -T- SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 20 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC34071,2,4,A MC33071,2,4,A PACKAGE DIMENSIONS TSSOP-14 DTB SUFFIX CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- EE CC CC EE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 21 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC34071,2,4,A MC33071,2,4,A Notes http://onsemi.com 22 MC34071,2,4,A MC33071,2,4,A Notes http://onsemi.com 23 MC34071,2,4,A MC33071,2,4,A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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