FAN3268TMX_F085 - Fairchild Semiconductor

December 2013

FAN3268 • Rev. 1.0.3 1

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

FAN3268

2 A Low-Voltage PMOS-NMOS Bridge Dri ver

Features

 4.5 V to 18 V Operating Range

 Drives High-Side PMOS and Low-Side NMOS in

Motor Control or Buck Step-Down Applications

 Inverting Channel B Biases High-Side PMOS

Device Off (with internal 100 kΩ Resistor) when

VDD is below UVLO Threshold

 TTL Input Thresholds

 2.4 A Sink / 1.6 A Source at VOUT=6 V

 Internal Resistors Turn Driver Off If No Inputs

 MillerDrive™ Technology

 8-Lead SOIC Package

 Rated from –40°C to +125°C Ambient

 Automotive Qualified to AEC-Q100 (F085 Version)

Applications

 Motor Control with PMOS / NMOS Half-Bridge

Configuration

 Buck Converters with High-Side PMOS Device;

100% Duty Cycle Operation Possible

 Logic-Controlled Load Circuits with High-Side

PMOS Switch

 Automotive-Qualified Systems (F085 version)

Description

The FAN3268 dual 2 A gate driver is optimized to drive

a high-side P-channel MOSFET and a low-side N-

channel MOSFET in motor control applications

operating from a voltage rail up to 18 V. The driver has

TTL input thresholds and provides buffer and level

translation functions from logic inputs. Internal circuitry

provides an under-voltage lockout function that

prevents the output switching devices from operating if

the VDD supply voltage is below the operating level.

Internal 100 kΩ resistors bias the non-inverting output

low and the inverting output to VDD to keep the external

MOSFETs off during startup intervals when logic control

signals may not be present.

The FAN3268 driver incorporates MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

The FAN3268 has two independent enable pins that

default to on if not connected. If the enable pin for non-

inverting channel A is pulled low, OUTA is forced low; if

the enable pin for inverting channel B is pulled low,

OUTB is forced high. If an input is left unconnected,

internal resistors bias the inputs such that the external

MOSFETs are off.

Related Resources

AN-6069 — Application Review and Comparative

Evaluation of Low-Side Gate Drivers

MOTOR

BYP

VDDGND

ENB

ENA

+VRAIL (4.5−18V)

Controller

FAN3268

Figure 1. Typical Motor Drive Application

FAN3268 • Rev. 1.0.3 2

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Ordering Information

Part Nu m b er Logic Input Threshold Packing Method

FAN3268TMX Non-Inverting Channel and Inverting

Channel + Dual Enables TTL 2,500 Units on

Tape & Reel

FAN3268TMX_F085(1) Non-Inverting Channel and Inverting

Channel + Dual Enables TTL 2,500 Units on

Tape & Reel

1. Qualif i ed t o AEC-Q100

Package Outline

ENA

INA

GND

INB

ENB

OUTA

VDD

OUTB

Figure 2. Pin Configuration (Top View)

Thermal Characteristics(2)

Package

JL(3)

JT(4)

JA(5)

JB(6)

JT(7) Units

8-Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3 °C/W

Notes:

2. Estim ates derived from thermal s i mulat i on; actual values depend on the application.

3. Theta_J L (ΘJL): T hermal res i stance bet ween the s emic onductor junc tion and the bot t om surface of al l the leads (including any

thermal pad) that are typically sol dered t o a PCB.

4. Theta_J T (ΘJT): T hermal resi stance between the sem i conductor j unction and t he t op surface of the package, assuming it is

held at a unif orm temperature by a top-s i de heatsink .

5. Theta_J A (ΘJA): Thermal resi stance between junction and ambient, dependent on the P CB design, heat s i nking, and airflow.

The value given is f or natural convection with no heats i nk using a 2S 2P board, as specif i ed i n JEDEC standards JESD51-2,

JESD51-5, and JESD51-7, as appropriate.

6. Psi_JB (ΨJB): Thermal charac terization parameter providing correlation bet ween semic onduc tor junct i on temperature and an

applicat i on c i rcuit board ref erenc e poi nt for the t hermal environment def i ned i n Note 5. For the SOIC-8 package, the board

reference is defined as t he PCB copper adj acent to pi n 6.

7. Psi_JT (ΨJT): Therm al c haracterizati on parameter providi ng correlation bet ween the s emic onductor junc tion temperature and

the center of the top of t he package for the therm al envi ronment def i ned i n Not e 5.

FAN3268 • Rev. 1.0.3 3

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Pin Definitions

Pin# Name Description

1 ENA Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds.

8 ENB Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds.

3 GND Ground. Common ground reference for input and output circuits.

2 INA Input to Channel A.

4 INB Input to Channel B.

7 OUTA Gate Drive Output A: Held low unless required input(s) are present and VDD is above the UVLO

threshold.

OUTB

Gate Drive Output B (inverted from the input): Held high unless required input is present and VDD

is above UVLO threshold.

6 VDD Supply Voltage. Provi des power to the IC.

Output Logi c

FAN3268 (Channel A) FAN3268 (Channel B)

ENA INA OUTA ENB INB

OUTB

0 0(8) 0 0 0(8) 1

0 1 0 0 1 1

1(8) 0(8) 0 1(8) 0(8) 1

1(8) 1 1 1(8) 1 0

Note:

8. Default input signal if no external connection is made.

FAN3268 • Rev. 1.0.3 4

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Block Diagram

VDD

VDD_OK

INA

100kΩ

ENA

GND

VDD

UVLO

100kΩ

VDD

ENB

INB

OUTA

100kΩ

OUTB

100kΩ

Figure 3. Block Diagram

FAN3268 • Rev. 1.0.3 5

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Absol ute Maximum Rati ngs

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD VDD to GND -0.3 20.0 V

VEN ENA, ENB to GND GND - 0.3 VDD + 0.3 V

VIN INA, INB to GND GND - 0.3 VDD + 0.3 V

VOUT OUTA, OUTB to GND GND - 0.3 VDD + 0.3 V

TL Lead Soldering Temperature (10 Seconds) +260 ºC

TJ Junction Temperature -55 +150 ºC

TSTG Storage Temperature -65 +150 ºC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

VDD Supply Voltage Range 4.5 18.0 V

VEN Enable Voltage (ENA, ENB) 0 VDD V

VIN Input Voltage (INA, INB) 0 VDD V

TA Operating Ambient Temperature -40 +125 ºC

FAN3268 • Rev. 1.0.3 6

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Electrical Characteristics

Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

SUPPLY

VDD Operating Range 4.5 18.0 V

IDD Supply Current Inputs / EN Not

Connected 0.75 1.20 mA

FAN3268T UVLO

VON Device Turn-On Voltage INA=ENA=VDD, INB=ENB=0 V 3.5 3.9 4.3 V

VOFF Device Turn-Off Voltage INA=ENA=VDD, INB=ENB=0 V 3.3 3.7 4.1 V

FAN3268TMX_F085 UVLO (Automotive-Qualified Versions)

VON Device Turn-On Voltage(12) INA=ENA=VDD, INB=ENB=0 V 3.3 3.9 4.5 V

VOFF Device Turn-Off Voltage(12) INA=ENA=VDD, INB=ENB=0 V 3.1 3.7 4.3 V

INPUT(9)

FAN3268T

VIL INx Logic Low Threshold 0.8 1.2 V

VIH INx Logic High Threshold 1.6 2.0 V

VHYS Logic Hysteresis Voltage 0.2 0.4 0.8 V

FAN3268TMX_F085 (Automotive-Qualified Versions)

VIL INx Logic Low Threshold(12) 0.8 1.2 V

VIH INx Logic High Threshold(12) 1.6 2.0 V

VHYS Logic Hysteresis Voltage(12) 0.1 0.4 0.8 V

Continued on the following page…

FAN3268 • Rev. 1.0.3 7

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Electrical Characteristics (Continued)

Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

ENABLE

VENL Enable Logic Low Threshold EN from 5 V to 0 V 0.8 1.2 V

VENH Enable Logic High Threshold EN from 0 V to 5 V 1.6 2.0 V

VHYS Logic Hysteresis Voltage(10) 0.4 V

RPU Enable Pull-up Resistance(10) 100 kΩ

OUTPUT

ISINK Out Current, Mid-Voltage, Sinking(10) Out at VDD/2,

CLOAD=0.1 µF, f=1 kHz 2.4 A

ISOURCE Out Current, Mid-Voltage,

Sourcing(10) Out at VDD/2,

CLOAD=0.1 µF, f=1 kHz -1.6 A

IPK_SINK Out Current, Peak, Sinking(10) CLOAD=0.1 µF, f=1 kHz 3 A

IPK_SOURCE Out Current, Peak, Sourcing

(10)

CLOAD=0.1 µF, f=1 kHz -3 A

tRISE Output Rise Time(11) CLOAD=1000 pF 12 22 ns

tFALL Output Fall Time(11) CLOAD=1000 pF 9 17 ns

FAN3268T

tD1 Propagation Delay

(11)

0 - 5 VIN, 1 V/ns Slew Rate 7 14 25 ns

tD2 Propagation Delay (11) 0 - 5 VIN, 1 V/ns Slew Rate 10 19 34 ns

FAN3268TMX_F085 (Automotive-Qualified Versions)

tD1 Propagation Delay (11)(12) 0 - 5 VIN, 1 V/ns Slew Rate 7 14 32 ns

tD2 Propagation Delay

(11)(12)

0 - 5 VIN, 1 V/ns Slew Rate 8 19 34 ns

VOH High Level Output Voltage(12) VOH=VDD–VOUT, IOUT=–1 mA 15 40 mV

VOL Low Level Output Voltage(12) IOUT=1 mA 10 25 mV

Notes:

9. EN inputs have TTL thresholds; refer to the ENABLE section.

10. Not tested in production.

11. See the Timing Diagrams of Figure 4 and Figure 5.

12. Apply only to Automotive Version(FAN3268TMX_F085)

Timing Diagrams

90%

10%

Output

Input

Enable

RISE

FALL

INL

INH

90%

10%

Output

FALL

RISE

INL

INH

Input

Enable

Figure 4. Non-Inverting

Figure 5. Inverting

FAN3268 • Rev. 1.0.3 8

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 6. IDD (Static) vs. Supply Voltage(13) Figure 7. IDD (No-Load) vs. Frequency

Figure 8. IDD (1 nF Load) vs. Frequency Figure 9. IDD (Static) vs. Temperature(13)

Figure 10. Input Thresholds vs. Supply Voltage Figure 11. Input Thresholds vs. Temperature

FAN3268 • Rev. 1.0.3 9

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 12. UVLO Threshold vs. Temperature Figure 13. Propagation Delays vs. Supply Voltage

Figure 14. Propagation Delays vs. Supply Voltage Figure 15. Propagation Delays vs. Temperature

Figure 16. Propagation Delays vs. Temperature

FAN3268 • Rev. 1.0.3 10

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 17. Fall Time vs. Supply Voltage Figure 18. Rise Time vs. Supply Voltage

Figure 19. Rise and Fall Times vs. Temperature

Figure 20. Rise/Fall Waveforms with 1 nF Load Figure 21. Rise/Fall Waveforms with 10 nF Load

FAN3268 • Rev. 1.0.3 11

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Typical Performance Characteristics

Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted.

Figure 22. Quasi-Static Source Current with VDD=12 V Figure 23. Quasi-Sta ti c Sink Current with VDD=12 V

Figure 24. Quasi-Static Source Current with VDD=8 V Figure 25. Quasi-Static Sink Current w i th V DD=8 V

Note:

13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by

the current flowing through the corresponding pull-up/down resistor shown in the block diagram in Figure 3.

Test Circuit

120µF

Al. El.

VDD

OUT

1µF

ceramic

4.7µF

ceramic

CLOAD

0.1µF

OUT

1kHz

Current Probe

LECROY AP015

Figure 26. Quasi-Static IOUT / VOUT Test Circuit

FAN3268 • Rev. 1.0.3 12

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Applications Information

Input Thresholds

The FAN3268 driver has TTL input thresholds and

provides buffer and level translation functions from logic

inputs. The input thresholds meet industry-standard

TTL-logic thresholds, independent of the VDD voltage,

and there is a hysteresis voltage of approximately 0.4 V.

These levels permit the inputs to be driven from a range

of input logic signal levels for which a voltage over 2 V

is considered logic high. The driving signal for the TTL

inputs should have fast rising and falling edges with a

slew rate of 6 V/µs or faster, so a rise time from 0 to

3.3 V should be 550 ns or less. W ith reduced slew rate,

circuit noise could cause the driver input voltage to

exceed the hysteresis voltage and retrigger the driver

input, causing erratic operation.

Static Supply Current

In the IDD (static) typical performance characteristics

(see Figure 6), the curve is produced with all inputs /

enables floating (OUT is low) and indicates the lowest

static IDD current for the tested configuration. For other

states, additional current flows through the 100 kΩ

resistors on the inputs and outputs shown in the block

diagram (see Figure 3). In these cases , the actual static

IDD current is the value obtained from the curves plus

this additional current.

Mill er Drive™ Gate Drive Technology

FAN3268 gate drivers incorporate the MillerDrive™

architecture shown in Figure 1. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT s wings between one and two

thirds VDD and the MOS devices pull the output to the

high or low rail.

The purpose of the MillerDrive™ architecture is to

speed up switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

For applications with zero voltage switching during the

MOSFET turn-on or turn-off interval, the driver supplies

high peak current for fast switching even though the

Miller plateau is not present. This situation often occurs

in synchronous rectifier applications because the body

diode is generally conducting before the MOSFET is

switched on.

The output pin slew rate is determined by VDD voltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slower rise or fall

time at the MOSFET gate is needed.

Input

stage

VDD

VOUT

Figure 27. MillerDrive™ Output Architecture

Under-Voltage Lockout

Internal circuitry provides an under-voltage lockout

function that prevents the output switching devices from

operating if the VDD supply voltage is below the

operating level. W hen VDD is rising, but below the 3.9 V

operational level, internal 100 kΩ resistors bias the non-

inverting output low and the inverting output to VDD to

keep the external MOSFETs off during startup intervals

when logic control signals may not be present. After the

part is active, the supply voltage must drop 0.2 V before

the part shuts down. This hysteresis helps prevent

chatter when low VDD supply voltages have noise from

the power switching.

VDD Bypass Capaci t or G uidelines

To enable this IC to turn a device on quickly, a local high-

frequency bypass capacitor CBYP with low ESR and ESL

should be connected between the VDD and GND pins

with minimal trace length. This capacitor is in addition to

bulk electrolytic capacitance of 10 µF to 47 µF commonly

found on driver and controller bias circuits.

A typical criterion for choosing the value of CBYP is to

keep the ripple voltage on the VDD supply to ≤5%. This

is often achieved with a value ≥20 times the equivalent

load capacitance CEQV, defined here as QGATE/VDD.

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics, such as X5R and

X7R, with good temperature characteristics and high

pulse current capability.

If circuit noise affects normal operation, the value of

CBYP may be increased to 50-100 times the CEQV or

CBYP may be split into two capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10 nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

switching simultaneously, the combined peak current

sourced from the CBYP would be twice as large as when

a single channel is switching.

FAN3268 • Rev. 1.0.3 13

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Layout and Connection Guideli nes

The FAN3268 gate driver incorporates fast-reacting

input circuits, short propagation delays, and powerful

output stages capable of delivering current peaks over

2 A to facilitate voltage transition times from under 10ns

to over 150 ns. The following layout and connection

guidelines are strongly recommended:

 Keep high-current output and power ground paths

separate from logic and enable input signals and

signal ground paths. This is especially critical when

dealing with TTL-level logic thresholds at driver

inputs and enable pins.

 Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

 If the inputs to a channel are not externally

connected, the internal 100 kΩ resistors indicated

on block diagrams command a low output (channel

A) or a high output (channel B). In noisy

environments, it may be necessary to tie inputs or

enables of an unused channel to VDD or GND

using short traces to prevent noise from causing

spurious output switching.

 Many high-s peed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input, enable, or output leads. For

best results, make connections to all pins as short

and direct as possible.

 The turn-on and turn-off current paths should be

minimized.

Operati onal W aveform s

Figure 28 shows startup waveforms for non-inverting

channel A. At power-up, the driver output for channel A

remains low until the VDD voltage reaches the UVLO turn-

on threshold, then OUT A operates in-phase with INA.

VDD

INA

OUTA

UVLO

Turn-on threshold

Figure 28. Non-Inverting Startup Waveforms

Figure 29 illustrates startup waveforms for inverting

channel B. At power-up, the driver output for channel B

is tied to VDD through an internal 100 kΩ resistor until

the VDD voltage reaches the UVLO turn-on threshold,

then OUTB operates out of phase with INB.

VDD

INB

OUTB

UVLO

Turn-on threshold

Figure 29. Inverting Startup Waveforms

FAN3268 • Rev. 1.0.3 14

FAN3268 —2 A Low-Volta g e PMOS -NMOS Bridge Dr iver

Thermal Guidel i nes

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure that the part is operating within

acceptable temperature limits.

The total power dissipation in a gate driver is the sum of

two components, PGATE and PDYNAMIC:

PTOTAL=PGATE + PDYNAMIC (1)

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that

results from driving a MOSFET at a specified gate-

source voltage, VGS, with gate charge, QG, at

switching frequency, fSW, is determined by:

PGATE=QG • VGS • fSW • n (2)

where n is the number of driver channels in use

(1 or 2).

Dynamic Pre-drive / Shoot-through Current: A

power loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-down resistors, can be

obtained using the “IDD (No-Load) vs. Frequency”

graphs in Typical Performance Characteristics to

determine the current IDYNAMIC drawn from VDD

under actual operating conditions:

PDYNAMIC=IDYNAMIC • VDD • n (3)

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

assuming ψJB was determined for a similar thermal

design (heat sinking and air flow):

TJ =PTOTAL • ψJB + TB (4)

where:

TJ =driver junction temperature

ψJB =(psi) thermal characterization parameter relating

temperature rise to total pow er dissipation

TB =board temperature in location defined in

Note 2 under Thermal Resistance table.

As an example of a power dissipation calculation,

consider an application driving two MOSFETs with a

gate charge of 60 nC with VGS=VDD=7 V. At a switching

frequency of 500 kHz, the total power dissipation is:

PGATE=60nC • 7V • 500kHz • 2=0.42W (5)

PDYNAMIC=3m A • 7V • 2=0.042W (6)

PTOTAL=0.46W (7)

The SOIC-8 has a junction-to-board thermal

characterization parameter of ψJB=43°C/W . In a sys tem

application, the localized temperature around the device

is a function of the layout and construction of the PCB

along with airflow across the surfaces. To ensure

reliable operation, the maximum junction temperature of

the device must be prevented from exceeding the

maximum rating of 150°C; with 80% derating, TJ would

be limited to 120°C. Rearranging Equation 4 determines

the board temperature required to maintain the junction

temperature below 120°C:

TB=TJ - PTOTAL • ψJB (8)

TB=120°C – 0.46W • 43°C/W=100°C (9)

FAN3268 • Rev. 1.0.3 15

FAN3268 —2 A Low-Voltage PMOS-NMOS Br idge Driver

Table 1. Related Products

Part

Number Type Gate

Drive(14)

(Sink/Src)

Input

Threshold Logic Package

FAN3111C Singl e 1 A +1.1 A / -0.9 A CMOS Single Channel of Dual -Input/Single-Output SOT23-5, MLP6

FAN3111E Si ngl e 1 A +1.1 A / -0.9 A External(15) Single Non-I nvert i ng Channel with E xternal Ref erenc e SOT23-5, MLP6

FAN3100C Singl e 2 A +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6

FAN3100T Si ngl e 2 A +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP 6

FAN3226C Dual 2 A +2.4 A / -1.6 A CMOS Dual Invert i ng Channels + Dual Enable SOIC8, MLP8

FAN3226T Dual 2 A +2.4 A / -1.6 A TTL Dual Invert i ng Channels + Dual Enable SOIC8, MLP8

FAN3227C Dual 2 A +2.4 A / -1.6 A CMOS Dual Non-Inverti ng Channel s + Dual Enable S O I C8, MLP 8

FAN3227T Dual 2 A +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOI C8, MLP8

FAN3228C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of T wo-Input/One-Output, Pin Config.1 SOIC8, MLP8

FAN3228T Dual 2 A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pi n Config.1 SOIC8, MLP8

FAN3229C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of T wo-Input/One-Output, Pin Config.2 SOIC8, MLP8

FAN3229T Dual 2 A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pi n Config.2 SOIC8, MLP8

FAN3268T Dual 2 A +2.4 A / -1.6 A TTL Non-Inverting Channel (NMOS) and Inverting Channel

(PMO S ) + Du al Enables SOIC8

FAN3223C Dual 4 A +4.3 A / -2.8 A CMOS Dual Invert i ng Channels + Dual Enable SOIC8, MLP8

FAN3223T Dual 4 A +4.3 A / -2.8 A TTL Dual Invert i ng Channels + Dual Enable SOIC8, MLP8

FAN3224C Dual 4 A +4.3 A / -2.8 A CMOS Dual Non-Inverti ng Channel s + Dual Enable S O I C8, MLP 8

FAN3224T Dual 4 A +4.3 A / -2.8 A TTL Dual Non-Inverti ng Channel s + Dual Enable S O I C8, MLP8

FAN3225C Dual 4 A +4.3 A / -2.8 A CMOS Dual Channels of T wo-Input/One-Output S O I C8, MLP 8

FAN3225T Dual 4 A +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8

FAN3121C Singl e 9 A +9.7 A / -7.1 A CMOS Single Inverting Channel + E nabl e SOIC8, MLP8

FAN3121T Singl e 9 A +9.7 A / -7.1 A TTL Single I nvert i ng Channel + Enable SOI C8, MLP8

FAN3122T Si ngl e 9 A +9.7 A / -7.1 A CMOS Singl e Non-Invert i ng Channel + Enable SOI C8, MLP8

FAN3122C Singl e 9 A +9.7 A / -7.1 A TTL Single Non-Invert i ng Channel + Enable SOI C8, MLP8

Notes:

14. Typical currents with OUT at 6 V and VDD=12 V.

15. Thresholds proportional to an externally supplied reference voltage.

FAN3268 • Rev. 1.0.3 16

FAN3268 —2 A Low-Voltage PMOS-NMOS Br idge Driver

Physical Dimensions

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08Arev15

F) FAIRCHILD SEMICONDUCTOR.

LAND PATTERN RECOMMENDATION

SEATING PLANE

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR 4

5.60

0.65

1.75

1.27

6.00±0.20 3.90±0.10

4.90±0.10

1.27

0.42±0.09

0.175±0.75

1.75 MAX

0.36

(0.86)

R0.10

0.65±0.25 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

0.25 C B A

0.10

0.22±0.30

(0.635)

Figure 30. 8-Lead Small Outline Integrated Circuit (SOIC)

Package draw ings are provided as a serv ic e to c ustomers consi dering Fairchild components. Drawings may c hange in any manner

without notice. P lease note the revis ion and/or date on the drawing and c ontact a Fairchild Semiconduct or representativ e to v erify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specificall y the warranty therei n, which covers F ai rc hi l d products.

Always vi sit Fai rchild Semic onductor’s online packaging area for the mos t recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN3268 • Rev. 1.0.3 17

FAN3268 —2 A Low-Voltage PMOS-NMOS Br idge Driver

Mouser Electronics

Authorized Distributor

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FAN3268TMX_F085