DM74LS112AMX - Fairchild Semiconductor

August 1986

Revised March 2000

DM74LS112A Dual Negative-Edge-Tri ggered Master-Slave J-K Flip-Flop wit h Preset, Clear, and Complementary

Outputs

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

with Preset, Clear, and Complementary Outputs

General Descript ion

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not dire ctly related to the transiti on time of t he

falling edge of the clock pulse. Data on the J and K inputs

may be changed while the clo ck is HIGH or LOW without

affecting the outputs as long as the setup and hold times

are not violated. A low logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic

levels of the other inputs.

Ordering Code:

Devices also available in Ta pe and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering c ode.

Connection Diagram Function Table

H = HIGH Lo gic Level

L = LOW Lo gic Level

X = Either LOW or HIGH Logic Level

↓ = Negative Going Edge of Pulse

Q0 = The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each falling edge of the cloc k pulse.

Note 1: This configuration is nonstable; that is, it will not persist when

preset and/or cl ear inputs ret urn to their inactive (H I GH) level.

Order Number Package Number Package Description

DM74KS1 12AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS112AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK J K Q Q

LHXXX H L

HLXXX L H

L L X X X H (Note 1) H (Note 1)

HH↓LL Q

0Q0

HH↓HL H L

HH↓LH L H

HH↓HH Toggle

HHHXX Q

0Q0

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DM74LS112A

Absolute Maximum Ratings(No te 2) Note 2: T he “Absol ute Maximum Ratings” are th ose values be yond which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: The symbol (↓) indicates t he f alling edg e of t he clock puls e is used f or referenc e.

Note 5: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Supply Voltage 7V

Input Voltag e 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 3) 0 30 MHz

fCLK Clock Frequency (Note 5) 0 25 MHz

tWPulse Width Clock HIGH 20

(Note 3) Preset LOW 25 ns

Clear LOW 25

tWPulse Width Clock HIGH 25

(Note 5) Preset LOW 30 ns

Clear LOW 30

tSU Setup Time (Note 3)(Note 4) 20↓ns

tSU Setup Time (Note 4)(Note 5) 25↓ns

tHHold Time (Note 3)(Note 4) 0↓ns

tHHold Time (Note 4)(Note 5) 5↓ns

TAFree Air Operating Temperature 0 70 °C

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DM74LS112A

Electri cal Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 6: All typicals are at VCC = 5V, TA = 25°C.

Note 7: N ot more tha n one output should be shorted at a time, and the durat ion shou ld not ex ce ed one secon d. For dev ic es , with fe edback from the outputs,

where shortin g th e outp uts to ground may ca use the outputs to ch ange l o gic state an equi vale nt te st may be perfor med wh ere VO = 2.125V with th e mi nimum

and maxim um limit s reduced by one half fro m t heir stated v alues. This is v ery us eful when using automatic test equipm ent.

Note 8: With all outputs OPEN, ICC is measure d w it h t he Q and Q ou t put s H I GH in turn. At th e t im e of measureme nt th e c lock is grounded.

Switching Characteristics

at VCC = 5V and TA = 25°C

Symbol Parameter Conditions Min Typ Max Units

(Note 6)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, I OL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max VCC = Max, VI = 7V J, K 0.1

Input V oltag e Clear 0.3 mA

Preset 0.3

Clock 0.4

IIH HIGH Level Input Current VCC = Max, VI = 2.7V J, K 20

Clear 60 µA

Preset 60

Clock 80

IIL LOW Level Input Current VCC = Max, VI = 0.4V J, K −0.4

Clear −0.8 mA

Preset −0.8

Clock −0.8

IOS Short Circuit Output Current VCC = Max (Note 7) −20 −100 mA

ICC Supply Current VCC = Max (Note 8) 4 6 mA

From (Input) RL = 2 kΩ

Symbol Parameter To (Out put) CL = 15 pF CL = 50 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 30 25 MHz

tPLH Propagation Delay Time Preset to Q 20 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Preset to Q 20 28 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Clear to Q 20 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Clear to Q 20 28 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Clock to Q or Q 20 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Clock to Q or Q 20 28 ns

HIGH-to-LOW Level Output

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DM74LS112A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

5 www.fairchildsemi.com

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary

Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described , no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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