0S2013 DALLAS SEMICONDUCTOR CORP DALLAS SEMICONDUCTOR SOE D MM 2614130 COO4L1L8 & MMDAL T= V6PS- DS2013 8192 x 9 FIFO Chip FEATURES First-in, first-out memory-based architecture @ Flexible 8192 x 9 organization Low-power HCMOS technology Asychronous and simultaneous read/write Bidirectional applications Fully expandable by word width or depth - Empty and full warning flags Half-full flag capability in single-device mode Retransmit capability Available in 50 ns, 65 ns, 80 ns, and 120 ns access times @ Industrial temperature range -40C to +85C avail- able designated N, in 50 ns, 65 ns, 80 ns, and 120 ns access times DESCRIPTION The DS2013 8192 x 9 FIFO Chip implements a first-in, first-out algorithm, featuring asynchronous read/write operations, full, empty, and half-full flags, and unlimited expansion capability in both word size and depth. The DS2013 is functionally and electrically equivalent to the PIN ASSIGNMENT Wow. 28 [J voc ose 271 D4 D3CI3 26 DS Dela 25D) D6 ois 24{9 D7 . DOO 23 0 FUAT xiO7 22 RS Frag 212 EF act}, 201 KOMF adie 1917 Q7 oy 18 a6 , Oye 17795 Os +9 1M Q4 ono 14 15 R 28-Pin DIP (300. and 600 Mit} See Mech. Drawings Sect. 16, Pgs. 1 & 4 PIN DESCRIPTION Ww - WRITE R - READ Rs - RESET FL/RT _ - First Load/Retransmit D, -Datain Q, = - Data Out xi - Expansion In XO/HF - Expansion Out/Half Full FF - Full Flag EF - Empty Flag Voc - Volts GND ~~ - Ground NC - No Connect DS2009 512 x 9 FIFO with the exceptions listed in the notes for DC Electrical Characteristics of the DS2009 data sheet. Refer to DS2009 512 x 9 FIFO Chip data sheet for detailed device description. 011392 1/1 3-36