2001-2013 Microchip Technology Inc. DS21669D-page 1
MCP6041/2/3/4
Features
Low Quiescent Current: 600 nA/amplifier (typical)
Rail-to-Rail Input/Output
Gain Bandwidth Product: 14 kHz (typical)
Wide Supply Voltage Range: 1.4V to 6.0V
Unity Gain Stable
Available in Single, Dual, and Quad
Chip Select (CS) with MCP6043
Available in 5-lead and 6-lead SOT-23 Packages
Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Applications
Toll Booth Tags
Wearable Products
Temperature Measurement
Battery Powered
Design Aids
SPICE Ma cr o Models
•FilterLab
® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Related Devices
MCP6141/2/3/4: G = +10 Stable Op Amps
Typical Application
Description
The MCP6041/2/3/4 family of operational amplifiers
(op am ps ) from Mic rochi p Techn ology Inc. ope rate wi th
a single supply voltage as low as 1.4V, while drawing
less than 1 µA (maximum) of quiescent current per
amplifier. These devices are also designed to support
rail-t o-rail in put and output o peratio n. T his co mbina tion
of features supports battery-powered and portable
applications.
The MCP6041/2/3/4 amplifiers have a gain-bandwidth
product of 14 kHz (typical) and are unity gain stable.
These specifications make these op amps appropriate
for low frequency applications, such as battery current
monitoring and sensor conditioning.
The MCP6041/2/3/4 family operational amplifiers are
offered in single (MCP6041), single with Chip Select
(CS) (MCP6043), dual (MCP6042), and quad
(MCP6044) configurations. The MCP6041 device is
available in the 5-lead SOT-23 package, and the
MCP6043 device is available in the 6-lead SOT-23
package.
Package Types
VDD
IDD
MCP604X
100 k
1M
1.4V VOUT
High Side Battery Current Sensor
10
to
6.0V
IDD VDD VOUT
10 V/V10

------------------------------------------=
VIN+
VIN
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NC
NC
MCP6041
PDIP, SOIC, MSOP
MCP6042
PDIP, SOIC, MSOP
MCP6043
PDIP, SOIC, MSOP
MCP6044
PDIP, SOIC, TSSOP
VINA+
VINA
VSS
VOUTB
VINB
1
2
3
4
8
7
6
5VINB+
VDD
VOUTA
VIN+
VIN
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
VINA+
VINA
VDD
VIND
VIND+
1
2
3
4
14
13
12
11 VSS
VOUTD
VOUTA
VINB
VINB+
VOUTB
VINC+
VINC
5
6
7
10
9
8VOUTC
VIN+
VSS VIN
1
2
3
5
4
VDD
VOUT
MCP6041
SOT-23-5
VIN+
VSS VIN
1
2
3
6
4
VDD
VOUT
MCP6043
SOT-23-6
5CS
600 nA, Rail-to-Rail Input/Ou tput Op Amp s
MCP6041/2/3/4
DS21669D-page 2 2001-2013 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins........................... .... ......... .... .... .. ...±2 mA
Analog Inputs (VIN+, VIN–)............. VSS 1.0V to VDD +1.0V
All Other Inputs and Outputs.......... VSS 0.3V to VDD +0.3V
Difference Input voltage ...................................... |VDD –V
SS|
Output Short Circuit Current ..................................continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................... .... .. .. .....–65°C to +150°C
Junction Temperature..................................................+150°C
ESD protection on all pins (HBM; MM)  4 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1 “Rail-to-Rail Input”
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA= 25°C, VCM =V
DD/2,
VOUT VDD/2, VL=V
DD/2, and RL = 1 Mto VL (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3 +3 mV VCM = VSS
Drift with Temperature VOS/TA—±2—µV/°CV
CM = VSS, TA= -40°C to +85°C
VOS/TA—±15—µV/°CV
CM = VSS,
TA= +85°C to +125°C
Power Supply Rejection PSRR 70 85 dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB—1—pA
Industrial Temperature IB 20 100 pA TA = +85°
Extended Temperature IB 1200 5000 pA TA = +125°
Input Offset Current IOS —1—pA
Common Mode Input Impedance ZCM —10
13||6 ||pF
Differential Input Impedance ZDIFF —10
13||6 ||pF
Common Mode
Common-Mode Input Range VCMR VSS0.3 VDD+0.3 V
Common-Mode Rejection Ratio CMRR 62 80 dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 60 75 dB VDD = 5V, VCM = 2.5V to 5.3V
CMRR 60 80 dB VDD = 5V, VCM = -0.3V to 2.5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 95 115 dB RL = 50 k to VL,
VOUT = 0.1V to VDD0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS +10 V
DD 10 mV RL = 50 k to VL,
0.5V input overdrive
Linear Region Output Voltage Swing VOVR VSS + 100 VDD 100 mV RL = 50 k to VL,
AOL 95 dB
Output Short Circuit Current ISC —2—mAV
DD = 1.4V
ISC —20—mAV
DD = 5.5V
Power Supply
Supply Voltage VDD 1.4 6.0 V (Note 1)
Quiescent Current per Amplifier IQ0.3 0.6 1.0 µA IO = 0
Note 1: All parts with date codes November 2007 and later have been screened to ensur e operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 1.4V and/or 5.5V.
2001-2013 Microchip Technology Inc. DS21669D-page 3
MCP6041/2/3/4
AC ELECTRICAL CHARACTERISTICS
MCP6043 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
FIGURE 1-1: Chip Select (CS) Timing
Diagram (MCP6 043 only).
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA= 25°C, VCM =V
DD/2,
VOUT VDD/2, VL=V
DD/2, RL = 1 Mto VL, and CL= 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP 14 kHz
Slew Rate SR 3.0 V/ms
Phase Margin PM 65 ° G = +1 V/V
Noise
Input Voltage Noise Eni —5.0—µV
P-P f = 0.1 Hz to 10 Hz
Input Voltage Noise Density eni 170 nV/Hz f = 1 kHz
Input Current Noise Density ini —0.6—fA/Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA= 25°C, VCM =V
DD/2,
VOUT VDD/2, VL=V
DD/2, RL = 1 Mto VL, and CL= 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —V
SS+0.3 V
CS Input Current, Low ICSL —5—pACS = VSS
CS High Specifications
CS Logic Threshold, High VIH VDD–0.3 VDD V
CS Input Current, High ICSH —5pACS = VDD
CS Inpu t H igh, GN D Cu rrent ISS —-20—pACS = VDD
Amplifier Output Leakage, CS High IOLEAK —20—pACS = VDD
Dynamic Specifications
CS Low to Amplifier Output Turn- on Time tON 2 50 ms G = +1V/V, CS = 0.3V to
VOUT = 0.9VDD/2
CS High to Amplifier Output High-Z tOFF 10 µs G = +1V/V, CS = VDD–0.3V to
VOUT = 0.1VDD/2
Hysteresis VHYST —0.6— VV
DD = 5.0V
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-20 pA
High-Z
ISS
ICS 5pA
-20 pA
-0.6 µA
(typical) (typical)
(typical)
(typical)
MCP6041/2/3/4
DS21669D-page 4 2001-2013 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
cap acitors are laid out ac cording to the rules d iscusse d
in Section 4.6 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA- 40 +85 °C Industrial Tem perat ure parts
TA-40 +125 °C Extended Temperature parts
Operating Temperat ure Range TA-40 +125 °C (Note 1)
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 JA 256 °C/W
Thermal Resistance, 6L-SOT-23 JA 230 °C/W
Thermal Resistance, 8L-PDIP JA —85—°C/W
Thermal Resistance, 8L-SOIC JA 163 °C/W
Thermal Resistance, 8L-MSOP JA 206 °C/W
Thermal Resistance, 14L-PDIP JA —70—°C/W
Thermal Resistance, 14L-SOIC JA 120 °C/W
Thermal Resistance, 14L-TSSOP JA 100 °C/W
Note 1: The MCP6041/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification
of +150°C.
VDD
MCP604X
RGRF
RNVOUT
VIN
VDD/2
F
CLRL
VL
0.1 µF
VDD
MCP604X
RGRF
RNVOUT
VDD/2
VIN
F
CLRL
VL
0.1 µF
2001-2013 Microchip Technology Inc. DS21669D-page 5
MCP6041/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift
with TA= -40°C to +85°C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD =1.4V.
FIGURE 2-4: Input Offset Voltage Drift
with TA= +85°C to +125°C and VDD =1.4V.
FIGURE 2-5: Input Offset Voltage Drift
with TA= +25°C to +125°C and VDD =5.5V.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD =5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational p urposes only. The performance characteristics li sted herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
-3 -2 -1 0 1 2 3
Input Offset Voltage (mV)
Percentage of Occurrences
1124 Samples
VDD = 1.4V and 5.5V
VCM = VSS
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-10-8-6-4-20246810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1124 Samples
TA = -40°C to +85°C
VDD = 1.4V
VCM = VSS
-2000
-1500
-1000
-500
0
500
1000
1500
2000
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 1.4V
Representative Part
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-32 -28 -24 -20 -16 -12 -8 -4 0 4
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
245 Samples
1 Representative Lot
TA = +85°C to +125°C
VDD = 1.4V
VCM = VSS
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-32 -28 -24 -20 -16 -12 -8 -4 0 4
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
239 Samples
1 Representative Lot
TA = +85°C to +125°C
VDD = 5.5V
VCM = VSS
-2000
-1500
-1000
-500
0
500
1000
1500
2000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
Representative Part
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6041/2/3/4
DS21669D-page 6 2001-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-9: CMRR, PSRR vs.
Frequency.
FIGURE 2-10: The MCP6041/2/3 /4 fami ly
shows no phase reversal.
FIGURE 2-11: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-12: CMRR, PSRR vs. Ambient
Temperature.
250
300
350
400
450
500
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
VDD = 1.4V
100
1000
0.1 1 10 100 1000
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
20
30
40
50
60
70
80
90
0.1 1 10 100 1000
Frequency (Hz)
CMRR, PSRR (dB)
PSRR
PSRR+
CMRR
Referred to Input
-1
0
1
2
3
4
5
6
0 5 10 15 20 25Time (5 ms/div)
Input, Output Voltages (V)
VIN
VDD = 5.0V
G = +2 V/V
VOUT
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/Hz)
f = 1 kHz
VDD = 5.0V
70
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
(VCM = VSS)
CMRR
(VDD = 5.0V, VCM = -0.3V to +5.3V)
2001-2013 Microchip Technology Inc. DS21669D-page 7
MCP6041/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-13: Input Bias, Offset Currents
vs. Ambient Temperature.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-16: Input Bias, Offset Currents
vs. Common Mode Input Voltage.
FIGURE 2-17: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-18: DC Open-Loop Gain vs.
Output Voltage Headroom.
0.1
1
10
100
1000
10000
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias and Offset Currents
(pA)
| IOS |
IB
VDD = 5.5V
VCM = VDD
0.1
1
10
100
1k
10k
-20
0
20
40
60
80
100
120
1.E-
03
1.E-
02
1.E-
01
1.E+
00
1.E+
01
1.E+
02
1.E+
03
1.E+
04
1.E+
05Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
0.001 0.01 0.1 1 10 100 1k 10k 100k
Gain
Phase
80
90
100
110
120
130
140
1.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
DC Open-Loop Gain (dB)
RL = 50 k
VDD = 5.0V
VOUT = 0.1V to VDD - 0.1V
0.1
1
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias and Offset Currents
(pA)
VDD = 5.5V
| IOS |
IB
0.1
1
10
100
1k
10k
TA = +125°C
TA = +85°C
60
70
80
90
100
110
120
130
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (:)
DC Open-Loop Gain (dB)
VDD = 1.4V
100 1k 10k 100k
VOUT = 0.1V to VDD – 0.1V
VDD = 5.5V
80
90
100
110
120
130
140
0.00 0.05 0.10 0.15 0.20 0.25
Output Voltage Headroom;
VDD  VOH or VOL  VSS (V)
DC Open-Loop Gain (dB)
RL = 50 k
VDD = 5.5V
VDD = 1.4V
MCP6041/2/3/4
DS21669D-page 8 2001-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-19: Channel-to-Channel
Separation vs. Frequency (MCP6042 and
MCP6044 only).
FIGURE 2-20: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD =1.4V.
FIGURE 2-21: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-22: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD =5.5V.
FIGURE 2-24: Output Short Circuit Current
vs. Power Supply Voltage.
60
70
80
90
100
110
120
130
1.E+02 1.E+03 1.E+04
Frequency (Hz)
Channel to Channel
Separation (dB)
100 1k 10k
Input Referred
0
2
4
6
8
10
12
14
16
18
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
PM
(G = +1)
GBWP
VDD = 1.4V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
(µA/Amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
2
4
6
8
10
12
14
16
18
20
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
100
Phase Margin (°)
PM
(G = +1)
GBWP
VDD = 5.0V
RL = 100 k
0
2
4
6
8
10
12
14
16
18
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
PM
(G = +1)
GBWP
VDD = 5.5V
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA
= -40°C
TA
= +25°C
TA
= +85°C
TA
= +125°C
2001-2013 Microchip Technology Inc. DS21669D-page 9
MCP6041/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-25: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-26: Slew Rate vs. Ambient
Temperature.
FIGURE 2-27: Small Signal Non-inverting
Pulse Response.
FIGURE 2-28: Output Volt age Headroom
vs. Ambient Temperature.
FIGURE 2-29: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-30: Small Signal Inverting Pulse
Response.
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom;
VDD – VOH or VOL – VSS (mV)
VDD – V
OH
VOL – VSS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/ms)
High-to-Low
Low-to-High
VDD = 1.4V
VDD = 5.5V
-25
-20
-15
-10
-5
0
5
10
15
20
25
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (100 µs/div)
Output Voltage (5mV/div)
G = +1 V/V
RL = 50 k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom,
VDD – VOH or VOL – VSS (mV)
VOL – VSS
VDD – VOH
VDD = 5.5V
RL = 50 k
0.1
1
10
1.E+01 1.E+02 1.E+03 1.E+04
Frequency (Hz)
Maximum Output Voltage
Swing (V P-P)
101001k10k
VDD = 5.5V
VDD = 1.4V
-25
-20
-15
-10
-5
0
5
10
15
20
25
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (100 µs/div)
Voltage (5 mV/div)
G = -1 V/V
RL = 50 k
MCP6041/2/3/4
DS21669D-page 10 2001-2013 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.4V to +6.0V, VSS = GND, VCM =V
DD/2, VOUT VDD/2,
VL=V
DD/2, RL=1M to VL, and CL=60pF.
FIGURE 2-31: Large Signal Non-inverting
Pulse Response.
FIGURE 2-32: Chip Select (CS) to
Amplifier Output Response Time (MCP60 43
only).
FIGURE 2-33: Input Current vs. Input
Voltage (below VSS).
FIGURE 2-34: Large Signal Inverting Pulse
Response.
FIGURE 2-35: Chip Select (CS) Hysteresis
(MCP6043 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
012345678910Time (1 ms/div)
Output Voltage (V)
VDD = 5.0V
G = +1 V/V
RL = 50 k
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0.0
2.5
5.0
7.5
012345678910Time (1 ms/div)
CS Voltage (V)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Output Voltage (V)
VDD = 5.0V
VOUT
High-Z High-Z
Output On
CS
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
100n
10n
1n
100p
10p
1p
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
012345678910Time (1 ms/div)
Output Voltage (V)
VDD = 5.0V
G = -1 V/V
RL = 50 k
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Input Voltage (V)
Internal CS Switch Output (V)
VOUT Active
VOUT High-Z
VDD = 5.0V
Hysteresis
CS
High-to-Low
CS
Low-to-High
2001-2013 Microchip Technology Inc. DS21669D-page 11
MCP6041/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-imped-
ance CMOS inputs with low bias currents.
3.3 Chip Select Digital Input
This i s a CMO S, Schmitt-tri ggered i nput that places the
part into a low power mode of operation.
3.4 Power Supply Pins
The positive power supply pin (VDD) is 1.4V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6041 MCP6042 MCP6043 MCP6044
Symbol Description
PDIP,
SOIC,
MSOP SOT-23-5 PDIP,
SOIC,
MSOP
PDIP,
SOIC,
MSOP SOT-23-6 PDIP,
SOIC,
TSSOP
61 161 1V
OUT,V
OUTA Analog Out put (op amp A)
24 224 2V
IN–, VINA Inver ting Input (op amp A)
33 333 3V
IN+, VINA+ Non-inverting Input (op amp A)
75 876 4V
DD Positive Power Supply
—— 5 5 V
INB+ Non-inverting Input (op amp B)
—— 6 6 V
INB Inver ting Input (op amp B)
—— 7 7V
OUTB Analog Output (op amp B)
—— 8V
OUTC Analog Output (op am p C)
—— 9V
INC Inverting Input (op amp C)
—— 10V
INC+ Non-inverting Input (op amp C)
42 442 11V
SS Negative Power Supply
—— 12V
IND+ Non-inverting Input (op amp D)
—— 13V
IND Inverting Input (op amp D)
—— 14V
OUTD Analog Output (op am p D)
—— 8 5 CS
Chip Select
1, 5, 8 1, 5 NC No Internal Connection
MCP6041/2/3/4
DS21669D-page 12 2001-2013 Microchip Technology Inc.
4.0 APPLICATIONS INFORMATION
The MCP6041/2/3/4 famil y of op amp s is manufactured
using Microchip’s state of the art CMOS process.
These op amps are unity gain stable and suitable for a
wide range of general purpose, low-power applica-
tions.
See Microchip’s related MCP6141/2/3/4 family of op
amps for applications, at a gain of 10 V/V or higher,
needing greater bandwidth.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERSAL
The MCP6041/2/3/4 op amps are designed to not
exhibi t phase inve rsio n when t he i nput pi ns excee d th e
supply voltages. Figure 2-10 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input tr ansis tors , and to min im ize i npu t bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resi stors R 1 and R 2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) fro m going too far ab ove VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is a lso pos sible to c onnect th e diodes to the left o f the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 n eed t o be limit ed by som e oth er
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-33. Applicat ions that are hi gh impedanc e may
need to limit the useable voltage range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6041/2/3/4 op amps uses
two di fferent ial in put sta ges in p arallel . One ope rates at
a low common mode input voltage (VCM), while the
other operates at a high VCM. With this topology, the
device operates with a VCM up to 300 mV above VDD
and 300 mV below VSS. The input offset voltage is
measured at VCM =V
SS –0.3V and V
DD + 0.3V to
ensure proper operation.
There are two transitions in input behavior as VCM is
changed. The first occurs, when VCM is near
VSS + 0.4V, and the second occurs when VCM is near
VDD –0.5V (see Figure 2-3 and Figure 2-6). For the
best distortion performance with non-inverting gains,
avoid these regions of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN
V1
MCP604X
R1
VDD
D1
R1>VSS (minimum expected V1)
2mA
VOUT
R2>VSS (minimum expected V2)
2mA
V2R2
D2
R3
2001-2013 Microchip Technology Inc. DS21669D-page 13
MCP6041/2/3/4
4.2 Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP6041/2/3/4 family of op
amps. The first specification (Maximum Output V oltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load condition. Thus,
the outpu t volta ge swings to w ithin 10 mV of either sup-
ply rail with a 50 k load to VDD/2. Figure 2-10 sh ows
how the output voltage is limited when the input goes
beyond the linear region of operation.
The second specification that describes the output
swing cap ability of these am plifiers is the Lin ear Output
Voltage Range. This specification defines the maxi-
mum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large signal DC
Open-Loop Gain (AOL) is meas ured at points inside the
supply rails. The measurement mu st meet the specified
AOL condition in the specif ication table.
4.3 Output Loads and Battery Life
The MCP6041/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current
glitching when Chip Select (CS) is raised or lowered.
This prevents excessive current draw, and reduced
battery life, when the part is turned off or on.
Heavy resistive loads at the output can cause
excessive battery drain. Driving a DC voltage of 2.5V
across a 100 k load resis tor will cause the s upply cur-
rent to increase by 25 µA, depleting the battery 43
times as fast as IQ (0.6 µA, typical) alone.
High frequency signals (fast edge rate) across
capacitive loads will also significantly increase supply
current. For instance, a 0.1 µF capacitor at the output
presents an AC impedance of 15.9 k (1/2fC) to a
100 Hz sinewave. It can be shown that the average
power drawn from the battery by a 5.0 Vp-p sinewave
(1.77 Vrms), under these conditions, is
EQUATION 4-1:
This will drain the battery 18 times as fast as IQ alone.
4.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, although all gains show
the same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive loa d.
FIGURE 4-3: Output Resistor, RISO
Stabilize s Lar ge Capacitiv e Load s.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit ’s noise g ain. For non-in verting gains , GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN=+2V/V).
FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6041/2/3/4 SPICE macro
model are helpful.
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )
= (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF)
= 3.0 µ W + 50 µW
VIN
MCP604X
RISO VOUT
CL
1,000
10,000
100,000
1.E+01 1.E+02 1.E+03 1.E+04
Normalized Load Capacitance; CL/GN (F)
Recommended RISO (:)
10p
1k
100k
100p
GN = +1
GN = +2
GNt +5
10k
10n1n
MCP6041/2/3/4
DS21669D-page 14 2001-2013 Microchip Technology Inc.
4.5 MCP6043 Chip Select
The MCP6043 is a single op amp with Chip Select
(CS). When CS is pulled high, the suppl y curre nt drop s
to 50 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier
may not operate properly. Figure 1-1 shows the ou tpu t
voltage and supply current response to a CS pulse .
4.6 Supply Bypass
With this family of operational amplifiers, the power
suppl y pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good hi gh frequ ency p erfor mance . It can u se a bul k
cap acitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with nearby
analog p arts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP6044)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
referenc e volt age within the outp ut volt age r ange of th e
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-5: Un used Op Amps.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces i s 1012. A 5V dif ference would
cause 5 pA of current to flow, which is greater than the
MCP6041/2/3/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensi tiv e p ins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-6 shows an example of this type of layout.
FIGURE 4-6: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the gua rd ring to the inverting input
pin ( VIN–). This bias es th e g uard rin g to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+) . Thi s bi as es t he gua rd r ing
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inv erting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
VDD
¼ MCP6044 (A) ¼ MCP6044 (B)
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
------------------=
Guard Ring VIN–V
IN+
2001-2013 Microchip Technology Inc. DS21669D-page 15
MCP6041/2/3/4
4.9 Application Circuits
4.9.1 BATTERY CURRENT SENSING
The MCP6041/2/3/4 op amps’ Common Mode Input
Range, which goes 0.3V beyond both supply rails,
supports their use in high-side and low-side battery
current sensing applications. The very low quiescent
current (0.6 µA, typical) helps prolong battery life, and
the rail-to-rail output supports detection low currents.
Figure 4-7 shows a high-side battery current sensor
circuit. The 10 resistor is sized to minimize power
losses. The battery current (IDD) through the 10
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the Common
mode input voltage of the op amp below VDD, which is
within its allowed range. The output of the op amp will
also b e bel ow VDD, which is within it s Maxim um Output
Voltage Sw ing spec ifi cat ion .
.
FIGURE 4-7: High-Side Bat ter y Cur rent
Sensor.
4.9.2 INSTRUMENTATION AMPL IFIER
The MCP6041/2/3/4 op amp is well suited for
conditioning sensor signals in battery-powered
applications. Figure 4-8 shows a two op amp instru-
mentation amplifier, using the MCP6042, that works
well for applications requiring rejection of Common
mode noise at higher gains. The reference voltage
(VREF) is suppli ed by a low impedance sourc e. In single
supply applications, VREF is typically VDD/2.
.
FIGURE 4-8: Two Op Amp
Instrumentation Amplifier.
VDD
IDD
MCP604X
100 k
1M
1.4V VOUT
10
to
6.0V
IDD VDD VOUT
10 V/V10

------------------------------------------=
VOUT V1V2
1R1
R2
------2R1
RG
---------++


VREF
+=
VREF R1R2R2R1VOUT
RG
V2
V1
½
MCP6042
½
MCP6042
MCP6041/2/3/4
DS21669D-page 16 2001-2013 Microchip Technology Inc.
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6041/2/3/4 family of op amps.
5.1 SPICE Macro Model
The lates t SPICE m acr o mod el fo r the MCP6041/2/3/4
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any desi gn and
cannot be replaced with simulations. Also, simulation
results using th is ma cro m od el need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Micro chi p web s ite at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filte r to sort fea tures for a p aram etric searc h of
devices and export side-by-side technical comparison
reports. Helpful links are a lso provided for d at a she et s ,
purchase, and sampling of Microchip parts.
5.4 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
design ed to help you ach ieve fast er time to m arket. For
a complete listing of these boards and their
corresp onding u ser’s gui des and t echni cal i nfo rmatio n,
visit the Microchip web site at www.microchip.com/
analogtools.
Some boards that are especially useful are:
P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5.5 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip.com/
appnotes and are recommended as supplemental ref-
erence resources:
ADN003: “Select the Right Operational Amplifier for
your Filteri ng Circu it s ”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
2001-2013 Microchip Technology Inc. DS21669D-page 17
MCP6041/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead MSOP Example:
XXXXXX
YWWNNN
6043I
304256
5-Lead SOT-23 (MCP6041)Example:
XXNN 7X25
Device I-Temp
Code
E-Temp
Code
MCP6041/T-E/OT SPNN 7XNN
Note: Parts with date codes prior to
November 2012 have their package
markings in the SBNN format.
6-Lead SOT-23 (MCP6043) Example:
XXNN SC25
Legend: XX...X Customer-s pec ifi c info rma tio n
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the even t the full Mic rochip part nu mb er cann ot be marked o n one lin e, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
Device I-Temp
Code
E-Temp
Code
MCP6043T-E/CH SCNN SDNN
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6041
I/P256
1304
MCP6042
I/SN1304
256
MCP6041
I/P 256
1304
MCP6042I
SN 1304
256
3
e
OR
OR
3
e
MCP6041/2/3/4
DS21669D-page 18 2001-2013 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6044)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6044-I/P
1304256
MCP6044
1304256
E/P
3
e
OR
14-Lead TSSOP (MCP6044)Example:
14-Lead SOIC (150 mil) (MCP6044)Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
6044ST
1304
256
XXXXXXXXXX MCP6044ISL
1304256
MCP6044
1304256
E/SL^^
OR
3
e
6044EST
1304
256
OR
I/SL^^
3
e
2001-2013 Microchip Technology Inc. DS21669D-page 19
MCP6041/2/3/4
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
 
 
 
 

 
   

 
  
  
   
   
  
  
  
  
   
  
  
  
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
   
MCP6041/2/3/4
DS21669D-page 20 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 21
MCP6041/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6041/2/3/4
DS21669D-page 22 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 23
MCP6041/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6041/2/3/4
DS21669D-page 24 2001-2013 Microchip Technology Inc.
 !"##$% !

 
 
 
 

 

 
   

 
 
    
  
   
    
   
   
   
    
   
  
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
   
2001-2013 Microchip Technology Inc. DS21669D-page 25
MCP6041/2/3/4
&' !"##$% !

 
 
 
 

 

 
   
 
 
 
    
  
   
    
   
   
   
    
   
  
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1 b1
be
   
MCP6041/2/3/4
DS21669D-page 26 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 27
MCP6041/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6041/2/3/4
DS21669D-page 28 2001-2013 Microchip Technology Inc.
(")*+,#$%!-
 

2001-2013 Microchip Technology Inc. DS21669D-page 29
MCP6041/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6041/2/3/4
DS21669D-page 30 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 31
MCP6041/2/3/4
 

MCP6041/2/3/4
DS21669D-page 32 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 33
MCP6041/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6041/2/3/4
DS21669D-page 34 2001-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS21669D-page 35
MCP6041/2/3/4
APPENDIX A: REVISION HISTORY
Revision D (March 2013)
The following is the list of modifications:
1. Updated the boards list in Section 5.4 “Analog
Demonstration and Evaluation Boards”.
2. Removed the Mindi™ Circuit Designer &
Simulator section.
3. Updated the E-Temp Code value for the 5-Lead
SOT-23 package in Section 6.0 “Packaging
Information”.
Revision C (February 2008)
The following is the list of modifications:
1. Updated Figure 2-4 and Figure 2-5.
2. Updated trademark and Sales listing pages.
3. Expanded this op amp family:
4. Added the SOT-23-6 packa ge for the MCP604 3
op amp with Chip Select .
5. Added Extended Temperature (-40°C to
+125 °C) par ts.
6. Expanded Analog Input Absolute Max Voltage
Range (applies retroactively).
7. Expanded o peratin g VDD to a maximum of 6.0V.
8. Section 1.0 “Electrical Characteristics”
updated.
9. Section 2.0 “Typical Performance Curves”
updated.
10. Section 3.0 “Pin Descriptions” added.
11. Section 4.0 “Applications Information” added.
12. Added Section 4.7 “Unused Op Amps”.
13. Updated input stage explanation.
14. Section 5.0 “Design Aids” updated.
15. Section 6.0 “Packaging Information” updated.
16. Added SOT-23-6 pa ckage.
17. Corrected package marking information.
18. Appendix A: “Revision History” add ed.
Revision B (June 2002)
The following is the list of modifications.
Undoc um ent ed cha nges.
Revision A (August 2001)
Original data sheet release.
MCP6041/2/3/4
DS21669D-page 36 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS21669D-page 37
MCP6041/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP6041 : Single Op Amp
MCP6041T Single Op Amp
(Tape and Reel for SOT-23, SOIC, MSOP)
MCP6042 Dual Op Amp
MCP6042T Dual Op Amp
(Tape an d Reel f or SOI C and MS OP)
MCP6043 Single Op Amp w/ Chip Select
MCP6043T Single Op Amp w/ Chip Select
(Tape and Reel for SOT-23, SOIC, MSOP)
MCP6044 Quad Op Amp
MCP6044T Quad Op Amp
(Tape an d Reel f or SOI C and TSSOP)
Temperature Range: I = -40°C to +8 C
E = -40°C to +125°C
Package: CH = Plastic Small Outline Transistor (SOT-23),
6-lead (Tape and Reel - MCP6043 only)
MS = Plastic Micro Small Outline (MSOP), 8-lead
OT = Plastic Small Outline Transistor (SOT-23),
5-lead (Tape and Reel - MCP6041 only)
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
ST = P last ic TSSOP (4.4 mm Body), 14-lead
Examples:
a) MCP6041-I/P: Industrial Temperature,
8LD PDIP package.
b) MCP6041T-E/OT: Tape and Reel,
Extended Temperatu r e,
5LD SOT-23 package.
a) MCP6042-I/SN: Industrial Temperature,
8LD SOIC package.
b) MCP6042T-E/MS: Tape and Reel,
Extended Temperatu r e,
8LD MSOP package.
a) MCP6043-I/P: Industrial Temperature,
8LD PDIP package.
b) MCP6043T-E/CH: Tape and Reel,
Extended Temperatu r e,
6LD SOT-23 package.
a) MCP6044-I/SL: Industrial Temperature,
14LD SOIC package.
b) MCP6044T-E/ST: Tape and Reel,
Extended Temperatu r e,
14LD TSSOP package.
MCP6041/2/3/4
DS21669D-page 38 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS21669D-page 39
Information contained in this publication regarding device
applications a nd t he lik e is provid ed only f or your con ve nience
and may be su perseded by updates. I t is your r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperF lash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Stor age Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE , In-Circuit Seria l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Tec hnolo gy Germ any II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-042-9
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCU s and dsPIC® DSCs, KEELOQ® code hoppin g
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS21669D-page 40 2001-2013 Microchip Technology Inc.
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11/29/12