S3C9654/C9658/P9658 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C9654/C9658/P9658 MICROCONTROLLER The S3C9654/C9658/P9658 microcontroller with USB function can be used in a wide range of general purpose applications. It is especially suitable for mouse or joystick controller and is available in 16, 18, 20-pin DIP and SOP package. The S3C9654/C9658/P9658 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9654/C9658/P9658 has 4/8 Kbytes of program memory on-chip (S3C9654/C9658), and 208 bytes of RAM including 16 bytes of working register. Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- Three configurable I/O ports (14 pin, at 20 pin) -- 14-bit programmable pins for external interrupts (at 20 pin) -- 8-bit timer/counter with two operating modes OTP The S3C9654/C9658 microcontroller is also available in OTP (One Time Programmable) version. S3P9658 microcontroller has an on-chip 4/8 Kbyte one-time-programmable EPROM instead of masked ROM. The S3P9658 is comparable to S3C9654/C9658, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9654/C9658/P9658 FEATURES CPU Timer/Counter * * One 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function * One 8-bit timer/counter with Compare/Overflow counter SAM88RCRI CPU core Memory * 4-K byte internal program memory (ROM S3C9654) * 8-K byte internal program memory (ROM S3P9658/C9658) * 208-byte RAM * 16 bytes of working register USB Serial Bus * Compatible to USB low speed (1.5 Mbps) device 1.0 specification. * Serial bus interface engine (SIE) -- Packet decoding/generation Instruction Set * 41 instructions -- CRC generation and checking * IDLE and STOP instructions added for powerdown modes -- NRZI encoding/decoding and bit-stuffing Instruction Execution Time * 0.66 s at 6 MHz fOSC * Two 8-byte receive/transmit USB buffer Operating Temperature Range * - 0C to + 85C Interrupts Operating Voltage Range * 14 interrupt sources with one vector (20 pin) * * 12 interrupt sources with one vector (18 pin) * 10 interrupt sources with one vector (16 pin) * One level, one vector interrupt structure 4.0 V to 5.25 V Package Types * 16, 18, 20 pin DIP * 16, 18, 20 pin SOP Oscillation Circuit Options * 6 MHz crystal/ceramic oscillator * External clock source * RC oscillator * Embedded oscillation capacitor (XI, XO, 33pF) General I/O * 14 bit-programmable I/O pins (20 pin) * 12 bit-programmable I/O pins (18 pin) * 10 bit-programmable I/O pins (16 pin) Sub Oscillator * Internal RC sub oscillator * Auto interrupt wake-up 1-2 Comparator * 6-channel mode, 32 step resolution * 5-channel mode, external reference * Low EMI design Low Voltage Reset * Low voltage Reset * Power on Reset High Sink Current Pin for LED * P0.0 (VOL: 0.4 V, 50mA) S3C9654/C9658/P9658 PRODUCT OVERVIEW BLOCK DIAGRAM TEST RESET Port I/O and Interrupt Control XIN OSC Port 1/ Compa -rator P1.0/CIN0/INT1 P1.1/CIN0/INT1 P1.2/CIN0/INT1 P1.3/CIN0/INT1 P1.4/CIN0/INT1 P1.5/CIN0/INT1 Port 0 P0.0/INT0 P0.1/INT0 P0.2/INT0 (note) P0.3/INT0 (note) P0.4/INT0 (note) P0.5/INT0 (note) XOUT SUB OSC SAM88RCRI CPU Basic Timer Timer 0 LVR 8K (4K) ROM NOTE: 208 Byte RAM USB SIE P2.1/D+/INT2 P2.0/D-/INT2 16, 18, 20 DIP and SOP. Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9654/C9658/P9658 PIN ASSIGNMENTS P0.2/INT0 1 20 P0.3/INT0 VSS 2 19 VDD P0.0/INT0 3 18 P2.0/D-/INT2 P1.0/COM0/INT1 4 17 P2.1/D+/INT2 P1.1/COM1/INT1 5 16 RESET P1.2/COM2/INT1 6 15 XIN P1.3/COM3/INT1 7 14 XOUT P1.4/COM4/INT1 8 13 TEST P1.5/COM5/INT1 9 12 P0.1/INT0 10 11 P0.5/INT0 P0.4/INT0 S3C9654/ S3C9658 Figure 1-2. Pin Assignment (20 Pin) 1-4 S3C9654/C9658/P9658 PRODUCT OVERVIEW P0.2/INT0 1 18 P0.3/INT0 VSS 2 17 VDD P0.0/INT0 3 16 P2.0/D-/INT2 P1.0/COM0/INT1 4 15 P2.1/D+/INT2 P1.1/COM1/INT1 5 14 RESET P1.2/COM2/INT1 6 13 XIN P1.3/COM3/INT1 7 12 XOUT P1.4/COM4/INT1 8 11 TEST P1.5/COM5/INT1 9 10 P0.1/INT0 S3C9654/ S3C9658 Figure 1-3. Pin Assignment (18 Pin) VSS 1 16 VDD P0.0/INT0 2 15 P2.0/D-/INT2 P1.0/COM0/INT1 3 14 P2.1/D+/INT2 P1.1/COM1/INT1 4 13 RESET P1.2/COM2/INT1 5 12 XIN P1.3/COM3/INT1 6 11 XOUT P1.4/COM4/INT1 7 10 TEST P1.5/COM5/INT1 8 9 S3C9654/ S3C9658 P0.1/INT0 Figure 1-4. Pin Assignment (16 Pin) 1-5 PRODUCT OVERVIEW S3C9654/C9658/P9658 Table 1-1. Signal Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 I/O Bit-programmable I/O port for Schmitt trigger input or n-ch open drain output (50 mA). Pull-up resistor is assignable to input pin by software and is automatically disabled for output pin. Port 0 can be individually configured as external interrupt input. SK 3 INT0 P0.1-P0.5 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors individually assignable to input pins by software and are automatically disabled for output pins. Port 0 can be individually configured as external interrupt inputs. D 1, 10, 11, 12, 20 INT0 P1.0-P1.5 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are individually assignable to input pins by software. Port 1 can be configured as comparator input or external interrupt inputs. Pull-down resistors are individually assignable. (in comparator input) CP 4-9 CIN0-5 INT1 P2.0/D- P2.1/D+ I/O Bit-programmable I/O port for Schmitt trigger input or n-ch open drain output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Port 2 can be individually configured as external interrupt inputs. Also it can be configured as an USB ports. CP 17, 18 INT2 XOUT, XIN - System clock input and output pin (crystal/ceramic oscillator, or external clock source) - 14, 15 - INT0 I External interrupt for bit-programmable port 0 D 1, 3, 10, 11, 12, 20 Port 0 INT1 I External interrupt for bit-programmable port 1 D 4-9 Port 1 INT2 I External interrupt for bit-programmable port 2 D 17, 18 Port 2 VDD - Power input pin - 19 - VSS - VSS is a ground power for CPU core. - 2 - RESET 1 Reset input pin (Pull-up register embedded) - 16 - 1-6 S3C9654/C9658/P9658 PRODUCT OVERVIEW Table 1-2. Pin Circuit Assignments for the S3C9654/C9658/P9658 Circuit Number Circuit Type S3C9654/C9658/P9658 Assignments C O D I/O Port 0.1-5, INT0, INT1, INT2 SK I/O Port 0.0 CP I/O Port 1, Port 2 NOTE: Diagrams of circuit types C-D, and F-8 are presented below. VDD V DD Data P-Channel Out Output DIsable N-Channel Pull-up Enable Data Output DIsable Circuit Type C I/O Data Figure 1-5. Pin Circuit Type C Figure 1-6. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C9654/C9658/P9658 VDD Pull-up Registor Pull-up Enable Output Disable I/O Output Data VSS Input Data MUX D0 D1 Mode Input Data Output D0 Input D1 Figure 1-7. Pin Circuit Type SK VDD Pull-up Enable Data Output DIsable Circuit Type C Data Input Enable Analog/ External VREF Input D+/D- Figure 1-8. Pin Circuit Type CP 1-8 I/O S3C9654/C9658/P9658 PRODUCT OVERVIEW S3C9654/ S3C9658/S3P9658 Button SW1 XI 15 14 19 XI P0.1/INT0 12 Button XOUT VDD P0.2/INT0 To Host 2 17 18 D+ SW3 VSS VDD Button + C_BULK VSS VDD D- 1 DM1 VSS P0.3/INT0 P2.1/D+/INT2 VSS SW2 VSS T_X R_XY 20 P2.0/D-/INT2 P1.0/COM0/INT1 13 P1.1/COM1/INT1 TEST 16 RESET (note) D_X 4 5 VDD VSS T_Y P1.2/COM2/INT1 P1.3/COM3/INT1 10 11 7 VDD P0.4/INT0 P0.5/INT0 VDD T_Z P1.4/COM4/INT1 P1.5/COM5/INT1 P0.0/INT0 NOTE: D_Y 6 R_Z D_Z 8 9 3 RESET Pin is connected to internal Pull-up register after power on reset. If RESET Pin is low, S3C9654/C9658/P9658 goes to reset. Figure 1-9. USB Mouse Circuit Diagram 1-9 S3C9654/C9658/P9658 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C9654/C9658/P9658 microcontroller has two kinds of address space: -- Program memory (ROM) -- Internal register file A 13-bit address bus supports both program memory. Special instructions and related internal logic determine when the 13-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9654/C9658 has 4/8 Kbytes of mask-programmable program memory on-chip. The S3C9654/C9658/P9658 microcontroller has 192 bytes general-purpose registers in its internal register file. Fortyeight bytes in the register file are mapped for system and peripheral control functions. 2-1 ADDRESS SPACES S3C9654/C9658/P9658 PROGRAM MEMORY (ROM) NORMAL OPERATING MODE (INTERNAL ROM) The S3C9654/C9658/P9658 has 4/8 Kbytes of internal mask-programmable program memory. The first 2 bytes of the ROM (0000H-0001H) are an interrupt vector address. The program reset address in the ROM is 0100H. 1000H 4.096 4 K byte Internal Program Memory Area 256 Program Start 2 1 Interrupt Vector 0 S3C9654 2000H 8.192 8 K byte Internal Program Memory Area 0100H 256 0002H 2 0001H 1 0000H 0 Program Start 0100H 0002H Interrupt Vector 0001H 0000H S3C9658/P9658 Figure 2-1. S3C9654/C9658/P9658 Program Memory Address Space 2-2 S3C9654/C9658/P9658 ADDRESS SPACES REGISTER ARCHITECTURE The upper 64 bytes of the S3C9654/C9658/P9658's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192 bytes of internal register file (00H-BFH) is called the general purpose register space. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H-BFH). This register file expansion is not implemented in the S3C9654/C9658/P9658. FFH Peripheral Control Registers 64 Bytes of Common Area E0H DFH System Control Registers D0H CFH Working Registers C0H BFH General Purpose Register File and Stack Area 192 Bytes ~ 00H Figure 2-2. Internal Register File Organization 2-3 ADDRESS SPACES S3C9654/C9658/P9658 COMMON WORKING REGISTER AREA (C0H-CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. However, because the S3C9654/C9658/P9658 uses only page 0, you can use the common area for any internal data operation. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. MSB LSB Rn Rn + 1 n = Even address Figure 2-3. 16-Bit Register Pairs + PROGRAMMING TIP -- Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: LD 2. ADD R2,40H ; R2 (C2H) the value in location 40H 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: ADD R3,#45H 2-4 ; R3 (C3H) R3 + 45H S3C9654/C9658/P9658 ADDRESS SPACES SYSTEM STACK KS86-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9654/C9658/P9658 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4. High Address PCL PCL Top of stack PCH PCH Top of stack Stack contents after a call instruction Low Address Flags Stack contents after an interrupt Figure 2-4. Stack Operations STACK POINTER (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the KS86C6104/P6104, the SP must be initialized to an 8-bit value in the range 00H-BFH. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area. 2-5 ADDRESS SPACES S3C9654/C9658/P9658 + PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0C0H ; SP C0H (Normally, the SP is set to 0C0H by the ; initialization routine) SYM CCON 20H R3 ; ; ; ; Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH R3 20H CCON SYM ; ; ; ; R3 Stack address 0BCH 20H Stack address 0BDH CCON Stack address 0BEH SYM Stack address 0BFH * * * PUSH PUSH PUSH PUSH * * * POP POP POP POP 2-6 SYM CCON 20H R3 S3C9654/C9658/P9658 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM) 3-1 ADDRESSING MODES S3C9654/C9658/P9658 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2). Program Memory 8-bit Register File Address dst OPCODE One-Operand Instruction (Example) Register File OPERAND Point to One Rigister in Register File Value used in Instruction Execution Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address Figure 3-1. Register Addressing Register File CFH . . . . Program Memory 4-Bit Working Register dst src OPCODE Two-Operand Instruction (Example) 4 LSBs OPERAND Point to the Woking Register (1 of 16) Sample Instruction: ADD R1, R2 ; Where R1 = C1H and R2 = C2H Figure 3-2. Working Register Addressing 3-2 C0H S3C9654/C9658/P9658 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Program Memory 8-Bit Register File Address dst OPCODE One-Operand Instruction (Example) Register File Point to One Rigister in Register File ADDRESS Address of Operand used by Instruction Value used in Instruction Execution OPERAND Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-Bit register address Figure 3-3. Indirect Register Addressing to Register File 3-3 ADDRESSING MODES S3C9654/C9658/P9658 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE REGISTER PAIR Points to Rigister Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4. Indirect Register Addressing to Program Memory 3-4 16-Bit Address Points to Program Memory S3C9654/C9658/P9658 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File CFH Program Memory 4-Bit Working Register Address dst OPCODE Sample Instruction: OR src R6, @R2 4 LSBs . . . . OPERAND Point to the Woking Register (1 of 16) Value used in Instruction C0H OPERAND Figure 3-5. Indirect Working Register Addressing to Register File 3-5 ADDRESSING MODES S3C9654/C9658/P9658 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File CFH . . . . Program Memory 4-Bit Working Register Address Example Instruction References either Program Memory or Data Memory dst src OPCODE Next 3 Bits Point to Working Register Pair (1 of 8) LSB Selects Value used in Instruction Register Pair C0H Program Memory or Data Memory 16-Bit address points to program memory or data memory OPERAND Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 S3C9654/C9658/P9658 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of -128 to +127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. Register File ~ Value used in Instruction + Program Memory Two-Operand Instruction Example Base Address dst src OPCODE 4 LSBs Point to One of the Woking Register (1 of 16) ~ OPERAND ~ ~ INDEX Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Figure 3-7. Indexed Addressing to Register File 3-7 ADDRESSING MODES S3C9654/C9658/P9658 INDEXED ADDRESSING MODE (Continued) Program Memory 4-Bit Working Register Address Register File XS (OFFSET) dst src OPCODE NEXT 3 Bits Point to Working Register Pair (1 of 8) Register Pair 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Datamemory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #04H[RR2] LDE R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 S3C9654/C9658/P9658 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory 4-Bit Working Register Address XL H (OFFSET) XL L (OFFSET) dst src OPCODE Register File NEXT 3 Bits Register Pair Point to Working Register Pair (1 of 8) 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Datamemory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #1000H[RR2] LDE R4, #1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset 3-9 ADDRESSING MODES S3C9654/C9658/P9658 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Program or Data Memory Program Memory Memory Address Used Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Sample Instructions: LDC R5,1234H ; LDE R5,1234H ; The values in the program address (1234H) are loaded into register R5. Identical operation to LDC example, except that external program memory is accessed. Figure 3-10. Direct Addressing for Load Instructions 3-10 S3C9654/C9658/P9658 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11. Direct Addressing for Call and Jump Instructions 3-11 ADDRESSING MODES S3C9654/C9658/P9658 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR. Program Memory Next OPCODE Program Memory Address Used Current PC Value Displacement OPCODE Current Instruction + Signed Displacement Value Sample Instructions: JR ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128 Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-13. Immediate Addressing 3-12 S3C9654/C9658/P9658 4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9654/C9658/P9658 control registers are presented in an easy-toread format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual. 4-1 CONTROL REGISTERS S3C9654/C9658/P9658 Table 4-1. System and Peripheral Control Registers Register Name Mnemonic Hex R/W General purpose register file & Stack area - 00-BFH R/W Working register area - C0H-CFH R/W T0CNT D0H R Timer 0 data register T0DATA D1H R/W Timer 0 Control register T0CON D2H R/W Timer 0 Counter register Location D3H is not mapped. Clock control register CLKCON D4H R/W System FLAG register FLAGS D5H R/W D9H R/W Locations D6H-D8H are not mapped. Stack pointer SP Locations DAH-DBH are not mapped. Basic timer control register BTCON DCH R/W Basic timer counter BTCNT DDH R SYM DFH R/W Port 0 data register P0 E0H R/W Port 1 data register P1 E1H R/W Port 2 data register P2 E2H R/W PDCON E3H R/W Comparator control mode register CCON E4H R/W Comparison result register CDATA E5H R Port 0 low nibble control register P0CONL E6H R/W Port 0 high nibble control register P0CONH E7H R/W Port 1 high nibble control register P1CONH E8H R/W Port 1 low nibble control register P1CONL E9H R/W Port 0 interrupt control register P0INT EAH R/W Port 0 interrupt pending register P0PND EBH R/W Port 1 interrupt control register P1INT ECH R/W Port 1 interrupt pending register P1PND EDH R/W P2CONINT EEH R/W SUBCON EFH R/W Location DEH is not mapped. System mode register Port 1 pull-down control Port 2 control/interrupt control and pending register Sub oscillator control register 4-2 S3C9654/C9658/P9658 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Hex R/W USB function address register FADDR F0H R/W Control endpoint status register EP0CSR F1H R/W Interrupt endpoint status register EP1CSR F2H R/W Control endpoint byte count register EP0BCNT F3H R Control endpoint FIFO register EP0FIFO F4H W Interrupt endpoint FIFO register EP1FIFO F5H W USB interrupt pending register USBPND F6H R/W USB interrupt enable register USBINT F7H R/W PWRMGR F8H R/W FBH R/W SNKCON FDH R/W USB signal control XCON FEH R/W USB reset register USBRST FFH R/W USB power management register Locations F9H is not mapped Locations FAH is not mapped USB mode select register USBSEL Locations FCH is not mapped Sink current control register NOTES: 1. RESET = value notation 2. "_" = Not used. 3. "x" = Undetermind value. 4-3 CONTROL REGISTERS S3C9654/C9658/P9658 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic Register address (hexadecimal) D5H FLAGS - System Flags Register Bit Identifier RESET Value Read/Write .7 .7 .6 .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W x R/W 0 R/W 0 R/W Carry Flag (C) .6 0 Operation dose not generate a carry or borrow condition 1 Operation generates carry-out or borrow into high-order bit7 Zero Flag .5 0 Operation result is a non-zero value 1 Operation result is zero Sign Flag 0 Operation generates positive number (MSB = "0") 1 Operation generates negative number (MSB = "1") R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Addressing mode or modes you can use to modify register values Description of the effect of specific bit settings RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one Figure 4-1. Register Description Format 4-4 Bit number: MSB = Bit 7 LSB = Bit 0 S3C9654/C9658/P9658 CONTROL REGISTERS BTCON -- Basic Timer Control Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 - .4 Watchdog Timer Enable Bits 1 0 1 0 Any other value .3 - .2 .1 .0 Disable watchdog function Enable watchdog function Basic Timer Input Clock Selection Bits 0 0 f OSC/4096 0 1 f OSC/1024 1 0 f OSC/128 1 1 Non divided (f OSC) Basic Timer Counter Clear Bit (note) 0 No effect 1 Clear BTCNT Basic Timer Divider Clear Bit (note) 0 No effect 1 Clear both dividers NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit is then cleared automatically to "0". 4-5 CONTROL REGISTERS S3C9654/C9658/P9658 CCON -- Comparator Mode Register E4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 - .0 Comparator Enable Bit 0 Disable comparator 1 Enable comparator Conversion Time 0 Conversion time (6 x 192/fx) 1 Conversion time (4 x 12/fx) External Reference Voltage 0 Internal reference voltage 1 External reference voltage Reference voltage (Vref) selection VDD x (n + 0.5)/24, n = 0 to 7 VDD x (0.3125 + (n - 7)/48), n = 8 to 23 VDD x (0.6458 + (n - 23)/24), n = 24 to 31 4-6 S3C9654/C9658/P9658 CONTROL REGISTERS CLKCON -- System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 - - 0 0 - - - R/W - - R/W R/W - - - Read/Write .7 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main system oscillator wake-up in power down mode 1 Disable IRQ for main system oscillator wake-up in power down mode .6 and .5 Not used for S3C9654/C9658/P9658 .4 and .3 CPU Clock (System Clock) Selection Bits .2 - .0 0 0 Divide by 16 (fOSC/16) 0 1 Divide by 8 (fOSC/8) 1 0 Divide by 2 (fOSC/2) 1 1 Non-divided clock (fOSC) Not used for S3C9654/C9658/P9658 4-7 CONTROL REGISTERS S3C9654/C9658/P9658 EP0CSR -- Control Endpoint Status Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 .2 .1 .0 4-8 SETUP_END Clear Bit 0 No effect (when write) 1 Clear SETUP_END (bit4) bit OUT_PKT_RDY Clear Bit 0 No effect (when write) 1 Clear OUT_PKT_RDY (bit0) bit STALL Signal Sending Bit 0 No effect (when write) 1 Send STALL signal to host Setup Transfer End Bit 0 No effect (when write) 1 SIE sets this bit when a control transfer ends before DATA_END (bit3) is set Setup Data End Bit 0 No effect (when write) 1 MCU set this bit after loading or unloading the last packet data into the FIFO STALL Signal Receive Bit 0 MCU clear this bit to end the STALL condition 1 SIE sets this bit if a control transaction is ended due to a protocol violation In Packet Ready Bit 0 SIE clear this bit once the packet has been successfully sent to the host 1 MCU sets this bit after writing a packet of data into Endpoint0 FIFO Out Packet Ready Bit 0 No effect (when write) 1 SIE sets this bit once a valid token is written to the FIFO S3C9654/C9658/P9658 CONTROL REGISTERS EP1CSR -- Interrupt Endpoint Status Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 - .3 .2 .1 .0 DATA_TOGGLE Clear Bit 0 No effect (when write) 1 Clears the data toggle sequence bit Maximum Packet Size Bits 0 No effect (when write) 1 Indicates the maximum packet size for interrupt endpoint FIFO Flush Bit 0 No effect (when write) 1 FIFO is flushed, and IN_PKT_RDY cleared Force STALL Bit 0 MCU clears this bit to end the STALL condition 1 Issues a STALL handshake to USB In Packet Ready Bit 0 SIE clear this bit once the packet has been successfully sent to the host 1 MCU sets this bit after writing a packet of data into Endpoint1 FIFO 4-9 CONTROL REGISTERS S3C9654/C9658/P9658 FLAGS -- System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 - - - - R/W R/W R/W R/W - - - - Read/Write .7 Carry Flag (C) 0 .6 .5 .4 .3 - .0 4-10 Operation does not generate a carry or borrow condition Zero Flag (Z) 0 Operation result is a non-zero value 1 Operation result is zero Sign Flag (S) 0 Operation generates a positive number (MSB = "0") 1 Operation generates a negative number (MSB = "1") Overflow Flag (V) 0 Operation result is +127 or -128 1 Operation result is +127 or -128 Not used for S3C9654/C9658/P9658 S3C9654/C9658/P9658 CONTROL REGISTERS P0CONH -- Port 0 Control Register (High Byte) (E7H, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7 - .4 Not used for S3C9654/C9658/P9658 .3 and .2 Port 0.5 Configuration Control Bits .1 and .0 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Not used Port 0.4 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Not used 4-11 CONTROL REGISTERS S3C9654/C9658/P9658 P0CONL -- Port 0 Control Register (Low Byte) (E6H, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 4-12 Port 0.3 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Not used Port 0.2 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Not used Port 0.1 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Not used Port 0.0 Configuration Control Bits 0 0 Input, rising edge external interrupt. 0 1 Input, falling edge external interrupt with pull-up resistor 1 0 Output mode, n-ch open drain 1 1 Not used S3C9654/C9658/P9658 CONTROL REGISTERS P0INT -- Port 0 Interrupt Control Register (EAH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - 0 0 0 0 0 0 Read/Write - - R/W R/W R/W R/W R/W R/W .7 and .6 Not used for S3C9654/C9658/P9658 .5 - .0 P0.5-P0.0 Interrupt Enable Bits 0 External interrupt disable 1 External interrupt enable P0PND -- Port 0 Interrupt Pending Register (EBH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - 0 0 0 0 0 0 Read/Write - - R/W R/W R/W R/W R/W R/W .7 and .6 Not used for S3C9654/C9658/P9658 .5 - .0 P0.5-P0.0 Interrupt Pending Bit 0 No pending (when read)/clear pending bit (when write) 1 Pending (when read)/no effect (when write) 4-13 CONTROL REGISTERS S3C9654/C9658/P9658 P1CONH -- Port 1 Control Register (High Byte) (E8H, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7 - .4 Not used for S3C9654/C9658/P9658 .3 and .2 Port 1.5 Configuration Control Bits .1 and .0 4-14 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input, (external reference voltage input) Port 1.4 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input S3C9654/C9658/P9658 CONTROL REGISTERS P1CONL -- Port 1 Control Register (Low Byte) E9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 Port 1.3 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input Port 1.2 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input Port 1.1 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input Port 1.0 Configuration Control Bits 0 0 Schmitt trigger input, rising edge external interrupt. 0 1 Schmitt trigger input, falling edge external interrupt with pull-up resistor 1 0 Output mode, push-pull 1 1 Comparator input, analog input 4-15 CONTROL REGISTERS S3C9654/C9658/P9658 P1INT -- Port 1 Interrupt Control Register (ECH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - 0 0 0 0 0 0 Read/Write - - R/W R/W R/W R/W R/W R/W .7 and .6 Not used for S3C9654/C9658/P9658 .5 - .0 P1.0-P1.5 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable P1PND -- Port 1 Interrupt Pending Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - 0 0 0 0 0 0 Read/Write - - R/W R/W R/W R/W R/W R/W .7 and .6 Not used for S3C9654/C9658/P9658 .5 - .0 P1.7 Interrupt Pending Bit 4-16 0 No pending (when read)/clear pending bit (when write) 1 Pending (when read)/no effect (when write) S3C9654/C9658/P9658 CONTROL REGISTERS P2CONINT -- Port 2 Control/Interrupt Control and Pending Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 Port 2.1 Configuration Control Bits 0 0 Shcmitt trigger input, falling edge external interrupt 0 1 Shcmitt trigger input, falling edge external interrupt with pull-up 1 0 N-CH open drain output mode 1 1 N-CH open drain output mode with pull-up Port 2.0 Configuration Control Bits 0 0 Shcmitt trigger input, falling edge external interrupt 0 1 Shcmitt trigger input, falling edge external interrupt with pull-up 1 0 N-CH open drain output mode 1 1 N-CH open drain output mode with pull-up P2.1-P2.0 Interrupt Enable Bit 0 External interrupt disable 1 External interrupt enable P2.1-P2.0 Interrupt Pending Bit 0 No pending (When read)/clear pending bit (When write) 1 Pending (When read)/No effect (When write) 4-17 CONTROL REGISTERS S3C9654/C9658/P9658 PDCON -- Port 1 Pull-down Resistor Control (E3H, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7 - .4 Not used for S3C9654/C9658/P9658 .3 "1" = Pull-down enable,"0" pull-down disable when P1 comparator input mode. .2 - .0 Select pull-down resistor value from 5 k-19 k 2 k/bit weight at VPORT = 2.5 V. "0x08" = 19 k "0x0F" = 5 k, when VPORT = 2.5 V PWRMGR -- USB Power Management Register (F8H) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 - .2 Always logic zero .1 RESUME Signal Sending Bit .0 4-18 0 RESUME signal is ended 1 While in suspend state, if the MCU wants to initiate a resume, it writes a 1 to this register for 10 ms (maximum of 15 ms), and clears this register. In suspend mode, if this bit is set to "1", USB generates resume signaling. SUSPEND Status Bit 0 Cleared automatically when MCU writes a zero to RESUME signal sending bit or when function receives resume signal from the host while in suspend mode 1 This bit is set when SUSPEND interrupt occur S3C9654/C9658/P9658 CONTROL REGISTERS SNKCON -- Sink Current Control Register (FDH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - - 0 0 Read/Write - - - - - - R/W R/W .7 - .2 Not used for S3C9654/C9658/P9658 .1 - .0 Select sink current of the Port 0.0 n-ch open drain. "0x00" = 30 mA, "0x01" = 40 mA, "0x02" = 50 mA, :"0x03": = 60 mA when VPORT = 0.4 V 4-19 CONTROL REGISTERS S3C9654/C9658/P9658 SUBCON -- SUB_Oscillator Control (EFH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - 0 - - 0 0 0 0 Read/Write - R/W - - R/W R/W R/W R/W .7 Not used for S3C9654/C9658/P9658 .6 Sub_Oscillator Interrupt Pending Bit 0 No pending (when read)/clear pending (when write) 1 Pending (when read)/no effect (when write) .5 - .4 Not used for S3C9654/C9658/P9658 .3 Sub_Oscillator Interrupt Enable Bit .2 and .0 0 Sub_oscillator disable, interrupt disable 1 Sub_oscillator enable, interrupt enable Sub_Oscillator Counter Input Clock Selection Bits 0 0 0 f OSC/2048 0 0 1 f OSC/3072 0 1 0 f OSC/4096 0 1 1 f OSC/6144 1 0 0 f OSC/8192 1 0 1 f OSC/12288 1 1 0 f OSC/16384 1 1 1 f OSC/24576 NOTE: fOSC= 130 KHz (Typ.) when VDD = 5.0 V, TA = 25 C. 4-20 S3C9654/C9658/P9658 CONTROL REGISTERS SYM -- System Mode Register (DFH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7 - .4 Not used for S3C9654/C9658/P9658 .3 Global Interrupt Enable Bit .2 and .0 0 Global interrupt processing disable 1 Global interrupt processing enable Page Select Bit 0 0 0 Page 0 0 0 1 Page 1 (Not allowed in S3C9654/C9658/P9658) 0 1 0 Page 2 (Not allowed in S3C9654/C9658/P9658) 0 0 1 Page 3 (Not allowed in S3C9654/C9658/P9658) 4-21 CONTROL REGISTERS S3C9654/C9658/P9658 T0CON -- Timer 0 Control Register D2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 .2 .1 .0 T0 Counter Input Clock Selection Bits 0 0 f OSC/4096 0 1 f OSC/256 1 0 f OSC/8 1 1 Not used for S3C9654/C9658/P9658 T0 Operating Mode Selection Bits 0 0 Interval timer mode (The counter is automatically cleared whenever T0DATA value equals to T0CNT value) 0 1 Invalid selection 1 0 1 1 Overflow mode (OVF interrupt can occur) T0 Counter Clear Bit (T0CLR) 0 No effect 1 Clear T0 counter (when write) T0 Overflow Interrupt Enable Bit (T0OVF) 0 Disable T0 overflow interrupt 1 Enable T0 overflow interrupt T0 Match Interrupt Enable Bit (T0INT) 0 Disable T0 match interrupt 1 Enable T0 match interrupt T0 Interrupt Pending Bit (T0PND) 0 No interrupt pending (when read)/Clear this pending bit (when write) 1 Interrupt is pending(when read)/No effect(when write) NOTE: When you write a "1" to T0CON.3, the timer 0 counter is cleared. The bit is then cleared automatically to "0". 4-22 S3C9654/C9658/P9658 CONTROL REGISTERS USBINT -- USB Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - 0 1 1 Read/Write - - - - - R/W R/W R/W .7 - .3 Not used for S3C9654/C9658/P9658 .2 SUSPEND/RESUME Interrupt Enable Bit .1 .0 0 Disable SUSPEND and RESEME interrupt (default) 1 Enable SUSPEND and RESEME interrupt ENDPOINT1 Interrupt Pending Bit 0 Disable ENDPOINT 1 interrupt 1 Enable ENDPOINT 1 interrupt (default) ENDPOINT0 Interrupt Pending Bit 0 Disable ENDPOINT 0 interrupt 1 Enable ENDPOINT 0 interrupt (default) 4-23 CONTROL REGISTERS S3C9654/C9658/P9658 USBPND -- USB Interrupt Pending Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7 - .4 Not used for S3C9654/C9658/P9658 .3 RESUME Interrupt Pending Bit .2 .1 .0 0 No effect (once read, this bit is cleared automatically) 1 This bit is set, if RESUME signaling is received while in SUSPEND mode SUSPEND Interrupt Pending Bit 0 No effect (once read, this bit is cleared automatically) 1 This bit is set, when suspend signaling is received ENDPOINT1 Interrupt Pending Bit 0 No effect (once read, this bit is cleared automatically) 1 This bit is set, when endpoint1 needs to be serviced ENDPOINT0 Interrupt Pending Bit 0 No effect (once read, this bit is cleared automatically) 1 This bit is set, while endpoint 0 needs to serviced. It is set under the following conditions: -- -- -- -- -- 4-24 OUT_PKT_RDY is set IN_PKT_RDY get cleared SENT_STALL gets set DATA_END gets cleared SETUP_END gets set S3C9654/C9658/P9658 CONTROL REGISTERS USBRST -- USB RESET Register FFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - - - 1 Read/Write - - - - - - - R/W .7 - .1 Not used for S3C9654/C9658/P9658 .0 USB Reset Signal Receive Bit 0 Clear reset signal bit 1 This bit is set when host send USB reset signal USBSEL -- PORT 2 MODE SELECT REGISTER FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - - - 0 Read/Write - - - - - - - R/W .7 - .1 Not used for S3C9654/C9658/P9658 .0 "0" = GPIO Port, PS/2 mode, "1" = USB Port USB mode. 4-25 CONTROL REGISTERS S3C9654/C9658/P9658 XCON -- USB Signal Control Register (FEH, R/W) Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - - - - Read/Write - - - - - - - - NOTE: XCON register value advised by factory. 4-26 S3C9654/C9658/P9658 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H-0001H. VECTOR SOURCES S1 0000H 0001H S2 S3 Sn NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable. Figure 5-1. S3C9-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The systemlevel control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose. 5-1 INTERRUPT STRUCTURE S3C9654/C9658/P9658 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RI, the order of service is determined by a sequence of source which is executed in interrupt service routine. "EI" Instruction Execution S RESET R Source Interrupts Source Interrupt Enable Q Interrupt Pending Register Interrpt priority is determind by software polling method Global Interrupt Control (EI, Di instruction) Figure 5-2. Interrupt Function Diagram 5-2 Vector Interrupt Cycle S3C9654/C9658/P9658 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method. INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI) -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI) to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address. 5-3 INTERRUPT STRUCTURE S3C9654/C9658/P9658 S3C9654/C9658/P9658 INTERRUPT STRUCTURE The S3C9654/C9658/P9658 microcontroller has thirteen peripheral interrupt sources: -- Timer 0 match interrupt -- Timer 0 overflow interrupt -- Suspend interrupt -- Resume interrupt -- Two Endpoint interrupts for Endpoint 0 and Endpoint 1 -- Three external interrupts for port 0, P0.0-P0.5 -- Four external interrupts for port 1, P1.1-P1.5 -- Five external interrupts for port 2, P2.0-P2.1 (PS/2 Mode only) -- Internal RC OSC interrupt. To Match Interrupt T0CON.0 T1CON.1 To Overflow Interrupt T1CON.2 SUBCON.6 Vector 0000H P0PND.0-6 SYM.3 (EI, DI) P1PND.0-5 P2PND.3 EP0_PND EP1_PND Suspend_ PND Resume_ PND Internal RC Interrupt SUBCON.3 P0.0-P0.5 Interrupt P0INT.x P1.0-P1.5 Interrupt P1INT.x PS2 PAD Interrupt P2INT.x Endpoint 0 interrupt Enable_EP0 Endpoint 1 interrupt Enable_EP1 Suspend Interrupt Resume Interrupt Suspend/Resume Interrupt Enable Figure 5-3. S3C9654/C9658/P9658 Interrupt Structure 5-4 S3C9654/C9658/P9658 7 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3C9654/C9658/P9658 has three oscillation circuit options, a crystal/ceramic oscillation and a RC oscillation and an external clock source. The crystal or ceramic oscillation source provides a maximum 6 MHz clock. The XIN and XOUT pins connect the oscillation source to the on-chip clock circuit. External clock and RC oscillation and crystal/ceramic oscillator circuits are shown in Figures 7-1, 7-2, and 7-3. XIN XIN S3C9654/ S3C9658 S3P9658 XOUT Figure 7-1. External Oscillator S3C9654/ S3C9658 S3P9658 XOUT Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator) XIN S3C9654/ S3C9658 S3P9658 R XOUT Figure 7-3. RC Oscillator 7-1 CLOCK CIRCUIT S3C9654/C9658/P9658 MAIN OSCILLATOR LOGIC To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the CPU to efficiently process logic operations. CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: -- In Stop mode, the main oscillator "freezes," halting the CPU and peripherals. The contents of the register file and current system register values are retained. RESET operation releases the Stop mode, and starts the oscillator. -- In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is retained. Idle mode is released by a RESET or by an interrupt (external or internally-generated). SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable (CLKCON.7) -- Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3) The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7. After a RESET, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2 or fOSC/8. 7-2 S3C9654/C9658/P9658 CLOCK CIRCUIT System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main system oscillator wake-up function 1 = Disable IRQ for main system oscillator wake-up function .4 .3 .2 .1 .0 LSB No effect Divide-by selection bits for CPU clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc(non-divided) No effect Figure 7-4. System Clock Control Register (CLKCON) 7-3 CLOCK CIRCUIT S3C9654/C9658/P9658 Stop Instruction CLKCON.4-.3 Oscillator Stop Main OSC Oscillator Wake-up 1/2 1/8 M U X 1/16 Noise Filter CLKCON.7 INT Pin Figure 7-5. System Clock Circuit Diagram 7-4 CUP Clock RESET and POWER-DOWN S3C9654/C9658/P9658 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW Start Up Reference Voltage Generator Comparator Glitch Filter RESET Voltage Divider NOTES: 1. Start Up Circuit: Start up reference voltage generator circuit when device powered. 2. Reference Voltage Generator: Supply voltage independent reference voltage generator. (Supply voltage must great then 2.5 V) 3. Voltage Divider: Divide supply voltage by "N" (N: integer, 2). 4. Comparator: Compare reference voltage and divided voltage. 5. Glitch Filter: Remove glitch and noise signal. Figure 8-1. LVR (LVD) Architecture 8-1 RESET and POWER-DOWN S3C9654/C9658/P9658 Vc (Compare Voltage) Divide Voltage Reference Voltage VDD (Supply Voltage) Reset Operation by LVR NOTES: 1. LVR Operation Voltage Range: 2.3 V-6.0 V 2. LVR Detection Voltage Range: 3.4 V 0.4 V 3. LVR Current Consumption: Less then 10 uA (normally 5 uA) 4. LVR Powered Reset Release Time: more then 500 usec (LVR only, typical) 5. LVR Simulation Conditions (Hspice Simulation) Temp: -40 - 80 C Process Veriation: Worst to best conditions Test Voltage: 0.0 V-7.0 V Powered Slew Rate: 5 V/1 usec- 5 V/100 msec Normal Operation Figure 8-2. LVR Characteristics The following sequence of events occur during a RESET operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0 and 1 are set to Schmitt trigger input mode and all pull-up resistors are disabled. -- Peripheral control and data registers are disabled and RESET to their initial values. -- The program counter is loaded with the ROM RESET address, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location 0100H (and 0101H) is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system RESET if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON. 8-2 RESET and POWER-DOWN S3C9654/C9658/P9658 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 120 A. All system functions are halted when the clock "freezes," but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt. Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral control registers are then RESET to their default values and the contents of all data registers are retained. RESET operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching the 16-bit address stored in ROM locations 0100H and 0101H. Using an External Interrupt to Release Stop Mode Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts in the KS86C6504/P6508 interrupt structure does not meet this criteria. Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. NOTE Do not use the STOP mode when external clock source is being used as the oscillation circuit option. IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered. There are two ways to release Idle mode: 1. Execute RESET. All system and peripheral control registers are RESET to their default values and the contents of all data registers are retained. The RESET automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. If interrupts are masked, RESET is the only way to release Idle mode. 2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction immediately following the one that initiated Idle mode is executed. NOTE Only external interrupts that are not clock-related can be used to release Stop mode. To release Idle mode, however, any type of interrupt (that is, internal or external) can be used. 8-3 RESET and POWER-DOWN S3C9654/C9658/P9658 HARDWARE RESET VALUES Tables 8-1 through 8-3 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these tables to represent specific RESET values: -- A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. -- An 'x' means that the bit value is undefined following RESET. -- A dash ('-') means that the bit is either not used or not mapped. Table 8-1. Register Values after RESET Register Name Mnemonic Bit Values After RESET Address 7 6 5 4 3 2 1 0 General purpose register file & stack area - 00-7FH x x x x x x x x Working register area - C0H-CFH x x x x x x x x T0CNT D0H 0 0 0 0 0 0 0 0 Timer 0 data register T0DATA D1H 1 1 1 1 1 1 1 1 Timer 0 control register T0CON D2H 0 0 0 0 0 0 0 0 Timer 0 counter register Location D3H is not mapped. Clock control register CLKCON D4H 0 0 0 0 0 0 0 0 System FLAG register FLAGS D5H 0 0 0 0 - - - - - - - - - - - Locations D6H-D8H are not mapped. Stack pointer SP D9H - Locations DAH-DBH are not mapped. Basic timer control register BTCON DCH 0 0 0 0 0 0 0 0 Basic timer counter register BTCNT DDH - - - - - - - - - - - - 0 0 0 0 Location DEH is not mapped. System mode register NOTE: 8-4 SYM DFH The timer 0 counter, T0CNT, the basic timer counter, BTCNT, and comparison result, CDATA, are read-only. All other registers are read/write addressable. RESET and POWER-DOWN S3C9654/C9658/P9658 Table 8-1. Register Values after RESET (Continued) Bank 0 Register Name Mnemonic Bit Values After RESET Address 7 6 5 4 3 2 1 0 Port 0 data register P0 E0H x x 0 0 0 0 0 0 Port 1 data register P1 E1H x x 0 0 0 0 0 0 Port 2 data register P2 E2H x x x x x x 0 0 PDCON E3H x x x x 0 0 0 0 Comparator control mode register CCON E4H 0 0 0 0 0 0 0 0 Comparison result register CDATA E5H x x 0 0 0 0 0 0 Port 0 low nibble control register P0CONL E6H 0 0 0 0 0 0 0 0 Port 0 high bit control register P0CONH E7H x x x x 0 0 0 0 Port 1 high bit control register P1CONH E8H x x x x 0 0 0 0 Port 1 low nibble control register P1CONL E9H 0 0 0 0 0 0 0 0 Port 0 interrupt control register P0INT EAH x x 0 0 0 0 0 0 Port 0 interrupt pending register P0PND EBH x x 0 0 0 0 0 0 Port 1 interrupt control register P1INT ECH x x 0 0 0 0 0 0 Port 1 interrupt pending register P1PND EDH x x 0 0 0 0 0 0 P2CONINT EEH 0 0 0 0 0 0 0 0 Sub oscillator control register SUBCON EFH x 0 x x 0 0 0 0 USB function address register FADDR F0H 0 0 0 0 0 0 0 0 Control endpoint status register EP0CSR F1H 0 0 0 0 0 0 0 0 Interrupt endpoint status register EP1CSR F2H 0 0 0 0 0 0 0 0 Control endpoint byte count register EP0BCNT F3H 0 0 0 0 0 0 0 0 Control endpoint FIFO register EP0FIFO F4H x x x x x x x x Interrupt endpoint FIFO register EP1FIFO F5H x x x x x x x x USB interrupt pending register USBPND F6H 0 0 0 0 0 0 0 0 USB interrupt enable register USBINT F7H 0 0 0 0 0 0 0 0 PWRMGR F8H 0 0 0 0 0 0 0 0 x x x x x x x 0 Port 1 pull-down control Port 2 control/interrupt control and pending register USB power management register Locations F9H-FAH are not mapped. USB mode select register USBSEL FBH Locations FCH is not mapped. Sink current control register USB signal control USB RESET register SNKCON FDH x x x x x x 0 0 XCON FEH x x 0 0 0 0 0 0 USBRST FFH x x x x x x x 0 8-5 S3C9654/C9658/P9658 9 I/O PORTS I/O PORTS OVERVIEW The S3C9654/C9658/P9658 has two I/O ports (Port 0, Port 1, Port 2 at PS/2 Mode only), 14 pins total. You access these ports directly by writing or reading port data register addresses. For mouse applications, ports 1.0-1.5 are usually configured as mouse sensing input. Port 0 is used for button data input. Table 9-1. S3C9654/C9658/P9658 Port Configuration Overview Port Function Description Programmability P0.0 Bit-programmable I/O port for Schmitt trigger input or n-ch open drain output (50 mA). Pull-up resistor is assignable to input pin by software and is automatically disabled for output pin. Port 0 can be individualy configured as external interrupt input. Bit P0.1 - P0.5 Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Port 0 can be individualy configured as external interrupt inputs. Bit P1.0 - P1.5 Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are individually assignable to input pins by software. Port 1 can be configured as comparator input or external interrupt inputs. Pull-down resistors are individually assignable. (in comparator input). Bit P2.0/D- P2.1/D+ Bit-programmable I/O port for Schmitt trigger input or n-ch open drain output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Port 2 can be individually configured as external interrupt pins. Also it can be configured as an USB ports. Bit 9-1 I/O PORTS S3C9654/C9658/P9658 PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0 and 1 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Hex R/W Port 0 data register P0 E0H R/W Port 1 data register P1 E1H R/W Port 2 data register P2 E2H R/W I/O Port nDATA Register (N = 0-2) MSB .5 P0.5 P1.5 .4 P0.4 P1.4 .3 P0.3 P1.3 .2 P0.2 P1.2 .1 Pn.1 Figure 9-1. Port Data Register Format 9-2 .0 Pn.0 LSB S3C9654/C9658/P9658 I/O PORTS PORT 0, PORT 1 AND PORT 2 Ports 0, 1 and 2 are bit-programmable, general-purpose, I/O ports. You can select Schmitt trigger input mode with rising edge external interrupt or push-pull output mode. Port1.0 to Port1.5 can be configured as comparator input. You access ports 0, 1 and 2 directly by writing or reading the corresponding port data registers -- P0 (E0H), P1 (E1H) and P2 (E2H). RESET clears the port control registers P0CONH, P0CONL, P1CONH, P1CONL and P2CONINT, to `00H', configuring all port 0, port 1, port 2 pins as schmitt trigger inputs. Port 0 Control Register P0CONH, E7H, R/W MSB .3 .2 .1 P0.5 3, 1 2, 0 0 0 0 1 1 1 0 1 .0 LSB P0.4 Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge ecxternal interrupt with pull-up register. Push-pull output mode. Not used. Figure 9-2. Port 0 Control Registers (P0CONH) Port 0 Control Register P0CONL, E6H, R/W MSB .7 .6 P0CONL P0.3 7, 5, 3, 1 6, 4, 2, 0 0 0 0 1 1 0 1 1 .5 .4 P0.2 .3 .2 P0.1 .1 .0 LSB P0.0 Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge ecxternal interrupt with pull-up register. Push-pull output mode. (Output mode, n-channel open drain: port 0.0 only) Not used. Figure 9-3. Port 0 Control Registers (P0CONL) 9-3 I/O PORTS S3C9654/C9658/P9658 Port 1 Control Registers P1CONH, E8H, R/W, P1CONL, E9H, R/W MSB .7 .6 .5 .4 .3 P1CONH P1.3 P1CONL 7, 5, 3, 1 6, 4, 2, 0 0 0 0 1 1 1 0 1 P1.2 .2 .1 .0 P1.5 P1.4 P1.1 P1.0 LSB Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge external interrupt with pull-up register. Push-pull output mode. Comparator input. Figure 9-4. Control Registers (P1CONH, P1CONL) + PROGRAMMING TIP -- Configuring S3C9654/C9658/P9658 Port Pins to Specification This example shows how to configure ports 0-1 to specification. The programming parameters are as follows: Examples: 1. Set port 0 push-pull output mode LD P0CONL,#0AAH ; P0.1-P0.3 Push-pull output (P0.0 Open-drain output) 2. Set port 1.4-port 1.5 schmitt trigger input mode LD P1CONH,#00H ; P1.4-P1.5 Schmitt trigger input 3. Set port 1.0-port 1.3 comparator input mode LD P1CONL,#0FFH 9-4 ; P1.0-P1.3 Comparator input S3C9654/C9658/P9658 I/O PORTS Port 2 Control Registers P2CONINT, EEH, R/W MSB P2CONINT: 7, 5 6, 4 0 0 1 1 0 1 0 1 .7 .6 P2.1 .5 .4 P2.0 .3 .2 P2.1, P2.0 interrupt enable bit .1 .0 LSB P2.1, P2.0 interrupt enable bit Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge ecxternal interrupt. N-channel open drain output mode. N-channel open drain output mode with pull-up. Figure 9-5. Port Control Registers (P2CONINT) 9-5 S3C9654/C9658/P9658 10 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C9654/C9658/P9658 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write) Timer 0 Timer 0 has two operating modes, one of which you select by the appropriate T0CON setting: -- Interval timer mode -- Overflow mode Timer 0 has the following functional components: -- Clock frequency divider (fOSC divided by 4096, 256, or 8) with multiplexer -- 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA) -- Timer 0 overflow interrupt (T0OVF) and match interrupt (T0INT) generation -- Timer 0 control register, T0CON 10-1 BASIC TIMER and TIMER 0 S3C9654/C9658/P9658 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of f OSC/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT, can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to BTCON.0. Basic Timer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function .2 .1 .0 LSB Divider clear bit for basic timer and timer 0: 0 = No effect 1 = Clear both dividers Basic timer counter clear bits: 0 = No effect 1 = Clear BTCNT Basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = non divide Figure 10-1. Basic Timer Control Register (BTCON) 10-2 S3C9654/C9658/P9658 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal to generate a reset by setting BTCON.7-BTCON.4 to any value other than '1010B' (The '1010B' value disables the watchdog function). A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting) divided by 4096 as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when Stop mode is released: 1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fOSC /4096. If an external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. When a BTCNT.4 is set, normal CPU operation resumes. Figure 10-2 and 10-3 show the oscillation stabilization time on RESET and STOP mode release, respectively. 10-3 BASIC TIMER and TIMER 0 S3C9654/C9658/P9658 Oscillation Stabilization Time Normal Operating mode 0.8 VDD VDD Reset Release Voltage RESET trst Internal Reset Release ~ RC 0.8 VDD Oscillator (XOUT) Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B tWAIT = (4096x16)/fOSC Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096 x 16/fOSC. tRST ~ RC (R is external resistor and C is on chip capacitor) Figure 10-2. Oscillation Stabilization Time on RESET Pin Used NOTE: See Figure 14-3. For LVD Reset 10-4 S3C9654/C9658/P9658 BASIC TIMER and TIMER 0 STOP Mode Normal Operating Mode Oscillation Stabilization Time Normal Operating Mode VDD STOP Instruction Execution STOP Mode Release Signal External Interrupt RESET STOP Release Signal Oscillator (XOUT) BTCNT clock 10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON. tWAIT tWAIT (When f OSC is 6 MHz) BTCON.3 BTCON.2 0 0 0 1 (1024 x 16)/fosc 2.7 ms 1 0 (128 x 16)/fosc 0.341 ms 1 1 Invalid setting (4096 x 16)/fosc 10.92 ms Figure 10-3. Oscillation Stabilization Time on STOP Mode Release 10-5 BASIC TIMER and TIMER 0 S3C9654/C9658/P9658 TIMER 0 CONTROL REGISTER (T0CON) T0CON is located at address D2H, and is read/write addressable. A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency of fOSC/4096, and disables the timer 0 overflow interrupt and match interrupt. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.3. The timer 0 overflow interrupt can be enabled by writing a "1" to T0CON.1. When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0. To enable the timer 0 match interrupt, you must write T0CON.1 to "1". To detect an interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a timer 0 match/ capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0. Timer 0 Control Register (T0CON) D2H, R/W MSB .7 .6 .5 Timer 0 input clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = Invalid selection Timer 0 operating mode selection bits: 00 = Interval match mode 01 = Invalid selection 10 = Invalid selection 11 = Overflow mode .4 .3 .2 .1 .0 LSB Timer 0 interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) No effect (when write) Timer 0 match interrupt enable bit: 0 = Disable match interrupt 1 = Enable match interrupt Timer 0 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 0 counter clear bit: 0 = No effect 1 = Clear the Timer 0 counter (when write) Figure 10-4. Timer 0 Control Register (T0CON) 10-6 S3C9654/C9658/P9658 BASIC TIMER and TIMER 0 TIMER 0 FUNCTION DESCRIPTION Interval Match Mode In interval match mode, a match signal is generated when the counter value is identical to the value written to the T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt and then clears the counter. If for example, you write the value '10H' to T0DATA, the counter will increment until it reaches '10H'. At this point, the T0 match interrupt is generated, the counter value is reset and counting resumes. Overflow Mode In overflow mode, a overflow signal is generated regardless of the value written to the T0 reference data register when the counter value is overflowed. The overflow signal generates a timer 0 overflow interrupt and then T0 counter is cleared. T0OVF Data Bus T0PND 8 CLK Counter T0INT R Comparator Match T0DATA Buffer Register When 8-Bit counter is cleared, this buffer is open T0DATA 8 Data Bus Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode 10-7 BASIC TIMER and TIMER 0 S3C9654/C9658/P9658 Bit 1 RESET or STOP Write '1010xxxxB' to disable. Bits 7, 6, 5, 4 Data Bus 1/4096 1/1024 XIN DIV R 8-Bit Up Counter (BTCNT, Read-Only) 1/128 fOSC When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts. Bits 3, 2 Bit 2 OVINT Bit 0 Bits 7, 6 R DIV Data Bus Overflow 8 1/4096 1/256 RESET OVF Bit 3 T0CLR 8-Bit Counter R (T0CNT, Read-Only) Bit 1 T0INT 1/8 8 8-Bit Comparator Match Signal Match/ Overflow 8 Bits 5, 4 T0DATA Buffer Register When 8-Bit counter is cleared. this buffer is open T0DATA 8 Data Bus Basic Timer Control Register Timer 0 Control Register Figure 10-6. Basic Timer and Timer 0 Block Diagram 10-8 Bit 0 IRQ S3C9654/C9658/P9658 11 UNIVERSAL SERIAL BUS UNIVERSAL SERIAL BUS OVERVIEW Universal Serial Bus (USB) is a communication architecture that supports data transfer between a host computer and a wide range of PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth through a host scheduled token based protocol. The USB module in S3C9654/C9658/P9658 is designed to serve at a low speed transfer rate (1.5 Mbs) USB device as described in the Universal Serial Bus Specification Revision 1.0. S3C9654/C9658/P9658 can be briefly describe as a microcontroller with SAM 87RCRI core with an on-chip USB peripheral as can be seen in figure 11-1. The S3C9654/C9658/P9658 comes equipped with Serial Interface Engine (SIE), which handles the communication protocol of the USB. The S3C9654/C9658/P9658 supports the following control logic: packet decoding/generation, CRC generation/checking, NRZI encoding/decoding, Sync detection, EOP (end of packet) detection and bit stuffing. S3C9654/C9658/P9658 supports two types of data transfers; control and interrupt. Two endpoints are used in this device; Endpoint 0 and Endpoint 1. Please refer to the USB specification revision 1.0 for detail description of USB. D+ DTransceiver Voltage Regulator SIE (Serial Interface Engine) SAM88RCRI CORE Data Bus Endpoint 0 FIFO Endpoint 1 FIFO Figure 11-1. USB Peripheral Interface 11-1 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 Serial Bus Interface Engine (SIE) The Serial Interface Engine interfaces to the USB serial data and handles, deserialization/serialization of data, NRZI encoding/decoding, clock extraction, CRC generation and checking, bit stuffing and other specifications pertaining to the USB protocol such as handling inter packet time out and PID decoding. Control Logic The USB control logic manages data movements between the CPU and the transceiver by manipulating the transceiver and the endpoint register. This includes both transmit and receive operations on the USB. The logic contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to determine the number of bytes to transfer. The same buffer is used for receive transactions to count the number of bytes received and transfer that number to the receive endpoint's byte count register at the end of the transaction. The control logic in S3C9654/C9658/P9658, when transmitting, manages parallel to serial conversion, packet generation, CRC generation, NRZI encoding and bit stuffing. When receiving, the control logic in S3C9654/C9658/P9658 handles Sync detection, packet decoding, EOP (end of packet) detection, bit (un)stuffing, NRZI decoding, CRC checking and serial to parallel conversion Bus Protocol All bus transactions involve the transmission of packets. S3C9654/C9658/P9658 supports three packet types; Token, Data and Handshake. Each transaction starts when the host controller sends a Token Packet to the USB device. The Token packets are generated by the USB host and decoded by the USB device. A Token Packet includes the type description, direction of the transaction, USB device address and the endpoint number. Data and Handshake packets are both decoded and generated by the USB device. In any transaction, the data is transferred from the host to a device or from a device to the host. The transaction source then sends a Data Packet or indicates that it has no data to transfer. The destination then responds with a Handshake Packet indicating whether the transfer was successful. Data Transfer Types USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint supports a specific type of data transfer. The S3C9654/C9658/P9658 supports two data transfer endpoints: control and interrupt. Control transfer configures and assigns an address to the device when detected. Control transfer also supports status transaction, returning status information from device to host. Interrupt transfer refers to a small, spontaneous data transfer from USB device to host. Endpoints Communication flows between the host software and the endpoints on the USB device. Each endpoint on a device has an identifier number. In addition to the endpoint number, each endpoint supports a specific transfer type. S3C9654/C9658/P9658 supports two endpoints: Endpoint 0 supports control transfer, and Endpoint 1 supports interrupt transfer. 11-2 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS STRUCTURE OF USB AND PS/2 COMBINATIONAL PORT Pull-up Enable USB Enable [A] Voltage Regulator (3.3 V Generation) [B] USB Signal Transceiver (With Pull-up) DM DP USB Control PS/2 Control (P2CONINT) NOTE: [C] PS/2 Signal Transceiver (With Pull-up) That block explain USB block can be enabled or disabled with pull-up by s/w. Voltage regulator also disabled automatically when USB block was disabled. And PS/2 block can be controlled by software with pull-up. Figure 11-2. Block Diagram of USB and PS/2 Transceiver 11-3 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 STRUCTURE OF VOLTAGE REGULATOR Enable Reference Voltage Generator A Current Amplifier 3.3 V Out B NOTE: This blcok can give a explanation how it can be controlled automatically. When the 3.3 voltage regulator be enable by software, voltage regulator will operating to cover fluctuation of the line load, sometimes the line is not stabled and the driving ability will be dropped. As it operating in the normal stage without any peak, power will be supplied with 8 mA, and when the operating. Current consumption go to peak, it was designed to cover by 50 mA. It means any kind of load problem will be compensated with above design. Figure 11-3. Block Diagram of Voltage Regulator 11-4 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS STRUCTURE OF USB SIGNAL TRANSMITTER Pull-up Control R, 1.5 K C A V33IN D- Control Sinals CTRL Enable D+ B DM TX/RX DM DP TX/RX DP Bias Clamp D NOTE: We didn't used the by-pass capacitor on the 3.3 V out, since the 3.3 V regulator and clamp circuit will give a solution through the feedback. USB block was designed to cover the line load, the typical value designed is 300 pF (max: 650 pF). The calmp block operating after it detect the voltage variation (actually the current fluctuation will be feedback into voltage variation, di/dt to dv/dt variation. Bias control the slope. Control signals means NRZI, EOP, XCON, IN/OUT. Enable is for the Tx, Rx. Internal pull-up resistor will be 1.5 K Figure 11-4. Block Diagram of USB Signal Transceiver 11-5 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 STRUCTURE OF PS/2 SIGNAL TRANSMITTER VDD VDD DM_DRVP DP_DRVP 4.3 K 4.3 K Pull-up Enable DM_DRVN NOTE: Pull-up Enable DM PS/2 Data DP_DRVN DP PS/2 CLK It explain the PS/2 block. The pull-up resistor value will be 4.3 k 20 % (Vport = 0 V) This block can be controlled with pull-up resistor and it was designed with totally different from usb. Figure 11-5. Block Diagram of PS/2 Signal Transmitter 11-6 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS USB FUNCTION ADDRESS REGISTER (FADDR) This register holds the USB address assigned by the host computer. USBADDR is located at address F0H and is read/write addressable. Bit7 Not used Bit6-0 FADDR: MCU updates this register once it decodes a SET_ADDRESS command. MCU must write this register before it clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0STU register. The function controller use this register's value to decode USB Token packet address. At reset, if the device is not yet configured the value is reset to 0. USB Function Address Register (FADDR) F0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used 7-bit programming device address. This register maintains the USB address assigned by the host. The function controller uses this register's value to decode USB token packet address. At reset when the device is not yet configured the value is reset to 0. Figure 11-6. USB Function Address Register (FADDR) 11-7 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 CONTROL ENDPOINT STATUS REGISTER (EP0CSR) EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is located at F1H and is read/write addressable. Bit7 CLEAR_SETUP_END: MCU writes "1" to this bit to clear SETUP_END bit (bit4). This bit is automatically cleared after writing "1" by USB block. Bit6 CLEAR_OUT_PKT_RDY: MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is automatically cleared after writing "1" by USB block. Bit5 SEND_STALL: MCU writes "1" to this bit to send STALL signal to the Host, at the same time it clears OUT_PKT_RDY (bit0), if it decodes an invalid token. USB issues a STALL Handshake to the current control transfer. This bit gets cleared once a STALL Handshake is issued to the current control transfer. Bit4 SETUP_END: USB sets this bit, when a control transfer ends before DATA_END bit (bit3) is set. MCU clears this bit, by writing a "1" to SERVICED_SETUP_END bit (bit7). When USB sets this bit, an interrupt is generated to MCU. When such condition occurs, USB flushes the FIFO, and invalidates MCU's access to FIFO. Bit3 DATA_END: MCU sets this bit: -- After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit is set. -- While it clears OUT_PKT_RDY bit after unloading the last packet of data. -- For a zero length data phase, when it clears OUT_PKT_RDY bit, and sets IN_PKT_RDY bit. Bit2 SENT_STALL: USB sets this bit, if a control transaction has ended due to a protocol violation. An interrupt is generated when this bit gets set. MCU clears this bit to end the STALL condition. Bit1 IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 0 FIFO. USB clears this bit, once the packet has been successfully sent to the host. An interrupt is generated when USB clears this bit so that MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit and DATA_END bit at the same time. Bit0 OUT_PKT_RDY: USB sets this bit, once a valid token is written to FIFO. An interrupt is generated, when USB sets this bit. MCU clears this bit by writing "1" to SERVICED_OUT_PKT_RDY bit. NOTES: 1. In control transfer case, where there is no data phase, MCU after unloading the setup token, sets IN_PKT_RDY, and DATA_END at the same time it clears OUT_PKT_RDY for the setup token. 2. When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer has ended, and a new control transfer is received before MCU can service the interrupt. In such case, MCU should first clear SETUP_END bit, and then start servicing the new control transfer. 11-8 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS Control Endpoint Status Register (EP0CSR) F1H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB OUT_PKT_RDY CLEAR_ SETUP_END IN_PKT_RDY CLEAR_ OUT_PKT_RDY SENT_STALL SEND_STALL DATA_END SETUP_END Figure 11-7. Control Endpoint Status Register (EP0CSR) 11-9 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 INTERRUPT ENDPOINT STATUS REGISTER (EP1CSR) EP1CSR is the control register for Endpoint 1, Interrupt Endpoint. This register is located at address F2H and is read/write addressable. Bit7 CLR_DATA_TOGGLE: MCU writes "1" to this bit to clear the data toggle sequence bit. When the MCU writes a 1 to this register, the data toggle bit is initialized to DATA0. Bit6-3 MAXP: These bits indicate the maximum packet size for IN endpoint, and needs to be updated by MCU before it sets IN_PKT_RDY. Once set, the contents are valid till MCU re-writes them. Bit2 FLUSH_FIFO: When MCU writes "1" to this register, the FIFO is flushed, and IN_PKT_RDY cleared. The MCU should wait for IN_PKT_RDY to be cleared for the flush to take place. Bit1 FORCE_STALL: MCU writes "1" to this register to issue a STALL Handshake to USB. MCU clears this bit, to end the STALL condition. Bit0 IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 1 FIFO. USB clears this bit, once the packet has been successfully sent to the Host. An interrupt is generated when USB clears this bit, so MCU can load the next packet. Control Endpoint Status Register (EP1CSR) F2H, R/W MSB .7 .6 .5 .4 .3 .2 .1 CLEAR_DATA_TOGGLE .0 LSB IN_PKT_RDY MAXP FORCE_STALL FLUSH_FIFO Figure 11-8. Interrupt Endpoint Status Register (EP1CSR) CONTROL ENDPOINT BYTE COUNT REGISTER (EP0BCNT) EP0BCNT register has the number of valid bytes in Endpoint 0 FIFO. It is located at address F3H read only addressable. Once the MCU receives a OUT_PKT_RDY (Bit0 of EP0CSR) for Endpoint 0, then it can read this register to find out the number of bytes to be read from Endpoint 0 FIFO. 11-10 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS CONTROL ENDPOINT FIFO REGISTER (EP0FIFO) This register is bi-directional, 8 byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at address F4H and is read/write addressable. Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control transfer, that is, after MCU unload the setup token bytes, and clears OUT_PKT_RDY, the direction of FIFO is changed automatically from MCU to the Host. INTERRUPT ENDPOINT FIFO REGISTER (EP1FIFO) EP1FIFO is an uni-direction 8-byte depth FIFO used to transfer data from the MCU to the Host. MCU writes data to this register, and when finished set IN_PKT_RDY. This register is located at address F5H. USB INTERRUPT PENDING REGISTER (USBPND) USBPND register has the interrupt bits for endpoints and power management. This register is cleared once read by MCU. While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H. Bit7-4 Not used Bit3 RESUME_PND: While in suspend mode, if resume signaling is received this bit gets set. Bit2 SUSPEND_PND: This bit is set, when suspend signaling is received. Bit1 ENDPT1_PND: This bit is set, when Endpoint 1 needs to be serviced. Bit0 ENDPT0_PND: This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the following conditions: -- OUT_PKT_RDY is set. -- IN_PKT_RDY gets cleared. -- SENT_STALL gets set. -- DATA_END gets cleared. -- SETUP_END gets set. USB Interrupt Pending Register (USBPND) F6H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB ENDPT0_PND Not used RESUME_PND ENDPT1_PND SUSPEND_PND Figure 11-9. USB Interrupt Pending Register (USBPND) 11-11 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 USB INTERRUPT ENABLE REGISTER (USBINT) USBINT is located at address F7H and is read/write addressable. This register serves as an interrupt mask register. If the corresponding bit = 1 then the respective interrupt is enabled. By default, all interrupts except suspend interrupt is enabled. Interrupt enables bits for suspend and resume is combined into a single bit (bit 2). Bit7-3 Not used Bit2 ENABLE_SUSPEND_RESUME_INT: 1 Enable SUSPEND and RESUME INTERRUPT 0 Disable SUSPEND and RESUME INTERRUPT (default) Bit1 ENABLE_ENDPT1_INT: 1 Enable ENDPOINT 1 INTERRUPT (default) 0 Disable ENDPOINT 1 INTERRUPT Bit0 ENABLE_ENDPT0_INT: 1 Enable ENDPOINT 0 INTERRUPT (default) 0 Disable ENDPOINT 0 INTERRUPT USB Interrupt Enable Register (USBINT) F7H, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .0 LSB ENABLE_ENDPT0_INT ENABLE_ENDPT1_INT ENABLE_SUSPEND_RESUME_INT Figure 11-10. USB Interrupt Enable Register (USBINT) 11-12 S3C9654/C9658/P9658 UNIVERSAL SERIAL BUS USB POWER MANAGEMENT REGISTER (PWRMGR) PWRMGR register interacts with the Host's power management system to execute system power events such as SUSPEND or RESUME. This register is located at address F8H and is read/write addressable. Bit7-2 RESERVED: The value read from this bit is zero. Bit1 SEND_RESUME: While in SUSPEND state, if the MCU wants to initiate RESUME, it writes "1" to this register for 10ms (maximum of 15ms), and clears this register. In SUSPEND mode if this bit reads "1", USB generates RESUME signaling. Bit0 SUSPEND_STATE: Suspend state is set when the MCU sets suspend interrupt. This bit is cleared automatically when: -- MCU writes "0" to SEND_RESUME bit to end the RESUME signaling (after SEND_RESUME is set for 10ms). -- MCU receives RESUMES signaling from the Host while in SUSPEND mode. USB Power Mangement Register (PWRMGR) F8H, R/W MSB .7 .6 .5 .4 .3 The value read form this bits is zero .2 .1 .0 LSB SUSPEND_STATE SEND_RESUME Figure 11-11. USB Power Management Register (PWRMGR) 11-13 UNIVERSAL SERIAL BUS S3C9654/C9658/P9658 USB RESET REGISTER (USBRST) USBRST register receives a reset signal from the Host. This register is located at address FFH and is read/write addressable. Bit7-1 Not used Bit0 USBRST: This bit is set when the Host issues an USB reset signal. USB RESET Register (USBRST) FFH, R/W MSB .7 .6 .5 .4 Not used .3 .2 .1 .0 USBRST Figure 11-12. USB RESET Register (USBRST) 11-14 LSB S3C9654/C9658/P9658 12 COMPARATOR COMPARATOR OVERVIEW P1.0-P1.5 can be used as a analog input port for a comparator. The reference voltage for the 6-channel comparator can be supplied either internally or externally at P1.5. When an internal reference voltage is used, six channels (P1.0-P1.5) are used for analog inputs and the internal reference voltage is varied in 32 levels. If an external reference voltage is input at P1.5, the other three pins (P1.0-P1.4) in port x are used analog input. Unused port x pins should be connected to VDD or VSS for current saving. When a conversion is completed, the result is saved in the comparison result register CDATA. The initial values of the CDATA are undefined and the comparator operation is disabled by a RESET. -- Analog comparator -- Internal reference voltage generator (5-bit resolution) -- External reference voltage source at P1.5 -- Comparator mode register (CCON) -- Four multiplexed analog data input pins (CIN0-CIN5) -- 6-channel conversion data result register (CDATA) -- 6-bit digital input port (alternatively, I/O port) -- Internal reference voltage is varied in 32 levels with hysteresis. FUNCTION DESCRIPTION The comparator compares analog voltage input at CIN0-CIN5 with an external or internal reference voltage (VREF) that is selected by CCON register. The result is written to the comparison result register CDATA at address E5H. The comparison result is calculated as follows. If "1" Analog input voltage VREF + 100 mV If "0" Analog input voltage VREF - 100 mV To obtain a comparison result, the data must be read out from the CDATA register after VREF is updated by changing the CCON value after a conversion time has elapsed. 12-1 COMPARATOR S3C9654/C9658/P9658 COMPARATOR CONTROL REGISTER (CCON) The comparator control register CCON is an 8-bit register that is used to set the operation mode of the comparator. To initiate a comparison procedure, you write the reference voltage selection data in the comparator control register CCON and set the comparison start of enable bit, CCON.7. 6-Bit Comparator Control Register (CCON) MSB .7 .6 Comparison start control bit: 1 = Start of enable the operation 0 = Disable the operation Comparison time selection bit: 1 = Comparison time (6 x 12/fCPU) 0 = Comparison time (6 x 192/fCPU) .5 .4 .3 .2 .1 .0 Reference voltage (VREF) selection bits: VDD x (n + 0.5)/24, n = 0 to 7 VDD x (0.3125 + (n-7)/48), n = 8 to 23 VDD x (0.6458 + (n-23)/24), n = 24 to 31 Example: n=0 VREF = 0.104 V (VDD = 5 V) n = 2 VREF = 0.313 V . . . n=7 n=8 VREF = 1.563 V VREF = 1.667 V Reference selection bits: 1 = CIN5: External reference, CIN0-4: Analog input 0 = Inrternal reference, CIN0-5: Analog input Figure 12-1. Comparison Control Register (CCON) 12-2 LSB S3C9654/C9658/P9658 COMPARATOR Internal Reference Voltage 5.00 VDD = 5 V 4.50 4.00 Ref Volatage 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 STEP Figure 12-2. Internal Reference Voltage (Hysteresis) 12-3 COMPARATOR S3C9654/C9658/P9658 BLOCK DIAGRAM Scan Signal 6 P0.0/CIN0 P0.1/CIN1 M U X P0.2/CIN2 P0.3/CIN3 Comparison Result Register (CMPREG) + P0.4/CIN4 - P0.5/CIN5 6 5-19 k M U X External Vreference Interval Vreference x6 6 4 I N T E R N A L P1CONH 4 B U S P1CONL 8 PDCON.3 3 PDCON.[2:0] Analog Input Mode 2 4 VDD 32 STEP CCON.7 M U X CCON.6 8 CCON.5 5 CCON.[4:0] Figure 12-3. Comparator Functional Block Diagram 12-4 S3C9654/C9658/P9658 13 SUB RC OSCILLATOR SUB RC OSCILLATOR OVERVIEW The S3C9654/C9658/P9658 have a programmable SUB RC OSCILLATOR. During IDLE or STOP, programmable SUB RC OSCILLATOR generated interrupt using SUB RC OSCILLATOR control register (SUBCON). SUB RC OSCILLATOR CONTROL REGISTER (SUBCON) SUB RC OSCILLATOR Control Register MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Sub RC oscillator counter input clock selection bits: Interrupt pending bit: 1 = No pending 0 = Pending Not used 000 001 010 011 100 101 110 111 fOSC/2048 fOSC/3072 fOSC/4096 fOSC/6144 fOSC/8192 fOSC/12288 fOSC/16384 fOSC/24576 Sub RC oscillator enable bit: 1 = Sub oscillator enable; interrupt enable 0 = Sub oscillator disable; interrupt disable NOTE: fOSC = 130 KHz typ. when VDD = 5.0 V, TA = 25 C Figure 13-1. SUB RC OSCILLATOR Control Register 13-1 LVR (LOW VOLTAGE RESET) RESET S3C9654/C9658/P9658 14 LVR (LOW VOLTAGE RESET) RESET OVERVIEW The S3C9654/C9658/P9658 have a LVR (Low Voltage Reset) for power on reset and voltage reset. Start Up Reference Voltage Generator Comparator Glitch Filter RESET Voltage Divider Figure 14-1. LVR Architecture -- Low Voltage Reset generated RESET signal. -- Start Up Circuit: Start up reference voltage generator circuit when device powered. -- Reference Voltage Generator: Supply Voltage indeoendent reference voltage generator. -- Voltage Divider: Divide supply voltage by "N" -- Comparator: Compare reference voltage and divided voltage. -- Glitch Filter: Remove glitch and noise signal. 14-1 LVR (LOW VOLTAGE RESET) RESET Vc (Compare Voltage) S3C9654/C9658/P9658 Divide Voltage Reference Voltage VDD (Supply Voltage) Reset Operation by LVR NOTES: 1. LVR Operation Voltage Range: 2.3 V-6.0 V 2. LVR Detection Voltage Range: 3.4 V 0.4 V 3. LVR Current Consumption: Less then 10 uA (normally 5 uA) 4. LVR Powered Reset Release Time: more then 500 usec (LVR only, typical) 5. LVR Simulation Conditions (Hspice Simulation) Temp: 0 C - 80 C Process Veriation: Worst to best conditions Test Voltage: 0.0 V - 7.0 V Powered Slew Rate: 5 V/1 usec- 5 V/100 msec Normal Operation Figure 14-2. LVR Characteristics 14-2 LVR (LOW VOLTAGE RESET) RESET S3C9654/C9658/P9658 LVR AND POWER ON RESET OPERATIONS T2 Normal Operating mode Oscillation Stabilization Time VDD LVD RESET Release Internal RESET Release Oscillator (XOUT) T1 LVD RESET Release Time T3 Oscillator Stabilization Time BTCNT clock 10000B BTCNT value 00000B tWAIT = (4096x16)/fOSC Basic timer increment and CPU operations are IDLE mode NOTES: 1. T1 = 500 usc (at normal) 2. T2 = T1 + (4096 x 16)/fOSC Figure 14-3. LVR and Power On RESET Operation 14-3 S3C9654/C9658/P9658 15 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9654/C9658/P9658 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- I/O capacitance -- A.C. electrical characteristics -- Oscillator characteristics -- Operating voltage range -- Oscillation stabilization time -- Clock timing measurement points at XIN -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- Stop mode release timing when initiated by an external interrupt -- Characteristic curves -- Comparator Electrical Characteristics 15-1 ELECTRICAL DATA S3C9654/C9658/P9658 Table 15-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol Conditions VDD - Rating Unit - 0.3 to + 6.5 V Input voltage VI All ports - 0.3 to VDD + 0.3 V Output voltage VO All output ports - 0.3 to VDD + 0.3 V Output current high I OH One I/O pin active - 18 All I/O pins active - 60 One I/O pin active (except P0.0) + 30 Total pin current for ports 0, 1, 2 (except P0.0) + 100 P0.0 + 50 Output current low I OL Operating temperature TA - 0 to + 85 Storage temperature TSTG - - 60 to + 150 15-2 mA mA C S3C9654/C9658/P9658 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (TA = 0C to + 85C, VDD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit 0.8 VDD - VDD V VIH1 All input pins except VIH2, D+, D- VIH2 XIN VIL1 All input pins except VIL2, D+, D- - - 0.2 VDD VIL2 XIN - - 0.4 Output high voltage VOH VDD = 4.0 V-5.25 V IOH = - 200 A All output ports except D+, D- VDD - 1.0 - - Output low voltage VOL VDD = 4.0 V-5.25 V IOL = 2 mA All output ports except D+, D-, P0.0 - - 0.4 Output low Current IOL VOL = 0.4 V Input high leakage current ILIH1 VIN = VDD All inputs except ILIH2 except D+, D-, XOUT - - 3 ILIH2 VIN = VDD, XIN - - 20 ILIL1 VIN = 0 V All inputs except ILIL2 except D+, D-, XOUT - - -3 ILIL2 VIN = 0 V, XIN - - - 20 Output high leakage current ILOH VOUT = VDD All output pins except D+, D- - - 3 Output low leakage current ILOL VOUT = 0 V All output pins except D+, D- XOUT, P0.0 - - -3 Pull-up resistors RL1 VIN = 0 V, VDD = 5.0 V, Port 0, Port 1 25 50 100 RL2 VIN = 0 V, VDD = 5.0 V, Port 2 - 4.3 - IDD1 Normal operation mode, VDD = 4.0 V-5.25 V 6 MHz, CPU clock - 6.5 15 IDD2 IDLE mode VDD = 4.0 V-5.25 V 6 MHz, CPU clock - 2 4 IDD3 Stop mode, oscillator stop VDD = 4.0 V-5.25 V - 13 25 Input high voltage Input low voltage Input low leakage current Supply current VDD - 0.5 VDD 50(4) mA A K mA A NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current load. 2. This parameter is guaranteed, but not tested (include D+, D-). 3. Only in 4.0 V to 5.25 V, D+ and D- satisfy the USB spec 1.0. 4. P0.0 designed for direct LED current sink, see the SNKCON resistor and Figure 1-9 (Page 1-9). 15-3 ELECTRICAL DATA S3C9654/C9658/P9658 Table 15-3. Input/Output Capacitance (TA = 0C to + 85C, VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS - - 10 pF Output capacitance COUT - 33 - Min Typ Max Unit 100 - 200 ns I/O capacitance XI/XO capacitance Except XIN, XOUT CIO CXI, CXO XIN, XOUT Table 15-4. A.C. Electrical Characteristics (TA = 0C to + 85C, VDD = 4.0 V to 5.25 V) Parameter Noise filter Symbol Conditions tNF1H, tNF1L P1 (RC delay) tNF1L tNF1H tNF2 0.8 VDD 0.5 VDD 0.2 VDD Figure 15-1. Nose Filter Timing Measurement Points 15-4 S3C9654/C9658/P9658 ELECTRICAL DATA Table 15-5. Oscillator Characteristics (TA = 0C + 85C) Oscillator Clock Circuit Main crystal Main ceramic (fOSC) X IN Test Condition Min Typ Max Unit Oscillation frequency VDD = 4.0 V-5.25 V - 6.0 - MHz Oscillation frequency VDD = 4.0 V-5.25 V - 6.0 - MHz X OUT External clock X IN X OUT RC oscillator XIN R XOUT Oscillation frequency VDD = 5.0 V R = 22.6 K R = 8.8 K R = 3.2 K MHz - - - 1.0 2.0 4.0 - - - Table 15-6. Oscillation Stabilization Time (TA = 0C + 85C, VDD = 4.0 V to 5.25 V) Oscillator Test Condition Min Typ Max Unit - - 10 ms Main crystal VDD = 4.0 V to 5.25 V, fOSC > 6.0 MHz Main ceramic (Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.) Oscillator tWAIT stop mode release time by a reset - 216/fOSC - stabilization wait time tWAIT stop mode release time by an interrupt - - - NOTE: The oscillator stabilization wait time, tWAIT, when it is released by an interrupt, is determined by the setting in the basic timer control register, BTCON. 15-5 ELECTRICAL DATA S3C9654/C9658/P9658 1/f OSC tXL tXH V DD - 0.5 V X IN 0.4 V Figure 15-2. Clock Timing Measurement Points at XIN Table 15-7. Data Retention Supply Voltage in Stop Mode (TA = 0C to + 70C) Parameter Symbol Conditions Data retention supply voltage VDDDR Stop mode Data retention supply current IDDDR Stop mode; VDDDR = 2.0 V 15-6 Min Typ Max Unit 2.0 - 6 V - - 5 A S3C9654/C9658/P9658 ELECTRICAL DATA IDLE Mode (Basic Timer Active) ~ ~ Stop Mode Data Retention Mode External Interrupt ~ ~ VDD Normal Operating Mode VDDDR Execution Of Stop Instrction 0.8 VDD 0.2 VDD tWAIT Figure 15-3. Stop Mode Release Timing When Initiated by an External Interrupt Table 15-8. Comparator Electrical Characteristics (TA = 0C to + 85C, VDD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Conversion time (1) tCON - - 6 x 12 or 6 x 192 - f CPU Comparator input voltage VICN - VSS - VDD V Comparator input impedance RCN - 2 1000 - M Comparator reference voltage VREF - 1.8 - VDD V Comparator input current ICIN VDD = 5 V -3 - 3 A Reference input current IREF VDD = 5 V -3 - 3 A Comparator block ICOM VDD = 5.5 V - 1 2 mA VDD = 4.5 V 0.5 1 mA VDD = 5 V (when power down mode) 100 500 nA current (2) NOTES: 1. Conversion time is the time required from the moment a conversion operation starts until it ends. 2. ICOM is an operating current during conversion. 15-7 ELECTRICAL DATA S3C9654/C9658/P9658 Table 15-9. Low Speed Source Electrical Characteristics (USB) (TA = 0C to + 85C, Internal Voltage Regulator Output V33OUT = 2.8 V to 3.6 V, typ 3.3 V) Parameter Symbol Conditions Min Max Unit CL = 200 pF 75 - ns CL = 650 pF - 300 CL = 200 pF 75 - CL = 650 pF - 300 Transition Time: Rise Time Tr Fall Time Tf Rise/Fall Time Matching Trfm (Tr/Tf) CL = 50 pF 80 125 % Output Signal Crossover Voltage Vcrs CL = 50 pF 1.3 2.0 V Internal Voltage Regulator Output Voltage V33OUT VDD = 4.0 - 5.25 V 2.8 3.6 V Test Point V33OUT S/W D-/D+ D. U. T R1 R2 90 % 90 % Measurement Points 10 % C2 10 % Tr R1 = 15 K R2 = 1.5 K CL = 200 pF - 650 pF Tf DM: S/W ON DP: S/W OFF Figure 15-4. USB Data Signal Rise and Fall Time 3.3 V DP MAX: 2.0 V VCRS MIN: 1.3 V DM 0V Figure 15-5. USB Output Signal Crossover Point Voltage 15-8 S3C9654/C9658/P9658 16 MECHANICAL DATA MECHANICAL DATA OVERVIEW This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad diagram #11 0-15 0.2 5 20-DIP-300A +0 - 0 .10 .05 7.62 6.40 0.20 #20 0.46 0.10 (1.77) NOTE: 1.52 0.10 2.54 5.08 MAX 26.40 0.20 3.30 0.30 26.80 MAX 3.25 0.20 #10 0.51 MIN #1 Dimensions are in millimeters. Figure 16-1. 20-DIP 300A Package Dimensions 16-1 MECHANICAL DATA S3C9654/C9658/P9658 9.25 #11 7.62 6.48 #20 0.3 8 20-DIP-300A-SG #1 #10 2.54 4.06 1.63 3.51 (2.92) 3.43 0.56 0.89 28.85 Figure 16-2. 20-DIP-300A-SG Package Dimensions 16-2 S3C9654/C9658/P9658 MECHANICAL DATA 0-8 #1 #10 2.30 0.10 0.203 14.10 MAX 13.70 0.20 + 0.10 - 0.05 0.85 0.20 20-SOP-300 9.53 5.40 0.20 #11 2.50 MAX 7.80 0.30 #20 1.27 (0.66) 0.40 NOTE: + 0.10 - 0.05 0.05 MIN 0.10 MAX Dimensions are in millimeters. Figure 16-3. 20-SOP-300 Package Dimensions 16-3 MECHANICAL DATA S3C9654/C9658/P9658 10.03 #10 7.62 6.48 #18 0.3 8 18-DIP-300A-SG #1 #9 2.54 4.06 1.63 3.51 (1.53) 3.18 0.56 0.89 23.50 Figure 16-4. 18-DIP-300A-SG Package Dimensions 16-4 S3C9654/C9658/P9658 MECHANICAL DATA 0-8 #10 7.59 18-SOP-BD300-AN #1 0.29 #9 18.06 0.48 2.64 0.32 1.02 10.41 #18 1.27BSC Figure 16-5. 18-SOP-BD300-AN Package Dimensions 16-5 MECHANICAL DATA S3C9654/C9658/P9658 0.3 8 16-DIP-300A-SG 10.03 #9 7.62 6.48 #16 #1 #8 2.54 4.06 1.63 3.51 (0.53) 3.43 0.56 0.89 19.23 Figure 16-6. 16-DIP-300A-SG Package Dimensions 16-6 S3C9654/C9658/P9658 MECHANICAL DATA 0-8 #9 7.60 16-SOP-BD300-SG #1 0.30 #8 10.56 0.48 2.65 0.32 1.27 10.50 #16 1.27BSC Figure 16-7. 16-SOP-BD300-SG Package Dimensions 16-7 S3C9654/C9658/P9658 17 S3P9658 OTP S3P9658 OTP OVERVIEW The S3P9658 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3P9658 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9658 is fully compatible with the S3P9658, both in function and in pin configuration. Because of its simple programming requirements, the S3P9658 is ideal for use as an evaluation chip for the S3P9658. P0.2/INT0 1 20 P0.3/INT0 VSS/VSS 2 19 VDD P0.0/INT0 3 18 P2.0/D-/INT2 SCLK/P1.0/COM0/INT1 4 17 P2.1/D+/INT2 SDAT/P1.1/COM1/INT1 5 16 RESET/RESET RESET P1.2/COM2/INT1 6 15 XIN P1.3/COM3/INT1 7 14 XOUT P1.4/COM4/INT1 8 13 TEST/TEST P1.5/COM5/INT1 9 12 P0.1/INT0 10 11 P0.5/INT0 P0.4/INT0 NOTE: S3P9658 The bold is indicate an OTP pin name. Figure 17-1. S3P9658 Pin Assignments (20 Pin) 17-1 KS86P6504/P6508 OTP S3C9654/C9658/P9658 P0.2/INT0 1 18 P0.3/INT0 VSS/VSS 2 17 VDD/VDD P0.0/INT0 3 16 P2.0/D-/INT2 SCLK/P1.0/COM0/INT1 4 15 P2.1/D+/INT2 SDAT/P1.1/COM1/INT1 5 14 RESET/RESET RESET P1.2/COM2/INT1 6 13 XIN P1.3/COM3/INT1 7 12 XOUT P1.4/COM4/INT1 8 11 TEST/TEST P1.5/COM5/INT1 9 10 P0.1/INT0 NOTE: S3P9658 The bold is indicate an OTP pin name. Figure 17-2. S3P9658 Pin Assignments (18 Pin) VSS/VSS 1 16 VDD/VDD P0.0/INT0 2 15 P2.0/D-/INT2 SCLK/P1.0/COM0/INT1 3 14 P2.1/D+/INT2 SDAT/P1.1/COM1/INT1 4 13 RESET/RESET RESET P1.2/COM2/INT1 5 12 XIN P1.3/COM3/INT1 6 11 XOUT P1.4/COM4/INT1 7 10 TEST/TEST P1.5/COM5/INT1 8 9 NOTE: S3P9658 P0.1/INT0 The bold is indicate an OTP pin name. Figure 17-3. S3P9658 Pin Assignments (16 Pin) 17-2 S3C9654/C9658/P9658 S3P9658 OTP Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.0 During Programming Pin Name Pin Number (20 DIP) I/O SDAT 5 I/O Serial Data Pin (Output when reading, Input when writing) Input and Push-pull Output Port can be assigned SCLK 4 I/O Serial Clock Pin (Input Only Pin) RESET RESET 16 I 0 V : OTP write and test mode 5 V : Operating mode TEST VPP (TEST) 13 I Chip Initialization and EPROM Cell Writing Power Supply Pin (Indicates OTP Mode Entering) When writing 12.5 V is applied and when reading. VDD/VSS VDD/VSS 19/2 I Logic Power Supply Pin. P1.1 Function Table 17-2. Comparison of S3P9658 and S3C9654/C9658 Features Characteristic S3P9658 S3C9654/C9658 Program Memory 8 K-byte EPROM 4/8 K-byte mask ROM Operating Voltage (VDD) 4.0 V to 5.25 V 4.0 V to 5.25 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 20/18/16 DIP, 20/18/16 SOP 20/18/16 DIP, 20/18/16 SOP, 16SSOP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (RESET) pin of the S3P9658, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 14-3 below. Table 17-3. Operating Mode Selection Criteria VDD VPP (RESET RESET) REG/MEM MEM Address (A15-A0) R/W 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 17-3 S3C9654/C9658/P9658 18 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code(.OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device automatically. 18-1 DEVELOPMENT TOOLS S3C9654/C9658/P9658 TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One times programmable microcontrollers (OTPs) are under development for S3C9654/C9658/P9658 microcontroller. IBM-PC AT or Compatible RS-232C SMDS2+ Target Application System PROM/OTP Writer Unit RAM Break/Display Unit Bus Probe Adapter Trace/Timer Unit SAM8 Base Unit Power Supply Unit POD TB9654/8A Target Board EVA Chip Figure 18-1. SMDS Product Configuration (SMDS2+) 18-2 S3C9654/C9658/P9658 DEVELOPMENT TOOLS TB9654/8A TARGET BOARD The TB9654/8A target board is used for the S3C9654/C9658/P9658 microcontrollers. It is supported by the SMDS2+ development system. TB9654/8A To User_VCC On Idle Stop + + GND U2 RESET VCC Off 100-Pin Connector 25 1 J101 1 20 20-Pin Socket 144 QFP S3E9600X EVA Chip 1 36 External Triggers CH1 CH2 SMDS2 SMDS2+ 10 11 SW1 SM1330A Figure 18-2. TB9654/8A Target Board Configuration 18-3 DEVELOPMENT TOOLS S3C9654/C9658/P9658 Table 18-1. Power Selection Settings for TB9654/8A 'To User_Vcc' Settings Operating Mode Comments To User_VCC Off On TB9654/8A Target System VCC SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. VSS VCC SMDS2/SMDS2+ To User_VCC Off On TB9654/8A External VCC Target System VSS SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have a power supply of its own. VCC SMDS2+ SMDS2+ Selection (SAM8) In order to write data into program memory available in SMDS2+, the target board should be selected for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 18-2. The SMDS2+ Tool Selection Setting 'SW1' Setting SMDS2 18-4 SMDS2+ Operating Mode R/W* SMDS2+ R/W* Target Board S3C9654/C9658/P9658 DEVELOPMENT TOOLS Table 18-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from External Trigger Sources of the Application System External Triggers CH1 CH2 You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. J101 P0.2/INT0 VSS P0.0/INT0 P1.0/COM0/INT1 P1.1/COM1/INT1 P1.2/COM2/INT1 P1.3/COM3/INT1 P1.4/COM4/INT1 P1.5/COM5/INT1 (note) P0.4/INT0 1 2 3 4 5 6 7 8 9 10 NOTE: 20-Pin SOP/DIP Socket (note) 20 19 18 17 16 15 14 13 12 11 P0.3/INT0 (note) VDD P2.0/D-/INT2 P2.1/D+/INT2 RESET XIN XOUT TEST P0.1/INT0 P0.5/INT0 (note) 16, 18, and 20 SOP/DIP. Figure 18-3. 20-Pin Socket for TB9654/8A 18-5 DEVELOPMENT TOOLS S3C9654/C9658/P9658 Target Board Target System 20-Pin SOP/DIP Socket J101 1 20 1 20 10 11 Part Name: AS20D Order Code: SM6304 10 11 Figure 18-4. TB9654/8A Adapter Cable for 20-SOP/DIP Package 18-6