SMD 14 Pin J-Lead 5 Tap High Speed CMOS (HCT) Compatible Active Delay Lines Tap Delays Total Delay Part +5% or+2 nS +5% or +2 nS Number 12 17 22 27 32 EPA505-32 12* 18 24 30 36 EPAS505-36 12" 19 26 33 40 EPA505-40 12* 20 28 36 44 EPA505-44 12* 21 30 39 48 EPA505-48 12" 22 32 42 52 EPA505-52 12 24 36 48 60 EPA505-60 15 30 45 60 75 EPAS05-75 20 40 60 80 100 EPAS05-100 "Inherent Delay + Delay times referenced from input to leading edges at 25C, 5.0V. DC Electrical Characteristics Schematic arameter Test Conditions Min) Max | Unit 14 vec Vi} | High Level Input Voltage Voc=4.5 to5.5 2.0 Volt Vit | Low Level Input Voltage Vega 5 to 5.5 0.8 | Volt we we 8 VoH| High Level Output Voltage | Vog=4.5V,I9=-4.0mA@Viy or Vi, | 4.0 Volt VoL | Low Level Output Voltage | Voc=4.5V,IG= 4.0mA@Vjp oF Vip_ 0.3 | Volt IL Input Leakage Current Voc=5.5V Vin orVit 1.0 uA 1 loc | Supply Current Voc=5.5V,Vin=0 15 mA RO| Output Rise Time .75 - 2.4 Volts 4 ns 7 Ground Ny | High Fanout Voc=5.5V,Voy=4.0V 10 LSTTL Load Recommended Package Dimensions Operating Conditions Min | Max! Unit ovoxae, 14 12 10 8 Be 0 Voc| DC Supply Voltage 45] 55 | Volt PCA 7 | Vi__| DC Input Voltage Range 0 | Voc] Volt EPASOS-32 | GRR 255 ays Vo | DC Output Voltage Range 0 | Vee} Volt Date Code | lo DC Output Source/Sink Current 25 mA ~ Py+| Pulse Width % of Total Delay 40 % 1 4 67 03 Ds Duty Cycle 40 % SUGGESTED SOLDERPAD LAYOUT Ta Operating Free Air Temperature 0 70 C 450 MAX . $8 vo max These two values are inter-dependent. t st hand Nd ae x 008 He tT Input Pulse Test Conditions @ 25C (Taps Unloaded) KOVAA Ein | Pulse Input Voltage 3.2 Volts Pw | Pulse Width % of Total Delay 150% 16799 SCHOENBORN ST. TR} | Input Rise Time (0.75 - 2.4 Volts) 2.0nS SEPULVEDA, CA 91343 Prr | Pulse Repetition Rate 1.0 MHz TEL: (818) 892-0761 FAX: (818) 894-5791 Voc | Supply Voltage 5.0 Volts cA TWX: (910) 496-1525 ELECTRONICS INC.