18-Bit Registered Transceivers
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
•V
CC = 2.7V to 3.6V
CY74FCT163501 Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 3.3V,
TA= 25˚C
CY74FCT163H501 Features:
• Bus hold retains the last active state
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
GND
Functional Block Diagram; CY74FCT163501, CY74FCT163H501 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
OEAB
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
LEAB
A1
GND
GND
VCC
GND
GND
FCT163501-1
A2
A3
A4
A5
A6
A7
A8
A9
GND
25
26
27
28
GND
A10
A11
A12
VCC
A13
A14
A15
A16
A17
A18
OEBA
LEBA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
B13
B14
B15
VCC
B16
B17
B18
CLKBA
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
D
C
D
C
D
A1B1
C
D
TO 17 OTHER CHANNELS
FCT163501-2
CY74FCT163501
CY74FCT163H501
2
Maximum Ratings[6, 7]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .....................................−55°C to +125°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
1. On the 74FCT163H501 these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operationbeyondthelimitssetforthmayimpairtheusefullifeofthedevice.Unlessotherwisenoted,theselimitsareoverthe operatingfree-air temperaturerange.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
Pin Description
Name Description
OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
A A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
B B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Function Table[2, 3]
Inputs Outputs
OEAB LEAB CLKAB A B
L X X X Z
H H X L L
H H X H H
H L L L
H L H H
H L L X B[4]
H L H X B[5]
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 2.7V to 3.6V
CY74FCT163501
CY74FCT163H501
3
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC = 2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.[8] Max. Unit
VIH Input HIGH Voltage All Inputs 2.0 5.5 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[9] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
IIH Input HIGH Current VCC=Max., VI=5.5 ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=5.5V ±1µA
IOZL High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=GND ±1µA
IOS Short Circuit Current[10] VCC=Max., VOUT=GND –60 –135 –240 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA
ICC Quiescent Power Supply Current VIN≤0.2V,
VIN>VCC–0.2V VCC=Max. 0.1 10 µA
∆ICC Quiescent Power Supply Current
(TTL inputs HIGH) VIN=VCC–0.6V[11] VCC=Max. 2.0 30 µA
Notes:
8. Typical values are at VCC=3.3V, TA = +25˚C ambient.
9. This parameter is specified but not tested.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
CY74FCT163501
CY74FCT163H501
4
Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.[8] Max. Unit
VIH Input HIGH Voltage All Inputs 2.0 VCC V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[9] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±100 µA
IIL Input LOW Current VCC=Max., VI=GND ±100 µA
IBBH
IBBL Bus Hold Sustain Current on Bus Hold Input[12] VCC=Min. VI=2.0V –50 µA
VI=0.8V +50 µA
IBHHO
IBHLO BusHoldOverdriveCurrentonBusHoldInput[12] VCC=Max., VI=1.5V ±500 µA
IOZH High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=VCC ±1µA
IOZL High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=GND ±1µA
IOS Short Circuit Current[10] VCC=Max., VOUT=GND –60 –135 –240 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA
ICC Quiescent Power Supply Current VIN≤0.2V,
VIN>VCC–0.2V VCC=Max. +40 µA
∆ICC Quiescent Power supply Current
(TTL inputs HIGH) VIN=VCC–0.6V[11] VCC=Max. +350 µA
Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.[8] Max. Unit
IODL Output LOW Dynamic Current[10] VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V 45 180 mA
IODH Output HIGH Dynamic Current[10] VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V –45 –180 mA
VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V
VCC=3.0V, IOH= –8 mA 2.4[13] 3.0 V
VCC=3.0V, IOH= –24 mA 2.0 3.0 V
VOL Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V
VCC=Min., IOL= 24 mA 0.3 0.55
Capacitance[9](TA = +25˚C, f = 1.0 MHz)
Parameter Description Test Conditions Typ.[8] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Notes:
12. Pins with bus hold are described in Pin Description.
13. VOH=VCC – 0.6V at rated current.
CY74FCT163501
CY74FCT163H501
5
Power Supply Characteristics
Sym. Parameter Test Conditions[14] Min. Typ.[8] Max. Unit
ICCD Dynamic Power Supply
Current[15] VCC=Max., Outputs Open
OEAB=OEBA=VCC or GND
One Input Toggling,
50% Duty Cycle
VIN=VCC or
VIN=GND — 75 120 µA/
MHz
ICTotal Power Supply
Current[16] VCC=Max., Outputs Open
f0 =10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB = GND, One Bit Toggling
f1 = 5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND — 0.8 1.7 mA
VIN=3.4V or
VIN=GND — 1.3 3.2
VCC=Max., Outputs Open
f0 = 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB=GND
Eighteen Bits Toggling
f1=2.5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND — 3.8 6.5[17]
VIN=3.4V or
VIN=GND — 8.5 20.8[17]
Notes:
14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
15. This parameter is not directly testable, but is derived for use in Total Power Supply Current.
16. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY74FCT163501
CY74FCT163H501
6
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[18]
CY74FCT163501C
CY74FCT163H501C
Fig.No.[19]
Parameter Description Min. Max. Unit
fMAX CLKAB or CLKBA frequency[9] — 150 MHz —
tPLH
tPHL Propagation Delay
A to B or B to A 1.5 4.6 ns 1,3
tPLH
tPHL Propagation Delay
LEBA to A, LEAB to B 1.5 5.3 ns 1,5
tPLH
tPHL Propagation Delay
CLKBA to A,
CLKAB to B
1.5 5.3 ns 1,5
tPZH
tPZL Output Enable Time
OEBA to A, OEAB to B 1.5 5.6 ns 1,7,8
tPHZ
tPLZ Output Disable Time
OEBA to A, OEAB to B 1.5 5.2 ns 1,7,8
tSU Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
3.0 — ns 4
tHHold Time
HIGH or LOW
A to CLKAB,
B to CLKBA
0 — ns 4
tSU Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Clock LOW 3.0 — ns 4
Clock HIGH 1.5 — ns 4
tHHold Time, HIGH or LOW, A to LEAB,
B to LEBA 1.5 — ns 4
tWLEAB or LEBA Pulse Width HIGH[9] 3.0 — ns 5
tWCLKAB or CLKBA Pulse Width HIGH or LOW[9] 3.0 — ns 5
tSK(O) Output Skew[20] — 0.5 ns —
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
CY74FCT163501
CY74FCT163H501
7
Ordering Information CY74FCT163501T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.6 CY74FCT163501CPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT163501CPVC/PVCT O56 56-Lead (300-Mil) SSOP
Ordering Information CY74FCT163H501T
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.6 74FCT163H501CPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT163H501CPVC O56 56-Lead (300-Mil) SSOP
74FCT163H501CPVCT O56 56-Lead (300-Mil) SSOP
Package Diagrams
56-Lead Shrunk Small Outline Package O56
CY74FCT163501
CY74FCT163H501
8
Package Diagrams (continued)
56-Lead Thin Shrunk Small Outline Package Z56
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74FCT163H501CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
74FCT163H501CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI
CY74FCT163501CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
CY74FCT163501CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
CY74FCT163501CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI
CY74FCT163501CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI
CY74FCT163H501CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI
CY74FCT163H501CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2005
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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