REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R410-97 97-08-11 Monica L. Poelking B Add Radiation Hardness Assurance limits. Editorial changes throughout. - jak 98-04-20 Monica L. Poelking C Add device type 02. Add case outlines X and Z. Add radiation features to device type 01. Add Vendor CAGE Code F8859. Update boilerplate to MIL-PRF-38535 requirements. - LTG 02-07-18 Thomas M. Hess D Change lead temperature for case outline X in 1.3. Add radiation features to 1.5 for device type 02. Update the boilerplate to include radiation hardness assured requirements for device type 02. Editorial changes throughout. - jak 04-12-01 Thomas M. Hess REV SHEET REV C B B B B B D D D D SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby STANDARD MICROCIRCUIT DRAWING APPROVED BY Monica L. Poelking THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Thomas J. Ricciuti MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 4-BIT PRESETTABLE BINARY COUNTER, ASYNCHRONOUS RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 92-12-23 REVISION LEVEL D AMSC N/A DSCC FORM 2233 APR 97 SIZE CAGE CODE A 67268 SHEET 1 OF 5962-91722 24 5962-E364-04 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example. 5962 F 91722 Federal stock class designator \ RHA designator (see 1.2.1) 01 Device type (see 1.2.2) / V E A Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 1/ 54ACT161 4-bit presettable binary counter, asynchronous reset, TTL compatible inputs 02 54ACT161 4-bit presettable binary counter, asynchronous reset, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class M Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter E F X Z 2 Descriptive designator GDIP1-T16 or CDIP2-T16 GDFP2-F16 or CDFP3-F16 CDFP4-F16 GDFP1-G16 CQCC1-N20 Terminals 16 16 16 16 20 Package style Dual-in-line Flat pack Flat pack Flat pack with gullwing Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Due to internal noise problems, device type 01 does not meet the minimum VIH threshold limit that is characteristic of this technology family. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 2 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc Input voltage range ............................................................................................. -0.5 V dc to VCC + 0.5 V dc 2/ Output voltage range .......................................................................................... -0.5 V dc to VCC + 0.5 V dc 2/ DC input diode current (IIK) (-0.5 V VIN VCC + 0.5 V) ..................................... 20 mA DC output diode current (IOK) (-0.5 V VOUT VCC + 0.5 V) ................................ 20 mA DC output current (IOUT) (per output pin) .............................................................. 50 mA DC VCC or GND current (ICC, IGND) (per pin) ........................................................ 250 mA 3/ Maximum power dissipation (PD) ........................................................................ 500 mW Storage temperature range (TSTG) ....................................................................... -65C to +150C Lead temperature (soldering, 10 seconds): Case outline X.................................................................................................... +260C All other case outlines except case X ................................................................ +300C Thermal resistance, junction-to-case (JC) .......................................................... See MIL-STD-1835 Junction temperature (TJ) .................................................................................... +175C 4/ 1.4 Recommended operating conditions. 2/ 5/ Supply voltage range (VCC) .................................................................................. +4.5 V dc to +5.5 V dc Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC Maximum low level input voltage (VIL).................................................................. 0.8 V dc Minimum high level input voltage (VIH): Device type 01 .................................................................................................. 3.0 V dc 6/ Device type 02 .................................................................................................. 2.0 V dc Case operating temperature range (TC) ............................................................... -55C to +125C Input edge rate (v/t) maximum (from VIN = 0.8 V to 2.0 V, 2.0 V to 0.8 V) ......................................................... 125 mV/ns Maximum high level output current (IOH) ............................................................. -24 mA Maximum low level output current (IOL) ............................................................... +24 mA 3.2 Radiation features. Device type 01: Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) ...................... 100 Krads (Si) Single Event Latch-up (SEL) ............................................................................. 100 MeV-cm2/mg Device type 02: Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) ...................... 300 krads (Si) Single Event Latchup (SEL) or Single Event Upset (SEU) ................................ 93 MeV-cm2/mg 1/ 2/ 3/ 4/ 5/ 6/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Unless otherwise noted, all voltages are referenced to GND. For packages with multiple VCC and GND pins, this value represents the maximum total current flowing into or out of all VCC and GND pins. Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Unless otherwise specified, the values listed above shall apply over the full VCC and TC recommended operating range. For dynamic operation, a VIH level between 2.0 and 3.0 V may be recognized by this device as a high logic level input. For static operation, a VIH 2.0 V will be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) EIA/JEDEC Standard No. 78 - IC Latch-Up Test JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available on line at http://www/jedec.org or from Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 4 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. Test conditions for these specified characteristics and limits are as specified in table I. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 40 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 5 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 6 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Symbol Positive input clamp voltage 3022 VIC+ Negative input clamp voltage 3022 VIC- High level output voltage 3006 VOH Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified For input under test, IIN = 1.0 mA 5/ 6/ M, D, P, L, R For input under test, IIN = -1.0 mA 5/ 6/ 5/ 6/ 7/ M, D, P, L, R For all inputs affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 For all other inputs, VIN = VCC or GND M, D, P, L, R IOH = -50 A For all inputs affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 For all other inputs, M, D, P, L, R VIN = VCC or GND IOH = -24 mA Low level output voltage 3007 VOL 5/ 6/ 7/ For all inputs affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 M, D, P, L, R For all other inputs, VIN = VCC or GND IOH = -50 mA 8/ For all inputs affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 For all other inputs, VIN = VCC or GND M, D, P, L, R IOL = 50 A For all inputs affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 For all other inputs, M, D, P, L, R VIN = VCC or GND IOL = 24 mA Device type and device class All Q, V 01 V All Q, V 01 V All All All All 01 All All All VCC Group A subgroups Limits 4/ Min Max 0.0 V 1 0.4 1.5 0.0 V 1 0.4 1.5 Open 1 -0.4 -1.5 Open 1 -0.4 -1.5 4.5 V 1, 2, 3 4.4 5.5 V 1 5.4 4.5 V 1, 2, 3 3.7 4.5 V 1 3.7 5.5 V 1, 2, 3 4.7 5.5 V 1, 2, 3 3.85 01 All 5.5 V 1 3.85 All All 4.5 V 1, 2, 3 All All 01 All All M 5.5 V 01 All All M All Q, V All Q, V 0.1 V 0.1 1 0.1 4.5 V 1 0.4 2, 3 0.5 4.5 V 1 0.4 5.5 V 1 2, 3 1, 3 2 1, 3 2 0.4 0.5 0.4 0.5 0.4 0.5 5.5 V V V 5.5 V 4.5 V V 5.4 5.5 V 01 All All All All All Unit See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Low level output voltage 3007 Input capacitance 3012 Power dissipation capacitance Quiescent supply current delta, TTL input levels 3005 Symbol VOL 5/ 6/ 7/ CIN CPD 9/ ICC 5/ 6/ 10/ Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified For all inputs, affecting output under test, VIN = 3.0 V or 0.8 V device 01 VIN = 2.0 V or 0.8 V device 02 For all other inputs, VIN = VCC or GND IOL = 50 mA 8/ M, D, P, L, R See 4.4.1c TC = +25C See 4.4.1c TC = +25C, f = 1 MHz For input under test, VIN = VCC - 2.1 V For all other inputs, VIN = VCC or GND ICCH For all inputs, VIN = VCC or GND VCC ICCL For all inputs, VIN = VCC or GND Limits 4/ Unit Max 5.5 V 1, 2, 3 1.65 5.5 V 1 1.65 GND 4 10.0 5.0 V 4 50 5.5 V 3 1.6 1, 2 1, 2, 3 1.0 1.6 5.5 V 1, 2, 3 1.6 5.5 V 1 5.5 V 1 1.6 3.5 2.0 2 40.0 V pF mA A All M 5.5 V 1 8.0 01 All 5.5 V 2, 3 1 mA 02 Q, V All Q, V 5.5 V 1 160.0 100.0 1.0 3.5 50.0 5.5 V 1 2.0 A 2 40.0 5/ 6/ M D P, L, R M, D, P, L, R, F 11/ Group A subgroups Min 5/ 6/ M D P, L, R M, D, P, L, R, F 11/ Quiescent supply current outputs low 3005 01 All All All All All 01 Q, V 02 Q, V All M 01 All All Q, V M, D P, L, R Quiescent supply current outputs high 3005 Device type and device class All All All M 5.5 V 1 8.0 01 All 5.5 V 2, 3 1 02 Q, V 5.5 V 160.0 100.0 1.0 3.5 50.0 1 A mA A See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Input leakage current high 3010 Symbol IIH 5/ 6/ Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified For input under test, VIN = VCC For all other inputs, VIN = VCC or GND Device type and device class All Q, V All M M, D, P, L, R Input leakage current low 3009 IIL 5/ 6/ For input under test, VIN = GND For all other inputs, VIN = VCC or GND 01 All All Q, V All M M, D, P, L, R Low level ground bounce noise VGBL 12/ High level ground bounce noise VGBH 12/ Latch-up input/output over-voltage ICC (O/V1) 13/ Latch-up input/output positive overcurrent ICC (O/I1+) 13/ Latch-up input/output negative overcurrent ICC (O/I1-) 13/ Latch-up supply over-voltage ICC (O/V2) 13/ VLD = 2.5 V IOL = +24 mA See figure 5 VLD = 2.5 V IOH = -24 mA See figure 5 tw 100 s, tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 10.5 V tw 100 s, tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = +120 mA tw 100 s, tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = -120 Ma tw 100 s, tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 9.0 V VCC Group A subgroups Limits 4/ Min 5.5 V Max 1 0.1 2 1.0 1 0.1 2, 3 1.0 5.5 V 1 0.1 5.5 V 1 -0.1 2 -1.0 1 -0.1 2, 3 -1.0 5.5 V 5.5 V Unit A A 01 All All Q, V 5.5 V 1 -0.1 4.5 V 4 1500 mV All Q, V 4.5 V 4 1500 mV All Q, V 5.5 V 2 200 mA All Q, V 5.5 V 2 200 mA All Q, V 5.5 V 2 200 mA All Q, V 5.5 V 2 100 mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Functional tests 3014 Propagation delay time, CP to Qn (count mode) 3003 Symbol 5/ 6/ 14/ tPHL1, tPLH1 5/ 6/ 15/ Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device 01-VIL = 0.4 V, VIH = 3.0 V Device 02-VIL = 0.8 V, VIH = 2.0 V M, D, P, L, R Verify output VOUT See 4.4.1d CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R Propagation delay time, CP to Qn (load mode) 3003 Propagation delay time, CP to TC 3003 Propagation delay time, CET to TC 3003 tPHL2, tPLH2 5/ 6/ 15/ tPHL3, tPLH3 5/ 6/ 15/ tPHL4, tPLH4 5/ 6/ 15/ CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R Device type and Device class All All 01 All All M All M 01 All All Q, V All Q, V All M 01 All All Q, V All Q, V All M 01 All All Q, V All Q, V All M 01 All All Q, V All Q, V VCC Group A subgroups Limits 4/ Unit Min Max 7, 8 L H 7 L H 5.5 V 7, 8 L H 4.5 V 9 1.0 9.5 10, 11 1.0 10.5 9 1.0 9.5 9, 11 1.0 9.5 10 1.0 10.5 9 1.0 8.5 10, 11 1.0 10.0 9 1.0 8.5 9, 11 1.0 8.5 10 1.0 10.0 9 1.0 12.0 10, 11 1.0 14.0 9 1.0 12.0 9, 11 1.0 12.0 10 1.0 14.0 9 1.0 8.5 10, 11 1.0 9.5 9 1.0 8.5 9, 11 1.0 8.5 10 1.0 9.5 4.5 V 4.5 V 4.5 V 4.5 V ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 10 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Symbol Propagation delay time, MR to Qn tPHL5 3003 5/ 6/ 15/ Propagation delay time, MR to TC 3003 Maximum clock frequency Input setup time, high or low, PE to CP Input setup time, high or low, Pn to CP tPHL6 5/ 6/ 15/ fMAX 16/ ts1 16/ ts2 16/ Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R CL = 50 pF minimum RL = 500 See figure 6 M, D, P, L, R CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 Device type and device class All M 01 All All Q, V All Q, V All M 01 All All Q, V All Q, V All All All M All M All Q, V All Q, V All M All M All Q, V All Q, V VCC 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V Group A subgroups Limits 4/ Unit Min Max 9 1.0 8.5 10, 11 1.0 10.0 9 1.0 8.5 9, 11 1.0 8.5 10 1.0 10.0 9 1.0 10.0 10, 11 1.0 11.5 9 1.0 10.0 9, 11 1.0 10.0 10 1.0 11.5 9 95 10, 11 85 9 8.5 10, 11 11.0 9, 11 8.5 10 11.0 9 9.5 10, 11 13.0 9, 11 9.5 10 13.0 ns ns MHz ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 11 TABLE I. Electrical performance characteristics - Continued. Test and ML-STD-883 test method 1/ Input setup time, high or low, CEP, CET to CP Input hold time, high or low, PE to CP Input hold time, high or low, Pn to CP Input hold time, high or low, CEP, CET to CP Clock pulse width, high or low, (count and load modes) MR pulse width low Recovery time, MR to CP Symbol ts3 16/ th1 16/ th2 16/ th3 16/ tw1 16/ tw2 16/ trec 16/ Test conditions 2/ 3/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 CL = 50 pF minimum RL = 500 See figure 6 Device type and device class All M All M All Q, V All Q, V All All VCC Group A subgroups Limits 4/ Min 4.5 V Unit Max 9 5.5 10, 11 7.0 9, 11 5.5 10 7.0 4.5 V 9, 10, 11 0.0 ns All All 4.5 V 9, 10, 11 0.0 ns All All 4.5 V 9, 10, 11 0.5 ns All All 4.5 V 9, 10, 11 5.0 ns All M All M All Q, V All Q, V All M All M All Q, V All Q, V 4.5 V 9 5.0 ns 10, 11 6.5 9, 11 5.0 10 6.5 9 0.0 10, 11 0.5 9, 11 0.0 10 0.5 4.5 V ns ns See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 12 TABLE I. Electrical performance characteristics - Continued. 1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure under the conditions listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits. Output terminals not designated shall be high level logic, low level logic, or open, except as follows: a. VIC (pos) tests, the GND terminal can be open. TC = +25C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25C. c. All ICC and ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. 3/ RHA parts for device type 01 are tested at all levels M, D, P, L, and R of irradiation. Pre and post irradiation values are identical unless otherwise specified in table I. RHA parts for device type 02 meet all levels M, D, P, L, R, and F of irradiation. However, these parts are only tested at the "F" level. Pre and post irradiation values are identical unless otherwise specified in table I. 4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I, as applicable, at 4.5 V VCC 5.5 V. 5/ RHA samples do not have to be tested at -55C and +125C postirradiation. 6/ When performing postirradiation electrical measurements for RHA level, TA = +25C. Limits shown are guaranteed at TA = +25C 5C. 7/ For dynamic operation, a VIH level between 2.0 V and 3.0 V may be recognized by this device as a high logic level input. For static operation, a VIH 2.0 V will be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system. 8/ Transmission driving tests are performed at VCC = 5.5 V with a 2 ms duration maximum. This test may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 3.0 V or 0.8 V for device 01 and VIN = 2.0 V or 0.8 V for device 02. 9/ Power dissipation capacitance (CPD) determines the no load power consumption, PD = (CPD + CL) (VCC x VCC) f + (ICC x VCC) + (n x d x ICC x VCC) and the dynamic current consumption, IS = (CPD + CL) VCCf + ICC + (n x d x ICC). For both PD and IS, n is the number of device inputs at TTL levels; f is the frequency of the input signal; and d is the duty cycle of the input signal. 10/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times ICC maximum limit; and the preferred method and limits are guaranteed. 11/ The maximum limit for this parameter at 100 krads (Si) is 2 A. 12/ This test is for qualification only. Ground bounce tests are performed on a nonswitching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = 24 mA, for example) and 50 pF of load capacitance (see figure 5). The loads must be located as close as possible to the device output. Inputs are then conditioned with 1 MHz pulse (tr = tf = 3.5 1.5ns) switching simultaneously and in phase such that one output is forced low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T. oscilloscope probe with at least 1 M impedance. Measurement is taken from the peak of the largest positive pulse with respect to the nominal low level output voltage (see figure 5). The device inputs are then conditioned such that the output under test is at a high nominal VOH level. The high level ground bounce measurement is then measured from nominal VOH level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a maximum number of outputs switching. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 13 TABLE I. Electrical performance characteristics - Continued. 13/ See EIA/JEDEC STD. 78 for electrically induced latch-up test methods and procedures. The values listed for Itrigger and Vover are to be accurate within 5 percent. 14/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. H 2.5 V, L < 2.5 V, VIH = 3.0 V, VIL = 0.4 V for device type 01 and VIH = 2.0 V, VIL = 0.8 V for device type 02. Allowable tolerances in accordance with MIL-STD-883 for input voltage levels may be incorporated. The VIH level used for functional testing shall be 3.0 V 0 percent for device type 01. 15/ AC limits at VCC = 5.5 V are equal to limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum AC limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths must be tested. 16/ This parameter shall be guaranteed, if not tested, to the limits in table I, herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 14 Device type Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 01, 02 E, F, X, Z 2 Terminal symbol MR CP P0 P1 P2 P3 CEP GND PE CET Q3 Q2 Q1 Q0 TC NC MR CP P0 P1 NC P2 P3 CEP GND NC PE CET Q3 Q2 NC Q1 Q0 TC VCC --------- VCC PIN Description Terminal Symbol CEP CET CP MR Pn PE Qn TC Description Count enable parallel control input Count enable trickle control input Clock pulse timing input (active rising edge) Asynchronous master reset control input (active low) Parallel data inputs (n = 0 to 3) Parallel enable control input (active low) Flip-flop outputs (n = 0 to 3) Terminal count output FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL C SHEET 15 Function MR PE CET CEP L X X X Reset (Qn = L, TC = L) (See note 1) H L X X Load (Qn = Pn) (See notes 2 and 3) H H H H Count (See notes 2, 3, and 4) H H L X No change (See notes 2, 3, and 5) H H X L No change (See notes 2, 3, and 5) H = High voltage level L = Low voltage level X = Irrelevant NOTES: 1. The reset operation occurs regardless of the input conditions of the other control inputs and timing input. 2. Action occurs on the rising edge of the clock (CP) input when the appropriate setup, hold, and pulse width timing requirements have been met in table I herein. 3. TC = H, whenever the conditions satisfy the logic equation, TC = Q0 z Q1 z Q2 z Q3 z CET are valid. For any other conditions, TC = L. The TC output will react to the CET input independent of the clock input. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers, or counters. 4. For the counting sequence, see the state diagram on figure 4. 5. Outputs maintain their current output state. For TC, the conditions in note 3 apply. FIGURE 2. Truth table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL B SHEET 16 FIGURE 3. Logic diagram. FIGURE 4. State diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL B SHEET 17 NOTE: Resistor and capacitor tolerances = 10%. FIGURE 5. Ground bounce waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL B SHEET 18 FIGURE 6. Switching waveforms and test circuit . STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL B SHEET 19 NOTES: 1. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance). 2. RT = 50 or equivalent, RL = 500 or equivalent. 3. Input signal from pulse generator: VIN = 0.0 V to 3.0V; PRR 10 MHz; tr 3.0 ns; tf 3.0 ns; duty cycle = 50 percent. 4. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 5. The outputs are measured one at a time with one transition per measurement. FIGURE 6. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL B SHEET 20 TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Subgroups (in accordance with MIL-PRF-38535, table III) Device class M Device class Q Interim electrical parameters (see 4.2) --- --- 1 Final electrical parameters (see 4.2) 1/ 1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 3/ 1, 2, 3, 7, 8, 9, 10, 11 Group A test requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 3/ 1, 2, 3, 7,8, 9, 10, 11 Group D end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 Device class V 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1, 7, and deltas. 3/ Delta limits, as specified in table III, shall be required where specified and the delta limits shall be completed with reference to the zero hour electrical parameters. TABLE III. Burn-in and operating life test, delta parameters (+25C). Parameter 1/ Supply current Symbol ICC IIL IIH VOL 100 nA 2/ 300 nA 0.4 mA 20 nA 20 nA 0.04 V VOH 02 0.20 V ICCH, ICCL Supply current delta Input current low level Input current high level Output voltage low level VCC = 5.5 V, IOL = 24 mA Output voltage high level VCC = 5.5 V, IOH = -24 mA Delta limits Device type 01 02 02 02 02 02 1/ These parameters shall be recorded before and after the required burn-in and life tests to determine delta limits. 2/ Guaranteed, if not tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 21 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Latch-up and ground bounce tests are required for device classes Q and V. These tests shall be performed only for initial qualification and after process or design changes which may affect the performance of the device. Latch-up tests shall be considered destructive. For latch-up and ground-bounce tests, test all applicable pins on five devices with zero failures. c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. For CIN and CPD, test all applicable pins on five devices with zero failures. d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. b. TA = +125C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table II herein. c. RHA tests for device classes M, Q, and V for levels M, D, P, L, R, and F shall be performed through each level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualification and after design or process changes which may affect the RHA performance of the device. d. Prior to irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified group A electrical parameters in table I for subgroups specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 22 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883, method 1019, condition A and as specified herein. Prior to and during total dose irradiation characterization and testing, the devices for characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing shall be biased to the worst case condition established during characterization. Devices shall be biased as follows: a. Device type 01: (1) Inputs tested high, VCC = 5.5 V dc +5%, RCC = 10 +20%, VIN = 5.0 V dc +5%, RIN = 1 k +20%, and all outputs are open. (2) Inputs tested low, VCC = 5.5 V dc +5%, RCC = 10 +20%, VIN = 0.0 V dc, RIN = 1 k +20%, and all outputs are open. b. Device type 02: (1) Inputs tested high, VCC = 5.5 V dc 5%, VIN = 5.0 V dc +10%, RIN = 1 k 20%, and all outputs are open. (2) Inputs tested low, VCC = 5.5 V dc 5%, VIN = 0.0 V dc, RIN = 1 k 20%, and all outputs are open. 4.4.4.1.1 Accelerated aging test. Accelerated aging shall be performed on classes M, Q, and V devices requiring an RHA level greater than 5K rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the preirradiation end-point electrical parameter limit at 25C 5C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.5 Methods of inspection. Methods of inspection shall be specified as follows: 4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 23 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-91722 A REVISION LEVEL D SHEET 24 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 04-12-01 Approved sources of supply for SMD 5962-91722 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-9172201MEA 27014 54ACT161DMQB 5962-9172201MFA 27014 54ACT161FMQB 5962-9172201M2A 27014 54ACT161LMQB 5962R9172201MEA 27014 54ACT161DMQB-RH 5962R9172201MFA 27014 54ACT161FMQB-RH 5962R9172201M2A 27014 54ACT161LMQB-RH 5962R9172201VEA 27014 54ACT161JRQMLV 5962R9172201VFA 27014 54ACT161WRQMLV 5962R9172201V2A 27014 54ACT161ERQMLV 5962R9172201VZA 27014 54ACT161WGRQMLV 5962-9172202VXA F8859 54ACT161K02V 5962-9172202VXC F8859 54ACT161K01V 5962-9172202QXA F8859 54ACT161K02Q 5962-9172202QXC F8859 54ACT161K01Q 5962F9172202VXA F8859 RHFACT161K02V 5962F9172202VXC F8859 RHFACT161K01V 5962F9172202QXA F8859 RHFACT161K02Q 5962F9172202QXC F8859 RHFACT161K01Q 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 1 of 2 STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. Vendor CAGE number Vendor name and address 27014 National Semiconductor 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 F8859 STMicroelectronics 3 rue de Suisse BP4199 35041 RENNES cedex2-FRANCE The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 2 of 2