DATA SH EET
Product specification
Supersedes data of April 1991
File under Discrete Semiconductors, SC07
1996 Aug 01
DISCRETE SEMICONDUCTORS
BF998; BF998R
Silicon N-channel dual-gate
MOS-FETs
1996 Aug 01 2
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
FEATURES
•Short channel transistor with high forward transfer
admittance to input capacitance ratio
•Low noise gain controlled amplifier up to 1 GHz.
APPLICATIONS
•VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
DESCRIPTION
Depletion type field effect transistor in a plastic
microminiature SOT143 or SOT143R package with source
and substrate interconnected. The transistors are
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
PINNING
CAUTION
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
PIN SYMBOL DESCRIPTION
1 s, b source
2 d drain
3g
2
gate 2
4g
1
gate 1
Fig.1 Simplified outline (SOT143)
and symbol; BF998.
Marking code: MOp.
handbook, halfpage
s,b
d
g1
g2
43
21
Top view
MAM039
handbook, halfpage
s,b
d
g1
g2
MAM040
34
12
Top view
Fig.2 Simplified outline (SOT143R)
and symbol; BF998R.
Marking code: MOp.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
VDS drain-source voltage −12 V
IDdrain current −30 mA
Ptot total power dissipation −200 mW
yfsforward transfer admittance 24 −mS
Cig1-s input capacitance at gate 1 2.1 −pF
Crs reverse transfer capacitance f = 1 MHz 25 −fF
F noise figure f = 800 MHz 1 −dB
Tjoperating junction temperature −150 °C
1996 Aug 01 3
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Device mounted on a ceramic substrate, 8 mm ×10 mm ×0.7 mm.
2. Device mounted on a printed-circuit board.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage −12 V
IDdrain current −30 mA
±IG1 gate 1 current −10 mA
±IG2 gate 2 current −10 mA
Ptot total power dissipation; BF998 up to Tamb =60°C; see Fig.3; note 1 −200 mW
up to Tamb =50°C; see Fig.3; note 2 −200 mW
Ptot total power dissipation; BF998R up to Tamb =50°C; see Fig.4; note 1 −200 mW
Tstg storage temperature −65 +150 °C
Tjoperating junction temperature −150 °C
Fig.3 Power derating curves; BF998.
handbook, halfpage
0
100
0 200100
200
(mW)
Ptot max (2) (1)
MLA198
Tamb ( C)
o
(1) Ceramic substrate.
(2) Printed-circuit board.
Fig.4 Power derating curve; BF998R.
handbook, halfpage
0
100
0 200100
200
(mW)
Ptot max
MGA002
Tamb (°C)
1996 Aug 01 4
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
THERMAL CHARACTERISTICS
Notes
1. Device mounted on a ceramic substrate, 8 mm ×10 mm ×0.7 mm.
2. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
Tj=25°C; unless otherwise specified.
Note
1. Measured under pulse condition.
DYNAMIC CHARACTERISTICS
Common source; Tamb =25°C; VDS =8V;V
G2-S = 4 V; ID= 10 mA.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient in free air; BF998 note 1 460 K/W
note 2 500 K/W
Rth j-a thermal resistance from junction to ambient in free air; BF998R note 1 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
±V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V
DS = 0; IG1-SS =±10 mA 6 20 V
±V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V
DS = 0; IG2-SS =±10 mA 6 20 V
−V(P)G1-S gate 1-source cut-off voltage VG2-S =4V; V
DS =8V; I
D=20µA−2.0 V
−V(P)G2-S gate 2-source cut-off voltage VG1-S = 0; VDS =8V; I
D=20µA−1.5 V
IDSS drain-source current VG2-S =4V; V
DS =8V; V
G1-S = 0; note 1 2 18 mA
±IG1-SS gate 1 cut-off current VG2-S =V
DS = 0; VG1-S =±5V −50 nA
±IG2-SS gate 2 cut-off current VG1-S =V
DS = 0; VG2-S =±5V −50 nA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfsforward transfer admittance f = 1 kHz 21 24 −mS
Cig1-s input capacitance at gate 1 f = 1 MHz −2.1 2.5 pF
Cig2-s input capacitance at gate 2 f = 1 MHz −1.2 −pF
Cos output capacitance f = 1 MHz −1.05 −pF
Crs reverse transfer capacitance f = 1 MHz −25 −fF
F noise figure f = 200 MHz; GS= 2 mS; BS=B
Sopt −0.6 −dB
f = 800 MHz; GS= 3.3 mS; BS=B
Sopt −1.0 −dB
1996 Aug 01 5
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.5 Output characteristics; typical values.
handbook, halfpage
010
24
0
8
16
4
12
20
MGE813
2468
V
DS (V)
ID
(mA) 0.4 V
0.3 V
0.2 V
0.1 V
0 V
−0.5 V
−0.4 V
−0.3 V
−0.2 V
−0.1 V
VG1-S =
VG2-S = 4 V; Tamb =25°C.
Fig.6 Transfer characteristics; typical values.
handbook, halfpage
−11
24
0
8
16
4
12
20
MGE815
0
3 V 2 V
1 V
0 V
VG2-S = 4 V
VG1 (V)
ID
(mA)
VDS = 8 V; Tamb =25°C.
Fig.7 Drain current as a function of gate 1
voltage; typical values.
handbook, halfpage
−1600 −400−800−1200 400
24
0
8
16
4
12
20
MGE814
0
max typ
min
VG1 (mV)
ID
(mA)
VDS = 8 V; VG2-S = 4 V; Tamb =25°C.
Fig.8 Forward transfer admittance as a function of
drain current; typical values.
handbook, halfpage
020
30
0
6
12
18
24
MGE811
161284 ID (mA)
0.5 V
4 V
1 V
2 V
3 V
VG2-S = 0 V
|yfs|
(mS)
VDS = 8 V; Tamb =25°C.
1996 Aug 01 6
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.9 Forward transfer admittance as a function of
gate 1 voltage; typical values.
VDS = 8 V; Tamb =25°C.
handbook, halfpage
−11
30
0
6
12
18
24
MGE812
0VG1 (V)
0 V
1 V
2 V
3 V
VG2-S = 4 V
|yfs|
(mS)
Fig.10 Output capacitance as a function of
drain-source voltage; typical values.
handbook, halfpage
414
1.5
1.0
1.1
1.2
1.3
1.4
MGE810
Cos
(pF)
6 8 10 12
VDS (V)
12 mA
10 mA
8 mA
VG2-S = 4 V; f = 1 MHz; Tamb =25°C.
Fig.11 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values.
handbook, halfpage
−2.4 −1.6 −0.8 0.8
MGE809
0
2.1
1.9
1.7
2.3
1.5
1.3
Cis
(pF)
VG1-S (V)
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb =25°C.
Fig.12 Gate 1 input capacitance as a function of
gate 2-source voltage; typical values.
handbook, halfpage
642
C
is
(pF)
−2
2.4
2.3
2.1
2.0
2.2
MBH479
0VG2−S (V)
VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb =25°C.
1996 Aug 01 7
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.13 Input admittance as a function of the
frequency; typical values.
VDS = 8 V; VG2-S = 4 V; ID= 10 mA; Tamb =25°C.
103
MGC466
102
10
10 2
1
10
10 1
yis
(mS)
f (MHz)
bis
gis
Fig.14 Reverse transfer admittance and phase as a
function of frequency; typical values.
VDS = 8 V; VG2-S = 4 V; ID= 10 mA; Tamb =25°C.
103
MGC467
102
10
103
102
10
1
yrs
103
10
10
1
2
(µS)
f (MHz)
rs
yrs
(deg)
rs
ϕ
ϕ
Fig.15 Forward transfer admittance and phase as a
function of frequency; typical values.
VDS = 8 V; VG2-S = 4 V; ID= 10 mA; Tamb =25°C.
103
MGC468
102
10
1
102
10
1
10
10
2
yfs
(mS) yfs
f (MHz)
(deg)
fs
fs
ϕ
ϕ
Fig.16 Output admittance as a function of the
frequency; typical values.
VDS = 8 V; VG2-S = 4 V; ID= 10 mA; Tamb =25°C.
103
MGC469
102
10
10 1
10
1
10 2
yos
(mS)
f (MHz)
bos
gos
1996 Aug 01 8
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
handbook, full pagewidth
MGE802
330 kΩ
1.8 kΩ
360 Ω
100 kΩ
140 kΩ
1 nF
1 nF
47 µF
20 µH
1 nF
10 pF
D2
BB405
330 kΩ
1 nF
1 nF
Vtun
output
50 Ω
output
C1
5.5 pF
50 Ω
input
VDD
VDD
Vagc
47 kΩ
1 nF
1 nF
1 nF
L2
L1
1 nF
15 pF
D1
BB405
Vtun
input
VDD = 12 V; GS= 2 mS; GL= 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL= 0.5 mS. C1 adjusted for GS= 2 mS.
Fig.17 Gain control test circuit at f = 200 MHz.
1996 Aug 01 9
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
Fig.18 Gain control test circuit at f = 800 MHz.
VDD = 12 V; GS= 3.3 mS; GL= 1 mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
handbook, full pagewidth
MGE801
1.8 kΩ360 Ω
100 kΩ
1 nF
1 nF
1 nF
50 Ω
output
1 nF
50 Ω
input
VDD
VDD
VDD Vagc
270 kΩ
140 kΩ
1 nF
1 nF
L4
L1
L2
1 nF
C1
2 to 18 pF C2
0.5 to 3.5 pF
C3
0.5 to
3.5 pF
C4
4 to 40 pF
L3
1996 Aug 01 10
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE808
∆Gtr
(dB)
2468
V
agc (V)
IDSS =
max
typ
min
Fig.19 Automatic gain control characteristics
measured in circuit of Fig.17.
VDD = 12 V; f = 200 MHz; Tamb =25°C.
handbook, halfpage
010
0
−50
−40
−30
−20
−10
MGE807
∆Gtr
(dB)
2468
V
agc (V)
IDSS =
max
typ
min
Fig.20 Automatic gain control characteristics
measured in circuit of Fig.18.
VDD = 12 V; f = 800 MHz; Tamb =25°C.
1996 Aug 01 11
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
PACKAGE OUTLINES
Fig.21 SOT143.
Dimensions in mm.
handbook, full pagewidth
MBC845
10
max
o
10
max
o
30
max
o
1.1
max
0.75
0.60
0.150
0.090
0.1
max
43
2
M0.1 AB
0
0.1
0.48
TOP VIEW
1.4
1.2 2.5
max
3.0
2.8
M
0.2 AB
A
B
1.9
1
0
0.1
0.88
1.7
handbook, full pagewidth
MBC844
10
max
o
10
max
o
30
max
o
1.1
max
0.40
0.25
0.150
0.090
0.1
max
34
2
1.4
1.2 2.5
max
3.0
2.8
A
B
1.9 M
0.2 A
1
M0.1 B
TOP VIEW
0.48
0.38 0.88
0.78
1.7
Dimensions in mm.
Fig.22 SOT143R.
1996 Aug 01 12
Philips Semiconductors Product specification
Silicon N-channel dual-gate MOS-FETs BF998; BF998R
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
