+
-
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R1 R2 R2 R1
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R3
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LMP2011 Single/LMP2012 Dual High Precision, Rail-to-Rail Output Operational Amplifier
1 Features 3 Description
The LMP201x series are the first members of TI's
1(For VS= 5 V, Typical Unless Otherwise Noted) new LMP™ precision amplifier family. The LMP201x
• Low Ensured VOS Over Temperature 60 µV series offers unprecedented accuracy and stability in
• Low Noise with No 1/f 35nV/√Hz space-saving miniature packaging, offered at an
affordable price. This device utilizes patented auto-
• High CMRR 130 dB zero techniques to measure and continually correct
• High PSRR 120 dB the input offset error voltage. The result is an
• High AVOL 130 dB amplifier which is ultra-stable over time and
temperature. It has excellent CMRR and PSRR
• Wide Gain-Bandwidth Product 3 MHz ratings, and does not exhibit the familiar 1/f voltage
• High Slew Rate 4 V/µs and current noise increase that plagues traditional
• Low Supply Current 930 µA amplifiers. The combination of the LMP201x
• Rail-to-Rail Output 30 mV characteristics makes it a good choice for transducer
amplifiers, high gain configurations, ADC buffer
• No External Capacitors Required amplifiers, DAC I-V conversion, and any other 2.7-V
to 5-V application requiring precision and long term
2 Applications stability.
• Precision Instrumentation Amplifiers Other useful benefits of the LMP201x are rail-to-rail
• Thermocouple Amplifiers output, a low supply current of 930 µA, and wide
• Strain Gauge Bridge Amplifier gain-bandwidth product of 3 MHz. These versatile
features found in the LMP201x provide high
performance and ease of use.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
LMP2011 SOT-23 (5) 2.90 mm × 1.60 mm
SOIC (8) 4.90 mm × 3.91 mm
LMP2012 VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Bridge Amplifier Offset Voltage vs Common Mode Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP2011
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LMP2012
SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
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Table of Contents
7.3 Feature Description................................................. 14
1 Features.................................................................. 17.4 Device Functional Modes........................................ 15
2 Applications ........................................................... 18 Application and Implementation ........................ 17
3 Description............................................................. 18.1 Application Information............................................ 17
4 Revision History..................................................... 28.2 Typical Applications ................................................ 17
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 20
6 Specifications......................................................... 410 Layout................................................................... 20
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 20
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 21
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 22
6.4 Thermal Information: LMP2011 ................................ 411.1 Device Support .................................................... 22
6.5 Thermal Information: LMP2012 ................................ 511.2 Documentation Support ........................................ 22
6.6 2.7-V DC Electrical Characteristics........................... 511.3 Related Links ........................................................ 22
6.7 2.7-V AC Electrical Characteristics........................... 611.4 Community Resources.......................................... 22
6.8 5-V DC Electrical Characteristics.............................. 711.5 Trademarks........................................................... 22
6.9 5-V AC Electrical Characteristics.............................. 811.6 Electrostatic Discharge Caution............................ 22
6.10 Typical Characteristics............................................ 911.7 Glossary................................................................ 23
7 Detailed Description............................................ 14 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................. 14 Information........................................................... 23
7.2 Functional Block Diagram....................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (March 2013) to Revision L Page
• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description
section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
Changes from Revision J (March 2013) to Revision K Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 19
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V+
1
2
3
4 5
6
7
8
N/C
VIN-
VIN+
V-
N/C
VOUT
N/C
-
+
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5 Pin Configuration and Functions
DBV Package D Package
5-Pin SOT-23 Single 8-Pin Single SOIC
Top View Top View
Pin Functions: LMP2011
PIN
NO. I/O DESCRIPTION
NAME DBV D
-IN 4 3 O Inverting input
+IN 3 2 I Non-Inverting input
N/C - 1 - No Internal Connection
N/C - 5 - No Internal Connection
N/C - 8 - No Internal Connection
OUT 1 6 I Output
V- 2 4 P Negative (lowest) power supply
V+ 5 7 P Positive (highest) power supply
D or DGK Package
8-Pin Dual SOIC and VSSOP
Top View
Pin Functions: LMP2012
PIN
NO. I/O DESCRIPTION
NAME D, DGK
–IN A 2 I Inverting input, channel A
+IN A 3 I Non-Inverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Non-Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 P Negative (lowest) power supply
V+ 8 P Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)
MIN MAX UNIT
Supply Voltage 5.8 V
Common-Mode Input Voltage (V-) - 0.3 (V+) + 0.3 V
Lead Temperature (soldering 10 sec.) 300 °C
Differential Input Voltage ±Supply Voltage
Current at Input Pin 30 30 mA
Current at Output Pin 30 30 mA
Current at Power Supply Pin 50 30 mA
Storage Temperature −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical
Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
Supply Voltage 2.7 5.25 V
Operating Temperature Range −40 125 °C
6.4 Thermal Information: LMP2011 LMP2011
THERMAL METRIC(1) D (SOIC) DBV (SOT-23) UNIT
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 119 164 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66 116 °C/W
RθJB Junction-to-board thermal resistance 60 28 °C/W
ψJT Junction-to-top characterization parameter 17 13 °C/W
ψJB Junction-to-board characterization parameter 59 27 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Thermal Information: LMP2012 LMP2012
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 110 157 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50 51 °C/W
RθJB Junction-to-board thermal resistance 52 77 °C/W
ψJT Junction-to-top characterization parameter 8 5 °C/W
ψJB Junction-to-board characterization parameter 51 75 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 2.7-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7 V, V−= 0 V, V CM = 1.35 V, VO= 1.35 V, and RL> 1 MΩ.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
TJ= 25°C 0.8 25
Input Offset Voltage
(LMP2011 only) The temperature extremes 60 μV
TJ= 25°C 0.8 36
Input Offset Voltage
VOS (LMP2012 only) The temperature extremes 60
TJ= 25°C 0.5 10
Offset Calibration Time ms
The temperature extremes 12
Input Offset Voltage 0.015 μV/°C
TCVOS Long-Term Offset Drift 0.006 μV/month
Lifetime VOS Drift 2.5 μV
IIN Input Current -3 pA
IOS Input Offset Current 6 pA
Input Differential 9
RIND MΩ
Resistance TJ= 25°C 95 130
Common Mode Rejection −0.3 ≤VCM ≤0.9 V,
CMRR dB
The temperature 90
Ratio 0 ≤VCM ≤0.9 V extremes
TJ= 25°C 95 120
Power Supply Rejection
PSRR dB
Ratio The temperature extremes 90
TJ= 25°C 95 130
RL= 10 kΩThe temperature 90
extremes
AVOL Open Loop Voltage Gain dB
TJ= 25°C 90 124
RL= 2 kΩThe temperature 85
extremes
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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2.7-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7 V, V−= 0 V, V CM = 1.35 V, VO= 1.35 V, and RL> 1 MΩ.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
TJ= 25°C 2.665 2.68
The temperature 2.655
extremes
RL= 10 kΩto 1.35 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.033 0.060
The temperature 0.075
extremes
Output Swing
(LMP2011 only) TJ= 25°C 2.630 2.65
The temperature 2.615
extremes
RL= 2 kΩto 1.35 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.061 0.085
The temperature 0.105
extremes
VOTJ= 25°C 2.64 2.68
The temperature 2.63
extremes
RL= 10 kΩto 1.35 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.033 0.060
The temperature 0.075
extremes
Output Swing
(LMP2012 only) TJ= 25°C 2.615 2.65
The temperature 2.6
extremes
RL= 2 kΩto 1.35 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.061 0.085
The temperature 0.105
extremes
TJ= 25°C 5 12
Sourcing, VO= 0 V, The temperature 3
VIN(diff) = ±0.5 V extremes
IOOutput Current mA
TJ= 25°C 5 18
VIN(diff) = ±0.5 V, The temperature 3
Sinking, VO= 5 V extremes
TJ= 25°C 0.919 1.20
Supply Current per
ISmA
Channel The temperature extremes 1.50
6.7 2.7-V AC Electrical Characteristics
TJ= 25°C, V+= 2.7 V, V−= 0 V, VCM = 1.35 V, VO= 1.35 V, and RL> 1 MΩ.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
GBW Gain-Bandwidth Product 3 MHz
SR Slew Rate 4 V/μs
θmPhase Margin 60 Deg
GmGain Margin −14 dB
enInput-Referred Voltage Noise 35 nV/√Hz
enp-p Input-Referred Voltage Noise RS= 100 Ω, DC to 10 Hz 850 nVpp
trec Input Overload Recovery Time 50 ms
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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6.8 5-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5 V, V−= 0 V, V CM = 2.5 V, VO= 2.5 V, and RL> 1MΩ.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
TJ= 25°C 0.12 25
Input Offset Voltage
(LMP2011 only) The temperature extremes 60 μV
TJ= 25°C 0.12 36
Input Offset Voltage
VOS (LMP2012 only) The temperature extremes 60
TJ= 25°C 0.5 10
Offset Calibration Time ms
The temperature extremes 12
Input Offset Voltage 0.015 μV/°C
TCVOS Long-Term Offset Drift 0.006 μV/month
Lifetime VOS Drift 2.5 μV
IIN Input Current -3 pA
IOS Input Offset Current 6 pA
Input Differential 9
RIND MΩ
Resistance TJ= 25°C 100 130
Common Mode −0.3 ≤VCM ≤3.2,
CMRR dB
Rejection Ratio 0 ≤VCM ≤3.2 The temperature extremes 90
TJ= 25°C 95 120
Power Supply Rejection
PSRR dB
Ratio The temperature extremes 90
TJ= 25°C 105 130
RL= 10 kΩThe temperature extremes 100
Open Loop Voltage
AVOL dB
Gain TJ= 25°C 95 132
RL= 2 kΩThe temperature extremes 90
TJ= 25°C 4.96 4.978
The temperature extremes 4.95
RL= 10 kΩto 2.5 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.040 0.070
The temperature extremes 0.085
Output Swing
(LMP2011 only) TJ= 25°C 4.895 4.919
The temperature extremes 4.875
RL= 2 kΩto 2.5 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.091 0.115
The temperature extremes 0.140
VOTJ= 25°C 4.92 4.978
The temperature extremes 4.91
RL= 10 kΩto 2.5 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.040 0.080
The temperature extremes 0.095
Output Swing
(LMP2012 only) TJ= 25°C 4.875 4.919
The temperature extremes 4.855
RL= 2 kΩto 2.5 V, V
VIN(diff) = ±0.5 V TJ= 25°C 0.0.91 0.125
The temperature extremes 0.150
TJ= 25°C 8 15
Sourcing, VO= 0 V,
VIN(diff) = ±0.5 V The temperature extremes 6
IOOutput Current mA
TJ= 25°C 8 17
Sinking, VO= 5 V,
VIN(diff) = ±0.5 V The temperature extremes 6
TJ= 25°C 0.930 1.20
Supply Current per
ISmA
Channel The temperature extremes 1.50
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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6.9 5-V AC Electrical Characteristics
TJ= 25°C, V+= 5 V, V−= 0 V, VCM = 2.5 V, VO= 2.5 V, and RL> 1MΩ.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
GBW Gain-Bandwidth Product 3 MHz
SR Slew Rate 4 V/μs
θmPhase Margin 60 deg
GmGain Margin −15 dB
enInput-Referred Voltage Noise 35 nV/√Hz
enp-p Input-Referred Voltage Noise RS= 100 Ω, DC to 10 Hz 850 nVpp
trec Input Overload Recovery Time 50 ms
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(2) Typical values represent the most likely parametric norm.
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-500
-400
-300
-200
-100
0
100
200
300
400
500
BIAS CURRENT (pA)
VCM (V)
VS = 5V
0.1 100 100k
10
100
1000
10000
1k
10 1M
FREQUENCY (Hz)
10k
1
VOLTAGE NOISE (nV/ Hz)
VS = 5V
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6.10 Typical Characteristics
TA=25C, VS= 5 V unless otherwise specified.
Figure 1. Supply Current vs Supply Voltage Figure 2. Offset Voltage vs Supply Voltage
Figure 3. Offset Voltage vs Common Mode Figure 4. Offset Voltage vs Common Mode
Figure 5. Voltage Noise vs Frequency Figure 6. Input Bias Current vs Common Mode
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10 1k 100k 10M
FREQUENCY (Hz)
0
40
80
120
PSRR
(dB)
1M
10k
100
100
60
20
VS = 2.7V
VCM = 1V
POSITIVE
NEGATIVE
10 1k 100k 10M
FREQUENCY (Hz)
0
40
80
120
PSRR
(dB)
1M
10k
100
100
60
20
VS = 5V
VCM = 2.5V
POSITIVE
NEGATIVE
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
Figure 7. PSRR vs Frequency Figure 8. PSRR vs Frequency
Figure 9. Output Sourcing at 2.7 V Figure 10. Output Sourcing at 5 V
Figure 11. Output Sinking at 2.7 V Figure 12. Output Sinking at 5 V
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100 10k 10M
FREQUENCY (Hz)
-20
20
100
GAIN (dB)
1M
100k
1k
80
40
0
60
-30.0
30.0
150.0
120.0
60.0
0.0
90.0
PHASE (°)
RL = 1M
CL = < 20pF
VS = 2.7V OR 5V
VS = 5V
VS = 5V
VS = 2.7V
PHASE
GAIN
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
Figure 13. Maximum Output Swing vs Supply Voltage Figure 14. Maximum Output Swing vs Supply Voltage
Figure 15. Minimum Output Swing vs Supply Voltage Figure 16. Minimum Output Swing vs Supply Voltage
Figure 18. Open Loop Gain and Phase vs Supply Voltage
Figure 17. CMRR vs Frequency
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1k 10k 100k 1M 10M
FREQUENCY (Hz)
-20
0
20
40
60
80
100
GAIN (dB)
VS = 2.7V
VOUT = 200 mVPP
RL = >1M
CL = < 20 pF
PHASE
GAIN
-40°C
85°C
25°C
85°C
-40°C
-23
0
23
45
68
90
113
PHASE (°)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
-20
0
20
40
60
80
100
GAIN (dB)
VS = 5V
VOUT = 200 mVPP
RL = >1M
CL = < 20pF
PHASE
GAIN
85°C
25°C
85°C
-23
0
23
45
68
90
113
PHASE (°)
-40°C
-40°C
100 10k 10M
FREQUENCY (Hz)
-20
20
100
GAIN (dB)
1M
100k
1k
80
40
0
60
-30.0
30.0
150.0
120.0
60.0
0.0
90.0
PHASE (°)
10pF
500pF 10pF
500pF
VS = 2.7V, RL = >1M
CL = 10,50,200 & 500pF
PHASE
GAIN
100 10k 10M
FREQUENCY (Hz)
-20
20
100
GAIN (dB)
1M
100k
1k
80
40
0
60
10pF
10pF
500pF
500pF
VS = 5V, RL = >1M
CL = 10,50,200 & 500pF -30.0
30.0
150.0
120.0
60.0
0.0
90.0
PHASE (°)
GAIN
PHASE
100 10k 10M
FREQUENCY (Hz)
-20
20
100
GAIN (dB)
1M
100k
1k
80
40
0
60
-30.0
30.0
150.0
120.0
60.0
0.0
90.0
PHASE (°)
VS = 2.7V
CL = < 20 pF
RL = >1M & 2k
RL = >1M
RL = 2k
RL = >1M
RL = 2k
PHASE
GAIN
100 10k 10M
FREQUENCY (Hz)
-20
20
100
GAIN (dB)
1M
100k
1k
80
40
0
60
-30.0
30.0
150.0
120.0
60.0
0.0
90.0
PHASE (°)
VS = 5V
CL = < 20 pF
RL = >1M & 2k
RL = >1M
RL = 2k
RL = >1M
PHASE
GAIN
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
Figure 19. Open Loop Gain and Phase vs RLat 2.7 V Figure 20. Open Loop Gain and Phase vs RLat 5 V
Figure 22. Open Loop Gain and Phase vs CLat 5 V
Figure 21. Open Loop Gain and Phase vs CLat 2.7 V
Figure 23. Open Loop Gain and Phase vs Temperature Figure 24. Open Loop Gain and Phase vs Temperature
at 2.7 V at 5 V
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NOISE (200 nV/DIV)
1 sec/DIV
0.1 1 10
OUTPUT VOLTAGE (VPP)
0.01
0.1
1
10
THD+N (%)
MEAS FREQ = 1 KHz
MEAS BW = 22 KHz
RL = 10k
AV = +10
VS = 2.7V
VS = 5V
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Typical Characteristics (continued)
TA=25C, VS= 5 V unless otherwise specified.
Figure 26. THD+N vs Frequency
Figure 25. THD+N vs AMPL
Figure 27. 0.1 Hz −10 Hz Noise vs Time
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0.1 100 100k
10
100
1000
10000
1k
10 1M
FREQUENCY (Hz)
10k
1
VOLTAGE NOISE (nV/ Hz)
VS = 5V
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7 Detailed Description
7.1 Overview
The LMP201x series offers unprecedented accuracy and stability in space-saving miniature packaging while also
being offered at an affordable price. This device utilizes patented techniques to measure and continually correct
the input offset error voltage. The result is an amplifier which is ultra stable over time and temperature.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 How the LMP201x Works
The LMP201x uses new, patented auto-zero techniques to achieve the high DC accuracy traditionally associated
with chopper-stabilized amplifiers without the major drawbacks produced by chopping. The LMP201x
continuously monitors the input offset and corrects this error.
The conventional low-frequency chopping process produces many mixing products, both sums and differences,
between the chopping frequency and the incoming signal frequency. This mixing causes large amounts of
distortion, particularly when the signal frequency approaches the chopping frequency. Even without an incoming
signal, the chopper harmonics mix with each other to produce even more trash. If this sounds unlikely or difficult
to understand, look at the plot (Figure 28), of the output of a typical (MAX432) chopper-stabilized op amp. This is
the output when there is no incoming signal, just the amplifier in a gain of -10 with the input grounded. The
chopper is operating at about 150 Hz; the rest is mixing products. Add an input signal and the noise gets much
worse.
Compare this plot with Figure 29 of the LMP201x. This data was taken under the exact same conditions. The
auto-zero action is visible at about 30 kHz but note the absence of mixing products at other frequencies. As a
result, the LMP201x has very low distortion of 0.02% and very low mixing products.
Figure 28. The Output of a Chopper Stabilized Op Amp Figure 29. The Output of the LMP2011/LMP2012
(MAX432)
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Feature Description (continued)
7.3.2 The Benefits of LMP201x: No 1/F Noise
Using patented methods, the LMP201x eliminates the 1/f noise present in other amplifiers. This noise, which
increases as frequency decreases, is a major source of measurement error in all DC-coupled measurements.
Low-frequency noise appears as a constantly-changing signal in series with any measurement being made. As a
result, even when the measurement is made rapidly, this constantly-changing noise signal will corrupt the result.
The value of this noise signal can be surprisingly large. For example: If a conventional amplifier has a flat-band
noise level of 10 nV/√Hz and a noise corner of 10 Hz, the RMS noise at 0.001 Hz is 1 µV/√Hz. This is equivalent
to a 0.50-µV peak-to-peak error, in the frequency range 0.001 Hz to 1.0 Hz. In a circuit with a gain of 1000, this
produces a 0.50-mV peak-to-peak output error. This number of 0.001 Hz might appear unreasonably low, but
when a data acquisition system is operating for 17 minutes, it has been on long enough to include this error. In
this same time, the LMP201x will only have a 0.21-mV output error. This is smaller by 2.4×. This 1/f error gets
even larger at lower frequencies. At the extreme, many people try to reduce this error by integrating or taking
several samples of the same signal. This is also doomed to failure because the 1/f nature of this noise means
that taking longer samples just moves the measurement into lower frequencies where the noise level is even
higher.
The LMP201x eliminates this source of error. The noise level is constant with frequency so that reducing the
bandwidth reduces the errors caused by noise.
7.3.3 No External Capacitors Required
The LMP201x does not need external capacitors. This eliminates the problems caused by capacitor leakage and
dielectric absorption, which can cause delays of several seconds from turn-on until the amplifier's error has
settled.
7.3.4 Copper Leadframe
Another source of error that is rarely mentioned is the error voltage caused by the inadvertent thermocouples
created when the common Kovar type IC package lead materials are soldered to a copper printed circuit board.
These steel-based leadframe materials can produce over 35 μV/°C when soldered onto a copper trace. This can
result in thermocouple noise that is equal to the LMP201x noise when there is a temperature difference of only
0.0014°C between the lead and the board!
For this reason, the lead-frame of the LMP201x is made of copper. This results in equal and opposite junctions
which cancel this effect. The extremely small size of the SOT-23 package results in the leads being very close
together. This further reduces the probability of temperature differences and hence decreases thermal noise.
7.3.5 More Benefits
The LMP201x offers the benefits mentioned above and more. It has a rail-to-rail output and consumes only 950
µA of supply current while providing excellent DC and AC electrical performance. In DC performance, the
LMP201x achieves 130 dB of CMRR, 120 dB of PSRR, and 130 dB of open loop gain. In AC performance, the
LMP201x provides 3 MHz of gain-bandwidth product and 4 V/µs of slew rate.
7.4 Device Functional Modes
7.4.1 Input Currents
The LMP201x input currents are different than standard bipolar or CMOS input currents. Due to the auto-zero
action of the input stage, the input current appears as a pulsating current at the chopping frequency (35 kHz)
flowing in one input and out the other. Under most operating conditions, these currents are in the picoamp level
and will have little or no effect in most circuits.
These currents tend to increase slightly when the common-mode voltage is near the minus supply. (See the
Typical Characteristics.) At high temperatures such as 85°C, the input currents become larger, 0.5 nA typical,
and are both positive except when the VCM is near V−. If operation is expected at low common-mode voltages
and high temperature, do not add resistance in series with the inputs to balance the impedances. Doing this can
cause an increase in offset voltage. A small resistance such as 1 kΩcan provide some protection against very
large transients or overloads, and will not increase the offset significantly.
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Device Functional Modes (continued)
Because of these issues, the LMV201x is not recommended for source impedances over 1MΩ.
7.4.2 Overload Recovery
The LMP201x recovers from input overload much faster than most chopper-stabilized op amps. Recovery from
driving the amplifier to 2X the full scale output, only requires about 40 ms. Many chopper-stabilized amplifiers will
take from 250 ms to several seconds to recover from this same overload. This is because large capacitors are
used to store the unadjusted offset voltage.
Figure 30. Overload Recovery Test Circuit
The wide bandwidth of the LMP201x enhances performance when it is used as an amplifier to drive loads that
inject transients back into the output. ADCs (Analog-to-Digital Converters) and multiplexers are examples of this
type of load. To simulate this type of load, a pulse generator producing a 1-V peak square wave was connected
to the output through a 10-pF capacitor. (Figure 30) The typical time for the output to recover to 1% of the
applied pulse is 80 ns. To recover to 0.1% requires 860 ns. This rapid recovery is due to the wide bandwidth of
the output stage and large total GBW.
16 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: LMP2011 LMP2012
C4
0.01
PF
1N4731A
(4.3V)
D1
7
2
6
4
3
Input -15V
R6
10k
(-0.7V)
-
+
R1
R7, 3.9k
R2
C2
3
2
6
7
4
LMP201X
U1 LM6171
U2
+
-
R5, 1M
(+2.5V)
Output
C5
0.01 PF
+15V
R4
3.9k
R3
20k
D2
1N4148 C3
0.01 PF
+15V
LMP2011
,
LMP2012
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV201x family offers excellent dc precision and ac performance. These devices offer true rail-to-rail output,
ultralow offset voltage and offset voltage drift over the entire –40 to 125°C temperature range, as well as 3-MHz
bandwidth and no 1/f noise. These features make the LMV201x a robust, high performance operational amplifier
ideal for industrial applications.
8.2 Typical Applications
8.2.1 Extending Supply Voltages and Output Swing with a Composite Amplifier
Figure 31. Inverting Composite Amplifier Figure 32. Non-Inverting Composite Amplifier
8.2.1.1 Design Requirements
In cases where substantially higher output swing is required with higher supply voltages, arrangements like the
ones shown in Figure 31 and Figure 32 could be used. These configurations utilize the excellent DC performance
of the LMP201x while at the same time allow the superior voltage and frequency capabilities of the LM6171 to
set the dynamic performance of the overall amplifier.
For example, it is possible to achieve ±12-V output swing with 300 MHz of overall GBW (AV= 100) while keeping
the worst case output shift due to VOS less than 4 mV.
8.2.1.2 Detailed Design Procedure
The LMP201x output voltage is kept at about mid-point of its overall supply voltage, and its input common mode
voltage range allows the V- terminal to be grounded in one case (Figure 31, inverting operation) and tied to a
small non-critical negative bias in another (Figure 32, non-inverting operation). Higher closed-loop gains are also
possible with a corresponding reduction in realizable bandwidth. Table 1 shows some other closed loop gain
possibilities along with the measured performance in each case.
In terms of the measured output peak-to-peak noise, the following relationship holds between output noise
voltage, enp-p, for different closed-loop gain, AV, settings, where −3 dB Bandwidth is BW:
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
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+
-
+
-VOUT
5V
R1 R2 R2 R1
10k, 0.1% 2k, 1% 2k, 1% 10k, 0.1%
R3
20:
npp1 V
npp2 V
eA 1
BW1
e BW2 A 2
= ·
LMP2011
,
LMP2012
SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
www.ti.com
Typical Applications (continued)
(1)
It should be kept in mind that in order to minimize the output noise voltage for a given closed-loop gain setting,
one could minimize the overall bandwidth. As can be seen from Equation 1 above, the output noise has a
square-root relationship to the Bandwidth.
In the case of the inverting configuration, it is also possible to increase the input impedance of the overall
amplifier, by raising the value of R1, without having to increase the feed-back resistor, R2, to impractical values,
by utilizing a "Tee" network as feedback. See the LMC6442 data sheet (Application Notes section) for more
details on this.
8.2.1.3 Application Results
Table 1 shows the results using various gains and compensation values.
Table 1. Composite Amplifier Measured Performance
R1 R2 C2 BW SR en p-p
AV(Ω) (Ω) (pF) (MHz) (V/μs) (mVPP)
50 200 10k 8 3.3 178 37
100 100 10k 10 2.5 174 70
100 1k 100k 0.67 3.1 170 70
500 200 100k 1.75 1.4 96 250
1000 100 100k 2.2 0.98 64 400
8.2.2 Precision Strain-gauge Amplifier
Figure 33. Precision Strain Gauge Amplifier
This Strain-Gauge amplifier (Figure 33) provides high gain (1006 or ~60 dB) with very low offset and drift. Using
the resistors' tolerances as shown, the worst case CMRR will be greater than 108 dB. The CMRR is directly
related to the resistor mismatch. The rejection of common-mode error, at the output, is independent of the
differential gain, which is set by R3. The CMRR is further improved, if the resistor ratio matching is improved, by
specifying tighter-tolerance resistors, or by trimming.
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8.2.3 ADC Input Amplifier
Figure 34. DC Coupled ADC Driver
The LMP201x is a great choice for an amplifier stage immediately before the input of an ADC (Analog-to-Digital
Converter). See Figure 34.
This is because of the following important characteristics:
• Very low offset voltage and offset voltage drift over time and temperature allow a high closed-loop gain setting
without introducing any short-term or long-term errors. For example, when set to a closed-loop gain of 100 as
the analog input amplifier for a 12-bit A/D converter, the overall conversion error over full operation
temperature and 30 years life of the part (operating at 50°C) would be less than 5 LSBs.
• Fast large-signal settling time to 0.01% of final value (1.4 μs) allows 12 bit accuracy at 100 KHZor more
sampling rate
• No flicker (1/f) noise means unsurpassed data accuracy over any measurement period of time, no matter how
long. Consider the following op amp performance, based on a typical low-noise, high-performance
commercially-available device, for comparison:
– Op amp flatband noise = 8 nV/√Hz
– 1/f corner frequency = 100 Hz
– AV= 2000
– Measurement time = 100 sec
– Bandwidth = 2 Hz
• This example will result in about 2.2 mVPP (1.9 LSB) of output noise contribution due to the op amp alone,
compared to about 594 μVPP (less than 0.5 LSB) when that op amp is replaced with the LMP201x which has
no 1/f contribution. If the measurement time is increased from 100 seconds to 1 hour, the improvement
realized by using the LMP201x would be a factor of about 4.8 times (2.86 mVPP compared to 596 μV when
LMP201x is used) mainly because the LMP201x accuracy is not compromised by increasing the observation
time.
• Copper leadframe construction minimizes any thermocouple effects which would degrade low level/high gain
data conversion application accuracy (see discussion under The Benefits of the LMP201X section above).
• Rail-to-Rail output swing maximizes the ADC dynamic range in 5-Volt single-supply converter applications.
Below is a typical block diagram showing the LMP201x used as an ADC amplifier (Figure 34).
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9 Power Supply Recommendations
The LMP201x is specified for operation from 2.7 V to 5.25 V (±1.35 V to ±2.625 V) over a –40°C to +125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single
supply, place a capacitor between V+ and V−supply leads. For dual supplies, place one capacitor between V+
and ground, and one capacitor between V- and ground.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply
applications.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
SLOA089,Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
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10.2 Layout Example
Figure 35. Single Non-Inverting Amplifier Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMP2011/12 PSPICE Model, SNOM113
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•SBOA015 (AB-028),Feedback Plots Define Op Amp AC Performance
•SLOA089,Circuit Board Layout Techniques
•SLOD006,Op Amps for Everyone
•TIPD128,Capacitive Load Drive Solution using an Isolation Resistor
•SBOA092,Handbook of Operational Amplifier Applications
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMP2011 Click here Click here Click here Click here Click here
LMP2012 Click here Click here Click here Click here Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
LMP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNOSA71L –OCTOBER 2004–REVISED SEPTEMBER 2015
11.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMP2011MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20
11MA
LMP2011MF NRND SOT-23 DBV 5 1000 Non-RoHS &
Non-Green Call TI Call TI -40 to 125 AN1A
LMP2011MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AN1A
LMP2011MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AN1A
LMP2012MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20
12MA
LMP2012MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP20
12MA
LMP2012MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AP1A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP2011MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP2011MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP2011MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP2012MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP2012MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP2011MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP2011MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP2011MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMP2012MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP2012MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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