Rev 0; 12/08 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC The DS4432 contains two I2C programmable current DACs that are each capable of sinking and sourcing current up to 200A. Each DAC output has 127 sink and 127 source settings that are programmed using the I2C interface. The current DAC outputs power up in a high-impedance state. Features Two Current DACs Full-Scale Current 50A to 200A Full-Scale Range for Each DAC Determined by External Resistors 127 Settings Each for Sink and Source Modes Applications I2C-Compatible Serial Interface Power-Supply Adjustment Low Cost Power-Supply Margining Small Package (8-Pin SOP) Adjustable Current Sink or Source -40C to +85C Temperature Range 2.7V to 5.5V Operating Range Ordering Information Pin Configuration TOP VIEW SDA 1 SCL 2 FS1 3 GND 4 + DS4432 8 VCC 7 OUT1 6 OUT0 5 FS0 PART TEMP RANGE PIN-PACKAGE DS4432U+ -40C to +85C 8 SOP DS4432U+T&R -40C to +85C 8 SOP +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. SOP Typical Operating Circuit VCC VOUT0 VOUT1 4.7k 4.7k OUT VCC SDA SCL DC-DC CONVERTER OUT0 DS4432 R0A FB R1A FB R0B FS0 DC-DC CONVERTER OUT1 GND RFS0 OUT R1B FS1 RFS1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 DS4432 General Description DS4432 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, SDA, and SCL Relative to Ground.............................................-0.5V to +6.0V Voltage Range on FS0, FS1, OUT0, OUT1 Relative to Ground..................................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature ...............................Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40C to +85C.) PARAMETER SYMBOL Supply Voltage VCC Input Logic 1 (SDA, SCL) VIH Input Logic 0 (SDA, SCL) VIL Full-Scale Resistor Values CONDITIONS (Note 1) MIN TYP 2.7 0.7 x VCC UNITS 5.5 V VCC + 0.3 V 0.3 x VCC V -0.3 RFS0, RFS1 (Note 2) MAX 40 160 k MAX UNITS 150 A 1 A 1 A DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL CONDITIONS Supply Current ICC VCC = 5.5V (Note 3) Input Leakage (SDA, SCL) I IL VCC = 5.5V Output Leakage (SDA) IL Output Current Low (SDA) I OL RFS Voltage VRFS I/O Capacitance CI/O MIN VOL = 0.4V 3 VOL = 0.6V 6 TYP mA 0.997 V 10 pF OUTPUT CURRENT SOURCE CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL Output Voltage for Sinking Current VOUT:SINK Output Voltage for Sourcing Current Full-Scale Sink Output Current CONDITIONS (Note 4) VOUT:SOURCE (Note 4) IOUT:SINK (Notes 1, 4) Full-Scale Source Output Current IOUT:SOURCE (Notes 1, 4) Output Current Full-Scale Accuracy I OUT:FS +25C, VCC = 3.3V; using 0.1% RFS resistor, VOUT0 = V OUT1 = 1.2V (Note 2) Output Current Temperature Coefficient I OUT:TC (Note 5) 2 MIN MAX UNITS 0.5 TYP 3.5 V 0 VCC 0.75 V 50 200 A -200 -50 A 5 % 130 _______________________________________________________________________________________ ppm/C Dual-Channel, I2C, 7-Bit Sink/Source Current DAC DS4432 OUTPUT CURRENT SOURCE CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL Output Current Variation Due to Power-Supply Change Output Current Variation Due to Output-Voltage Change Output Leakage Current at Zero Current Setting CONDITIONS MIN TYP DC source, V OUT measured at 1.2V 0.41 DC sink, VOUT measured at 1.2V DC source, VCC = 3.3V 0.41 0.08 DC sink, VCC = 3.3V 0.14 I ZERO MAX UNITS %/V %/V -1 +1 A Output Current Differential Linearity DNL (Notes 6, 7) -0.5 +0.5 LSB Output Current Integral Linearity INL (Notes 7, 8) -1 +1 LSB MAX UNITS 400 kHz AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL CONDITIONS (Note 9) MIN TYP SCL Clock Frequency f SCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 s Hold Time (Repeated) START Condition tHD:STA 0.6 s Low Period of SCL tLOW 1.3 s High Period of SCL tHIGH 0.6 s Data Hold Time tHD:DAT 0 Data Setup Time t SU:DAT 100 0.9 ns START Setup Time t SU:STA 0.6 s SDA and SCL Rise Time tR (Note 10) 20 + 0.1CB 300 SDA and SCL Fall Time tF (Note 10) 20 + 0.1CB 300 STOP Setup Time t SU:STO SDA and SCL Capacitive Loading CB 0.6 (Note 10) s ns ns s 400 pF All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Input resistors (RFS) must be between the specified values to ensure the device meets its accuracy and linearity specifications. Supply current specified with all outputs set to zero current setting. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS). Note 4: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. Note 5: Temperature drift excludes drift caused by external resistor. Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 127. Note 7: Guaranteed by design. Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 10: CB--total capacitance of one bus line in pF. Note 1: Note 2: Note 3: _______________________________________________________________________________________ 3 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC DS4432 Pin Description NAME PIN SDA 1 I2C Serial Data. Input/output for I2C data. FUNCTION SCL 2 I2C Serial Clock. Input for I2C clock. FS1 3 FS0 5 Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current for each output. FS0 controls OUT0; FS1 controls OUT1. GND 4 Ground OUT0 6 OUT1 7 Current Outputs. Sinks or sources the current determined by the register settings and the resistance connected to FS0 and FS1. VCC 8 Power Supply Typical Operating Characteristics (Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25C, and no loads on OUT0, OUT1, FS0, or FS1, unless otherwise noted.) 75 50 DS4432 toc03 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0 OR FS1. 125 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 100 VOLTCO (SOURCE) -150 40k LOAD ON FS0 AND FS1. -175 100 IOUT (A) DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0 OR FS1. 125 150 DS4432 toc01 150 SUPPLY CURRENT vs. TEMPERATURE DS4432 toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE VCC = 5.5V 75 VCC = 2.7V -200 VCC = 3.3V 50 -225 25 0 0 3.5 4.0 4.5 5.0 5.5 0 20 40 60 80 2 3 4 TEMPERATURE COEFFICIENT vs. SETTING (SOURCE) TEMPERATURE COEFFICIENT vs. SETTING (SINK) 175 300 DS4432 toc05 VOLTCO (SINK) 200 RANGE FOR THE 50A TO 200A CURRENT SOURCE RANGE. 250 200 150 +25C TO -40C 100 50 0 +25C TO +85C 1.0 1.5 2.0 VOUT (V) 2.5 3.0 3.5 4.0 650 RANGE FOR THE 50A TO 200A CURRENT SINK RANGE. 550 5 450 350 250 +25C TO -40C 150 50 +25C TO +85C -50 -150 -250 -50 150 0.5 1 VOUT (V) 40k LOAD ON FS0 AND FS1. 0 0 TEMPERATURE (C) TEMPERATURE COEFFICIENT (C/ppm) IOUT (A) -20 SUPPLY VOLTAGE (V) 225 4 -250 -40 TEMPERATURE COEFFICIENT (C/ppm) 250 3.0 DS4432 toc04 2.5 DS4432 toc06 25 0 25 50 75 SETTING (DEC) 100 125 0 25 50 75 SETTING (DEC) _______________________________________________________________________________________ 100 125 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC INTEGRAL LINEARITY RANGE FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE. 0.8 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) 0.6 0 -0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 25 50 75 100 RANGE FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE. 0.8 DS4432 toc08 DIFFERENTIAL LINEARITY 1.0 DS4432 toc07 1.0 0 125 25 50 75 100 125 SETTING (DEC) SETTING (DEC) Block Diagram SDA SCL VCC I2C-COMPATIBLE SERIAL INTERFACE DS4432 VCC F8h F9h SOURCE OR SINK MODE CURRENT DAC0 GND 127 POSITIONS EACH FOR SINK AND SOURCE MODE CURRENT DAC1 FS1 FS0 RFS0 OUT0 RFS1 OUT1 _______________________________________________________________________________________ 5 DS4432 Typical Operating Characteristics (continued) (Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25C, and no loads on OUT0, OUT1, FS0, or FS1, unless otherwise noted.) DS4432 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC Detailed Description The DS4432 contains two I2C adjustable current DACs that are each capable of sinking and sourcing current. Each output (OUT0 and OUT1) has 127 sink and 127 source settings that can be controlled by the I2C interface. The full-scale ranges and corresponding step sizes of the outputs are determined by external resistors, connected to pins FS0 and FS1. The formula to determine RFS (connected to the FSx pins) to attain the desired full-scale current range is: Memory Organization To control the DS4432's current sources, write to the memory addresses listed in Table 1. Table 1. Memory Addresses MEMORY ADDRESS (HEX) CURRENT SOURCE F8h OUT0 F9h OUT1 Equation 1: RFS = VRFS x 127 16 x IFS where IFS is the desired full-scale current value, VRFS is the RFS voltage (see the DC Electrical Characteristics table), and RFS is the external resistor value. To calculate the output current value (IOUT) based on the corresponding DAC value (see Table 1 for corresponding memory addresses), use equation 2. Equation 2: IOUT = DAC Value(dec) x IFS 127 On power-up the DS4432 outputs zero current. This is done to prevent the device from sinking or sourcing an incorrect amount of current before the system host controller has had a chance to modify the DS4432's setting. As a source for biasing instrumentation or other circuits, the DS4432 provides a simple and inexpensive current DAC with an I2C interface for control. The adjustable full-scale range allows the application to get the most out of its 7-bit sink or source resolution. When used in adjustable power-supply applications (see the Typical Operating Circuit), the DS4432 does not affect the initial power-up voltage of the supply because it defaults to providing zero output current on power-up. As the device sources or sinks current into the feedback-voltage node, it changes the amount of output voltage required by the regulator to reach its steady-state operating point. Using the external resistor, RFS, to set the output current range, the DS4432 provides some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined. 6 The format of each output control register is: MSB LSB S D6 D5 D4 D3 D2 D1 D0 where: BIT NAME FUNCTION POWER-ON DEFAULT S Sign Bit Determines if DAC sources or sinks current. For sink S = 0; for source S = 1. 0b Data 7-Bit Data Controlling DAC Output. Setting 0000000b outputs zero current regardless of the state of the sign bit. 0000000b DX Example: RFS0 = 80k and register 0xF8h is written to a value of 0xAAh. Calculate the output current. IFS = (0.997V/80k) x (127/16) = 98.921A The MSB of the output register is 1, so the output is sourcing the value corresponding to position 2Ah (42 decimal). The magnitude of the output current is equal to: 98.921A x (42/127) = 32.714A I2C Serial Interface Description I2C Slave Address The DS4432's slave address is 90h. I2C Definitions The following terminology is commonly used to describe I2C data transfers: Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. _______________________________________________________________________________________ Dual-Channel, I2C, 7-Bit Sink/Source Current DAC Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 1 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 1 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a NACK by transmitting a one during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 2). An ACK is the acknowledgement that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. SDA tBUF tF tHD:STA tLOW tSP SCL tHIGH tHD:STA tHD:DAT STOP tSU:STA tR START tSU:STO tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 1. I2C Timing Diagram _______________________________________________________________________________________ 7 DS4432 Slave Devices: Slave devices send and receive data at the master's request. DS4432 Dual-Channel, I2C, 7-Bit Sink/Source Current DAC TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 0 0 1 0 0 0 R/W MSB SLAVE ACK b7 READ/ WRITE SLAVE ADDRESS LSB b6 b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 REGISTER/MEMORY ADDRESS b4 b3 b2 b1 b0 SLAVE ACK STOP DATA EXAMPLE I2C TRANSACTIONS 90h A) SINGLE BYTE WRITE -WRITE RESISTOR F9h TO 00h 90h B) SINGLE BYTE READ -READ RESISTOR F8h F9h START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK SLAVE 0 0 0 0 0 0 0 0 ACK F8h START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK SLAVE ACK STOP DATA 91h REPEATED START MASTER NACK 1 0 0 1 0 0 0 1 SLAVE ACK STOP Figure 2. I2C Communication Examples Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits, and the R/W bit in the least significant bit. The DS4432's slave address is 90h. When the R/W bit is 0 (such as in 90h), the master is indicating it will write data to the slave. If R/W = 1 (91h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4432 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. 8 I2C Communication Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Applications Information Example Calculation for an Adjustable Power Supply In this example, the typical operating circuit is used to create Figure 3, a 2.0V voltage supply with 20% margin. The adjustable power supply has a DC-DC converter output voltage, VOUT, of 2.0V and a DC-DC converter feedback voltage, VFB, of 0.8V. To determine the relationship of R0A and R0B, start with the equation: VFB = R 0B x VOUT R 0 A + R 0B Substituting VFB = 0.8V and VOUT = 2.0V, the relationship between R0A and R0B is determined to be: R0A = 1.5 x R0B _______________________________________________________________________________________ Dual-Channel, I2C, 7-Bit Sink/Source Current DAC I OUT0 = IR0B - IR0 A where IR0B = VFB R 0B VCC Decoupling To achieve the best results when using the DS4432, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate highfrequency response for decoupling applications. and IR0 A = To create a 20% margin in the supply voltage, the value of VOUT is set to 2.4V. With these values in place, R0B is calculated to be 2.67k, and R0A is calculated to be 4k. The current DAC in this configuration allows the output voltage to be moved linearly from 1.6V to 2.4V using 127 settings. This corresponds to a resolution of 6.3mV/step. VOUT - VFB R 0A VCC 4.7k 4.7k VOUT = 2.0V* OUT VCC SDA SCL DS4432 DC-DC CONVERTER IR0A R0A = 4k FB OUT0 VFB = 0.8V* IR0B GND R0B = 2.67k FS0 IOUT0 RFS0 = 80k *VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VRFS OF THE DS4432. Figure 3. Example Application Circuit Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 SOP U8+1 21-0036 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. DS4432 IOUT0 is chosen to be 100A (midrange source/sink current for the DS4432). Summing the currents into the feedback node, we have the following: