MTD3055VLT4 - ON Semiconductor

 Semiconductor Components Industries, LLC, 2000

November, 2000 – Rev. 3 1Publication Order Number:

MTD3055VL/D

MTD3055VL

Preferred Device

Power MOSFET

12 Amps, 60 Volts

N–Channel DPAK

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and power

motor controls, these devices are particularly well suited for bridge

circuits where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected voltage

transients.

•Avalanche Energy Specified

•IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–Source Voltage VDSS 60 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc

Gate–Source Voltage

– Continuous

– Single Pulse (tp ≤ 50 ms) VGS

VGSM ±15

±20 Vdc

Vpk

Drain Current – Continuous @ 25°C

Drain Current – Continuous @ 100°C

Drain Current – Single Pulse (tp ≤ 10 µs)

IDM

8.0

Adc

Apk

Total Power Dissipation @ 25°C

Derate above 25°C

Total Power Dissipation @ TA = 25°C, when

mounted to minimum recommended pad

size

PD48

0.32

1.75

Watts

W/°C

Watts

Operating and Storage Temperature

Range TJ, Tstg –55 to

175 °C

Single Pulse Drain–to–Source Avalanche

Energy – Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 5.0 Vdc,

IL = 12 Apk, L = 1.0 mH, RG = 25 Ω)

EAS 72 mJ

Thermal Resistance

– Junction to Case

– Junction to Ambient

– Junction to Ambient, when mounted to

minimum recommended pad size

RθJC

RθJA

3.13

100

71.4

°C/W

Maximum Temperature for Soldering

Purposes, 1/8″ from case for 10

seconds

TL260 °C

PIN ASSIGNMENT

Gate 3

Source

Drain

12 AMPERES

60 VOLTS

RDS(on) = 180 mΩ

Device Package Shipping

ORDERING INFORMATION

MTD3055VL DPAK 75 Units/Rail

CASE 369A

DPAK

STYLE 2

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N–Channel

MTD3055VL1 DPAK 75 Units/Rail

Preferred devices are recommended choices for future use

and best overall value.

MARKING

DIAGRAM

Y = Year

WW = Work Week

T = MOSFET

YWW

3055VL

MTD3055VLT4 DPAK 2500 Tape & Reel

123

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)

Temperature Coefficient (Positive)

V(BR)DSS 60

––

62 –

–Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)

(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

IDSS –

––

–10

100

µAdc

Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS – – 100 nAdc

ON CHARACTERISTICS (Note 1.)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

Threshold Temperature Coefficient (Negative)

VGS(th) 1.0

–1.6

3.0 2.0

–Vdc

mV/°C

Static Drain–Source On–Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) – 0.12 0.18 Ohm

Drain–Source On–Voltage (VGS = 5.0 Vdc)

(ID = 12 Adc)

(ID = 6.0 Adc, TJ = 150°C)

VDS(on) –

–1.6

–2.6

2.5

Vdc

Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) gFS 5.0 8.8 – mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(V 25 Vd V 0 Vd

Ciss – 410 570 pF

Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

)

Coss –114 160

Reverse Transfer Capacitance

MHz)

Crss – 21 40

SWITCHING CHARACTERISTICS (Note 2.)

Turn–On Delay Time td(on) – 9.0 20 ns

Rise Time (VDD = 30 Vdc, ID = 12 Adc,

VGS =50Vdc

tr– 85 190

Turn–Of f Delay Time VGS = 5.0 Vdc,

RG = 9.1 Ω)td(off) – 14 30

Fall Time

9.1

Ω)

tf– 43 90

Gate Charge

(S Fi 8)

QT– 8.1 10 nC

(See Figure 8) (VDS = 48 Vdc, ID = 12 Adc, Q1– 1.8 –

(VDS

Vdc

Adc

VGS = 5 Vdc) Q2– 4.2 –

Q3– 3.8 –

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc)

(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)

VSD –

–0.97

0.86 1.3

–

Vdc

Reverse Recovery Time

(S Fi 14)

trr – 55.7 – ns

(See Figure 14)

(IS=12Adc V

GS = 0 Vdc

ta– 37 –

(IS = 12 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs) tb– 18.7 –

Reverse Recovery Stored

Charge

dIS/dt

100

A/µs)

QRR – 0.116 – µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die) LD– 3.5 – nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad) LS– 7.5 – nH

1. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

2. Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

01 2 3 5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

ID, DRAIN CURRENT (AMPS)

2.0 3.0 4.0 5.0 6.0

ID, DRAIN CURRENT (AMPS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0481216 24

0.02

0.14

0.26

0.32

RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

0 4 12 16 20 24

0.07

0.12

0.17

0.22

0.27

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

01020 405060

0.1

100

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

IDSS , LEAKAGE (nA)

TJ = 25°CVGS = 10 V 5 V

4.5 V

3 V

2.5 V

3.5 V

VGS = 5 V

TJ = 100°C

25°C

-55°C

VDS ≥ 10 V TJ = -55°C

25°C100°C

TJ = 25°C

VGS = 0 V

TJ = 125°C

20 8

4 V

2.5 3.5 4.5 5.5

0.20

0.08

1.0

100°C

VGS = 10 V

5 V

RDS(on), DRAIN-TO-SOURCE RESISTANCE

(NORMALIZED)

-50

0.5

1.0

1.5

TJ, JUNCTION TEMPERATURE (°C)

-25 0 25 50 75 100 125 150

2.0

VGS = 5 V

ID = 6 A

175

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (∆t)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain–gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known a s the plateau voltage, VSGP. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG – VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve a t

a voltage corresponding to the off–state condition when

calculating t d(on) and is read at a voltage corresponding to the

on–state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is a ffected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

10 5 0 10 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

VGS VDS

1400

1000

600

Ciss

Coss

Crss

515

Crss

1200

800

400

200

VDS = 0 V VGS = 0 V

Ciss

TJ = 25°C

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VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

0.50 0.60 0.70 0.80 0.90

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

IS, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

t, TIME (ns)

VDD = 30 V

ID = 12 A

VGS = 5 V

TJ = 25°C

VGS = 0 V

TJ = 25°C

Figure 10. Diode Forward Voltage versus Current

Qg, TOTAL GATE CHARGE (nC)

246810

ID = 12 A

TJ = 25°C

1000

100

td(off)

td(on)

VGS

VDS

0.55 0.65 0.75 0.85 0.95 1.0

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal

Resistance–General Data and Its Use.”

Switching between the off–state and the on–state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded and the

transition time (tr,tf) do not exceed 10 µs. In addition the total

power averaged over a complete switching cycle must not

exceed (TJ(MAX) – TC)/(RθJC).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored ener gy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction

temperature.

Although many E–FETs can withstand the stress of

drain–to–source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry

custom. The ener gy rating must be derated for temperature

as shown in the accompanying graph (Figure 12). Maximum

energy at currents below rated continuous ID can safely be

assumed to equal the values indicated.

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SAFE OPERATING AREA

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

0.1 100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

ID, DRAIN CURRENT (AMPS)

VGS = 5 V

SINGLE PULSE

TC = 25°C

1.0

Figure 13. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

1.0

100

0.1

100 µs

1 ms

10 ms

10 µs

t, TIME (s)

1.0

0.1

0.01

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

0.2

D = 0.5

0.1

RθJC(t) = r(t) RθJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) - TC = P(pk) RθJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

0.05

0.01

SINGLE PULSE

0.02

TJ, STARTING JUNCTION TEMPERATURE (°C)

AS, SINGLE PULSE DRAIN-TO-SOURCE

AVALANCHE ENERGY (mJ)

25 50 75 100 125

ID = 12 A

150

175

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INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the

total design. The footprint for the semiconductor packages

must be the correct size to ensure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self align when

subjected to a solder reflow process.

0.190

4.826

inches

0.100

2.54

0.063

1.6

0.165

4.191

0.118

3.0

0.243

6.172

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a

function of the drain pad size. These can vary from the

minimum pad size for soldering to a pad size given for

maximum power dissipation. Power dissipation for a

surface mount device is determined by TJ(max), the

maximum rated junction temperature of the die, RθJA, the

thermal resistance from the device junction to ambient, and

the operating temperature, TA. Using the values provided

on the data sheet, PD can be calculated as follows:

PD = TJ(max) – TA

RθJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature TA of 25°C,

one can calculate the power dissipation of the device. For a

DPAK device, PD is calculated as follows.

PD = 175°C – 25°C

71.4°C/W = 2.1 Watts

The 71.4°C/W for the DPAK package assumes the use of

the recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 2.1 Watts. There are

other alternatives to achieving higher power dissipation

from the surface mount packages. One is to increase the

area of the drain pad. By increasing the area of the drain

pad, the power dissipation can be increased. Although one

can almost double the power dissipation with this method,

one will be giving up area on the printed circuit board

which can defeat the purpose of using surface mount

technology. For example, a graph of RθJA versus drain pad

area is shown in Figure 15.

Figure 15. Thermal Resistance versus Drain Pad

Area for the DPAK Package (Typical)

1.75 Watts

Board Material = 0.0625″

G-10/FR-4, 2 oz Copper

100

20 1086420

3.0 Watts

5.0 Watts

TA = 25°C

A, AREA (SQUARE INCHES)

TO AMBIENT ( C/W)°

RJA, THERMAL RESISTANCE, JUNCTION

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Another alternative would be to use a ceramic substrate

or an aluminum core board such as Thermal Clad. Using

a board material such as Thermal Clad, an aluminum core

board, the power dissipation can be doubled using the same

footprint.

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads.

Solder stencils are used to screen the optimum amount.

These stencils are typically 0.008 inches thick and may be

made of brass or stainless steel. For packages such as the

SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,

SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode

packages, the stencil opening should be the same as the pad

size o r a 1 : 1 registration. This is not the case with the DPAK

and D2PAK packages. If one uses a 1:1 opening to screen

solder onto the drain pad, misalignment and/or

“tombstoning” may occur due to an excess of solder. For

these two packages, the opening in the stencil for the paste

should be approximately 50% of the tab area. The opening

for the leads is still a 1:1 registration. Figure 16 shows a

typical stencil for the DPAK and D2PAK packages. The

pattern of the opening in the stencil for the drain pad is not

critical as long as it allows approximately 50% of the pad to

be covered with paste.

ÇÇ

ÇÇÇ

ÇÇ

Figure 16. Typical Stencil for DPAK and

D2PAK Packages

SOLDER PASTE

OPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within

a short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

•Always preheat the device.

•The delta temperature between the preheat and

soldering should be 100°C or less.*

•When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

•The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

•When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

•After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

•Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause

excessive thermal shock and stress which can result in

damage to the device.

* Due to shadowing and the inability to set the wave height

to incorporate other surface mount components, the D2PAK

is not recommended for wave soldering.

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TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of

control settings that will give the desired heat pattern. The

operator must set temperatures for several heating zones,

and a figure for belt speed. Taken together, these control

settings make up a heating “profile” for that particular

circuit board. On machines controlled by a computer, the

computer remembers these profiles from one operating

session to the next. Figure 17 shows a typical heating

profile for use when soldering a surface mount device to a

printed circuit board. This profile will vary among

soldering systems but it is a good starting point. Factors that

can affect the profile include the type of soldering system in

use, density and types of components on the board, type of

solder used, and the type of board or substrate material

being used. This profile shows temperature versus time.

The line on the graph shows the actual temperature that

might be experienced on the surface of a test board at or

near a central solder joint. The two profiles are based on a

high density and a low density board. The Vitronics

SMD310 convection/infrared reflow soldering system was

used to generate this profile. The type of solder used was

62/36/2 Tin Lead Silver with a melting point between

177–189°C. When this type of furnace is used for solder

reflow work, the circuit boards and solder joints tend to

heat first. The components on the board are then heated by

conduction. The circuit board, because it has a large surface

area, absorbs the thermal energy more efficiently, then

distributes this energy to the components. Because of this

effect, the main body of a component may be up to 30

degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT STEP 7

COOLING

200°C

150°C

100°C

5°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205° TO 219°C

PEAK AT

SOLDER

JOINT

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

100°C

150°C160°C

170°C

140°C

Figure 17. Typical Solder Heating Profile

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PACKAGE DIMENSIONS

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

2 PL

0.13 (0.005) T

–T– SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.235 0.250 5.97 6.35

B0.250 0.265 6.35 6.73

C0.086 0.094 2.19 2.38

D0.027 0.035 0.69 0.88

E0.033 0.040 0.84 1.01

F0.037 0.047 0.94 1.19

G0.180 BSC 4.58 BSC

H0.034 0.040 0.87 1.01

J0.018 0.023 0.46 0.58

K0.102 0.114 2.60 2.89

L0.090 BSC 2.29 BSC

R0.175 0.215 4.45 5.46

S0.020 0.050 0.51 1.27

U0.020 --- 0.51 ---

V0.030 0.050 0.77 1.27

Z0.138 --- 3.51 ---

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

123

DPAK

CASE 369A–13

ISSUE AA

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Notes

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