October 2000 Page 1
ISD5116
Advance Information
Single-Chip Voice Record/Playback Device Up to
16-Minute Duration with Digital Storage Capability
Features Summary
28-PIN TSOP
ISD5116
SOIC
ISD5116
Fully-Integrated Solution
! Single-chip voice record/playback solution
! Dual storage of digital and analog information
Low Power Consumption
! +2.7 to +3.3V (VCC) Supply Voltage
! Supports 2.0V and 3.0V interface logic
! Operating Current:
" ICC Play = 15 mA (typical)
" ICC Rec = 30 mA (typical)
" ICC Feedthrough = 12 mA (typical)
! Standby Current:
" ISB = 1µA (typical)
! Most stages can be individually powered down
to minimize power consumption
Enhanced Vo ic e Feat u res
! One or two-way conversation record
! One or two-way message playback
! Voi ce memo record and playback
! Private call screening
! In-terminal answering machine
! Personalized outgoing message
! Private call announce while on call
Digital Memory Features
! Up to 4 MB available
! Storage of phone numbers, system configuration
parameters and message address table in cellular
application
Easy-to-use and Control
! No compression algorithm development required
! User-controllable sampling rates
! Programmable analog interface
! Fast mode I2C serial interface (400 kHz)
! Fully addressable to handle multiple messages
High Quality Solution
! High quality voice and music reproduction
! ISD’s standard 100-year message retention
(typical)
! 100K record cycles (t ypical) for analog data
! 10K record cycles (typic al) for dig ital data
Options
! Available in die form, µBGA (available upon
request), TSOP and SOIC
! Extended (-20 to +70C) and Industrial (-40 to
+85C) available
October 2000 Page 1
ISD5116
Advance Information
Single-Chip Voice Record/Playback Device Up to
16-Minute Duration with Digital Storage Capability
Features Summary
28-PIN TSOP
ISD5116
SOIC
ISD5116
Fully-Integrated Solution
! Single-chip voice record/playback solution
! Dual storage of digital and analog information
Low Power Consumption
! +2.7 to +3.3V (VCC) Supply Voltage
! Supports 2.0V and 3.0V interface logic
! Operating Current:
" ICC Play = 15 mA (typical)
" ICC Rec = 30 mA (typical)
" ICC Feedthrough = 12 mA (typical)
! Standby Current:
" ISB = 1µA (typical)
! Most stages can be individually powered down
to minimize power consumption
Enhanced Vo ic e Feat u res
! One or two-way conversation record
! One or two-way message playback
! Voi ce memo record and playback
! Private call screening
! In-terminal answering machine
! Personalized outgoing message
! Private call announce while on call
Digital Memory Features
! Up to 4 MB available
! Storage of phone numbers, system configuration
parameters and message address table in cellular
application
Easy-to-use and Control
! No compression algorithm development required
! User-controllable sampling rates
! Programmable analog interface
! Fast mode I2C serial interface (400 kHz)
! Fully addressable to handle multiple messages
High Quality Solution
! High quality voice and music reproduction
! ISD’s standard 100-year message retention
(typical)
! 100K record cycles (t ypical) for analog data
! 10K record cycles (typic al) for dig ital data
Options
! Available in die form, µBGA (available upon
request), TSOP and SOIC
! Extended (-20 to +70C) and Industrial (-40 to
+85C) available
October 2000 Page 2
Product Description
The ISD5116 ChipCorder Product provides high
quality, fully integrated, single-chip
Record/Playback solutions for 8- to 16-minute
messaging applications that are ideal for use in
cellular phones, automotive communications,
GPS/navigation systems and other portable
products. T he IS D 51 1 6 product is a n enha nceme nt
of the ISD5000 architecture, providing: 1) the I2C
se rial port - a ddress, control a nd duration sele ction
are accomplished through an I2C interface to
minimize pin count (ONLY two control lines
required); 2) the capability of the storage array to
store digital, in addition to analog, information.
These features allow customers to store phone
book numbers, system configuration parameters
and message address pointers for message
management capability.
Analog functions and audio gating have also been
integrated into the ISD5116 product to allow easy
interface with integrated digital cellular chip sets on
the market. Audio paths have been designed to
enable full duplex conversation record, voice
memo, answering machine (including outgoing
message playback) and call screening features.
This product enables playback of messages while
the phone is in standby, AND both simplex and
duplex playback of messages while on a phone call.
Additional voice storage features for digital cellular
include: 1) a personalized outgoing message can
be sent to the person by getting caller-ID
information from the host chipset 2) a private call
announce while on ca ll can be he a rd from the host
by giving caller-ID on call waiting information from
the host chipset.
Logic Interface Options of 2.0V and 3.0V are
supported by the ISD5116 to accommodate
portable communication products customers (2.0-
and 3.0-volt required).
Like other ChipCorder® products, the ISD5116
integrates the sampling clock, anti-aliasing and
smoothing filters, and the multi-level storage array
on a single-chip. For enhanced voice features, the
ISD5116 eliminates external circuitry by integrating
automatic gain control (AGC), a power
amplifier/speaker driver, volume control, summing
amplifiers, analog switches, and a car kit interface.
Input level adjustable amplifiers are also included,
providing a flexible interface for multiple
applications.
Recordings are stored in on-chip nonvolatile
memory cells, providing zero-power message
storage. This unique, single-chip solution is made
possible through ISD’s patented multilevel storage
technology. Voice and audio signals are stored
directly into solid-state memory in their natural,
uncompressed form, providing superior quality
voice and music reproduction.
ISD5116 Block Di agram
AUX IN
AMP
1.0 / 1.4 / 2.0 / 2.8
AGC
SUM1 MUX
Vol MUX
Filter
MUX
Low Pass
Filter
SUM1
FTHRU
INP
ANA OUT MUX
VOL
SUM2
ANA IN
VOL SP+
SP-
SPEAKER
AUX OUT
ANA OUT-
ANA OUT+
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
XCLK
ANA IN
VSSA
VCCA VSSA VSSD VSSD VCCD
VCCD
64-bit/samp.
ARRAY OUTPUT MUX
ARRAY
INPUT
MUX
Input Source MUX
Array I/O Mux
FILTO
SUM1
INP
ANA IN
SUM2
FILTO
SUM2
SUM1
Summing
AMP
ANA IN
AMP
0.625/0.883/1.25/1.76
6dB
SUM2
Summing
AMP
Output M U X
Volume
Control
MIC IN
AUX IN FILTO
ANA IN
SUM1 ANA IN
FILTO
SUM2
(ANALOG)
ARRAY
INP
SUM1 MUX
CTRL
(DIGITAL)
64-bit/samp.
ARRAY OUT
(ANALOG) ARRAY OUT
(DIGITAL)
ARRAY
Spkr.
AMP
AUX
OUT
AMP
Power Conditioning
RACINTSDA
SCL A1A0
Device Control
Internal
Clock Multilevel/Digital
Storage Array
ANA
OUT
AMP
Σ
ΣΣ
ΣΣ
ΣΣ
Σ
2( )
VLS0
VLS1
2
( )
AIG0
AIG1
2( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1 2( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
( )
FLD0
FLD1 2
(INS0)1
1
(AXPD)
1
(AGPD) 1(FLPD)
1(FLS0)
1
(AIPD)
1
(AOPD)
( )
3
AOS0
AOS1
AOS2
3( )
VOL0
VOL1
VOL2
1(VLPD)
October 2000 Page 3
Table of Contents
ISD5116............................................................................................................................................1
1 Overview....................................................................................................................................5
1.1 Speech/Sound Quality.......................................................................................................5
1.2 Duration..............................................................................................................................5
1.3 Flash Storage.....................................................................................................................5
1.4 Microcontroll er Interface ....................................................................................................5
1.5 Programming......................................................................................................................5
2 Functional Description ...........................................................................................................6
2.1 Internal Registers...............................................................................................................7
2.2 Memory Organization.........................................................................................................7
2.3 Pinout Table.......................................................................................................................8
3 Operational Modes Description.............................................................................................9
3.1 I2C Int e rface .......................................................................................................................9
3.2 Command Byte ................................................................................................................11
3.3 Opcode Summary............................................................................................................11
3.4 Data Bytes........................................................................................................................13
3.5 Configuration Register Bytes...........................................................................................13
3.6 Power-up Sequence.........................................................................................................15
3.7 Feed throug h mMde.........................................................................................................15
3.8 Call Record ......................................................................................................................17
3.9 Memo Record...................................................................................................................18
3.10 Memo and Call Playback.................................................................................................19
3.11 Message Cue ing..............................................................................................................20
4 Analog Mode..........................................................................................................................21
4.1 Aux In and Ana In Descript ion.........................................................................................21
4.2 Analog Structure (left half) desc ription.............................................................................22
4.3 Analog Structure (r ight half) description...........................................................................22
4.4 Volume Control Description.............................................................................................23
4.5 Apeak er and Aux Out Description....................................................................................23
4.6 Ana Out Description.........................................................................................................24
4.7 Analog Inputs...................................................................................................................24
5 Digital Mode...........................................................................................................................27
5.1 Writing Data .....................................................................................................................27
5.2 Reading Data ...................................................................................................................27
5.3 Erasing Data ....................................................................................................................27
5.4 Example Command Sequences......................................................................................28
6 Pin Descriptions....................................................................................................................31
6.1 Digital I/O Pins .................................................................................................................31
6.2 Analog I/O Pins................................................................................................................33
6.3 Power and Ground Pins...................................................................................................36
6.4 Sample PC Layout...........................................................................................................36
7 Electrical Characteristics and Parameters.........................................................................37
7.1 Electrical Characteristics..................................................................................................37
7.2 Parameters.......................................................................................................................38
8 Timing Diagrams...................................................................................................................45
8.1 I2C Timing Diagram..........................................................................................................45
8.2 Playback and Stop Cycle.................................................................................................45
8.3 Example of Power Up Command (first 12 bits)................................................................46
October 2000 Page 4
9I
2C Serial Interface Technical Information..........................................................................47
9.1 Characteristics of the I2C Serial Interface........................................................................47
9.2 I2C Protocol......................................................................................................................49
10 Device Physical Dimensions............................................................................................51
10.1. Plastic Thin Small Outline Package (TSOP) Type e Dimensions................................51
10.2. Plastic Small Outline Integrated Circuit (soic) Dimensions..........................................52
10.3. Plastic Dual Inline Package (PDIP) Dimensions..........................................................53
10.4. Die Bonding Physical La yout........................................................................................ 54
11 Ordering Information.........................................................................................................56
October 2000 Page 5
1. OVERVIEW
1.1 SPEECH/SOUND QUALITY
The ISD5116 ChipCorder product can be configured via software to operate at 4.0, 5.3, 6.4 and 8. 0 kHz
sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration
de creases th e sa m pling fre qu e ncy a n d ba ndwidt h, which af fe cts s ound qua lit y. The tabl e in the f ollowing
section compares filter pass band and product durations.
1.2 DURATION
To meet end-s ystem requirements, the ISD5116 dev ice is a sin gle-chip s olut ion, which pr ovides f rom 8 to
16 minutes of voice record and playback, depending on the sample rates defined by customer software.
Input Sample
Rate (kHz) Duration1Typical Filter Knee
(kHz)
8.0 8 min 44 sec 3.4
6.4 10 min 55 sec 2.7
5.3 13 min 6 sec 2.3
4.0 17 min 28 sec 1.7
1. Minus any pages selected for digital storage
1.3 FLASH STORAGE
One of the benefits of ISD’s ChipCorder technology is the use of on-chip nonvolatile memory, which
provides zero-power message storage. The message is retained for up to 100 years (typically) without
power. In a ddition, the de vice can be re- recorded over 1 0,000 times (typically) for the digital me ssage s
and over 100,000 times (typically) for the analog messages.
A new feature has been added that allows memory space in the ISD5116 to be a llocate d to either digital
or analog storage when recorded. The fact that a section has been assigned digital or analog data is
stored in the Message Address Table by the system microcontroller when the recording is made.
1.4 MICROCONTROLLER INTERFACE
The ISD5116 is controlled through an I2C 2-wire interface. This synchronous serial port allows
commands, configurations, address data, and digital data to be loaded to the device, while allowing
status, digital data and current address information to be read back from the device. In addition to the
seria l int e rf a c e , two othe r pins can be conn e cted to t he m icrocontr olle r for enhanced inte r face. These are
the RAC timing pin a nd the I NT pin for interrupts to the controlle r. Communications with a ll the interna l
registers are through the serial bus, as well as digital memory Read and Write operations.
1.5 PROGRAMMING
The ISD5116 series is also ideal for playback-only applications, where single or multiple messages may
be played back when desired. Playback is controlled through the I2C interface. Once the desired message
configuration is created, duplicates can easily be generated via a third-party programmer. For more
information on available application tools and programmers, please see the ISD web site at
www.winbond-usa.com
October 2000 Page 6
2 FUNCTIONAL DESCRIPTION
The ISD5116 is a single chip solution for voice and analog storage that also includes the capability to
store digital information in the memory array. The array may be divided between analog and digital
stora ge , a s the use r choose s, whe n configuring the de vice . T he de vice consists of se ve ra l se ctions tha t
will be described in the following paragraphs.
Looking a t the block diagram below, one ca n see that the ISD5116 ma y be very ea sily de signed into a
cellular phone. Placing the device between the microphone and the existing voice encoder chip takes
care of the transmit path. The ANA IN is connected between one of the speaker leads on the voice
de c ode r ch ip and the spea k er is conn e c te d to th e S PEAKER p ins of the I SD5116. Two p ins are nee ded
for the I2C digital control and digital information for storage.
S tarting a t the M I CR O PH O N E inputs, the signa l from the microphone ca n be route d dire ctly through the
chip to the ANA OUT pins through a 6 dB am plifier s tage. Or, the sign al can b e pass ed through the AGC
amplifie r and directe d to the ANA O UT pins, directe d to the stora ge a rra y, or mixe d with voice from the
receive path coming from ANA IN and be directed to the same places.
In ad dit ion, if th e phone is ins erted in to a "hands-f ree" car k it, then the s ignal f rom the pick up m icrophone
in the car can be passed t hrou gh to th e sam e plac es fr om the AUX IN pi n and t he ph one' s m icrophone is
switched off. Under this situation, the other party's voice from the phone is played into ANA IN and
passed through to the AUX OUT pin that drives the car kit's loudspeaker.
Depending upon whether one desires recording one side (simplex) or both sides (duplex) of a
conve rsa tion, the va rious pa ths will a lso be switche d through to the low pa ss filte r ( for a nti- alia sing) a nd
into the storage array. Later, the cell phone owner can play back the messages from the array. When
this ha ppens the Arra y Output MUX is conne cted to the volume control through the O utput MU X to the
Speaker Amplifier.
For applications other than a cell phone, the audio paths can be switched into many different
configurations, providing great flexibility.
RF
Section MI C IN+
MIC IN-
SP OUT-
SP OUT+
VB
Codec
DSP
123456789
BB
Codec
Baseband
ANA OUT+
ANA OUT-
SP+
SP-
MIC+
MIC-
ANA IN
SDA, SCL
AUX IN AUX OUT
CAR KIT
Earpiece
Speaker
Keyboard
Display
ISD5116
Microcontroller
October 2000 Page 7
2.1 INTERNAL REGISTERS
The ISD5116 has multiple internal registers that are used to store the address information and the
configuration or set-up of the device. The two 16-bit configuration registers control the audio paths
through the de vice, the sample fre quency, the various gains a nd attenuations, the se ctions powere d up
and down, and the volume settings. These registers are discussed in detail in section 3.5 on page 13.
2.2 MEMORY ORGANIZATION
The ISD5116 memory array is arranged as 2048 rows (or pages) of 2048 bits for a total memory of
4,194,304 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the
analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus at 8 kHz
there is actually room for 8 minutes and 44 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. T he
contents of a page are either analog or digita l. T his is determined by instruction (op code) at the time the
data is written. A record of what is analog and what is digital, and where, is stored by the system
microcontroller in the message address table (MAT). The MAT is a table kept in the microcontroller
me mory that de fines the sta tus of e ach me ssage “block.” It can be store d back into the I SD 51 1 6 if the
power fails or the system is turned off. Using this table allows for efficient message management.
Segments of messages can be stored wherever there is available space in the memory array. [This is
e xpla ine d in de tail for the I S D 5 0 0 8 in Applica tions N ote # 9 a nd will be sim ila rly de scribe d in a la te r Note
for the ISD5116.]
When a page is used for analog storage, the same 32 blocks are present but there are 8 EOM (End-of-
Message) markers. This means that for each 4 blocks there is an EO M marker at the end. Thus, when
recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when EN DING an a nalog recording. Beginning a n analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when the
S top comma nd is given, but continue s until the 3 2 millise cond block is fille d. T he n a bit is pla ce d in the
EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode.
Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted and
stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it
becomes the register that is paralle l written into the array. T he prior write register becomes the new serial
input register. A mechanism is built-in to ensure there is always a register available for storing new data.
Storing data in the memory is accomplished by accepting data one byte at a time and issuing an
acknowledge. If data is com ing in fas ter than it can be wri tten , th e chi p iss ues an acknowledge to th e hos t
microcontroller, but holds SCL LOW until it is ready to accept more data.
T he re ad mode is the opposite of the write mode . D ata is re ad into one of two 6 4- bit re gisters from the
array and serially sent to the I2C interface. (See section 5 on page 27 for details).
October 2000 Page 8
2.3 PINOUT TABLE
Pin Name Pin No.
28-pin
TSOP
Pin No.
28-pin
SOIC
Functionality
RAC 3 24 Row Address Clock; an open drain output. The RAC pin goes LOW
TRACLO1 before the end of each row of memory and returns HIGH at
exactly the end of each row of memory.
INT 4 25 Interrupt Output; an open drain output that indicates that a set EOM bit
has been found during Playback or that the chip is in an Overflow (OVF)
condition. This pin remains LOW until a Read Status command is
executed.
XCLK 5 26 This pin allows the internal clock of the device to be driven externally for
enhanced timing precision. This pin is grounded for most applications.
SCL 8 1 Serial Clock Line is part of the I2C interface. It is used to clock the data
into and out of the I2C i nterface.
SDA 10 3 Serial Data Line is part of the I2C interface. Data is passed between
devices on the bus over this line.
A0 11 4 Input pin that supplies the LSB for the I2C Slave Address.
A1 9 2 Input pin that supplies the LSB +1 bit for the I2C Slave Address.
MIC+ 16 8 Differential Positive Input to the microphone amplifier.
MIC- 17 10 Differential Negative Input to the microphone amplifier.
ANA OUT+ 18 11 Differential Positive Analog Output for ANA OUT of the device.
ANA OUT- 19 12 Differential Negative Analog Output for ANA OUT of the device.
ACAP 20 13 AG C Capacitor connection. Required for the on-chip AGC amplifier.
SP+ 23 16 Differential Positive Speaker Driver Output.
SP- 21 14 Differential Negative Speaker Driver Output. When the speaker outputs
are in use, the AUX OUT output is disabled.
ANA IN 25 18 Analog Input. This is one of the gain adjustable analog inputs of the
device.
AUX IN 26 19 Auxiliary Input. This is one of the gain adjustable analog inputs of the
device.
AUX OUT 27 20 Auxiliary Output. This is one the analog outputs of the device. When this
output is in use, the SP+ and SP- outputs are disabled.
VCCD 6,7 27,28 Positive Digital Supply pins. These pins carry noise generated by
internal clocks in the chip. They must be carefully bypassed to Digital
Ground to insure correct device operation.
VSSD 12,13 5,6 Digital Ground pins.
VSSA 2,15,22 9,15,23 Analog Ground pins.
VCCA 24 17 Positive Analog Supply pin. This pin supplies the low level audio
sections of the device. It should be carefully bypassed to Analog Ground
to insure correct device operation.
NC 1,14,28 7,21,22 No Connect.
1 See the Parameters section of on page 38.
October 2000 Page 9
3 OPERATION AL MODES DESCRIPTION
3.1 I2C INTERFACE
Important note: The rest of this data sheet will assume that the reader is familiar with the I2C
serial interface. Additional information on I2C may be found in section 9.0 on page 47 of this
document. If you are not familiar with this serial protocol, please read this section to familiarize
yourself with it. A large amount of additional infor mation on I2C can also be found on the Philips
web page at http://www.philips.com/.
3.1.1 I2C Sl ave Address
The ISD5116 has a 7-bit sla ve address of <100 00xy> where x and y are e qua l to the state, respectively,
of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the
address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data.
Therefore, there are 8 possible slave addresses for the ISD5116. These are:
A1 A0 Slave Address R/W Bit HEX Value
0 0 <100 0000> 0 80
0 1 <100 0001> 0 82
1 0 <100 0010> 0 84
1 1 <100 0011> 0 86
0 0 <100 0000> 1 81
0 1 <100 0001> 1 83
1 0 <100 0010> 1 85
1 1 <100 0011> 1 87
To use more than four ISD5116 devices in an application requires some external switch ing of the I2C
interface.
3.1.2 ISD5116 I2c Operation Definitions
There are many control functions used to operate the ISD5116.
Among them are:
1. READ STATUS COMMAND: The Read Status command is a
read request from the Host processor to the ISD5116 without
delivering a Command Byte. The Host supplies all the clocks
(SCL). In each case, the entity sending the data drives the data
line (SDA). The Read Status Command is executed by the
follo wing I2C sequence.
1. Host executes I2C START
2. Send Slave Address with R/W bit = “1” (Read) 81h
3 . S la ve (I SD51 16 ) re spon ds ba ck to H ost a n Ac knowle dg e ( AC K)
followed by 8-bit Status word
4. Host sends an Acknowledge (ACK) to Slave
5. Wait for SCL to go HIGH
6. Slave responds with Upper Address byte of internal address
register
7. Host sends an ACK to Slave
8. Wait for SCL to go HIGH
Conventions used in I
2
C Data
Transfer Diagrams
= START Condition
= STOP Condition
= 8-bit data transfer
= “1” in the R/W bit
= “0” in the R/W bit
= ACK (Acknowledge)
= No ACK
W
S
SLAV E AD DR ESS
R
A
DATA
P
= H ost to Slave (Gray)
= Slave to Host (White)
The Box color indicates the
direction of data flow
= 7-bit Slave
Address
N
October 2000 Page 10
9. Slave responds with Lower Address byte of internal address register (A[4:0] will always return set to 0.)
10. Host sends a NO ACK to Slave, then executes I2C STOP
Note that the pr ocess or c oul d h ave sent an I2C ST O P after the Status Word data transfer and aborted the
transfer of the Address bytes.
A graphical representation of this operation is found below. See the caption box above for more
explanation.
2. LOAD COMMAND BYTE REGISTER (SINGLE BYTE LOAD): A single byte may be written to the
Command Byte Register in order to power up the device, start or stop Analog Record (if no address
information is needed), or do a Message Cueing function. The Command Byte Register is loaded as
follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = “0” (Write) [80h]
3. Slave responds back with an ACK.
4. Wait for SCL to go HIGH
5. Host sends a command byte to Slave
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host executes I2C STOP
3. LOAD COMMAND BYTE REGISTER (ADDRESS LOAD): For the normal addressed mode the
Registers are loaded as follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = “0” (Write)
3. Slave responds back with an ACK.
4. Wait for SCL to go HIGH
5. Host sends a byte to Slave - (Command Byte)
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK
10. Wait for SCL to go HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL to go HIGH
14. Host executes I2C STOP
SSL AVE ADDRES S
A
A
DATA P
R
DATADATA
A
N
Status High Addr. Low Addr.
SSL AVE ADDRES S ADATA PW
Command Byte
A
SSL AVE ADDRES S
A
PW
Command
DATA
A
DATA
A
DATA
A
High Add r. Low Addr.
October 2000 Page 11
3.1.3 I2C Cont r ol Regi sters
The ISD5116 is contro lled b y loadi ng c om mands to, or, readi ng f r om, the internal command, configur ation
and address registe rs. T he C omma nd byte se nt is used to sta rt a nd stop re cording, write or re ad digita l
data and perform other functions necessary for the operation of the device.
3.2 COMMAND BYTE
Control of the ISD5116 is implemented through an 8-bit command byte, sent after the 7-bit device
address and the 1-bit Read/Write selecti on bit. The 8 bits are:
! Global power up bit
! DAB bit: determines whether device is performing an analog or digital function
! 3 function bits: the se dete rmine which function the device is to perform in conjunction with the D AB
bit.
! 3 register address bits: these determine if and when data is to be loaded to a register
C7 C6 C5 C4 C3 C2 C1 C0
PU DAB FN2 FN1 FN0 RG2 RG1 RG0
Function Bits Register Bits
Function Bits
The command byte function bits are
detailed in the table to the right. C6, the
D AB bit, de termines whe the r the de vice is
performing an analog or digital function.
T he other b its a re de c ode d to pro duce the
individual commands. Not all decode
combinations are currently used, and are
reserved for future use. Out of 16 possible
codes, the ISD5116 uses 7 for normal
operation. The other 9 are undefined.
Register Bits
The register load may be used to modify a command
sequence (such as load an address) or used with the null
command sequence to load a configuration or test register.
Not all registers are accessible to the user. [RG2 is always 0
as the four additional combinations are undefined.]
3.3 OPCODE SUMMARY
OpCode Command Description
The following commands are used to access the chip through the I2C interface.
! Play: analog play command
! Re cord: analog record command
! Message Cue: analog message cue command
! Read: digital read command
! Write: digital write command
Command Bits
C6 C5 C4 C3
DAB FN2 FN1 FN0
Function
0 0 0 0 STOP (or do nothing)
0101Analog Play
0010Analog Record
0111Analog MC
1 1 0 0 Digital Read
1 0 0 1 Digital Write
1 0 1 0 Erase (row)
RG2 RG1 RG0
C2 C1 C0 Function
0 0 0 No action
0 0 1 Load Address
0 1 0 Load CFG0
0 1 1 Load CFG1
Power Up
Bit
October 2000 Page 12
! Erase: digital page and block erase command
! Power up: global power up/down bit. (C7)
! Load address: load address register (is incorporated in play, record, read and write commands)
! Load CFG0: load configuration register 0
! Load CFG1: load configuration register 1
! Read STATUS: Read the interrupt status and address register, including a hardwired device ID
OPCODE COMMAND BYTE TABLE
Pwr Function Bits Register Bits
OPCODE HEX PU DA
BFN
2FN
1FN
0RG
2RG
1RG
0
COMMAND BIT NUMBER CMD C7 C6 C5 C4 C3 C2 C1 C0
POWER UP 80 1 0 0 0 0 0 0 0
POWER DOWN 00 0 0 0 0 0 0 0 0
STOP (DO NOTHING) STAY
ON 8010000000
STOP (DO NOTHING) STAY
OFF 0000000000
LOAD ADDRESS 8110000001
LOAD CFG0 8210000010
LOAD CFG1 8310000011
RECORD ANALOG 90 1 0 0 1 0 0 0 0
RECORD ANALOG @ ADDR 91 1 0 0 1 0 0 0 1
PLAY ANALOG A8 1 0 1 0 1 0 0 0
PLAY ANALOG @ ADDR A9 1 0 1 0 1 0 0 1
MSG CUE ANALOG B8 1 0 1 1 1 0 0 0
MSG CUE ANALOG @ ADDR B9 1 0 1 1 1 0 0 1
ERASE DIGITAL PAGE D0 1 1 0 1 0 0 0 0
ERASE DIGITAL PAGE @
ADDR D111010001
WRITE DIGITAL C811001000
WRI TE DIGITAL @ ADDR C9 1 1 0 0 1 0 0 1
READ DIGITAL E0 1 1 1 0 0 0 0 0
READ DIGITAL @ ADDR E1 1 1 1 0 0 0 0 1
READ STATUS1N/A N/A N/A N/A N/A N/A N/A N/A N/A
1. See section 3.1.2 on page 9 for details.
October 2000 Page 13
3.4 DATA BYTES
In the I2C write mode, the device can a c cept data sent after the c omm and b yte. If a register lo ad opti on is
selected, the next two bytes are loaded into the se lected register. T he format of the data is MS B first, the
I2C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is
acknowledge d, and DATA<7:0> is se nt next. T he address register consists of two bytes. T he format of
the address is as follo ws:
ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0>
Note: if an analog function is selected, the block address bits must be set to 0000. Digital Read
and Write are block addressable.
W hen the device is polled with the Read Status command, it will return thre e bytes of data. The first byte
is the status byte, the next the upper address byte and the last the lower address byte. The status register
is one byte long and its bit function is:
STATU S<7:0> = EOM, OVF, READY, PD, PR B, DEVIC E _ID <2:0>
Lower address byte will always return the block address bits as zero, either in digital or analog mode.
The functions of the bits are:
EOM Indicates whether an EOM interrupt has occurr ed.
OVF Indicates whether an overflo w inter rupt has occurr ed.
READY Indicates the internal status of the device – if READY is LOW no new commands
should be sent to device.
PD Device is powered down if PD is HIGH.
PRB Play/Record mode indicator. HIGH=Play/LOW=Record.
DEVICE_ID An internal device ID. This is 001 for the ISD5116.
It is recommended that you read the status register after a W rite or Record operation to ensure that the
de vice is re ad y to a c ce pt ne w comm a nds. D e p e nding upon t he de s ign a nd the numbe r of pins a vailable
on the c ontrolle r, th e polling o ve rhe ad c a n be reduc e d. I f I N T a nd RAC a re tie d to the m icrocontroller, it
does not have to poll as frequently to determine the status of the ISD5116.
3.5 CONFIGURATION REGISTER BYTES
The configuration register bytes are defined, in detail, in the drawings of Section 4 on page 21. The
drawings display how each bit enables or disables a function of the audio paths in the ISD5116. The
tables below give a gener al il lus tr ation of the bits. There ar e t wo c onf igurat io n r eg isters , CFG0 and CFG1,
so there are four 8-bit bytes to be loaded during the set-up of the device.
October 2000 Page 14
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
Configuration Register 0 (CFG0)
AI G1 AIG0 AIPD AXG1 AXG 0 AXPD IN S0 AOS2 AOS1 AOS0 AOPD O PS1 OP S0 OPA1 O PA0 VLPD
Volume C ontrol Pow e r Do wn
SPKR & AUX OUT Contr ol (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Pow er Down
AUXOUT MUX Sele c t (3 bits )
INPUT SOURC E MUX Selec t (1 bit )
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Dow n
ANA IN AMP Gain SET (2 bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
Configuration Register 0 (CFG0)
AI G1 AIG0 AIPD AXG1 AXG 0 AXPD IN S0 AOS2 AOS1 AOS0 AOPD O PS1 OP S0 OPA1 O PA0 VLPD
Volume C ontrol Pow e r Do wn
SPKR & AUX OUT Contr ol (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Pow er Down
AUXOUT MUX Sele c t (3 bits )
INPUT SOURC E MUX Selec t (1 bit )
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Dow n
ANA IN AMP Gain SET (2 bits)
AGC AMP Power Down
Fil ter Po wer Dow n
SAM PLE R ATE (& Fil t er) Se t up (2 bi ts)
FILTER MUX Select
SUM 2 SU M MIN G A MP C ont r o l ( 2 bi t s )
SUM 1 SU M MIN G A MP C ont r o l ( 2 bi t s )
SUM 1 MUX Se lec t (2 bits )
VOLUME CONTROL (3 bits)
VOLUME CONT. M UX Select (2 bits)
Configuration Register 1 (CFG1)
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
AGC AMP Power Down
Fil ter Po wer Dow n
SAM PLE R ATE (& Fil t er) Se t up (2 bi ts)
FILTER MUX Select
SUM 2 SU M MIN G A MP C ont r o l ( 2 bi t s )
SUM 1 SU M MIN G A MP C ont r o l ( 2 bi t s )
SUM 1 MUX Se lec t (2 bits )
VOLUME CONTROL (3 bits)
VOLUME CONT. M UX Select (2 bits)
Configuration Register 1 (CFG1)
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
October 2000 Page 15
3.6 POWER-UP SEQUENCE
This sequence prepares the ISD5116 for an operation to follow, waiting the Tpud time before sending the
next command sequence.
1. Send I2C POWER UP
2. Send on e byte 10000000 {Slave Address, R/W = 0} 80h
3. Slave ACK
4. Wait for SCL High
5. Send one byte 10000000 {Command Byte = Power Up} 80h
6. Slave ACK
7. Wait for SCL High
8. Send I2C STOP
3.6.1 Playback Mode
The comm and sequence for an an alog Playback operation can be handled several ways. One t echnique
would be to do a Load Address (81h), which re quires se nding a tota l of four bytes, and the n sending a
Pla y Analog, which would be a Command Byte (A8h) proceeded by the Slave Address Byte. This is a
total of six bytes plus the times for Start, ACK, and Stop.
Another a pproach would be to incorporate both into a single four byte exchange, which consists of the
Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address bytes.
3.6.2 Record Mode
The command sequence for an Analog Record would be a four byte sequence consisting of the Slave
Address (80h), the Command Byte (9 1h) for Record Ana log @ Address, and the two address bytes. See
“Load Command Byte Register (Address Load)” in section 3.1.2 on page 10.
3.7 FEED THROUGH MODE
The previous examples were dependent upon the device already being powered up and the various paths
being set through the device for the desired operation. To set up the device for the various paths requires
loa ding the two 1 6- bit C onfigura tion R egisters with the correct da ta. For exa mple, in the Fe e d Through
Mode the device only needs to be powered up and a few paths selected.
This mode ena bles the I SD5116 to connect to a cellular or cordless base band phone chip set without
affecting the audio source or destination. T here are two paths involved, the transmit path and the receive
path. T he tra nsmit path conne cts the IS D chip’s microphone source through to the microphone input on
the base band chip set. The receive path connects the base band chip set’s speaker output through to the
spe ak e r drive r on the I SD ch ip. T his a llows th e I S D c hip to substit ute for th ose functio ns a n d incidentall y
gain access to the audio to and from the base band chip set.
To set up the environment described above, a series of commands need to be sent to t he ISD5116. First,
the chip needs to be powered up as described in this section. Then the Configuration Registers must be
filled with the specif ic da ta to con ne ct t he p a ths de s ire d. I n the case of the Fe ed Through Mod e , m ost of
the chip can remain powered down. The follow ing figure illustrates the affected paths.
October 2000 Page 16
The figure above shows the part of the ISD5116 block diagram that is used in Feed Through Mode. The
re st of the chip will be powe red down to conse rve powe r. T he bold lines highlight the audio pa ths. N ote
that the Microphone to ANA OUT +/– path is differential.
To sele c t this mode, th e followi ng contr ol bits must be configur e d in the ISD5116 configuration re gis te rs.
To set up the transmit path:
1. Select the FTHRU path through the ANA OUT MUX—Bits AO S0, AOS1 and AOS2 control the
state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration
Register 0 (CFG0) and they sho uld all be ZERO to select t he FTHRU pat h.
2. Power up the ANA OUT amplifier—Bit AO PD controls the power up state of ANA OUT . T his is bit
D5 of CFG0 and it should be a ZERO to power up the amplifier.
To set up the receive path:
1 . Set up t he AN A IN am plifier f or the cor re c t gain— B its AIG0 a n d AI G1 contr ol t he gain s e tt ings of
this am plifier. These are bits D14 and D15 r espectively of CFG0. The input level at th is p in deter-
mines the setti ng of this gain st a ge . The ANA IN Amplifier Gain Settings table o n pa ge 25 will
help determine this setting. In this example, we will assume that the peak signal never goes
above 1 volt p-p sing le ended. That woul d enab le us to use the 9 dB attenuation setting , or where
D14 is ONE and D15 is ZERO.
2 . P owe r up the AN A I N a mplif ie r— Bit AI P D controls the powe r up sta te of AN A I N . This is bit D 1 3
of CFG0 and should be a ZERO to power up the amplifier.
3. Select the ANA IN path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of the
OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to the
state where D3 is ONE and D4 is ZERO to select the ANA IN path.
4. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and AUX
amplifiers. These are bits D1 and D2 respectively of CFG0. T hey should be set to the state where
D1 is ONE and D2 is ZERO. This po wers up t he Speak er Am plif ier and co nfigur es it for its higher
gain setting for use with a piezo speaker element and also powers down the AUX output stage.
The status of the rest of the functions in the ISD5116 chip must be defined before the configuration
registers settings are updated:
October 2000 Page 17
1. Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
2. Po wer down th e A UX IN amplif ier —B it AXPD controls the power up s tate of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
3. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1 M0 and S1M1 control the SUM1
mixer and bits S2M0 and S2M1 control the SUM 2 mixer. T hese are bits D7 and D8 in CF G1
and bits D 5 and D6 in C FG 1 respe ctively. All 4 bits should be set to a ON E to powe r down
these two amplifiers.
4. Power do wn th e FILTER stage—Bit FLPD controls the power up state of the FI LT ER stage in
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
5. Po we r do wn th e AGC am plifier—Bit AG PD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
6. Don’t Care bi ts—The follo win g s tag es are n ot used in Feed Through Mo de. Their bits may b e
se t to e ithe r leve l. I n this e xample , we will se t a ll the following bits to a Z ER O . ( a ). Bit I N S0 ,
bit D9 of C FG 0 controls the Input Source Mux. (b) . Bits AX G0 a nd AX G1 are bits D 11 and
D 12 res pecti ve l y in C FG0. They control the AUX IN am plif ie r gain s e t ting. (c ) . Bits F LD0 and
F LD 1 a re bits D 2 a nd D3 re spe ctive ly in C F G 1. T hey control the s ample ra te a nd filte r ba nd
pa s s se ttin g. (d). Bit F LS0 is bit D4 in C FG1. It contr ols the FILTER M UX. (e). Bits S1S0 and
S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VO L1 and
VO L2 are bits D1 1, D12 and D 13 of C FG 1. T hey control the setting of the Volume Control.
(g). Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control
MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two
registers m us t be loaded i n this order. The internal set u p f or both regis ters will tak e eff ect synchronous l y
with the rising edge of SCL.
3.8 CALL RECORD
The call record mode adds the ability to record an incoming phone call. In most applications, the
ISD5116 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5116 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMI NG amplifier. T he path traces back from there through the LOW PASS Filter, TH E FILT ER
MUX, THE SU M1 SUMMING amplifier, the SUM1 MUX , the n from the ANA in amplifier. Feed T hrough
M ode ha s alre ady powe red up the AN A I N a mp s o we o nly nee d t o powe r u p a nd e nab le the pat h to the
Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the state
where both D9 and D10 are ZERO to select the ANA IN path.
October 2000 Page 18
2 . S e le ct the S U M 1 M U X input ( only) to the S 1 S U M M I N G a mplifie r— Bits S 1 M 0 a nd S 1M 1 control
the state of the SU M1 SUMMING amplifier. T hese are bits D7 and D8 respective ly of CFG 1 and
they should be s et to the state where D7 is ONE and D8 is ZERO to s elect the SUM1 MUX (only)
path.
3. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 contr ols the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUM-
MING amplifier path.
4. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
F ILT ER stage . T his is bit D 1 of C FG 1 a nd it must be set to Z ER O to powe r up the LOW P ASS
FILTER STAGE.
5. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 6.4 kHz sample rate, D2 m ust be set to ONE and D3 set to ZERO.
6 . Select the LO W P AS S FILTER input (only) to the S2 SUMMING am plifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
In this mode, the elements of the original PASS THROUGH mode do not change. T he sections of the
chip not required to add the record path remain powered down. In fact, CFG0 does not change and
remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CF G0 is not changed, it is only nece ssary to load CF G1 . Note tha t if only CF G0 wa s changed, it
would be necessary to load both registers.
3.9 MEMO RECORD
T he Me mo Record mode sets the chip up to record from the local microphone into the chip’s M ultile vel
Stor age Array. A co nnec ted cellu lar t elephone or c ordl ess pho ne ch ip s et may rem ain p o wered do wn and
is not active in this mode. The path to be used is microphone input to AGC amplifier, then through the
INPUT SOURC E MUX to the SUM1 SUMMING amplifier. From there the path goes through the FILTER
MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL STORAGE
ARRAY. In this instance, we will select the 5.3 kH z sample rate. T he rest of the chip may be powered
down.
1. Power up the AGC amplifier—Bit AGPD controls the power up state of the AG C amplifier. T his is
bit D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifie r through the I NP UT S OURCE MUX—Bit INS0 controls the state of the
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC am-
plifier.
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of
CFG1 and the y should be set to the state where D7 is ZERO and D8 is ONE to se lect the IN PUT
SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 contr ols the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1
SUMMING amplifier path.
October 2000 Page 19
5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
F ILT ER stage . T his is bit D 1 of C FG1 a nd it must be set to Z ER O to powe r up the LOW P ASS
FILTER STAGE.
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sam ple rate, D2 must be set to ZERO and D3 set to ONE.
7 . Select the LO W P AS S FILTER input (only) to the S2 SUMMING am plifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
3.10 MEMO AND CALL PLAYBACK
This mode sets the chip up for local playback of messages recorded e arlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From
there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo
speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered
down.
1. Select the MU LT ILEV EL ST ORAGE ARRAY path through the F ILT ER MUX—Bit F LS 0 , the sta te
of the F I LT E R M U X . T his is bit D 4 of CF G 1 a nd m ust be se t to O N E to se le ct the M U LT I LEV E L
STORAGE ARRAY.
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
F ILT ER stage . T his is bit D 1 of C FG 1 a nd it must be set to Z ER O to powe r up the LOW P ASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (onl y) to the S2 SUMMING amplif ier —Bi ts S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They
should be se t to the state where D1 4 is O NE and D 1 5 is Z ERO to se lect the SU M 2 S UM MI NG
amplifier.
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to
power-up the VOLUME CONTROL.
7. Sel ect a VOLUME CONTROL LEVEL—Bits VOL0, VOL1, and VOL2 co ntrol the state of the VOL-
UME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary
count of 000 through 111 controls the amount of attenuation through that state. In most cases,
the software will select an attenuation level according to the desires of the current users of the
October 2000 Page 20
product. In this example, we will assume the user wants an attenuation of –12 dB. For that
setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO.
8. Select the VOLUME CONTROL path through the OUTPUT MUX—These are bits D3 and D4,
respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to
select the VOLUME CONTROL.
9. Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and OPA1
control the state of the speaker (SP+ and SP–) and AUX OUT outputs. T hese are bits D1 and D2
of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the
speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0010 (hex 2422).
CFG1=0101 1001 1101 0001 (hex 59D1).
Only those portions necessary for this mode are powered up.
3.11 MESSAGE CUEING
Message cueing allows the user to skip through analog messages without knowing the actual physical
location of the m essage. This operation is us ed durin g playba c k . In this m ode, the m essages are s kipped
512 times faster than in normal playback mode. It will stop when an EOM marker is reached. Then, the
internal address counter will be pointing to the next message.
October 2000 Page 21
4 ANALOG MODE
4.1 AUX IN AND ANA IN DESCRIPTIO N
The AUX IN is an a dd itiona l audi o input to the I S D511 6 , s uch a s f rom the m icrophone circui t in a m obile
phone “car kit.” This input has a nominal 700 mV p-p level at its minimum gain setting ( 0 dB). See the
AUX IN Amplifier G ain Settings table o n pa ge 26. Additional gain is ava ilable i n 3 dB st e ps (c ontrolled
by the I2C se rial interface) up to 9 dB.
T he AN A I N pin is the a na log input from the te le phone chip se t. I t ca n be switche d ( by the se ria l bus) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1.11 Vp-p when at its minimum gain (6 dB) setting. See the ANA IN Amplifier Gain Settings table on
page 25. There is additional gain available in 3 dB steps controlled from the I2C inte rf a ce , if re quire d, up
to 15 dB.
ANA IN
Input Amplifier
ANA IN
Input
CCOUP=0.1
µ
FRa
Rb
Internal to the device
NOTE: fCUTOFF=2πRaCCOUP
1
AUX IN
Input Amplifier
AUX IN
Input
CCOUP=0.1
µ
FRa
Rb
Internal to the device
NOTE: fCUTOFF=2πRaCCOUP
1
October 2000 Page 22
4.2 ISD5116 ANALOG STRUCTURE (LEFT HALF ) DESCRIPTION
INPUT
AGC AMP SUM 1
Σ
2 (S1M1 ,S 1M0)
SO URCE
MUX
SUM1 SUMMING
AMP
AUX IN AMP
FILTO
SUM1
MUX
ANA IN AMP
ARRAY
2 (S1S 1,S1S0)
(INS0)
1514131211109876543210
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
1514131211109876543210
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
4.3 ISD5116 ANALOG STRUCTURE (RIGHT HALF ) DESCRIPTION
SUM1
SUM2
Σ
2 (S2 M1,S 2M0)
FILTER
MUX SUM2 SUMM IN G
AMP
ARRAY
2
FILTO
LOW PASS
FILTER
INTERN AL
CLOCK
MULTILEVEL
STO RAGE
ARRAY
1
(FLS0) 1
(FLPD)
ARRAY
ANA I N AMP
XCLK
(FLD1,FLD0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
INP
Inso Source
0 AGC AMP
1AUX IN AMP
S1M1 S1M0 SOURCE
00BOTH
01SUM1 MUX ONLY
10INP Only
1 1 Power Down
S1S1 S1S0 SOURCE
0 0 ANA IN
0 1 ARRAY
10FILTO
11N/C
FLS0 SOURCE
0SUM1
1 ARRAY
FLPD CONDITION
0Power Up
1Power Down
S1M1 S1M0 SOURCE
00BOTH
0 1 ANA IN ONLY
10FILTO ONLY
1 1 Power Down
FLD1 FLD0 SAMPLE
RATE FILTER
BANDWIDTH
0 0 8 KHz 3.6 KHz
0 1 6.4 KHz 2.9 KHz
1 0 5.3 KHz 2.4 KHz
1 1 4.0 KHz 1.8 KHz
FILTER
MUX FILTO
October 2000 Page 23
4.4 VOLUME CONTROL DESCRIPTION
VOL
SUM 2
VOL
MUX
SUM 1
IN P
2
ANA IN AMP
VOLUME
CONTROL
(VLS1,VLS0) 3
(VOL2,VOL1,VOL0) 1 (VLP D)
4.5 SPEAKER AND AUX OUT DESCRIPTION
Sp eaker
SP+
SP–
AUX OUT
Car Kit
(1 Vp-p Max )
ANA I N AMP
OUTPUT
MUX
FILTO
SUM 2
2
VOL
(OPS1,OPS0)
2
(OPA1, OPA0)
INS0
1514131211109876543210
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
VLPD CONDITION
0Power Up
1Power Down
VLS1 VLS0 SOURCE
0 0 ANA IN AMP
01SUM2
10SUM1
11INP
VOL2 VOL1 VOL0 ATTENUATION
000 0 dB
001 4 dB
010 8 dB
0 1 1 12 dB
1 0 0 16 dB
1 0 1 20 dB
1 1 0 24 dB
1 1 1 28 dB
INS0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLS1 VLS0 VOL2 VOL1 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
VOL0
OPS1 OPS0 SOURCE
00VOL
0 1 ANA IN
10FILTO
11SUM2
OPA1 OPA0 SPKR DRIVE AUX OUT
0 0 Power Down Power Down
01
3.6 VP-P @ 150 ΩPower Down
10
23.5 m Watt @ 8 ΩPower Down
1 1 Power Down 1 VP-P Max @ 5 KΩ
October 2000 Page 24
4.6 ANA OUT DESCRIPTION
Chip Set
ANA OUT+
ANA OUT–
*VOL
*FILTO
*SUM2
3 (A OS2,A OS1,AOS0 )
*FTHRU
1
(AOPD)
*INP
*SUM1
(1 Vp- p max. from AUX I N or ARRAY)
(694 mV p-p max. from microphone input)
INS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AI G1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
4.7 ANALOG INPUTS
4.7.1 Microphone Inputs
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier or directly to the AN A
OUT M UX, de pe nding on the selecte d pa th. The direct pa th to the ANA O UT M UX ha s a ga in of 6 dB so
a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA
OUT pins. The AGC circuit has a range of 45 dB in order t o d eliv er a n ominal 694 mV p-p in to the s tor age
array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is typically 10kΩ.
The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC
circuit. I t should ha ve a 4 . 7 µF ca pacitor conne cte d to ground. I t ca nnot be le ft floa ting. T his is be ca use
the ca pac itor is a lso use d in the playba ck mode for the AutoM ute circuit. This cir cuit re duces the a m ount
of noise present in the output durin g quiet paus es. Tying this pin to ground gi ves maximum gain; t o VCCA
gives minimum gain for the AGC amplifier but will cancel the AutoMute function.
MIC+
MIC–
ACAP
FTHRU
AGC
1 (AGPD)
6 dB
To AutoMute
(Playback Only)
*
* Differential Path
AGC
1514131211109876543210
VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
AGPD CONDITION
0Power Up
1Power Down
AOS2 AOS1 AOS0 SOURCE
0 0 0 FTHRU
001INP
010VOL
011FILTO
100SUM1
101SUM2
110N/C
111N/C
AOPD CONDITION
0Power Up
1Power Down
*DIFFERENTIAL PATH
MIC IN
October 2000 Page 25
A NA IN (Analog Input)
The ANA IN p in is the analog input from the telephone chip set. It can be switched (by the I2C interface) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1 .11 V p-p when at it s minim um ga in (6 dB ) sett ing. Ther e is additi onal gain available, if re q uired, in 3 dB
steps, up to 15 dB. The gain settings are controlled from the I2C interface.
ANA IN Input Modes
ANA IN Amplifier Gain Settings
1. Gain from ANA IN to SP+/-
2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing.
This level is typically 3 dB below clipping
4. Speaker Out gain set to 1.6 (High). (Differential)
Gain
Setting Resistor Ratio
(Rb/Ra) Gain Gain2
(dB)
00 63.9 / 102 0.625 -4.1
01 77.9 / 88.1 0.883 -1.1
10 92.3 / 73.8 1.250 1.9
11 106 / 60 1.767 4.9
CFG0Setting(1) 0TLP Input
VP-P(3)
AIG1 AIG0
Gain(2) Array
In/Out VP-P
Speaker
Out VP-P(4)
6 dB 1.110 0 0 0.625 0.694 2.22
9 dB 0.785 0 1 0.883 0.694 2.22
12 dB 0.555 1 0 1.250 0.694 2.22
15 dB 0.393 1 1 1.767 0.694 2.22
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the ISD5116, such as from the microphone circuit in a mobile phone
“car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the following table.
Additional gain is available in 3 d B steps (control led by the I2C int e rface) up to 9 dB.
October 2000 Page 26
A UX IN Input Modes
AUX IN Amplifier Gain Settings
CFG0
Setting(1) 0TLP Input
VP-P(3) AIG1 AIG0 Gain(2) Array
In/Out VP-P
Speaker
Out VP-P(4)
0 dB 0.694 0 0 1.00 0.694 0.694
3 dB 0.491 0 1 1.41 0.694 0.694
6 dB 0.347 1 0 2.00 0.694 0.694
9 dB 0.245 1 1 2.82 0.694 0.694
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is
typically 3 dB below cl ipp ing
4. Differential
Gain
Setting Resistor Ratio
(Rb/Ra) Gain Gain(2)
(dB)
00 40.1 / 40.1 1.0 0
01 47.0 / 33.2 1.41 4 3
10 53.5 / 26.7 2.0 6
11 59.2 / 21 2.82 9
Page 27
5 DIGITAL MODE
5.1 WRITING DATA
The Digital Write function allows the user to select a portion of the array to be used as digital
memory. The partition between analog and digital memory is left up to the user. A page can
only be either Digital or Analog, not both. The minimum addressable block of memory in the
digital mode is one block or 64 bits, when reading or writing. The address sent to the device
is the 11-bit row (or page) address with the 5-bit scan (or block) address. However, one must
send a Digital Erase before attempting to change digital data on a page. This means that
even when changing only one of the 32 blocks, all 32 will need to be rewritten to the page.
After the address is entered, the data is sent in one-byte packets followed by an I2C
acknowledge generated by the chip. Data for each block is sent MSB first. The data transfer
is ended when the master generates an I2C STOP condition. If only a partial block of data is
sent before the STOP condition, zero is “written” in the remaining bytes; that is, they are left at
the erase level. An erased page (row) will be read as all zeros. The device can buffer up to
two blocks of data. If the device is unable to accept more data due to the internal write
process, the SCL line will be held LOW indicating to the master to halt data transfer. If the
device encounters an overflow condition, it will respond by generating an interrupt condition
and an I2C Not Acknowledge signal after the last valid byte of data. Once data transfer is
terminated, the device needs up to two cycles (64 us) to complete its internal write cycle
before another command is sent. If an active command is sent before the internal cycle is
finished, the part will hold SCL LOW until the current command is finished.
5.2 READING DATA
The Digital Read command utilizes the combined I2C command format. That is, a command is
sent to the chip using the write data direction. Then the data direction is reversed by sending
a repeated start condition, and the slave address with R/W set to 1. After this, the slave
device (ISD5116) begins to send data to the master until the master generates a Not
Acknowledge. If the part encounters an overflow condition, the INT pin is pulled LOW. No
other communication with the master is possible due to the master generating ACK signals.
As with Digital Write, Digital Read can be done a “block” at a time. Thus, only 64 bits need be
read in each Digital Read command sequence.
5.3 ERASING DATA
The Digital Erase command can only erase an entire page at a time. This means that only the
D1 command needs to include the 11-bit page address; the 5-bit for block address are left at
00000.
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if
a block has been previously written then the entire page of 2048 bits must be erased in order
to re-write (or change) a block.
A sequence might be look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page
Page 28
5.4 EXAMPLE COMMAND SEQUENCES
An explanation and graphical representation of the Write, Read and Erase operations are
found below.
1. Write digital data
For the normal digital addressed mode the Registers are loaded as follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = “0” (Write)
3. Slave responds back with an ACK.
4. Wait for SCL HIGH
5. Host sends a byte to Slave - (Command Byte = C9h)
6. Slave responds with an ACK
7. Wait for SCL HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK
10. Wait for SCL HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL HIGH
14. Host sends a byte to Slave - (First 8 bits of digital information)
15. Slave responds with an ACK
16. Wait for SCL HIGH
17. Steps 14, 15 and 16 are repeated until last byte is sent and acknowledged
18. Host executes I2C STOP
SSLAVE ADDRESS
A
W
Command Byte
C9h
A
DATA
A
DATA A
High Addr. Byte Low Addr. Byte
DATA
A
DATA A
~
~ ~
~
PDATA A
October 2000 Page 29
2. Read digital data
For a normal digital read, the Registers are loaded as follows:
1. Host executes I2C START
2. Send Slave Address with R/W bit = “0” (Write)
3. Slave responds back with an ACK
4. Wait for SCL HIGH
5. Host sends a byte to Slave - (Command Byte = E1)
6. Slave responds with an ACK
7. Wait for SCL HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK.
10. Wait for SCL HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL HIGH
14. Host sends repeat START
15. Host sends Slave Address with R/W bit = 1 (Reverses Data Direction)
16. Slave responds with an ACK
17. Wait for SCL HIGH
18. Slave sends a byte to Host - (First 8 bits of digital information)
19. Host responds with an ACK
20. Wait for SCL HIGH
21. Steps 18, 19 and 20 ar e repeated until last byte is sent and a NO ACK is returned
22. Host executes I2C STOP
A
SSL AVE ADDRES S W
Command Byte
C9h
A
DATA
A
DATA A
High Addr. Byt e Low Addr. Byte
DATA
A
DATA A
~
~~
~
PDATA N
A
SSLAV E AD DR ESS R
Page 30
3. Erase digital data
1. Host executes I2C START
2. Send Slave Address with R/W bit = “0” (Write)
3. Slave responds back with an ACK
4. Wait for SCL to go HIGH
5. Host sends a byte to Slave - (Command Byte = D1)
6. Slave responds with an ACK
7. Wait for SCL to go HIGH
8. Host sends a byte to Slave - (High Address Byte)
9. Slave responds with an ACK.
10. Wait for SCL to go HIGH
11. Host sends a byte to Slave - (Low Address Byte)
12. Slave responds with an ACK
13. Wait for SCL to go HIGH
14. Host executes I2C STOP
15. Host counts RAC cycles to track where the chip is in the erase operation.
16. Host determines erase of final row has begun
17. Host executes I2C START
18. Send Slave Address with R/W bit = “0” (Write)
19. Slave responds back with an ACK
20. Wait for SCL to go HIGH
21. Host sends a byte to Slave - (Command Byte = 80)
22. Slave responds back with an ACK
23. Wait for SCL to go HIGH
24. Host executes I2C STOP
AS SLAVE ADDRESS W
Command Byte
D1h ADATA ADATA A
High Addr. Byte Low Addr. Byte
A
SSLAVE ADDRESS W
P
Command Byte
80h
Erase starts on falling
edge of Slave
acknowledge
Note 2
"N" RAC cycles
Note 3.
Last erased row
Note 4.
AP
Notes
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low
Address Byte will be ignored.
2. I2C bus is released while erase proceeds. Other devices may use the bus until it is
time to execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end
of each erased row. The erase of the "next" row begins with the rising edge of RAC.
See the Digital Erase RAC timing diagram on page 32.
4. When the erase of the last desired row begins, the following STOP command
(Command Byte = 80 hex) must be issued. This command must be completely given,
including receiving the ACK from the Slave before the RAC pin goes HIGH .25
microseconds before the end of the row.
October 2000 Page 31
6 PIN DESCRIPTIONS
6.1 DIGITAL I/O PINS
SCL (Serial Clock Line)
T he S eria l Clock Line is a bi- dire ctiona l clock line . It is an ope n-dra in line re quiring a pull- up resistor to
Vc c. I t is driv en by the "mas ter" chips in a system a nd con trols t he tim ing of the data exc hanged ov er the
Serial Data Line.
SDA (Serial Data Line)
T he S eria l D ata Line carrie s the da ta be twe en de vice s on the I 2C inte rfa ce. Da ta must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bi-
directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency, the
duration of this period is 256 ms. There are 2048 pages of memory in the ISD5116 devices. RAC stays
HIGH for 248 ms and stays LOW for the remaining 8 ms bef ore it reaches the end of the page.
1 R OW
RAC Waveform
During 8 KHz Operation
256 m sec
T
RAC
8 m se c
T
RACLO
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing mode.
See the Timing Parameters table on page 39 for R AC timing inf ormation a t ot he r sam ple rate s . When a
re cord comma nd is first initia ted, the RAC pin rema ins H IG H for an e xtra T RACLO period, to load sa mple
and hold circuits internal to the device. The RAC pin can be used for message management techniques.
1 RO W
RAC W aveform
During M essage Cu eing
500 usec
T
RAC
1 5 .6 us
T
RACLO
October 2000 Page 32
RAC Waveform During Digital Erase
Sample Rate 4.0 kHz 5.3 kHz 6.4 kHz 8.0 kHz
tRAC 2.5µs 1.87µs 1.56µs 1.25µs
tRACL0 0.5µs 0.37µs 0.31µs 0.25µs
tRACL1 2.0µs 1.50µs 1.25µs 1.00µs
INT (Interrupt)
I N T is a n ope n dra in output pin . T he IS D5116 int e rrupt pin goes LO W and s ta ys LO W whe n an Ove rflo w
(OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF
generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
The external clock input for the ISD5116 product has an internal pull-down device. Normally, the ISD5116
is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If
greater precision is required, the devic e can be clocked through the XCLK pin at 4.096 MHz as described
in Section 4.3 on page 22.
Because the anti-aliasing and smoothing filters track the Sample R ate Select bits, one must, for optimum
performance, maintain the external clock at 4.096 MHz AND set the Sample Rate Configuration bits to
one of the four values to properly set the filters to the correct cutoff frequency as described in Section 4. 3
on page 2 2. T he duty cycle on the input clock is not critica l, as the clock is immediately divided by two
internally. If the XCLK is not used, this input should be connected to VSSD.
External Clock Input Table
Duration
(Minutes) Sample Rate
(kHz) Required Clock
(kHz) FLD1 FLD0 Filter Knee (kHz)
8.73 8.0 4096 0 0 3.4
10.9 6.4 4096 0 1 2.7
13.1 5.3 4096 1 0 2.3
17.5 4.0 4096 1 1 1.7
A0, A1 (Address Pins)
These two pins a r e norm ally strapped for the desired address that the ISD5116 will h ave on th e I2C serial
interface. If there are four of these devices on the bus, then each must be strapped differently in order to
allow the Master device to address them individually. The possible addresses range from 80h to 87h,
de pend ing upon whe the r the de v ice is be ing written to, or re ad from , by the hos t. T he ISD5116 ha s a 7-
bit sla ve a ddress of which only A0 and A1 are pin programmable. T he e ighth bit ( LSB) is the R /W bit.
Thus, the ad dress will be 1000 0xy0 or 1000 0xy1. (See the table in section 3.1.1 on page 9.)
.25 µsec
1.25 µsec
October 2000 Page 33
6.2 ANALOG I/O PINS
MIC+, MIC- (Microphone Input +/-)
The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the AN A
OU T MUX, de pen ding on th e selected pa t h. The d ire c t pa th t o the ANA OUT M UX has a gain of 6 dB s o
a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA
OUT pins. The AGC circuit has a range of 45 dB in or der t o deliver a n ominal 694 mV p-p into t he s tor age
array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is typically 10 kΩ.
ANA OUT+, ANA OUT- (Analog Output +/-)
This diff e re ntia l outp ut is de signed to go to the m icrophone i nput of the t e le phone chip s e t. I t is de signed
to drive a minimum of 5 kΩ be twe e n the “+” and “–” pins to a nominal voltage level of 700 mV p-p. Both
pins have DC bias of approximately 1.2 VDC. T he AC signa l is superimposed upon this ana log ground
volta g e . The s e pins ca n be use d s ingle -e n de d, getting onl y ha lf the v olta ge . D o NOT grou nd the unuse d
pin.
ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the
ca pacitor is a lso used in the pla yba ck mode for the AutoMute circuit. This circuit re duce s the amount of
noise pre se nt in the output during quie t pa use s. Tying this pin to ground give s ma ximum ga in; tying it to
VCCA gives minimum gain for the AGC amplifier but cancels the AutoMute function.
SP +, SP- (Speak e r +/-)
T his is the spe a ke r diffe re ntia l output circuit. I t is de signe d t o drive a n 8 Ω spe a ke r conne cte d a cross the
speaker pins up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32 and
1.6, whic h can b e chosen through the conf igurat ion reg isters. These pins are biased to approx im ately 1.2
VD C a nd, if use d single-ende d, must be capa citively coupled to their loa d. D o NOT ground the unused
pin.
Internal to the device
NOTE: fCUTOFF=2πRaCCOUP
1
FTHRU
CCOUP=0.1
µ
F Ra=10kΩ
6 dB
MIC IN
VCC
10kΩ
0.1 µF
1.5kΩ
Electret
Microphone
WM-54B
Panasonic
+
220 µF
1.5kΩ
1.5kΩ
AGC
MIC+
MIC-
October 2000 Page 34
AUX OUT (Auxiliary Output)
T he AU X O U T is a n a ddit iona l a udio out put pin to be use d, for e xa m ple, to drive the spe a ke r circuit in a
“car kit.” It drives a minimum load of 5 kΩ and up to a maximum of 1 V p-p. The AC signal is
superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load.
Speaker
SP+
SP–
AU X OU T
Car Kit
(1 Vp-p Max)
ANA IN AMP
OUTPUT
MUX
FILTO
SUM2
2
VOL
(OPS1,OPS0)
2
(OPA1, OPA0)
INS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
CFG0
A NA IN (Analog Input)
The ANA IN p in is the analog input from the telephone chip set. It can be switched (by the I2C interface) to
the speaker output, the array input or to various other paths. This pin is designed to accept a nominal
1 .11 V p-p when at it s minim um ga in (6 dB ) sett ing. Ther e is additi onal gain available, if re q uired, in 3 dB
steps, up to 15 dB. The gain settings are controlled from the I2C interface.
ANA IN Input Modes
Gain
Setting Resistor Ratio
(Rb/Ra) Gain Gain2
(dB)
00 63.9 / 102 0.625 -4.1
01 77.9 / 88.1 0.88 -1.1
10 92.3 / 73.8 1.25 1.9
11 106 / 60 1.77 4.9
OPS1 OPS0 SOURCE
00VOL
0 1 ANA IN
10FILTO
11SUM2
OPS1 OPA0 SPKR DRIVE AUX OUT
0 0 Power Down Power Down
0 1 3.6 Vp.p @150ΩPower Down
1 0 23.5 mWatt @ 8ΩPower Down
1 1 Power Down 1 Vp.p Max @ 5KΩ
October 2000 Page 35
ANA IN Amplifier Gain Settings
CFG0
Setting(1) 0TLP Input
VP-P(3) AIG1 AIG0 Gain(2) Array
In/Out VP-P
Speaker
Out VP-P(4)
6 dB 1.110 0 0 0.625 0.694 2.22
9 dB 0.785 0 1 0.883 0.694 2.22
12 dB 0.555 1 0 1.250 0.694 2.22
15 dB 0.393 1 1 1.767 0.694 2.22
1. Gain from ANA IN to SP+/-
2. Gain from ANA IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clippi ng
4. Speaker Out gain set to 1.6 (High). (Differential)
AUX IN (Auxiliary Input)
The AUX IN is an a dd itiona l audi o input to the I S D511 6 , s uch a s f rom the m icrophone circui t in a m obile
phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the
AUX IN Amplifier G ain Settings table o n pa ge 26. Additional gain is ava ilable i n 3 dB st e ps (c ontrolled
by the I2C interface) up to 9 dB.
A UX IN Input Modes
AUX IN Amplifier Gain Settings
CFG0
Setting(1) 0TLP Input
VP-P(3) AIG1 AIG0 Gain(2) Array
In/Out VP-P
Speaker
Out VP-P(4)
0 dB 0.694 0 0 1.00 0.694 0.694
3 dB 0.491 0 1 1.41 0.694 0.694
6 dB 0.347 1 0 2.00 0.694 0.694
9 dB 0.245 1 1 2.82 0.694 0.694
1. Gain from AUX IN to ANA OUT
2. Gain from AUX IN to ARRAY IN
3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clippi ng
4. Differential
Gain
Setting Resistor Ratio
(Rb/Ra) Gain Gain(2)
(dB)
00 40.1 / 40.1 1.0 0
01 47.0 / 33.2 1.41 4 3
10 53.5 / 26.7 2.0 6
11 59.2 / 21 2.82 9
October 2000 Page 36
6.3 POWE R AND GROUND PINS
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the ISD5116 device use separate power busses.
These +3 V busses lead to separate pins. Tie the VCCD pins toge the r a s close a s possible a nd decouple
both supplies as near to the pa ckage as possib le.
VSSA, VSSD (Ground Inputs)
The ISD51 16 series utilizes separate analog and digital ground busses. The analog ground ( VSSA) pins
should be tied together as close to the package as possible and connected through a low-impedance
pa th to powe r supply ground. T he digita l ground ( V SSD) pin should be conne cte d through a sepa ra te low
impedance p a th to po we r s upply groun d. T he s e ground pat hs should be large e nough to e nsure t ha t the
impedance b etween the VSSA pins a nd the V SSD pin is le ss than 3Ω. The back side of the die is con ne c ted
to VSSD through the substrate resistance. In a chip-on-board design, the die attach area must be con-
nec ted to VSSD.
NC (Not Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or VCC, may result in incorrect device behavior or cause damage to the device.
6.4 SAMPLE PC LAYOUT
The SOIC package is illustrated from the top. PC board traces and the three chip capacitors are on the
bottom side of the board.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
V
C
C
D
XCLK
Analog Ground
1
VSSA
To
VCCA
V
S
S
D
(Digital Ground)
Note 1: VSSD traces should be kept
separated back to the VSS supply feed
point..
Note 2: VCCD traces should be kept
separate back to the VCC Supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
VCCA and VCCD supplies will also need
filter capacitors per good engineering
pr acti ce (typ . 50 to 100 uF).
C1
C2
C3
Note 1
Note 2
C1=C2=C3=0.1 uF ch ip Cap acit ors
Note 3
Note 3
October 2000 Page 37
7 ELECTRICAL CHARACTERISTICS AND PARAMETERS
7.1 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Packaged Parts)(1)
Condition Value
Junction temperature 1500C
Storage temperature range -650C to +1500C
Voltage Applied to any pin (VSS - 0.3V) to (VCC + 0.3 V)
Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VCC + 1.0V)
Lead temperature (soldering – 10 seconds) 3000C
VCC - VSS -0.3V to +5.5V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
Absolute Maximum Ratings (Die)(1)
Condition Value
Junction temperature 1500C
Storage temperature range -650C to +1500C
Voltage Applied to any pad (VSS - 0.3V) to (VCC + 0.3 V)
VCC - VSS -0.3V to +5.5V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
Operating Conditions (Packaged Parts)
Condition Value
Commercial operating temperature range(1) 00C to +700C
Ex tended operatin g tem perature(1) -200C to +700C
Industrial operatin g tem perature(1) -400C to +850C
Supply voltage (VCC)(2) +2.7V to +3.3V
Ground voltage (VSS)(3) 0V
1. Case temperature 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD
Operating Conditions (Die)
Condition Value
Die operating temper ature range(1) 00C to +500C
Supply voltage (VCC)(2) +2.7V to +3.3V
Ground voltage (VSS)(3) 0V
1. Case temperature 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD
October 2000 Page 38
7.2 PARAMETERS
General Parameters
Symbol Parameters Min(2) Typ(1) Max(2) Units Conditions
VIL Input Low Voltage VCC x 0.2 V
VIH Input High Voltage VCC x 0.8 V
VOL SCL, SDA Output Lo w Voltage 0.4 V IOL = 3 mA
VIL2V Input low voltage for 2V
interface 0.4 V Apply only to SCL,
SDA
VIH2V Input high voltage for 2V
interface 1.6 V Apply only to S CL,
SDA
VOL1 RAC, INT Output Low Voltage 0.4 V IOL = 1 mA
VOH Output High Voltage VCC – 0.4 V IOL = -10 µA
ICC VCC Current (Operating)
- Playback
- Record
- Feedthrough
15
30
12
25
40
15
mA
mA
mA
No Load(3)
No Load(3)
No Load(3)
ISB VCC Current (Standby) 1 10 µA(3)
IIL Input Leakage Current +/-1 µA
1. Typical values: TA = 25°C and Vcc = 3.0 V.
2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are
100 percent tested.
3. VCCA and VCCD summed together.
October 2000 Page 39
Timing Parameters
Symbol Parameters Min(2) Typ(1) Max(2) Units Conditions
FSSampling Frequency 8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
(5)
(5)
(5)
(5)
FCF Filter Knee
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
Knee Point(3)(7)
Knee Point(3)(7)
Knee Point(3)(7)
Knee Point(3)(7)
TREC Record Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8.73
10.9
13.1
17.5
min
min
min
min
(6)
(6)
(6)
(6)
TPLAY Playback Duration
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8.73
10.9
13.1
17.5
min
min
min
min
(6)
(6)
(6)
(6)
TPUD Power-Up Delay
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1
1
1
1
msec
msec
msec
msec
TSTOP OR PAUSE Stop or Pause
Record or Play
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
32
40
48
64
msec
msec
msec
msec
TRAC RAC Clock Period
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
256
320
384
512
msec
msec
msec
msec
(9)
(9)
(9)
(9)
TRACLO RAC Clock Low Time
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
8
10
12.1
16
msec
msec
msec
msec
TRACM RAC Clock Period i n
Mes sage Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
500
625
750
1000
µsec
µsec
µsec
µsec
October 2000 Page 40
TRACE RAC Clock Period i n
Erase Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
1.25
1.56
1.87
2.50
msec
msec
msec
msec
TRACML RAC Clock Low Time in
Mes sage Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
15.6
19.5
23.4
31.2
µsec
µsec
µsec
µsec
THD Total Harmonic Distortion
ANA IN to ARRAY,
ARRAY to SPKR 1
12
2%
%
@1 KHz at 0TLP,
sample rate = 5.3 KHz
Analog Parameters
MICROPHONE INPUT(14)
Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions
VMIC+/- MIC +/- Input Voltage 300 mV Peak-to-Peak(4)(8)
VMIC (0TLP) MIC +/- input reference
transmission level point
(0TLP)
208 mV Peak-to-Peak(4)(10)
AMIC Gain from MIC +/- input to
ANA OUT 5.5 6.0 6.5 dB 1 kHz at VMIC (0TLP)(4)
AMIC (GT) MIC +/- Gain Tracking +/-0.1 dB 1 kHz, +3 to –40 dB
0TLP Input
RMIC Microphone input resistance 10 kΩMIC- and MIC+ pins
AAGC Microphone AGC Amplifier
Range 6 40 dB Over 3-300 mV Range
ANA IN(14)
Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions
VANA IN ANA IN Input Voltage 1.6 V Peak-to-Peak (6 dB gain
setting)
VANA IN (0TLP) ANA IN (0TLP) Input Voltage 1.1 V Peak-to-Peak (6 dB gain
setting)(10)
AANA IN (sp) Gain from ANA IN to SP+/- +6 to +15 dB 4 Steps of 3 dB
AANA IN (AUX OUT) Gain from ANA IN to AUX
OUT -4 to +5 dB 4 Steps of 3 dB
AANA IN (GA) ANA IN Gain Accuracy -0.5 +0.5 dB (11)
AANA IN (GT) ANA IN Gain Tracking +/-0.1 dB 1000 Hz, +3 to –45 dB
0TLP Input,
6 dB setting
RANA IN ANA IN Input Resistance (6
dB to +15 dB) 10 to 100 kΩDepending on ANA IN
Gain
Page 41
AUX IN(14)
Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions
VAUX IN AUX IN Input Voltage 1.0 V Peak-to-Peak (0 dB gain
setting)
VAUX IN (0TLP) AUX IN (0TLP) Input Voltage 694.2 mV Peak-to-Peak (0 dB gain
setting)
AAUX IN (ANA OUT) Gain from AUX IN to ANA
OUT
0 to +9 dB 4 Steps of 3 dB
AAUX IN (GA) AUX IN Gain Accuracy -0.5 +0.5 dB (11)
AAUX IN (GT) AUX IN Gain Tracking +/-0.1 dB 1000 Hz, +3 to –45 dB
0TLP Input, 0 dB setting
RAUX IN AUX IN Input Resistance 10 to 100 kΩ Depending on AUX IN
Gain
SPEAKER OUTPUTS(14)
Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions
VSPHG SP+/- Output Voltage (High
Gain Setting)
3.6 V Peak-to-Peak, differential
load = 150Ω, OPA1,
OPA0 = 01
RSPLG SP+/- Output Load Imp. (Low
Gain)
8
Ω OPA1, OPA0 = 10
RSPHG SP+/- Output Load Imp. (High
Gain)
70 150 Ω OPA1, OPA0 = 01
CSP SP+/- Output Load Cap. 100 pF
VSPAG SP+/- Output Bias Voltage
(Analog Ground)
1.2 VDC
VSPDCO Speaker Output DC Offset +/-100 mV
DC
With ANA IN to Speaker,
ANA IN AC coupled to
VSSA
ICNANA IN/(SP+/-) ANA IN to SP+/- Idle Channel
Noise
-65 dB Speaker Load =
150Ω(12)(13)
CRT(SP+/-)/ANA
OUT
SP+/- to ANA OUT Cross
Talk
-65 dB 1 kHz 0TLP input to ANA
IN, with MIC+/- and AUX
IN AC coupled to VSS,
and measured at ANA
OUT feed through mode
(12)
PSRR Power Supply Rejection Ratio -55 dB Measured with a 1 kHz,
100 mV p-p sine wave
input at VCC and VCC pins
FR Frequency Response (300-
3400 Hz)
+0.5 dB With 0TLP input to ANA
IN, 6 dB setting (12)
Guaranteed by design
POUTLG Power Output (Low Gain
Setting)
23.5 mW
RMS
Differential load at 8Ω
SINAD SINAD ANA IN to SP+/- 62.5 dB 0TLP ANA In input
minimum gain, 150Ω
load (12)(13)
Page 42
ANA OUT (14)
Symbol Parameters Min
(2)
Type
(1)(14)
Max (2) Units Conditions
SINAD SINAD, MIC IN to ANA OUT 62.5 dB Load = 5kΩ(12)(13)
SINAD SINAD, AUX IN to ANA OUT
(0 to 9 dB)
62.5 dB
Load = 5kΩ(12)(13)
ICONIC/ANA OUT Idle Channel Noise –
Microphone
-65 dB
Load = 5kΩ(12)(13)
ICN AUX IN/ANA
OUT
Idle Channel Noise – AUX IN
(0 to 9 dB)
-65 dB
Load = 5kΩ(12)(13)
PSRR (ANA OUT) Power Supply Rejection Ratio -55 dB Measured with a 1 kHz,
100 mV P-P sine wave to
VCCA, VCCD pins
VBIAS ANA OUT+ and ANA OUT- 1.2 VDC Inputs AC coupled to
VSSA
VOFFSET ANA OUT+ to ANA OUT- +/- 100 mV
DC
Inputs AC coupled to
VSSA
RL Minimum Load Impedance 5 kΩ Differential Load
FR Frequency Response (300-
3400 Hz)
+0.5 dB 0TLP input to MIC+/- in
feedthrough mode.
0TLP input to AUX IN in
feedthrough mode(12)
CRTANA OUT/(SP+/-) ANA OUT to SP+/- Cross
Talk
-65 dB 1 kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
measured at SP+/-(12)
CRTANA OUT/AUX
OUT
ANA OUT to AUX OUT Cross
Talk
-65 dB 1 kHz 0TLP output from
ANA OUT, with ANA IN
AC coupled to VSSA, and
measured at AUX
OUT(12)
AUX OUT(14)
Symbol Parameters Min(2) Typ(1(14)) Max(2) Units Conditions
VAUX OUT AUX OUT – Maximum Output
Swing
1.0 V
5kΩ Load
RL Minimum Load Impedance 5 KΩ
CL Maximum Load Capacitance 100 pF
VBIAS AUX OUT 1.2 VDC
SINAD SINAD – ANA IN to AUX OUT 62.5 dB 0TLP ANA IN input,
minimum gain, 5k
load(12)(13)
ICN(AUX OUT) Idle Channel Noise – ANA IN
to AUX OUT
-65 dB
Load=5kΩ(12)(13)
CRTAUX OUT/ANA
OUT
AUX OUT to ANA OUT Cross
Talk
-65 dB 1 kHz 0TLP input to ANA
IN, with MIC +/- and AUX
IN AC coupled to VSSA,
measured at SP+/-, load
= 5kΩ. Referenced to
nominal 0TLP @ output
October 2000 Page 43
VOLUME CONTROL(14)
Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions
AOUT Output Gain -28 to 0 dB 8 steps of 4 dB,
referenced to output
Absolute Gain -0.5 +0.5 dB ANA IN 1.0 kHz 0TLP, 6
dB gain setting
me asured differentially at
SP+/-
1. Typical values: TA = 25°C and Vcc = 3.0V.
2. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications
are 100 percent tested.
3. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions).
4. Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
5. Sampling frequency can var y as much as –6/+4 percent over the industrial temperature and voltage
ranges. For greater stability, an external clock can be utilized (see Pin Descriptions).
6. Playback and Record Duration can vary as much as –6/+4 percent over the industrial temperature and
voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions).
7. Filter specification applies to the low pass filter.
8. For optimal signal quality, this maximum limit is recommended.
9. When a record comm and is sent, TRAC = TRAC + TRACLO on the first page addressed.
10. The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission level
point. (0TLP) This is the point where signal clipping may begin.
11. Measured at 0TLP point for each gain setting. See the ANA IN table and AUX IN table on pages 25 and
26 respectively.
12. 0TLP is the reference test level through inputs and outputs. See the ANA IN table and AUX IN table on
pages 25 and 26 respectively.
13. Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
14. For die, only typic al valu es are applicable.
October 2000 Page 44
I2C Interface Timing
STANDARD-MODE FAST-MODE
PARAMETER SYMBOL MIN. MAX. MIN. MAX. UNIT
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
tHD; STA 4.0 - 0.6 - µs
LOW period of the SCL clock tLOW 4.7 - 1.3 - µs
HIGH period of the SCL clock tHIGH 4.0 - 0.6 - µs
Set-up time for a repeated START
condition tSU; STA 4.7 - 0.6 - µs
Data set-up time tSU; DAT 250 - 100(1) -ns
Rise time of both SDA and SCL
signals tr- 1000 20 + 0.1Cb(2) 300 ns
Fall time of both SDA and SCL
signals tf- 300 20 + 0.1Cb(2) 300 ns
Set-up time for STOP condition tSU; STO 4.0 - 0.6 - µs
Bus-free time between a STOP and
START condition tBUF 4.7 - 1.3 - µs
Capacitive load for eac h bus line Cb- 400 - 400 pF
Noi se margin at the LOW level for
each connected device (including
hysteresis)
VnL 0.1 VDD - 0.1 VDD -V
Noise margin at the HIGH level for
each connected device (including
hysteresis)
VnH 0.2 VDD - 0.2 VDD -V
1. A Fast-mode I2C-interface device can be used in a Standard-mode I2C-interface system, but the requirement
tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line;
tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C -interface specification) before the
SCL line is released.
2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed.
October 2000 Page 45
8 TIMING DIAGRAMS
8.1 I2C TIMING DIAGRAM
8.2 PLAYBACK AND STOP CYCLE
SDA
SCL
ANA IN
ANA OUT
DATA CLOCK PULSES
STOP
PLAY AT ADDR
t
STOP
t
START
STOP
tLOW
tSCLK
tHIGH
tftr
tSU;DAT
tSU;STO
tf
START
SDA
SCL
STOP
October 2000 Page 46
8.3 EX AMPLE OF POWER UP COMMAND (FIRST 12 BITS)
October 2000 Page 47
9 I2C SERI AL INTERF ACE TECHNICAL INFORMATION
9.1 CHARACTERISTICS OF THE I2C SERIAL INTERF ACE
The I2C inte rfa ce is f or bi- dire ctiona l, two- line comm unica tion be twe e n diffe re nt I C s or m odule s. T he t wo
lines are a seria l data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive
supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not busy.
9.1.1 Bit transfer
One data b it is transf e r re d dur ing each c lock pulse. Th e data on t he S DA l ine m ust r e m a in stable dur ing
the H IGH period of the clock pulse, as changes in the data line at this tim e will be inter preted as a c ontro l
signal.
Bit transfer on the I C-bus
2
data line
stable;
data valid
change
of data
allowed
SDA
SCL
9.1.2 Start and stop conditions
Both da t a a nd cl ock line s re main H IGH whe n the in te rfa ce bus is not bus y. A H I GH-to-LOW transition of
the data line whi le th e c lock is HIGH is defin ed as t he start cond ition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P).
Definition of START and STOP conditions
handbook, full pagewidth
MBC622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
October 2000 Page 48
9.1.3 System configuration
A device generating a message is a ‘transmitter’; a device receiving a message is the ‘receiver’. The
de vice tha t controls the m essa ge is the ‘master’ and the devices that are controlled by the master are the
‘slaves’.
MBC645
SDA
SCL
MICRO -
CONTROLLER STATIC
RAM OR
EEPROM
LCD
DRIVER
GATE
ARRAY ISD 5116
Example of an I C-bus configuration using two microcontrollers
2
9.1.4 Acknowledge
The num ber of data b ytes transf erred b etween t he start an d st op co nd iti ons f rom tr ansm itter to r eceiv er is
unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH le vel
signal put on the interface bus by the transmitter during which time the master generates an extra
acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge
after the rece ption of ea ch byte. I n a ddition, a master receiver must generate an acknowledge afte r the
reception of each byte that has been clocked out of the slave transmitter.
T he device tha t a cknowle dge s must pull down the S D A line during the a cknowle dge clock pulse so tha t
the SD A line is sta ble LOW during the HI GH pe riod of the acknowledge rela ted clock pulse (se t-up a nd
hold times must be taken into consideration). A master receiver must signal an end of data to the
tra nsmitte r by not ge ne ra ting a n a cknowle dge on the la st b yte tha t ha s be e n clocke d out of the sla ve . I n
this event, the transmitter must leave the data line HIGH to enable the master to generate a stop
condition.
Acknowledge on the I2C-bus
MBC602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
October 2000 Page 49
9.2 I2C Protocol
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A S la ve Addre ss consists of 7 bits, followe d by a single bit tha t
indicates the dir e ction of da ta flo w. T his sing le bit is 1 for a Wr ite cycle , which ind ica te s t he da t a is bei ng
sent from the current bus maste r to the de vice being addresse d. T his single bit is a 0 for a Re ad cycle,
which indicates that the data is being sent from the device being addressed to the current bus master. For
example, the valid Slave Addresses for the ISD5116 device, for both Write and Read cycles , are shown in
Section 3.1.1 on page 9 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is a lways sent out as the 1 st byte following the Sta rt
Condition sequence. An example of a Master transm itting an address to a ISD5116 slave is s ho wn below.
In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write cycle. All the bits
transferred are from the Master to the Slave, except for the indicated Acknowledge bits. The following
example details the transfer explained in Section 3.1.2-3 on page 10 of this datasheet.
Master Transmits to Slave Receiver (Write) Mode
SWAAAAPSLAVE ADDRESS COMMAND BYTE Hig h ADDR. BYTE Low ADDR. BYTE
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
Start Bit Stop Bit
A common procedure in the ISD5 116 is the reading of the Status Bytes. The Read Status condition in the
ISD5116 is triggered when the Master addresses the chip with its proper Slave Address, immediately
followed by the R/W bit set to a “0” and with out the Com mand Byte b e in g se nt . This is an e xam ple of the
Master sending to the Sla ve, immediately followed by the Slave sending data back to the Master. T he “N”
not-acknowledge cycle from the Master ends the transfer of data from the Slave. The following example
details the transfer explained in Sec tion 3.1.2-1 on page 9 of this datasheet.
Master Reads from Slave immediately after first byte (Read Mode)
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from sla ve
acknowledgement
from M a s ter
not-acknowledged
from M a s ter
acknowledgement
from M a s ter
From M aster
From Slave From SlaveFrom Slave
SRA A A NPLow ADDR BYTESLAVE ADDRESS STATUS WORD High ADDR. BYTE
Another common operation in the ISD5116 is t he reading of digital data f rom the chip ’s memory a rray at a
specific address. This requires the I2C interface Master to first send an address to the ISD5116 Slave
device, and then receive data from the Slave in a single I2C operation. To accomplish this, the data
direction R/W bit must be changed in the middle of the command. The following example shows the
Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the
ISD5116, and then immediately changing the data direction and reading some number of bytes from the
chip’s digital array. An unlim ited n umber of bytes can be rea d in this operat ion. The “N” not- a ck nowle dge
October 2000 Page 50
cycle from the Master forces the end of the data transfer from the Slave. The following example details
the transfer explained in Section 5.4-2 on page 29 of this datasheet.
Master Reads from the Slave after setting data address in Slave (Write data address, READ Data)
SWA A A ASLAVE ADD RES S COMMAND BYTE High ADDR. BYTE Low ADDR. BYTE
acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave acknowledgement
from slave
R/W
From
Master
Start Bit
From
Master
SRA A A NP8 BITS of DATASLAVE ADDRESS 8 BITS of DATA 8 BITS of DATA
R/W
From
Master
Start Bit
From
Master
Stop Bit
From
Master
acknowledgement
from slave
acknowledgement
from Master
not-acknowled
from Master
acknowledgement
from Master
From Master
From Slave From SlaveFrom Slave
October 2000 Page 51
10 DEVICE PHYSICAL DIMENSIONS
10.1. PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
5
6
7
8
9
10
11
12
13
14
2
3
4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
BG
F
C
D
E
HJ
I
Min Nom Max Min Nom Max
A0.520 0.528 0.535 13.20 13.40 13.60
B0.461 0.465 0.469 11.70 11.80 11.90
C0.311 0.315 0.319 7.90 8.00 8.10
D0.002 0.006 0.05 0.15
E0.007 0.009 0.011 0.17 0.22 0.27
F0.0217 0.55
G0.037 0.039 0.041 0.95 1.00 1.05
H003060003060
I0.020 0.022 0.028 0.50 0.55 0.70
J0.004 0.008 0.10 0.21
Note: Lead coplanarity to be w ithin 0.004 inches.
INCHES MILLIMETERS
Plastic Th in Small Ou tline P ackage (TSOP ) Type E Dimensions
October 2000 Page 52
10.2. PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1234567891011 12 13 14
A
D
E
F
B
G
C
H
Min Nom Max Min Nom Max
A0.701 0.706 0.711 17.81 17.93 18.06
B0.097 0.101 0.104 2.46 2.56 2.64
C0.292 0.296 0.299 7.42 7.52 7.59
D0.005 0.009 0.0115 0.127 0.22 0.29
E0.014 0.016 0.019 0.35 0.41 0.48
F0.050 1.27
G0.400 0.406 0.410 10.16 10.31 10.41
H0.024 0.032 0.040 0.61 0.81 1.02
Note: Lead coplanarit y to be within 0.004 inches.
Plastic Small Outline Integrated Circuit (SOIC) Dimensions
INCHES MILLIMETERS
October 2000 Page 53
10.3 PLASTIC DUAL INLINE PACKAGE (PDIP) DIMENSIONS
Plastic Dual Inline Package (PDIP) (P) Dimensions
October 2000 Page 54
10.4 DIE BONDING PHYSICAL LAYOUT
ISD5116 DEVICE PIN/PAD LOCATIONS WITH RESPECT TO DIE CENTER IN MICRON (µM)
PIN Pin Name X Axis Y Axis
VSSD VSS Digital Ground -1842.90 3848.65
VSSD VSS Digital Ground -1671.30 3848.65
AD0 Address 0 -1369.40 3848.65
SDA Serial Data Address -818.20 3848.65
AD1 Address 1 -560.90 3848.65
SCL Serial Clock Line -201.40 3848.65
VCCD VCC Digita l Supply Voltage 73.20 3848.65
VCCD VCC Digita l Supply Voltage 288.60 3848.65
XCLK External Clock Input 475.60 3848.65
INT Interrupt 787.40 3848.65
RAC Row Address Clock 1536.20 3848.65
VSSA VSS Analog Ground 1879.45 3848.65
VSSA “ “ “-1948.00 -3841.60
MIC+ Non-inverting Microphone Input -1742.20 -3841.60
MIC- Inverting Microphone Input -1509.70 -3841.60
ANA OUT+ Non-inverting Analog Output -1248.00 -3841.60
ANA OUT- Inverting Analog Output -913.80 -3841.60
ACAP AGC/AutoMute Cap -626.50 -3841.60
SP- Speaker Negative -130.70 -3841.60
VSSA VSS Analog Ground 202.90 -3841.60
SP+ Speaker Positive 626.50 -3841.60
VCCA VCC Analog Supply Voltage 960.10 -3841.60
ANA IN Analog Input 1257.40 -3841.60
AUX IN Auxilia ry Input 1523.00 -3841.60
AUX OUT Auxiliary Output 1767.20 -3841.60
October 2000 Page 55
ISD 5116 SERIES BONDING PHYSICAL LAYOUT (1) ( UNPACKAGED DIE)
I SD5116 Series
Die Dim e nsions
X: 4125 um
Y: 8030 um
Die Thic kne s s(3)
292.1 um + 12. 7 um
Pad Opening (min )
90 x 90 mi cr o n s
3.5 x 3.5 mils
VSSD
ISD5116
VSSA
VSSA
MIC+ AUX I N
ANA IN
ANAOUT+
MIC–
VSSA
(2)
ANAOUT–
ACAP
AUXOUT
SP–VCCA(2)
SP+
RAC
VSSDAD0 SDA ADL SCL VCCD VCCD
INT
XCLK
1. The backside of die is internally connected to Vss. It MUST NOT be connected to any other
potential or damage may occur.
2. Double bond recommended.
3. This figure reflects the current die thickness. Pleas e contact ISD as this thickness may change in
the future.
October 2000 Page 56
11 ORDERING INFORMATION
ISD Part Number Description
When ordering ISD5116 series devices, please refer to the following valid part numbers.
Part Number
ISD5116E
ISD5116ED
ISD5116EI
ISD5116S
ISD5116SD
ISD5116SI
ISD5116X
ISD5116P
Chip scale package is available upon customer’s request.
For the latest product information, access our website at www.winbond-usa.com.
Special Temperature Field:
Blank = Commercial Packaged (0°C to +70°C)
or Commercial Die (0°C to + 50°C)
D = Extended (–20°C to +70°C)
I= Industrial (–40°C to +85°C)
Package Type:
E= 28-Lead 8x13.4mm Plastic Thin Small Outline
Package (TSOP) Type 1
S= 28-Lead 0.300-Inch Pl as tic Sm all Outline Package
(SOIC)
X=Die
P= 28-Lead 0.600-Inch Plastic Dual Inline Packa
g
e
(
PDIP
)
Product Family
ISD5116 Product
(8- to 16-minute durations)
ISD5116-_ _
