8
Linear Technology Magazine Vol. 2, No. 1, February 1992
DESIGN FEATURES
Easier Remote or Isolated
Installations
Remote or isolated systems are made
easier for three reasons. First, the serial
data transmission requires fewer wires
than parallel transmission. A system
can be isolated with two opto-isolators,
one to send the clock and one to return
the data. Second, analog signals can be
digitized at the source and sent back in
digital form, increasing noise immunity
and reducing difficulties with analog
isolation. Third, the 3V to 9V single
supply range and the low power con-
sumption makes it easier to get power
to a remote or isolated system. Figure 8
shows a floating system, powered by a
diode-capacitor charge pump and trans-
mitting data with two opto-isolators.
The LTC1096 and 1098 make it
easier to meet the UL and gas regula-
tions, which limit the allowable bypass
capacitor size, by operating with a
smaller bypass capacitor. Improved
power supply rejection and lower cur-
rent allow the use of capacitors as small
as 0.01µF.
Advantages over Microprocessors
with Built-in ADCs
As an alternative, designers of 8-bit
systems can use a microprocessor with
a built in ADC, such as the 68HC11.
The LTC1096/8 can have noise, power,
size, and cost advantages over built-in
ADCs.
The LTC1096 is useful with refer-
ence voltages much lower than 1V.
In contrast, ADCs built into micropro-
cessors can have noise and accuracy
problems as the reference is reduced.
By reducing the LTC1096’s reference, a
system can be designed so that the
ADC is located near the sensor, permit-
ting it to directly digitize the sensor’s
output and transmit digital data to the
microprocessor. This can result
in much lower noise and cost and
smaller size than amplifying and send-
ing analog data to the microprocessor
package. Even in systems where the
signal source is near the microproces-
sor, the noise performance of the
LTC1096 is much better than that of
built-in ADCs.
The power consumption of a system
designed with the LTC1096/8 also can
be much lower than that of a system
with the ADC on the microprocessor. In
many CMOS microprocessors without
ADCs, the supply current can be made
arbitrarily low by reducing the supply
voltage and clock frequency. By putting
the ADC function in the LTC1096/8,
extremely low power consumption can
be achieved because the ADC shuts
down when not taking readings. The
processor can continue to perform op-
erations and timing tasks without any
current being consumed by the ADC.
HOW IT WORKS: THE ADC
DESIGN
The LTC1096 and LTC1098 use a
switched-capacitor, successive-ap-
proximation (SAR) architecture. The
SAR technique provides the best com-
promise among die size, speed, and
power.
Die size must be small in order to
achieve SO-8 packaging. Surprisingly,
speed can be important in micropower
applications that are powered-down
between readings. The faster the sys-
tem can take the required readings, the
less time the power needs to be applied
and the lower the average power con-
sumption will be. Some systems are
powered-up continuously or are con-
strained to long power-on times for
reasons other than ADC conversion
time (for example, sensor settling time).
In these applications, the ADC must
not burn excessive power.
The LTC1096 and 1098 achieve these
goals with a conversion time of 16µs at
an operating supply current of 100µA.
They automatically shut down to 1nA
typically between conversions, as shown
in Figure 5. Adding the power-on wake-
up time and data-transfer time gives a
throughput time of 29µs and a maxi-
mum sample rate of 33kHz.
Comparator
In a switched-capacitor ADC, most
of the power is consumed by the com-
parator. As power is reduced, the pri-
mary concern is to keep the comparator
as fast as possible. There are some
techniques for reducing the power
drain of the DAC, logic, and other
circuitry, but the comparator is the
greatest challenge.
LTC1096 continued from page 7
CLOCK FREQUENCY (Hz)
0.002
SUPPLY CURRENT, I
CC
(µA)
140
100 10k 100k 1M
1098_6. eps
01k
120
100
80
60
40
20
SUPPLY CURRENT vs CLOCK RATE FOR
ACTIVE AND SHUTDOWN MODES
ACTIVE (CS LOW)
SHUTDOWN (CS HIGH)
T
A
= 25°C
V
CC
= 5V
At the low overdrives typically seen
in ADCs, the comparator delay is domi-
nated by the first stage. This is because
the overdrive for later stages is larger
due to the gain of earlier stages. Figure
6a shows the first stage of a compara-
tor. The delay is related to the input
overdrive, the transconductance (g
m
) of
the input stage, the capacitive load on
the output of the first stage, and the
required swing from the first-stage-
output clamp voltage to the trip point of
the second stage.
Before major bit decisions, the input
swings far away from zero and the
output of the first stage swings into
the clamp. (The first-stage output is
clamped because the input of
the comparator cannot be clamped
without losing charge from the sample-
and-hold capacitor.) When the DAC
updates, the comparator input will
swing back to zero and slightly beyond.
In the case of an 8-bit ADC, this over-
drive can be as low as 1mV.
Figure 5. After a conversion, when the
microprocessor drives CS high, the ADC
automatically shuts down until the next
conversion. The supply current, which is
very low during conversions, drops to
zero in shutdown