MIC25400
2A Dual Output PWM Synchronous Buck
Regulator IC
Ramp Control is a trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2011 M9999-020111-C
General Description
The MIC25400 is a synchronous PWM dual output step
down converter with internal 2A high-side switches. The
MIC25400 has an integrated low-side gate driver for
synchronous step-down conversion by connecting an
external N-channel MOSFET to achieve high efficiencies
in low duty-cycle applications. The IC’s switching
frequency is 1MHz. A patented control scheme allows the
use of a wide range of output capacitance from small
ceramic capacitors to large electrolytic types with only one
compensation component. A 2% output voltage tolerance
over the temperature range allows the maximum level of
system performance. The MIC25400 power good signal
allows full control for sequencing the output voltages with
minimum external components.
An adjustable current limit allows the use of smaller
inductors in lower current applications.
The MIC25400 is available in the ePAD 24-pin 4mm x
4mm MLF® package, and has an operating junction
temperature range of –40°C to +125°C.
Features
• 4.5V to 13.2V input voltage range
• Adjustable output voltages down to 0.7V
• 2A per channel
• 180° out of phase operation
• Low-side driver for synchronous operation
• 2% output voltage accuracy (over temperature)
• 1MHz switching frequency
• Output voltage sequencing
• Programmable max current-limit
• Power good output
• Ramp Control™ provides soft-start
• Low-side current sensing allows very low duty-cycle
• Works with ceramic output capacitors
• 24-pin 4mm x 4mm MLF® package
• Junction temperature range of –40°C to +125°C
Applications
• Multi-output power supplies with sequencing
• DSP, FPGA, CPU and ASIC power supplies
• Telecom and networking equipment, servers
_________________________________________________________________________________________________________________________
Typical Application
MIC25400 Dual Output Buck Converter
Micrel, Inc. MIC25400
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Ordering Information
Part Number Voltage Switching
Frequency Temperature Range Package Lead Finish
MIC25400YML Adj 1MHz -40°C to +125°C 24-Pin 4mm x 4mm MLF® Pb-Free
Pin Configur ation
24-Pin 4mm x 4mm MLF® (ML)
Pin Description
Pin Number Pin Name Pin Description
1 BST1
Boost 1 (Input): Provides voltage for high-side internal MOSFET for
channel 1. Connect a 0.01µF capacitor from SW1 to BST1 pin and a
diode-to-PVDD.
2 LSD1
Low-side Drive 1 (Output): External low-side N-Channel MOSFET
driver. Use 4.5V rated MOSFETs.
3 PGND1 Power Ground 1 (Input).
4 CS1
Current Sense 1 (Input): Place a resistor from SW1 to this pin to
program the current limit point from 0.5A to 2.7A.
5 PG1
Power Good 1 (Output): Open drain. Device is in the OFF state. i.e.,
high when output is within 90% of regulation.
6 EN/DLY1
Enable/Delay 1 (Input): This pin can be used to disable VOUT1. When
used to disable VOUT1, this pin must be pulled down to ground in less
than 1µs for proper operation. It is also used for soft-start of the
output. Soft start capacitor range is 4.7nf to 22nf. See the Functional
Description section of this datasheet for additional information.
7 COMP1 Compensation 1 (Input): Pin for external compensation, Channel 1.
8 FB1 Feedback 1 (Input): Input to Ch1 error amplifier. Regulates to 0.7V.
9 NC No Connect.
10 AGND
Analog Ground (Input): Control section ground. Connect to PGND.
11 FB2
Feedback 2 (Input): Input to Channel 2 error amplifier. Regulates to
0.7V.
12 COMP2 Compensation 2 (Input): Pin for external compensation, Channel 2.
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Pin Number Pin Name Pin Description
13 EN/DLY2
Enable/Delay 2 (Input): This pin can be used to disable VOUT2. When
used to disable VOUT2, this pin must be pulled down to ground in less
than 1µs for proper operation. It is also used for soft-start of the
output. Soft start capacitor range is 4.7nf to 22nf. See Functional
Description section for additional information.
14 PG2
Power Good 2 (Output) Open drain. Device is in the OFF state. i.e.,
high when output is within 90% of regulation
15 CS2
Current Sense 2 (Input) Place a resistor from SW2 to this pin to
program the current limit point from 0.5A to 2.7A
16 PGND2 Power Ground 2 (Input)
17 LSD2
Low-side Drive 2 (Output): External low-side N-Channel MOSFET
driver. Use 4.5V rated MOSFETs.
18 BST2
Boost 2 (Input): Provides voltage for high-side internal MOSFET for
Channel 2. Connect a 0.01µF capacitor from SW2 to BST2 pin and a
diode-to-PVDD.
19 SW2 Switch Node 2 (Output): Source of internal high-side power MOSFET.
20 VIND2
Supply voltage (Input): For the drain of internal high-side power
MOSFET 4.5V to 13.2V.
21 PVDD
5V Internal Linear Regulator (Output): PVDD is the external MOSFET
gate drive for LSD1 and LSD2 and an internal supply bus for the IC.
Connect to an external 1µF bypass capacitor. When VIN is <6V, this
regulator operates in drop-out mode. Connect VDD to VIN when VIN
<6V.
22 VIN
Supply voltage (Input): For the internal 5V linear regulator. 4.5V to
13.2V.
23 VIND1
Supply voltage (Input): For the drain of internal high-side power
MOSFET 4.5V to 13.2V.
24 SW1 Switch Node 1 (Output): Source of internal high-side power MOSFET.
EP GND
Exposed thermal pad for package only. Connect to ground. Must
make a full connection to the ground plane to maximize thermal
performance of the package.
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Absolute Maximum Ratings(1)
VIN to PGND .................................................... –0.3V to 16V
VIND1, VIND2 to PGND........................................ –0.3V to 16V
VPVDD to PGND .................................................. –0.3V to 6V
VSW1, VSW2 to PGND ............................ –0.7V to (VIN + 0.3V)
VCS1, VCS2 to PGND ............................. –0.7V to (VIN + 0.3V)
VBST1 to VSW1, VBST2 to VSW2............................ –0.3V to 6.0V
VBST1, VBST2 to PGND....................................... –0.3V to 22V
VEN/DLY1, VEN/DLY2 to PGND...............–0.7V to (VPVDD + 0.3V)
VCOMP1, VCOMP2 to PGND..................–0.7V to (VPVDD + 0.3V)
VFB1, VFB2 to PGND..........................–0.7V to (VPVDD + 0.3V)
VPG1, VPG2 to PGND .........................–0.7V to (VPVDD + 0.3V)
PGND1, PGND2 to AGND ........................... –0.3V to +0.3V
Junction Temperature ................................................ 150°C
Storage Temperature ...............................–65°C to +150°C
Lead Temperature (soldering,10 sec.)....................... 260°C
Operating Ratings(2)
Supply Voltage (VIN)................................... +4.5V to +13.2V
Output Voltage Range (VOUT)……………......0.7V to 0.7*VIN
Maximum Output Current (IOUT)…………….. ...................2A
Junction Temperature (TJ) ........................ –40°C to +125°C
Junction Thermal Resistance
4mm x 4mm MLF-24L (θJA) ...............................35°C/W
Electrical Characteristics(4)
VIN = 12; VEN=5V; VOUT=1.8V; ILOAD=10mA; TA = 25°C, bold values indicate –40°C≤ TJ ≤ +125°C, unless noted.
Parameter Condition Min Typ Max Units
Power Input Supply
Input Voltage Range (VIN) 4.5 13.2 V
Quiescent Supply Current VFB = 0.8V, IOUT = 0A; Both outputs not switching 3.6 7 mA
Shutdown Current VEN1 = VEN2 = 0V 360 425 µA
VIN UVLO Threshold VIN Rising, PVDD open, for VIN≥6V 3.6 4.02 4.5 V
VIN UVLO Hysteresis VIN ≥ 6V 150 mV
VIN UVLO VIN <6V) VIN Rising, PVDD connected to VIN, for VIN<6V 3.2 3.5 3.9 V
VDD Supply
Internal Bias Voltages PVDD V
FB = 0.8V, IPVDD = 75mA 4.7 5.1 5.4 V
Reference (Each Channel)
Feedback Reference Voltage ±2% over temperature 686 700 714 mV
FB Bias Current VFB = 0.7V 5 nA
FB Line Regulation VIN = 6V to 13.2V, IOU T = 10mA 0.005 %/V
Output Voltage Line Regulation VIN = 6V to 13.2V , VOUT = 1.8V, IOU T = 1A 0.005 %/V
Output Voltage Load Regulation VOUT = 1.8V, IOU T = 0A to 2A 0.15 %
Output Voltage Total Regulation VIN = 6V to 13.2V , IOU T = 0.25A to 2A, VOUT = 1.8V 0.1 %
External Current Sense, Adjustable
Current Limit Trip Point Current Sourcing current 175 200 225 µA
Current Limit Temperature
Coefficient 750 ppm/°C
Current Limit Comparator Offset -10 0 10 mV
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Parameter Condition Min Typ Max Units
Oscillator / PWM
Switching Frequency 0.8 1 1.2 MHz
Maximum Duty-cycle 70 75 %
Minimum On-Time ILOAD > 200mA (5) 15 ns
Error Amplifier (each channel)
DC Gain 68 dB
High-side internal MOSFET
On Resistance RDS(ON) IFET = 1A, VFB=0.8V 150 mΩ
Low-side MOSFET driver
Pull Up, ISOURCE = 10mA 4 Ω
DH On-Resistance Pull Down; ISINK = 10mA 2.5 Ω
Into 1000pF 12 ns
DH Transition Time Into 1000pF 9 ns
Driver Non-overlap Dead Time (Adaptive) 25 ns
EN/DLY and soft-start control
EN/DLY Pull-up Current VEN/DLY=0V 5.0 6.5 8.0 µA
PVDD Threshold PVDD turns on 0.3 0.4 0.6 V
Soft-start Begins Threshold Channel soft-start begins 1 1.35 1.8 V
Soft-start Ends Threshold Channel soft-start ends 2 2.4 2.8 V
Power Good
PG Threshold Voltage VOUT Rising (% of VOUT nominal) 86 90 94 %Nom
PG Output Low Voltage VFB = 0V, IPG = 1mA 0.24 0.3 V
PG Leakage Current VFB = 800mV, VPG = 5.5V 5 nA
Thermal Protection
Over-temperature Shutdown TJ Rising 172 °C
Over-temperature Shutdown
Hysteresis
22
°C
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. Minimum on-time before automatic cycle skipping begins. See applications section.
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January 2011 6 M9999-020111-C
Typical Characteristics
12V
IN
Efficiency
vs . Output Current (09)
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0 0.5 1.0 1.5 2.0
O UTPUT CURRENT ( A)
EFFI CIENCY ( % )
5Vo
1.8Vo
1.2Vo
0.7Vo
5V
IN
Efficiency
vs . Output Current (09)
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0 0.5 1.0 1.5 2.0
O UTPUT CURRENT ( A)
EFFICI ENCY (%)
1.8Vo
1.2Vo
0.7Vo
I
DD_OFF
vs.
Input Volta ge
2
3
4
5
6
6 8 10 12
INPUT V OLTAGE (V )
IDD_OFF (mA
)
25°C
-40°C
85°C
IDD_ON vs.
Input Voltage
20
25
30
35
40
45
50
55
60
6 8 10 12
INPUT VOLTAGE (V)
IDD_ON (mA
)
-40°C
85°C
25°C
Enab le Threshold
vs. Input Voltage
1.30
1.32
1.34
1.36
1.38
1.40
6 8 10 12
INPUT VOLTAGE (V )
ENABLE THRESHOLD (V)
-40°C
85°C
25°C
Current Limit Threshold
vs. Input Voltage
3.00
3.05
3.10
3.15
3.20
6 8 10 12
INPUT V OLTAGE (V )
CURRENT LIMI T THRESHOLD (A)
25°C
Output Voltage
vs. Input Voltage
3.20
3.25
3.30
3.35
6 8 10 12
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
-40°C
85°C
25°C
Load Regulation
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
0.0 0.5 1.0 1.5 2.0
OUTPUT CURRENT(A)
OUTPUT VOLTAGE (V)
VIN = 12V
VOUT = 3.3V
-40°C
85°C
25°C
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Functional Characteristics
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Functional Diagram
PWM Core
MIC25400 Block Diagram
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Functional Description
The MIC25400 is a dual output, synchronous buck
regulators. Output regulation is performed using a fixed
frequency, voltage mode control scheme. The fixed
frequency clock drives the two sections 180° out of
phase, which reduces input ripple current.
Oscillator
An internal oscillator provides a clock signal to each of
the two sides. The clock signals are 180° out of phase
with the other. Each phase is used to generate a ramp
for the PWM comparator and a clock pulse that
terminates the switching cycle. The MIC25400 oscillator
frequency is nominally 1MHz.
UVLO
The UVLO monitors voltage on the VIN pin. The circuit
controls both regulators (side 1 and side 2). It disables
the output drivers and discharges the EN/DLY capacitor
when VIN is below the UVLO threshold. As VIN rises
above the threshold, the internal high-side FET drivers
and external low-side drives are enabled and the
EN/DLY pins are released.
A low impedance source should be used to supply input
voltage to the MIC25400. When VIN drops below the
UVLO threshold and the outputs turn off, the change in
input current will cause VIN to slight rise. The output
voltage will momentarily turn back on if the rise in VIN is
greater than the UVLO hysteresis.
The preferred method is to use the EN/DLY pins, as
shown in Figure 1, for startup and shutdown of the
outputs. This avoids the possibility of glitching during
startup and shutdown. If an external control signal is not
available, the circuit in Figure 1A may be used to set a
higher turn-on and turn-off threshold than the internal
UVLO circuit. Moreover, the hysteresis is adjustable and
can accommodate a wider input source impedance
range. Please refer to the MIC841 datasheet for
additional information on selecting the resistor values.
Regulator/Reference
The internal regulator generates a PVDD pin voltage that
powers the high-side MOSFET and low-side gate drive
circuits. It also generates an internal analog voltage,
AVDD, which is used by the low level analog and digital
sections. The AVDD voltage is also used by the bandgap
to generate a nominal 700mV for the error amplifier
reference. The output undervoltage and power good
circuits use the bandgap for their references.
The dropout of the internal regulator causes VPVDD to
drop when VIN is below 6V. When operating below 6V,
the PVDD pin must be jumpered to VIN. This bypasses
the internal LDO and prevents VPVDD from dropping out.
A 1µF ceramic capacitor should be used to decouple
VPVDD-to-ground.
EN/DLY pin
The EN/DLY pins are used to turn on, turn off and soft-
start the outputs. The pins can be controlled with an
open collector or open drain device as shown in Figure
1. It must not be actively driven high or damage will
result. When disabling the output with an external
device, the enable pin turn-off time must be less than
1µs.
Figure 1. Enable and soft-start circuit
Figure 1A. Adjustable UVLO startup circuit
Minimum Output Load when Disabled
When one output is disabled and the other enabled, then
the disabled output requires a minimum output load to
prevent its output voltage from rising. Typically, a 2kΩ
load on the output will keep the output voltage below
100mV. The output setting voltage divider resistors may
be used for the 2kΩ load if the total resistance is set low
enough. A separate output resistor should be used for
lower output voltages since the voltage divider
resistance becomes impractically low.
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January 2011 10 M9999-020111-C
Soft-start
Enable and soft-start waveforms are shown in Figure 2.
Figure 2. Soft-start Timing Diagram
A capacitor, CSS, is connected to the EN/DLY pin. The
CSS capacitor range is 4.7nf to 22nf. Releasing the pin
allows an internal current source to charge the capacitor.
The delay between the EN/DLY pin release and when
VOUT starts to rise can be calculated by the equation
below.
SS
StartThreshold_SS
DI
VC
t×
=
Where:
CSS is the soft-start capacitor.
ISS is the internal soft-start current (200µA nominal).
VThreshold_start is the EN/DLY pin voltage where the output
starts to rise (1.35V nominal).
The output voltage starts to rise when voltage on the
EN/DLY pin reaches the start threshold. The output
voltage reaches regulation when the EN/DLY pin voltage
reaches the end threshold. The output voltage rise time
can be calculated by the equation below:
SS
StartThreshold_EndThreshold_SS
DI
)V(VC
t−×
=
Where:
VThreshold_End is the EN/DLY pin voltage where the output
reaches regulation.
Power Good
Power good is an open drain signal that asserts when
VOUT exceed the power good threshold. The circuit
monitors the FB pin. The internal FET is turned on while
the FB voltage is below the FB threshold. When voltage
on the FB in exceeds the FB threshold, the FET is
turned off. A pull-up resistor can be connected to PVDD or
and external source. The external source voltage must
not exceed the maximum rating of the pin. The PG pin
can be connected to another regulator’s EN/DLY pin for
sequencing of the outputs. A pull-up resistor is not used
when the power good pin is connected to another
regulators EN/DLY pin.
Output Sequencing
Sequencing of the outputs is shown in Figure 3. The
power good pin is used to disable VOUT2 until the VOUT1
reaches regulation. Sequencing waveforms are shown in
Figure 4.
Figure 3. Output Sequencing
Figure 4. Output Sequencing Waveforms
The MIC25400 must start up without a pre-biased output
voltage. During start up, the MIC25400 pulls the output
to ground if it is above 0V. This may cause the output to
ring below ground and excessive voltage on the VSW
node. A pre-bias condition can occur if the output is
turned off then immediately turned back on before the
output capacitor is discharged to ground. It is also
possible that the output of the MIC25400 could be pulled
up or pre-biased through parasitic conduction paths from
one supply rail to another in multiple voltage level ICs
like a FPGA.
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High-side Drive
The internal high-side drive circuit is designed to switch
the internal N-channel MOSFET. Figure 5 shows a
diagram of the high-side MOSFET, gate drive and
bootstrap circuit. D2 and CBST comprise the bootstrap
circuit, which supplies drive voltage to the high-side
MOSFET. Bootstrap capacitor CBST is charged through
diode D2 when the low-side MOSFET turns on and pulls
the SW pin voltage-to-ground. When the high-side
MOSFET driver is turned on, energy from CBST charges
the MOSFET gate, turning it on. Voltage on the SW pin
increases to approximately VIN. Diode D2 is reversed
biased and CBST flies high while maintaining gate voltage
on the high-side MOSFET.
A resistor should be added in series with the BST1 and
BST2 pins. This will slow down the turn-on time of the
high-side MOSFET while leaving the turn-off time
unaffected. Slowing down the MOSFET risetime will
reduce the turn-on overshoot at the switch node, which
is important when operating with an input voltage close
to the maximum operating voltage.
The recommended capacitor for CBST is a 0.01µF
ceramic capacitor. The recommended value for RBST is
20Ω.
Figure 5. High-side Drive Circuitry
Low-side Drive Output
The LSD pin is used to drive an external MOSFET. This
MOSFET is driven out of phase with the internal high-
side MOSFET to conduct inductor current during the
high-side MOSFETs off-time. Circuitry internal to the
regulator prevents short circuit “shoot-through” current
from flowing by preventing the high-side and low-side
MOSFETs from conducting at the same time.
The low-side MOSFET gate voltage is supplied from
VPVDD. Turn off of the MOSFET is accomplished by
discharging the gate through the LSD pin. The return
path is through the PGND pin and back to the
MOSFET’s source pin. These circuit paths must be kept
short to minimize noise. See the layout section of this
datasheet for additional information.
Driving the low-side MOSFET on and off dissipates
power in the MIC25400 regulator. The power can be
calculated by the equation below:
SGSGDRIVER fVQP ×
×
=
Where:
PDRIVER is the power dissipated in the regulator by
switching the MOSFET on and off.
QG is the total Gate charge of the MOSFET at VGS.
VGS is the MOSFET’s Gate to Source voltage which is
equal to the voltage on PVDD.
fS is the switching frequency of the regulator (1MHz
nominal).
dV/dT Induced Turn-on of the Low-Side MOSFET
As the high-side MOSFET turns on, the rising dv/dt on
the switch-node forces current through CGD of the low-
side MOSFET causing a glitch on its gate. Figure 6
demonstrates the basic mechanism causing this issue. If
the glitch on the gate is greater than the MOSFET’s turn-
on threshold, it may cause an unwanted turn-on of the
low-side MOSFET while the high-side MOSFET is on. A
short circuit between input and ground would
momentarily occur, which lowers efficiency and
increases power dissipation in both FETs. Additionally,
turning on the low-side FET during the off-time could
interfere with overcurrent sensing.
Figure 6. dv/dt induced turn-on of the low-side MOSFET
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The following steps can be taken to lower the gate drive
impedance, minimize the dv/dt-induced current and
lower the FET’s susceptibility to the induced glitch:
• Chose a low-side MOSFET with a high CGS/CGD
ratio and a low internal gate resistance
• Do not put a resistor between the LSD output
and the gate.
• Insure both the gate drive and return etch are
short, low inductance connections.
• Use a 4.5V VGS rated MOSFET. Its higher gate
threshold voltage is more immune to glitches
than a 2.5V or 3.3V rated MOSFET. MOSFETs
that are rated for operation at less than 4.5 VGS
should not be used.
• Add a resistor in series with the BST pin. This
will slow down the turn-on time of the high-side
MOSFET while leaving the turn-off time
unaffected.
Current Limit
The MIC25400 uses the synchronous (low-side)
MOSFET’s RDSON to sense an over-current condition.
The low-side MOSFET is used because it displays lower
parasitic oscillations after switching than the upper
MOSFET. Additionally, it improves the accuracy and
reduces false tripping at lower voltage outputs and
narrow duty cycles since the off-time increases as duty-
cycle decreases. Figure 7 shows how over current
protection is performed using the low-side MOSFET.
Figure 7. Over-current Circuit
Inductor current, IL, flows from the lower MOSFET
source to the drain during the off-time, causing the drain
voltage to become negative with respect to ground. This
negative voltage is proportional to the instantaneous
inductor current times the MOSFET RDSON. The low-
side MOSFET voltage becomes even more negative as
the output current increases.
The over-current circuit operates by passing a known
fixed current source through a resistor RCS. This sets up
an offset voltage (ICS x RCS) that is compared to the VDS
of the low-side FET. When ISD (source-to-drain current) x
RDSON is equal to this voltage the soft-start circuit is
reset and a hiccup current mode is initiated to protect the
power supply and load from excessive current during
short circuits.
Current Limit Calculations and Maximum Peak Limit
The current limit method requires careful selection of the
inductor value and saturation current. If a short circuit
occurs during the off-time, the overcurrent circuit will
take up to a full cycle to detect the overcurrent once it
exceed the overcurrent limit. The worst case occurs if
the output current is 0A and a hard short is applied to the
output. The short circuit causes the output voltage to fall,
which increases the pulse width of the regulator. It may
take three or four cycles for the current to build up in the
inductor before current limit forces the part into hiccup
mode. The wider pulse width generates a larger peak to
peak inductor current which can saturate the inductor.
For this reason, the minimum inductor value for the
MIC25400 is 4.7µH and the maximum peak current limit
setpoint is 2.7A. The saturation current for each of these
inductors should be at least 1.5A higher than the
overcurrent limit setting.
Voltage Setting Components
The regulator requires two external resistors to set the
output voltage as shown in Figure 8.
Figure 8. Setting the Output Voltage
The output voltage is determined by the equation below.
⎟
⎠
⎞
⎜
⎝
⎛+×= R2
R1
1VV REFOUT
Where: VREF is 0.7V nominal.
If the voltage divider resistance is used to provide the
minimum load (see EN/DLY section) then R1 should be
low enough to provide the necessary impedance.
Once R1 is selected, R2 can be calculated with the
following formula:
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REFOUT
REF
VV
R1V
R2 −
×
=
Minimum Pulse Width
Output voltage is regulated by adjusting the on-time
pulse width of the high-side FET. This is accomplished
by comparing the error amplifier output with a sawtooth
waveform (see block diagram). The pulse width output of
the comparator becomes smaller as the error amplifier
voltage decreases. Due to propagation delay and other
circuit limitations, there is a minimum pulse width at the
output of the comparator. If the error amplifier voltage
drops any further, then the output of the comparator will
be low.
The PWM circuit will skip pulses if a smaller duty-cycle is
required to maintain output voltage regulation. This
effectively cuts the output frequency in half.
Thermal Protection
The internal temperature of the regulator is monitored to
prevent damage to the device. Both outputs are inhibited
from switching if the over-temperature threshold is
exceeded. Hysteresis in the circuit allows the regulator
to cool before turning back on.
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Application Information
Component Selection
Inductor
The value of inductance is determined by the peak to
peak inductor current. Higher values of inductance
reduce the inductor current ripple at the expense of a
larger inductor. Smaller inductance values allow faster
response to output current transients but increase the
output ripple voltage and require more output
capacitance.
The inductor value and saturation current are also
controlled by the method of overcurrent limit used (see
explanation in the previous section). The minimum value
of inductance for the MIC25400 is 4.7µH.
The peak-to-peak ripple current may be calculated using
the formula below.
LfVη
)VV(ηV
I
SIN(max)
OUTIN(max)OUT
PP ⋅⋅⋅
−⋅⋅
=
Where:
IPP is the peak to peak inductor ripple current
L is the value of inductance
fS is the switching frequency of the regulator
η is the efficiency of the power supply
Efficiency values from the Functional Characteristics
section can be use for these calculations.
The peak inductor current in each channel is equal to the
average output current plus one half of the peak-to-peak
inductor ripple current.
PPOUTPK I0.5II ×+=
The RMS inductor current is used to calculate the I2R
losses in the inductor.
2
OUT
PP
OUT
INDUCTOR I
I
3
1
1
I
IRMS ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+⋅=
Maximizing efficiency requires the proper selection of
core material and minimizing the winding resistance. The
high frequency operation of the MIC25400 requires the
use of ferrite materials. Lower cost iron powder cores
may be used but the increase in core loss will reduce the
efficiency of the power supply. This is especially
noticeable at low output power. The inductor winding
resistance decreases efficiency at the higher output
current levels. The winding resistance must be
minimized although this usually comes at the expense of
a larger inductor.
The power dissipated in the inductor equals the sum of
the core and copper losses. Core loss information is
usually available from the magnetics vendor.
Input Capacitor
A 10μF ceramic is suggested on each of the VIN pins for
bypassing. X5R or X7R dielectrics are recommended for
the input capacitor. Y5V dielectrics should not be used.
Besides losing most of their capacitance over
temperature, they also become resistive at high
frequencies, which reduce their ability to filter out high
frequency noise.
Output Capacitor
The MIC25400 regulator is designed for ceramic output
capacitors although tantalum and Aluminum Electrolytic
may also be used.
Output ripple voltage is determined by the magnitude of
inductor current ripple, the output capacitor’s ESR and
the value of output capacitance. When using ceramic
output capacitors, the primary contributor to output ripple
is the value of capacitance. Output ripple using ceramic
capacitors may be calculated using the equation below:
SOUT
PP
OUT f2ΔV8
I
C⋅⋅⋅
≥
Where:
ΔVOUT is the peak-to-peak output voltage ripple
IPP is the peak-to-peak ripple current as see by the
capacitors
fS is the switching frequency (1MHz nominal).
When using tantalum or Aluminum Electrolytic
capacitors, both the capacitance and ESR contribute to
output ripple. The total ripple is calculated below:
[]
2
ESRPP
2
SOUT
PP
OUT RI
f2C8
I
ΔV⋅+
⎥
⎦
⎤
⎢
⎣
⎡
⋅⋅⋅
=
The output capacitor RMS current is calculated below:
12
I
IPP
COUTRMS =
The power dissipated in the output capacitors can be
calculated by the equation below:
(
)
ESR
2
COUTDISS RIP RMSCOUT ⋅=
Current limit resistor
The current limit circuit responds to the peak inductor
current flowing through the low-side FET. Calculating the
current setting resistor RCS should take into account the
peak inductor current and the blanking delay of
approximately 100ns.
Micrel, Inc. MIC25400
January 2011 15 M9999-020111-C
Figure 9. Overcurrent waveform
Figure 9 shows the low-side MOSFET current waveform.
Peak current is measured after a small delay. The
equations used to calculate the current limit resistor
value are shown below:
2
I
+I=I PP
OUTPK
L
TV
II DLYOUT
PKOC
⋅
−=
CS
ONOC
CS I
RDSI
R⋅
=
Where:
IOC is the current limit set point
L = inductor value
TDLY = Current limit blanking time ~ 100ns
ICS is the overcurrent pin sense current (200µA nominal)
RDSON is the on resistance of the low-side MOSFET
Snubber
A snubber is used to damp out high frequency ringing
caused by parasitic inductance and capacitance in the
buck converter circuit. Figure 10 shows a simplified
schematic of one of the buck converter phases. Stray
capacitance consists mostly of the two MOSFET’s
output capacitance (COSS). The stray inductance is
mostly package and etch inductance. The arrows show
the resonant current path when the high-side MOSFET
turns on. This ringing causes stress on the
semiconductors in the circuit as well as increased EMI.
Figure 10. Output Parasitics
One method of reducing the ringing is to use a resistor to
lower the Q of the resonant circuit. The circuit in Figure
11 shows an RC network connected between the switch
node and ground. Capacitor CS is used to block DC and
minimize the power dissipation in the resistor. This
capacitor value should be between five and ten times the
parasitic capacitance of the MOSFET COSS. A capacitor
that is too small will have high impedance and prevent
the resistor from damping the ringing. A capacitor that is
too large causes unnecessary power dissipation in the
resistor, which lowers efficiency.
The snubber components should be placed as close as
possible to the low-side MOSFET and/or external
schottky diode since in contributes to most of the stray
capacitance. Placing the snubber too far from the FET or
using an etch that is too long or too thin adds inductance
to the snubber and diminishes its effectiveness.
Figure 11. Snubber Circuit
Micrel, Inc. MIC25400
January 2011 16 M9999-020111-C
Proper snubber design requires the parasitic inductance
and capacitance be known. A method of determining
these values and calculating the damping resistor value
is outlined below.
1. Measure the ringing frequency at the switch node
which is determined by parasitic LP and CP. Define this
frequency as f1.
2. Add a capacitor CS (normally at least 3 times as big as
the COSS of the FET) from the switch node-to-ground and
measure the new ringing frequency. Define this new
(lower) frequency as f2. LP and CP can now be solved
using the values of f1, f2 and CS.
3. Add a resistor RS in series with CS to generate critical
damping.
Step 1: First measure the ringing frequency on the
switch node voltage when the high-side MOSFET turns
on. This ringing is characterized by the equation:
PP
1CL2π
1
f⋅
=
Where:
CP and LP are the parasitic capacitance and inductance
Step 2: Add a capacitor, CS, in parallel with the
synchronous MOSFET, Q2. The capacitor value should
be approximately 3 times the COSS of Q2. Measure the
frequency of the switch node ringing, f2.
)C(CL2π
1
f
PSP
2+⋅
=
Define f’ as:
2
1
f
f
f' =
Combining the equations for f1, f2 and f’ to derive CP, the
parasitic capacitance
1)(f2
C
C2'
S
P−⋅
=
LP is solved by re-arranging the equation for f1.
()
2
1P
2
P)(fC2π
1
L⋅⋅
=
Step 3: Calculate the damping resistor.
Critical damping occurs at Q=1
1
CC
L
R
1
Q
PS
P
S
=
+
=
Solving for RS
PS
P
SCC
L
R+
=
Figure 11 shows the snubber in the circuit and the
damped switch node waveform.
The snubber capacitor, Cs, is charged and discharged
each switching cycle. The energy stored in Cs is
dissipated by the snubber resistor, Rs, two times per
switching period. This power is calculated in the
equation below.
2
INSSsnubber VCfP ⋅⋅=
Where:
fS is the switching frequency for each phase
VIN is the DC input voltage
Low-side MOSFET Selection
An external N-channel logic level power MOSFET must
be used for the low-side switch. The MOSFET gate-to-
source drive voltage of the MIC25400 is regulated by an
internal 5V regulator. Logic level MOSFETs, whose
operation is specified at VGS = 4.5V must be used. Use
of MOSFETs with a lower specified VGS (such as 3.3V or
2.5V) are not recommended since the low threshold can
cause them to turn on when the high-side FET is turning
on. When operating the regulator below a 6V input,
connect VDD to VIN to prevent the VDD regulator from
dropping out.
Total gate charge is the charge required to turn the
MOSFET on and off under specified operating conditions
(VDS and VGS). The gate charge is supplied by the
regulator’s gate drive circuit. Gate charge is a source of
power dissipation in the regulator due to the high
switching frequencies. At low output load this power
dissipation is noticeable as a reduction in efficiency. The
average current required to drive the MOSFETs is:
SGDD fQI
⋅
=
Where:
QG is the gate charge for both of the external MOSFETs.
This information should be obtained from the
manufacturer’s data sheet.
Since current from the gate drive is supplied by the input
voltage, power dissipated in the MIC25400 due to gate
drive is:
INSGGATE_DRIVE VfQP ⋅⋅
=
Parameters that are important to MOSFET selection are:
• Voltage rating
• On resistance
• Total Gate Charge
Micrel, Inc. MIC25400
January 2011 17 M9999-020111-C
The MOSFET is subjected to a VDS equal to the input
voltage. A safety factor of 20% should be added to the
VDS(max) of the MOSFET to account for voltage spikes
due to circuit parasitics. Generally, 30V MOSFETs are
recommended for all applications since lower VDS rated
MOSFETs tend to have a VGS rating that is lower than
the recommended 4.5V.
RMS Current and MOSFET Power Dissipation
Calculation
Switching loss in the low-side MOSFET can be
neglected since it is turned on and off at a VDS of 0V.
The power dissipated in the MOSFET is mostly
conduction loss during the on-time (PCONDUCTION).
ON
2
SWITCHCONDUCTION RDSIP RMS ⋅=
Where:
RDSON is the on resistance of the MOSFET switch.
The RMS value of the MOSFET current is:
)
12
I
(ID)(1I
2
PP
2
OUT_MAXSW_RMS +⋅−=
Where:
D is the duty-cycle of the converter
IPP is the inductor ripple current
IN
OUT
Vη
V
D⋅
=
Where:
η is the efficiency of the converter.
External Schottky Diode
A freewheeling diode in parallel with the low-side FET is
needed to maintain continuous inductor current flow
while both MOSFETs are turned off (dead-time). Dead-
time is necessary to prevent current from flowing
unimpeded through both MOSFETs. An external
Schottky diode is used to bypass the low-side
MOSFET’s parasitic body diode. An external diode
improves efficiency due to its lower forward voltage drop
as compared to the internal parasitic diode in the FET. It
may also decrease high frequency noise because the
Schottky diode junction does not suffer from reverse
recovery.
An external Schottky diode conducts at a lower forward
voltage preventing the body diode in the MOSFET from
turning on. The lower forward voltage drop dissipates
less power than the body diode. Depending on the circuit
components and operating conditions, an external
Schottky diode may give up to 1% improvement in
efficiency.
Compensation
The voltage regulation, filter and power stage section is
shown in Figure 12. The error amplifier regulates the
output voltage and compensates the voltage regulation
loop. It is a simplified type III compensator utilizing two
compensating zeros and two poles. Figure 12 also
shows the transfer function for each section.
Compensation is necessary to insure the control loop
has adequate bandwidth and phase margin to properly
respond to input voltage and output current transients.
High gain at DC and low frequencies is needed for
accurate output voltage regulation. Attenuation near the
switching frequency prevents switching frequency noise
from interfering with the control loop.
The output filter contains a complex double pole formed
by the capacitor and inductor and a zero from the output
capacitor and its ESR. The transfer function of the filter
is:
2
ωo
s
+
ωoQ
s
+1
ωz
s
+1
=Gfilter(s)
Where:
L
C
RQ
LC
1
ωo
RC
1
ωz
O
OO
ESRO
⋅=
⋅
=
⋅
=
The Modulator Gain is proportional to the input voltage
and inversely proportional to the internal ramp voltage
generated by the oscillator. The peak-peak ramp voltage
is 1V.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
RAMP
IN
V
V
Gmod
The output voltage divider attenuates VOUT and feeds it
back to the error amplifier. The divider gain is:
OUT
REF
V
V
R4R1
R4
H=
+
=
Micrel, Inc. MIC25400
January 2011 18 M9999-020111-C
Figure 12. Voltage Loop and Transfer Functions
The modulator, filter and voltage divider gains can be
multiplied together to show the open loop gain of these
parts.
GmodHGfilter(s)Gvd(s) ⋅⋅=
This transfer function is plotted in Figure 13. At low
frequency, the transfer function gain equals the
modulator gain times the voltage divider gain. As the
frequency increases toward the LC filter resonant
frequency, the gain starts to peak. The increase in the
gain’s amplitude equals Q. Just above the resonant
frequency, the gain drops at a -40db/decade rate. The
phase quickly drops from 0° to almost 180° before the
phase boost of the zero brings it back up to -90°. Higher
values of Q will cause the phase to drop quickly. In a
well damped, low Q system the phase will change more
slowly.
As the frequency approaches the zero frequency (fZ),
formed by CO and its ESR, then the slope of the gain
curve changes from -40db/dec. to -20db/dec and the
phase increases. The zero causes a 90° phase boost.
Ceramic capacitors, with their smaller values of
capacitance and ESR, push the zero and its phase boost
out to higher frequencies, which allow the phase lag
from the LC filter to drop closer to -180°. The system will
be close to being unstable if the overall open loop gain
crosses 0dB while the phase is close to -180°.
Figure 13: Gvd Transfer Function
If the output capacitance and/or ESR is high, the zero
moves lower in frequency and helps to boost the phase,
leading to a more stable system.
Error Amplifier Poles and Zeros
The error amplifier has internal poles and zeros that can
be shifted in frequency with an external capacitor. The
general form of the error amplifier compensation is
shown in the equation below:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛+
×=
ωp2
s
1
ωp1
s
1
ωz2
s
1
ωz1
s
1
GGea(s) DC
Gv d Transfer Function
-50
-40
-30
-20
-10
0
10
20
30
40
50
10 100 1000 10000 100000 1000000
FREQUENCY (Hz)
GAIN ( dB)
-210
-180
-150
-120
-90
-60
-30
0
30
60
90
PHA SE (°)
Gain
Phase
V
IN
= 12V
V
OUT
= 1.8V
C
OUT
= 20µF
L = 4.7µH
Micrel, Inc. MIC25400
January 2011 19 M9999-020111-C
The GDC is the DC gain of the error amplifier. It is
internally set to 2500 (68dB).
As illustrated in Figure 12, there are two compensating
zeros. ωz1 is internally set with R3 and C3. The zero
frequency is fixed at a nominal 16kHz in the MIC25400.
The second zero, ωz2, is set by the external capacitor,
C2.
For the MIC25400:
C21021π2
1
fz2
16kHz
C3R3π2
1
fz1
100pfC3
100kR3
3×⋅××
=
=
×××
=
=
=
The two compensating pole frequencies are shown
below.
C21012π2
1
fp2
250Hzfp1
3×⋅××
=
=
fp2 and fz2 both depend on the value of C2 and are
proportionally spaced in frequency with the zero at a
lower frequency than the pole. This provides gain and
phase boost in the control loop.
Voltage Divider Feedforward Capacitor
The capacitor across the upper voltage divider resistor
boosts the gain and phase of the control loop by short
circuiting the high-side resistor at higher frequencies.
The capacitor and upper resistor form a zero at a lower
frequency. The capacitor and parallel combination of
upper and lower resistors form a pole at a higher
frequency. This phase boost circuit is most effective at
higher output voltages, where there is a larger
attenuation from the voltage divider resistors. The
general form of the feedforward circuit is shown below.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛+
×
+
=
ωp3
s
1
ωz3
s
1
R2R1
R2
H(s)
Where:
⎟
⎠
⎞
⎜
⎝
⎛
+
×
×××
=
×××
=
R2R1
R2R1
C1π2
1
fp3
C1R1π2
1
fz3
The total open loop transfer function is:
H(s)Gfilter(s)GmodGea(s)T(s)
×
×
×
=
The following tables list the recommended values of
compensation and filter components for different output
voltages. The output capacitors are ceramic.
MIC25400
VIN VOUT R1 R2 C2 C1 Lo Co
12V 1.0V 1k 2.32k 47pF 1.5nF 4.7µH 22µF
12V 1.2V 1k 1.4k 47pF 1.5nF 4.7µH 22µF
12V 1.4V 1k 1k 47pF 1.5nF 4.7µH 22µF
12V 1.8V 1k 634 47pF 1.5nF 4.7µH 22µF
12V 2.5V 1k 383 47pF 3.3nF 4.7µH 22µF
12V 3.3V 1k 274 68pF 3.3nF 4.7µH 22µF
12V 5.0V 1k 162 68pF 3.3nF 4.7µH 22µF
Micrel, Inc. MIC25400
January 2011 20 M9999-020111-C
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths.
The following guidelines should be followed to insure
proper operation of the MIC25400 converter.
IC
• Place the IC and the external Low-side MOSFET
close to the point of load (POL).
• Use fat traces to route the input and output power
lines.
• The exposed pad (EP) on the bottom of the IC must
be connected to the ground.
• Use several vias to connect the EP to the ground
plane on layer 2.
• Signal and power grounds should be kept separate
and connected at only one location, the EP ground
of the package.
• The following signals and their components should
be decoupled or referenced to the power ground
plane: VIND1, VIND2, PVDD, PGND1, PGND2,
LSD1, and LSD2.
• These analog signals should be referenced or
decoupled to the analog ground plane: VIN,
EN/DLY1, EN/DLY2, COMP1, COMP2, FB1, and
FB2.
• Place the overcurrent sense resistor close to the
CS1 or CS2 pins. The trace coming from the switch
node to this resistor has high dv/dt and should be
routed away from other noise sensitive components
and traces. Avoid routing this trace under the
inductor to prevent noise from coupling into the
signal.
Input Capacitor
• Place the input capacitor next. Ceramic capacitors
must be placed between VIND1 and PGND1 and
between VIND2 and PGND2.
• Place the input capacitors on the same side of the
board and as close to the IC and low-side MOSFET
as possible.
• Keep both the VIN and PGND connections short.
• Place several vias to the ground plane close to the
input capacitor ground terminal, but not between the
input capacitors and IC pins.
• Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
• If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be derated by 50%.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-
voltage spike seen on the input supply with power is
suddenly applied. The value must be sufficiently
large to prevent this voltage spike from exceeding
the maximum voltage rating of the MIC25400.
• An additional Tantalum or Electrolytic bypass input
capacitor of 22µF or higher is required at the input
power connection.
Inductor
• Keep the inductor connection to the switch node
(SW) short.
• Do not route any digital or analog signal lines
underneath or close to the inductor.
• Keep the switch node (SW) away from the feedback
(FB) pin.
• To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
terminal.
• Phase margin will change as the output capacitor
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
the BOM.
• The feedback trace should be separate from the
power trace and connected as close as possible to
the output capacitor. Sensing a long high current
load trace can degrade the DC load regulation.
• If 0603 package ceramic output capacitors are used,
then make sure that it has enough capacitance at
the desired output voltage. Please refer to the
capacitor datasheet for more details.
Diode
• The external Schottky diode is placed next to the
low-side MOSFET.
• The connection from the Schottky diode’s anode to
the input capacitors ground terminal must be as
short as possible.
• The diode’s cathode connection to the switch node
(SW) must be keep as short as possible.
Micrel, Inc. MIC25400
January 2011 21 M9999-020111-C
RC Snubber
• Place the RC snubber on the same side of the board
and as close as possible to the low-side MOSFET.
Low-side MOSFET
• Low-side drive MOSFET traces (LSD pin-to-
MOSFET gate pin) must be short and routed over a
ground plane. The ground plane should be the
connection between the MOSFET source and
PGND.
• Chose a low-side MOSFET with a high CGS/CGD
ratio and a low internal gate resistance to minimize
the effect of dv/dt inducted turn-on.
• Do not put a resistor between the LSD output and
the gate.
• Use a 4.5V Vgs rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than a
2.5V or 3.3V rated MOSFET. MOSFETs that are
rated for operation at less than 4.5VGS should not be
used.
High-side MOSFET
• Add a 20 ohm resistor in series with the boost pin.
This will slow down the turn-on time of the high-side
MOSFET while leaving the turn-off time unaffected.
Micrel, Inc. MIC25400
January 2011 22 M9999-020111-C
MIC25400 Evaluation Board Schematic
Micrel, Inc. MIC25400
January 2011 23 M9999-020111-C
MIC25400 Bill of Materials
Item Part Number Manufacturer Description Qty.
C1 12103D226MAT2A AVX(1) Ceramic Capacitor, 22µF, 25V, X5R 1
C2, C13 12063D106MAT2A AVX Ceramic Capacitor, 10µF, 25V, X5R 2
C4, C10, C6,
C9
06033D103MAT2A AVX Ceramic Capacitor, 10nF, 25V 4
C5 08056D225MAT2A AVX Ceramic Capacitor, 2.2µF, 6.3V 1
C7 VJ0603Y680KXXMB Vitramon(2) Ceramic Capacitor, 68pF, 50V, X7R 1
C8 VJ0603Y470KXXMB Vitramon Ceramic Capacitor, 47pF, 50V, X7R 1
C11, C14 08056D226MAT2A AVX Ceramic Capacitor, 22µF, 6.3V, X5R 2
C12 06033D105MAT2A AVX Ceramic Capacitor, 1µF, 25V 1
C16 VJ0603Y332KXXMB Vitramon Ceramic Capacitor, 3.3nF, 50V, X7R 1
C17 VJ0603Y152KXXMB Vitramon Ceramic Capacitor, 1.5nF, 50V, X7R 1
C18, C19 VJ0603Y102KXXMB Vitramon Ceramic Capacitor, 1nF, 50V, X7R 2
D1, D2 SD103BWS Vishay(2) Schottky Diode, 100mA, 30V 2
D3, D4 B0530W Diodes. Inc(3) Schottky Diode, 30V, 0.5A 2
L1, L2 DR74-4R7-R Cooper(4) Inductor, 4.7µH, 4.3A 2
R1, R6 CRCW06031001FRT1 Vishay Dale(2) Resistor, 1k (0603 size), 1% 4
R2 CRCW06032740FRT1 Vishay Dale Resistor, 274 (0603 size), 1% 1
R3, R8 CRCW06031002FRT1 Vishay Dale Resistor, 10k (0603 size), 1% 4
R4, R5 CRCW06036040FRT1 Vishay Dale Resistor, 604 (0603 size), 1% 2
R7 CRCW06031401FRT1 Vishay Dale Resistor, 1.4k (0603 size), 1% 1
R9, R10 CRCW060320R0FRT1 Vishay Dale Resistor, 20 (0603 size), 1% 2
R12, R13 CRCW06034992FRT1 Vishay Dale Resistor, 49.9k (0603 size), 1% 2
R15, R16,
R17
CRCW06030000FRT1 Vishay Dale Resistor, 0Ω (0603 size) 3
R20, R21 CRCW08051R21FRT1 Vishay Dale Resistor, 1.21Ω (0805 size), 1% 2
Q1, Q2 FDN359AN Fairchild(5) MOSFET 2
Q3, Q4 BSS138 Fairchild MOSFET 2
U1 MIC25400YML Micrel, Inc.(6) 2A Dual Output PWM Synchronous Buck Regulator IC 1
Notes:
1. AVX: www.avx.com
2. Vishay: www.vishay.com
3. Diodes Inc.: www.diodes.com
4. Cooper Magnetics: www.cooperet.com
5. Fairchild Semiconductor: www.fairchildsemi.com
6. Micrel, Inc.: www.micrel.com
Micrel, Inc. MIC25400
January 2011 24 M9999-020111-C
PCB Layout Recommendations
Top Layer
Mid Layer 1
Micrel, Inc. MIC25400
January 2011 25 M9999-020111-C
Mid Layer 2
Bottom Layer
Micrel, Inc. MIC25400
January 2011 26 M9999-020111-C
Package Information
24-Pin 4mm x 4mm MLF® (ML)
Micrel, Inc. MIC25400
January 2011 27 M9999-020111-C
Recommended Land Pattern
24-Pin 4mm x 4mm MLF® (ML)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
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Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
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Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
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