VIN
CIN
22 PF
Enable
RFBT
See Table
CSS
0.47 PFRFBB
See Table Co
220 PF
LMZ23605
VOUT
SS/TRK
SYNC
FB
VIN
EN
PGND
VOUT @ 5A
AGND
0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
9 VIn
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
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LMZ23605
SNVS659I –MARCH 2011–REVISED AUGUST 2015
LMZ23605 5-A SIMPLE SWITCHER
®
Power Module With 36-V Maximum Input Voltage
1
1 Features
• Integrated Shielded Inductor 2 Applications
• Simple PCB Layout • Point-of-load Conversions from 12-V and 24-V
Input Rail
• Frequency Synchronization Input (650 kHz to 950
kHz) • Time-Critical Projects
• Flexible Start-up Sequencing Using External Soft- • Space Constrained / High Thermal Requirement
Start, Tracking and Precision Enable Applications
• Protection Against Inrush Currents and Faults • Negative Output Voltage Applications See
such as Input UVLO and Output Short Circuit SNVA425
• Junction Temperature Range –40°C to +125°C 3 Description
• Single Exposed Pad and Standard Pinout for Easy The LMZ23605 SIMPLE SWITCHER®power module
Mounting and Manufacturing is an easy-to-use step-down DC – DC solution
• Fast Transient Response for Powering FPGAs capable of driving up to 5-A load. The LMZ23605 is
and ASICs available in an innovative package that enhances
• Fully Enabled for WEBENCH®Power Designer thermal performance and allows for hand or machine
soldering.
• Pin Compatible With
LMZ22005/LMZ23603/LMZ22003 The LMZ23605 can accept an input voltage rail
• Performance Benefits between 6 V and 36 V and can deliver an adjustable
and highly accurate output voltage as low as 0.8 V.
– High Efficiency Reduces System Heat The LMZ23605 only requires two external resistors
Generation and three external capacitors to complete the power
– Tested to EN55022 Class B solution. The LMZ23605 is a reliable and robust
– See SNVA473 and Layout for Information design with the following protection features: thermal
shutdown, programmable input undervoltage lockout,
on Device Under Test. output overvoltage protection, short circuit protection,
– Vin=24VVo=3.3VIo=5A output current limit, and the device allows start-up
NOTE: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. into a prebiased output. The sync input allows
synchronization over the 650- to 950-kHz switching
– Low Component Count, only 5 External frequency range.
Components
– Low Output Voltage Ripple Device Information(1)(2)
– Uses PCB as Heat Sink, no Airflow Required PART NUMBER PACKAGE BODY SIZE (NOM)
• Electrical Specifications LMZ23605 NDW (7) 10.16 mm × 9.85 mm
– 30-W Maximum Total Output Power (1) For all available packages, see the orderable addendum at
– Up to 5-A Output Current the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
– Input Voltage Range 6 V to 36 V more details.
– Output Voltage Range 0.8 V to 6 V
– Efficiency up to 92%
Simplified Application Schematic Efficiency 5-V Output at 25°C Ambient
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ23605
SNVS659I –MARCH 2011–REVISED AUGUST 2015
www.ti.com
Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 17
8.1 Application Information............................................ 17
2 Applications ........................................................... 18.2 Typical Application ................................................. 17
3 Description............................................................. 19 Power Supply Recommendations...................... 22
4 Revision History..................................................... 210 Layout................................................................... 22
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 22
6 Specifications......................................................... 310.2 Layout Examples................................................... 23
6.1 Absolute Maximum Ratings ...................................... 310.3 Power Dissipation and Thermal Considerations... 24
6.2 ESD Ratings.............................................................. 310.4 Power Module SMT Guidelines ............................ 25
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 26
6.4 Thermal Information.................................................. 411.1 Device Support...................................................... 26
6.5 Electrical Characteristics........................................... 411.2 Documentation Support ........................................ 26
6.6 Typical Characteristics.............................................. 611.3 Community Resources.......................................... 26
7 Detailed Description............................................ 14 11.4 Trademarks........................................................... 26
7.1 Overview ................................................................. 14 11.5 Electrostatic Discharge Caution............................ 26
7.2 Functional Block Diagram....................................... 14 11.6 Glossary................................................................ 26
7.3 Feature Description................................................. 14 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 16 Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (October 2013) to Revision I Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Removed Easy-To-Use PFM 7-Pin Package image ............................................................................................................. 1
Changes from Revision G (December 2012) to Revision H Page
• Deleted 10 mil......................................................................................................................................................................... 4
• Changed 10 mil .................................................................................................................................................................... 22
• Changed 10 mil .................................................................................................................................................................... 25
• Added Power Module SMT Guidelines................................................................................................................................. 25
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PGND/EP
Connect to AGND
5 FB
6 SS/TRK
3 EN
1 VIN
2 SYNC
4 AGND
7 VOUT
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
5 Pin Configuration and Functions
NDW Package
7-Pin
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 4 Ground Analog Ground — Reference point for all stated voltages. Must be externally connected to PGND (EP).
EN 3 Analog Enable — Input to the precision enable comparator. Rising threshold is 1.279 V typical. Once the module
is enabled, a 21-µA source current is internally activated to facilitate programmable hysteresis.
FB 5 Analog Feedback — Internally connected to the regulation amplifier, over-voltage comparators. The regulation
reference point is 0.796V at this input pin. Connect the feedback resistor divider between the output and
AGND to set the output voltage.
PGND — Ground Exposed Pad / Power Ground Electrical path for the power circuits within the module. — NOT Internally
connected to AGND / pin 4. Used to dissipate heat from the package during operation. Must be electrically
connected to pin 4 external to the package.
SS/TRK 6 Analog Soft-Start/Track — To extend the 1.6-ms internal soft-start connect an external soft-start capacitor. For
tracking connect to an external resistive divider connected to a higher priority supply rail.
SYNC 2 Analog Sync Input — Apply a CMOS logic level square wave whose frequency is between 650 kHz and 950 kHz
to synchronize the PWM operating frequency to an external frequency source. When not using
synchronization connect to ground. The module free running PWM frequency is 812 kHz (typical).
VIN 1 Power Supply input — Nominal operating range is 6 V to 36 V. A small amount of internal capacitance is
contained within the package assembly. Additional external input capacitance is required between this pin
and exposed pad (PGND).
VOUT 7 Power Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and
exposed pad.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
VIN to PGND –0.3 40 V
EN, SYNC to AGND –0.3 5.5 V
SS/TRK, FB to AGND –0.3 2.5 V
AGND to PGND –0.3 0.3 V
Junction temperature 150 °C
Peak reflow case temperature (30 sec) 245 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, refer to the following document: SNOA549
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN 6 36 V
EN, SYNC 0 5 V
Operation junction temperature −40 125 °C
6.4 Thermal Information LMZ23605
THERMAL METRIC(1) NDW UNIT
7 PINS
RθJA 4-layer Evaluation Printed-Circuit-Board, 60 vias, No air 12
Junction-to-ambient thermal flow °C/W
resistancet(2) 2-layer JEDEC Printed-Circuit-Board, No air flow 21.5
RθJC(top) Junction-to-case (top) thermal resistance 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) RθJA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal vias,
no air flow, and 1-W power dissipation. Refer to application note layout diagrams.
6.5 Electrical Characteristics
Limits in standard type are for TJ= 25°C unless otherwise specified. Minimum and maximum limits are ensured through test,
design or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 3.3 V
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SYSTEM PARAMETERS
ENABLE CONTROL
1.279 V
VEN EN threshold trip point VEN rising over the junction temperature 1.1 1.458
(TJ) range of –40°C to +125°C
EN input hysteresis –21 µA
VEN-HYS VEN > 1.279 V
current
SOFT-START
50 µA
ISS SS source current VSS = 0 V over the junction temperature 40 60
(TJ) range of –40°C to +125°C
tSS Internal soft-start interval 1.6 ms
CURRENT LIMIT
over the junction temperature 5.4 A
ICL Current limit threshold DC average (TJ) range of –40°C to +125°C
INTERNAL SWITCHING OSCILLATOR
Free-running oscillator 711 812 914 kHz
fosc Sync input connected to ground.
frequency
fsync Synchronization range 650 950 kHz
Synchronization logic zero over the junction temperature 0.4 V
VIL-sync Relative to AGND
amplitude (TJ) range of –40°C to +125°C
Synchronization logic one over the junction temperature 1.5 V
VIH-sync Relative to AGND.
amplitude (TJ) range of –40°C to +125°C
Synchronization duty cycle 15% 50% 85%
Sync DC range
Dmax Maximum Duty Factor 83%
(1) Minimum and Maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics (continued)
Limits in standard type are for TJ= 25°C unless otherwise specified. Minimum and maximum limits are ensured through test,
design or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V, VOUT = 3.3 V
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
REGULATION AND OVERVOLTAGE COMPARATOR
0.796 V
In-regulation feedback VSS >+ 0.8 V
VFB over the junction temperature 0.776 0.816
voltage IO= 5 A (TJ) range of –40°C to +125°C
Feedback overvoltage 0.86 V
VFB-OV protection threshold
Feedback input bias 5 nA
IFB current
Non-switching input 2.6 mA
IQVFB= 0.86 V
current
Shutdown quiescent 70 μA
ISD VEN= 0 V
current
THERMAL CHARACTERISTICS
TSD Thermal shutdown Rising 165 °C
Thermal shutdown 15 °C
TSD-HYST Falling
hysteresis
PERFORMANCE PARAMETERS(3)
Cout = 220 uF with 7 mΩESR + 100 uF X7R + 2 x 9 mVPP
ΔVOOutput voltage ripple 0.047 uF BW at 20 MHz
ΔVO/ΔVIN Line regulation VIN = 12 V to 36 V, IO= 0.001 A ±0.02%
ΔVO/ΔIOUT Load regulation VIN = 12 V, IO= 0.001 A to 5 A 1 mV/A
VIN = 12 V VO= 3.3 V, IO= 1 A 86%
ηPeak efficiency VIN = 24 V VO= 3.3 V, IO= 2 A 80%
VIN = 12 V VO= 3.3 V, IO= 5 A 81.5%
ηFull load efficiency VIN = 24 V VO= 3.3 V, IO= 5 A 76%
(3) Refer to BOM in Table 1.
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0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
9 VIn
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
10 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
LMZ23605
SNVS659I –MARCH 2011–REVISED AUGUST 2015
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6.6 Typical Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 1. Efficiency 6-V Output at 25°C Ambient Figure 2. Dissipation 6-V Output at 25°C Ambient
Figure 3. Efficiency 5-V Output at 25°C Ambient Figure 4. Dissipation 5-V Output at 25°C Ambient
Figure 5. Efficiency 3.3-V Output at 25°C Ambient Figure 6. Dissipation 3.3-V Output at 25°C Ambient
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0 1 2 3 4 5
25
35
45
55
65
75
85
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
0 1 2 3 4 5
30
40
50
60
70
80
90
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin*
0 1 2 3 4 5
30
40
50
60
70
80
90
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
LMZ23605
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 7. Efficiency 2.5-V Output at 25°C Ambient Figure 8. Dissipation 2.5-V Output at 25°C Ambient
Figure 9. Efficiency 1.8-V Output at 25°C Ambient Figure 10. Dissipation 1.8-V Output at 25°C Ambient
Figure 11. Efficiency 1.5-V Output at 25°C Ambient Figure 12. Dissipation 1.5-V Output at 25°C Ambient
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0 1 2 3 4 5
10
20
30
40
50
60
70
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin*
24 Vin*
30 Vin*
36 Vin*
0 1 2 3 4 5
20
30
40
50
60
70
80
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin*
30 Vin*
36 Vin*
0 1 2 3 4 5
20
30
40
50
60
70
80
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
LMZ23605
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 13. Efficiency 1.2-V Output at 25°C Ambient Figure 14. Dissipation 1.2-V Output at 25°C Ambient
Figure 15. Efficiency 1-V Output at 25°C Ambient Figure 16. Dissipation 1-V Output at 25°C Ambient
Figure 17. Efficiency 0.8-V Output at 25°C Ambient Figure 18. Dissipation 0.8-V Output at 25°C Ambient
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0 1 2 3 4 5
30
40
50
60
70
80
90
EFFICIENCY (%)
OUTPUT CURRENT (A)
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
0 1 2 3 4 5
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT CURRENT (A)
10 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 19. Efficiency 6-V Output at 85°C Ambient Figure 20. Dissipation 6-V Output at 85°C Ambient
Figure 21. Efficiency 5-V Output at 85°C Ambient Figure 22. Dissipation 5-V Output at 85°C Ambient
Figure 23. Efficiency 3.3-V Output at 85°C Ambient Figure 24. Dissipation 3.3-V Output at 85°C Ambient
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0 1 2 3 4 5
20
30
40
50
60
70
80
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
0 1 2 3 4 5
30
40
50
60
70
80
90
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin*
0 1 2 3 4 5
30
40
50
60
70
80
90
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 25. Efficiency 2.5-V Output at 85°C Ambient Figure 26. Dissipation 2.5-V Output at 85°C Ambient
Figure 27. Efficiency 1.8-V Output at 85°C Ambient Figure 28. Dissipation 1.8-V Output at 85°C Ambient
Figure 29. Efficiency 1.5-V Output at 85°C Ambient Figure 30. Dissipation 1.5-V Output at 85°C Ambient
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0 1 2 3 4 5
20
30
40
50
60
70
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin*
24 Vin*
30 Vin*
36 Vin*
0 1 2 3 4 5
15
25
35
45
55
65
75
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin*
30 Vin*
36 Vin*
0 1 2 3 4 5
20
30
40
50
60
70
80
EFFICIENCY (%)
OUTPUT CURRENT (A)
6 Vin
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin*
36 Vin*
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
Figure 31. Efficiency 1.2-V Output at 85°C Ambient Figure 32. Dissipation 1.2-V Output at 85°C Ambient
Figure 33. Efficiency 1-V Output at 85°C Ambient Figure 34. Dissipation 1-V Output at 85°C Ambient
Figure 35. Efficiency 0.8-V Output at 85°C Ambient Figure 36. Dissipation 0.8-V Output at 85°C Ambient
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0 1 2 3 4 5
0.998
0.999
1.000
1.001
1.002
NORMALLIZED OUTPUT VOLTAGE (V/V)
OUTPUT CURRENT (A)
9 Vin
12 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10 mV/Div 500 ns/Div
30 40 50 60 70 80 90 100 110 120130
0
1
2
3
4
5
6
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
JA=12°C/W
30 40 50 60 70 80 90 100 110 120130
0
1
2
3
4
5
6
MAXCIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
JA=12°C/W
30 40 50 60 70 80 90 100 110 120130
0
1
2
3
4
5
6
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
JA=12°C/W
30 40 50 60 70 80 90 100 110 120130
0
1
2
3
4
5
6
MAXIMUM OUTPUT CURRENT (A)
TEMPERATURE (°C)
JA = 12 °C/W
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
VIN = 12 V, VOUT = 5 V VIN= 12 V, VOUT = 3.3 V
Figure 37. Thermal Derating Figure 38. Thermal Derating
VIN = 24 V, VOUT = 5 V VIN = 24 V, VOUT = 3.3 V
Figure 39. Thermal Derating Figure 40. Thermal Derating
12 VIN 3.3 VOat 5 A, BW = 20 MHz
VOUT = 3.3 V
Figure 42. Output Ripple
Figure 41. Normalized Line and Load Regulation
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0 4 8 12 16 20 24 28 32 36
0
1
2
3
4
5
6
7
8
9
CURRENT (A)
INPUT VOLTAGE (V)
Output Current
Input Current
100 mV/Div 500 µs/Div
2A/Div
10 mV/Div 500 ns/Div
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO= 220 μF
Specialty Polymer + 10-µF Ceramic; TA= 25° C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting in slightly higher Output ripple.
12 VIN 3.3 VOat 5 A BW = 250 MHz 12 VIN 3.3 VO0.5 to 5-A Step
Figure 43. Output ripple Figure 44. Transient response
Figure 45. Short Circuit Current vs Input Voltage
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1 3
FB
1
2 3
Linear
Regulator
2M
3.3 uH
CBST
EN
AGND Regulator IC
CSS
Internal Passives
VOUT
CINint
CO
SYNC
EP/
PGND
Comp
CIN
RFBB
SS/TRK
VREF
1
2 3
VIN
800 kHz
PWM
RFBT
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7 Detailed Description
7.1 Overview
The architecture used is an internally compensated emulated peak current mode control, based on a monolithic
synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is
maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the
valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to
start the next cycle.
The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a
narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external
ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is
normally required for peak current-mode control.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Synchronization Input
The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to ground through a resistor of 1.5 kΩor less. The allowed
synchronization frequency range is 650 kHz to 950 kHz. The typical input threshold is 1.4-V transition level.
Ideally the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5-
kΩThevenin source resistance is recommended.
NOTE
Applying a sustained logic 1 corresponds to zero hertz PWM frequency and will cause the
module to stop switching.
7.3.2 Output Overvoltage Protection
If the voltage at FB is greater than a 0.86-V internal reference, the output of the error amplifier is pulled toward
ground, causing VOto fall.
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Feature Description (continued)
7.3.3 Current Limit
The LMZ23605 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit
detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 5.4 A (typical) the
current limit comparator disables the start of the next switching period. Switching cycles are prohibited until
current drops below the limit. DC current limit is dependent on both duty cycle as illustrated in the graph in the
Typical Characteristics section. The HS current limit monitors the current of top side MOSFET. Once HS current
limit is detected (7 A typical) , the HS MOSFET is shut off immediately, until the next cycle. Exceeding HS
current limit causes VOto fall. Typical behavior of exceeding LS current limit is that fSW drops to 1/2 of the
operating frequency.
7.3.4 Thermal Protection
The junction temperature of the LMZ23605 must not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VOto fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 150°C (typical hysteresis = 15°C)
the SS pin is released, VOrises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require additional
derating at elevated temperatures.
7.3.5 Prebiased Start-Up
The LMZ23605 will properly start up into a prebiased output. This start-up situation is common in multiple rail
logic applications where current paths may exist between different power rails during the start-up sequence.
Figure 46 shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.5-V prebias rising
to 3.3 V. Rise-time determined by CSS, trace three.
Figure 46. Prebiased Start-Up
7.3.6 Tracking Supply Divider Option
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the
3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration
allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails
during ramp-up is small (that is, < 0.15 V typical). The values for the tracking resistive divider must be selected
such that the effect of the internal 50-µA current source is minimized. In most cases the ratio of the tracking
divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode
dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy satisfy
because the CSS cap is replaced by RTKB. The tracking function is only supported for the power up interval of the
master supply; once the SS/TRK rises past 0.8 V the input is no longer enabled and the 50-µA internal current
source is switched off.
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1.07k
Rfbb
2.26k
Rfbt
107
Rtkb
226
Rtkt
SS/TRK
3.3V Master
FB
2.5Vout
50 PA
Int VCC
LMZ23605
SNVS659I –MARCH 2011–REVISED AUGUST 2015
www.ti.com
Feature Description (continued)
Figure 47. Tracking Option Input Detail
7.4 Device Functional Modes
7.4.1 Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). In CCM, current flows through the
inductor through the entire switching cycle and never falls to zero during the OFF-time. When operating in DCM,
inductor current is maintained to an average value equaling IOUT. Inductor current exhibits normal behavior for
the emulated current mode control method used. Output voltage ripple typically increases during this mode of
operation.
Figure 48 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
VIN = 12 V, VO= 3.3 V, IO= 3 A / 0.3 A 2 μs/div
Figure 48. CCM and DCM Operating Modes
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4
5
6
7
3
2
1
PGND/EP
VOUT
SS
SYNC
FB
VIN
EN
AGND
VIN
CIN2,3
10 PF
Enable
7V to 36V
U1
RFBB
1.07k
LMZ23605TZ
3.3VO @ 5A
CO1,6
0.047 PFCO5
220 PF
RENH OPT
100
RENT
42.2k
RENB
12.7k
RFBT
3.32k
CIN1,5
0.047 PFCO2
100 PF
OPT
+
D1 OPT
5.1V
SYNC
RSNOPT
1.50 k:
CSS
0.47 PF
CIN6 OPT
150 PF
+
RFRA OPT
23.7:
LMZ23605
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ23605 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 5 A. The following design procedure can be used to select
components for the LMZ23605. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
Figure 49. Typical Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist:
• VIN Range = Up to 36 V
• VOUT =0.8Vto6V
• IOUT =5A
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps
The LMZ23605 is fully supported by WEBENCH which offers: component selection, electrical and thermal
simulations. Additionally there are both evaluation and demonstration boards that may be used as a starting point
for design. The following list of steps can be used to manually design the LMZ23605 application.
All references to values refer to the Figure 49.
1. Select minimum operating VIN with enable divider resistors
2. Program VOwith resistor divider selection
3. Select CO
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ENABLE
2.0M
21 PA
INT-VCC (5V)
1.279V
RUN
12.7k
RENB
42.2k
RENT
VIN
100:
RENH
5.1V
LMZ23605
SNVS659I –MARCH 2011–REVISED AUGUST 2015
www.ti.com
Typical Application (continued)
4. Select CIN
5. Determine module power dissipation
6. Layout PCB for required thermal performance
8.2.2.2 Enable Divider, RENT, RENB and RENH Selection
Internal to the module is a 2-MΩpullup resistor connected from VIN to Enable. For applications not requiring
precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will
always enable the module. In such case, the internal UVLO occurs typically at 4.3 V (VINrising).
In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case
of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than
the LMZ23605 output rail.
Enable provides a precise 1.279-V threshold to allow direct logic drive or connection to a voltage divider from a
higher enable voltage such as VIN. Additionally there is 21 μA (typical) of switched offset current allowing
programmable hysteresis. See Figure 50.
The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will
be disabled. This implements the feature of programmable UVLO. The two resistors must be chosen based on
the following ratio:
RENT / RENB = (VIN UVLO / 1.279 V) – 1 (1)
The LMZ23605 typical application shows 12.7 kΩfor RENB and 42.2 kΩfor RENT resulting in a rising UVLO of
5.46 V. This divider presents 8.33 V to the input when the divider is raised to 36 V which would exceed the
recommended 5.5-V limit for Enable. A midpoint 5.1-V Zener clamp is applied to allow the application to cover
the full 6 V to 36 V range of operation. The Zener clamp is not required if the target application prohibits the
maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of RENH. It is possible to select values for
RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
VEN(rising) = 1.279 ( 1 + (RENT|| 2 meg)/ RENB) (2)
Whereas the falling threshold level can be calculated using:
VEN(falling) = VEN(rising) – 21 µA ( RENT|| 2 meg || RENTB + RENH ) (3)
Figure 50. Enable input detail
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Typical Application (continued)
8.2.2.3 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VOand ground. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO= 0.796 V × (1 + RFBT / RFBB) (4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO/ 0.796 V) - 1 (5)
These resistors must generally be chosen from values in the range of 1.0 kΩto 10.0 kΩ.
For VO= 0.8 V the FB pin can be connected to the output directly and RFBB can be set to 8.06 kΩto provide
minimum output load.
Table 1 lists the values for RFBT and RFBB.
Table 1. Typical Application Bill of Materials
REF DES DESCRIPTION CASE SIZE MANUFACTURER MANUFACTURER P/N
U1 SIMPLE SWITCHER PFM-7 Texas Instruments LMZ23605TZ
Cin1,5 0.047 µF, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473
Cin2,3 10 µF, 50 V, X7R 1210 Taiyo Yuden UMK325BJ106MM-T
Cin6 (OPT) CAP, AL, 150 µF, 50 V Radial G Panasonic EEE-FK1H151P
CO1,6 0.047 µF, 50 V, X7R 1206 Yageo America CC1206KRX7R9BB473
CO2 (OPT) 100 µF, 6.3 V, X7R 1210 TDK C3225X5R0J107M
CO5 220 μF, 6.3 V, SP-Cap (7343) Panasonic EEF-UE0J221LR
RFBT 3.32 kΩ0805 Panasonic ERJ-6ENF3321V
RFBB 1.07 kΩ0805 Panasonic ERJ-6ENF1071V
RSN (OPT) 1.50 kΩ0805 Vishay Dale CRCW08051K50FKEA
RENT 42.2 kΩ0805 Panasonic ERJ-6ENF4222V
RENB 12.7 kΩ0805 Panasonic ERJ-6ENF1272V
RFRA(OPT) 23.7Ω0805 Vishay Dale CRCW080523R7FKEA
RENH (OPT) 100 Ω0805 Vishay Dale CRCW0805100RFKEA
CSS 0.47 μF, ±10%, X7R, 16 V 0805 AVX 0805YC474KAT2A
D1(OPT) 5.1V, 0.5 W SOD-123 Diodes Inc. MMSZ5231BS-7-F
8.2.2.4 Soft-Start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turnon, after all UVLO conditions have been passed, an internal 1.6-ms circuit slowly ramps the SS/TRK
input to implement internal soft-start. If 2 ms is an adequate turnon time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft-start duration is given by the formula:
tSS = VREF × CSS / Iss = 0.796 V × CSS / 50 µA (6)
This equation can be rearranged as follows:
CSS = tSS × 50 μA / 0.796 V (7)
Using a 0.22-μF capacitor results in 3.5 ms typical soft-start duration; and 0.47 μF results in 7.5 ms typical. 0.47
μF is a recommended initial value.
As the soft-start input exceeds 0.796 V the output of the power stage will be in regulation and the 50-μA current
is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground
with an internal current sink.
• The Enable input being pulled low
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• Thermal shutdown condition
• Internal VCC UVLO (Approx 4.3-V input to VIN)
8.2.2.5 COSelection
None of the required COoutput capacitance is contained within the module. A minimum value of 200 μF is
required based on the values of internal compensation in the error amplifier. Low ESR tantalum, organic
semiconductor or specialty polymer capacitor types are recommended for obtaining lowest ripple. The output
capacitor COmay consist of several capacitors in parallel placed in close proximity to the module. The output
capacitor assembly must also meet the worst case minimum ripple current rating of 0.5 × ILR P-P, as calculated in
Equation 14 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low
enough to permit it. Loop response verification is also valuable to confirm closed loop behavior.
For applications with dynamic load steps; the following equation provides a good first pass approximation of CO
for load transient requirements. Where VO-Tran is 100 mV on a 3.3-V output design.
CO≥IO-Tran / (VO-Tran – ESR × IO-Tran) × (Fsw / VO) (8)
Solving:
CO≥4.5 A / (0.1 V – .007 × 4.5) × ( 800000 / 3.3) ≥271 μF (9)
NOTE
The stability requirement for 200 µF minimum output capacitance will take precedence.
One recommended output capacitor combination is a 220-µF, 7-mΩESR specialty polymer cap in parallel with a
100-µF 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements
of certain applications. Additionally some small ceramic capacitors can be used for high frequency EMI
suppression.
8.2.2.6 CIN Selection
The LMZ23605 module contains a small amount of internal ceramic input capacitors. Additional input
capacitance is required external to the module to handle the input ripple current of the application. The input
capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to
the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather
than by capacitance value. Input ripple current rating is dictated by the equation:
I(CIN(RMS))≊1 / 2 × IO× SQRT (D / 1 – D)
where
• D ≊VO/ VIN (10)
As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when VIN = 2 × VO
Recommended minimum input capacitance is 22uF X7R (or X5R) ceramic with a voltage rating at least 25%
higher than the maximum applied input voltage for the application. It is also recommended that attention be paid
to the voltage and temperature derating of the capacitor selected.
NOTE
The ripple current rating of ceramic capacitors may be missing from the capacitor data
sheet and you may have to contact the capacitor manufacturer for this parameter.
If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔVIN) be maintained
then the following equation may be used.
CIN ≥IO× D × (1 – D) / fSW-CCM ×ΔVIN (11)
If ΔVIN is 1% of VIN for a 12-V input to 3.3-V output application this equals 120 mV and fSW = 812 kHz.
CIN ≥5 A × 3.3 V / 12 V × (1 – 3.3 V / 12 V) / (812000 × 0.12 V) (12)
≥10.2 μF
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0 200 400 600 800 1000
0
5
10
15
20
25
30
35
40
45
50
AMPLITUDE (dBuV/m)
FREQUENCY (MHz)
Class A Limit
Class B Limit
Horiz Peak
Horiz Quasi-peak
012345
0
10
20
30
40
50
60
70
80
90
100
0
1
2
3
4
5
EFFICIENCY (%)
OUTPUT CURRENT (A)
DISSIPATION (W)
30 40 50 60 70 80 90 100 110120 130
0
1
2
3
4
5
6
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
JA=12°C/W
LMZ23605
www.ti.com
SNVS659I –MARCH 2011–REVISED AUGUST 2015
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines. The LMZ23605 typical applications schematic
and evaluation board include a 150-μF 50-V aluminum capacitor for this function. There are many situations
where this capacitor is not necessary.
8.2.2.7 Discontinuous Conduction and Continuous Conduction Mode Selection
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊VO× (VIN – VO) / (2 × 3.3 μH × fSW(CCM) × VIN) (13)
The inductor internal to the module is 3.3 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
ILR P-P = VO× (VIN– VO) / (3.3 µH × fSW × VIN)
Where
• VIN is the maximum input voltage
• fSW is typically 812 kHz (14)
If the output current IOis determined by assuming that IO= IL, the higher and lower peak of ILR can be
determined.
8.2.3 Application Curves
VIN = 12 V, VOUT = 5 V VIN = 12 V, VOUT = 5 V
Figure 51. Efficiency Figure 52. Thermal Derating Curve
Figure 53. Radiated EMI (EN 55022)
of Demo Board (See SNVA473)
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9 Power Supply Recommendations
The LMZ23605 device is designed to operate from an input voltage supply range between 6 V and 36 V. This
input supply must be well regulated and able to withstand maximum input current and maintain a stable voltage.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMZ23605 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is more than a few inches from the LMZ23605, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF
electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in
the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as
shown in the figure above. The high current loops that do not overlap have high di/dt content that will cause
observable high frequency noise on the output pin if the input capacitor (CIN1) is placed at a distance away
from the LMZ23605. Therefore place CIN1 as close as possible to the LMZ23605 VIN and PGND exposed
pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input
and output capacitor must consist of a localized top side plane that connects to the PGND exposed pad
(EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components must be routed to the AGND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Additionally provide the single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Since the FB node is high
impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB must be routed away
from the body of the LMZ23605 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to
inner layer heat-spreading ground planes. For best results use a 6 × 10 via array with a minimum via
diameter of 8 mils thermal vias spaced 39 mils (1.0 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
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SYNC
EN
FB
GND
SS
VIN
1 2 3 4 5 6 7
Top View
VIN
COUT
VOUT
RENT
GND
Thermal Vias
VOUT
CIN
GND
RENB
CFF
RFBT
RFBB
GND Plane
EPAD
CSS
SYNC
VIN
GND
VIN
VO
Cin1 CO1
Loop 1 Loop 2
LMZ23605 VOUT
High
di/dt
LMZ23605
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SNVS659I –MARCH 2011–REVISED AUGUST 2015
10.2 Layout Examples
Figure 54. Critical Current Loops to Minimize
Figure 55. PCB Layout Guide
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Layout Examples (continued)
Figure 56. Top View Evaluation Board – See AN–2085 SNVA457
Figure 57. Bottom View Demonstration Board
10.3 Power Dissipation and Thermal Considerations
When calculating module dissipation use the maximum input voltage and the average output current for the
application. Many common operating conditions are provided in the characteristic curves such that less common
applications can be derived through interpolation. In all designs, the junction temperature must be kept below the
rated maximum of 125°C.
For the design case of VIN = 24 V, VO= 3.3 V, IO= 5 A, and TAMB(MAX) = 85°C, the module must see a thermal
resistance from case to ambient of less than:
RθCA< (TJ-MAX – TA-MAX) / PIC-LOSS – RθJC (15)
Given the typical thermal resistance from junction to case to be 1.9°C/W. Use the 85°C power dissipation curves
in the Typical Characteristics section to estimate the PIC-LOSS for the application being designed. In this
application it is 5.5 W.
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Power Dissipation and Thermal Considerations (continued)
NOTE
For package dissipations above 5-W air flow or external heat sinking may be required.
RθCA = (125 – 85) / 5.5 W – 1.9 = 5.37 (16)
To reach RθCA = 5.37, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink,
a good estimate of the required board area covered by 2-oz. copper on both the top and bottom metal layers is:
Board_Area_cm2= 500°C × cm2/ W / RθCA (17)
As a result, approximately 93 square cm of 2-oz. copper on top and bottom layers is required for the PCB
design. The PCB copper heat sink must be connected to the exposed pad. Approximately sixty, 8 mil thermal
vias spaced 39 mils (1.0 mm) apart connect the top copper to the bottom copper. For an example of a high
thermal performance PCB layout for SIMPLE SWITCHER power modules, refer to SNVA457,SNVA473,
SNVA419 and SNVA424.
10.4 Power Module SMT Guidelines
The recommendations below are for a standard module surface mount assembly
• Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
– For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land
pattern
– For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness — 0.125 to 0.15 mm
• Reflow — Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information.
• Maximum number of reflows allowed is one
Figure 58. Sample Reflow Profile
Table 2. Sample Reflow Profile Table
MAX TEMP REACHED TIME ABOVE REACHED TIME ABOVE REACHED TIME ABOVE REACHED
PROBE (°C) MAX TEMP 235°C 235°C 245°C 245°C 260°C 260°C
1242.5 6.58 0.49 6.39 0.00 – 0.00 –
2242.5 7.10 0.55 6.31 0.00 7.10 0.00 –
3241.0 7.09 0.42 6.44 0.00 – 0.00 –
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For developmental support, see the following:
WEBENCH Tool, http://www.ti.com/webench
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• AN-2027 Inverting Application for the LMZ14203 SIMPLE SWITCHER Power Module, (SNVA425)
•Absolute Maximum Ratings for Soldering, (SNOA549)
• AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422)
• AN-2085 LMZ23605/03, LMZ22005/03 Evaluation Board (SNVA457)
• AN-2054 Evaluation Board for LM10000 - PowerWise AVS System Controller (SNVA437)
•Step-Down DC-DC Converter with Integrated Low Dropout Regulator and Startup Mode (SNVA473)
• AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
• AN-2026 Effect of PCB Design on Thermal Performance of SIMPLE SWITCHER Power Modules (SNVA424)
•Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LMZ23605
LMZ23605
www.ti.com
SNVS659I –MARCH 2011–REVISED AUGUST 2015
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LMZ23605
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMZ23605TZ/NOPB ACTIVE TO-PMOD NDW 7 45 RoHS & Green SN Level-3-245C-168 HR -40 to 85 LMZ23605
LMZ23605TZE/NOPB ACTIVE TO-PMOD NDW 7 250 RoHS & Green SN Level-3-245C-168 HR -40 to 85 LMZ23605
LMZ23605TZX/NOPB ACTIVE TO-PMOD NDW 7 500 RoHS & Green SN Level-3-245C-168 HR -40 to 85 LMZ23605
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMZ23605TZE/NOPB TO-
PMOD NDW 7 250 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
LMZ23605TZX/NOPB TO-
PMOD NDW 7 500 330.0 24.4 10.6 14.22 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMZ23605TZE/NOPB TO-PMOD NDW 7 250 367.0 367.0 45.0
LMZ23605TZX/NOPB TO-PMOD NDW 7 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2018
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
www.ti.com
TZA07A (Rev D)
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
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