Kinetis KL36 Sub-Family
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K3x family. General purpose
MCU with segment LCD, featuring market leading ultra low-
power to provide developers an appropriate entry-level 32-bit
solution.
This product offers:
• Run power consumption down to 50 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4.5 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
• Memory option is up to 256 KB Flash and 32 KB RAM
• Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
Performance
• 48 MHz ARM® Cortex®-M0+ core
Memories and memory interfaces
• Up to 256 KB program flash memory
• Up to 32 KB SRAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request
sources
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Clocks
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Human-machine interface
• Segment LCD controller supporting up to 47
frontplanes and 8 backplanes, or 51 frontplanes and
4 backplanes
• Low-power hardware touch sensor interface (TSI)
• Up to 84 general-purpose input/output (GPIO)
Communication interfaces
• Two 16-bit SPI modules
• I2S (SAI) module
• One low power UART module
• Two UART modules
• Two I2C module
Analog Modules
• 16-bit SAR ADC
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
• Periodic interrupt timers
MKL36ZxxxVLH4
MKL36Z256VMP4,
MKL36ZxxxVLL4
MKL36ZxxxVMC4
64-pin LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
64-pin MAPBGA (MP)
5 x 5 x 1.23 Pitch 0.5
mm
100-pin LQFP (LL)
14 x 14 x 1.4 Pitch 0.5
mm
121-pin MAPBGA (MP)
8 x 8 x 0.8 Pitch 0.65
mm
Freescale Semiconductor, Inc. Document Number: KL36P121M48SF4
Data Sheet: Technical Data Rev 5 08/2014
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
• 16-bit low-power timer (LPTMR)
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
Ordering Information 1
Part Number Memory Maximum number of I\O's
Flash (KB) SRAM (KB)
MKL36Z64VLH4 64 8 54
MKL36Z128VLH4 128 16 54
MKL36Z256VLH4 256 32 54
MKL36Z256VMP4 256 32 54
MKL36Z64VLL4 64 8 84
MKL36Z128VLL4 128 16 84
MKL36Z256VLL4 256 32 84
MKL36Z128VMC4 128 16 84
MKL36Z256VMC4 256 32 84
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type Description Resource
Selector Guide The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of
the structure and function (operation) of a device.
KL36P121M48SF4RM1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
KL36P121M48SF41
Chip Errata The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_L_xN40H2
Package
drawing
Package dimensions are provided in package drawings. LQFP 64-pin: 98ASS23234W1
MAPBGA 64-pin: 98ASA00420D1
LQFP 100-pin: 98ASS23308W1
MAPBGA 121-pin: 98ASA00344D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x”
replaced by the revision of the device you are using.
2Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................4
1.1 Thermal handling ratings............................................... 4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings..................................................... 4
1.4 Voltage and current operating ratings............................4
2 General................................................................................. 5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................5
2.2.1 Voltage and current operating requirements......6
2.2.2 LVD and POR operating requirements.............. 6
2.2.3 Voltage and current operating behaviors...........7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC radiated emissions operating behaviors... 15
2.2.7 Designing with radiated emissions in mind........16
2.2.8 Capacitance attributes....................................... 16
2.3 Switching specifications.................................................16
2.3.1 Device clock specifications................................ 16
2.3.2 General switching specifications........................17
2.4 Thermal specifications................................................... 17
2.4.1 Thermal operating requirements........................17
2.4.2 Thermal attributes..............................................17
3 Peripheral operating requirements and behaviors................ 18
3.1 Core modules................................................................ 18
3.1.1 SWD electricals .................................................18
3.2 System modules............................................................ 20
3.3 Clock modules............................................................... 20
3.3.1 MCG specifications............................................20
3.3.2 Oscillator electrical specifications...................... 22
3.4 Memories and memory interfaces................................. 24
3.4.1 Flash electrical specifications............................ 24
3.5 Security and integrity modules.......................................26
3.6 Analog............................................................................26
3.6.1 ADC electrical specifications..............................26
3.6.2 CMP and 6-bit DAC electrical specifications......31
3.6.3 12-bit DAC electrical characteristics.................. 33
3.7 Timers............................................................................36
3.8 Communication interfaces............................................. 36
3.8.1 SPI switching specifications...............................36
3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....41
3.8.3 UART................................................................. 42
3.8.4 I2S/SAI switching specifications........................ 42
3.9 Human-machine interfaces (HMI)..................................46
3.9.1 TSI electrical specifications................................46
3.9.2 LCD electrical characteristics.............................47
4 Dimensions........................................................................... 48
4.1 Obtaining package dimensions......................................48
5 Pinout....................................................................................49
5.1 KL36 Signal Multiplexing and Pin Assignments.............49
5.2 KL36 pinouts..................................................................53
6 Ordering parts....................................................................... 57
6.1 Determining valid orderable parts..................................57
7 Part identification...................................................................58
7.1 Description.....................................................................58
7.2 Format........................................................................... 58
7.3 Fields............................................................................. 58
7.4 Example.........................................................................59
8 Terminology and guidelines.................................................. 59
8.1 Definition: Operating requirement..................................59
8.2 Definition: Operating behavior....................................... 59
8.3 Definition: Attribute........................................................ 59
8.4 Definition: Rating........................................................... 60
8.5 Result of exceeding a rating.......................................... 60
8.6 Relationship between ratings and operating
requirements..................................................................61
8.7 Guidelines for ratings and operating requirements........61
8.8 Definition: Typical value.................................................61
8.9 Typical value conditions.................................................62
9 Revision history.....................................................................63
Kinetis KL36 Sub-Family, Rev5 08/2014. 3
Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
–500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Ratings
4Kinetis KL36 Sub-Family, Rev5 08/2014.
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1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO IO pin input voltage –0.3 VDD + 0.3 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
General
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2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO IO pin negative DC injection current — single pin
• VIN < VSS-0.3V -3 — mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
• Negative current injection -25 — mA
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 — V
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V —
VLVDH Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48 2.56 2.64 V —
Low-voltage warning thresholds — high range 1
Table continues on the next page...
General
6Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±60 — mV —
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V —
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±40 — mV —
VBG Bandgap voltage reference 0.97 1.00 1.03 V —
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs —
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad (except
RESET_b)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
VOH Output high voltage — High drive pad (except
RESET_b)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
1, 2
IOHT Output high current total for all ports — 100 mA
VOL Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
0.5
V
V
1
Table continues on the next page...
General
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Table 7. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
VOL Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
0.5
V
V
1
IOLT Output low current total for all ports — 100 mA
IIN Input leakage current (per pin) for full temperature
range
— 1 μA 3
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3
IIN Input leakage current (total all pins) for full
temperature range
— μA 3
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ 4
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
113
124
μs
Table continues on the next page...
General
8Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• VLLS1 → RUN — 112 124 μs
• VLLS3 → RUN
—
53
60
μs
• LLS → RUN
—
4.5
5.0
μs
• VLPS → RUN
—
4.5
5.0
μs
• STOP → RUN
—
4.5
5.0
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol Description Typ. Max Unit Note
IDDA Analog supply current — — See note mA 1
IDD_RUNCO_ CM Run mode current in compute operation
- 48 MHz core / 24 MHz flash/ bus
disabled, LPTMR running using 4 MHz
internal reference clock, CoreMark®
benchmark code executing from flash,
at 3.0 V
— 6.7 — mA 2
IDD_RUNCO Run mode current in compute operation
- 48 MHz core / 24 MHz flash / bus
clock disabled, code of while(1) loop
executing from flash, at 3.0 V
— 4.5 5.1 mA 3
IDD_RUN Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
disabled, code executing from flash
at 1.8 V 5.6 6.3 mA 3
at 3.0 V 5.4 6.0 mA
IDD_RUN Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
enabled, code executing from flash, at
1.8 V
— 6.9 7.3 mA 3, 4
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral clocks
enabled, code executing from flash, at
3.0 V
at 25 °C 6.9 7.1 mA
at 125 °C 7.3 7.6 mA
Table continues on the next page...
General
Kinetis KL36 Sub-Family, Rev5 08/2014. 9
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Typ. Max Unit Note
IDD_WAIT Wait mode current - core disabled / 48
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
— 2.9 3.5 mA 3
IDD_WAIT Wait mode current - core disabled / 24
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), wait
mode reduced frequency current at 3.0
V — all peripheral clocks disabled
— 2.2 2.8 mA 3
IDD_PSTOP2 Stop mode current with partial stop 2
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
— 1.6 2.1 mA 3
IDD_VLPRCO _CM Very-low-power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, LPTMR
running with 4 MHz internal reference
clock, CoreMark benchmark code
executing from flash, at 3.0 V
— 798 — µA 5
IDD_VLPRCO Very low power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, code
executing from flash, at 3.0 V
— 167 336 µA 6
IDD_VLPR Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks disabled, code
executing from flash, at 3.0 V
— 192 354 µA 6
IDD_VLPR Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks enabled, code
executing from flash, at 3.0 V
— 257 431 µA 4, 6
IDD_VLPW Very low power wait mode current -
core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled,
at 3.0 V
— 112 286 µA 6
IDD_STOP Stop mode current at 3.0 V at 25 °C 306 328 µA —
at 50 °C 322 349 µA
at 70 °C 348 382 µA
at 85 °C 384 433 µA
at 105 °C 481 578 µA
IDD_VLPS Very-low-power stop mode current at
3.0 V
at 25 °C 2.71 5.03 µA —
at 50 °C 7.05 11.94 µA
at 70 °C 15.80 26.87 µA
at 85 °C 29.60 47.30 µA
at 105 °C 69.13 106.04 µA
Table continues on the next page...
General
10 Kinetis KL36 Sub-Family, Rev5 08/2014.
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Table 9. Power consumption operating behaviors (continued)
Symbol Description Typ. Max Unit Note
IDD_LLS Low leakage stop mode current at 3.0
V
at 25 °C 2.00 2.7 µA —
at 50 °C 3.96 5.14 µA
at 70 °C 7.77 10.71 µA
at 85 °C 14.15 18.79 µA
at 105 °C 33.20 43.67 µA
IDD_VLLS3 Very low-leakage stop mode 3 current
at 3.0 V
at 25 °C 1.5 2.2 µA —
at 50 °C 2.83 3.55 µA
at 70 °C 5.53 7.26 µA
at 85 °C 9.92 12.71 µA
at 105 °C 22.90 29.23 µA
IDD_VLLS1 Very low-leakage stop mode 1 current
at 3.0V
at 25 °C 0.71 1.2 µA —
at 50 °C 1.27 1.9 µA
at 70 °C 2.48 3.51 µA
at 85 °C 4.65 6.29 µA
at 105 °C 11.55 14.34 µA
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0
V
at 25 °C 0.41 0.9 µA —
at 50 °C 0.96 1.56 µA
at 70 °C 2.17 3.1 µA
at 85 °C 4.35 5.32 µA
at 105 °C 11.24 14.00 µA
IDD_VLLS0 Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0
V
at 25 °C 0.23 0.69 µA 7
at 50 °C 0.77 1.35 µA
at 70 °C 1.98 2.52 µA
at 85 °C 4.16 5.14 µA
at 105 °C 11.05 13.80 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
General
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Table 10. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
206 228 237 245 251 258 µA
IEREFSTEN32KHz External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with the
crystal enabled.
VLLS1 440 490 540 560 570 580 nA
VLLS3 440 490 540 560 570 580
LLS 490 490 540 560 570 680
VLPS 510 560 560 560 610 680
STOP 510 560 560 560 610 680
ICMP CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM set
for 1 minute. Includes ERCLK32K (32 kHz
external crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
66 66 66 66 66 66 µA
OSCERCLK
(4 MHz
external
crystal)
214 237 246 254 260 268
ITPM TPM peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and I/O
switching currents.
MCGIRCLK
(4 MHz
internal
reference
clock)
86 86 86 86 86 86 µA
OSCERCLK
(4 MHz
external
crystal)
235 256 265 274 280 287
Table continues on the next page...
General
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Table 10. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IBG Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
366 366 366 366 366 366 µA
ILCD LCD peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
OSC0_CR[EREFSTEN, EREFSTEN] bits.
VIREG disabled, resistor bias network
enabled, 1/8 duty cycle, 8 x 36 configuration
for driving 288 Segments, 32 Hz frame rate,
no LCD glass connected. Includes
ERCLK32K (32 kHz external crystal) power
consumption.
555555µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
Kinetis KL36 Sub-Family, Rev5 08/2014. 13
Freescale Semiconductor, Inc.
4.00E-03
5.00E-03
6.00E-03
7.00E-03
8.00E-03
All Off
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
All Peripheral CLK Gates
000.00E+00
1.00E-03
2.00E-03
3.00E-03
'1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2
1 2 3 4 6 12 24 48
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD(A)
Run Mode Current Vs Core Frequency
Figure 3. Run mode supply current vs. core frequency
General
14 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
200.00E-06
250.00E-06
300.00E-06
350.00E-06
VLPR Mode Current Vs Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
All Peripheral CLK Gates
000.00E+00
50.00E-06
100.00E-06
150.00E-06
'1
-
1
'1
-
2
'1
-
2
'1
-
4
1 2 4
All Off
All On
CLK Ratio
Flash-Core
Core Freq (MHz)
Current Consumption on VDD (A)
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 12 dBμV 1,2
VRE2 Radiated emissions voltage, band 2 50–150 8 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 7 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 4 dBμV
VRE_IEC IEC level 0.15–1000 M — 2,3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
General
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Freescale Semiconductor, Inc.
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol Description Min. Max. Unit
CIN Input capacitance — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol Description Min. Max. Unit
Normal run mode
fSYS System and core clock — 48 MHz
fBUS Bus clock — 24 MHz
fFLASH Flash clock — 24 MHz
fLPTMR LPTMR clock — 24 MHz
VLPR and VLPS modes1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock2— 24 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
— 16 MHz
fTPM TPM asynchronous clock — 8 MHz
fUART0 UART0 asynchronous clock — 8 MHz
General
16 Kinetis KL36 Sub-Family, Rev5 08/2014.
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1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5 — Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time — 36 ns 3
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
General
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2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type Symbol Description 121
MAPBG
A
100
LQFP
64
LQFP
64
MAPBG
A
Unit Notes
Single-layer (1S) RθJA Thermal resistance, junction
to ambient (natural
convection)
94 64 69 49.8 °C/W 1
Four-layer (2s2p) RθJA Thermal resistance, junction
to ambient (natural
convection)
57 51 51 42.3 °C/W
Single-layer (1S) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
81 54 58 40.9 °C/W
Four-layer (2s2p) RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
53 45 44 37.7 °C/W
— RθJB Thermal resistance, junction
to board
40 37 33 39.2 °C/W 2
— RθJC Thermal resistance, junction
to case
30 19 19 50.3 °C/W 3
—ΨJT Thermal characterization
parameter, junction to
package top outside center
(natural convection)
8 4 4 2.2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
Peripheral operating requirements and behaviors
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3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
• Serial wire debug
20
—
ns
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 5. Serial wire clock input timing
Peripheral operating requirements and behaviors
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Freescale Semiconductor, Inc.
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
— ± 0.3 ± 0.6 %fdco 1
Table continues on the next page...
Peripheral operating requirements and behaviors
20 Kinetis KL36 Sub-Family, Rev5 08/2014.
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Table 18. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ± 3 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
— ± 0.4 ± 1.5 %fdco 1, 2
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
— 4 — MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
— +1/-2 ± 3 %fintf_ft 2
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency — (16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS = 00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01)
1280 × ffll_ref
40 41.94 48 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
— 23.99 — MHz 5, 6
Mid range (DRS = 01)
1464 × ffll_ref
— 47.97 — MHz
Jcyc_fll FLL period jitter
• fVCO = 48 MHz
— 180 — ps 7
tfll_acquire FLL target frequency acquisition time — — 1 ms 8
PLL
fvco VCO operating frequency 48.0 — 100 MHz
Ipll PLL operating current
• PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
— 1060 — µA 9
Ipll PLL operating current
• PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
— 600 — µA 9
fpll_ref PLL reference frequency range 2.0 — 4.0 MHz
Jcyc_pll PLL period jitter (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
—
—
120
—
—
ps
ps
10
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 18. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Jacc_pll PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
—
—
1350
600
—
—
ps
ps
10
Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 %
Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 %
tpll_lock Lock detector detection time — — 150 × 10-6
+ 1075(1/
fpll_ref)
s11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
nA
μA
μA
μA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 19. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
• 24 MHz
• 32 MHz
— 1.5 — mA
IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
Peripheral operating requirements and behaviors
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3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 48 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
Peripheral operating requirements and behaviors
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3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversblk128k Erase Block high-voltage time for 128 KB — 52 452 ms 1
thversall Erase All high-voltage time — 52 452 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk128k
Read 1s Block execution time
• 128 KB program flash
—
—
1.7
ms
—
trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersblk128k
Erase Flash Block execution time
• 128 KB program flash
—
88
600
ms
2
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 1.8 ms —
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs —
tersall Erase All Blocks execution time — 175 1300 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Peripheral operating requirements and behaviors
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3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
Peripheral operating requirements and behaviors
26 Kinetis KL36 Sub-Family, Rev5 08/2014.
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3.6.1.1 16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V —
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V —
CADIN Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF —
RADIN Input series
resistance
— 2 5 kΩ —
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 18.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
818.330
Ksps
5
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
—
461.467
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 27
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RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 7. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to 0.5
LSB45
Table continues on the next page...
Peripheral operating requirements and behaviors
28 Kinetis KL36 Sub-Family, Rev5 08/2014.
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Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN =
VDDA5
EQQuantization
error
• 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number
of bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise
plus distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
82
78
95
90
—
—
dB
dB
7
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 8
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 29
Freescale Semiconductor, Inc.
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Peripheral operating requirements and behaviors
30 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
3.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1,
PMODE=1)
— — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 31
Freescale Semiconductor, Inc.
00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
32 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
00
01
10
HYSTCTR
Setting
10
11
0.1 3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.1
0
0.02
0.04
0.06
0.18
0.14
0.12
0.08
0.16
Vin level (V)
CMP Hysteresis (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 33
Freescale Semiconductor, Inc.
3.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 250 μA
IDDA_DACH
P
Supply current — high-speed mode — — 900 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
34 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 12. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 35
Freescale Semiconductor, Inc.
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
36 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 30. SPI master mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 18 — ns —
7 tHI Data hold time (inputs) 0 — ns —
8 tvData valid (after SPSCK edge) — 15 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 31. SPI master mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1
2 tSPSCK SPSCK period 2 x tperiph 2048 x
tperiph
ns 2
3 tLead Enable lead time 1/2 — tSPSCK —
4 tLag Enable lag time 1/2 — tSPSCK —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x
tperiph
ns —
6 tSU Data setup time (inputs) 96 — ns —
7 tHI Data hold time (inputs) 0 — ns —
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 37
Freescale Semiconductor, Inc.
Table 31. SPI master mode timing on slew rate enabled pads (continued)
Num. Symbol Description Min. Max. Unit Note
8 tvData valid (after SPSCK edge) — 52 ns —
9 tHO Data hold time (outputs) 0 — ns —
10 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
11 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
(OUTPUT)
2
8
6 7
MSB IN2
LSB IN
MSB OUT2 LSB OUT
9
5
5
3
(CPOL=0)
4
11
11
10
10
SPSCK
SPSCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) BIT 6 . . . 1
BIT 6 . . . 1
Figure 14. SPI master mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
38 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
2
6 7
MSB IN2
BIT 6 . . . 1
MASTER MSB OUT2 MASTER LSB OUT
5
5
8
10 11
PORT DATA PORT DATA
310 11 4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
9
(OUTPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS1
(OUTPUT)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT) LSB IN
BIT 6 . . . 1
Figure 15. SPI master mode timing (CPHA = 1)
Table 32. SPI slave mode timing on slew rate disabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2.5 — ns —
7 tHI Data hold time (inputs) 3.5 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 31 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 25 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 39
Freescale Semiconductor, Inc.
Table 33. SPI slave mode timing on slew rate enabled pads
Num. Symbol Description Min. Max. Unit Note
1 fop Frequency of operation 0 fperiph/4 Hz 1
2 tSPSCK SPSCK period 4 x tperiph — ns 2
3 tLead Enable lead time 1 — tperiph —
4 tLag Enable lag time 1 — tperiph —
5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns —
6 tSU Data setup time (inputs) 2 — ns —
7 tHI Data hold time (inputs) 7 — ns —
8 taSlave access time — tperiph ns 3
9 tdis Slave MISO disable time — tperiph ns 4
10 tvData valid (after SPSCK edge) — 122 ns —
11 tHO Data hold time (outputs) 0 — ns —
12 tRI Rise time input — tperiph - 25 ns —
tFI Fall time input
13 tRO Rise time output — 36 ns —
tFO Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
2
10
6 7
MSB IN
BIT 6 . . . 1
SLAVE MSB SLAVE LSB OUT
11
5
5
3
8
4
13
NOTE: Not defined
12
12
11
SEE
NOTE
13
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
LSB IN
BIT 6 . . . 1
Figure 16. SPI slave mode timing (CPHA = 0)
Peripheral operating requirements and behaviors
40 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
2
6 7
MSB IN
BIT 6 . . . 1
MSB OUT SLAVE LSB OUT
5
5
10
12 13
312 13
4
SLAVE
8
9
see
note
(INPUT)
(CPOL=0)
SPSCK
SPSCK
(CPOL=1)
SS
(INPUT)
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
NOTE: Not defined
11
LSB IN
BIT 6 . . . 1
Figure 17. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 34. I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.3 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 41
Freescale Semiconductor, Inc.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 18. Timing definition for fast and standard mode devices on the I2C bus
3.8.3 UART
See General switching specifications.
3.8.4 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
Peripheral operating requirements and behaviors
42 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
3.8.4.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 35. I2S/SAI master mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15.5 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 19 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 19. I2S/SAI timing — master modes
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 43
Freescale Semiconductor, Inc.
Table 36. I2S/SAI slave mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 33 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 10 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 28 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 20. I2S/SAI timing — slave modes
3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Peripheral operating requirements and behaviors
44 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 37. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 62.5 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 45
Freescale Semiconductor, Inc.
Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num. Characteristic Min. Max. Unit
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 87 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 22. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 39. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit
TSI_RUNF Fixed power consumption in run mode — 100 — µA
Table continues on the next page...
Peripheral operating requirements and behaviors
46 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table 39. TSI electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
TSI_RUNV Variable power consumption in run mode
(depends on oscillator's current selection)
1.0 — 128 µA
TSI_EN Power consumption in enable mode — 100 — µA
TSI_DIS Power consumption in disable mode — 1.2 — µA
TSI_TEN TSI analog enable time — 66 — µs
TSI_CREF TSI reference capacitor — 1.0 — pF
TSI_DVOLT Voltage variation of VP & VM around nominal
values
0.19 — 1.03 V
3.9.2 LCD electrical characteristics
Table 40. LCD electricals
Symbol Description Min. Typ. Max. Unit Notes
fFrame LCD frame frequency
• GCR[FFR]=0
• GCR[FFR]=1
23.3
46.6
—
—
73.1
146.2
Hz
Hz
CLCD LCD charge pump capacitance — nominal
value
— 100 — nF 1
CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1
CGlass LCD glass capacitance — 2000 8000 pF 2
VIREG VIREG
• RVTRIM=0000
• RVTRIM=1000
• RVTRIM=0100
• RVTRIM=1100
• RVTRIM=0010
• RVTRIM=1010
• RVTRIM=0110
• RVTRIM=1110
• RVTRIM=0001
• RVTRIM=1001
• RVTRIM=0101
• RVTRIM=1101
• RVTRIM=0011
• RVTRIM=1011
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.91
0.92
0.93
0.94
0.96
0.97
0.98
0.99
1.01
1.02
1.03
1.05
1.06
1.07
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V3
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis KL36 Sub-Family, Rev5 08/2014. 47
Freescale Semiconductor, Inc.
Table 40. LCD electricals (continued)
Symbol Description Min. Typ. Max. Unit Notes
• RVTRIM=0111
• RVTRIM=1111
—
—
1.08
1.09
—
—
ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG
IVIREG VIREG current adder — RVEN = 1 — 1 — µA 4
IRBIAS RBIAS current adder
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
—
10
1
—
—
µA
µA
RRBIAS RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
—
0.28
2.98
—
—
MΩ
MΩ
VLL1 VLL1 voltage — — VIREG V5
VLL2 VLL2 voltage — — 2 x VIREG V5
VLL3 VLL3 voltage — — 3 x VIREG V5
VLL1 VLL1 voltage — — VDDA / 3 V 6
VLL2 VLL2 voltage — — VDDA / 1.5 V 6
VLL3 VLL3 voltage — — VDDA V6
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. 2000 pF load LCD, 32 Hz frame frequency
5. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump
is enabled (GCR[CPSEL]=1).
6. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = VDDA
through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is
connected to VDDA externally (GCR[VSUPPLY]=1).
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
Dimensions
48 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
64-pin LQFP 98ASS23234W
64-pin MAPBGA 98ASA00420D
100-pin LQFP 98ASS23308W
121-pin MAPBGA 98ASA00344D
5 Pinout
5.1 KL36 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
121
BGA
100
LQFP
64
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
E4 1 A1 1 PTE0 DISABLED LCD_P48 PTE0 SPI1_MISO UART1_TX RTC_
CLKOUT
CMP0_OUT I2C1_SDA LCD_P48
E3 2 B1 2 PTE1 DISABLED LCD_P49 PTE1 SPI1_MOSI UART1_RX SPI1_MISO I2C1_SCL LCD_P49
E2 3 — — PTE2 DISABLED LCD_P50 PTE2 SPI1_SCK LCD_P50
F4 4 — — PTE3 DISABLED LCD_P51 PTE3 SPI1_MISO SPI1_MOSI LCD_P51
H7 5 — — PTE4 DISABLED LCD_P52 PTE4 SPI1_PCS0 LCD_P52
G4 6 — — PTE5 DISABLED LCD_P53 PTE5 LCD_P53
F3 7 — — PTE6 DISABLED LCD_P54 PTE6 I2S0_MCLK audioUSB_
SOF_OUT
LCD_P54
E6 8 — 3 VDD VDD VDD
G7 9 C4 4 VSS VSS VSS
L6 — — — VSS VSS VSS
H1 14 E1 5 PTE16 ADC0_DP1/
ADC0_SE1
LCD_P55/
ADC0_DP1/
ADC0_SE1
PTE16 SPI0_PCS0 UART2_TX TPM_
CLKIN0
LCD_P55
H2 15 D1 6 PTE17 ADC0_DM1/
ADC0_SE5a
LCD_P56/
ADC0_DM1/
ADC0_SE5a
PTE17 SPI0_SCK UART2_RX TPM_
CLKIN1
LPTMR0_
ALT3
LCD_P56
J1 16 E2 7 PTE18 ADC0_DP2/
ADC0_SE2
LCD_P57/
ADC0_DP2/
ADC0_SE2
PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO LCD_P57
Pinout
Kinetis KL36 Sub-Family, Rev5 08/2014. 49
Freescale Semiconductor, Inc.
121
BGA
100
LQFP
64
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
J2 17 D2 8 PTE19 ADC0_DM2/
ADC0_SE6a
LCD_P58/
ADC0_DM2/
ADC0_SE6a
PTE19 SPI0_MISO I2C0_SCL SPI0_MOSI LCD_P58
K1 18 G1 9 PTE20 ADC0_DP0/
ADC0_SE0
LCD_P59/
ADC0_DP0/
ADC0_SE0
PTE20 TPM1_CH0 UART0_TX LCD_P59
K2 19 F1 10 PTE21 ADC0_DM0/
ADC0_SE4a
LCD_P60/
ADC0_DM0/
ADC0_SE4a
PTE21 TPM1_CH1 UART0_RX LCD_P60
L1 20 G2 11 PTE22 ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22 TPM2_CH0 UART2_TX
L2 21 F2 12 PTE23 ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
PTE23 TPM2_CH1 UART2_RX
F5 22 F4 13 VDDA VDDA VDDA
G5 23 G4 14 VREFH VREFH VREFH
G6 24 G3 15 VREFL VREFL VREFL
F6 25 F3 16 VSSA VSSA VSSA
L3 26 H1 17 PTE29 CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29 TPM0_CH2 TPM_
CLKIN0
K5 27 H2 18 PTE30 DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30 TPM0_CH3 TPM_
CLKIN1
L4 28 H3 19 PTE31 DISABLED PTE31 TPM0_CH4
L5 29 — — VSS VSS VSS
K6 30 — — VDD VDD VDD
H5 31 H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
J5 32 H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
H6 33 — — PTE26 DISABLED PTE26 TPM0_CH5 RTC_
CLKOUT
J6 34 D3 22 PTA0 SWD_CLK TSI0_CH1 PTA0 TPM0_CH5 SWD_CLK
H8 35 D4 23 PTA1 DISABLED TSI0_CH2 PTA1 UART0_RX TPM2_CH0
J7 36 E5 24 PTA2 DISABLED TSI0_CH3 PTA2 UART0_TX TPM2_CH1
H9 37 D5 25 PTA3 SWD_DIO TSI0_CH4 PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
J8 38 G5 26 PTA4 NMI_b TSI0_CH5 PTA4 I2C1_SDA TPM0_CH1 NMI_b
K7 39 F5 27 PTA5 DISABLED PTA5 TPM0_CH2 I2S0_TX_
BCLK
E5 — — — VDD VDD VDD
G3 — — — VSS VSS VSS
K3 40 — — PTA6 DISABLED PTA6 TPM0_CH3
H4 41 — — PTA7 DISABLED PTA7 TPM0_CH4
K8 42 H6 28 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0
L8 43 G6 29 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS
K9 44 — — PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_
BCLK
I2S0_TXD0
Pinout
50 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
121
BGA
100
LQFP
64
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
L9 45 — — PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
J10 46 — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO I2S0_RX_FS I2S0_RXD0
H10 47 — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI I2S0_MCLK
L10 48 G7 30 VDD VDD VDD
K10 49 H7 31 VSS VSS VSS
L11 50 H8 32 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RX TPM_
CLKIN0
K11 51 G8 33 PTA19 XTAL0 XTAL0 PTA19 UART1_TX TPM_
CLKIN1
LPTMR0_
ALT1
J11 52 F8 34 PTA20 RESET_b PTA20 RESET_b
G11 53 F7 35 PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8/
TSI0_CH0
LCD_P0/
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL TPM1_CH0 LCD_P0
G10 54 F6 36 PTB1 LCD_P1/
ADC0_SE9/
TSI0_CH6
LCD_P1/
ADC0_SE9/
TSI0_CH6
PTB1 I2C0_SDA TPM1_CH1 LCD_P1
G9 55 E7 37 PTB2 LCD_P2/
ADC0_SE12/
TSI0_CH7
LCD_P2/
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL TPM2_CH0 LCD_P2
G8 56 E8 38 PTB3 LCD_P3/
ADC0_SE13/
TSI0_CH8
LCD_P3/
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA TPM2_CH1 LCD_P3
E11 57 — — PTB7 LCD_P7 LCD_P7 PTB7 LCD_P7
D11 58 — — PTB8 LCD_P8 LCD_P8 PTB8 SPI1_PCS0 EXTRG_IN LCD_P8
E10 59 — — PTB9 LCD_P9 LCD_P9 PTB9 SPI1_SCK LCD_P9
D10 60 — — PTB10 LCD_P10 LCD_P10 PTB10 SPI1_PCS0 LCD_P10
C10 61 — — PTB11 LCD_P11 LCD_P11 PTB11 SPI1_SCK LCD_P11
B10 62 E6 39 PTB16 LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16 SPI1_MOSI UART0_RX TPM_
CLKIN0
SPI1_MISO LCD_P12
E9 63 D7 40 PTB17 LCD_P13/
TSI0_CH10
LCD_P13/
TSI0_CH10
PTB17 SPI1_MISO UART0_TX TPM_
CLKIN1
SPI1_MOSI LCD_P13
D9 64 D6 41 PTB18 LCD_P14/
TSI0_CH11
LCD_P14/
TSI0_CH11
PTB18 TPM2_CH0 I2S0_TX_
BCLK
LCD_P14
C9 65 C7 42 PTB19 LCD_P15/
TSI0_CH12
LCD_P15/
TSI0_CH12
PTB19 TPM2_CH1 I2S0_TX_FS LCD_P15
F10 66 — — PTB20 LCD_P16 LCD_P16 PTB20 CMP0_OUT LCD_P16
F9 67 — — PTB21 LCD_P17 LCD_P17 PTB21 LCD_P17
F8 68 — — PTB22 LCD_P18 LCD_P18 PTB22 LCD_P18
E8 69 — — PTB23 LCD_P19 LCD_P19 PTB23 LCD_P19
B9 70 D8 43 PTC0 LCD_P20/
ADC0_SE14/
TSI0_CH13
LCD_P20/
ADC0_SE14/
TSI0_CH13
PTC0 EXTRG_IN audioUSB_
SOF_OUT
CMP0_OUT I2S0_TXD0 LCD_P20
D8 71 C6 44 PTC1/
LLWU_P6/
RTC_CLKIN
LCD_P21/
ADC0_SE15/
TSI0_CH14
LCD_P21/
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL TPM0_CH0 I2S0_TXD0 LCD_P21
Pinout
Kinetis KL36 Sub-Family, Rev5 08/2014. 51
Freescale Semiconductor, Inc.
121
BGA
100
LQFP
64
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
C8 72 B7 45 PTC2 LCD_P22/
ADC0_SE11/
TSI0_CH15
LCD_P22/
ADC0_SE11/
TSI0_CH15
PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS LCD_P22
B8 73 C8 46 PTC3/
LLWU_P7
LCD_P23 LCD_P23 PTC3/
LLWU_P7
UART1_RX TPM0_CH2 CLKOUT I2S0_TX_
BCLK
LCD_P23
F7 74 E3 47 VSS VSS VSS
E7 — E4 — VDD VDD VDD
A11 75 C5 48 VLL3 VLL3 VLL3
A10 76 A6 49 VLL2 VLL2 VLL2/
LCD_P4
PTC20 LCD_P4
A9 77 B5 50 VLL1 VLL1 VLL1/
LCD_P5
PTC21 LCD_P5
B11 78 B4 51 VCAP2 VCAP2 VCAP2/
LCD_P6
PTC22 LCD_P6
C11 79 A5 52 VCAP1 VCAP1 VCAP1/
LCD_P39
PTC23 LCD_P39
A8 80 B8 53 PTC4/
LLWU_P8
LCD_P24 LCD_P24 PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX TPM0_CH3 I2S0_MCLK LCD_P24
D7 81 A8 54 PTC5/
LLWU_P9
LCD_P25 LCD_P25 PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 CMP0_OUT LCD_P25
C7 82 A7 55 PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI EXTRG_IN I2S0_RX_
BCLK
SPI0_MISO I2S0_MCLK LCD_P26
B7 83 B6 56 PTC7 LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7 SPI0_MISO audioUSB_
SOF_OUT
I2S0_RX_FS SPI0_MOSI LCD_P27
A7 84 — — PTC8 LCD_P28/
CMP0_IN2
LCD_P28/
CMP0_IN2
PTC8 I2C0_SCL TPM0_CH4 I2S0_MCLK LCD_P28
D6 85 — — PTC9 LCD_P29/
CMP0_IN3
LCD_P29/
CMP0_IN3
PTC9 I2C0_SDA TPM0_CH5 I2S0_RX_
BCLK
LCD_P29
C6 86 — — PTC10 LCD_P30 LCD_P30 PTC10 I2C1_SCL I2S0_RX_FS LCD_P30
C5 87 — — PTC11 LCD_P31 LCD_P31 PTC11 I2C1_SDA I2S0_RXD0 LCD_P31
B6 88 — — PTC12 LCD_P32 LCD_P32 PTC12 TPM_
CLKIN0
LCD_P32
A6 89 — — PTC13 LCD_P33 LCD_P33 PTC13 TPM_
CLKIN1
LCD_P33
D5 90 — — PTC16 LCD_P36 LCD_P36 PTC16 LCD_P36
C4 91 — — PTC17 LCD_P37 LCD_P37 PTC17 LCD_P37
B4 92 — — PTC18 LCD_P38 LCD_P38 PTC18 LCD_P38
D4 93 C3 57 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_PCS0 TPM0_CH0 LCD_P40
D3 94 A4 58 PTD1 LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1 SPI0_SCK TPM0_CH1 LCD_P41
C3 95 C2 59 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO LCD_P42
B3 96 B3 60 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI LCD_P43
A3 97 A3 61 PTD4/
LLWU_P14
LCD_P44 LCD_P44 PTD4/
LLWU_P14
SPI1_PCS0 UART2_RX TPM0_CH4 LCD_P44
Pinout
52 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
121
BGA
100
LQFP
64
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
A2 98 C1 62 PTD5 LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5 SPI1_SCK UART2_TX TPM0_CH5 LCD_P45
B2 99 B2 63 PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI1_MOSI UART0_RX SPI1_MISO LCD_P46
A1 100 A2 64 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISO UART0_TX SPI1_MOSI LCD_P47
F1 10 — — NC NC NC
F2 11 — — NC NC NC
G1 12 — — NC NC NC
G2 13 — — NC NC NC
J3 — — — NC NC NC
H3 — — — NC NC NC
K4 — — — NC NC NC
L7 — — — NC NC NC
J9 — — — NC NC NC
J4 — — — NC NC NC
H11 — — — NC NC NC
F11 — — — NC NC NC
A5 — — — NC NC NC
B5 — — — NC NC NC
A4 — — — NC NC NC
B1 — — — NC NC NC
C2 — — — NC NC NC
C1 — — — NC NC NC
D2 — — — NC NC NC
D1 — — — NC NC NC
E1 — — — NC NC NC
5.2 KL36 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, ssee KL36 Signal Multiplexing and Pin
Assignments.
Pinout
Kinetis KL36 Sub-Family, Rev5 08/2014. 53
Freescale Semiconductor, Inc.
1
A PTD7
B NC
C NC
D NC
E NC
F NC
G NC
H PTE16
J PTE18
K PTE20
1
L PTE22
2
PTD5
PTD6/
LLWU_P15
NC
NC
PTE2
NC
NC
PTE17
PTE19
PTE21
2
PTE23
3
PTD4/
LLWU_P14
PTD3
PTD2
PTD1
PTE1
PTE6
VSS
NC
NC
PTA6
3
PTE29
4
NC
PTC18
PTC17
PTD0
PTE0
PTE3
PTE5
PTA7
NC
NC
4
PTE31
5
NC
NC
PTC11
PTC16
VDD
VDDA
VREFH
PTE24
PTE25
PTE30
5
VSS
6
PTC13
PTC12
PTC10
PTC9
VDD
VSSA
VREFL
PTE26
PTA0
VDD
6
VSS
7
PTC8
PTC7
PTC6/
LLWU_P10
PTC5/
LLWU_P9
VDD
VSS
VSS
PTE4
PTA2
PTA5
7
NC
8
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTC2
PTC1/
LLWU_P6/
RTC_CLKIN
PTB23
PTB22
PTB3
PTA1
PTA4
PTA12
8
PTA13
9
VLL1
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTA3
NC
PTA14
9
PTA15
10
VLL2
PTB16
PTB11
PTB10
PTB9
PTB20
PTB1
PTA17
PTA16
VSS
10
VDD
11
AVLL3
BVCAP2
CVCAP1
DPTB8
EPTB7
FNC
G
PTB0/
LLWU_P5
HNC
JPTA20
KPTA19
11
LPTA18
Figure 23. KL36 121-pin BGA pinout diagram
Pinout
54 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
60
59
58
57
56
55
54
53
52
51
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PTE22
PTE21
PTE20
PTE19
PTE18
PTE17
PTE16
NC
NC
NC
NC
VSS
VDD
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VLL3
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
PTB11
PTB10
PTB9
PTB8
PTB7
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
25
24
23
22
21
VSSA
VREFL
VREFH
VDDA
PTE23
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
PTD6/LLWU_P15
VCAP1
VCAP2
VLL1
VLL2
50
49
48
47
46
45
44
43
42
41
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13
PTA12
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTE26
PTE25
PTE24
VDD
VSS
PTE31
PTE30
PTE29
98 PTD5
97 PTD4/LLWU_P14
96 PTD3
95 PTD2
94 PTD1
93 PTD0
92 PTC18
91 PTC17
90 PTC16
89 PTC13
88 PTC12
80 PTC4/LLWU_P8
PTC5/LLWU_P9
PTC6/LLWU_P10
81
82
83 PTC7
84 PTC8
85 PTC9
86 PTC10
87 PTC11
100 PTD7
Figure 24. KL36 100-pin LQFP pinout diagram
Pinout
Kinetis KL36 Sub-Family, Rev5 08/2014. 55
Freescale Semiconductor, Inc.
1
A PTE0
B PTE1
C PTD5
D PTE17
E PTE16
F PTE21
G PTE20
1
H PTE29
2
PTD7
PTD6/
LLWU_P15
PTD2
PTE19
PTE18
PTE23
PTE22
2
PTE30
3
PTD4/
LLWU_P14
PTD3
PTD0
PTA0
VSS
VSSA
VREFL
3
PTE31
4
PTD1
VCAP2
VSS
PTA1
VDD
VDDA
VREFH
4
PTE24
5
VCAP1
VLL1
VLL3
PTA3
PTA2
PTA5
PTA4
5
PTE25
6
VLL2
PTC7
PTC1/
LLWU_P6/
RTC_CLKIN
PTB18
PTB16
PTB1
PTA13
6
PTA12
7
PTC6/
LLWU_P10
PTC2
PTB19
PTB17
PTB2
PTB0/
LLWU_P5
VDD
7
VSS
8
A
PTC5/
LLWU_P9
B
PTC4/
LLWU_P8
C
PTC3/
LLWU_P7
D
PTC0
EPTB3
FPTA20
GPTA19
8
HPTA18
Figure 25. KL36 64-pin BGA pinout diagram
Pinout
56 Kinetis KL36 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
PTE24
PTE31
PTE30
PTE29
VSSA
VREFL
VREFH
VDDA
PTE23
PTE22
PTE21
PTE20
PTE19
PTE18
PTE17
PTE16
VSS
VDD
PTE1
PTE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP1
VCAP2
VLL1
VLL2
VLL3
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA18
VSS
VDD
PTA13
PTA12
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTE25
Figure 26. KL36 64-pin LQFP pinout diagram
6Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search
for the following device numbers: PKL36 and MKL36
Ordering parts
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7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 41. Part number fields descriptions
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
KL## Kinetis family • KL36
A Key attribute • Z = Cortex-M0+
FFF Program flash memory size • 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
R Silicon revision • (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
PP Package identifier • LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
CC Maximum CPU frequency (MHz) • 4 = 48 MHz
N Packaging type • R = Tape and reel
Part identification
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7.4 Example
This is an example part number:
MKL36Z256VMC4
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
Terminology and guidelines
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8.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
8.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
60 Kinetis KL36 Sub-Family, Rev5 08/2014.
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8.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
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8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Terminology and guidelines
62 Kinetis KL36 Sub-Family, Rev5 08/2014.
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Table 42. Typical value conditions
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
9 Revision history
The following table provides a revision history for this document.
Table 43. Revision history
Rev. No. Date Substantial Changes
3 3/2014 • Updated the front page and restructured the chapters
• Updated Voltage and current operating behaviors
• Updated EMC radiated emissions operating behaviors
• Updated Power mode transition operating behaviors
• Updated Capacitance attributes
• Updated footnote in the Device clock specifications
• Added thermal attributes of 64-pin MAPBGA in the Thermal
attributes
• Added VREFH and VREFL in the 16-bit ADC electrical
characteristics
• Updated footnote to the VDACR in the 12-bit DAC operating
requirements
• Added Inter-Integrated Circuit Interface (I2C) timing
45/2014 • Updated Power consumption operating behaviors
• Updated Definition: Operating behavior
5 08/2014 • Updated related source in the front page
• Updated Power consumption operating behaviors
Revision history
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How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Document Number KL36P121M48SF4
Revision 5 08/2014
© 2012-2014 Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm.
Off. All other product or service names are the property of their
respective owners. ARM and Cortex are registered trademarks of ARM
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