CD4015BCNX - Fairchild Semiconductor

October 1987

Revised March 2002

CD4015BC Dual 4-Bit Static Shift Register

CD4015BC

Dual 4-Bit Static Shift Register

General Description

The CD4015BC contains two identical, 4-stage, serial-

input/parallel-output registers with independent “Data”,

“Clock,” and “Reset” inputs. The logic level present at the

input of each stage is transferred to the output of that stage

at each positive-go ing clock transition. A logic high on the

“Reset” input resets all four stages covered by that input.

All inputs are protected from static discharge by a series

resistor and diode clamps to VDD and VSS.

Features

■Wide supply voltage rang e: 3.0V to 18V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL: Fan out of 2 driving 74L

compatibility: or 1 driving 74LS

■Medium speed operation: 8 MHz (typ.) clock rate

■Fully static design: @VDD − VSS = 10V

Applications

• Serial -inp ut/p ar all el-o utp ut data queueing

• Serial to parallel data conversion

• General purpose register

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the ordering code.

Connection Diagram Truth Table

X = Don't Care Case

Note 1: Lev el C hange

Order Number Package Number Package Description

CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

(Note 1) DRQ

1Qn



000Q

n−1



101Q

n−1



X0Q

1Qn(No change)

XX100

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CD4015BC

Logic Diagrams

Terminal No. 16 = VDD

Terminal No. 8 = GND

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CD4015BC

Absolute Maximum Ratings(Note 2)

(Note 3) Recommended Operating

Conditions

Note 2: “Absolute Maximum Ratings” are those va lues beyond which the

safety of th e device ca nnot be guaranteed; th ey are not meant to imply th at

the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Charac t eristics” pro v ide con-

ditions f or actual device o peration.

Note 3: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 3)

Note 4: IOH and IOL are tes t ed one ou tp ut at a ti m e.

DC Supply Voltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5 to VDD +0.5 VDC

Stora ge Temper atu re Rang e (TS)−65°C to +150°C

Power Di ssipa ti on (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260 °C

DC Supply Voltage (VDD)+3 to +15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 5 0.005 5 150 µACurrent VDD = 10V, VIN = VDD or VSS 10 0.010 10 300

VDD = 15V, VIN = VDD or VSS 20 0.015 20 600

VOL LOW Level VDD = 5V 0.05 0 0.05 0.05 VOutput Voltage VDD = 10V |IO| < 1 µA 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95 VOutput Voltage VDD = 10V |IO| < 1 µA 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0

VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIG H Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4015BC

AC Electrical Characteristics (Note 5)

TA= 25°C, CL= 50 pF, RL= 200k, tr = tf = 20 ns, unless otherwise specified

Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.

Symbol Parameter Conditions Min Typ Max Units

CLOCK OPERATION

tPHL, tPLH Propagation Delay Time VDD = 5V 230 350 nsVDD = 10V 80 160

VDD = 15V 60 120

tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10 V 50 100

VDD = 15V 40 80

tWL, tWM Minimum Clock VDD = 5V 160 250 nsPulse-Width VDD = 10V 60 110

VDD = 15V 50 85

trCL, tfCL Clock Rise and VDD = 5V 15 µsFall Time VDD = 10V 15

VDD = 15V 15

tSU Minimum Data VDD = 5V 50 100 µsSet-Up Time VDD = 10V 20 40

VDD = 15V 15 30

fCL Maximum Clock VDD = 5V 2 3.5 MHzFrequency VDD = 10V 4.5 8

VDD = 15V 6 11

CIN Input Capacitance Clock Input 7.5 10 pF

Other Inputs 5 7.5

RESET OPERATION

tPHL(R) Propagation Delay Time VDD = 5V 200 400 nsVDD = 10V 100 200

VDD = 15V 80 160

tWH(R) Minimum Reset VDD = 5V 135 250 nsPulse Width VDD = 10V 40 80

VDD = 15V 30 60

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CD4015BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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CD4015BC Dual 4-Bit Static Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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