Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent o
r
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information contained herein supersedes
previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995 January 1999 Order Number: 243667-003
INTEL PENTIUM II PRO C ESSOR
MOBI LE MOD U LE : MOBI LE MODULE
CONNECTOR 1 (MMC-1)
n
Intel Mobile Pentium II Processo r with core
frequency running at speeds of 300 MHz, 266 MHz,
and 233 MHz
n
Processor core voltage regulation supports input
voltages from 5V to 21V
Above 80 percent peak efficiency
n
Integrated Active Thermal Feedback (ATF) system
ACPI Rev. 1.0 compliant
Internal A/D – digital signaling (SMBus) across
the module interface
Programmable trip point interrupt or poll mode
for temperature reading
n
Thermal transfer plate for heat dissipation
n
Intel 443BX Host Bridge system controller
DRAM controller supports EDO and SDRAM at
3.3V
Support s PCI CLKRUN# protocol
SDRAM clock enable support and self refresh
of EDO or SDRAM during Suspend mode
3.3V PCI bus control, Rev 2.1 compliant
The Intel Pentium II processor mobile module connector 1 (MMC-1) is a highly integrated assembly containing an Intel Pentium II
m obile proce ssor and its im mediate system -le vel suppo rt. The module in terfaces electrically to its hos t syst em via a 3.3-V PCI bus ,
a 3.3-V memory bus and Intel 443BX Host Bridge control signals.
2
Intel Pentium II Processor Mobile Module MMC-1
Informati on in this document is provided in con nection w ith Intel products . No license, ex press or implied, by estoppe l or ot herwis e, to any int ellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoev er, and Intel d isc laims any expr es s or implied warr anty , rel atin g to sa le and /or us e of In tel pro duc ts includ ing li abil ity or warrant ies relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical , life-s aving, or life-sus taining applicat ions. Intel may m ake c hanges to spec if ications and pr oduct descr iptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Pentium II processor mobile modules may contain design defects or errors known as errata. Current characterized errata are available on
request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of d oc uments whic h have an or dering num ber and are r eferenc ed in th is doc ument, or other In tel liter ature, m ay be obta ine d by c alling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com
Copyright © Intel Corporation1998.
*Third-party brands and names are the property of their respective owners.
3
Intel Pentium II Processor Mobile Module MMC-1
CONTENTS
1.0 INTRODUCTION ..................................................5
1.1 Revision History....................................................5
2.0. ARCHITECTURE OVERVIEW ............................5
3.0 MODULE CONNECTOR INTERFACE................7
3.1 Signal Definition....................................................7
3.1.1. Signal List..............................................................8
3.1.2. Memory (108 Signals) ..........................................9
3.1.3. PCI (56 Signals)..................................................10
3.1.4 Processor and PIIX4E Sideband (9 Signals).....11
3.1.5 Power Ma na ge me nt (8 Si gn als ).........................12
3.1.6 Clock (8 Signals).................................................13
3.1.7 Voltages (39 Signals) .........................................14
3.1.8 JTAG (7 Signals) ................................................14
3.1.9 Miscellaneous (45 Signals) ................................15
3.2. Connector Pin Assignments...............................16
3.3 Pin an d Pa d Assig n me nts..................................18
4.0. FUNCTIONAL DESCRIPTION ..........................19
4.1. Pentium II Proces s or M ob ile Modul e...............19
4.2. L2 Cache.............................................................19
4.3. The 443BX Host Bridge System Controller .......19
4.3.1. Memory Organization.........................................19
4.3.2. Reset Stra p O pti ons ...........................................20
4.3.3. PCI Interface.......................................................20
4.3.4 AGP Feature Set ................................................20
4.4. Power Management............................................21
4.4.1 Clock Control Architecture..................................21
4.4.2. Normal State.......................................................23
4.4.3. Auto Halt State....................................................23
4.4.4. Stop Grant State.................................................23
4.4.5. Quick Start State.................................................23
4.4.6. HALT/Grant Snoop State ...................................23
4.4.7. Sleep State..........................................................23
4.4.8. Deep Sleep State................................................24
4.5. Typical POS/STR Power....................................24
4.6. Elec tr ic al Re quire me nt .......................................25
4.6.1. DC Requirements ...............................................25
4.6.2 AC Requirements................................................26
4.6.2.1. System Bus Clock (BCLK) Signal
Quality Specifications and
Measurement Guidelines.....................27
4.7. Voltage Regulator ...............................................27
4.7.1. Voltage Regulator Efficiency ..............................27
4.7.2. Control of the Voltage Regulator........................28
4.7.2.1. Voltage Signal Definition and
Sequencing............................................29
4.7.3. Power Planes: Bulk Capacitance Requirements30
4.7.4. Surge Current Guidelines ...................................31
4.7.4.1. Slew-Rate Control: Circuit
Description............................................33
4.7.4.2. Under-Voltage Lockout: Circuit
Description (V_uv_lockout)...................34
4.7.4.3. Over-Voltage Lockout: Circuit
Description (V_ov_lockout)...................35
4.7.4.4. Over-Current Protection: Circuit
Description ..........................................................35
4.8. Active Thermal Feedback...................................35
4.9 Thermal Sensor Configuration Register.............36
5.0. MECHANICAL SPECIFICATION ......................37
5.1. Module Dimensions ............................................37
5.1.1. Board Area..........................................................37
5.1.2. MMC-1 Pin 1 Location ........................................38
5.1.3. Printed Circuit Board Thickness.........................38
5.1.4. Height Restrictions..............................................39
5.2. The rm al Tra ns fe r Plat e.......................................40
5.3. Module Physical Support....................................41
5.3.1 Module Mounting Requirements ........................41
5.3.2. Module Weight ....................................................41
6.0. THERMAL SPECIFICATION.............................42
6.1. The rm al Des i gn Power.......................................42
6.2 Therm al Se ns or Set po in t....................................42
7.0. LABELING INFORMATION...............................43
8.0. ENVIRONMENTAL STANDARDS ....................45
4
INTEL PENTIUM II PROCESSOR MOBILE MODULE MMC- 1
FIGURES
Figure 1. Block Diagram of the Pentium II Proce ssor
Mobile Module .........................................................6
Figure 2. 280-Pin Connector Footprint Pad Numbers,
Module Secondary Side.........................................18
Figure 3. Pentium II Processor Mobile Module Clock
Control States .......................................................22
Figure 4. BCLK, TCK, PICCLK Generic Clock Waveform
at the Processor Core Pin .....................................27
Figure 5. Power-On Sequence Timing.................................30
Figure 6. Instantaneous In-Rush Current Model..................31
Figure 7. Instantaneous In-Rush Current.............................32
Figure 8. Over-Current Protection Circuit.............................33
Figure 9. Sp ice Simulation Using In-Rush Prote ction
(Example Only).....................................................34
Figure 10. Pentium II Processor MMC-1 Board Dimensions
with 280-Pin Connector Orientation....................37
Figure 11. Pentium II 280-Pin Connector - Pin 1
Orientation............................................................38
Figure 12. Printed Circuit Board Thickness..........................39
Figure 13. Pentium II Processor Mobile Module 3-D
Keep-out Zone.....................................................39
Figure 14. Pentium II Processor Mobile Module
Thermal Transfer Plate........................................40
Figure 15. Pentium II Processor Mobile Module
Thermal Transfer Plate........................................41
Figure 16. Standoff Holes, Board Edge Clearance,
and EMI Containment Ring .................................42
Figure 17. Pentium II Processor Mobile Module
Product Tracking Code........................................44
TABLES
Table 1. Module Connector Signal Summary.........................7
Table 2. Memory Signal Descriptions.....................................9
Table 3. PCI Signal Descriptions ..........................................10
Table 4 . Processor/PIIX4E Sideband Sign al
Descriptions.............................................................11
Table 5. Power Management Signal Descriptions ...............12
Table 6. Clock Signal Descriptions .......................................13
Table 7. Voltage Descriptions...............................................14
Table 8. JTAG Pins................................................................14
Table 9. Miscellaneous Pins..................................................15
Table 10. Connector Pin Assignments .................................16
Table 11. Connector Specifications......................................19
Table 12. Configuration Straps for the 443BX Host Bridge
System Controller...................................................20
Table 13. Mobile Pentium II Processor Clock State
Characteristics........................................................24
Table 14. Mobile Pentium II Processor POS/STR Power..24
Table 15 . Pentium II Processor Mobile Module Power
Specifications 1......................................................25
Table 16 . Pentium II Processor Mobile Module AC
Specifications (BCLK)............................................26
Table 17. BCLK Signal Quality Specifications at the
Processor Core ......................................................27
Table 18. Typical Voltage Regulator Efficiency....................28
Table 19. Voltage Signal Definitions and Sequences ..........29
Table 20. Capacitance Requirements per Power Plane......30
Table 21. Thermal Sensor SMBus Address Table...............35
Table 22. Thermal Sensor Configuration Register...............36
Table 23 . Pentium II Processor Mobile Module (MMC-1)
Maximum Power Specifications.............................43
Table 24. Environmental Standards......................................45
5
INTEL PENTIUM II PROCESSOR MOBILE MODULE MMC- 1
1.0 INTRODUCTION
This document provides the technical information for
int egr ating the P e nti u m II Processor Mobile Module
Connector 1 (MMC-1) into the latest notebook systems for
today’s notebook market.
Buil ding a round this modular design gives th e system
manufacturer these advantages:
•Avoids complexities associated with designing high-
speed processor core logic boards.
• Provides an upgrade path from previous Pentium II
proc es s or mob ile mo dules us in g a standar d in terfac e.
1.1 Revision History
This is the first version of this document.
2.0. ARCHI TECTURE OVERVIEW
The Pentium II processor mobile module is a highly
integrated assembly containing the mobile Pentium II
pro cessor cor e, the Intel 443BX Host Bridg e system
controller, and system level sup por t. The Pentium II
pro cessor mobile m odule has a 66 -MHz system bus speed
and runs at speeds of 300 MHz, 266 MHz, and 233 MHz.
The Pe nt iu m I I proc es s or mobile mo dule inclu des a sec o nd-
leve l cac h e of pip el in e bur s t SR A M su pp ortin g up to 51 2 K B.
The ZZ “snooze” mode featured in previous mobile modules
is no longer supported. Instead, the Pentium II processor
mobile module supports the “Stop Clock” mode for the L2
SRAMs. The clock signals to the L2 SRAMs are stopped or
“parked” in a low power state by the processor.
The PIIX4E PCI/ISA Bridge is one of two large-scale
integrated devices of the Intel 440BX PCIset. A notebook’s
system electronics must in clude a PIIX4 E device to connect
to the Pentium II processor mobile module. The PIIX4E
prov i des ex te ns iv e power m an ag em e nt ca pab il iti es and
supports the second integrated device, the 443BX Host
Br idge. Key features of the Intel 443BX Ho st Bridge system
controller include the DRAM controller that supports EDO at
3.3V with a burst read at 7-2-2-2 (60 ns) or SDRAM at 3.3V
with a burst read at 8-1-1-1 (66 MHz, CL=2). The 443BX
Host Bridge also provides a PCI CLKRUN# signal to
request the PIIX4E to regulate the PCI clock on the PCI bus.
The 82443Bx cl ock enab les Self-Re fresh mode of EDO or
SD RAM during Suspend mode and is compa tible with
SMRAM (C _S MRAM) and Extend ed SMRAM (E_SMR A M)
modes of power m an ag e me nt. E_SMRA M m od e su pp orts
write-bac k cac he able S MR A M up to 1 MB .
A thermal transfer plate (TTP) on the 443BX Host Bridge and
the mobile Pentium II processor provides heat dissipation
and a standard thermal attach point for the notebook
manufacturer’s thermal solution.
An on -board vo ltage regu lator convert s the system DC
voltage to the processor’s core and I/O voltage. Isolating the
pro cessor voltage requirements allows the system
manufacturer to incorporate different processor variants into
a single note book system.
Supporting input voltages from 5V to 21V, the processor core
voltag e r eg ul at or en ab les an ab ov e 80 perc ent pe ak
efficiency and decouples processor voltage requirements
from the system.
The Pentium II processor mobile module also incorporates
Active Thermal Feedback (ATF) sensing, compliant to the
ACPI Rev 1.0 specification. A system man agement bus
(SMBus) supports the internal and external temperature
sensing with programmable trip points.
6
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Figure 1 illustrates the block diagram of the Pentium II processor mobile module.
280 Pin Board-t o-B oard Connector
CPU
Volt. Reg.
5V-21V
Processor Core Voltage
PC I Bu s
Memory Bus
PCLK1
HCLK1
443BX
"Northbridge"
V_3
HCLK0
PIIX4E Sidebands
ATF
Sense
SMBUS
FSB
Mobile
Pentium®
II
Processor
Core
PB SRAM
V_3S TAG
V_3S PB SRAM
V_3S
2.5V
Backside Bus I/O Voltage
R_GTL
DCLKWR
DCLKRD
BSB
Figure 1. Block Diagram of the Pentium II Processor Mobile Module
7
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.0 MODULE CONNECTOR INTERFACE
3.1 Sign al Definit io n
This section provides information on signal groups for the
Pentium II processor MMC-1. The signals are variably
defined for compatibility with future Intel mobile modules.
Table 1 provides a list of signals by category and the
corresponding number of signals in each category. For
proper signal termination, please contact your Intel sales
representative.
Tabl e 1. Module C onn e ctor S ign al Su mm ar y
Signal Group Number
Memory 108
PCI 56
Processor/ PIIX 4E Sid eba nd 9
Power Management 8
Clocks 8
Voltage: V_DC 10
Voltage: V_3S 20
Voltage: V_5 1
Voltage: V_3 5
Voltage: V_CPUIO 3
JTAG 7
Misc el laneous & Mo du le ID 5
Ground 32
Reserved 8
Total 280
8
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.1. Sign al Lis t
The following notations are used to denote the signal type:
I Inp ut pi n
O Outp ut pi n
O D Open Drain Output pin. This pin requires a pull up resistor.
I D Open Drain Input pin. This pin requires a pull up resistor.
I/O D Input / Open Drain Output pin. This pin requires a pull up resistor.
I/O Bi-directional Input / Output pin
The signal description also includes the type of buffer used for a particular signal:
GTL+ Open Drain GTL+ interface signal.
PCI PCI bus interface signals.
CMOS The CMOS buffers are Low Voltage TTL compatible signals. They are also 3.3V outputs with 5.0V tolerant
inputs.
9
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.2. Memory (108 Signals)
Table 2 lists the memory interface signals.
Table 2. Memory Signal Descriptions
Name Type Voltage Description
MECC[7:0] I/O
CMOS V_3 Memory ECC Data: These signals carry Memory ECC data during
access to DRAM. These pins are not implemented on the MMC-1
and are reserved for future use.
RASA[5:0]# or
CSA[5:0]# O
CMOS V_3 Row Address Strobe (EDO): These pins select the DRAM row.
Chip Sel ect (SDRA M): Thes e pi ns act iv at e t he SDR AMs . SDRAM
accepts any command when its CS# pin is active low.
CASA[7:0]# or
DQMA[7:0] O
CMOS V_3 Column Address Strobe (EDO): These pins select the DRAM
column.
Input/Output Data Mask (SDRAM): T hese pins ac t as
synchronized output enables during a read cycle and as a byte
m ask during a write cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS V_3 Memory Address (EDO/SDRAM): This is the row and column
address for DRAM. The 443BX Host B ridge system controller has
two identical sets of address lines (MAA and MAB#). The Pentium
II processor mobile module supports only the MAB set of address
lines. For additional addressing features, please refer to the
Intel
440BX PCIset Datasheet
.
MWE[A, B] # O
CMOS V_3 Memory Write Enable (EDO/SDRAM): MWEA# should be used as
the write enable for the memory data bus.
SRAS[A, B]# O
CMOS V_3 SDRAM Row Address Strobe (SDRAM): When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge.
SCAS[A, B]# O
CMOS V_3 SDRAM Column Address Strobe ( SDRAM ): When active low, this
signal latches Column Address on the positive edge of the clock.
This signal also allows Column access.
CKE[A, B] O
CMOS V_3 SDRAM Clock Enable (SDRA M): When these signals are
deasserted, SDRAM enters power-down mode. CKEB is NC and
not used by the system electronics.
MD[63:0] I/O
CMOS
V_3 Memory Data: These signals are connected to the DRAM data bus.
They are not terminated on the Pentium II processor mobile
module.
NOTES:
1. DQMA signals are non-inverted. Please refer to 82443BX Spec Update
2. MAB[13] is a non-inverted address signal. Please refer to 82443BX Spec Update.
10
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.3. PCI (56 Signals)
Table 3 lists the PCI interface signals.
Tab le 3. PC I Sign al D e script io ns
Name Type Voltage Description
AD[31:0] I/O
PCI V_3 Address/Data: The standard PCI address and data lines. The
address is driven with FRAME# assertion, and data is driven or
received in following clocks.
C/BE[3:0]# I/O
PCI V_3 Command/Byte Enable: The comm and is dr iven with FRAME#
assertion and byte enables corresponding to supplied or
requested data are driven on th e follow ing clocks.
FRAME# I/O
PCI V_3 Frame: Assertion indicates the address phase of a PCI transfer.
Neg ati on indicates th at on e mo re da ta tr a ns fers are d es ir ed by the
cycle initiator.
DEVSEL# I/O
PCI V_3 Device Select: The 443BX Host Bridge drives this signal when a
PCI initiator is attempting to access DRAM. DEVSEL# is asserted
at medium decode time.
IRDY# I/O
PCI V_3 Initiator Re ady : Asserted when the initiator is ready for data
transfer.
TRDY# I/O
PCI V_3 Target Ready: A s s erte d w he n th e tar g et is ready for a dat a
transfer.
STOP# I/O
PCI V_3 Stop: Asserted by the target to request the master to stop the
current transaction.
PLOCK# I/O
PCI V_3 Lock: I nd ic ates an ex c lus iv e bus operation and may re qu ire
multiple transactions to complete. When LOCK# is asserted, non-
exclusive transactions may proceed. The 443BX supports lock for
CPU initiated cycles only. PCI initiated locked cycles are not
supported.
REQ[4:0]# I
PCI V_3 PCI Request: PCI master requests for PCI.
GNT[4:0]# O
PCI V_3 PCI Grant: Permission is given to the master to use PCI.
PHOLD# I
PCI V_3 PCI Hold: This signal comes from the expansion bridge; it is the
bridge request for PCI. Th e 44 3BX Hos t B ri dge wi ll dr ain the
DRAM write buffers, drain the processor-to-PCI posting buffers,
and acquire the host bus before granting the request via PHLDA#.
This ensures that GAT timing is met for ISA masters. The
PHOLD# protocol has been modified to include support for
passive release.
PHLDA# O
PCI V_3 PCI Hold Acknowledge: The 443BX Host Bridge drives this
signal to grant PCI to the expansion bridge. The PHLDA# protocol
has been modified to include support for passive release.
PAR I/O
PCI V_3 Parity: A single parity bit is provided over AD[31:0] and
C/BE[3:0]#.
SERR# I/O
PCI V_3 System Error: The 443BX asserts this signal to indicate an error
condition. Plea se refer to th e
Intel
440BX PCIset Datasheet
(Order Number 290633-001) for further information.
CLKRUN# I/O D
PCI V_3 Clock Run: An open-drain output and input. The 443BX Host
Bridge requests the central resource (PIIX4E) to start or maintain
the PCI clock by asserting CLKRUN#. The 443BX Host Bridge tri-
states CLKRUN# upon deassertion of Reset (since CLK is running
upon deassertion of Reset).
11
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Name Type Voltage Description
PCI_RST# I
CMOS V_3 Reset: When asserted, this signal asynchronously resets the
443BX Host Bridge. The PCI signals also tri-state, compliant with
PCI Rev 2.1 specifications.
3.1.4 Processor and PIIX4E Sideband (9
Signals)
Table 4 lists the processor and PIIX4E sideband interface
signals. These voltage levels are determined by V_CPUIO.
Table 4. Processor/PIIX4E Sideband Signal Descriptions
Name Type Voltage Description
FERR# O
CMOS V_CPUIO Numeric Coprocessor Error: This pin functions as a FERR#
signal supporting coprocessor errors. This signal is tied to the
coprocessor error signal on the processor and is driven by the
processor to the PIIX4E.
CPURST N/C
CMOS V_CPUIO Processor Reset: The signal is not used in the Pentium II
Processor MMC-1.
IGNNE# ID
CMOS V_CPUIO Ignore Error: This open drain signal is connected to the ignore
error pin on the processor and is driven by the PIIX4E.
INIT# ID
CMOS V_CPUIO Initialization: INIT# is asserted by the PIIX4E to the processor for
system initialization. This signal is an open drain.
INTR ID
CMOS V_CPUIO Proces sor Int er rupt: INTR is driven by the PIIX4E to signal the
processor that an interrupt request is pending and needs to be
serviced. This signal is an open drain.
NMI ID
CMOS V_CPUIO Non-Maskable Interrupt: NM I is us ed to forc e a no n- m as k ab le
interrupt to the processor. The PIIX4E ISA bridge generates an
NMI when either SERR# or IOCHK# is asserted, depending on
how th e N MI Sta tus an d C ontr ol Re gis t er is pr o gr am m ed. This
signal is an open drain.
A20M# ID
CMOS V_CPUIO Address Bit 20 Mask: Whe n enabled, this open drain signal
causes the processor to emulate the address wraparound at one
MB which occurs on the Intel 8086 processor.
SMI# ID
CMOS V_CPUIO Syst e m Man agement Inter rupt : SMI # is an act iv e low
synchronous output from the PIIX4E that is asserted in response
to one of many enabled hardware or software events. The SMI#
open drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK# ID
CMOS V_CPUIO Stop Clock: STPCLK# is an active low synchronous open drain
output from the PIIX4E that is asserted in response to one of
many hardware or software events. STPCLK# connects directly to
the processor and is synchronous to PCICLK. When the
processor samples STPCLK# asserted it responds by entering a
low power state (Quick Start). The processor will only exit this
mode when this signal is deasserted.
12
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.5 Power Management (8 Signals)
Table 5 lists the power management interface signals. The
SM_CLK and SM_DATA signals refer to the two-wire serial
SMB us inte rfac e. A ltho ugh this inter f ac e is curre ntly use d
solely for the digital thermal sensor, the SMBus contains
reserved serial addresses for future use. See section 4.9 for
mor e de tails .
Table 5. Power Management Signal Descriptions
Name Type Voltage Description
OEM_PU I
CMOS V_3 OEM Pullup: This pullup resistor is not required on the Intel
Pentium II processor mobile module. This signal is used by
prev i ous Int el m obile mo dule ge ner at io ns .
L2_ZZ N/C
CMOS V_CPUIO Low-Power Mode For Cache SRAM: This signal is not used on
the Intel Pentium II processor mobile module. It is a signal
used by pr ev i ous Int el m obile mo dule ge ner at io ns .
SUS_STAT# I
CMOS V_3AL WAYS 1Suspend Status: This signal connects to the SUS_STAT1#
output of PIIX4E. It provides information on host clock status and
is asserted during all suspend states.
VR_ON I V_3S VR_ON: Voltage regulator ON. T his 3.3 V (5 V tol er a nt) si g nal
controls the operation of the voltage regulator. VR_ON should be
generated as a function of the PIIX4E SUSB# signal which is
used for controlling the “Suspend State B” voltage planes. This
signal should be driven by a digital signal with a rise/fall time of
less than or equal to 1 us. (VIL (max)=0.4V, VIH (min)=3.0V).
See Figure 5 for proper sequencing of VR_ON.
VR_PWRGD O V_3S VR_PWRG D : This signal is driven high to indicate that the
voltage regulator is stable and is pulled low using a 100K resistor
when inactive. It can be used in some combination to generate
the syste m PWRGOOD signal.
SM_CLK I/O D
CMOS V_3 Serial Clock: This clock signal is used on the SMBus interface
to the digital thermal sensor. Ensure proper termination based
upon the
System Management Bus Specification, Revision 1.0
.
SM_DATA I/O D
CMOS V_3 Serial Data: Open-drain dat a signal on the SMBus inte rface to
the digital thermal sensor. Ensure proper termination based upon
the
System Management Bus Specification, Revision 1.0
.
ATF_INT# O D
CMOS V_3 ATF Interrupt: This signal is an open-drain output signal of the
digital thermal sensor.
NOTE:
V_3ALWAYS: 3.3V supply. It is generated whenever V_DC is available and supplied to PIIX4E resume well.
13
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.6 Clock (8 Signals)
Table 6 lists the clock interface signals.
Tab le 6. Clock S ig nal De scr ipt i on s
Name Type Voltage Description
OEM_PD I
CMOS V_3 OEM Pull-Down: It is renamed from PCI_REF and this pulldown
resistor is not required on the Intel Pentium II proc essor mobile
module. It is a signal used by previous Intel mobile module
generations.
PCLK I
PCI V_3S PCI Clock In: PCLK is an input to the module from the CKDM66-M
clock sou rce and is one of the system’ s PCI cl ocks. This clock is
used by all of the 443BX Host Bridge logic in the PCI clock domain.
This clock is stopped when the PIIX4E PCI_STP# signal is asserted
and/or during all suspend states.
HCLK[1:0] I
CMOS V_CPUIO Host Clock In: These clo cks are inputs to the module f rom the
CKDM66-M clock source and are used by the processor and the
443BX Host Bridge system control ler. This clock is st opped when
the PIIX4E CPU_STP# signal is asserted and/or during all suspend
states.
SUSCLK N/C
CMOS V_3 Suspend Clock: This signal is not used on the Intel Pentium
proc es s or mob ile modu le.
FQS[1:0] O
CMOS V_3S Frequency Status: This signal provides status of the host clock
frequency to the syst em ele c tronics. These signals are static and
are pulled either low or high to the V_3S voltage.
FQS1 FQS0 Frequency
0 0 60 MHz
0 1 66 MHz
1 0 Reserved
1 1 Reserved
CPU3.3_2.5# O
CMOS V_CPUIO Clock Voltage Select: Provides status to the system electronics
about the voltage level at which the CKDM66-M clock generator
should be operating. This signal is pulled low by the Intel Pentium
II processor mobile module.
14
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.1.7 Voltages (39 Signals)
Table 7 lis ts the voltage signal definitions.
Table 7. Voltage Descriptions
Name Type Number Description
V_DC I 10 DC Input: 5V - 21V
V_3S I 20 SUSB# controlled 3.3V: Power-managed 3.3V supply. An out put of the
voltag e regulator on th e system electronics. This rail is off during STR,
STD, and Soff.
V_5 I 1 SUSC# controlled 5V: Pow er-managed 5V supply. An output of the
voltag e regulator on th e system electronics. This rail is off during STD
and Soff.
V_3 I 5 SUSC# controlled 3.3V: Power-managed 3.3V supply. A n out p ut of the
voltag e regulator on th e system electronics. This rail is off during STD
and Soff.
V_CPUIO O 3 Processor I/O Ring: Powers processor interface signals such as the
PIIX4E open-drain pullups for the processor/PIIX4E sideband signals
and the CKDM66-M clock source.
3.1.8 J TAG (7 Signals)
Table 8 lists the ITP/ JTAG signals, whi c h the system
electronics can use to implement a JTAG chain and ITP port,
if desired. The JTAG signals prov ided can no t be used as an
ITP port, since the definition of the ITP interface has
changed between the Pentium processor and mobile
Pentium II processor generations.
Tab le 8. JTAG Pins
Name Type Voltage Description
TDO O V_CPUIO JTAG Test Data Out: Serial output port. TAP instructions and
data are shifted out of the processor from this port.
TDI I V_CPUIO JTAG Test Data In: Serial input port. TAP instructions and data
are shifted into the processor from this port.
TMS I V_CPUIO JTAG Te st Mod e S el ect: Controls the TAP controller change
sequence.
TCLK I V_CPUIO JTAG Test Clock: Testability clock for clocking the JTAG
boundary scan sequence.
TRST# I V_CPUIO JTAG Test Reset: Asynchronously resets the TAP controll er in
the processor.
ITP(1:0)
ITP1
ITP0
O
IV_CPUIO Debug Port Signals: Curr ently def ined for the gener ation of
Pentium processors. These signals are not used in the Pentium
II processor mobile module, and should not be connected.
NOTE:
DBREST# (reset target system) on the ITP debug port can be “logically ANDed” with VR_PWRGD TO PIIX4E’s PWROK.
15
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3 .1.9 Miscellaneous (45 Signals)
Table 9 lists the miscellaneous signals.
Tab le 9. Mi sc ellaneou s Pins
Name Type Number Description
Module
ID[3:0] O
CMOS
4Module Revision ID: These pins track the revision level of the
Intel Pentium II proc es s or mod ul e. A 10 0K pul l up res is tor to
V_3S is requ ired on these signals and t o be placed on the system
electronics for these signals.
PPP_PP# O
CMOS 1Pentium II processor or Pentium processor present: A hi gh
on this signal indicates to the PIIX4E ISA bridge CONFIG1 pin
that the processor module used is based on the Pentium Pro
architecture; a low indicates that it is of the Pentium processor
family. This signal is allowed to float on Pentium II processor
mobile m odul es and r e qu ir es a 10 0K pul l up r es is t or to V_3 S on
the system electronics. Th is signal is grounded.
Ground I 32 Ground.
Reserved RSVD 8 Unallocated Reserved pins and should not be connected.
16
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.2. Co nn ect or Pin Assign ments
Table 10 lists the signals for each pin of the connector from
the Pentium II processor mobile module to the notebook manufacturer’s syst em electronics. Refer to Sect ion 3.3 for
the pin assignments of the pads on the connector.
Table 10. Connector Pin Assignments
Pin# Row Row Row Row
AA AB BA BB
1 Gnd Gnd Gnd Gnd
2 MD31 MD63 MID0 MID1
3 MD30 MD61
Reserved
Reserved
4 MD29 MD62 V DC V DC
5 MD27 MD58 V DC V DC
6 V3S V3S VDC VDC
7 MD28 MD60 V DC V DC
8 MD26 MD56 V DC V DC
9 MD25 MD57
Reserved
Reserved
10 MD24 MD59 MID2 MID3
11 Gnd Gnd Gnd Gnd
12 CAS3#/D
Q
M3 CAS7#/D
Q
M7 AD00 FRAME#
13 CAS6#/D
Q
M6 CAS2#/D
Q
M2 AD01 LOCK#
14 MA00 MA01 AD02 DEVSEL#
15 CKEA CKEB AD03 IRDY#
16 V3S V3S V3S V3S
17 MA02 MA04 AD04 TRDY#
18 MA03 MA05 AD05 STOP#
19 MD55 MD22 AD06 PHOLD#
20 MD54 MD23 AD07 PHLDA#
21 Gnd Gnd Gnd Gnd
22 MD51 MD20 AD08 PCI RST#
23 MD52 MD21 AD09 PAR
24 MD53 MD19 AD10 SERR#
25 MD49 MD17 AD11 RE
Q
0#
26 V3S V3S V3S RE
Q
1#
27 MD48 MD18 AD12 RE
Q
2#
28 MD50 MD16 AD13 RE
Q
3#
29 SRASA# SCASA# AD14 GNT0#
30 SRASB# SCASB# AD15 GNT1#
31 Gnd Gnd Gnd Gnd
32 MWEA# MECC3 AD16 GNT2#
33 MWEB# MECC7 AD17 GNT3#
34 RAS0#/CS0# MECC6 AD18 L2 ZZ
35 RAS1#/CS1# MECC2 AD19 Reserved
36 V3S V3S V3S V3S
37 MD14 MECC1 AD20 Reserved
38 MD11 MECC5 AD21 PPP PP#
39 MD15 MECC4 AD22 CLKRUN#
40 Gnd Gnd Gnd Gnd
41 MD10 MECC0
RAS2#/CS2#
SM CLK
42 MD13 MD43
RAS3#/CS3#
SM DATA
43 MD09 MD41
RAS4#/CS4#
ATF INT#
44 MD08 MD45
RAS5#/CS5#
SUSCLK
45 V3S V3S V3 V3
17
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Pin# Row Row Row Row
46 MD12 MD42 AD23 SUS STAT#
47 MA06 MD40 AD24 V 3
48 MA07 MD44 AD25 OEM PU
49 MA08 MD46 AD26 VR ON
50 Gnd Gnd Gnd Gnd
51 MA09 MD47 AD27 VR PWRGD
52 CAS1#/DQM1 CAS5#/DQM5 AD28 V 3
53 CAS4#/DQM4 CAS0#/DQM0 AD29 V 3
54 MA10 MA12 AD30 Reserved
55 V 3S V 3S V 3S Reserved
56 MA11 MA13 AD31 INIT#
57 MD39 MD07 C/BE0# V CPUIO
58 MD37 MD02 C/BE1# INTR
59 MD38 MD00 C/BE2# CPURST
60 Gnd Gnd Gnd Gnd
61 MD36 MD04 C/BE3# STPCLK#
62 MD33 MD01 IGNNE# SMI#
63 MD35 MD03 FERR# NMI
64 MD32 MD06 A20M# V 5
65 MD34 MD05
VCPUIO
VCPUIO
66 V 3S V 3S TDO TRST#
67 OEM PD PCLK ITP0 TDI
68 FQS0 FQS1 ITP1 TMS
69 HCLK1 HCLK0
CPU3.3 2.5#
TCLK
70 Gnd Gnd Gnd Gnd
18
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
3.3 Pin and P ad Assignments
The Pentium II processor MMC-1 is a surface mount, 0.6-
mm pitch, and 280-pin connector. There are currently three
different sized mating connector receptacles offered for the
Pentium II processor mobile module. See section 5.1.4.
Height Restrictions
or contact your local Intel sales
repr es e ntative for mo re information.
Figure 2 shows the connector pad assignments for the
manufacturer’s system electronics. This footprint is view ed
from th e secondary side of the Pentium II proce ssor module
(the side of the printed circuit board on which the 280-pin
connector is soldered).
AA 70AA 1
AB 70AB 1
BA 70BA 1
BB 70BB 1
280- Pin Connect or Footprint
OEM Pa d A s signments
( Viewed from the se c ondary side of the processor mo dule)
Figur e 2. 28 0-Pi n Co nn ect or Footpr int Pad Nu mb ers, Mod ule Seco ndar y Sid e
19
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Table 11 summarizes the key specifications for the MMC-1.
Table 11. Connector Specifications
Parameter Condition Specification
Material Contact Copper Alloy
Housing Thermo Plastic Molded Compound: LCP
Electrical Current 0.5 A
Vol t ag e 50 VAC
Insulation Re sistance 100 MΩ min. at 500 VDC
Termination Resistance 20 mΩ max. at 2 0 mV op en c irc uit wit h 10 mA
Capac i tanc e 5 pF max. pe r co ntac t
Mechanical Mating Cycles 50 cycles
Connector Mating Force 0.9N (90 gf) max. per contact
Contact Un-mating Force 0.1N (10gf) min. per contact
4.0. F UNCTIONAL DES CRIPTION
4.1. Pentium II Processor Mobile Module
The Pentium II processor mobile module supports the
Mobile Pentium II processor core with 32 KB L1 data cache,
the 443BX Host B ridge System Controller, and system level
support. The mobile Pentium II processor includes a 66-MHz
system bus speed and offers speeds of 300 MHz, 266 MHz,
and 233 MHz.
4.2. L 2 Cache
The Mobile Pentiu m II processor core’s internal cache is
enhanc ed by a sec o nd-level cache us ing a hi gh-
perf or ma nc e pi pe line b ur s t SRA M. SRA M us es a ded ic at ed
high- s p ee d bus into t he proc es s or co re. T he L2 cac h e ca n
support 512 MB of system memory. The maximum amount
of cacheable system memory supported by the 443BX Host
Br idge syst em controller is 256 MB with 16-Mbit DRAM s.
(The system controller can support up to 1 GB of system
memory using 64-Mbit technology.) The Pentium II processor
mobile module has two 100-pin TQFP footprints for 512K
direct-mapped write-back L2 cache.
The Pentium II processor mobile module supports the “Stop
Clock” mode of power management for the L2 SRAMs. In
this mode, the clock signals to the synchronous SRAMs are
“parked” in a low power state.
4.3. T he 443BX Host Brid ge System
Controller
Intel’s 443BX Host Bridge system control ler combines the
mobile P e nti um II processor bus controller, the DRAM
controller, and the PCI bus controller. The 443BX Host
Bridge has multiple po wer managemen t fea tures designed
spec ifically for note bo ok systems such as:
• C LKRU N#, a f ea ture tha t en ab les co ntr ollin g of t h e PCI
clock on or off.
• The 443BX Host Bridge suspend modes, including
Suspend-to-RAM (STR), Suspend-to-Disk (STD), and
Powered-On-Suspend (POS).
• System Ma nagement RAM (SM RAM) power
management modes, including Compatible SMRAM
(C_SMRAM) and Extended SMRAM (E_SMRAM).
C_SMRAM is the traditional SMRAM feature
implemented in all Intel PCI chipsets. E_SMRAM is a
new feature that supports write-back cacheable
SMRAM s pac e up to 1 MB . To min im iz e power
consumption while the system is idle, the internal
443BX Host Bridge clock is turned off (gated off). This
is accomplished by setting the G_CLK enable bit in the
power management register in the 443BX through the
system BIOS.
Pentium II processor mobile modules support only the
443BX Host Bridge features in mobile compatible mode.
Refer to Intel’s latest revision of the 443BX Host Bridge
specification for complete details.
4.3.1. Memory Organization
The me mor y int erfac e of th e 443B X H os t Bridge is av ai la ble
at the MMC-1 allowing support for the following:
• One set of memory control signals sufficient to support
up to three SO_DIMM sockets and six banks of
SDRAM at 66 MHz.
• One CKE signal for all banks.
Memory features not supported by the MMC-1 are:
20
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
• Support for eight banks of memory.
• Mixed Mode memory (EDO and SDRAM).
• Second set of memory address lines (MAA[13:0]).
• Error Correction Code (ECC).
• 100-MHz SDRAM (and PSB).
• Accelerated Graphics Port (AGP).
The 443BX Host Bridge syst em controller includes EDO and
SDRAM. T hese memory types should not be mixed in the
system, so that all DRAM in all ro ws (R AS[5:0]#) must be of
the same technology. The 443 BX Host Bridge system
controller targets 60-ns EDO DRAMs and 66-MHz SDRAMs.
The Pentium II processor mobile module’s clocking
architecture supports the use of SDRAM. Due to the tight
timing requiremen ts of 66-MHz SDR AM clocks, all ho st and
SDRAM clocks may be gen erated from the same clocking
architecture on the OEM’s system elect ronics. For complete
details about using SDRAM memory, and for trace length
guideli nes , ref er to th e
Mobile Pentium® II processor /
82443BX PCIset Advanced Platform Recommended Design
and Debug Practices.
Refer to the
Intel 440BX PCIset
Datasheet
for details on memory device support,
organization , size, and add ressing.
4.3.2 . Reset Str ap Options
Several strap options on the memory address bus define the
behav ior of the Pent ium II processor mobile module after
reset. Other straps are allowed to override the default
settings. Table 12 shows the various straps and their
implementation.
Table 12. Configuration Straps for the 443BX Host Bridge System Controller
Signal Function Module Default Setti ng
MAB[12]# Host Frequency
Select No strap. (66 MHz default).
MAB[ 1 1]# In ord er qu eu e
depth No strap. (Maximum Queue Dept h is set, i.e. 8 ).
MAB[10] Quick Start
Select Strapped high on the module for Quick Start mode.
M AB[9]# AGP disable Strapped to disable AGP.
MAB[7]# MM Config Strapped for MMC-1 compatible mode.
MAB[6]# Host Bus Buffe r
Mode Select Strapped high on the module for mobile FSB buffers.
4.3.3. PCI Interface
The PCI interface of the 443BX Host Bridge is available at
the MMC-1. The 443BX Host Bridge supports the PCI
Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain
signal when they require the use of the PCI interface. Refer
to the
PC I Mobile Design G uide
for comple te det ails on the
PCI Clockrun protocol.
The 443BX Host Bridge is responsible for arbitrating the PCI
bus. In MMC-1 mode, the 443BX Host Bridge can only
support up to five PCI bus masters. There are five PCI
Req ues t/G r an t pairs , R EQ [4 :0]# an d GN T [4: 0]#, av aila ble on
the MMC-1.
The 443BX Host Bridge system cont roller is com plian t with
the PCI 2.1 specification, which improves the worst case PCI
bus access latency from earlier PCI specifications. As
detailed in the PCI specification, the 443BX Host Bridge
supports only Mechanism #1 for accessing PCI configuration
space. This implies that signals AD[31:11] are available for
PCI IDSEL signals. However , since the 443BX Host Bridge is
always device #0, AD11 will never be asserted during PCI
configuration cycles as an IDSEL. The 443BX reserves
AD12 for the AGPbus, which is not supported by MMC-1.
Thus, AD13 is t he firs t av ai la bl e ad dr es s lin e us ab le as an
IDSEL. AD18 should be used by the PIIX4E.
4.3.4 AGP Feature Set
The Intel Pentium II MMC-1 family does not support the
AGP interface. However, the MMC-2 family supports AGP.
Please refer to the
Pentium II Processor Mobile Module:
M obile Module Connec tor 2 (M MC-2) Data sh eet.
21
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.4. Power Management
4.4.1 Clock Control Architecture
The Pentium II processor mobile module’s clock control
architecture (Figure 3) is optimal for notebook designs.
The clock control architecture consists of seven different
clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep states.
The Auto Halt state provides a low power clock state that
can be c ontrolle d thr o u gh th e sof t ware ex ec utio n of t he HLT
instruction. The Quick Start state provides a very low power,
low exit latency clock state that can be used for hardware
controlled “idle” computer states. The Deep Sleep State
prov i des an extr em ely low p ower st at e tha t ca n be us ed f or
“Power-on Suspend” computer states, which is an alternative
to shutting off the processor’s power.
Com pa red t o the Pe ntiu m pr oc es s or mob il e module exit
latency of 1 msec, the exit latency of the Deep Sleep state
has be en r e duc e d to 30 µsec in the Pentium II processor
mobile m o d ul e.
The Stop Grant and Quick Start clock states are mutually
exclusive, for example a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is
asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the
STPCLK# signal puts the Pentium II processor into the Stop
Grant state. The Stop Grant state has a higher power level
than the Qui ck Start state and is designed for SMP
platforms. The Quick Start state has a much lower power
level, but it can only be used in uniprocessor (UP) platforms.
Performing state transitions not shown in Figure 3 is neither
recommended nor supported.
22
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
HALT/Grant
Snoop
Normal
State
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and ! HS)
or RESET#
Snoop
serviced Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
HLT and
halt bus cycle
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP# BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
NOTES: halt break – A20 M#, BINIT#, FLUSH#, IN IT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT – H LT instruction executed
HS – Processor Halt State
QSE – Qui ck Start State Enabl ed
SGA – Stop Grant Acknowledge bus cycle issued
Stop break – BINIT#, FLUSH#, RESET#
Figur e 3. Pent ium II Processor Mobile Module Clock Control States
23
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.4.2. Normal State
The normal operating mode for the mobile Pentium II
processor. The processor’s core clock is running and the
processor is actively executing instructions.
4.4.3. Auto Halt State
This is a low-power mode entered through the HLT
instruction. The power level is similar to the Stop Grant state.
A transition to the Normal state is made by a halt break
event (one of the following signals going active: NMI, INTR,
BINIT#, INIT#, RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state
will cause the processor to transition to the Stop Grant or
Quick Start state, which issues a Stop Grant Acknowledge
bus cycle. Deasserting STPCLK# will cause the processor to
return to the Auto Halt state without issuing a new Halt bus
cycle.
The SMI# (System Management Interrup t) is recogni z ed in
the Auto Halt state. The return from the SMI handler can be
to either the Normal state or the Auto Halt state. See the
Intel ® Architecture Software Developer’ s Manual, Volume
III: System Programmer’s Guide
for more information. No
Halt bus cycle is issued when returning to the Auto Halt state
from System Mana gement M ode (SMM).
The FLUSH# signal i s serviced in th e Auto Halt state . After
flushing the on-chip, the processor will return to the Auto
Halt state without issuing a Halt bus cycle. Transitions in the
A20M# and PREQ# signals are recognized while in the Auto
Halt state.
4.4.4. Stop Grant State
The Stop Grant state is not supported in the Intel mobile
modules The processor enters this mode with the assertion
of the STPCLK# signal when it is configured for Stop Grant
state (via the A15# strapping option). The processor is still
able to respond to snoop requests and latch interrupts.
Latched interrupts will be serviced when the processor
returns to the Normal state. Only one occurrence of each
interrupt event will be latched. A transition back to the
Normal state can be made by the deassertion of the
STPCLK# signal or the occurrence of a stop break event (a
BINIT#, FLUSH #, or RESET# assert ion).
The processor will return to the Stop Grant state after the
comp le tion of a B INI T # bus in iti al iz ati on unles s STPCLK #
has been deasserted. RESET# assertion will cause the
processor to immediately initialize itself, but the processor
will stay in the Stop Grant state after initialization until
STPCLK# is deasserted. If the FLUSH# signal is asserted,
the processor will flush the on-chip caches and return to the
Stop Grant state. A transition to the Sleep state can be made
by the assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#, INIT#,
INTR, and NMI (or LINT[1:0]) will be latched by the
processor. These latched events will not be serviced until the
processor returns to the Normal state. Only one of each
event will be recognized upon return to the Normal state.
4.4.5. Quick Start State
This is a mode entered with the assertion of the STPCLK#
signal when it is configured for the Quick Start state (via the
A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions
generated by the system bus priority device. Because of its
snooping behavior, Quick Start can only be used in UP
configuration. A transition to the Deep Sleep state can be
made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start
state) is made only if the STPCLK# signal is deasserted.
While in this state the processor is limited in its ability to
respon d to inpu t. It is incapa ble of latching an y interrupts,
servicing snoop transactions from symmetric bus masters, or
res po nd in g to FLU SH# or BIN IT # as s ert i ons . Whil e t he
processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#,
or BPRI#. If any other input signal changes, then the
behavior of the processor will be unpredictable. No serial
interrupt messages may begin or be in progress while the
processor is in the Quick Start state. RESET# assertion will
cause the processor to immediately initialize itself, but the
processor will stay in the Quick Start state after initialization
unt il STP C LK# is deas s er te d.
4.4.6. HALT/Grant Snoop State
The processor will respon d to snoop transactions on the
system bus while in the Auto Halt, Stop Gra nt, or Quick Start
state. When a snoop t ransac tion is presented on the system
bus the processor will enter the HALT/Grant Snoop state.
The processor will remain in this state until the snoop has
been serviced and the system bus is quiet. After th e snoop
has been serviced, the processor will return to its previous
state. If the HALT/Grant Snoop state is entered from the
Quick Start state, then the input signal re strictions of the
Quick Start state still apply in the HALT/Grant Snoop state,
except for those signal transitions that are required to
perform the snoop.
4.4.7. Sleep State
The Sleep state is a very low power state in which the
processor maintains its context and the phase-locked loop
(PLL) maintains phase lock. The Sleep state can only be
entered from the Stop Grant state. After entering the Stop
Grant state th e SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# signal is not
recognized in the Normal or Auto Halt states.
The processor can be reset by the RESET# signal while in
the Sleep state. If RESET# is driven active while the
processor is in the Sleep state then SLP# and STPCLK#
must immediately be dr iven inactive to ensure that the
processor correctly initializes itself.
Input signals (other than RESET#) may not change while the
processor is in the Sleep state or transitioning into or out of
24
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
the Sleep stat e. Inpu t signa l changes at these time s will
cause unpredictable behavior. Thus, the processor is
incapable of snooping or latching any events in the Sleep
state.
While in the Sleep state the processor can enter its lowest
power state, the Deep Sleep state. Removing the
processor’s input clock puts the processor in the Deep Sleep
state. PICCLK may be removed in the Sleep state.
The Sleep state is not supported in Intel mobile modules.
4.4.8. Deep Sleep State
The Deep Sleep state is the lowest power mode the
processor can enter while maintaining its context. The Deep
Stopping the BCLK input to the processor enters sleep state,
while it is in the Sleep state or Quick Start state. For proper
operation, the BCLK input should be stopped in the low
state.
The processor will return to the Sleep state or Quick Start
state from the Deep Sleep state when the BCLK input is
restarted. Due to the PLL lock latency, there is a 30-msec
delay af ter the clocks have st arted before this state transition
happens. PICCLK may be removed in the Deep Sleep state.
PICCLK should be designed to turn on when BCLK turns on
when transitioning out of the Deep Sleep state.
The input signal restrictions for the Deep Sleep state are the
same as for the Sleep state, except that RESET# assertion
will result in unpredictable behavior.
Table 13. Mobile Pentium II Processor Clock State Characteristics
Clock
State Exit Laten cy Proc es sor
Power Snooping
?System Uses
Normal N/A Varies Yes Normal program execution.
Auto Halt Approximately 10 bus clocks 1.2 W Yes S/W controlled en try idle
mode.
Stop Grant 10 bus clocks 1.2 W Yes H/W controlled entry/exit
mobile thrott li ng.
Quick Start Through snoop, to HALT/Grant
Snoop stat e: immediate
Through STPCLK#, to Normal
state: 10 bus clocks
0.5 W Yes H/W controlled entry/exit
mobile thrott li ng.
HALT/Grant
Snoop A few bu s clocks a fter the end of
snoo p ac tiv ity . Not
specified Yes Supports snooping in the
low power st at es .
Sleep To Stop Grant state 10 bus clocks 0.5 W No H/W controlled entry/exit
desktop idle mode support.
Deep Sleep 30 msec 150 mW No H/W controlled entry/exit
mobile powered-on suspend
support.
NOTE:
Not 100% tested. Specified at 50°C by design/characterization.
4.5. Typ ical POS/ST R Power
Table 14 shows the POS/STR power va lues.
Table 14. Mobile Pentium II Processor POS/STR Power
State Typical MMC1 Power
POS 910 mW
STR 3 mW
NOTE:
These are average values of measurement on several typical modules and are guidelines only.
25
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.6. Electrical Requirement
The following section provides information on the DC
requirements for the Pentium II processor mobile module.
4.6.1 . DC Requirements
Please refer to Table 15 for power supply design criteria to
ensure compliance with the DC power requirements.
Table 15. Pentium II Pr oc es sor M obil e Mo dul e Pow er Sp ecific ati ons 1
Voltage
Plane Minimum
Voltage Typical
Voltage
Absolute
Maximum
Voltage
DC
Minimum
Operatin
g Current
DC
Typical
Operatin
g Current
DC
Maximum
Operatin
g Current
Instan-
taneous
Peak
Current
Leakage3
Typical
25°C
V_DC 5.0V 12.0V421. 0V 75 mA 0.6 A 12.85A214.2A 4.0 uA
V_5 4.75V 5.0V 5.25V 13 mA 32 mA 60 mA 500 mA 1 uA
V_3 3.135V 3.3V 3.465V 0.2A 0.7A 1.60A 2.0A 1.1 mA
V_3S 3.135V 3.3V 3 .465V 30 m A 0.2A 0.52A 0. 7A 2 uA
V_CPUIO 2.375V 2.5V 2.625V 0.0 mA450 mA480 mA 0.0 mA 0.0 mA
NOTES:
1. V_DC is set for 18V in order to determine typical V_DC current.
2. V_DC is set for 5V in order to determine Maximum Operating V_DC current.
3. Leakage current that can be expected when VR_ON is deactivated and V_DC is still app lie d .
4. These values are OEM system dependent.
26
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.6.2 AC Requirements
Table 16 provides the BCLK AC requirements.
Table 16. Pentium II Processor Mobile Module AC Specifications (BCLK)
at the Processor Core Pins 1, 2, 3
T# Parameter Min Nom Max Unit Figure Notes
Sy s tem Bus Fr e qu enc y 66. 67 MHz All proces s or core
freq ue nc i es 4
T1: BCLK Per iod 15.0 ns 4, 5
T2: BCLK Period Stability ±250 ps 6, 7, 8
T3: BCLK High Time 5.3 ns At >1.8V
T4: BCLK Low Time 5.3 ns At <0.7V
T5: BCLK Rise Time 0.175 0.875 ns (0.9V-1.6V) 8
T6: BCLK Fall Ti me 0.175 0.8 75 ns (1.6 V– 0.9V ) 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
2. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All GTL+ signal
timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal
timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
4. The internal core clock frequency is derived from the system bus clock. The system bus clock to core clock rati o is deter mined during
initialization as described and is predetermined by the Pentium II processor mobile module.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the
CK97 Clock Synthesizer/Driver Specification
for further
information.
6. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew
between devic es.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock
driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than?500 kHz. This specification may be
ensured by design characterization and/or measured with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver Specification
for further details.
8. Not 100% tested. Specified by design characterization as a clock driver requirement.
27
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.6.2.1. System Bus Clock (BCLK) Signal Quality
Spe cifications and Measurement
Guidelines
Table 17 describes the signal quality specifications at the
processor core for the BCLK signal.
Figure 4 describes the signal quality waveform for the BCLK
at the processor core pins.
Table 17. BCLK Signal Quality Specifications at the Processor Core
T# Parameter Min Nom Max Unit Figure Notes
V1: BCLK VIL 0.7 V 4 2
V2: BCLK VIH 1.8 V 42
V3: VIN Absolute Voltage Range –0.8 3.5 V 4 3
V4: Rising Edge Ringback 1.8 V 4 4
V5: F al li ng Ed ge R in g bac k 0.7 V 4 4
BCLK rising/falling slew rate 0.8 4 V/ns
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
2. BCLK must rise/fall monotonically between VIL,BCLK and VIH, BCLK.
3. The system bus clock overshoot and undershoot specification for the 66-MHz system bus operation.
4. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal
can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
5. For proper signal termination, refer to the Clocking Guidelines in the
Mobile Pent ium
II Processor / 440BX PCIset Advanced
Platform Recommend Design and Debug Practices.
V2
V1
V3
V3
T3
V5
V4
T6 T4 T5
000806
Figure 4. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pin
4.7. Vol t age Regulator
The DC voltage regulator (DC/DC converter) provides the
appropriate core voltage, the I/O ring voltage, and the
sideband signal pullup voltage. The voltage range is 5V –
21V.
4.7.1. Voltage Regulator Efficiency
Table 18 lists the voltage regulat or efficiencies.
28
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Table 18. Typical Voltage Regulator Efficiency
Icore, A3V_DC, V I _ DC, A2Efficiency1
1 5.0 0.370 82.8%
2 5.0 0.702 88.8%
3 5.0 1.044 89.8%
4 5.0 1.404 89.7%
5 5.0 1.762 88.1%
6 5.0 2.144 86.4%
7 5.0 2.528 85.0%
1 12.0 0.159 79.7%
2 12.0 0.295 87.0%
3 12.0 0.438 87.8%
4 12.0 0.584 87.3%
5 12.0 0.736 86.1%
6 12.0 0.890 84.9%
7 12.0 1.043 83.8%
1 21.0 0.091 79.3%
2 21.0 0.170 86.0%
3 21.0 0.253 87.3%
4 21.0 0.340 85.3%
5 21.0 0.429 84.1%
6 21.0 0.519 82.9%
7 21.0 0.617 80.7%
NOTES:
1. These efficiencies will change with future voltage regulators that accommodate wider ranges of input voltages.
2. With V_DC applied and the voltage regulator off, typical leakage is 0.3 mA with a maximum of 0.7 mA.
3. Icore indicates the CPU core current being drawn during test and measurement.
4.7.2. Control of the Voltage Regulator
The VR_ON pin turns the DC voltage regulator on or off. The
VR_ON pin should be controlled as a function of the SUSB#,
whic h controls the system’s power planes. VR_O N should
switch high only when the following conditions are met:
V_5(s ) => 4.5V an d V_D C => 4.75V .
CAUTION- Turning on VR_O N pri or to meet ing the s e
conditions will severely damage the Pentium II
proc es sor mobile module.
The VR_P WRGD signal in dicates that the voltage regula tor
power is operating at a stable voltage level. Use
VR_PWRGD on the system electronics to control power
inputs and to gate P WROK to the P IIX4 E.
Table 19 lists the voltage signa l def initions and sequences.
Figure 5 shows the signal sequencing and the voltage
planes sequencing required for normal oper ation.
29
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.7.2.1. Voltage Signal Definition and Sequencing
Table 19. Voltage Signal Definitions and Sequences
Signal Source Definitions and Sequences
V_DC Sy s tem E l ec tro nic s DC voltage is driven from the power supply and is
required to be between 5V and 21V DC. V_DC
powers the Pentium II processor mobile module’s
DC-to-DC converter for processor core and I/O
voltages. It cannot be hot inserted or removed while
V_DC is powered on.
V_3 Sy s tem El ec tr o nic s V_ 3 is suppl ied by the system electronics for the
443BX.
V_5 System Ele ctronics V_5 is supplied by the system electronics for the
443B X’s r ef erenc e v oltage and the volt age r eg ul ator .
V_3S System Ele c tronics V_3S is supplied by the system electronics for the L2
cache devices. Each must be powered off during
system STR and STD states.
VR_O N Sys tem E l ec tro nic s Enables the voltage regulator circuit. When driven
active high (3.3V) the voltage regulator circuit is
ac tivated. The sign al dri v ing VR_ON shou ld be a
digital signal with a rise/fall time of less than or equal
to 1 µs. (VIL (max)=0.4V, VIH (min)=3.0V). See notes
below.
V_CORE (also
used as host bus
GTL+ termination
voltage VTT )
Pentium II processor mobile
module Only; not on module
interface.
A resu lt of VR _O N be in g as s er te d, V_CO RE is an
output of the DC-DC regulator on the Mobile Module
and is driven to the core voltage of the processor. It is
also used as the host bus GTL+ termination voltage,
known as VTT.
V_BSB_IO Pentium II processor mobile
module V_BSB_I O is 1.8V. The system electron ics uses this
volta ge t o powe r the L2 cac h e-t o- pr oc es s or interf ac e
circuitry.
VR_PWRGD Pentium II processor mobile
module Upon sampling the voltage level of V_CORE (minus
tolerances for ripple), VR_PWRGD is driven active
high. If VR_PWRGD is not sampled active within 1
sec. of the assertion of VR_ON, then the system
electronics should deassert VR_ON. After Vcore is
stabil ized, VR_ PWRGD will assert to logic high
(3.3V). This signal
must not be pull ed up
by the
system el ectronics. VR_PWRGD should be “AND ed”
with V_3s to generate the PIIX4E input signal,
PWROK . The system el ectronics should mon itor
VR_PWRGD to verify it is asserted high prior to the
active high assertion of PIIX4E PWROK.
V_CPUIO Pentium II processor mobile
module V_CPUIO is 2.5V. The system electronics uses this
voltage to power the PIIX4E-to-processor interface
circuitry, as well as the HCLK(0:1) drivers for the
processor clock.
NOTES:
1. The VR_ON signal may only be asserted to a logical high by a digital signal only after V_DC>=4.7V, V_5>=4.5V, and V_3>=
3.0V.
2. The rise time and fall time of VR_ON must be less than or equal to 1 µs when it goes through its Vil to Vih.
3. VR_ON has its Vil (max) = +0.4V and Vih (min) = + 3.0V.
4. VR_ON needs to rise monotonically through its Vil to Vih points.
5. VR_ON needs to provide an instantaneous in-rush current to the module with the following values: an instantaneous max. of
41 mA with a typical of 0.2 mA; a DC operating max. of 0.1 µA with a typical of 0.0.
6. In going from a valid on to valid off and then back on, VR_ON must be low for 1 ms. In addition, the original voltage level
requirements for turn-on always need to be met before assertion of VR_ON (i.e. V_DC>=4.7V, V5>=4.5V, V_3>=3.0V).
30
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
POWER SEQUENCE TIMING
V_DC
1. PWROK on I/O board s houl d be ac ti ve on when VR_PWRGD is active and V _3S is good.
2. CPU_RST from I/O boar d should be active for a minim um of 6 m s after PWROK is act ive and PLL_STP# and CPU_STP# are
inactive. Not e tha t PLL_STP# is an AN D condit ion of RSMRST# and SUSB# on the PI IX4E / M .
3. V_DC >= 4.7V, V_5>=4.5V, V_3S>=3.0V.
4. V_CP UP U and V_CLK are ge nerat ed on t he I nte l M obile Modu le.
5. This is the 5V power supplied to the processor m odule connector. This should be the first 5V plane t o power up.
6. VR_P WRGD is speci fiedt o it s associat ed high/active by the module re gul at or wit hi n less than or equal t o 6 ms max. after the
a ss er t ion of V R_ON.
V_3
V_5
VR_PWRGD
V_3S
VR_ON
0 MS MIN 0 MS MIN
0 MS MINSee Note 6
See Note 3
V_CPUIO/
V_CLK
See Note 5
Figure 5. Power-On Sequence Timing
In the power-on process, Intel recommend s that the higher
voltage power (V_DC) plane is raised first, followed by the
lower power planes (V_5 and V_3), and finally the assertion
of VR_ON. In the power-off process, the reverse applies so
that first VR_ON is deasserted, followed by the lower power
planes, and finally the higher power plane.
4.7.3. Power Planes: Bulk Capacitance
Requirements
In ord er to pr ov i de ade qu at e filter i ng and in - rus h current
protection for any system design, bulk capacitance is
required. A small amount of bulk capacitance is supplied on
the Pentium II processor mobile module. However, in order
to achieve proper filtering additional capacitance should be
plac ed on t he system electronics.
Table 20 details t he bulk ca pacitance requirements for the
system electroni cs when using the Pentium II processor
mobile m o d ul e.
Table 20. Capacitance Requirements per Power Plane
Power Plane Capacitance Requirements ESR Ripple Current Rating
V_DC 100 uf, 0.1 uf, 0.01 uf120 mΩ1- 3. 5A 320% t ol era nc e at 35V
V_5 100 uf, 0.1 uf, 0.01 uf110 0 mΩ1A 20% tol eranc e at 10V
V_3 470 uf, 0.1 uf, 0.01 uf110 0 mΩ1A 20 % t ol era nc e at 6V
V_3S 100 uf, 0.1 uf, 0.01 uf110 0 mΩN /A 20% toler a nc e at 6V
V_CPUIO 2.2 uf, 8200 pf1n/a n/a 20 % toler a nc e at 6V
NOTES:
1. Placement of above capacitance requirements should be located near the MMC-1.
2. V_CPUI O filtering should be located n ext to the system clock synthesizer.
3. Ripple current specification depends on V_DC input. For 5.0V V_DC, a 3.5A device is required. For V_DC at 18V or higher,
1A is sufficient.
31
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.7.4. Surge Current Guidelines
This section provides the results of a worst case, surge
current analysis. The analysis determines the maximum
amount of surge current that the Pentium II processor
mobile module can manage.
In the analysis, the Pentium II processor mobile module has
two 4.7 µf with an ESR of 0.15Ωs each. The MMC-1 is
appr ox i m ate ly 30 mΩ of series resistance, for a total series
resistance of .18Ω. If the user powers the system with the
A/C adapter (18V), the amount of surge current on the
module would be approximately 100A.
This information was also used to develop I/O bulk
capacitance requirements (See Table 20).
NOTE: Depending on th e system electronics de sign,
different impedances may yield different results. The OEM
shou ld per for m a thor o ug h an aly s is to und ers tan d t he
implicati ons of s urg e current on th eir system.
Figure 6 shows an electrical model used when analyzing
instantaneous power-on conditions and Figure 7 illustrates
the results with a SPICE simulation.
Figur e 6. Inst antaneo us In-Rush Current Mo de l
32
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Figur e 7. Instantaneo u s In-R ush Current
Due to the stringent component height requirements of the
Pentium II proc ess or mobil e mo dule , P oly m erized Organic
Se mi-c o nd uc tor capac it or s mus t be use d as inp ut bu lk
capacitance in the voltage regulator circuit. Because of the
capacitor’s susceptibility to high in-rush current, special care
must be taken. One way to soften the in-rush current and
provide over-voltage and over-current protection is to ramp
up V_DC slowly using a circuit similar to the one shown in
Figure 8.
33
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Figure 8. Over-Current Protection Circuit
4.7.4.1. Slew-Rate Control: Circuit Description
In Figure 8, PWR is the voltage generated by applying the
AC Adaptor or Battery. M1 is a low RDS (on) P-Channel
MOSFET such as a Siliconix* SI4435DY. When the voltage
on PWR is app lied an d inc r e as e d to ov er 4.75V, t he
UNDER_VOLTAGE_LOCKOUT circuit allows R4 to pull up
the gate of M3 to start a turn-on sequence. M3 pulls its drain
toward ground, forcing current to flow through R2. M1 will
not start to source any current until after t_delay with t_delay
defined as:
t_delay ..
R2 C9 ln 1 Vt
Vpwr Vgs_max
Vg s _max .
R16
R16 R2 Vpwr
The manufacturer’s Vgs_max specification of 20V must
never be exceeded. However, Vgs_max must be high
enough to keep the RDS (on) of the device as low as
possible. After the initial t_delay, M1 will begin to source
current and V_DC will start to ramp up. The ramp up time,
t_ramp, is defined as:
t_ramp ..
R2 C9 ln 1 Vsat
Vgs_max t_delay
Maximum current during the voltage ramping is:
I .
Ct o tal Vpwr
t_ramp
34
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
With the circuit shown in Figure 8, t_delay = 5.53 ms, t_tran
= 14.0 ms and I_max = 146 mA. Figure 9 shows a SPICE
simulation of the circuit in Figure 8. To increase the reliability
of Tantalum capacitors, use a slew rate control circuit as
described in Figure 8 and voltage-derate the capacitor about
50 percent. That is, for a maximum input voltage of 18V, use
a 35V, low ESR capacitor with high ripple current capability.
Place five, 22 µF/35V capacitors on the baseboard directly at
the V_DC pins of the Pentium II processor MMC-1.
The slew rate control circuit should also be applied to every
input pow er source to th e system V_DC to provide the most
protection. If all power is OR’ed together at the PWR node,
there is still a potential problem. For example, if a 3X3 Li-Ion
battery pack is po wering the system (12V at PWR), and the
AC Adaptor (18V) is plugged into the system , curren t will
immediately be sourced to the PWR node and V_DC. This is
because the slew rate control is already ON. Therefore, the
slew rate control must be applied to every input power
source to provide the most protection.
.
Figure 9. Spice Simulation Using In-Rush Protection (Example Only)
4.7.4.2. Under-Voltage Lockout: Circuit Description
(V_uv_lockout)
The circ uit shown in Figu re 8 provides an under-voltage
protection and locks out the applie d volta ge to the Pentium
II processor mobile module to prevent an accidental turn-on
at low voltage. The output of this circuit, pin 1 of the LM339
comparator, is an open-collector output. It is low when the
applied voltage at PWR is less than 4.75V. This voltage can
be calculated with the following equation with the voltage
across D7 as 2.5V. (D7 is a 2.5-V reference generator).
V_uv_lockout .
Vref 1 R17
.
R18R25
R18 R25
=V_uv_lockout 4.757 volt
35
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.7.4.3. Over-Voltage Lockout: Circuit Description
(V_ov_lockout)
The Pentium II processor mobile module is specified to
operate with a maximum input voltage of 21V. This circuit
locks out the input voltage if it exceeds the maxim um 21V.
The output of this circuit, Pin 14 of the LM339 comparator, is
an open- c ol lec t or outpu t. I t is low w h en th e ap pli ed vol tage
at PWR is more than 21V. This voltage can be calculated
with the following equation:
V_ov_lockout ..
Vref R26
R26 R27 1R24
R23
=V_ov_lockout 20.998 volt
4.7.4.4. Over-Current Protection: Circuit
Description
Figure 8 shows the circuit detecting an over-current
condition and cuts off the input. Two different current limit
trip points cause the different maximum current drain
at different input voltages. Assuming the AC Adaptor
is 18V and the battery is a 3x3 Li-Ion configuration with a
minimum voltage of 7.5V, the maximum current for the
above circuit can be calculated using the following
expression:
With AC Adaptor (I_wAd apt or):
I_wAdaptor .
Vref Vbe_Q1
R14
R13
R1
I_wAdaptor = 0.989 • amp
Without AC Adaptor (I_woAdaptor):
I_woAdaptor .
Vref Vbe_Q1
.
R14R33
R14 R33
R13
R1
I_wo Ad aptor = 2.3 75 • amp
4.8. Active T hermal Feedback
Table 21 identifie s the addresses alloc ated for the SM Bus
thermal sensor. Table 21. Thermal Sensor SMBus Address Table
Function Fixed Add ress AD Bit s (6:4) Selectable Address AD Bits (3:0)
Ther m al Se ns or 100 1110
Reserved 010 1010
Reserved 010 1011
NOTE:
The thermal sensor used is compliant with SMBus addressing. Please refer to the
Pentium® II processor Thermal Sensor Interface
Specification
.
36
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
4.9 Thermal Sensor Configuration
Register
The configuration register of the thermal sensor controls the
operating mode (Auto-convert vs. Standby). Since the
processor temperature varies dynamically during normal
operation, auto-convert mode should be used exclusively to
monitor processor temperature If the RUN/STOP bit is low,
then the thermal sensor enters auto-conversion mode. If the
RUN/STOP bit is set high, then the thermal sensor
immediately stops converting and enters
Standby mode. The thermal sensor will still perform
temperature conversions in Standby mode when it receives
a one-shot command. However, the result of a one-shot
command during auto-convert mode is not guaranteed. Intel
recommends that only auto-convert mode should be used.
Refer to
Mobile Pentium
®
II Processor and Pentium
®
II
Processor Mobile Module Thermal Sensor Interface
Specifications
, Rev.1.0. Table 22 shows the format of the
configuration register.
Table 22. Thermal Sensor Configuration Register
Bit Name Reset State Function
7 MSB MASK 0 Masks SMBALERT# when high.
6 RUN/STO
P0 Standby mode control bit. If low, the device enters auto-
convert mode. If high, the device immediately stops
converting, and enters standby mode where the one-shot
command can be performed.
5 – 0 RFU 0 Reserved for future use.
NOTE:
All RFU bits should be written as “0” and read as “don’t care” for programming purposes.
37
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
5.0. MECHANICAL SPECIFICATION
5.1. Module Dimensions
This section provides the physical dimensions for the
Pentium II processor MMC-1.
5.1.1. Board Area
Figure 10 shows the board dimensions and the orientation
for the Pentium II processor MMC-1.These dimensions are
neces s ary to ac c om m od ate the nex t gen er a ti on of Int el
mobile modules and PCI 443BX chipset controllers.
Figur e 10. Penti um II Processor MMC-1 Board Dimensions with 280-Pin Connector Orientation
38
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
5.1.2. MMC-1 Pin 1 Location
Figure 11 shows the location of pin 1 of the 280-pin MMC-1
as referenced to the adjacent mounting hole.
Secondary Side
Dimensions are i n Inches
Figur e 11. Penti um II Processor Mobile Module Board Dimensions with 280-Pin Connector - Pin 1 Orientation
5.1.3. Printed Circuit Board Thickness
Figure 12 shows the Pentium II processor mobile module
prof il e and t he as s oc ia te d minimum a nd max im um t hic k n es s
of the printed circuit board (PCB). The range of PCB
thickness allows for different PCB technologies to be used
with current and future Intel mobile modules.
NOTE: The system manufacturer must ensure that the
m echanical restraining method or system-level EMI contacts
are able to support this range of PCB thickness, to ensure
compatibility with future Intel mobile modules.
39
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
min: 0.90 mm
max: 1.10 mm
Processor Module
printed circuit boar d
Figure 12. Printed Circuit Board Thickness
5.1.4. Height Restrictions
Figure 13 shows the mechanical stackup and associated
component clearance requirements. This is referred to as
the module keep-ou t zone and should not be enter ed or
altered.
One of three possible mating connectors (4 mm, 6mm, and
8mm) establish board-to-board clearance between the
Pentium II processor mobile module and the system
electronics. Information on these connectors can be
obtained from your local Intel representative.
Figur e 13. Penti um II Processor Mobile Module 3-D Mechanical Drawing
40
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
5.2. Thermal Transfer Plate
A thermal transfer plate (TTP) on the mobile Pentium II
processor and the 443BX provides for heat dissipation. The
TTP may vary on different generations of Intel mobile
modules. The TTP provides the thermal attach point, where
a system manufacturer can use a heat pipe, a heat spreader
plate, or a thermal solution to transfer heat through the
notebook system. Attachment dimensi ons for th e OEM
thermal interface block to the TTP are provided in the
following figures 14 and 15. The system manufacturer
should use the exact dimensions for maximum contact area
to the TTP. This also protects against warpage of the TTP.
If warpage occurs, the thermal resistance of the Pentium II
processor mobile module could be adversely affected.
A thermal elastimer or thermal grease should be used to
reduce the thermal resistance. The TTP thermal r esistance
between the processor core to the system interface (top of
the TTP) is less than 1°C per Watt. The OEM thermal
int erf ac e bloc k shou ld be sec ured wit h 2.0 mm sc r ews usi ng
a maxi mum torque of 1.5 – 2. 0 Kg* c m (equ iv al ent t o 0.1 47 -
.197 N*m). The thre ad length of the 2.00-mm screws should
be 2. 25- m m ga geab le thread ( 2. 25-mm mi ni mum to 2.80-
mm maximum).
The following figures 14 and 15 detail the mechanical
dimensions of the TTP and the thermal attach point.
Figur e 14. Penti um II Processor Mobile Module Thermal Transfer Plate
41
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Figur e 15. Penti um II Processor Mobile Module Thermal Transfer Plate
5.3. Module Physical Support
Figure 16 shows the standoff support hole patterns, the
boar d e dg e cle ar anc e, t he di m ens i ons of th e EMI
containment ring, and the keep-out area. These hole
locations and board edge clearances will remain fixed for all
Intel mobile modules.
5.3.1 Module Mounting Requirements
Three mounting holes secure the module to the electronics.
See Figure 11 for mounting hole locations. Intel
recommends th at all three mounting holes be us ed to ensure
long term reliability of the system. The hole patterns al so
have a plated surrounding ring, which can be uses with a
m etal standoff for EMI shielding purpo s es.
The board edge clearance includes a 0.762 mm (0.030 in)
width EMI containment ring ar ound the perimeter of the
m odule. This ring is on each la yer of th e module PCB and is
grounded. The metal on the surface of the module is
exposed for EMI shielding purposes.
Standoffs should be used to provide support for the installed
Pentium II processor mobile module. The distance from the
bottom of the module PCB to the top of the OEM system
electronics board with the connectors mated is 4.0 mm +0.16
mm / -0.13 mm. However warpage of the baseboard may
vary and should be calculated into the final. All calculations
can be made with the
I nt el M MC-1 Stando ff/Rece ptac l e
Height
Spreadsheet
. Information on this spreadsheet can be
obtained from your local Intel representative.
5.3.2. Module Weight
The weight of the Pentium II processor mobile module is 48g +/- 2g.
42
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Hole detail, 3 places
Standoff Holes and Board Edge Keepouts (Top Side)
0.762 mm width of EMI containment ring
1.27+/- 0.19 mm board edge to EMI ring
2.54+/-0.19 mm keepout area
3.81+/-0.19 mm board edge to hole centerline
3.81+/-0.19 mm
4.45 mm diameter grounded ring
+ 0.050 mm
- 0.025 mm
hole diameter
2.413 mm
Figure 16. Standoff Holes, Board Edge Clearance, and EMI Containment Ring
6.0. T HERMAL SPECIFICATION
6.1. T hermal Desig n Pow er
The maximum thermal design power (TDP) is the maximum
tot al pow er dis s ip at io n un der n orm al operatin g co ndi tions at
nominal Vcc while executing the worst case power
instruction mix. This includes the power dissipated by
all
of
the relevant components of the Pentium II proce ssor mobile
m odule. System therma l designs do not need the capability
to dissipate this level of power if they incorporate some type
of thermal feedback fail-safe syst em.
The use of nominal Vcc in this measurement accounts for
the ther mal time constant of the package/system. The pow er
supply must be centered at nominal Vcc such that during
transients the Vcc levels stay within the Vcc ± Vcc_Delta (%)
range.
The duration of surges to Vcc + Vcc_Delta (%) are less than
the thermal time constant. During all operating
environments, the processor case temperature, TPROC, must
be within the specified range of 0°C to 100°C.
See Table 23 for the maximum TDP specification.
6.2 Thermal Sensor Setpoint
The thermal sensor in the Pentium II proc es s or mo bil e
module implements the SMBALERT# signal described in the
SMBus specification. SMBALERT# is always asserted when
the temperature of the processor core thermal diode or the
thermal sensor internal temperature exceeds either the
upper or lower te mp erature thr es ho lds . S M BALE RT# may
also be asserted if the measured temperature equals either
the upper or th e lower threshold .
43
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Table 23. Pentium II Pr oc es sor M obil e Mo dul e ( M MC- 1) Ma xi mum Pow er Spe cifi ca tions
Symbol Parameter Typ Max1Unit Notes
TDP2MMC-1 Ther m al Des i gn at 30 0 MH z
Power (MMC-1 modu le) at 26 6 MH z
at 233 MHz
— 13.9 W Module (core, 443BX,
voltage regulator, & L2
cache)
NOTES:
1. TDPMAX is a specification of the total power dissipation of the worst case processor, worst case 443BX, and worst case voltage
regulator while executing a worst case instruction mix under normal operating conditions at nominal voltages. Not 100% tested.
Specified by design/characterization.
7.0. LABELING INFORMATION
The Pentium II processor mobile module is tracked in two
ways. The first is by the Product Tracking Code (PTC). Intel
uses the PTC label to determine the assembly level of the
module. The P TC la be l is located on the sec o nd ar y si de of
the module as shown in Figure 17 and provides the following
information.
• The Product Tracking code will consist of 13 characters as identified in the above example
and can be broken down as follows:
Example:
PMD30005001AA
• Definition: AA - Processor Module = PM
B - Pentium II processor mobile module = D
CCC - Speed Identity = 300, 266, 233
DD - Cache Size = 05 (512.)
EEE - Notifiable Design Revision (Start at 001)
FF - Notifiable Processor Revision (Start at AA)
• Note: For other Intel mobile modules, the second field (B) is defined as:
Pentium II processor mobile module (MMC-2) = E
44
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
Figur e 17. Penti um II Proc es sor Mobile Mo dul e Product Tr a ck ing Cod e
The second tracking method is by OEM generated software
utility. Four strapping resistors located on the Pentium II
processor mobile module determine its production level. If
connected and terminated properly, up to 16-module revision
levels can be determined. An OEM generated software utility
can then read these ID bits with CPU IDs and stepping IDs
to prov i de a c om plete modu le man ufac t ur ing revis io n lev el.
For current PTC and module ID bit information, please refer
to the latest Pentium II processor mobile module Product
Change Notification letter which can be obtained from your
local Intel sales representative
.
45
INTEL PENTI UM II PROCESSOR MOBILE MODULE MMC-1
8.0. ENV IRO NMENT AL STANDARDS
The environmental standards for the Pentium II processor
mobile module are defined in Table 24.
Tab le 24 . Environ me ntal St and ar d s
Parameter Condition Specification
Temperature Non-Operating -40°C to 85°C
Operating 0°C to 55°C
Humidity Unbiased 85% relative humidity at 55 °C
Voltage V_5 5V +/- 5%
V_3 3.3V +/- 5%
Shock Non-Operating Half Sine, 2G, 11 msec
Unpac k a ge d Trap ez oi da l, 50G, 11 msec
Packaged Inclined Impact at 5.7 ft./s
Packaged Half Sine, 2 msec at 36 in.
Simul ated Fr e e Fa ll
Vibration Unpackaged 5 Hz to 500 Hz 2.2 gRMS random
Pac kaged 10 Hz to 50 0 Hz 1.0 gR M S
Package d 11,800 im pacts 2 Hz to 5 Hz (lo w
frequency)
ESD Human Body Model 0 to 2 kV (no detectable err)
UNITED STATES, Intel Corporation
2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119
Tel: +1 408 765-8080
JAPAN, Intel Japan K.K.
5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26
Tel: + 81-29847-8522
FRANCE, Intel Corporation S.A.R.L.
1, Quai de Grenelle, 75015 Paris
Tel: +33 1-45717171
UNITED KINGDOM, Intel Corporation (U.K.) Ltd.
Pipers Way, Swindon, Wiltshire, England SN3 1RJ
Tel: +44 1-793-641440
GERMANY, Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/ Muenchen
Tel: +49 89/99143-0
HONG KONG, Intel Semiconductor Ltd.
32/F Two Pacific Place, 88 Queensway, Central
Tel: +852 2844-4555
CANADA, Intel Semiconductor of Canada, Ltd.
190 Attwell Drive, Suite 500
Rexdale, Ontario M9W 6H8
Tel: +416 675-2438
Printed in USA/96/POD/PMG
