PD - 96224 IRLR3636PbF IRLU3636PbF Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET(R) Power MOSFET D G Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V V GS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free S VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited) 60V 5.4m: 6.8m: 99A 50A c D S S D G G D-Pak I-Pak IRLR3636PbF IRLU3636PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS Parameter Max. Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) 99 70 50 396 143 0.95 16 22 d Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds f dv/dt TJ TSTG Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy d Units c c A W W/C V V/ns -55 to + 175 C 300 (1.6mm from case) e 170 d See Fig.14, 15, 22a, 22b mJ A mJ Thermal Resistance Symbol RJC RJA RJA www.irf.com k Parameter Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient j Typ. Max. Units --- --- --- 1.05 50 110 C/W 1 02/06/09 IRLR/U3636PbF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage 60 --- --- --- 1.0 --- --- --- --- RG(int) Internal Gate Resistance --- --- 0.07 5.4 6.6 --- --- --- --- --- 0.6 Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 5mA 6.8 VGS = 10V, ID = 50A m 8.3 VGS = 4.5V, ID = 50A 2.5 V VDS = VGS, ID = 100A VDS = 60V, VGS = 0V 20 A 250 VDS = 60V, VGS = 0V, TJ = 125C VGS = 16V 100 nA -100 VGS = -16V d g g --- Dynamic @ TJ = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units i h Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) 31 --- --- --- --- --- --- --- --- --- --- --- --- --- --- 33 11 15 18 45 216 43 69 3779 332 163 437 636 --- 49 --- --- --- --- --- --- --- --- --- --- --- --- Conditions S VDS = 25V, ID = 50A ID = 50A VDS = 30V nC VGS = 4.5V ID = 50A, VDS =0V, VGS = 4.5V VDD = 39V ID = 50A ns RG = 7.5 VGS = 4.5V VGS = 0V VDS = 50V pF = 1.0MHz VGS = 0V, VDS = 0V to 48V ,See Fig.11 VGS = 0V, VDS = 0V to 48V g g i h Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM d Notes: Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 50A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.136 mH RG = 25, IAS = 50A, VGS =10V. Part not recommended for use above this value . ISD 50A, di/dt 1109 A/s, VDD V(BR)DSS, TJ 175C. 2 Min. Typ. Max. Units --- --- --- --- 99 c 396 Conditions MOSFET symbol A showing the integral reverse D G S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 50A, VGS = 0V TJ = 25C VR = 51V, --- 27 --- ns T = 125C I --- 32 --- J F = 50A di/dt = 100A/s TJ = 25C --- 31 --- nC TJ = 125C --- 43 --- --- 2.1 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) g g Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniquea refer to applocation note # AN- 994 echniques refer to application note #AN-994. R is measured at TJ approximately 90C. www.irf.com IRLR/U3636PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V 10 2.7V 1 100 60s PULSE WIDTH Tj = 25C 1 10 2.7V 10 60s PULSE WIDTH Tj = 175C 1 0.1 0.1 BOTTOM 0.1 100 Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 1000 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) 100 T J = 175C T J = 25C 10 1 VDS = 25V 60s PULSE WIDTH 0.1 ID = 50A VGS = 10V 2.0 1.5 1.0 0.5 2 3 4 5 6 7 T J , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 10000 Ciss 1000 -60 -40 -20 0 20 40 60 80 100120140160180 Coss Crss Fig 4. Normalized On-Resistance vs. Temperature 5.0 ID= 50A 4.5 VGS, Gate-to-Source Voltage (V) 1 C, Capacitance (pF) VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V VDS= 48V VDS= 30V VDS= 12V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 5 10 15 20 25 30 35 40 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRLR/U3636PbF 1000 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) T J = 175C 100 T J = 25C 10 1 100sec 100 LIMITED BY PACKAGE 10 1msec 10msec 1 VGS = 0V 0.1 0.1 0.1 0.4 0.7 1 1.3 1.6 0.1 1.9 Limited By Package ID, Drain Current (A) 90 80 70 60 50 40 30 20 10 0 50 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 110 25 100 80 Id = 5mA 75 70 65 60 55 50 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C ) T C , Case Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage 0.8 EAS , Single Pulse Avalanche Energy (mJ) 800 0.6 Energy (J) 10 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 100 1 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 0.4 0.2 0.0 ID 5.69A 10.64A BOTTOM 50A 700 TOP 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 DC Tc = 25C Tj = 175C Single Pulse 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRLR/U3636PbF Thermal Response ( Z thJC ) C/W 10 1 D = 0.50 0.20 0.10 0.05 0.02 0.01 0.1 J 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 R1 R1 J 1 R2 R2 R3 R3 R4 R4 C 1 2 3 2 Ci= i/Ri Ci i/Ri 0.0001 3 4 4 Ri (C/W) i (sec) 0.02028 0.000011 0.29406 0.000158 0.49179 0.001393 0.24336 0.00725 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 100 0.01 0.05 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 200 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 50A 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRLR/U3636PbF 14 IF = 20A V R = 51V 12 2.5 TJ = 25C TJ = 125C 10 2.0 IRRM (A) VGS(th) , Gate threshold Voltage (V) 3.0 1.5 ID = 100A ID = 250A ID = 1.0mA 1.0 8 6 4 ID = 1.0A 0.5 2 0.0 0 -75 -50 -25 0 25 50 75 100 125 150 175 0 200 T J , Temperature ( C ) 600 800 1000 Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 350 16 IF = 30A V R = 51V 14 TJ = 25C TJ = 125C 250 QRR (A) 10 IF = 20A V R = 51V 300 TJ = 25C TJ = 125C 12 IRRM (A) 400 diF /dt (A/s) 8 6 200 150 100 4 50 2 0 0 0 200 400 600 800 0 1000 200 400 600 800 1000 diF /dt (A/s) diF /dt (A/s) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 350 IF = 30A V R = 51V 300 TJ = 25C TJ = 125C QRR (A) 250 200 150 100 50 0 0 200 400 600 800 1000 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRLR/U3636PbF Driver Gate Drive D.U.T - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG VGS 20V + V - DD IAS A 0.01 tp I AS Fig 22a. Unclamped Inductive Test Circuit RD VDS Fig 22b. Unclamped Inductive Waveforms VDS 90% VGS D.U.T. RG + - VDD V10V GS 10% VGS Pulse Width 1 s Duty Factor 0.1 % td(on) Fig 23a. Switching Time Test Circuit tr t d(off) Fig 23b. Switching Time Waveforms Id Current Regulator Same Type as D.U.T. Vds Vgs 50K 12V tf .2F .3F D.U.T. + V - DS Vgs(th) VGS 3mA IG ID Current Sampling Resistors Fig 24a. Gate Charge Test Circuit www.irf.com Qgs1 Qgs2 Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRLR/U3636PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information (;$03/( 7+,6,6$1,5)5 3$57180%(5 :,7+$66(0%/< ,17(51$7,21$/ /27&2'( ,5)5 $ 5(&7,),(5 $66(0%/('21:: /2*2 ,17+($66(0%/