AD5160BRJ100 - Analog Devices

PRELIMINARY TECHNICAL DATA

a 256-Position SPI Compatible

Digital Potentiometer

Preliminary Technical Data AD5160

FEATURES

• 256-Position

• End-to-End Resistance 5k, 10k, 50k, 100kΩ

• Compact SOT23-8 (2.9 x 3mm) Package

• SPI Compatible Interface

• Power ON Reset to Midscale

• Single Supply +2.7V to +5.5V

• Low Temperature Coefficient 35ppm/°C

• Low power, IDD=5µA

• Wide Operating Temperature –40°C to +125°C

Applications

• Mechanical Potentiometer Replacement in new

designs

• Transducer Adjustment of pressure,

temperature, position, chemical and optical

sensors

• RF Amplifier biasing

• Automotive Electronics Adjustment

• Gain Control and Offset Adjustment

GENERAL DESCRIPTION

The AD5160 provides a compact 2.9x3mm packaged

solution for 256-position adjustment applications.

This device performs the same electronic adjustment

function as a mechanical potentiometer or a variable

resistor. Available in four different end-to-end

resistance values (5k, 10k, 50k, 100kΩ) these low

temperature coefficient devices are ideal for high

accuracy and stability variable resistance

adjustments.

The wiper settings are controllable through the SPI

compatible digital interface. The resistance between

the wiper and either end point of the fixed resistor

varies linearly with respect to the digital code

transferred into the RDAC latch1.

Operating from a 2.7 to 5.5 volt power supply

consuming less than 5µA allows for usage in portable

battery operated applications.

Notes:

1. The terms digital potentiometers, VR, and RDAC are used

interchangeably.

FUNCTIONAL DIAGRAM

SPI INTERFACE

WIPER

VDD

CLK

SDI

GND

PIN CONFIGURATION

BVDD

SDICLK

GND

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responsibility is assumed by Analog Devices for its use; nor for any infringements of patents

or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2003

PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

AD5160 ELECTRICAL CHARACTERISTICS 5K, 10K, 50K, 100KΩ VERSION (VDD = +5V ± 10%, or

+3V ± 10%, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)

Parameter Symbol Conditions Min Typ1 Max Units

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect -1 ±0.25 +1 LSB

Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect -2 ±0.5 +2 LSB

Nominal Resistor Tolerance3 ∆RAB T

A = 25°C -30 30 %

Resistance Temperature Coefficient RAB/∆T VAB = VDD, Wiper = No Connect 35 ppm/°C

Wiper Resistance RW V

DD = +5V 50 100 Ω

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution N 8 Bits

Differential Nonlinearity4 DNL –1 ±1/4 +1 LSB

Integral Nonlinearity4 INL –2 ±1/2 +2 LSB

Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H 5 ppm/°C

Full-Scale Error VWFSE Code = FFH –1.5 -0.5 +0 LSB

Zero-Scale Error VWZSE Code = 00H 0 +0.5 +1.5 LSB

RESISTOR TERMINALS

Voltage Range5 V

A,B,W V

SS V

DD V

Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 80H 45 pF

Capacitance6 W CW f = 1 MHz, measured to GND, Code = 80H 60 pF

Shutdown Supply Current7 I

DD_SD VDD = 5.5V 0.01 5 µA

Common-Mode Leakage ICM V

A =VB = VDD / 2 1 nA

DIGITAL INPUTS & OUTPUTS

Input Logic High VIH 2.4 V

Input Logic Low VIL 0.8 V

Input Logic High VIH V

DD = +3V 2.1 V

Input Logic Low VIL V

DD = +3V 0.6 V

Input Current IIL V

IN = 0V or +5V ±1 µA

Input Capacitance6 C

IL 5 pF

POWER SUPPLIES

Logic Supply VLOGIC 2.7 5.5 V

Power Supply Range VDD RANGE V

SS = 0V -0.3 5.5 V

Supply Current IDD V

IH = +5V or VIL = 0V 5 µA

Power Dissipation8 P

DISS V

IH = +5V or VIL = 0V, VDD = +5V 0.2 mW

Power Supply Sensitivity PSS ∆VDD = +5V ±10%, Code = Midscale -0.01 0.001 +0.01 %/%

DYNAMIC CHARACTERISTICS6, 9

Bandwidth –3dB BW_10K RAB = 10KΩ, Code = 80H 600 KHz

Bandwidth –3dB BW_50K RAB = 50KΩ, Code = 80H 100 KHz

Total Harmonic Distortion THDW V

A =1Vrms, VB = 0V, f=1KHz, RAB = 10KΩ 0.003 %

VW Settling Time (10KΩ/50KΩ) tS V

A= 5V, VB=0V, ±1 LSB error band 2/9 µs

Resistor Noise Voltage Density eN_WB R

WB = 5KΩ, RS = 0 9 nV√Hz

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PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

AD5160 ELECTRICAL CHARACTERISTICS 5K, 10K, 50K, 100KΩ VERSION (VDD = +5V ± 10%, or

+3V ± 10%, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)

Parameter Symbol Conditions Min Typ1 Max Units

INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,10)

Input Clock Pulse Width tCH,tCL Clock level high or low 20 ns

Data Setup Time tDS 5 ns

Data Hold Time tDH 5 ns

CS Setup Time tCSS 15 ns

CS High Pulse Width tCSW 40 ns

CLK Fall to CS Fall Hold Time tCSH0 0 ns

CLK Fall to CS Rise Hold Time tCSH 0 ns

CS Rise to Clock Rise Setup tCS1 10 ns

NOTES:

1. Typicals represent average readings at +25°C and VDD = +5V.

2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the

relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3. VAB = VDD, Wiper (VW) = No connect

4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

5. Resistor terminals A,B,W have no limitations on polarity with respect to each other.

6. Guaranteed by design and not subject to production test.

7. Measured at the A terminal. A terminal is open circuited in shutdown mode.

8. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation

9. All dynamic characteristics use VDD = +5V.

10. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics

are measured using VLOGIC = +5V.

11. The AD5160 contains 2532 transistors. Die Size: 30.7mil x 76.8 mil, 2358sq. mil.

12. See timing diagram for location of measured values.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD5160 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

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PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

ABSOLUTE MAXIMUM RATINGS1 (TA = +25°C, unless

otherwise noted)

VDD to GND ...................................................... -0.3, +7V

VA, VB, VW to GND ................................................... VDD

IMAX ..................................................................... ±20mA2

Digital Inputs & Output Voltage to GND.............. 0V, +7V

Operating Temperature Range ..............-40°C to +125°C

Maximum Junction Temperature (TJ MAX)..............+150°C

Storage Temperature.............................-65°C to +150°C

Lead Temperature (Soldering, 10 sec) ................+300°C

Thermal Resistance3 θJA,

SOT23-8 ................................................ 230°C/W

NOTES

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating; functional operation of the device at these or

any other conditions above those listed in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

2. Maximum terminal current is bounded by the maximum current handling of the switches,

maximum power dissipation of the package, and maximum applied voltage across any two of

the A, B, and W terminals at a given resistance

3. Package Power Dissipation (TJMAX-TA)/ θJA

ORDERING GUIDE

Model# RAB

(Ω)

Package

Description

Package

Option

Brand

AD5160BRJ5 5K SOT23-8 RJ-8 D08

AD5160BRJ10 10K SOT23-8 RJ-8 D09

AD5160BRJ50 50K SOT23-8 RJ-8 D0A

AD5160BRJ100 100K SOT23-8 RJ-8 D0B

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PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

TABLE 1: AD5160 Serial-Data Word Format

B7 B6 B5 B4 B3 B2 B1 B0

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

27 2

D7 D6 D5 D4 D3 D2 D1 D0SDI

CLK

VOUT

DAC REGISTER LOAD

Figure 1A. AD5160 Timing Diagram(VA = 5V, VB = 0V, VW =

VOUT)

tCSH0

tCSS

tCH

tCL

tDS tDH

tCSH1

tCS W

±1 LSB

SDI

(Data In) 0

VDD

CLK

VOUT

Dx Dx

tCS 1

Figure 1B. Detail Timing Diagram(VA = 5V, VB = 0V, VW = VOUT)

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PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

TABLE 2: AD5160 PIN Descriptions

Pin Name Description

1 VW W Terminal

2 VDD Positive Power Supply

3 GND Ground

4 CLK Serial Clock Input, positive edge

triggered

5 SDI Serial Data Input

6 CS Chip Select Input, Active Low. When

CS returns high, data will be loaded

into the DAC register.

7 VB B Terminal

8 VA A Terminal

PIN CONFIGURATION

BVDD

SDICLK

GND

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PRELIMINARY TECHNICAL DATA

256 Position Digital Potentiometer AD5160

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