CMOS Single-Supply, Rail-to-Rail Input/Output
Operational Amplifiers with Shutdown
AD8591/AD8592/AD8594
Rev. B
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FEATURES
Single-supply operation: 2.5 V to 6 V
High output current: ±250 mA
Extremely low shutdown supply current: 100 nA
Low supply current: 750 μA/Amp
Wide bandwidth: 3 MHz
Slew rate: 5 V/μs
No phase reversal
Very low input bias current
High impedance outputs when in shutdown mode
Unity-gain stable
APPLICATIONS
Mobile communication handset audio
PC audio
PCMCIA/modem line driving
Battery-powered instrumentation
Data acquisition
ASIC input or output amplifiers
LCD display reference level drivers
GENERAL DESCRIPTION
The AD8591, AD8592, and AD8594 are single, dual, and quad
rail-to-rail, input and output single-supply amplifiers featuring
250 mA output drive current and a power saving shutdown mode.
The AD8592 includes an independent shutdown function for
each amplifier. When both amplifiers are in shutdown mode,
the total supply current is reduced to less than 1 μA. The AD8591
and AD8594 include a single master shutdown function that
reduces the total supply current to less than 1 μA. All amplifier
outputs are in a high impedance state when in shutdown mode.
These amplifiers have very low input bias currents, making them
suitable for integrators and diode amplification. Outputs are stable
with virtually any capacitive load. Supply current is less than
750 μA per amplifier in active mode.
Applications for these amplifiers include audio amplification for
portable computers, portable phone headsets, sound ports, sound
cards, and set-top boxes. The AD859x family is capable of driving
heavy capacitive loads, such as LCD panel reference levels.
The ability to swing rail to rail at both the input and output enables
designers to buffer CMOS DACs, ASICs, and other wide output
swing devices in single-supply systems.
PIN CONFIGURATIONS
O
UT A
1
V–
2
+IN A
3
V+
6
SD
5
–IN A
4
AD
8591
TOP VIEW
(Not to Scale)
0
1106-001
Figure 1. 6-Lead SOT-23 (RJ Suffix)
SDB
V– +IN B
OUT A
–IN A
+IN A
V+
OUT B
–IN B
SDA
1
2
3
4
5
10
9
8
7
6
AD
8592
TOP VIEW
(Not to Scale)
0
1106-002
Figure 2. 10-Lead MSOP (RM Suffix)
OUT A
–IN A
V+
+IN A
+IN B
–IN B
OUT B
NC
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
SD
1
2
3
4
16
15
14
13
512
611
710
8 9
NC = NO CONNECT
AD
8594
TOP VIEW
(Not to Scale)
01106-003
Figure 3. 16-Lead Narrow SOIC (R Suffix)
OUT A
–IN A
V+
+IN A
+IN B
–IN B
OUT B
NC
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
SD
NC = NO CONNECT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD
8594
TOP VIEW
(Not to Scale)
01106-004
Figure 4. 16-Lead TSSOP (RU Suffix)
The AD8591, AD8592, and AD8594 are specified over the
industrial temperature range (−40°C to +85°C). The AD8591,
single, is available in the tiny 6-lead SOT-23 package. The AD8592,
dual, is available in the 10-lead surface-mount MSOP package. The
AD8594, quad, is available in 16-lead narrow SOIC and 16-lead
TSSOP packages.
AD8591/AD8592/AD8594
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Input Voltage Protection............................................................ 11
Output Phase Reversal ............................................................... 11
Output Short-Circuit Protection .............................................. 11
Power Dissipation....................................................................... 11
Capacitive Loading ..................................................................... 12
PC98-Compliant Headphone/Speaker Amplifier .................. 12
A Combined Microphone and Speaker Amplifier for
Cellphone and Portable Headsets ............................................ 13
An Inexpensive Sample-and-Hold Circuit ............................. 13
Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface) ........................................................ 14
Single-Supply Differential Line Driver .................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/09—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Deleted Spice Model for AD8591/AD8592/AD8594 Amplifiers
Sections ............................................................................................ 12
Changes to PC98-Compliant Headphone/Speaker Amplifier
Section and Figure 38 ..................................................................... 12
Changes to Figure 39 ...................................................................... 13
Changes to Figure 42 and Figure 43 ............................................. 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
AD8591/AD8592/AD8594
Rev. B | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 25 mV
−40°C < TA < +85°C 30 mV
Input Bias Current IB 5 50 pA
−40°C < TA < +85°C 60 pA
Input Offset Current IOS 1 25 pA
−40°C < TA < +85°C 30 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 38 45 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = 0.3 V to 2.4 V 25 V/mV
Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +85°C 20 μV/°C
Bias Current Drift ΔIB/ΔT −40°C < TA < +85°C 50 fA/°C
Offset Current Drift ΔIOS/ΔT −40°C < TA < +85°C 20 fA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
L = 10 mA 2.55 2.61 V
−40°C to +85°C 2.5 V
Output Voltage Low VOL I
L = 10 mA 60 100 mV
−40°C to +85°C 125 mV
Output Current IOUT ±250 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 60 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.5 V to 6 V 45 55 dB
Supply Current per Amplifier ISY V
O = 0 V 1 mA
−40°C < TA < +85°C 1.25 mA
Supply Current Shutdown Mode ISD All amplifiers shut down 0.1 1 μA
−40°C < TA < +85°C 1 μA
I
SD1 Amplifier 1 shut down (AD8592) 1.4 mA
I
SD2 Amplifier 2 shut down (AD8592) 1.4 mA
SHUTDOWN INPUTS
Logic High Voltage VINH −40°C < TA < +85°C 1.6 V
Logic Low Voltage VINL −40°C < TA < +85°C 0.5 V
Logic Input Current IIN −40°C < TA < +85°C 1 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 3.5 V/μs
Settling Time tS To 0.01% 1.4 μs
Gain Bandwidth Product GBP 2.2 MHz
Phase Margin Φo 67 Degrees
Channel Separation CS f = 1 kHz, RL = 2 kΩ 65 dB
NOISE PERFORMANCE
Voltage Noise Density en f = 1 kHz 45 nV/√Hz
f = 10 kHz 30 nV/√Hz
Current Noise Density in f = 1 kHz 0.05 pA/√Hz
AD8591/AD8592/AD8594
Rev. B | Page 4 of 16
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 2 25 mV
−40°C < TA < +85°C 30 mV
Input Bias Current IB 5 50 pA
−40°C < TA < +85°C 60 pA
Input Offset Current IOS 1 25 pA
−40°C < TA < +85°C 30 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 38 47 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = 0.5 V to 4.5 V 15 30 V/mV
Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +85°C 20 μV/°C
Bias Current Drift ΔIB/ΔT −40°C < TA < +85°C 50 fA/°C
Offset Current Drift ΔIOS/ΔT −40°C < TA < +85°C 20 fA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
L = 10 mA 4.9 4.94 V
−40°C to +85°C 4.85 V
Output Voltage Low VOL I
L = 10 mA 50 100 mV
−40°C to +85°C 125 mV
Output Current IOUT ±250 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 40 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.5 V to 6 V 45 55 dB
Supply Current per Amplifier ISY V
O = 0 V 1.25 mA
−40°C < TA < +85°C 1.75 mA
Supply Current Shutdown Mode ISD All amplifiers shut down 0.1 1 μA
−40°C < TA < +85°C 1 μA
I
SD1 Amplifier 1 shut down (AD8592) 1.6 mA
I
SD2 Amplifier 2 shut down (AD8592) 1.6 mA
SHUTDOWN INPUTS
Logic High Voltage VINH −40°C < TA < +85°C 2.4 V
Logic Low Voltage VINL −40°C < TA < +85°C 0.8 V
Logic Input Current IIN −40°C < TA < +85°C 1 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 5 V/μs
Full Power Bandwidth BWP 1% distortion 325 kHz
Settling Time tS To 0.01% 1.6 μs
Gain Bandwidth Product GBP 3 MHz
Phase Margin Φo 70 Degrees
Channel Separation CS f = 1 kHz, RL = 10 kΩ 65 dB
NOISE PERFORMANCE
Voltage Noise Density en f = 1 kHz 45 nV/√Hz
f = 10 kHz 30 nV/√Hz
Current Noise Density in f = 1 kHz 0.05 pA/√Hz
AD8591/AD8592/AD8594
Rev. B | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage GND to VS
Differential Input Voltage ±6 V
Output Short-Circuit Duration to GND1 Observe Derating Curves
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θJA θJC Unit
6-Lead SOT-23 (RJ) 230 92 °C/W
10-Lead MSOP (RM) 200 44 °C/W
16-Lead SOIC (R) 120 36 °C/W
16-Lead TSSOP (RU) 180 35 °C/W
1 For supplies less than ±5 V, the differential input voltage is limited to the
supplies. ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD8591/AD8592/AD8594
Rev. B | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
10
0.1
1
100
1k
1k0.01 0.1 1 10 100
LOAD CURRENT (mA)
ΔOUTPUT VOLTAGE (mV)
V
S
= 2.7V
T
A
= 25°C
SOURCE
SINK
01106-005
Figure 5. Output Voltage to Supply Rail vs. Load Current
10
0.1
1
100
10k
1k
1k0.01 0.1 1 10 100
LOAD CURRENT (mA)
ΔOUTPUT VOLTAGE (mV)
VS = 5V
TA = 25°C
SOURCE SINK
0
1106-006
Figure 6. Output Voltage to Supply Rail vs. Load Current
–40 –20 1000 20406080
0.90
0.50
0.85
0.70
0.65
0.60
0.55
0.80
0.75
VS = 5V
VS = 2.7V
TEMPERATURE (°C)
SUPPLY CURRENT/AMPLIFIER (mA)
01106-007
Figure 7. Supply Current per Amplifier vs. Temperature
0.8
0.7
0
0.4
0.3
0.2
0.1
0.6
0.5
T
A
= 25°C
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT/AMPLIFIER (mA)
0.75 1.25 1.75 2.25 2.75 3.00
01106-008
Figure 8. Supply Current per Amplifier vs. Supply Voltage
–
2
–8
–50 –35 85
5
–3
–4
–5
–6
–7
–15
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)
25 45 65
V
S
= 5V
V
CM
= 2.5V
01106-009
Figure 9. Input Offset Voltage vs. Temperature
8
2
7
6
5
4
3
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
–50 –35 855–15 25 45 65
V
S
= 2.7V, 5V
V
CM
= V
S
/2
01106-010
Figure 10. Input Bias Current vs. Temperature
AD8591/AD8592/AD8594
Rev. B | Page 7 of 16
4
–2
3
2
1
0
–1
TEMPERATURE (°C)
INPUT OFFSET CURRENT (pA)
–50 –35 855–15 25 45 65
V
S
= 2.7V, 5V
V
CM
= V
S
/2
01106-011
Figure 11. Input Offset Current vs. Temperature
510 234
8
7
1
5
4
3
2
6
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
V
S
= 5V
T
A
= 25°C
0
1106-012
Figure 12. Input Bias Current vs. Common-Mode Voltage
80
60
40
0
20
45
90
135
180
PHASE SHIFT (Degrees)
FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k 1M 10M 100M
V
S
= 2.7V
R
L
= NO LOAD
T
A
= 25°C
01106-013
Figure 13. Open-Loop Gain and Phase vs. Frequency
80
60
40
0
20
45
90
135
180
PHASE SHIFT (Degrees)
FREQUENCY (Hz)
GAIN (dB)
1k 10k 100k 1M 10M 100M
V
S
= 5V
R
L
= NO LOAD
T
A
= 25°C
01106-014
Figure 14. Open-Loop Gain and Phase vs. Frequency
5
4
0
3
2
1
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
1k 10k 100k 1M 10M
V
S
= 2.7V
R
L
= 2kΩ
T
A
= 25°C
V
IN
= 2.5V p-p
01106-016
Figure 15. Closed-Loop Output Voltage Swing vs. Frequency
5
4
0
3
2
1
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
1k 10k 100k 1M 10M
V
S
= 5V
R
L
= 2kΩ
T
A
= 25°C
V
IN
= 2.5V p-p
01106-017
Figure 16. Closed-Loop Output Voltage Swing vs. Frequency
AD8591/AD8592/AD8594
Rev. B | Page 8 of 16
80
60
40
0
20
100
120
140
160
180
200
FREQUENCY (Hz)
IMPEDANCE (
Ω)
1k 10k 100k 1M 10M 100M
AV = 10
AV = 1
VS = 5V
TA = 25°C
01106-018
Figure 17. Closed-Loop Output Impedance vs. Frequency
110
90
50
80
70
60
100
FREQUENCY (Hz)
CMRR (dB)
1k 10k 100k 1M 10M
V
S
= 5V
T
A
= 25°C
01106-019
Figure 18. Common-Mode Rejection Ratio vs. Frequency
80
60
40
0
20
100
120
140
–20
–40
–60
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M 10M
V
S
= 2.5V
T
A
= 25°C
+PSRR
–PSRR
01106-020
Figure 19. Power Supply Rejection Ratio vs. Frequency
80
60
40
0
20
100
120
140
–20
–40
–60
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M 10M
V
S
= 5V
T
A
= 25°C
+PSRR
–PSRR
01106-021
Figure 20. Power Supply Rejection Ratio vs. Frequency
60
50
0
30
20
10
40
CAPACITANCE (pF)
SMALL SIGNAL OVERSHOOT (%)
10 100 1k 10k
V
S
= 2.5V
R
L
= 2kΩ
T
A
= 25°C
+OS
–OS
01106-022
Figure 21. Small Signal Overshoot vs. Load Capacitance
60
50
0
30
20
10
40
CAPACITANCE (pF)
SMALL SIGNAL OVERSHOOT (%)
10 100 1k 10k
VS = 5V
RL = 2kΩ
TA = 25°C
+OS
–OS
01106-023
Figure 22. Small Signal Overshoot vs. Load Capacitance
AD8591/AD8592/AD8594
Rev. B | Page 9 of 16
500 ns/DIV
20mV/DI
V
0V
V
S
= ±1.35V
V
IN
= ±50mV
A
V
= +1
R
L
= 2kΩ
C
L
= 300pF
T
A
= 25°C
01106-024
Figure 23. Small Signal Transient Response
500 ns/DIV
20mV/DI
V
0V V
S
= ±2.5V
V
IN
= ±50mV
A
V
= +1
R
L
= 2kΩ
C
L
= 300pF
T
A
= 25°C
01106-025
Figure 24. Small Signal Transient Response
01106-026
10
500mV 500ns
100
0
90
V
S
= ±1.35V
A
V
= +1
R
L
= 2kΩ
T
A
= 25°C
Figure 25. Large Signal Transient Response
01106-027
10
500mV 500ns
100
0
90
V
S
= ±2.5V
A
V
= +1
R
L
= 2kΩ
T
A
= 25°C
Figure 26. Large Signal Transient Response
01106-028
10
1V
10µs1V
100
0
90
V
S
= ±2.5V
A
V
= +1
T
A
= +25°C
Figure 27. No Phase Reversal
1
0.1
0.01
FREQUENCY (Hz)
CURRENT NOISE DENSITY (pA/
√Hz)
10 100 1k 10k 100k
V
S
= 5V
T
A
= 25°C
01106-029
Figure 28. Current Noise Density vs. Frequency
AD8591/AD8592/AD8594
Rev. B | Page 10 of 16
100µV/DIV
MARKER 41µV/√Hz
01106-030
10
100
0
90
V
S
= 5V
A
V
= +1000
T
A
= 25°C
FREQUENCY = 1kHz
Figure 29. Voltage Noise Density vs. Frequency
200µV/DI
V
MARKER 25.9
µV/√Hz
01106-031
10
100
0
90
V
S
= 5V
A
V
= +1000
T
A
= 25°C
FREQUENCY = 10kHz
Figure 30. Voltage Noise Density vs. Frequency
300
500
600
400
200
100
–12–14 6–10
V
S
= 2.7V
V
CM
= 1.35V
T
A
= 25°C
0
INPUT OFFSET VOLTAGE (mV)
QUANTITY (Amplifiers)
–8 –6 –4 –2 0 2 4
01106-032
Figure 31. Input Offset Voltage Distribution
300
500
600
400
200
100
–12–14 6–10
V
S
= 5V
V
CM
= 2.5V
T
A
= 25°C
0
INPUT OFFSET VOLTAGE (mV)
QUANTITY (Amplifiers)
–8 –6 –4 –2 0 2 4
0
1106-033
Figure 32. Input Offset Voltage Distribution
AD8591/AD8592/AD8594
Rev. B | Page 11 of 16
THEORY OF OPERATION
The AD859x amplifiers are CMOS, high output drive, rail-to-
rail input and output single-supply amplifiers designed for low
cost and high output current drive. The parts include a power
saving shutdown function that makes the AD8591/AD8592/
AD8594 op amps ideal for portable multimedia and
telecommunications applications.
Figure 33 shows the simplified schematic for the AD8591/AD8592/
AD8594 amplifiers. Two input differential pairs, consisting of
an n-channel pair (M1, M2) and a p-channel pair (M3, M4),
provide a rail-to-rail input common-mode range. The outputs of
the input differential pairs are combined in a compound folded-
cascode stage that drives the input to a second differential pair
gain stage. The outputs of the second gain stage provide the gate
voltage drive to the rail-to-rail output stage.
The rail-to-rail output stage consists of M15 and M16, which
are configured in a complementary common source configuration.
As with any rail-to-rail output amplifier, the gain of the output
stage, and thus the open-loop gain of the amplifier, is dependent
on the load resistance. In addition, the maximum output voltage
swing is directly proportional to the load current. The difference
between the maximum output voltage to the supply rails, known as
the dropout voltage, is determined by the on-channel resistance
of the AD8591/AD8592/AD8594 output transistors. The output
dropout voltage is given in Figure 5 and Figure 6.
50µA 100µA
100µA
20µA
V
B2
M5
M8
M12
M15
M16
M11
OUT
M3 M4
M1
IN–
IN+ V
B3
M6
M7 M10
20µA
M13
50µA
V
+
V–
M9 M14
M2
*
*
**
M337
SD
INV
*
*
M340
*ALL CURRENT SOURCES GO TO 0µA IN SHUTDOWN MODE.
INV
M31
M30
01106-034
Figure 33. Simplified Schematic
INPUT VOLTAGE PROTECTION
Although not shown in the simplified schematic, ESD protection
diodes are connected from each input to each power supply rail.
These diodes are normally reverse-biased, but turn on if either
input voltage exceeds either supply rail by more than 0.6 V. If this
condition occurs, limit the input current to less than ±5 mA.
This is done by placing a resistor in series with the input(s).
The minimum resistor value should be
mA5
,MAXIN
IN
V
R≥ (1)
OUTPUT PHASE REVERSAL
The AD8591/AD8592/AD8594 are immune to output voltage
phase reversal with an input voltage within the supply voltages
of the device. However, if either of the inputs of the device exceeds
0.6 V outside of the supply rails, the output could exhibit phase
reversal. This is due to the ESD protection diodes becoming
forward-biased, thus causing the polarity of the input terminals
of the device to switch.
The technique recommended in the Input Voltage Protection
section should be applied in applications where the possibility
of input voltages exceeding the supply voltages exists.
OUTPUT SHORT-CIRCUIT PROTECTION
To achieve high output current drive and rail-to-rail performance,
the outputs of the AD859x family do not have internal short-
circuit protection circuitry. Although these amplifiers are
designed to sink or source as much as 250 mA of output current,
shorting the output directly to the positive supply could damage or
destroy the device. To protect the output stage, limit the maximum
output current to ±250 mA.
By placing a resistor in series with the output of the amplifier,
as shown in Figure 34, the output current can be limited. The
minimum value for RX is
mA250
SY
X
V
R≥ (2)
For a 5 V single-supply application, RX should be at least 20 Ω.
Because RX is inside the feedback loop, VOUT is not affected. The
trade-off in using RX is a slight reduction in output voltage
swing under heavy output current loads. RX also increases the
effective output impedance of the amplifier to RO + RX, where RO
is the output impedance of the device.
R
X
20ΩV
OUT
AD8592
+5
V
V
IN
01106-035
Figure 34. Output Short-Circuit Protection
POWER DISSIPATION
Although the AD859x amplifiers are able to provide load
currents of up to 250 mA, proper attention should be given to
not exceeding the maximum junction temperature for the device.
The junction temperature equation is
TJ = PDISS × θJA + TA (3)
where:
TJ is the AD859x junction temperature.
PDISS is the AD859x power dissipation.
θJA is the AD859x junction-to-ambient thermal resistance of the
package.
TA is the ambient temperature of the circuit.
AD8591/AD8592/AD8594
Rev. B | Page 12 of 16
In any application, the absolute maximum junction temperature
must be limited to 150°C. If the junction temperature is exceeded,
the device could suffer premature failure. If the output voltage
and output current are in phase, for example, with a purely resistive
load, the power dissipated by the AD859x can be found as
PDISS = ILOAD × (VSY − VOUT) (4)
where:
ILOAD is the AD859x output load current.
VSY is the AD859x supply voltage.
VOUT is the output voltage.
By calculating the power dissipation of the device and using the
thermal resistance value for a given package type, the maximum
allowable ambient temperature for an application can be found
using Equation 3.
CAPACITIVE LOADING
The AD859x exhibits excellent capacitive load driving capabilities
and can drive to 10 nF directly. Although the device is stable
with large capacitive loads, there is a decrease in amplifier
bandwidth as the capacitive load increases. Figure 35 shows
a graph of the AD8592 unity-gain bandwidth under various
capacitive loads.
4.0
3.5
0
0.01 0.1 110
2.0
1.5
1.0
0.5
3.0
2.5
V
S
= ±2.5V
R
L
= 1kΩ
T
A
= 25°C
100
CAPACITIVE LOAD (nF)
BANDWIDTH (MHz)
01106-036
Figure 35. Unity-Gain Bandwidth vs. Capacitive Load
When driving heavy capacitive loads directly from the AD859x
output, a snubber network can be used to improve the transient
response. This network consists of a series RC connected from
the output of the amplifier to ground, placing it in parallel with
the capacitive load. The configuration is shown in Figure 36.
Although this network does not increase the bandwidth of the
amplifier, it significantly reduces the amount of overshoot, as
shown in Figure 37.
R
S
5Ω
V
OUT
AD8592
+5V
V
IN
100mV p-p
C
S
1µF
C
L
47nF
01106-037
Figure 36. Configuration for Snubber Network to Compensate for Capacitive Loads
4
7nF LOAD
ONLY
SNUBBER
IN CIRCUIT
01106-038
50mV
50mV 10µs
Figure 37. Snubber Network Reduces Overshoot and Ringing
Caused by Driving Heavy Capacitive Loads
The optimum values for the snubber network should be
determined empirically based on the size of the capacitive load.
Table 5 shows a few sample snubber network values for a given
load capacitance.
Table 5. Snubber Networks for Large Capacitive Loads
Load Capacitance, CL (nF)
Snubber Network
RS (Ω) CS (μF)
0.47 300 0.1
4.7 30 1
47 5 1
PC98-COMPLIANT HEADPHONE/SPEAKER
AMPLIFIER
Because of its high output current performance and shutdown
feature, the AD8592 makes an excellent amplifier for driving an
audio output jack in a computer application. Figure 38 shows
how the AD8592 can be interfaced with an AC’97 codec to
drive headphones or speakers.
U1-A
4
C1
100µF
+5V
1
10
2
3
5
+5
V
AD1881A*
(AC’97)
R4
20Ω
+5V
R1
100kΩ
7
8
6
9
R5
20Ω
C2
100µF
*ADDITIONAL PINS OMITTED FOR CLARITY.
U1-B
U1 = AD8592
NC
R2
2kΩ
R3
2kΩ
AV
DD1
AV
DD2
LINE_OUT_
LINE_OUT_L
AV
SS1
25
38
35
36
26
01106-039
Figure 38. PC98-Compliant Headphone/Line Out Amplifier
AD8591/AD8592/AD8594
Rev. B | Page 13 of 16
When headphones are plugged into the jack, the normalizing
contacts disconnect from the audio contacts. This allows the
voltage to the AD8592 shutdown pins to be pulled to 5 V,
activating the amplifiers. With no plug in the output jack, the
shutdown voltage is pulled to 100 mV through the R1 and R3 + R5
voltage divider. This powers the AD8592 down when it is not
needed, saving current from the power supply or battery.
If gain is required from the output amplifier, add four additional
resistors, as shown in Figure 39. The gain of the AD8592 can
be set as
6
7
R
R
AV= (5)
A
V
= = 6dB WITH VALUES SHOWN
R7
R6
U1-A
4
C1
100µF
+5V
1
10
2
3
5
+5
V
AV
DD1
AV
DD2
LINE_OUT_L
AD1881A*
(AC’97)
LINE_OUT_
R
AV
SS1
R4
20Ω
+5V
R1
100kΩ
7
8
6
9
R5
20Ω
R6
10kΩ
R7
10kΩ
R7
10kΩ
R6
10kΩ
C2
100µF
*ADDITIONAL PINS OMITTED FOR CLARITY.
U1-B
U1 = AD8592
NC
R2
2kΩ
R3
2kΩ
25
38
35
36
VREF
27
26
01106-040
Figure 39. PC98-Compliant Headphone/Line Out Amplifier with Gain
Input coupling capacitors are not required for either circuit
because the reference voltage is supplied from the AD1881A.
R4 and R5 help protect the AD8592 output in case the output
jack or headphone wires accidentally are shorted to ground. The
output coupling capacitors, C1 and C2, block dc current from the
headphones and create a high-pass filter with a corner frequency of
()
L
dB RRC
f+π
=
−412
1
3 (6)
where RL is the resistance of the headphones.
A COMBINED MICROPHONE AND SPEAKER
AMPLIFIER FOR CELLPHONE AND PORTABLE
HEADSETS
The dual amplifiers in the AD8592 make an efficient design for
interfacing with a headset containing a microphone and speaker.
Figure 40 demonstrates a simple method for constructing an
interface to a codec.
U1-A
4
+5V
1
10
2
3
5
C2
10µF
U1 = AD8592
7
8
6
9U1-B FROM CODEC
MONO OUT
(OR LEFT OUT)
TO
CODEC
V
REF
FROM CODEC
MICROPHONE
A
ND SPEAKER
JACK
R1
2.2kΩ
+5V
+5V
C1
0.1µF
NC
(RIGHT OUT)
R2
10kΩ
R3
100kΩ
R8
100kΩ
R5
10kΩR6
10kΩ
(OPTIONAL)
R4
10kΩ
R7
1kΩ
01106-041
Figure 40. Speaker/Microphone Headset Amplifier Circuit
U1-A is used as a microphone preamplifier, where the gain of
the preamplifier is set as R3/R2. R1 is used to bias an electret
microphone, and C1 blocks any dc voltages from the amplifier.
U1-B is the speaker amplifier, and its gain is set at R5/R4. To
sum a stereo output, add R6, equal in value to R4.
Using the same principle described in the PC98-Compliant
Headphone/Speaker Amplifier section, the normalizing contact
on the microphone/speaker jack can be used to put the AD8592
into shutdown when the headset is not plugged in. The AD8592
shutdown inputs can also be controlled with TTL- or CMOS-
compatible logic, allowing microphone or speaker muting, if
desired.
AN INEXPENSIVE SAMPLE-AND-HOLD CIRCUIT
The independent shutdown control of each amplifier in the
AD8592 allows a degree of flexibility in circuit design. One
particular application for which this feature is useful is in
designing a sample-and-hold circuit for data acquisition. Figure 41
shows a schematic of a simple, yet extremely effective, sample-
and-hold circuit using a single AD8592 and one capacitor.
V
IN
U1-A
C1
1nF
U1-B
SAMPLE
AND HOLD
OUTPUT
+5V
1
2
35
9
8
76
SAMPLE
CLOCK
U1 = AD8592
+5V
4
10
0
1106-042
Figure 41. An Efficient Sample-and-Hold Circuit
AD8591/AD8592/AD8594
Rev. B | Page 14 of 16
The U1-A amplifier is configured as a unity-gain buffer driving
a 1 nF capacitor. The input signal is connected to the noninverting
input, and the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows VIN. When the sample clock goes
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
SINGLE-SUPPLY DIFFERENTIAL LINE DRIVER
Figure 43 shows a single-supply differential line driver circuit
that can drive a 600 Ω load with less than 0.7% distortion from
20 Hz to 15 kHz with an input signal of 4 V p-p and a single 5 V
supply. The design uses an AD8594 to mimic the performance
of a fully balanced transformer-based solution. However, this
design occupies much less board space, while maintaining low
distortion, and can operate down to dc. Like the transformer-based
design, either output can be shorted to ground for unbalanced
line driver applications without changing the circuit gain of 1.
The U1-B amplifier is used as a unity-gain buffer to prevent
loading on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is little voltage droop from C1 during
the hold period. This circuit can be used with sample frequencies as
high as 500 kHz and as low as 1 Hz. By increasing the C1 value,
lower voltage droop is achieved for very low sample rates.
R
L
600Ω
C1
22µF
A2 9
8
7
3
1
2
A1
+5V
R1
10kΩ
R2
10kΩ
R11
10kΩ
R7
10kΩ
8
7
A1
+5V
+5V
R8
100kΩ
R9
100kΩ
C2
1µF
R12
10kΩ
R14
50Ω
A2 1
2
3
R
3
10kΩ
R6
10kΩ
R13
10kΩ
C3
47µF
V
O1
V
O2
C4
47µF
A1, A2 = 1/2 AD8592
GAIN = R3
R2
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
V
IN
R10
10kΩ
R5
50Ω
10
4
10
4
9
0
1106-044
DIRECT ACCESS ARRANGEMENT FOR PCMCIA
MODEMS (TELEPHONE LINE INTERFACE)
Figure 42 illustrates a 5 V transmit/receive telephone line
interface for 600 Ω systems. It allows full duplex transmission
of signals on a transformer-coupled 600 Ω line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the high output current
drive and low dropout voltages of the AD8594, the largest signal
available on a single 5 V supply is approximately 4.5 V p-p into
a 600 Ω transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons. It prevents the transmit
signal from interfering with the receive signal, and it extracts
the receive signal from the transmission line for amplification
by A4. The gain of A4 can be adjusted in the same manner as
the gain of A1 to meet the input signal requirements of the
modem. Standard resistor values permit the use of single
inline package (SIP) format resistor arrays. Couple this with
the 16-lead TSSOP or SOIC footprint of the AD8594, and this
circuit offers a compact, cost-effective solution.
Figure 43. Low Noise, Single-Supply Differential Line Driver
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the dc voltage of the input is equal to half
of the supply voltage.
The circuit can also be configured to provide additional gain, if
desired. The gain of the circuit is
2
3
R
R
V
V
A
IN
OUT
V== (7)
R7
10kΩ
R8
10kΩ
+5V
6.2V
6.2V
TRANSMIT
TxA
RECEIVE
RxA
C1
0.1µF
R1
10kΩ
R2
9.09kΩ
2kΩ
P1
Tx GAIN
ADJUST
A1
A2
A3
A4
A1, A2 = 1/4 AD8594
A3, A4 = 1/4 AD8594
R3
360Ω
1:1
T1
TO TELEPHONE
LINE
1
2
3
7
6
5
11
12
10
15
14
16
R5
10kΩ
R6
10kΩ
R9
10kΩ
R14
14.3kΩ
R10
10kΩ
R11
10kΩ
R12
10kΩ
R13
10kΩ
C2
0.1µF
P2
Rx GAIN
ADJUST
2kΩ
ZO
600Ω
MIDCOM
671-8005
SHUTDOWN
9
9
9
9
10µF
0
1106-043
where:
VOUT = VO1 − VO2
R2 = R7 = R10 = R11
R3 = R6 = R12 = R1
Figure 42. Single-Supply Direct Access Arrangement for PCMCIA Modems
AD8591/AD8592/AD8594
Rev. B | Page 15 of 16
OUTLINE DIMENSIONS
1 3
45
2
6
2.90 BSC
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.22
0.08
10°
4°
0°
0.50
0.30
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.60
0.45
0.30
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 44. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 45. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 46. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
AD8591/AD8592/AD8594
Rev. B | Page 16 of 16
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8591ART-REEL −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A
AD8591ART-REEL7 −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A
AD8591ARTZ-REEL1 −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A#
AD8591ARTZ-REEL71 −40°C to +85°C 6-Lead SOT-23 RJ-6 A9A#
AD8592ARM-REEL −40°C to +85°C 10-Lead MSOP RM-10 AQA
AD8592ARMZ-REEL1 −40°C to +85°C 10-Lead MSOP RM-10 AQA#
AD8594AR −40°C to +85°C 16-Lead SOIC_N R-16
AD8594AR-REEL −40°C to +85°C 16-Lead SOIC_N R-16
AD8594AR-REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
AD8594ARZ1 −40°C to +85°C 16-Lead SOIC_N R-16
AD8594ARZ-REEL1 −40°C to +85°C 16-Lead SOIC_N R-16
AD8594ARZ-REEL71 −40°C to +85°C 16-Lead SOIC_N R-16
AD8594ARU-REEL −40°C to +85°C 16-Lead TSSOP RU-16
AD8594ARUZ-REEL1 −40°C to +85°C 16-Lead TSSOP RU-16
1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01106-0-1/09(B)