A8291SETTR-TB - Allegro MicroSystems, Inc.

Description

Intended for analog and digital satellite receivers, this single

low noise block converter regulator (LNBR) is a monolithic

linear and switching voltage regulator, specifically designed to

provide the power and the interface signals to an LNB down

converter via coaxial cable. The A8291 requires few external

components, with the boost switch and compensation circuitry

integrated inside of the device. A high switching frequency is

chosen to minimize the size of the passive filtering components,

further assisting in cost reduction. The high levels of component

integration ensure extremely low noise and ripple figures.

The A8291 has been designed for high efficiency, utilizing

the Allegro® advanced BCD process. The integrated boost

switch has been optimized to minimize both switching and

static losses. To further enhance efficiency, the voltage drop

across the tracking regulator has been minimized.

The A8291 has integrated tone detection capability, to support

full two-way DiSEqC™ communications. Several schemes

are available for generating tone signals, all the way down

to no-load, and using either the internal clock or an external

8291-DS, Rev.3

Features and Benefits

▪ 2-wire serial I2C™ -compatible interface: control (write) and

status (read)

▪ LNB voltages (16 programmable levels) compatible with

all common standards

▪ Tracking switch-mode power converter for lowest dissipation

▪ Integrated converter switches and current sensing

▪ Provides up to 500 mA load current

▪ Static current limit circuit allows full current at startup and

13→18 V output transition; reliably starts wide load range

▪ Push-pull output stage minimizes 13→18 V and 18→13 V

output transition times for highly capacitive loads

▪ Adjustable rise/fall time via external timing capacitor

▪ Built-in tone oscillator, factory-trimmed to 22 kHz

facilitates DiSEqC™ tone encoding, even at no-load

▪ Four methods of 22 kHz tone generation, via I2C™ data

bits and/or external pin

▪ Filter bypass MOSFET minimizes losses during tone transmit

▪ 22 kHz tone detector facilitates DiSEqC™ 2.0 decoding

▪ Auxiliary modulation input

▪ LNB overcurrent with timer

▪ Diagnostics for output voltage level, input supply UVLO,

and DiSEqC™ tone output

▪ Cable disconnect diagnostic

Single LNB Supply and Control Voltage Regulator

Continued on the next page…

Functional Block Diagram

A8291

Boost

Converter

LNB

BOOST

VIN

220 nF

TCAP

10 nF

Clock

Divider

VCP

VOUT

100 nF

SDA

SCL

VPump

ADD

Fault Monitor

OCP

PNG

TSD

VUV

EXTM

VDD

IRQ

Charge

Pump

Oscillator

Regulator

Tone

Detect

TDO

TDI

VREG

TDO

TCAP

fsw

22 kHz

EXTM

TGate

TMode

10 nF

GNDLX

DAC

LNB

Voltage

Control

Wave

Shape Linear

Stage

10 nF

C13

220 nF

C10

220 nF

R1 R2 R3 R4

33 μHD1

220 μH

BFC

R5 R6 BFO

BFC

D2 C12

100 7

C11

0.68 μF

BFI

15 7

R10

GND

I2C™-

Compatible

Interface

100 μF

C51 μF

PAD

100

1MH

R9-C11 network is needed only when a highly

inductive load is applied, such as ProBand LNB.

D2, D4, D5, and R10 are used for surge protection.

Either C12 or C9 should be used, but not both.

Package:

28 pin 5 mm × 5mm MLP/QFN

(suffix ET)

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Package Thermal Characteristics*

Package RθJA

(°C/W) PCB

ET 32 4-layer

* Additional information is available on the Allegro website.

Selection Guide

Part Number PackingaDescription

A8291SETTR-Tb7 in. reel, 1500 pieces/reel

12 mm carrier tape

ET package, MLP/QFN surface mount

0.90 mm nominal height

aContact Allegro for additional packing options.

bLeadframe plating 100% matte tin.

time source. A DiSEqC™ filter bypass switch is also integrated, to

minimize the output impedance during tone generation.

A comprehensive set of fault registers are provided, which comply

with all the common standards, including: overcurrent, thermal

shutdown, undervoltage, cable disconnect, power not good, and

tone detect.

The device uses a 2-wire bidirectional serial interface, compatible

with the I2C™ standard, that operates up to 400 kHz.

The A8291 is supplied in a lead (Pb) free 28-lead MLP/QFN.

Description (continued)

Absolute Maximum Ratings

Characteristic Symbol Conditions Rating Units

Load Supply Voltage, VIN pin VIN 16 V

Output Current* IOUT Internally

Limited A

Output Voltage; BFI, BFO, LNB, LX, and

BOOST pins –1 to 33 V

Output Voltage, VCP pin –1 to 41 V

Logic Input Voltage, EXTM and BFC pins –0.3 to 5 V

Logic Input Voltage, other pins –0.3 to 7 V

Logic Output Voltage –0.3 to 7 V

Operating Ambient Temperature TA –20 to 85 °C

Junction Temperature TJ(max) 150 °C

Storage Temperature Tstg –55 to 150 °C

*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the

specified current ratings, or a junction temperature, TJ, of 150°C.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

PAD

LNB

GNDLX

VIN

BFI

BFO

GND

VREG

SDA

ADD

SCL

IRQ

BFC

BOOST

VCP

TCAP

TDO

EXTM

TDI

Terminal List Table

Name Number Function

ADD 11 Address select

BFC 19 Bypass FET control

BFI 24 Bypass FET input (connect to LNB)

BFO 22 Bypass FET output

BOOST 1 Tracking supply voltage to linear regulator

EXTM 6 External modulation input

GND 8 Signal ground

GNDLX 27 Boost switch ground

IRQ 14 Interrupt request

LNB 28 Output voltage to LNB

LX 26 Inductor drive point

NC 4, 13, 15-18,

20, 21, 23 No connection

PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation

SCL 12 I2C™-compatible clock input

SDA 10 I2C™-compatible data input/output

TCAP 3 Capacitor for setting the rise and fall time of the LNB output

TDI 7 Tone detect input

TDO 5 Tone detect output

VCP 2 Gate supply voltage

VIN 25 Supply input voltage

VREG 9 Analog supply

Device Pin-out Diagram

(Top View)

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1

Characteristics Symbol Test Conditions Min. Typ. Max. Units

General

Set-Point Accuracy, Load and Line Regulation Err Relative to selected VLNB target level,

ILOAD = 0 to 450 mA –4.5 – 4.5 %

Supply Current

IIN(Off) ENB bit = 0, LNB output disabled, VIN = 12 V – – 10.0 mA

IIN(On)

ENB bit = 1, LNB output enabled,

ILOAD = 0 mA, VIN = 12 V – – 19.0 mA

Boost Switch On Resistance RDS(on)BOOST ILOAD = 450 mA – 300 600 mΩ

Switching Frequency fSW 320 352 384 kHz

Switch Current Limit ILIMSW 2.2 3.0 4.0 A

Linear Regulator Voltage Drop ∆VREG

VBOOST – VLNB, no tone signal,

ILOAD = 450 mA 600 800 1000 mV

TCAP Pin Current ICHG TCAP capacitor (C7) charging –12.5 –10 –7.5 μA

IDISCHG TCAP capacitor (C7) discharging 7.5 10 12.5 μA

Output Voltage Rise Time2tr(VLNB)

For VLNB 13 → 18 V; CTCAP = 5.6 nF,

ILOAD = 450 mA – 500 – μs

Output Voltage Pull-Down Time2tf(VLNB)

For VLNB 18 → 13 V; CLOAD = 100 μF,

ILOAD = 0 mA – 12.5 – ms

Output Reverse Current IRLNB

ENB bit = 0, VLNB = 33 V , BOOST capacitor

(C5) fully charged –15mA

Ripple and Noise on LNB Output, Peak-to-Peak2Vrip,n(pp) 20 MHz bandwidth – 30 – mVPP

Protection Circuitry

Output Overcurrent Limit ILIMLNB 500 600 700 mA

Overcurrent Disable Time tDIS 40 48 56 ms

VIN Undervoltage Lockout Threshold VUVLO VIN falling 7.05 7.35 7.65 V

VIN Turn On Threshold VIN(th) VIN rising 7.40 7.70 8.00 V

Undervoltage Hysteresis VUVLOHYS – 350 – mV

Thermal Shutdown Threshold2TJ– 165 – °C

Thermal Shutdown Hysteresis2∆TJ–20–°C

Power Not Good Flag Set PNGSET With respect to VLNB 77 85 93 %

Power Not Good Flag Reset PNGRESET With respect to VLNB 82 90 98 %

Power Not Good Hysteresis PNGHYS With respect to VLNB –5–%

Cable Disconnect Boost Voltage VCAD

CADT bit = 1, ENB bit = 1, VSEL0 through

VSEL3 = 1 22.0 22.8 23.5 V

Cable Disconnect Set VCADSET 20.16 21.00 21.84 V

Cable Disconnect Current Source ICADSRC VLNB = 21.00 V, VBOOST = 22.8 V 1.0 1.75 2.5 mA

Continued on the next page…

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Bypass FET

Bypass FET Control (BFC) Logic Input VBFC(H) 2.0 – – V

VBFC(L) – – 0.8 V

Input Leakage IBFCLKG –1 – 1 μA

Bypass FET On Resistance RDS(on)

ILOAD = 450 mA, and VBFC = Low, or

BFC2 bit = 1 – 0.5 1 Ω

Turn On/Off Delay2tD(ON/OFF) VBFC = Low, or BFC2 bit = 1 – 650 – μs

Tone

Tone Frequency fTONE 20 22 24 kHz

Tone Amplitude, Peak-to-Peak VTONE(pp) ILOAD = 0 to 450 mA, CLOAD = 750 nF 400 620 800 mV

Tone Duty Cycle DCTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 40 50 60 %

Tone Rise Time trTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs

Tone Fall Time tfTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs

EXTM Logic Input VEXTM(H) 2.0 – – V

VEXTM(L) – – 0.8 V

EXTM Input Leakage IEXTMLKG –1 – 1 μA

Tone Detector

Tone Detect Input Amplitude Receive, Peak-to-Peak VTDR(pp) fTONE = 22 kHz sine wave, TMODE = 0 300 – – mV

Tone Detect Input Amplitude Transmit, Peak-

to-Peak

VTDT(pp)Int

fTONE = 22 kHz sine wave, using internal tone

(options 1 and 2, in figure 1) 400 – – mV

VTDT(pp)Ext

fTONE = 22 kHz sine wave, using external

tone (options 3 and 4, in figure 1) 300 – – mV

Tone Reject Input Amplitude, Peak-to-Peak VTRI(pp) fTONE = 22 kHz sine wave – – 100 mV

Frequency Capture fTDI 600 mVpp sine wave 17.6 – 26.4 kHz

Input Impedance2ZTDI – 8.6 – kΩ

TDO Output Voltage VTDO(L) Tone present, ILOAD = 3 mA – – 0.4 V

TDO Output Leakage ITDOLKG Tone absent, VTDO = 7 V – – 10 μA

I2C™-Compatible Interface

Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V

Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V

Logic Input Hysteresis VI2CIHYS – 150 – mV

Logic Input Current II2CI VI2CI = 0 to 7 V –10 <±1.0 10 μA

Logic Output Voltage SDA and IRQ Vt2COut(L) ILOAD = 3 mA – – 0.4 V

Logic Output Leakage SDA and IRQ Vt2CLKG Vt2COut = 0 to 7 V – – 10 μA

SCL Clock Frequency fCLK – – 400 kHz

Output Fall Time tfI2COut Vt2COut(H) to Vt2COut(L) – – 250 ns

Bus Free Time Between Stop/Start tBUF 1.3 – – μs

Hold Time Start Condition tHD:STA 0.6 – – μs

Setup Time for Start Condition tSU:STA 0.6 – – μs

SCL Low Time tLOW 1.3 – – μs

Continued on the next page…

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

SCL High Time tHIGH 0.6 – – μs

Data Setup Time tSU:DAT 100 – – ns

Data Hold Time tHD:DAT 0 – 900 ns

Setup Time for Stop Condition tSU:STO 0.6 – – μs

I2C™ Address Setting

ADD Voltage for Address 0001,000 Address1 0 – 0.7 V

ADD Voltage for Address 0001,001 Address2 1.3 – 1.7 V

ADD Voltage for Address 0001,010 Address3 2.3 – 2.7 V

ADD Voltage for Address 0001,011 Address4 3.3 – 5.0 V

1Operation at 16 V may be limited by power loss in the linear regulator.

2Guaranteed by design.

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1

Characteristics Symbol Test Conditions Min. Typ. Max. Units

I2C™ Interface Timing Diagram

tSU:STA t

HD:STA t

SU:DAT t

HD:DAT t

BUF tSU:STO

tHIGH tLOW

SDA

SCL

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Functional Description

Protection

The A8291 has a wide range of protection features and fault diag-

nostics which are detailed in the Status Register section.

Boost Converter/Linear Regulator

The A8291 solution contains a tracking current-mode boost

converter and linear regulator. The boost converter tracks the

requested LNB voltage to within 750 mV, to minimize power

dissipation. Under conditions where the input voltage, VBOOST

is greater than the output voltage, VLNB, the linear regulator must

drop the differential voltage. When operating in these conditions,

care must be taken to ensure that the safe operating temperature

range of the A8291 is not exceeded.

The boost converter operates at 352 kHz typical: 16 times

the internal 22 kHz tone frequency. All the loop compensation,

current sensing, and slope compensation functions are provided

internally.

The A8291 has internal pulse-by-pulse current limiting on the

boost converter and dc current limiting on the LNB output to pro-

tect the IC against short circuits. When the LNB output is short-

ed, the LNB output current is limited to 600 mA, typical. If the

ODT timer is enabled, the IC will be shut down if the overcurrent

condition lasts for more than 48 ms. If this occurs, the A8291

must be reenabled for normal operation. It is strongly recom-

mended that the ODT timer be enabled at all times. The system

should provide sufficient time between successive restarts to limit

internal power dissipation; a minimum of 2 s is recommended.

At extremely light loads, the boost converter operates in a

pulse-skipping mode. Pulse skipping occurs when the BOOST

voltage rises to approximately 450 mV above the BOOST target

output voltage. Pulse skipping stops when the BOOST voltage

drops 200 mV below the pulse skipping level.

In the case that two or more set top box LNB outputs are con-

nected together by the customer (e.g., with a splitter), it is pos-

sible that one output could be programmed at a higher voltage

than the other. This would cause a voltage on one output that is

higher than its programmed voltage (e.g., 19 V on the output of a

13 V programmed voltage). The output with the highest voltage

will effectively turn off the other outputs. As soon as this voltage

is reduced below the value of the other outputs, the A8291 output

will auto-recover to their programmed levels.

Charge Pump. Generates a supply voltage above the internal

tracking regulator output to drive the linear regulator control.

Slew Rate Control. During either start-up, or when the output

voltage on the BOOST or the LNB pins is changing, the output

voltage rise and fall times can be set by the value selected for

the external capacitor (C7) connected to the TCAP pin. Note that

during start-up, the BOOST pin is precharged to the input voltage

minus a diode drop. As a result, the slew rate control occurs from

this point.

The rating for C7, CTCAP , can be calculated using the follow-

ing formula:

CTCAP = (ITCAP × 6) / SR

where SR (V/s) is the required slew rate. The minimum value for

CTCAP is 2.2 nF. Using the recommended value of CTCAP , 5.6 nF,

this calculates to a slew rate of 10.7 V/ms.

Modulation is unaffected by the choice of C7. If it is not re-

quired to limit the LNB output voltage rise and fall times, then

C7 must have a value of at least 2.2 nF to minimize output noise.

Pull-Down Rate Control. In applications that have to operate at

very light loads and that require large load capacitances (in the

order of tens to hundreds of microfarads), the output linear stage

provides approximately 40 mA of pull-down capability. This

ensures that the output volts are ramped from 18 V to 13 V in a

reasonable amount of time.

ODT (Overcurrent Disable Time)

This function should be enabled at all times. If the ODT function

is enabled and the LNB output current exceeds 600 mA, typical,

for more than 48 ms, then the LNB output will be disabled and

the ODT bit will be set.

Short Circuit Handling

If the LNB output is shorted to ground, the LNB output current

will be clamped to 600 mA, typical. If the short circuit condition

lasts for more than 48 ms, the A8291 will be disabled and the

ODT bit will be set.

Auto-Restart

After a short circuit condition occurs, the host controller should

periodically reenable the A8291 to check if the short circuit has

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

been removed. Consecutive startup attempts should allow at least

2 s of delay between restarts.

In-Rush Current

At start-up or during an LNB reconfiguration event, a transient

surge current above the normal dc operating level can be

provided by the A8291. This current increase can be as high as

600 mA, typical, for as long as required, up to a maximum of

48 ms with the ODT timer enabled.

Tone Detection

A 22 kHz tone detector is provided in the A8291 solution. The

detector extracts the tone signal and provides it as an open-drain

signal on the TDO pin. The maximum tone out error is ±1 tone

cycle, and the maximum tone out delay with respect to the input

is 1 tone cycle..Detection thresholds are given in table 1.

Tone Generation

The A8291 solution offers four options for tone generation,

providing maximum flexibility to cover every application. The

EXTM pin (external modulation), in conjunction with the I2C™

control bits: TMODE (tone modulation) and TGATE (tone gate),

provide the necessary control. The TMODE bit controls whether

the tone source is either internal or external (via the EXTM pin).

Both the EXTM pin and TGATE bit determine the 22 kHz con-

trol, whether gated or clocked.

Four options for tone generation are shown in figure 1. Note

that when using option 4, when EXTM stops clocking, the LNB

volts park at the LNB voltage, either plus or minus half the tone

signal amplitude, depending on the state of EXTM. For example,

if the EXTM is held low, the LNB dc voltage is the LNB pro-

grammed voltage minus 325 mV (typical).

With any of the four options, when a tone signal is generated,

TDET is set in the status register. When the internal tone is used

(options 1 or 2), the minimum tone detect amplitude is 400 mV,

and when an external tone is used (options 3 or 4), the minimum

tone detection amplitude is 300 mV.

DiSEqC™ Bypass MOSFET

A pair of N-channel MOSFETs are connected in parallel (source

to drain and drain to source) to provide a low source output

impedance during tone transmission.

The MOSFETs are enabled either via the BFC input pin (ac-

tive low) or by setting the BFC2 bit to 1 in the Control register.

When the BFC pin is used instead of I2C™ control, it is not

latched; a logic high or low turns the FET off or on. When the

EXTM

TMODE

TGATE

Tone

(LNB Ref)

LNB (V)

EXTM

TMODE

TGATE

Tone

(LNB Ref)

LNB (V)

EXTM

TMODE

TGATE

Tone

(LNB Ref)

LNB (V)

EXTM

TMODE

TGATE

Tone

(LNB Ref)

LNB (V)

Option 1 – Use internal tone, gated by the TGATE bit.

Option 2 – Use internal tone, gated by the EXTM pin.

Option 3 – Use external tone, gated by the TGATE bit.

Option 4 – Use external tone.

Figure 1. Options for tone generation

Table 1. Detection Thresholds for Tone Generation Options

Transmit Receive

Option

(Fig. 1) 1 2 3 4 n.a. n.a.

TMODE 1 1 0 0 0 1

TGATE Control

0/1 1Control

0/1 1

At least one must

be 0 to prevent

tone transmission

EXTM 1 Control

0/1

22 kHz

logic signal,

continuous

Control

gated

22 kHz

logic

signal

Guaranteed

Detection

Threshold

(mVPP)

400 400 300 300 300 400

Rejection

Threshold

(mVPP)

100 100 100 100 100 100

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

I2C™-compatible interface is used, the BFC pin is not connected,

but the pull up resistor R5 must be present.

I2C™-Compatible Interface

This is a serial interface that uses two bus lines, SCL and SDA,

to access the internal Control and Status registers of the A8291.

Data is exchanged between a microcontroller (master) and the

A8291 (slave). The clock input to SCL is generated by the master,

while SDA functions as either an input or an open drain output,

depending on the direction of the data.

Timing Considerations

The control sequence of the communication through the I2C™-

compatible interface is composed of several steps in sequence:

1. Start Condition. Defined by a negative edge on the SDA line,

while SCL is high.

2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)

or write (0), and an acknowledge bit. The first five bits of the

address are fixed as: 00010. The four optional addresses, de-

fined by the remaining two bits, are selected by the ADD input.

The address is transmitted MSB first.

3. Data Cycles.

Write – 6 bits of data and 2 bits for addressing four internal

control registers, followed by an acknowledge bit. See Control

Read – Two status registers, where register 1 is read first,

followed by register 2, then register 1, and so on. At the start

of any read sequence, register 1 is always read first. Data is

transmitted MSB first.

4. Stop Condition. Defined by a positive edge on the SDA line,

while SCL is high. Except to indicate a Start or Stop condi-

tion, SDA must be stable while the clock is high. SDA can

only be changed while SCL is low. It is possible for the Start or

Stop condition to occur at any time during a data transfer. The

A8291 always responds by resetting the data transfer sequence.

1 2 3 4 5 6 7 8 9

0 0 0 1 0 A1 A0 0 AK AK I0 D5 D4 D3 D2 D1 D0 I1

Control Data Address Start W Stop

SDA

SCL

0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 NAK

Status Register 1 Address Start R Stop

1 2 3 4 5 6 7 8 9

SDA

SCL

0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 - - - D3 D2 D1 D0 - AK NAK

Status Data in Register 2 Address Start R Stop Status Data in Register 1

1 2 3 4 5 6 7 8 9

SDA

SCL

acknowledge

from LNBR

acknowledge

from LNBR

acknowledge

from LNBR

no acknowledge

from master

no acknowledge

from master

acknowledge

from LNBR

acknowledge

from LNBR

Write to Register

Read One Byte from Register

Read Multiple Bytes from

Figure 2. I2C™ Interface. Read and write sequences.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

The Read/Write bit is used to determine the data transfer direc-

tion. If the Read/Write bit is high, the master reads the contents of

the Read/Write bit is low, the master writes data to one of the two

Control registers. Note that multiple writes are not permitted. All

write operations must be preceded with the address.

The Acknowledge bit has two functions. It is used by the mas-

ter to determine if the slave device is responding to its address

and data, and it is used by the slave when the master is reading

data back from the slave. When the A8291 decodes the 7-bit ad-

dress field as a valid address, it responds by pulling SDA low

during the ninth clock cycle.

During a data write from the master, the A8291 also pulls SDA

low during the clock cycle that follows the data byte, in order to

indicate that the data has been successfully received. In both cas-

es, the master device must release the SDA line before the ninth

clock cycle, in order to allow this handshaking to occur.

During a data read, the A8291 acknowledges the address in the

same way as in the data write sequence, and then retains control

of the SDA line and send the data from register 1 to the master.

On completion of the eight data bits, the A8291 releases the SDA

line before the ninth clock cycle, in order to allow the master to

acknowledge the data. If the master holds the SDA line low dur-

ing this Acknowledge bit, the A8291 responds by sending the

data from register 2 to the master. Data bytes continue to be sent

to the master until the master releases the SDA line during the

Acknowledge bit. When this is detected, the A8291 stops sending

data and waits for a stop signal.

Interrupt Request

The A8291 also provides an interrupt request pin, IRQ, which

is an open-drain, active-low output. This output may be connect-

ed to a common IRQ line with a suitable external pull-up and can

be used with other I2C™-compatible devices to request attention

from the master controller.

The IRQ output becomes active when either the A8291 first

recognizes a fault condition, or at power-on, when the main sup-

ply, VIN , and the internal logic supply, VREG , reach the correct

operating conditions. It is only reset to inactive when the I2C™

master addresses the A8291 with the Read/Write bit set (caus-

ing a read). Fault conditions are indicated by the TSD, VUV, and

OCP bits (when ODT is set to 1) and are latched in the Status reg-

ister. See the Status register section for full description.

The OCP (with ODT= 0), DIS, PNG, CAD and TDET status

bits do not cause an interrupt. All these bits are continually up-

dated, apart from the DIS bit, which changes when the LNB is

either disabled, intentionally or due to a fault, or is enabled.

When the master recognizes an interrupt, it addresses all

slaves connected to the interrupt line in sequence, and then reads

the status register to determine which device is requesting atten-

tion. The A8291 latches all conditions in the Status register until

the completion of the data read. The action at the resampling

point is further defined in the Status Register section. The bits

in the Status register are defined such that the all-zero condition

indicates that the A8291 is fully active with no fault conditions.

When VIN is initially applied, the I2C™-compatible interface

does not respond to any requests until the internal logic supply

VREG has reached its operating level. Once VREG has reached this

point, the IRQ output goes active, and the VUV bit is set. After

the A8291 acknowledges the address, the IRQ flag is reset. After

the master reads the status registers, the registers are updated with

the VUV reset.

0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 NAK

Status Register 1 Address Start R Stop

1 2 3 4 5 6 7 8 9

SDA

SCL

IRQ

Fault

Event

Reload

Status Register

Read after Interrupt

Figure 3. I2C™ Interface. Read sequences after interrupt request.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Control Registers (I2C™-Compatible Write Register)

All main functions of the A8291 are controlled through the I2C™-

compatible interface via the 8-bit Control registers. As the A8291

contains numerous control options, it is necessary to have two

control registers. Each register contains up to 6 bits of data (bit

0 to bit 5), followed by 2 bits for the register address (bit 6 and

bit 7). The power-up states for the control functions are all 0s.

The following tables define the control bits for each address

and the settings for output voltage:

Table 2. Control Register Address (I1, I0) = 00

Bit Name Function

0 VSEL0

See table 4, Output Voltage Amplitude Selection1 VSEL1

2 VSEL2

3 VSEL3

0: LNB = Low range

1: LNB = High range

4 ODT

0: Overcurrent disable time off

1: Overcurrent disable time on

5 ENB

0: Disable LNB Output

1: Enable LNB Output

6 I0 Address Bit: 0

7 I1 Address Bit: 0

Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output.

Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards

Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage

levels are defined in table 4, Output Voltage Amplitude Selection.

Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output.

0 selects the low level voltage and 1 selects the high level. The low-level center voltage

is 12.709 V nominal and the high level is 18.042 V nominal. These may be increased

in steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits.

Bit 4 ODT Enables the overcurrent disable timer. When set to 1, and an overcurrent occurs for

longer than the detection time, the LNB output on that channel is disabled. When set

to 0, and an overcurrent occurs, the LNB output will operate in current limit indefi-

nitely. It is highly recommended that the ODT function be enabled at all times.

Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to

0, the LNB output is disabled.

Bit 6 I0 Address

Bit 7 I1 Address

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 3. Control Register Address (I1, I0) = 10 and 11

Bit Name Function

0 TMODE

0: External Tone

1: Internal Tone

1 TGATE

0: Tone Gated Off

1: Tone Gated On

2 CADT

0: Cable Disconnect Test Off

1: Cable Disconnect Test On

3 - Not Used

4 - Not Used

5BFC2

0: Bypass MOSFET Off

1: Bypass MOSFET On

6 I0 Address Bit: 0

7 I1 Address Bit: 1

Bit 0 TMODE Tone Mode. Selects between the use of an external 22 kHz logic signal or the use of

the internal 22 kHz oscillator to control the tone generation on the LNB output. A 0

selects the external tone and a 1 selects the internal tone. See the Tone Generation

section for more information

Bit 1 TGATE Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated,

unless the EXTM is selected for gating. When set to 0, the selected tone (via

TMODE) is off. When set to 1, the selected tone is on. See Tone Generation Section

for more information.

Bit 2 CADT Cable Disconnect Test. To perform this test, set bits CADT, ENB, and VSEL0

through VSEL3 through the I2C™-compatible interface. During this test, the LNB

linear regulator is disabled, a 1 mA current source between the BOOST output and

the LNB output is enabled, and the BOOST voltage is increased to 22.8 V. After

these conditions are set, if the LNB voltage is above 21 V, it is assumed that the

coaxial cable connection between the LNBR output and the LNB head has been dis-

connected. In this case, the CAD bit is set in the status register. If there is a load on

the LNB pin, then the LNB voltage will decrease proportionally to the load current.

If the LNB volts drop below 19.95 V, it is assumed that the coax cable is connected

and the CAD bit in the status register is set to 0.

Bit 3 – Not Used.

Bit 4 – Not Used.

Bit 5 BFC2 Bypass MOSFET Control. When set to 1, the internal bypass MOSFETs are en-

abled. A 0 disables the bypass MOSFETs.

Bit 6 I0 Address.

Bit 7 I1 Address.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 4. Output Voltage Amplitude Selection

VSEL3 VSEL2 VSEL1 VSEL0 LNB (V)

000012.709

000113.042

001013.375

001113.709

010014.042

010114.375

011014.709

011115.042

100018.042

100118.375

101018.709

101119.042

110019.375

110119.709

111020.042

111120.375

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Status Registers (I2C™-Compatible Read Register)

The main fault conditions: overcurrent (OCP, with overcurrent

disable timer, ODT enabled), under voltage (VUV) and overtem-

perature (TSD), are all indicated by setting the relevant bits in the

Status registers. In all fault cases, once the bit is set, it remains

latched until the A8291 is read by the I2C™ master, assuming the

fault has been resolved.

The current status of the LNB output is indicated by the dis-

able bit, DIS. The DIS bit is set when either a fault occurs or if

the LNB is disabled intentionally. This bit is latched, and is reset

when the LNB is commanded on again. The power not good

(PNG), tone detect (TDET), and cable disconnected (CAD) flags

are the only bits which may be reset without an I2C™ read se-

quence. In addition, the overcurrent bit (OCP) can be reset without

an I2C™ read, if the overcurrent disable timer (ODT) is disabled.

Table 5 summarizes the condition of each bit when set and how it

is reset.

As the A8291 has a comprehensive set of status reporting bits,

it is necessary to have two Status registers. When performing a

multiple read function, register 1 is read followed by register 2,

then register 1 again and so on. Whenever a new read function is

performed, register 1 is always read first.

The normal sequence of the master in a fault condition will be

to detect the fault by reading the Status registers, then rereading

the Status registers until the status bit is reset indicating the fault

condition is reset. The fault may be detected either by continuously

polling, by responding to an interrupt request (IRQ), or by detect-

ing a fault condition externally and performing a diagnostic poll of

all slave devices. Note that the fully-operational condition of the

Status registers is all 0s, to simplify checking of the Status bit.

Table 5. Status Register Bit Setting

Status Bit Function Set Reset

Condition

CAD Cable disconnected Non-latched Cable disconnect test off or

cable connected

DIS LNB disabled, either intentionally or

due to fault Latched LNB enabled and no fault

OCP

Overcurrent with overcurrent disable

timer set to 1 Latched I2C™ read and fault removed

Overcurrent with overcurrent disable

timer set to 0 Non-latched Overcurrent removed

PNG Power not good Non-latched LNB volts in range

TDET Tone detect Non-latched Tone removed

TSD Thermal shutdown Latched I2C™ read and fault removed

VUV Undervoltage Latched I2C™ read and fault removed

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 6. Status Register 1

Bit Name Function

0 DIS LNB output disabled

1 – Not Used

2 OCP Overcurrent

3 – Not Used

4 PNG Power Not Good

5 – Not Used

6 TSD Thermal Shutdown

7 VUV VIN Undervoltage

Bit 0 DIS LNB Output Disabled. DIS is used to indicate the current condition of the LNB

output. At power-on, or if a fault condition occurs, DIS will be set. This bit changing

to 1 does not cause the IRQ to activate because the LNB output may be disabled in-

tentionally by the I2C™ master. This bit will be reset at the end of a write sequence

if the LNB output is enabled.

Bit 1 – Not used.

Bit 2 OCP Overcurrent. If the LNB output detects an overcurrent condition, for greater than

the detection time, and the overcurrent detection timer, ODT, is enabled, the LNB

output will be disabled. The OCP bit will be set to indicate that an overcurrent has

occurred and the disable bit, DIS, will be set. The Status register is updated on the

rising edge of the 9th clock pulse in the data read sequence, where the OCP bit is

reset in all cases, allowing the master to reenable the LNB output.

If the overcurrent timer is not enabled, the device operate in current limit indefinitely

and the OCP bit will be set. If the overcurrent condition is removed, the OCP bit will

automatically be reset. Note that if the overcurrent operates long enough, and a ther-

mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set.

Bit 3 – Not used.

Bit 4 PNG Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is

below 85% of the programmed voltage. The PNG is reset when the LNB volts are

within 90% of the programmed LNB voltage.

Bit 5 – Not used.

Bit 6 TSD Thermal shutdown. 1 indicates that the A8291 has detected an overtemperature

condition and has disabled the LNB output. The disable bit, DIS, will also be set.

The status of the overtemperature condition is sampled on the rising edge of the 9th

clock pulse in the data read sequence. If the condition is no longer present, then the

TSD bit will be reset, allowing the master to reenable the LNB output if required. If

the condition is still present, then the TSD bit will remain at 1.

Bit 7 VUV Undervoltage Lockout. 1 indicates that the A8291 has detected that the input sup-

ply, VIN is, or has been, below the minimum level and an undervoltage lockout has

occurred disabling the LNB outputs. The disable bit, DIS, will also be set and the

A8291 will not reenable the output until so instructed by writing the relevant bit into

the control registers. The status of the undervoltage condition is sampled on the rising

edge of the 9th clock pulse in the data read sequence. If the condition is no longer

present, then the VUV bit will be reset allowing the master to reenable the LNB out-

put if required. If the condition is still present, then the VUV bit will remain at 1.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 7. Status Register 2

Bit Name Function

0 CAD Cable Disconnected

1 – Not Used

2 TDET Tone Detect

3 – Not Used

4 – Not Used

5 – Not Used

6 – Not Used

7 – Not Used

Bit 0 CAD Cable between LNB and the LNB head is disconnected. When cable disconnect test

mode is applied, the LNB linear regulator is disabled and a 1 mA current source is

applied between the BOOST and LNB output. If the LNB volts rise above 21 V,

CAD will be set to 1. The CAD bit is reset if the LNB volts drop below 19.95 V.

Bit 1 – Not used.

Bit 2 TDET Tone Detect. When tone is enabled by whatever option, or if a tone signal is re-

ceived from the LNB, TDET will be set to 1 if the tone appears at the LNB output.

When the tone is disabled and no tone is received from the LNB, TDET is reset.

Bits 3 to 7 Not used.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 8. Component Selection Table

Component Characteristics Manufacturer Device

C3 220 nF, 10 VMIN, X5R or X7R, 0402 or 0603

C8, C9b, C12b220 nF, 50 V, X5R or X7R, 0805

C1, C4 100 nF, 50 V, X5R or X7R, 0603

C2, C5 100 μF, 35 VMIN , ESR < 75 mΩ, IRIPPLE > 800 mA ChemiCon: EKZE500ELL101MHB5D

Nichicon: UHC1V101MPT

C7 10 nF, 10 VMIN, X5R or X7R, 0402 or 0603

C10, C13 10 nF, 50 V, X5R or X7R, 0402 or 0603

C11 0.68 μF, 25 VMIN, X5R or X7R, 0805

TDK: C2012X5R1E684K

Murata: GRM21BR71E684KA88

Kemet: C0805C684K3PAC

AVX: 08053D684KAT2A

C6 1.0 μF, 25 VMIN, X5R or X7R, 1206

TDK: C3216X7R1E105K

Murata: GRM31MR71E105KA01

Taiyo Yuden: TMK316BJ105KL-T

Kemet: C1206C105K3RACTU

D1, D2, D3 Schottky diode, 40 V, 1 A, SOD-123 Diodes, Inc: B140HW-7

Central Semi: CMMSH1-40

TVS, 24 V, 200 A, 1500 W;

Use one TVS to provide surge protection up to 3 kV

and two TVSs for protection from 3 kV to 6 kV

(1.2/50, 8/20, 12 A, per IEC61000-4-5)

Vishay: 1.5KE24A-E3/54

Diodes, Inc.: 1.5KE24A-T

D5 Schottky diode, 40 V, 3 A, SMA

Sanken: SFPB-74

Vishay: B340A-E3/5AT

Diodes, Inc: B340A-13-F

Central Semi: CMSH3-40MA

L1 33 μH, ISAT > 1.3 A, DCR < 130 mΩ

TDK: TSL0808RA-330K1R4-PF

Taiyo Yuden: LHLC08TB330K

Coilcraft: DR0608-333L

L2 220 μH, ISAT > 0.5 A, DCR < 0.8 Ω

TDK: TSL0808RA-221KR54-PF

Taiyo Yuden: LHLC08TB221K

Coilcraft: DR0608-224L

L3 1 μH, 1 A, DCR < 120 mΩ, 1206

Kemet: LB3218-T1R0MK

Murata: LQM31PN1R0M00L

Taiyo Yuden: LB3218T1R0M

TDK: MLP3216S1R0L

R1 to R6 Determined by VDD, bus capacitance, etc.

R7 15 Ω, 1%, 1/8 W

R8 100 Ω, 1%, 1/8 W

R9 30 Ω, 1/8 W

R10 1 Ω, 1/8 W

*Either C9 or C12 are used, but not both.

Single LNB Supply and Control Voltage Regulator

A8291

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

I2C™ is a trademark of Philips Semiconductors.

DiSEqC™ is a trademark of Eutelsat S.A.

Package ET 28-Pin MLP/QFN

0.30

NOM .012

0.50

NOM .020

1.15

NOM .045

3.15

NOM .124

3.15

NOM .124

4.8

NOM .189

4.8

NOM .189

0.30

0.18 .012

.007

0.65

0.45 .026

.018

1.00

0.80 .039

.031

0.05

0.00 .002

.000

5.15

4.85 .203

.191

5.15

4.85 .203

.191

0.20

REF .008

SEATING

PLANE

C0.08 [.003]

28X

0.10 [.004] M C A B

0.05 [.002] M C 0.50 .020

4X0.20

MIN .008

24X0.20

MIN .008

ATerminal #1 mark area

BExposed thermal pad (terminal #1 identifier appearance

at supplier discretion)

All dimensions reference only, not for tooling use

(reference JEDEC MO-220VHHD)

Dimensions in millimeters

U.S. Customary dimensions (in.) in brackets, for reference only

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

QFN50P500X500X100-29V1M); adjust as necessary to

meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal

vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

R0.30

REF .012

3.15

NOM .124

3.15

NOM .124

4X0.20

MIN .008

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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