NH82801GHM - Intel - Pdf.Support

Document Number: 307013-003

Intel® I/O Controller Hub 7 (ICH7)

Family

Datasheet

— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,

82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O

Controller Hubs

April 2007

2Intel ® ICH7 Family Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® I/O Controller Hub 7 (ICH7) F amily chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Intel SpeedStep, and the Intel logo are trademarks or reg ister ed trademarks of Intel Corporation or its subsidiaries in the United States and other

countries.

*Other names and brands may be claimed as the property of others.

Intel ® ICH7 Family Datasheet 3

Contents

1Introduction............................................................................................................39

1.1 Overview .........................................................................................................42

1.2 Intel® ICH7 Family High-Level Component Differences ...........................................50

2 Signal Description ...................................................................................................51

2.1 Direct Media Interface (DMI) to Host Controller.....................................................55

2.2 PCI Express* (Desktop and Mobile Only) ..............................................................55

2.3 Platform LAN Connect Interface (Desktop and Mobile Only).....................................56

2.4 EEPROM Interface (Desktop and Mobile Only)........................................................56

2.5 Firmware Hub Interface (Desktop and Mobile Only)................................................56

2.6 PCI Interface ....................................................................................................57

2.7 Serial ATA Interface (Desktop and Mobile Only).....................................................59

2.8 IDE Interface....................................................................................................60

2.9 LPC Interface....................................................................................................62

2.10 Interrupt Interface ............................................................................................62

2.11 USB Interface.... ........... .. .. ........... .. .. .......... ... .. .......... .. ........... .. .. ........... .. .. ........63

2.12 Power Management Interface..............................................................................64

2.13 Processor Interface............................................................................................66

2.14 SMBus Interface................................................................................................68

2.15 System Management Interface............................................................................68

2.16 R eal Time Cl ock In terface.......... .......................................... .. .. .. .........................69

2.17 Other Clocks.....................................................................................................69

2.18 Miscellaneous Sig n als ...... .. .. ..................... .. ... ..................... .. .. ..................... .. .. ..7 0

2.19 AC ’97/Intel® High Definition Audio Link...............................................................71

2.20 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) ....................................72

2.21 Intel® Quick Resume Technology (Intel® ICH7DH Only) .........................................72

2.22 General Purpose I/O Signals ................ ....................... ....................... .................72

2.23 Power and Ground.............................................................................................74

2.24 Pin Straps ........................................................................................................76

2.24.1 Functional Straps .............. .. .. .......... ... .. ..................... .. .. ..................... .. ..7 6

2.24.2 External RTC Circuitry.............................................................................78

3Intel

® ICH7 Pin States.............................................................................................79

3.1 Integrated Pull-Ups and Pull-Downs .....................................................................79

3.2 IDE Integrated Series Termination Resistors..........................................................80

3.3 Output and I/O Signals Planes and States.............................................................81

3.4 Power Planes for Input Signals............................................................................90

4Intel

® ICH7 and System Clock Domains...................................................................95

5 Functional Description.............................................................................................99

5.1 PCI-to-PCI Bridge (D30:F0)................................................................................99

5.1.1 PCI Bus Interface...................................................................................99

5.1.2 PCI Bridge As an Initiator........................................................................99

5.1.2.1 Memory Reads and Writes..........................................................99

5.1.2.2 I/O Reads and Writes .............................................................. 100

5.1.2.3 Configuration Reads and Writes ................................................ 100

5.1.2.4 Locked Cycles......................................................................... 100

5.1.2.5 Target / Master Aborts............... .. .. .. ........................................ 100

5.1.2.6 Secondary Master Latency Timer............................................... 100

5.1.2.7 Dual Address Cy cle (D AC)................ .. ........... .. .. ........... .. .. ........ 100

5.1.2.8 Memory and I/O Decode to PCI................................................. 101

5.1.3 Parity Error Detection and Generation ..................................................... 101

5.1.4 PCIRST#............................................................................................. 101

4Intel ® ICH7 Family Datasheet

5.1.5 Peer Cycles..........................................................................................102

5.1.6 PCI-to-PCI Bridge Model ........................................................................102

5.1.7 IDSEL to Device Number Mapping...........................................................103

5.1.8 Standard PCI Bus Configuration Mechanism..............................................103

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) ..........103

5.2.1 Interrupt Generation .............................................................................103

5.2.2 Power Management...............................................................................104

5.2.2.1 S3/S4/S5 Support...................................................................104

5.2.2.2 Resuming from Suspended State...............................................104

5.2.2.3 Device Initiated PM_PME Message .............................................104

5.2.2.4 SMI/SCI Generation .................................................................105

5.2.3 SERR# Generation................................................................................105

5.2.4 Hot-Plug..............................................................................................106

5.2.4.1 Presence Detection..................................................................106

5.2.4.2 Message Generation ................................................................106

5.2.4.3 Attention Button Detection .......................................................107

5.2.4.4 SMI/SCI Generation .................................................................107

5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only)..........................................108

5.3.1 LAN Controller PCI Bus Interface.............................................................108

5.3.1.1 Bus Slav e Ope ration .................. .. .. ..................... .. .. .................109

5.3.1.2 CLKRUN# Signal (Mobile Only)..................................................110

5.3.1.3 PCI Power Management ...........................................................110

5.3.1.4 PCI Reset Signal......................................................................110

5.3.1.5 Wake-Up Events......................................................................111

5.3.1.6 Wak e on LAN* (Pre b oot Wake-Up)................ ............ ............. ....112

5.3.2 Serial EEPROM Interface........................................................................112

5.3.3 CSMA/CD Unit......................................................................................113

5.3.3.1 Full Duplex.............................................................................113

5.3.3.2 Flow Control........ .. .......... .. .. ...................... .. .. .. .......... ... .. ........113

5.3.3.3 VLAN Support.........................................................................113

5.3.4 Media Management Interface .................................................................113

5.3.5 TCO Functionality .................................................................................114

5.3.5.1 Advanced TCO Mode................................................................114

5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) .......................................115

5.4.1 ASF Management Solution Features/Capabilities .......................................116

5.4.2 ASF Hardware Support ..........................................................................117

5.4.2.1 Intel® 82562EM/EX .................................................................117

5.4.2.2 EEPROM (256x16, 1 MHz) .................................... ............. .......117

5.4.2.3 Legacy Sensor SMBus Devices ..................................................117

5.4.2.4 R emote Control SMBus Devices.................................... .............117

5.4.2.5 ASF Sensor SMBus Devices.......................................................117

5.4.3 ASF Software Support ...........................................................................118

5.5 LPC Bridge (w/ System and Management Functions) (D31:F0)...............................118

5.5.1 LPC Interface .......................................................................................118

5.5.1.1 LPC Cycle Types......................................................................119

5.5.1.2 Start Field Definition.......... ......................................................119

5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................120

5.5.1.4 SIZE......................................................................................120

5.5.1.5 SYNC.....................................................................................121

5.5.1.6 SYNC Time-Out.......................................................................121

5.5.1.7 SYNC Error Indication ..............................................................121

5.5.1.8 LFRAME# Usage............. .. .. ..................... ... .. .......... .. .. ........... ..122

5.5.1.9 I/O Cycles..............................................................................122

5.5.1.1 0 Bus Master Cy cles ................ ... .......... .. .. ........... .. .. ........... .. .. ....122

5.5.1.11 LPC Power Management...........................................................122

5.5.1.12 Configuration and Intel® ICH7 Implications.................................123

5.5.2 SERR# Generation................................................................................123

Intel ® ICH7 Family Datasheet 5

5.6 DMA Operation (D31:F0).................................................................................. 124

5.6.1 Channel Priority ................................................................................... 124

5.6.1.1 Fixed Priority.......................................................................... 125

5.6.1.2 Rotating Priority ..................................................................... 125

5.6.2 Address Compatibility Mode................................................................... 125

5.6.3 Summary of DMA Transfe r Sizes............... .. .. .. ........... .. .. .. ..................... .. 125

5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by

Words ................................................................................... 126

5.6.4 Autoinitialize........................................................................................ 126

5.6.5 Software Commands............................................................................. 126

5.7 LPC DMA (Desktop and Mobile Only).................................................................. 127

5.7.1 Asserting DMA Requests........................................................................ 127

5.7.2 Abandoning DMA Requests ........... .. .. ........... .. .. ..................... .. ... .. .......... 127

5.7.3 General Flow of DMA Transfers............................................................... 128

5.7.4 Terminal Count .................................................................................... 128

5.7.5 Verify Mode ......................................................................................... 128

5.7.6 DMA Request Deassertion...................................................................... 129

5.7.7 SYNC Field / LDRQ# Rules..................................................................... 129

5.8 8254 Timers (D31:F0) ..................................................................................... 130

5.8.1 Timer Programming.............................................................................. 131

5.8.2 Reading from the Interval Timer............................................................. 132

5.8.2.1 Simple Read........................................................................... 132

5.8.2.2 Counter Latch Command...................... .. ... .. ..................... .. .. .. .. 132

5.8.2.3 Read Back Command .............................................................. 132

5.9 8259 Interrupt Controllers (PIC) (D31:F0).......................................................... 133

5.9.1 Interrupt Handling................................................................................ 134

5.9.1.1 Generating Interrupts.............................................................. 134

5.9.1.2 Acknowledging Interrupts ........................................................ 134

5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135

5.9.2 Initialization Command Words (ICWx)..................................................... 135

5.9.2.1 ICW1 .................................................................................... 135

5.9.2.2 ICW2 .................................................................................... 136

5.9.2.3 ICW3 .................................................................................... 136

5.9.2.4 ICW4 .................................................................................... 136

5.9.3 Operation Command Words (OCW)......................................................... 136

5.9.4 Modes of Oper ation ........... .......... .. .. ... ..................... .. .. .. ..................... .. 136

5.9.4.1 Fully Nested Mode................................................................... 136

5.9.4.2 Special Fully-Nested Mode........................................................ 137

5.9.4.3 Automatic Ro tation Mod e (Equal Priorit y De vice s).................. .. .. .. 137

5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137

5.9.4.5 Poll Mode............................................................................... 137

5.9.4.6 Cascade Mode......... .. .. ........... .. .. .......... ... .. .......... .. .. ........... .. .. 138

5.9.4.7 Edge and Level Triggered Mode................................................. 138

5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138

5.9.4.9 Normal End of Interrupt........................................................... 138

5.9.4.10 Automatic End of Interrupt Mo de ................. .. .. ......................... 138

5.9.5 Masking Interrupts ............................................................................... 139

5.9.5.1 Masking on an Individual Interrupt Request................................ 139

5.9.5.2 Special Mask Mode.................................................................. 139

5.9.6 Steering PCI Interrupts......................................................................... 139

5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) ...... ........................ 140

5.10.1 Interrupt Handling................................................................................ 140

5.10.2 Interrupt Mapping ................................................................................ 140

5.10.3 PCI / PCI Express* Message-Based Interrupts.......................................... 141

5.10.4 Front Side Bus Interrupt Deliv e ry ............................ ............ ............. ...... 141

5.10.4.1 Edge-Triggered Operation......................................................... 142

6Intel ® ICH7 Family Datasheet

5.10.4.2 Level-Triggered Operation.........................................................142

5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery ..........142

5.10.4.4 Interrupt Message Format ........................................................142

5.11 Serial Interrupt (D31:F0)..................................................................................143

5.11.1 Start Frame .........................................................................................143

5.11.2 Data Frames ........................................................................................144

5.11.3 Stop Frame..........................................................................................144

5.11.4 Specific Interrupts Not Supported via SERIRQ...........................................144

5.11.5 Data Frame Format...............................................................................145

5.12 Real Time Clock (D31:F0) .................................................................................146

5.12.1 Update Cycles ......................................................................................146

5.12.2 Interrupts............................................................................................147

5.12.3 Lockable RAM Ranges............................................................................147

5.12.4 Century Rollover.............. .. .. ..................... .. .. ..................... .. .. ...............147

5.12.5 Clearing Battery-Backe d RTC RAM................. ............. ............ ............. ....147

5.13 Processor Interface (D31:F0) ............................................................................149

5.13.1 Processor Interface Signals ....................................................................149

5.13.1. 1 A20M# (Mask A20)..... .. .. ..................... .. .. ........... .. .. ........... .. .. ..149

5.13.1.2 INIT# (Initialization)................................................................150

5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric

Error) ....................................................................................150

5.13.1.4 NMI (Non-Maskable Interrupt) ..................................................151

5.13.1.5 Stop Clock Re q uest and CP U Sle ep (ST PC LK # and CPU SLP #)........151

5.13.1.6 CPU Power Good (CPUPW RGOOD) ........... .. ... .............................151

5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/U ltra Mobile Only)............ .. .. .. .. ..151

5.13.2 Dual-Processor Issues (Desktop Only) .....................................................152

5.13.2.1 Signal Differen ce s .............. ..................... ... .. ..................... .. .. ..152

5.13.2.2 Power Management .................................................................152

5.14 Power Management (D31:F0)............................................................................153

5.14.1 Features..............................................................................................153

5.14.2 Intel® ICH7 and System Power States............... ......................................153

5.14.3 Sy stem Power Planes ........... .. .......... .. ... .......... .. .. ........... .. .. ........... .. .. ....156

5.14.4 SMI#/SCI Generation............................................................................156

5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) ..............................159

5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ..... ..................159

5.14.5 Dynamic Processor Clock Control ............ ................................................159

5.14.5.1 Transition Rules among S0/Cx and Throttling States.....................160

5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) .................................161

5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) ..................161

5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only).............161

5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................161

5.14.6.1 Conditions for Checking the PCI Clock........................................162

5.14.6.2 Conditions for Maintaining the PCI Clock.....................................162

5.14.6.3 Conditions for Stopping the PCI Clock ........................................162

5.14.6.4 Conditions for Re-Starting the PCI Clock.....................................162

5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only)............16 2

5.14.7 Sleep States ........................................................................................163

5.14.7.1 Sleep State Overview...............................................................163

5.14.7.2 Initiating Sleep State...............................................................163

5.14.7.3 Exiting Sleep States.................................................................163

5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (

Desktop and Mobile only)............. .. ....................... ...................165

5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................165

5.14.8 Thermal Manageme nt............... .. .. ........... .. .. .. ........... .. .. ..................... .. ..166

5.14.8. 1 THRM# Signal................ .. .. ........... .. .. ..................... .. .. ........... ..166

5.14.8.2 Processor Initiated Passive Cooling ............................................166

5.14.8.3 THRM# Overrid e Soft ware Bit ................. ..................................167

Intel ® ICH7 Family Datasheet 7

5.14.8.4 Active Cooling ........................................................................ 167

5.14.9 Event Input Signals and Their Usage....................................................... 167

5.14.9.1 PWRBTN# (Power Button)........................................................ 167

5.14.9.2 RI# (Ring Indicator)................................................................ 168

5.14.9.3 PME# (PCI Power Management Event)....................................... 169

5.14.9.4 SYS_RESET# Signal................................................................ 169

5.14.9.5 THRMTRIP# Sig nal... .. .. .. ..................... .. ... ..................... .. .. ...... 169

5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only)....................................... 170

5.14.10ALT Access Mode............................. ... .. .......... .. .. ........... .. .. ........... .. .. .... 170

5.14.10.1Write Only Registers with Read Paths in ALT Access Mode............. 1 71

5.14.10.2PIC Reserved Bits ................................................................... 173

5.14.10.3Read Only Registers with W rite Paths in ALT Access Mode............. 173

5.14.11System Power Supplies, Planes, and Signals ............................................ 173

5.14.11.1Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ......... 173

5.14.11.2SLP_S4# and Suspend-To-RAM Sequencing................................ 174

5.14.11.3PWROK Signal........................................................................ 174

5.14.11.4CPUPWRGD Signal .................................................................. 175

5.14.11.5VRMPWRGD Signal.................................................................. 175

5.14.11.6BAT LOW# (Battery Low) (Mobile/Ultra Mobile Only)..................... 175

5.14.11.7Controlling Leakage and Power Consumption during Low-Power

States ................................................................................... 175

5.14.12Clock Generators.................................................................................. 176

5.14.12.1Clock Control Signals from Intel® ICH7 to Clock

Synthesizer (Mobile/Ultra Mobile Only)....................................... 176

5.14.13Legacy Power Management Theory of Operation....................................... 177

5.14.13.1APM Power Management (Desktop Only).................................... 177

5.14.13.2Mobile APM Power Management (Mobile/Ultra Mobile Only)........... 177

5.15 System Management (D31:F0).......................................................................... 178

5.15.1 Theory of Operation.............................................................................. 178

5.15.1.1 Detecting a System Lockup...................................................... 178

5.15.1.2 Handling an Intruder............................................................... 178

5.15.1.3 Detecting Improper Firmware Hub Programming......................... 179

5.15.2 He artbeat and Event Reporting via SMBus (Desktop and Mobile Only) ......... 179

5.16 IDE Controller (D31:F1) ................................................................................... 183

5.16.1 PIO Transfers....................................................................................... 183

5.16.1.1 PIO IDE Timing Modes............................................................. 184

5.16.1.2 IORDY Masking....................................................................... 184

5.16.1.3 PIO 32-Bit IDE Data Po rt Acce sse s ............. .. .. ............ ............. .. 184

5.16.1.4 PIO IDE Data Port Prefetching and Posting ................................. 185

5.16.2 Bus Master Function ............................................................................. 185

5.16.2.1 Physical Region Descriptor Format............................................. 185

5.16.2.2 Bus Master IDE Timings........................................................... 186

5.16.2.3 Interrupts.............................................................................. 186

5.16.2.4 Bus Master IDE Operation........................................................ 187

5.16.2.5 Error Conditions....... .. .. ............. .................................. ............ 188

5.16.3 Ultra ATA/100/66/33 Protocol................................................................. 188

5.16.3.1 Operation .............................................................................. 189

5.16.4 Ultra ATA/33/66/100 Timing .................................................................. 190

5.16.5 ATA Swap Bay...................................................................................... 190

5.16.6 SMI Trapp ing .................... .. .. .......... ... .. .......... .. .. ........... .. ........... .. .. ...... 190

5.17 SATA Host Controller (D31:F2) (Desktop and Mobile Only).................................... 191

5.17.1 Theory of Operation.............................................................................. 192

5.17.1.1 Standard ATA Emulation .......................................................... 192

5.17.1.2 48-Bit LBA Operation.......... ... .. ............................... .. ... .. .......... 192

5.17.2 SATA Swap Bay Support........................................................................ 193

5.17.3 Intel® Matrix Storage Technology Configur ation (Intel® ICH7R, ICH7DH,

and ICH7-M DH Only) ........................................................................... 193

8Intel ® ICH7 Family Datasheet

5.17.3.1 Intel® Matrix Storage Manager RAID Option ROM ........................194

5.17.4 Power Management Operation ................................................................194

5.17.4.1 Power State Mappings..............................................................194

5.17.4.2 Power State Transitions............................................................195

5.17.4.3 SMI Trapp ing (APM).......... .. .. ...................... .. .. ..................... .. ..196

5.17.5 SATA LED ............................................................................................196

5.17.6 AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only) .........................196

5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) .................197

5.18 High Precision Event Timers ..............................................................................197

5.18.1 Timer Accuracy.....................................................................................197

5.18.2 Interrupt Mapping.................................................................................198

5.18.3 Periodic vs. Non-Periodic Modes..............................................................198

5.18.4 Enabling the Tim er s ................. .. .. ........... .. .. .......... ... .. .......... .. .. ........... ..199

5.18.5 Interrupt Levels....................................................................................199

5.18.6 Handling Interrupts...............................................................................199

5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors ..............................200

5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................200

5.19.1 Data Structures in Main Memory.............................................................200

5.19.2 Data Transfers to/from Main Memory............. .. .. .. .. ............. ............. ........200

5.19.3 Data Encoding and Bit Stuffing ...............................................................200

5.19.4 Bus Protocol .........................................................................................200

5.19.4.1 Bit Ordering............. .......... .. ... ..................... .. .. ..................... ..200

5.19.4.2 SYNC Field .............................................................................201

5.19.4.3 Packet Field Formats................................................................201

5.19.4.4 Address Fields.........................................................................201

5.19.4.5 Frame Number Field ................................................................201

5.19.4.6 Data Field ..............................................................................201

5.19.4.7 Cyclic Redundancy Check (CRC)................................................201

5.19.5 Packet Formats.....................................................................................201

5.19.6 USB Interrupts .....................................................................................201

5.19.6.1 Transaction-Based Interrupts ....................................................202

5.19.6.2 Non-Transaction Based Interrupts..............................................203

5.19.7 USB Power Management........................................................................204

5.19.8 USB Legacy Keyboard Operation.............................................................204

5.20 USB EHCI Host Controller (D29:F7)....................................................................207

5.20.1 EHC Initialization..................................................................................207

5.20.1.1 BIOS Initialization ...................................................................207

5.20.1.2 Driver Initialization..................................................................207

5.20.1. 3 EHC R e se ts........ .. .......... .. .. .. ........... .. .. ........... .. .. ........... .. .. ......208

5.20.2 Data Structures in Main Memory.............................................................208

5.20.3 USB 2.0 Enhanced Host Controller DMA ...................................................208

5.20.4 Data Encoding and Bit Stuffing ...............................................................208

5.20.5 Packet Formats.....................................................................................208

5.20.6 USB 2.0 Interrupts and Error Conditions ..................................................209

5.20.6.1 Aborts on USB 2.0- Initiated Me mory Reads................ .. .. ... .. ........209

5.20.7 USB 2.0 Power Management ..................................................................210

5.20.7.1 Pause Feature.........................................................................210

5.20.7.2 Suspend Feature.....................................................................210

5.20.7.3 ACPI Device States..................................................................210

5.20.7.4 ACPI System States.................................................................211

5.20.7.5 Mobile/Ultra Mobile Only Considerations .....................................211

5.20.8 Interaction with UHCI Host Controllers.....................................................211

5.20.8.1 Port-Routing Logic...................................................................211

5.20.8.2 Device Connects ................ .. ........... .. .. ..................... .. ... ..........213

5.20.8.3 Device Disconnects........... .. ..................... ... .. .. .........................213

5.20.8.4 Effect of Resets on Port-Routing Logic ........................................214

Intel ® ICH7 Family Datasheet 9

5.20.9 USB 2.0 Lega cy Keyboard Operation............... .. ................................ .. .. .. 214

5.20.10USB 2.0 Base d De bug P ort ....... .. .. ........... .. .. .. ........... .. .. .......... ... .. .......... 214

5.20.10.1 Theory of Operation ............................................................... 215

5.21 SMBus Controller (D31:F3)............................................................................... 219

5.21.1 Host Controller..................................................................................... 220

5.21.1.1 Command Protocols ................................................................ 220

5.21.2 Bus Arbitration..................................................................................... 224

5.21.3 Bus Timing.......................................................................................... 224

5.21.3.1 Clock Stretching ..................................................................... 224

5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)............................. 224

5.21.4 Interrupts / SMI#................................................................................. 225

5.21.5 SMBALERT# ........................................................................................ 226

5.21.6 SMBus CRC Generation and Checking...................................................... 226

5.21.7 SMBus Slave Interface.......................................................................... 226

5.21.7.1 Format of Slave Write Cycle ..................................................... 227

5.21.7.2 Format of Read Command........................................................ 229

5.21.7.3 Format of Host Notify Command ............................................... 231

5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232

5.22.1 PCI Power Management ........................................................................ 234

5.22.2 AC-Link Overview................................................................................. 234

5.22.2.1 Re g ister Acce ss ................. ... .. ....................... ......................... 236

5.22.3 AC-Link Low Power Mode....................................................................... 237

5.22.3.1 External Wake Event ....................... .. .. .. ........... .. .. ................... 238

5.22.4 AC ’97 Cold Reset................................................................................. 239

5.22.5 AC ’97 Warm Reset............................................................................... 239

5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec.......................... 239

5.23 Intel® High Definition Audio Overview................................................................ 240

5.23.1 Intel® High Definition Audio Docking (Mobile Only)................................... 240

5.23.1.1 Dock Sequence....................................................................... 240

5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241

5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242

5.23.1.4 Undock Sequen ce .............. ... .. .......... .. .. ........... .. .. .. ........... .. .. .. 242

5.23.1.5 Interaction Between Dock/Undock and Power Management

States ................................................................................... 243

5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST#.................. 243

5.24 Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)....... 244

5.24.1 Intel® AMT Features............................................................................. 244

5.24.2 Intel® AMT Requirements...................................................................... 244

5.25 Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245

5.25.1 SPI Arbitration between Intel® ICH7 and Intel PRO 82573E ....................... 245

5.25.2 Flash Device Configurations................................................................... 245

5.25.3 SPI Device Compatibility Requirements ................................................... 246

5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements

(Non-Shared Flash Configuration) ............................................. 246

5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware

Configuration Requirements (Shared Flash Configuration) ............ 246

5.25.4 Intel® ICH7 Compatible Command Set.................................................... 247

5.25.4.1 Required Command Set for Inter Operability............................... 247

5.25.4.2 Rec ommended Standard Command s.. .. .. .. ... .. .. ............ ............. .. 247

5.25.4.3 Multiple Page Write Usage Model............................................... 248

5.25.5 Flash Protection ................................................................................... 248

5.25.5.1 BIOS Ra ng e Write Protection .............. .. .. ...................... .. .. .. ...... 248

5.25.5.2 SMI# Based Global Write Protection .......................................... 249

5.25.5.3 Shared Flash Address Range Protection ...................................... 249

5.26 Intel® Quick Resume Technology (Digital Home Only) .......................................... 249

5.26.1 Visual Off............................................................................................ 249

10 Intel ® ICH7 Family Datasheet

5.26.2 CE-like On/Off......................................................................................249

5.26.3 Intel® Quick Resume Technology Signals (ICH7DH Only)............... ... .. .. ......250

5.26.4 Power Button Sequence (ICH7DH Only) ...................................................250

5.27 Feature Capability Mechanism ...........................................................................251

6 Register and Memory Mapping...............................................................................253

6.1 PCI Devices and Functions ................................................................................254

6.2 PCI Configuration Map......................................................................................255

6.3 I/O Map..........................................................................................................255

6.3.1 Fixed I/O Address Ranges......................................................................255

6.3.2 Variable I/O Decode Ranges...................................................................258

6.4 Memory Map...................................................................................................259

6.4.1 Boot -Block Up date Sc he me ............... .. ............. ............. ............ .............261

7 Chipset Configuration Registers.............................................................................263

7.1 Chipset Configuration Registers (Memory Space)..................................................263

7.1.1 VCH—Virtual Channel Capability Header Register ......................................265

7.1.2 VCAP1—Virtual Channel Capability #1 Register.........................................265

7.1.3 VCAP2—Virtual Channel Capability #2 Register.........................................266

7.1.4 PVC—Port Virtual Channel Control Register...............................................266

7.1.5 PVS—Port Virtual Channel Status Register................................................266

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register..............................267

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register..................................267

7.1.8 V0STS—Virtual Channel 0 Resource Status Register...................................268

7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register..............................268

7.1.10 V1CTL—Virtual Channel 1 Resource Control Register..................................269

7.1.11 V1STS—Virtual Channel 1 Resource Status Register...................................269

7.1.12 RCTCL—Root Complex Topology Capabilities List Register ...........................270

7.1.13 ESD—Element Self Description Register...................................................270

7.1.14 ULD—Upstream Link De scriptor Register.............. .. ............. ............. ........270

7.1.15 ULBA—Upstream Link Base Address Register............................................271

7.1.16 RP1D—Root Port 1 Descriptor Register.....................................................271

7.1.17 RP1BA—Root Port 1 Base Address Register...............................................271

7.1.18 RP2D—Root Port 2 Descriptor Register.....................................................272

7.1.19 RP2BA—Root Port 2 Base Address Register...............................................272

7.1.20 RP3D—Root Port 3 Descriptor Register.....................................................272

7.1.21 RP3BA—Root Port 3 Base Address Register...............................................273

7.1.22 RP4D—Root Port 4 Descriptor Register.....................................................273

7.1.23 RP4BA—Root Port 4 Base Address Register...............................................273

7.1.24 HDD—Intel® High Definition Audio Descriptor Register...............................274

7.1.25 HDBA—Intel® High Definition Audio Base Address Register.........................274

7.1.26 RP5D—Root Port 5 Descriptor Register.....................................................274

7.1.27 RP5BA—Root Port 5 Base Address Register...............................................275

7.1.28 RP6D—Root Port 6 Descriptor Register.....................................................275

7.1.29 RP6BA—Root Port 6 Base Address Register...............................................275

7.1.30 ILCL—Internal Link Capabilities List Register.............................................276

7.1.31 LCAP—Link Capabilities Register .............................................................276

7.1.32 LCTL—Link Control Register....................................................................277

7.1.33 LSTS—Link Status Register ....................................................................277

7.1.34 RPC—Root Port Configuration Register.....................................................278

7.1.35 RPFN—Root Port Function Number for PCI Express Root Ports

(Desktop and Mobile only) .....................................................................279

7.1.36 TRSR—Trap Status Register....................................................................280

7.1.37 TRCR—Trapped Cycle Register ................................................................280

7.1.38 TWDR—Trapped Write Data Register........................................................280

7.1.39 IOTRn — I/O Trap Register (0-3).............................................................281

Intel ® ICH7 Family Datasheet 11

7.1.40 TCTL—TCO Configuration Register........................................................... 282

7.1.41 D31IP—Device 31 Interrupt Pin Register.................................................. 283

7.1.42 D30IP—Device 30 Interrupt Pin Register.................................................. 284

7.1.43 D29IP—Device 29 Interrupt Pin Register.................................................. 285

7.1.44 D28IP—Device 28 Interrupt Pin Register (Desktop and Mobile Only)............ 286

7.1.45 D27IP—Device 27 Interrupt Pin Register.................................................. 287

7.1.46 D31IR—Device 31 Interrupt Route Register.. .. .. .. ............. ....................... .. 287

7.1.47 D30IR—Device 30 Interrupt Route Register.. .. .. .. ............. ....................... .. 289

7.1.48 D29IR—Device 29 Interrupt Route Register.. .. .. .. ............. ....................... .. 290

7.1.49 D28IR—Device 28 Interrupt Route Register.. .. .. .. ............. ....................... .. 292

7.1.50 D27IR—Device 27 Interrupt Route Register.. .. .. .. ............. ....................... .. 293

7.1.51 OIC—Other Interrupt Control Regi ster.......................... .. .. ..................... .. 294

7.1.52 RC—RTC Configuration Register.............................................................. 295

7.1.53 HPTC—High Precision Timer Configuration Register ................ ............. .. .... 295

7.1.54 GCS—Gener al Control and Status Registe r................................ ... .. .. .. ...... 296

7.1.55 BUC—Backed Up Control Register........................................................... 298

7.1.56 FD—Function Disable Register...... .......................................................... 299

7.1.57 CG—Clock Gating (Mobile/Ultra Mobile Only)............... ............ .. ... .. .. .. ...... 301

8 LAN Controller Regi sters (B1:D8: F0) (Desktop and Mobile Only)........................... 303

8.1 PCI Configuration Registers (LAN Controller—B1:D8:F0)....................................... 303

8.1.1 VID—Vendor Identification R e g i ster (LA N Cont roller—B1:D8:F0)................. 304

8.1.2 DID—Device Identification Register (LAN Controller—B1:D8:F0)............... .. 304

8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0).................... 305

8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) .......................... 306

8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ............... 307

8.1.6 SCC—Sub Class Code Register (LAN Controller—B1:D8:F0)........................ 307

8.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ...................... 307

8.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)........................ 308

8.1.9 PMLT— Primary Master Latency Timer Register (LAN Controller—B1:D8:F0)... 308

8.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0)..................... 308

8.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base

Address Register (LAN Controller—B1:D8:F0)........................................... 309

8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register

(LAN Controller—B1:D8:F0)................................................................... 309

8.1.13 SVID — Subsystem Vendor Identification (LAN Controller—B1:D8:F0) ......... 309

8.1.14 SID — Subsystem Identification (LAN Controller—B1:D8:F0)...................... 310

8.1.15 CAP_PTR — Capabilities Pointer (LAN Controller—B1:D8:F0) ...................... 310

8.1.16 INT_LN — Interrupt Line Register (LAN Controller—B1:D8 :F0)... .. ... .. .. .. ...... 310

8.1.17 INT_PN — Interrupt Pin Register (LAN Controller—B1:D8:F0)..................... 311

8.1.18 MIN_GNT — Minimum Grant Register (LAN Controller—B1:D8:F0) .............. 311

8.1.19 MAX_LAT — Maximum Latency Register (LAN Controller—B1:D8:F0)........... 311

8.1.20 CAP_ID — Capability Identification R e gister (LAN Controller—B1:D8:F0)...... 311

8.1.21 NXT_PTR — Next Item Pointer (LAN Controller—B1:D8:F0)........................ 312

8.1.22 PM_ CAP — Power Management Capabilities (LAN Controller—B1:D8:F0). ..... 312

8.1.23 PMCSR — Power Management Control/

Status Register (LAN Controller—B1:D8:F0)............................................. 313

8.1.24 PCIDATA — PCI Power Management Data Register

(LAN Controller—B1:D8:F0)................................................................... 314

8.2 LAN Control / Status Registers (CSR) (LAN Controller—B1:D8:F0).......................... 315

8.2.1 SCB_STA—System Control Block Status Word Register

(LAN Controller—B1:D8:F0)................................................................... 316

8.2.2 SCB_CMD—System Control Block Command Word

8.2.3 SCB_GENPNT—System Control Block General Pointer

12 Intel ® ICH7 Family Datasheet

8.2.4 PORT—PORT Interface Register (LAN Controller—B1:D8:F0) .......................319

8.2.5 EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0).........321

8.2.6 MDI_CNTL—Management Data Interface (MDI) Control

8.2.7 REC_D MA_BC—Receive DMA Byte Count Register

(LAN Controller—B1:D8:F0) ...................................................................322

8.2.8 EREC_INTR —Early Receive Interrupt Register

(LAN Controller—B1:D8:F0) ...................................................................323

8.2.9 FLOW_CNTL—Flow Control Register (LAN Controller—B1:D8:F0) .................323

8.2.10 PMDR—Power Management Driver Register (LAN Controller—B1:D8:F0).......324

8.2.11 GENCNTL—General Control Reg iste r (LA N Cont roller—B1:D8:F0)....... .. .. .. .. ..325

8.2.12 GENSTA—General Status Register (LAN Controller —B1 :D8 :F0 )....................326

8.2.13 SMB_PCI—SMB via PCI Register (LAN Controller—B1:D8:F0)......................326

8.2.14 Statistical Counters (LAN Controller—B1:D8:F0) .......................................327

8.3 ASF Configuration Registers (LAN Controller—B1:D8:F0).......................................329

8.3.1 ASF_RID—ASF Revision Identification Register (LAN Controller—B1:D8:F0) ..330

8.3.2 SMB_CNTL—SMBus Control Re g iste r (LA N Contro ller—B1:D8:F0) ................330

8.3.3 ASF_CNTL—ASF Control Register (LAN Controller—B1:D8:F0).....................331

8.3.4 ASF_CNTL_EN—ASF Control Enable Register (ASF Controller—B1:D8:F0) .....332

8.3.5 ENABLE—Enable Register (ASF Controller—B1:D8:F0) ...............................333

8.3.6 APM—APM Register (ASF Controller—B1:D8:F0)........................................334

8.3.7 WTIM_CONF—Watchdog Timer Configuration R egister

(ASF Controller—B1:D8:F0) ...................................................................334

8.3.8 HEART_TIM—Heartbeat Timer Register (ASF Controller—B1:D8:F0).............335

8.3.9 RETRAN_I NT—Retransmission Interval Register

(ASF Controller—B1:D8:F0) ...................................................................335

8.3.10 RETRAN_PCL—Retransmission Packet Count Limit

8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register

(ASF Controller—B1:D8:F0) ...................................................................336

8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register

(ASF Controller—B1:D8:F0) ...................................................................336

8.3.13 PET_SEQ1—PET Sequence 1 Register (ASF Controller—B1:D8:F0)...............337

8.3.14 PET_SEQ2—PET Sequence 2 Register (ASF Controller—B1:D8:F0)...............337

8.3.15 STA—Status Register (ASF Controller—B1:D8:F0) .....................................338

8.3.16 FOR_ACT—Forced Actions Register (ASF Controller—B1:D8:F0)...................339

8.3.17 RMCP_SNUM—RMCP Sequence Number Register

(ASF Controller—B1:D8:F0) ...................................................................340

8.3.18 SP_MODE—Special Modes Register (ASF Controller—B1:D8:F0) ..................340

8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register

(ASF Controller—B1:D8:F0) ...................................................................340

8.3.20 PHIST_CLR—Poll History Clear Register (ASF Controller—B1:D8:F0) ............341

8.3.21 PMSK1—Polling Mask 1 Register (ASF Controller—B1:D8:F0) ......................341

8.3.22 PMSK2—Polling Mask 2 Register (ASF Controller—B1:D8:F0) ......................342

8.3.23 PMSK3—Polling Mask 3 Register (ASF Controller—B1:D8:F0) ......................342

8.3.24 PMSK4—Polling Mask 4 Register (ASF Controller—B1:D8:F0) ......................342

8.3.25 PMSK5—Polling Mask 5 Register (ASF Controller—B1:D8:F0) ......................343

8.3.26 PMSK6—Polling Mask 6 Register (ASF Controller—B1:D8:F0) ......................343

8.3.27 PMSK7—Polling Mask 7 Register (ASF Controller—B1:D8:F0) ......................343

8.3.28 PMSK8—Polling Mask 8 Register (ASF Controller—B1:D8:F0) ......................344

9 PCI-to-PCI Bridge Registers (D30:F0)....................................................................345

9.1 PCI Configuration Registers (D30:F0) ........ .. ............. ....................... ...................345

9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0).............................346

9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) .............................346

9.1.3 PCICMD—P C I Command (PCI -P CI—D30 :F0 ) ........... .. ...................... .. .. .. ....346

Intel ® ICH7 Family Datasheet 13

9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................... 347

9.1.5 RID—R evision Ide ntification Register (PC I-PCI —D 30 :F0 ).................... .. .. .. .. 349

9.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 349

9.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0)............... 350

9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ........................ ......... 350

9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)...................................... 350

9.1.10 SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0)........... 351

9.1.11 IOBASE_LIMIT—I/O Base and Limit Register (PCI-PCI—D30:F0) ................. 351

9.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)............................ 352

9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI —D30:F0)........ 353

9.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) ..................................................... 353

9.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 354

9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)........................... 354

9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)................................... 355

9.1.20 SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0)................ 356

9.1.21 DTC—Delayed Transaction Control Register (PCI-PCI—D 30 :F0 )............. .. .. .. 357

9.1.22 BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0)....................... 359

9.1.23 BPC— B ridg e Policy Configuration Register (PCI-PCI—D 30 :F0)...... ... .. .......... 360

9.1.24 SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0).............. 361

9.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)......................... 361

10 LPC Interface Bridge Registers (D31:F0)............................................................... 363

10.1 PCI Configuration Registers (LPC I/F—D31:F0).................................................... 363

10.1.1 VID— Vendor Identification Register (LPC I/F—D31:F0)............... ... .. .......... 364

10.1.2 DID—Device Identification Register (LPC I/F—D31:F0) ............. .. ........... .. .. 364

10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 365

10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 365

10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 366

10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 366

10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)..................................... 367

10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)........... .. ............. .......... 367

10.1.9 PLT—Primary Latency Timer Re gister (LPC I/F—D31:F0) ............................ 367

10.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0).................................. 367

10.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................. 368

10.1.12CAPP—Capability List Pointer (LPC I/F—D31:F0)....................................... 368

10.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0 ) .................. .. .. .. .. 368

10.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)............................. 369

10.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0)..................... 369

10.1.16GC—GPIO Control Register (LPC I/F — D31:F0)........................................ 370

10.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) (Desktop and Mobile Only).......................................... 370

10.1.18SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0)....................... 371

10.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)................................................................................ 372

10.1.20LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) .................. 373

10.1.21LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................ 374

10.1.22GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0).... 375

10.1.23GEN2_D EC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0)..... 375

10.1.24GEN3_D EC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0)..... 376

10.1.25GEN4_D EC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0)..... 376

10.1.26FWH_SEL1 —Firmware Hub Select 1 Register (LPC I/F—D31:F0) ...... .. ......... 377

14 Intel ® ICH7 Family Datasheet

10.1.27FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0)..................378

10.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) ..378

10.1.29BIOS_CNTL—BIOS Control R e g iste r (LP C I/F—D3 1:F0 ) ............... .. ... ..........381

10.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0)........................382

10.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0)..................382

10.1.32FDVER—Feature Detection Version (LPC I/F—D31:F0)................................382

10.1.33FDVCT—Feature Vector Register (LPC I/F—D31:F0) ...................................383

10.1.34RCBA—Root Complex Base Address Register (LPC I/F—D31:F0)..................384

10.2 DMA I/O Registers (LP C I/F—D31:F0)........ .. ..................... .. ... .. .......... .. .. .............385

10.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0) ...................................................................386

10.2.2 DMABASE_CC—DMA Base and Current Count Registers (LPC I/F—D31:F0) ...387

10.2.3 DMAMEM_LP—DMA Memory Low Page Registers (LPC I/F—D31:F0).............387

10.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) ..............................388

10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0).....................................388

10.2.6 DMA_WRSMSK—DMA Write Single Mask Register (LPC I/F—D31:F0)............389

10.2.7 DMACH_MODE—DMA Channel Mode Register (LPC I/F—D31:F0) .......... .. .....39 0

10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)...................................391

10.2.9 DMA Master Clear Register (LPC I/F—D31:F0) ..........................................391

10.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................391

10.2.11DMA_WRMSK—DMA Write All Mask Register (LPC I/F—D31:F0)...................392

10.3 Timer I/O R e g i sters (LP C I/F—D3 1:F0) ................. ............ .. ... ............ .. ............. ..392

10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ...............................393

10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0) ................................................................................395

10.3.3 Counter Access Ports Register (LPC I/F—D31:F0)......................................396

10.4 8259 Interrupt Controller (PIC) Registers (LPC I/F—D31:F0) .................................396

10.4.1 Interrupt Controller I/O MAP (LP C I/F—D31:F0)................. .. .. .. .. ............. ..396

10.4.2 ICW1—Initialization Command Word 1 Register (LPC I/F—D31 :F0 )..............397

10.4.3 ICW2—Initialization Command Word 2 Register (LPC I/F—D31 :F0 )..............398

10.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LP C I/F—D3 1:F0 ) ................... ......................................398

10.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register (LP C I/F—D3 1:F0 ) ................... ......................................399

10.4.6 ICW4—Initialization Command Word 4 Register (LPC I/F—D31 :F0 )..............399

10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

10.4.8 OCW2—Operational Control Word 2 Register (LPC I/F—D31:F0)..................400

10.4.9 OCW3—Operational Control Word 3 Register (LPC I/F—D31:F0)..................401

10.4.10ELCR1—Master Controller Edge/Level Tr iggered Register (LPC I/F—D31:F0) ..402

10.4.11ELCR2—Slave Controller Edge/Level Triggered Register (LPC I/F—D31:F0) ...403

10.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................404

10.5.1 APIC Register Map (LPC I/F—D31:F0)......................................................404

10.5.2 IND—Index Register (LPC I/F—D31:F0) ...................................................404

10.5.3 DAT—Data Register (LP C I/F— D3 1 : F0 ) ......................... .. .. .. .....................405

10.5.4 EOIR—EOI Register (LP C I/F— D3 1 : F0 ) ........ .. .. .. ........... .. .. .. .....................405

10.5.5 ID—Identification Register (LPC I/F—D31:F0)...........................................406

10.5.6 VER—Version Register (LPC I/F—D31:F0).................................................406

10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)......................................407

10.6 Real Time Clock Registers (LPC I/F—D31:F0).......................................................409

10.6.1 I/O Register Address Map (LPC I/F—D31:F0)............................................409

10.6.2 Indexe d Regi sters (LP C I/F—D3 1:F0 ) ............ ............. ............ ............. ....410

10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0) ..................................411

10.6.2.2 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0).412

10.6.2.3 RTC_REGC—Register C (Flag Register) (LPC I/F—D3 1 : F0 ).............413

Intel ® ICH7 Family Datasheet 15

10.6.2.4 RTC_REGD—Register D (Flag Register) (LPC I/F—D31:F0)........... . 414

10.7 Processor Interface Registers (LPC I/F—D31:F0) ................................................. 415

10.7.1 NMI_SC—NMI Status and Control Register (LPC I/F—D31:F0) .................... 415

10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

10.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) ............................. 416

10.7.4 COPROC_ERR—Coprocessor Error Register (LPC I/F—D31:F0) .................... 417

10.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)... .............................. 417

10.8 Power Management Registers (PM—D31:F0) ....................................................... 418

10.8.1 Power Management PCI Configuration Registers (PM—D31:F0)................... 418

10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ........................................................................ 419

10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ........................................................................ 420

10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) ........................................................................ 422

10.8.1.4 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 424

10.8.1.5 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile/Ultra Mobile Only) ................................... 425

10.8.1.6 BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only) . 426

10.8.1.7 MSC_FUN—Miscellaneous Functionality Register (PM—D31:F0)...... 427

10.8.1.8 EL_STS—Intel® Quick Resume Technology Status Register

(PM—D31:F0) (ICH7DH Only)................................................... 427

10.8.1.9 EL_CNT1—Intel® Quick Resume Technology Control 1 Register

(PM—D31:F0) (ICH7DH Only)................................................... 428

10.8.1.10EL_CNT2—Intel® Quick Resume Technology Control 2 Register

(PM—D31:F0) (ICH7DH Only)................................................... 429

10.8.1.11GPIO_ROUT—GPIO Routing Control Register (PM—D31:F0) .......... 429

10.8.2 APM I/O Decode................................................................................... 430

10.8.2.1 APM_CNT—Advanced Power Management Control Port Register..... 430

10.8.2.2 APM_STS—Advanced Power Management Status Port Register ... .. . 430

10.8.3 Power Management I/O Registers........................................................... 431

10.8.3.1 PM1_STS—Power Management 1 Status Register ........................ 432

10.8.3.2 PM1_EN—Power Management 1 Enab le Regi ste r.............. .. .. .. .. .. .. 435

10.8.3.3 PM1_CNT—Power Management 1 Control ................................... 436

10.8.3.4 PM1_TMR—Power Management 1 Timer Register......................... 437

10.8.3.5 PROC_CNT—Processor Control Register......... .. .. .. .. .. .. ............. .. .. 437

10.8.3.6 LV2 — Level 2 Register (Mobile/Ultra Mobile Only)....................... 439

10.8.3.7 LV3—Level 3 Register (Mobile/Ultra Mobile Only)......................... 439

10.8.3.8 LV4—Level 4 Register (Mobile/Ultra Mobile Only)......................... 439

10.8.3.9 PM2_CNT—Power Management 2 Control Register

(Mobile/Ultra Mobile Only)........................................................ 440

10.8.3.10GPE0_STS—General Purpose Event 0 Status Register .................. 440

10.8.3.11GPE0_EN—General Purpose Event 0 Enables Register .................. 444

10.8.3.12SMI_EN—SMI Control and Enable Register ................................. 447

10.8.3.13SM I _ STS—SM I Status Register........... .. .. .................................. 449

10.8.3.14ALT_GP_SMI_EN—Alternate GPI SMI Enable Register................... 452

10.8.3.15ALT_GP_SMI_STS—Alternate GPI SMI Status Register......... ......... 452

10.8.3.16GPE_CNTL— General Purpose Control Register...... ............... ....... 453

10.8.3.17DEVACT_STS — Device Activity Status Register .......................... 454

10.8.3.18SS_CNT— Intel Speed Step® Technology

Control Register (Mobile/Ultra Mobile Only) ................................ 455

10.8.3.19C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only) ......... 455

10.9 System Management TCO Registers (D31:F0) ..................................................... 456

10.9.1 TCO_RLD—TCO Timer Reload and Current Value Register........................... 456

10.9.2 TCO_DAT_IN—TCO Data In Register........................................................ 457

10.9.3 TCO_DAT_OUT—TCO Data Out Register................................................... 457

16 Intel ® ICH7 Family Datasheet

10.9.4 TCO1_STS—TCO1 Status Register...........................................................457

10.9.5 TCO2_STS—TCO2 Status Register...........................................................459

10.9.6 TC O 1_ CNT—TC O1 Control Register.................. ................................ .. .. .. ..460

10.9.7 TC O 2_ CNT—TC O2 Control Register.................. ................................ .. .. .. ..461

10.9.8 TCO_MESSAGE1 an d TCO_MESS AGE2 Re gisters........ ... .. .......... .. .. .............461

10.9.9 TCO_WDCNT—TCO Watchdog Control Register..........................................462

10.9.10SW_IRQ_GEN—Software IRQ Generation Register.....................................462

10.9.11TCO_TMR—TCO Timer Initial Value Register..............................................462

10.10 General Purpose I/O Registers (D31:F0) .............................................................463

10.10.1GPIO_USE_SEL—GPIO Use Select Register...............................................464

10.10.2GP_IO_SEL—GPI O Input/Output Select Register........................................464

10.10.3GP_LVL—GPIO Level for Input or Output Register......................................465

10.10.4GPO_BLINK—GPO Blink Enable Register...................................................465

10.10.5GPI_INV—GPIO Signal Invert Register .....................................................466

10.10.6GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]................................466

10.10.7GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32] ........................467

10.10.8GP_LVL2—GPIO Level for Input or Output 2 Register[63:32].......................467

11 UHCI Controllers Registers ....................................................................................469

11.1 PCI Configuration R e g i sters (USB—D 29 :F0/ F1/F2 /F3)......... .. ... .. ............ .. ... ..........469

11.1.1 VID—Vendor Identification Register (USB—D29:F0/F1/F2/F3)................ .. .. .470

11.1.2 DID—Device Identification Register (USB—D29:F0/F1/F2/F3) ... ..................470

11.1.3 PCICMD—PCI Command Re g ister (US B—D29 :F0 /F1/F2 / F3 )........................470

11.1.4 PCISTS—PCI Status Register (USB—D 29 :F0/F1/F2/F3) ..............................471

11.1.5 RID—Revision Identification Register (USB—D29:F0/F1/F2/F3) ............ .......471

11.1.6 PI—Programming Interface Register (USB—D29:F0/F1/F2/F3) ................. .. .472

11.1.7 SCC—Sub Class Code Register (USB—D29:F0/F1/F2/F3)............................472

11.1.8 BCC—Base Class Code Register (USB—D29:F0/F1/F2/F3)...........................472

11.1.9 MLT—Master Latency Timer Register (USB—D29 :F0 /F1 /F2 /F3).............. ......473

11.1.10HEADTYP—Header Type Register (USB—D29:F0/F1/F2/F3).........................473

11.1.11BASE—Base Ad dress Register (USB—D29:F0/F1/F2/F3).............................474

11.1.12SVI D — Subsystem Vendor Identification Register (USB—D29:F0/F1/F2/F3).474

11.1.13SID — Subsystem Identi fication Register (USB—D29:F0/F1/F2/F3) ........ .. .. .474

11.1.14INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3)....................... .. .475

11.1.15INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3).......................... .475

11.1.16US B_RELNUM—Serial Bus Release Number Register

(USB—D29:F0/F1/F2/F3).......................................................................475

11.1.17US B_LEGKEY—USB Legacy Keyboard/Mouse Control

11.1.18US B_RES—USB Resume Enable Register (USB—D29:F0/F1/F2/F3)........... .. .478

11.1.19CWP—Core Well Policy Register (USB—D29:F0/F1/F2/F3)........... ................478

11.2 USB I/O Re gisters............................................................................................479

11.2.1 USBCMD—USB Command Register..........................................................480

11.2.2 USBSTS—USB Status Register................................................................483

11.2.3 USBINTR—USB Interrupt Enable Register.................................................484

11.2.4 FRNUM—Frame Number Register ............................................................484

11.2.5 FRBASEADD—Frame List Base Address Register........................................485

11.2.6 SOFMOD—Start of Frame Modify Register ................................................486

11.2.7 PORTSC[0,1]—Port Status and Control Register ........................................487

12 SATA Controller Registers (D3 1 :F2) (Desktop and Mobile Only).............................489

12.1 PCI Configuration R e g i sters (SATA–D31:F2 )........... .. .. .. .. ............. .. ............. .. ........489

12.1.1 VID—Vendor Identification Register (SATA—D31:F2)..................................491

12.1.2 DID—Device Identification Register (SATA—D31:F2)..................................491

12.1.3 PCICMD—PC I Comm and Register (SATA–D31:F2)............. .. .. ............. ........491

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)..........................................492

Intel ® ICH7 Family Datasheet 17

12.1.5 RID—Revision Identification Register (SATA—D31:F2) ............................... 493

12.1.6 PI—Programming Interface Register (SATA–D31:F2) ................... .............. 493

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h........... 493

12.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h........... 494

12.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h........... 494

12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)......................................... 495

12.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2).............. ....... 495

12.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2).................... 495

12.1.10PCMD_BAR—Primary Command Block Base Address

12.1.11PCNL_ BAR—Primary Control Block Base Address Register

(SATA–D31:F2).................................................................................... 496

12.1.12SCMD_BAR—Secondary Command Block Base Address

12.1.13SCNL_BA R—Secondary Control Block Base Address

12.1.14BAR — Legacy Bus Master Base Address Register (SATA–D31:F2)............... 497

12.1.15ABAR — AHCI Base Address Register (SATA–D31:F2)................................ 497

12.1.15.1Non AHCI Capable (Intel® ICH7 Feature Supported

Components Only).................. .. ..................... .. .. ..................... 497

12.1.15.2AHCI Capable (Intel® ICH7R, ICH7DH, and Mobile Only).............. 498

12.1.16SVID—Subsystem Vendor Identification Register (SATA–D31:F2)................ 498

12.1.17SID—Subsystem Identification Register (SATA–D31:F2)............................. 498

12.1.18CAP—Capabilities Pointer Register (SATA–D31:F2) .................................... 499

12.1.19INT_LN—Interrupt Line Register (SATA–D31:F2)....................................... 499

12.1.20INT_PN—Interrupt Pin Register (S ATA–D31:F2)................. .. ............. .. ...... 499

12.1.21IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2).......................... 499

12.1.22IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2)............................. 501

12.1.23SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2)................. 502

12.1.24SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2).................. 503

12.1.25IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2) .............. .. .. .. 504

12.1.26PID—PCI Power Management Capability Identification

12.1.27PC—PCI Power Management Capabilities Register (SATA–D31:F2)............... 506

12.1.28PMCS—PCI Power Management Control and Status

12.1.29MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 507

12.1.30MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2)......... 507

12.1.31MSIMA— Message Signaled Interrupt Message Address (SATA –D31:F2)....... 508

12.1.32MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............ 509

12.1.33MAP—Address Map Register (SATA–D31:F2)............................................. 509

12.1.34PCS—Port Control and Status Register (SATA–D31:F2) .............................. 510

12.1.35SIR—SATA Initialization Register ............................................................. 511

12.1.36SIRI—SATA Indexed Registers Index....................................................... 512

12.1.37STRD—SATA Indexed Register Data ........................................................ 512

12.1.37.1STTT1—SATA Indexed Registers Index 00h

(SATA TX Termination Test Register 1)....................................... 513

12.1.37.2STME—SATA Indexed Registers Index C1h

(SATA Test Mode Enable Regi ster)......... .. ............. ............. ........ 513

12.1.37.3STTT2 — SATA Indexed Registers Index 74h

(SATA TX Termination Test Register 2)....................................... 514

12.1.38SCAP0—SATA Capability Register 0 (SATA–D31:F2)................................... 514

12.1.39SCAP1—SATA Capability Register 1 (SATA–D31:F2)................................... 515

12.1.40ATC—APM Trapping Control Register (SATA–D31:F2) ................................. 516

12.1.41ATS—APM Trapping Status Re gister (SATA–D31:F2) .................................. 516

12.1.42SP — Scr atch Pad Register (SATA–D31:F2) ................... .. .. .. .. ............. .. .... 516

18 Intel ® ICH7 Family Datasheet

12.1.43BFCS—BIS T FIS Control/Status Register (SATA–D31:F2)............................517

12.1.44BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) .........................518

12.1.45BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) .........................519

12.2 Bus Master IDE I/O Registers (D31:F2)...............................................................519

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2).................. .........520

12.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ................................521

12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)........522

12.2.4 AIR—AHCI Index Register (D3 1 : F2 ).. .. ..................... ... .. .. ..................... .. ..522

12.2.5 AIDR—AHCI Index Data Register (D31:F2)...............................................522

12.3 AHCI Registers (D31:F2) (Intel® ICH7R, ICH7DH, ICH7-M, and ICH7-M DH Only) ....523

12.3.1 AHCI Generic Host Control Registers (D31:F2)..........................................524

12.3.1.1 CAP—Host Capabilities Register (D31:F2) ...................................524

12.3.1.2 GHC—Global ICH7 Control Register (D31:F2) ........ ......................526

12.3.1.3 IS—Interrupt Status Register (D31:F2) ......................................527

12.3.1.4 PI—Ports Implemented Register (D31:F2)...................................528

12.3.1.5 VS—AHCI Version (D31:F2).......... .. .. ................................ .. .. .. ..528

12.3.2 Port Registers (D31:F2).........................................................................529

12.3.2.1 PxCLB—Port [3:0] Command List Base Address Register (D31:F2).531

12.3.2.2 PxCLBU—Port [3:0] Command List Base Address Upper

32-Bits Register (D31:F2).........................................................531

12.3.2.3 PxFB—Port [3:0] FIS Base Address Register (D31:F2)..................531

12.3.2.4 PxFBU—Port [3:0] FIS Base Address Upper 32-Bits

12.3.2.5 PxIS—Port [3:0] Interrupt Status Register (D31:F2) ....................532

12.3.2.6 PxIE—Port [3:0] Interrupt Enable Register (D31:F2) ....................533

12.3.2.7 PxCMD—Port [3:0] Command Register (D31:F2) .........................535

12.3.2.8 PxTFD—Port [3:0] Task File Data Register (D31:F2).....................538

12.3.2.9 PxSIG—Port [3:0] Signature Register (D31:F2) ...........................538

12.3.2.10PxSSTS—Port [3:0] Serial ATA Status Register (D31:F2) . ..............539

12.3.2.11PxSCTL — Port [3:0] Serial ATA Control Register (D31:F2)..... .......540

12.3.2.12PxSERR—Port [3:0] Serial ATA Error Register (D31:F2).................541

12.3.2.13PxSACT—Port [3:0] Serial ATA Active (D31:F2) ................ .. .........542

12.3.2.14PxCI—Port [3:0] Command Issue Register (D31:F2) ....................543

13 EHCI Controller Registers (D29:F7) .......................................................................545

13.1 USB EHCI Configuration Registers

(USB EHCI—D29:F7)........................................................................................545

13.1.1 VID—Vendor Identification Register (USB EHCI—D29:F7)...........................546

13.1.2 DID—Device Identification Register (USB EHCI—D29:F7) ...........................546

13.1.3 PCICMD—PC I Command Re g i ster (US B EHCI—D29 :F7)........... .. ............. .. ..547

13.1.4 PCISTS—P C I Status Register (USB EHCI—D29:F7)............. .. .. .. .. ............. ..548

13.1.5 RID—Revision Identification Register (USB EHCI—D29:F7).........................549

13.1.6 PI—Programming Interface Register (USB EHCI—D29:F7)..........................549

13.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F7)..................................549

13.1.8 BCC—Base Class Code Register (USB EHCI—D29:F7) ................................549

13.1.9 PMLT—Primary Master Latency Timer Register (USB EHCI—D29:F7).............550

13.1.10MEM_BASE—Memory Base Address Register (USB EHCI—D29:F7)...............550

13.1.11SVID—USB EHCI Subsystem Vendor ID Register (USB EHCI—D29:F7) .........550

13.1.12SID—USB EHCI Subsystem ID Register (USB EHCI—D29:F7)......................551

13.1.13CAP_PTR—Capabilities Pointer Register (USB EHCI—D29:F7)......................551

13.1.14INT_LN—Interrupt Line Register (USB EHCI—D29:F7) ...............................551

13.1.15INT_PN—Interrupt Pin Register (USB EHCI—D29:F7).................................551

13.1.16PWR_CAPID—PCI Power Management Capability ID

13.1.17NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7).................552

13.1.18PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F7).............................................................................552

Intel ® ICH7 Family Datasheet 19

13.1.19PWR_ CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F7) ...................................................... 553

13.1.20DEBUG_CAPID—Debug Port Capability ID Register (USB EHCI—D29:F7)...... 554

13.1.21NXT_PT R2—Next Item Pointer #2 Register (USB EHCI—D29:F7) ................ 554

13.1.22DEBUG _BASE—Debug Port Base Offset Register (USB EHCI—D29:F7) ......... 554

13.1.23USB_RELNUM—USB Release Number Register (USB EHCI—D29:F7)............ 555

13.1.24FL_ADJ—Frame Length Adjustment Register (USB EHCI—D29:F7) .............. 555

13.1.25PWAKE_CAP—P ort Wake Capability R egister (USB EHCI—D29:F7)............... 556

13.1.26LEG_EXT_CAP—USB EHCI Legacy Support Extende d

Capability Register (USB EHCI—D29:F7).................................................. 556

13.1.27LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F7)......................................... 557

13.1.28SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..... 559

13.1.29ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) .................... 560

13.2 Memory-Mapped I/O Registers.......................................................................... 561

13.2.1 Host Controller Capability Registers ........................................................ 561

13.2.1.1 CAPLENGTH—Capability Registers Length Register....................... 561

13.2.1.2 HCIVERSION—Host Controller Interface Version Number

13.2.1.3 HCSPARAMS—Host Controller Structural Pa rameters.................... 562

13.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register........ 563

13.2.2 Host Controller Operational Registers...................................................... 564

13.2.2.1 USB2.0_CMD—USB 2.0 Command Register .... ............................ 565

13.2.2.2 USB2.0_STS—USB 2.0 Status Register ...................................... 568

13.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ....................... 570

13.2.2.4 FRINDEX—Frame Index Register............................................... 571

13.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register... .. .. . 572

13.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register.... 572

13.2.2.7 ASYNCLISTADDR—Current Asynchronous List A ddress Register.... . 573

13.2.2.8 CONFIGFLAG—Configure Flag Register....................................... 573

13.2.2.9 PORTSC—Port N Status and Control Register .............................. 573

13.2.3 USB 2.0-Based Debug Port Register........................................................ 577

13.2.3.1 CNTL_STS—Control/Status Register .......................................... 577

13.2.3.2 USBPID—U SB PID s Register........... .. .. ........... .. .. ........... .. .. ........ 580

13.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ......................... 581

13.2.3.4 CONFIG—Configuration Register ............................................... 581

14 SMBus Controller Registers (D31:F3) .................................................................... 583

14.1 PCI Configuration Registers (SMBUS—D31:F3).................................................... 583

14.1.1 VID—Vendor Identification Register (SMBUS—D31:F3) .............................. 583

14.1.2 DID—Device Identification Register (SMBUS—D31:F3) .............................. 584

14.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3) ................................. 58 4

14.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3) ....................................... 585

14.1.5 RID—Re vision Ide ntification Register (SMBUS —D 31 :F3 ) .................. .. .. .. .. .. 585

14.1.6 PI—Programming Interface Register (SMBUS—D31:F3) ............................. 586

14.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)..................................... 586

14.1.8 BCC—Base Class Code Register (SMBUS—D31:F3).................................... 586

14.1.9 SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3) ................... 586

14.1.10SVID — Subsystem Vendor Identification Register (SMBUS—D31:F2/F4) ..... 587

14.1.11SID — Subsystem Identification Register (SMBUS—D31:F2/F4).................. 587

14.1.12INT_LN—Interrupt Line Register (SMBUS—D31:F3)................................... 587

14.1.13INT_PN—Interrupt Pin Register (SMB US —D 31 :F3 )................... .. ............. .. 587

14.1.14HOSTC—Host Configuration Register (SMBUS—D31:F3)............................. 588

14.2 SMBus I/O Registers........................................................................................ 588

14.2.1 HST_STS—Host Status Register (SMBUS—D31:F3)................................... 589

14.2.2 HST_CNT—Host Control Register (SMB US —D 31 :F3)............... .. .. ............. .. 591

14.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3)............................. 593

20 Intel ® ICH7 Family Datasheet

14.2.4 XMIT_SLVA—Transmit Slave Address Register (SMBUS—D31:F3)............ .....593

14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3).....................................593

14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3).....................................593

14.2.7 Host_BLOCK_DB—Host Block Data Byte Register (SMBUS—D31:F3)............594

14.2.8 PEC—Packet Error Check (PEC) Register (SMBUS—D31:F3) ........................594

14.2.9 RCV_SLVA—Receive Slave Address Register (SMBUS—D31:F3) ...................595

14.2.10SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)........................595

14.2.11AUX _STS—Auxiliary Status Register (SMBUS—D31:F3)............................. .595

14.2.12AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) .............................596

14.2.13SMLINK_PIN_CTL—SMLink Pin Control Register (SMBUS—D31:F3) ..............596

14.2.14SMBUS_PIN_ CT L—SMBUS Pin Contro l Register (SMBUS—D31:F3) ...............597

14.2.15SLV_STS— S l ave Status Register (SMBUS —D3 1 : F3)................ ...................597

14.2.16SLV_CMD—S lave Comm and Regi ster (SM BUS —D31:F3)................... .. .. .. ....598

14.2.17NOTIFY_DADDR—Notify Device Address Register (SMBUS—D31:F3)............598

14.2.18NOTIFY_DLOW—Notify Data Low Byte Register (SMBUS—D31:F3)...............599

14.2.19NOTIFY_DHIGH—Notify Data High Byte Re gister (SMBUS—D31:F3).............599

15 IDE Controller Registers (D31:F1)..........................................................................601

15.1 PCI Configuration Registers (IDE—D 3 1:F1) ............... ............. ............ .. ............. ..601

15.1.1 VID—Vendor Identification Register (IDE—D31:F1)....................................602

15.1.2 DID—Device Identification Register (IDE—D31:F1)....................................602

15.1.3 PCICMD—PCI Command Register (IDE—D3 1 :F1 )..... .. ... .............................602

15.1.4 PCISTS — PCI Status Register (IDE—D31:F1)...........................................603

15.1.5 RID—Revision Identification Register (IDE—D31:F1)..................................603

15.1.6 PI—Programming Interface Register (IDE—D31:F1)...................................604

15.1.7 SCC—Sub Class Code Register (IDE—D31:F1) ..........................................604

15.1.8 BCC—Base Class Code Register (IDE—D31:F1).........................................604

15.1.9 CLS—Cache Line Size Register (IDE—D31:F1) ..........................................604

15.1.10PMLT—Primary Master Latency Timer Register (IDE—D31:F1).....................605

15.1.11PCMD_BA R—Primary Command Block Base Address

15.1.12PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) .....605

15.1.13SCMD_BAR—Secondary Command Block Base Address

15.1.14SCNL_BAR—Secondary Control Block Base Address

15.1.15BM_BASE — Bus Master Base Address Register (IDE—D31:F1) ...................607

15.1.16IDE_SVID — Subsystem Vendor Identification (IDE—D31:F1).....................607

15.1.17IDE_SID — Subsystem Identification Register (IDE—D31:F1) .....................607

15.1.18INTR_LN—Interrupt Line Register (IDE—D31:F1) ......................................608

15.1.19INTR_PN—Interrupt Pin Register (IDE—D31:F1)........................................608

15.1.20IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)...........................608

15.1.21IDE_TIMS — IDE Secondary Timing Register (IDE—D31:F1).......................610

15.1.22SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1) (Desktop and Mobile Only) ...............................................610

15.1.23SDM A_CNT—Synchronous DMA Control Register (IDE—D31:F1)..................611

15.1.24SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1). ..................611

15.1.25IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)......................612

15.1.26ATC—APM Trapping Control Register (IDE—D31:F1)...................................614

15.1.27ATS—APM Trapping Status Register (IDE—D31:F1)....................................614

15.2 Bus Master IDE I/O Registers (IDE—D31:F1).......................................................615

15.2.1 BMICP—Bus Master IDE Command Register (IDE—D31:F1) ........................615

15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1) ............. ................616

15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register (IDE—D31:F1) .... .617

Intel ® ICH7 Family Datasheet 21

16 AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)................. 619

16.1 AC ’97 Audio PCI Configuration Space (Audio—D30:F2)........................................ 619

16.1.1 VID—Vendor Identification Register (Aud io—D30 : F2 ) ............... .. ... .. .......... 620

16.1.2 DID—Device Identification Register (Audio—D30:F2)................................. 620

16.1.3 PCICMD—PCI Command Register (Audio—D30:F2) ................................... 621

16.1.4 PCISTS—PCI Status Register (Audio—D30:F2) ......................................... 622

16.1.5 RID—R evision Ide ntification Register (Audio—D30:F2) ........... .. .. ... .. .. .. .. .. .. 622

16.1.6 PI—Programming Interface Register (Audio—D30:F2) ............................... 623

16.1.7 SCC—Sub Class Code Register (Audio—D30:F2) ....................................... 623

16.1.8 BCC—Base Class Code Register (Audio—D30:F2)...................................... 623

16.1.9 HEADTYP—Header Type Register (Audio—D30:F2) .................................... 623

16.1.10NAMBAR—Native Audio Mixer Base Address Register (Audio—D30:F2)......... 624

16.1.11NABMBAR—Native Audio Bus Mastering Base Address

16.1.12MMBAR—Mixer Base Address Register (Audio—D30:F2)................... .. .. .. .. .. 625

16.1.13MBBAR—Bus Master Base Address Register (Audio—D30:F2)...................... 626

16.1.14SVID—Subsystem Vendor Identification Register (Audio—D30:F2) .............. 626

16.1.15SID—Su bsyste m Ide ntification Register (A ud io—D3 0 :F2)...... .. .. ..... .. .. .. ...... 627

16.1.16CAP_PTR—Capabilities Pointer Register (Audio—D30:F2) ........................... 627

16.1.17INT_LN—Interrupt Line Register (Audio—D30:F2)..................................... 627

16.1.18INT_PN—Interrupt Pin Register (A ud io—D3 0 :F2) ....................... ... ............ 628

16.1.19PCID—Programmable Codec Identification Register (Audio—D30:F2)........... 6 28

16.1.20CFG—Configuration Register (Audio—D30:F2).......................................... 628

16.1.21PID—PCI Power Management Capability Identification

16.1.22PC—Power Management Capabilities Register (Audio—D30:F2)................... 629

16.1.23PCS—Power Management Control and Status Register (Audio—D30:F2)....... 630

16.2 AC ’97 Audio I/O Space (D30:F2) ...................................................................... 631

16.2.1 x_BDBAR—Buffer Descriptor Base Address Register (Audio—D30:F2) ..... .. ... 635

16.2.2 x_CIV—Current Index Value Register (Audio—D30:F2) ................... ........... 635

16.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2) .................................... 636

16.2.4 x_SR—Status Registe r (A udio—D30:F2) .............. .. ... .. .. .. .. ............. .. ........ 636

16.2.5 x_PICB—Position In Current Buffer Register (Audio—D30:F2)..................... 638

16.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2) .......................... 638

16.2.7 x_CR—Control Register (Audio—D30:F2)................................................. 639

16.2.8 GLOB_CNT—Global Control Register (Audio—D30:F2).................. .............. 640

16.2.9 GLOB_STA—Global Status Register (Audio—D30:F2)................................. 642

16.2.10CAS—Cod e c Acce ss Sem aphore R e gister (A udio—D30:F2) ............. .. .. .. .. .. .. 644

16.2.11SDM—SDATA_IN Map Register (Audio—D30:F2) ....................................... 645

17 AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)............... 647

17.1 AC ’97 Modem PCI Configuration Space (D30:F3) ................................................ 647

17.1.1 VID—Vendor Identification Register (Modem—D30:F3) .............................. 648

17.1.2 DID—Device Identification Register (Modem—D30:F3) .............................. 648

17.1.3 PCICMD—PCI Command Register (Modem—D30:F3) ...................... ........... 648

17.1.4 PCISTS—PCI Status Register (Modem—D30:F3) ....................................... 649

17.1.5 RID—Revision Identification Register (Modem—D30:F3) ............................ 650

17.1.6 PI—Programming Interface Register (Modem—D30:F3) ............................. 650

17.1.7 SCC—Sub Class Code Register (Modem—D30:F3)..................................... 650

17.1.8 BCC—Base Class Code Register (Modem—D30:F3).................................... 650

17.1.9 HEADTYP—Header Type Register (Modem—D30:F3).................................. 650

17.1.10MMBAR—Modem Mixer Base Address Register (Modem—D30:F3)..... .. .. .. .. ... 651

17.1.11MBAR—Modem Base Address Register (Modem—D30:F3)........................... 651

17.1.12SVID—Subsystem Vendor Identification Register (Modem—D30:F3)....... ..... 652

17.1.13SID—Subsystem Identification Register (Modem—D30:F3) ......... ... .. .......... 652

22 Intel ® ICH7 Family Datasheet

17.1.14CAP_PTR—Capabilities Pointer Register (Modem—D30:F3)..........................652

17.1.15INT_LN—Interrupt Line Register (Modem—D30:F3)...................................653

17.1.16INT_PIN—Interrupt Pin Register (Modem—D30:F3) ...................................653

17.1.17PID—PCI Power Management Capability Identification

17.1.18PC—Power Management Capabilities Register (Modem—D30:F3).............. ...654

17.1.19PCS—Power Management Control and Status Register (Modem—D30:F3).....654

17.2 AC ’97 Modem I/O Space (D30:F3) ....................................................................655

17.2.1 x_BDBAR—Buffer Descriptor List Base Address Register (Modem—D30:F3)...657

17.2.2 x_CIV—Current Index Value Register (Modem—D30:F3) ............................657

17.2.3 x_LVI—Last Valid Index Register (Mode m —D 30 :F3 )... ... .. .. ............ ... ..........657

17.2.4 x_SR—Status Register (Modem—D30:F3).................................................658

17.2.5 x_PICB—Position in Current Buffer Register (Modem—D30:F3) ...................659

17.2.6 x_PIV—Prefetch Index Value Register (Modem—D30:F3)............................659

17.2.7 x_CR—Control Register (Modem—D30:F3) ...............................................660

17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3)..............................661

17.2.9 GLOB_STA—Global Status Register (Modem—D30:F3) ...............................662

17.2.10CAS—Codec Access Semaphore Register (Modem—D30:F3) .......................664

18 PCI Express* Configuration Registers (Desktop and Mobile Only)..........................665

18.1 PCI Express* Configuration Registers

(PCI Express—D28:F0/F1/F2/F3/F4/F5)..............................................................665

18.1.1 VID—Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................667

18.1.2 DID—Device Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................667

18.1.3 PCICMD—PCI Command Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................667

18.1.4 PCISTS—PCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................668

18.1.5 RID—Revision Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................669

18.1.6 PI—Programming Interface Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................669

18.1.7 SCC—Sub Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................669

18.1.8 BCC—Base Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................670

18.1.9 CLS—Cache Line Size Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................670

18.1.10PLT—Primary Latency Timer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................670

18.1.11HEADTYP—Header Type Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................670

18.1.12BNUM—Bus Number Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................671

18.1.13IOBL—I/O Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................671

18.1.14SSTS—Secondary Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................672

18.1.15MBL—Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................673

18.1.16PMBL—Prefetchable Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................673

18.1.17PMBU32—Prefetc hab le Memory Base Upper 32 Bits

Intel ® ICH7 Family Datasheet 23

18.1.18PMLU 32—Prefetchable Memory Limit Upper 32 Bits

18.1.19CAPP—Capabilities List Pointer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 674

18.1.20INTR—Interrupt Information Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 675

18.1.21BCTRL—Bridge Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 676

18.1.22CLIST—Capabilities List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677

18.1.23XCAP—PCI Express* Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 677

18.1.24DCAP—Device Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 678

18.1.25DCTL—Device Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 679

18.1.26DS TS—Device Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 680

18.1.27LCAP—Link Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 681

18.1.28LCTL—Link Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 682

18.1.29LSTS—Link Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ............ 683

18.1.30SLCAP—Slot Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 684

18.1.31SLCTL—Slot Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5).......... 685

18.1.32SL STS—Slot Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 686

18.1.33RCTL—Root Control Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)........... 687

18.1.34RSTS—Root Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ........... 687

18.1.35MID—Message Signaled Interrupt Identifiers Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688

18.1.36MC—Message Signaled Interrupt Message Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 688

18.1.37MA—Message Signaled Interrupt Message Address

18.1.38MD—Message Signaled Interrupt Message Data Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.39SVCAP—Subsystem Vendor Capability Re gister

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.40SVID—Subsystem Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.41PMCAP — Power Management Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 689

18.1.42PMC—PCI Power Management Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 690

18.1.43PMCS—PCI Power Management Control and Status

18.1.44MPC—Miscellaneous Port Configuration Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 691

18.1.45SM SCS—SMI/SCI Status Register (PCI Express—D28:F0/F1/F2/F3/F4/F5) ... 693

18.1.46RPDCGEN - Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)............... .................. 694

18.1.47IPWS—Intel® PRO/Wireless 3945ABG Status

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only)............................... 694

18.1.48VCH—Virtual Channel Capability Header Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)................................................... 695

24 Intel ® ICH7 Family Datasheet

18.1.49VCAP2—Virtual Channel Capability 2 Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................695

18.1.50PVC—Port Virtual Channel Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................695

18.1.51PVS — Port Virtual Channel Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................696

18.1.52V0CAP — Virtual Channel 0 Resource Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................696

18.1.53V0CTL — Virtual Channel 0 Resource Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................697

18.1.54V0STS — Virtual Channel 0 Resource Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................697

18.1.55UES — Uncorrectable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................698

18.1.56UEM — Uncorrectable Error Mask

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................699

18.1.57UEV — Uncorrectable Error Severity

Q(PCI Express—D28:F0/F1/F2/F3/F4/F5).................................................700

18.1.58CES — Correctable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................701

18.1.59CEM — Correctable Error Mask Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................701

18.1.60AECC — Advanced Error Capabilities and Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................702

18.1.61RES — Root Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................702

18.1.62RCTCL — Root Complex Topology Capability List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.63ES D — Element Self Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................703

18.1.64ULD — Upstream Link Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

18.1.65ULBA — Upstream Link Base Address Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

18.1.66PEETM — PCI Express Extended Test Mode Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)...................................................704

19 Intel® High Definition Audio Controller Registers (D27:F0)....................................705

19.1 Intel® High Definition Audio PCI Configuration Space (Intel® High Definition

Audio— D27:F0)..............................................................................................705

19.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................707

19.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................707

19.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0) .....................................708

19.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................709

19.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0) .....................................709

19.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

19.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0) .....................................710

Intel ® ICH7 Family Datasheet 25

19.1.10LT—Laten cy Timer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 710

19.1.11HEADTYP—Header Typ e Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 711

19.1.12HDBARL—Intel® High Definition Audio Lower Base Address Register

(Intel® High Definition Audio—D27:F0) ................................................... 711

19.1.13HDBARU—Intel® High Definition Audio Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 711

19.1.14SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 712

19.1.15SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 712

19.1.16CAPPTR—Capabilities Pointer Register (Audio—D30:F2) ............................. 713

19.1.17INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 713

19.1.18INTP N—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 713

19.1.19HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 714

19.1.20TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 715

19.1.21DCKCTL—Docking Control Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)..................................... 715

19.1.22DCKSTS—Docking Status Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile Only) ................. 716

19.1.23PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 716

19.1.24PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 716

19.1.25PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 717

19.1.26MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.27MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.28MML A—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.29MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 718

19.1.30MMD—MSI Message Data R egister

(Intel® High Definition Audio Controller—D27:F0)..................................... 719

19.1.31PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) (Desktop and Mobile Only)7 19

19.1.32PXC—PCI Express* Capabilities Register (Desktop and Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)..................................... 719

19.1.33DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 720

19.1.34DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 721

19.1.35DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 721

19.1.36VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only) ....... .. ................................ .. .. .. ..................... 722

19.1.37PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only) ....... .. ................................ .. .. .. ..................... 722

26 Intel ® ICH7 Family Datasheet

19.1.38PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0) .....................................722

19.1.39PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.40PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.41VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................723

19.1.42VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................724

19.1.43VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................724

19.1.44VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................725

19.1.45VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................725

19.1.46VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................726

19.1.47RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register (Intel® High Definition Audio

Controller—D27:F0) (Desktop and Mobile Only) ........................................726

19.1.48ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0) .....................................726

19.1.49L1DE SC—Link 1 Description Re g i s ter

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.1.50L1A DDL—L ink 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.1.51L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) .....................................727

19.2 Intel® High Definition Audio Memory-Mapped Configuration Registers

(Intel® High Definition Audio— D27:F0)..............................................................728

19.2.1 GCAP—Global Capabilitie s Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0) .....................................732

19.2.4 OUTPAY—Output Pa yload Capabilit y Register

(Intel® High Definition Audio Controller—D27:F0) .....................................733

19.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0) .....................................733

19.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................734

19.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0) .....................................735

19.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................735

19.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0) .....................................736

19.2.10ECAP—Extended Capabilities

(Intel® High Definition Audio Controller—D27:F0) .....................................737

19.2.11OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .....................................737

19.2.12INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0) .....................................738

19.2.13INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0) .....................................739

Intel ® ICH7 Family Datasheet 27

19.2.14INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 740

19.2.15WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 741

19.2.16SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 741

19.2.17CORBLBAS E—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.18CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.19CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 742

19.2.20CORBRP—CORB Read Pointer R egister

(Intel® High Definition Audio Controller—D27:F0)..................................... 743

19.2.21CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 743

19.2.22CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 744

19.2.23CORBSI ZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0)...................................... 744

19.2.24RIRBLBASE—RIRB Lower Base Addre ss Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 744

19.2.25RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 745

19.2.26RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 745

19.2.27RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 746

19.2.28RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 746

19.2.29RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.30RIRBSIZE—RIRB Size Re gister

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.31IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 747

19.2.32IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 748

19.2.33IRS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 748

19.2.34DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 749

19.2.35DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 749

19.2.36SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 750

19.2.37SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 752

19.2.38SDLPIB—Stream Descriptor Link Position in Buffer

19.2.39SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 753

19.2.40SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 754

19.2.41SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0)..................................... 754

28 Intel ® ICH7 Family Datasheet

19.2.42SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) .....................................755

19.2.43SDF MT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) .....................................756

19.2.44SDBDPL—Stream Descriptor Buffer Descriptor List Pointer Lower Base

Address Register (Intel® High Definition Audio Controller—D27:F0).............757

19.2.45SDBDPU—Stream Descriptor Buffer Descriptor List PointerUpper Base

Address Register (Intel® High Definition Audio Controller—D27:F0).............757

20 High Precision Event Timer Registers.....................................................................759

20.1 Memory Mapped Registers ................................................................................759

20.1.1 GCAP_ID—General Capabilities and Identification Register....................... .. .760

20.1.2 GEN_CONF—General Configuration Register .............................................761

20.1.3 GINTR_STA—General Interrupt Status Register.........................................761

20.1.4 MAIN_CNT—Main Counter Valu e Register ................. ............. ............. .. ....762

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Re gister......................762

20.1.6 TIMn_COMP—Timer n Comparator Value Register......................................764

21 Serial Peripheral Interface ( SPI) (Desktop and Mobile Only) .................................765

21.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................765

21.1.1 SPIS—SPI Status Register (SPI Memory Mapped Configuration

Registers)............................................................................................767

21.1.2 SPIC—SPI Control Register (SPI Memory Mapped Configuration

Registers)............................................................................................768

21.1.3 SPIA—SPI Address Register (SPI Memory Mapped Configuration

Registers)............................................................................................769

21.1.4 SPID[N] —SPI Data N Register (SPI Memory Mapped Configuration

Registers)............................................................................................769

21.1.5 BBAR—BIOS Base Address Register

(SPI Memory Mapped Configuration Registers)..........................................770

21.1.6 PREOP—Prefix Opcode Configuration Re gister

(SPI Memory Mapped Configuration Registers)..........................................770

21.1.7 OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers)..........................................771

21.1.8 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers)..........................................772

21.1.9 PBR[N]—Protected BIOS Range [N]

(SPI Memory Mapped Configuration Registers)..........................................772

22 Ballout Definition...................................................................................................773

22.1 Desktop , Mo bile , and Dig i tal Home Component Ballout............... .. .. ............. .. .. ......773

22.2 Ultra Mobile Component Ballout.........................................................................782

23 Electrical Characteristics........................................................................................789

23.1 Thermal Spe cifications.......... .. .. ................................ .. .. .. ..................... ... .. .. ......789

23.2 Absolute Maximum Ratings ...............................................................................789

23.3 DC Char acte ristics ............... .. .. ..................... ... .. .. ..................... .. .. .. .................790

23.4 AC Char acte ristics......................... .. .. .. ..................... .. .. .. ..................... ... .. .. ......801

23.5 Timing Diagrams ............. .. ........... .. .. .......... .. ... .......... .. .. ........... .. ........... .. .. ......817

24 Package Information .............................................................................................835

24.1 Desktop and Mobile Package Information ............................................................835

24.2 Ultra Mobile Package Information.......................................................................837

25 Testability (Desktop and Mobile Only)....................................................................839

25.1 XOR Chain Tables.............................................................................................841

Intel ® ICH7 Family Datasheet 29

Figures

2-1 Interface Signals Block Diagram (Desktop Only)...........................................................52

2-2 Interface Signals Block Diagram (Mobile Only) ............................................................53

2-3 Interface Signals Block Diagram (Ultra Mobile Only) .....................................................54

2-4 Example External RTC Circuit.....................................................................................78

4-1 Desktop Only Conceptual System Clock Diagram..........................................................96

4-2 Mobile Only Conceptual Clock Diagram........................................................................96

4-3 Ultra Mobile Only Conceptual Clock Diagram................................................................97

5-1 Generation of SERR# to Platform ............................................................................. 105

5-2 64-Word EEPR OM Read Instruction Waveform.... ........................................................ 112

5-3 LPC Interface Diagram............................................................................................ 118

5-4 LPC Bridge SERR# Generation ................................................................................. 123

5-5 Intel® ICH7 DMA Controller..................................................................................... 124

5-6 DMA Request Assertion through LDRQ# .................................................................... 127

5-7 Coprocessor Error Timing Diagram ........................................................................... 151

5-8 Physical Region Descriptor Table Entry...................................................................... 186

5-9 SATA Power States................................................................................................. 195

5-10USB Legacy Keyboard Flow Diagram......................................................................... 205

5-11 Intel® ICH7-USB Port Connections ......... .......... .. ... .. ..................... .. .. .. ..................... 212

5-12Intel® ICH7-Based Audio Codec ’97 Specification, Version 2.3...................................... 233

5-13AC ’97 2.3 Controller-Codec Connection.................................................................... 235

5-14AC-Link Protocol .................................................................................................... 236

5-15AC-Link Powerdown Timing ..................................................................................... 237

5-16SDIN Wake Signaling.............................................................................................. 238

22-1 Desktop and Mobile Component Ballout (Topview–Left Side)....................................... 774

22-2Desktop and Mobile Component Ballout (Topview–Right Side)...................................... 775

22-3Intel® ICH7-U Ballout (top view, left side)................................................................. 782

22-4Intel® ICH7-U Ballout (top view, right side)............................................................... 783

23-1Clock Timing ......................................................................................................... 817

23-2Valid Delay from Rising Clock Edge........................................................................... 817

23-3Setup and Hold Times............................................................................................. 817

23-4Float Delay ........................................................................................................... 818

23-5Pulse Width........................................................................................................... 818

23-6Output Enable Delay............................................................................................... 818

23-7IDE PIO Mode........................................................................................................ 819

23-8IDE Multiword DMA ................................................................................................ 819

23-9Ultra ATA Mode (Drive Initiating a Burst Read)........................................................... 820

23-10Ultra ATA Mode (Sustained Burst) .......................................................................... 820

23-11Ultra ATA Mode (Pausing a DMA Burst).................................................................... 821

23-12Ultra ATA Mode (Terminating a DMA Burst).............................................................. 821

23-13USB Rise and Fall Times........................................................................................ 822

23-14USB Jitter............................................................................................................ 822

23-15USB EOP Width.................................................................................................... 822

23-16SMBus Tran saction........... .. .. ..................... .. .. ..................... ... .. ..................... .. .. .... 823

23-17SMBus Tim eou t... .. .. ........... .. .. ........... .. .. .......... ... .. ..................... .. .. ........... .. .. ........ 823

23-18Power Sequencing and Reset Signal Timings (Desktop Only)...................................... 824

23-19Power Sequencing and Reset Signal Timings (Mobile/Ultra Mobile Only)....................... 825

23-20G3 (Mechanical Off) to S0 Timings (Desktop Only).................................................... 826

23-21G3 (Mechanical Off) to S0 Timings (Mobile/Ultra Mobile Only) .................................... 827

23-22S0 to S1 to S0 Timing (Desktop Only)..................................................................... 827

23-23S0 to S5 to S0 Timings, S3COLD (Desktop Only)........................................................ 828

23-24S0 to S5 to S0 Timings, S3HOT (Desktop Only)......................................................... 829

23-25S0 to S5 to S0 Timings, S3COLD (Mobile/Ultra Mobile Only) ........................................ 830

23-26S0 to S5 to S0 Timings, S3HOT (Mobile/Ultra Mobile Only).......................................... 831

30 Intel ® ICH7 Family Datasheet

23-27C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................831

23-28C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................832

23-29C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only) ....................................................832

23-30AC ’97 Data Input and Output Timings (Desktop and Mobile Only)...............................833

23-31Intel® High Definition Audio Input and Output Timings ..............................................833

23-32SPI Timings (Desktop and Mobile Only) ...................................................................834

24-1Intel® ICH7 Package (Top View).................................................... .. .. .. .....................835

24-2Intel® ICH7 Package (Bottom View)............. .. .. .. .......................................................836

24-3Intel® ICH7 Package (Side View)................... .. ........... .. .. ..................... .. .. .................836

24-4Intel ICH7-U Package Drawing .................................................................................837

25-1XOR Chain Test Mode Selection, Entry and Testing......................................................839

25-2Example XOR Chain Circuitry ........................ .. .........................................................840

Tables

1-1 Industry Specifications......................................... ... .. .. ..................... .. .. .. ...................39

1-2 PCI Devices and Functions.........................................................................................43

1-3 Intel® ICH7 Desktop/Server Family ............................................................................50

1-4 Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components...........................................50

2-1 Direct Media Interface Signals....................................................................................55

2-2 PCI Express* Signals ................................................................................................55

2-3 Platform LAN Connect Interface Signals.......................................................................56

2-4 EEPROM In terface Signals..................... .. .. .......... .. ... .......... .. ........... .. .. ........... .. .. ........56

2-5 Firmware Hub Interface Signals..................................................................................56

2-6 PCI Interface Signals ................................................................................................57

2-7 Serial ATA Interface Signals........... .. ........... .. .. .. ..................... .. ... .. ..................... .. .. .. ..59

2-8 IDE Interface Signals ................................................................................................60

2-9 LPC Interface Signals................................................................................................62

2-10Interrupt Signals......................................................................................................62

2-11USB Interface Signals ................. .. ........... .. .. ..................... .. .. ..................... ... .. ..........63

2-12Power Management Interface Signals..........................................................................64

2-13Processor Interface Signals........................................................................................66

2-14SM Bus Interface Signals................................ .. .. .. ........... .. .. ..................... .. ... ............68

2-15System Management Interface Signals........................................................................68

2-16Real Time Clock Interface. .........................................................................................69

2-17Other Clocks...................... .. .. ........... .. .. .. .......... .. ... .......... .. .. ........... .. .. ........... .. .. ......69

2-18Miscellaneous Signals................................................................................................70

2-19AC ’97/Intel® High Definition Audio Link Signals...........................................................71

2-20Serial Peripheral Interface (SPI) Signals ......................................................................72

2-21General Purpose I/O Signals ......................................................................................72

2-22Pow er and Ground Si gnals............... ... .. .. .......... .. .. ...................... .. .. ..................... .. .. ..74

2-23Functional Strap Definitions .......................................................................................76

3-1 Integrated Pull-Up and Pull-Down Resistors..................................................................79

3-2 IDE Series Termination Resistors................................................................................80

3-3 Power Plane and States for Output and I/O Signals for Desktop Only Configurations..........81

3-4 Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile Only

Configurations .........................................................................................................86

3-5 Power Plane for Input Signals for Desktop Only Configurations .......................................90

3-6 Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations ........................92

4-1 Intel® ICH7 and System Clock Domains ......................................................................95

5-1 PCI Bridge Initiator Cycle Types .................................................................................99

5-2 Type 1 Address Format ...........................................................................................102

5-3 MSI vs. PCI IRQ Actions ..................... .. ...................................................................104

5-4 Advanced TCO Functionality.....................................................................................114

5-5 LPC Cycle Types Supported......................................................................................119

Intel ® ICH7 Family Datasheet 31

5-6 Start Field Bit Definitions ................... .. .. .. .. ............................................................. 119

5-7 Cycle Type Bit Definitions.. .. .. .. ............. .......... .. .. ... ..................... .. .. .. ..................... .. 120

5-8 Transfer Size Bit Definition...................................................................................... 120

5-9 SYNC Bit Definition ................................................................................................. 121

5-10DMA Transfer Size.................................................................................................. 126

5-11Address Shifting in 16-Bit I/O DMA Transfers............................................................. 126

5-12Counter Operating Modes........................................................................................ 131

5-13Interrupt Controller Core Connections....................................................................... 133

5-14Interrupt Status Registers....................................................................................... 134

5-15Content of Interrupt Vector Byte.............................................................................. 134

5-16APIC Interrupt Mapping .......................................................................................... 140

5-17Interrupt Message Address Format........................................................................... 142

5-18Interrupt Message Data Format ............................................................................... 143

5-19Stop Fram e Exp l anation................ ... ..................... .. .. .. .......... ... .. ..................... .. .. .... 144

5-20Data Frame Format.............. .. .. ........... .. .. .. ........... .. .. ..................... .. .. ..................... 145

5-21Configuration Bits Reset by RTCRST# Assertion ......................................................... 148

5-22INIT# Going Active ................................................................................................ 150

5-23NMI Sources.......................................................................................................... 151

5-24DP Signal Differences ............................................................................................. 152

5-25General Power States for Systems Using Intel® ICH7.............. .. ... .......... .. ........... .. ...... 153

5-26State Transition Rules for Intel® ICH7 ..... .. .. ........... .. .......... .. ........... .. .. ........... .. ........ 155

5-27System Power Plane............................................................................................... 156

5-28Causes of SMI# and SCI......................................................................................... 157

5-29Break Events (Mobile/Ultra Mobile Only).................................................................... 160

5-30Sleep Types .......................................................................................................... 163

5-31Causes of Wake Events........................................................................................... 164

5-32GPI Wake Events ................................................................................................... 165

5-33Transitions Due to Power Failure.............................................................................. 166

5-34Transitions Due to Power Button .............................................................................. 167

5-35Transitions Due to RI# Signal.................................................................................. 168

5-36Write Only Registers with Read Paths in ALT Access Mode ........................................... 171

5-37PIC Reserved Bits Return Values.............................................................................. 173

5-38Register Write Accesses in ALT Access Mode.............................................................. 173

5-39Intel® ICH7 Clock Inputs ........................................................................................ 176

5-40Heartbeat Message Data......................................................................................... 182

5-41 IDE Transaction Timings (PCI Clocks) ...................................................................... 184

5-42Interrupt/Active Bit Interaction Definition.................................................................. 188

5-43SATA Features Support in Intel® ICH7...................................................................... 191

5-44SATA Feature De scription.............. ... .. .. .......... .. .. ... .......... .. .. .. ...................... .. .. .. ...... 192

5-45Legacy Re placement Routing.............. .......... .. .. ........... .. .. ........... .. .. .......... ... .. .......... 198

5-46Bits Maintained in Low Power States......................................................................... 204

5-47USB Legacy Keyboard State Transitions .................................................................... 205

5-48UHCI vs. EHC I................. .. .. ........... .. .......... .. .. ........... .. .. ........... .. .. .......... ... .......... .. 207

5-49Debug Port Behavior .............................................................................................. 215

5-50I2C Block Read ...................................................................................................... 223

5-51Enable for SMBALERT#........................................................................................... 225

5-52Enables for SMBus Slave Write and SMBus Host Events............................................... 225

5-53Enables for the Host Notify Command................ .. ... .. .. ............ ............. ............. ........ 226

5-54Slave Write Registers ............................................................................................. 227

5-55Command Types.................................................................................................... 228

5-56Read Cycle Format.................................... .. .. .. ........... .. .. ..................... .. .. ............... 229

5-57Data Values for Slave Read Registers........................................................................ 229

5-58Host Notify Format................................................................................................. 231

5-59Features Supported by Intel® ICH7.......................................................................... 232

5-60Output Tag Slot 0 .................................................................................................. 237

32 Intel ® ICH7 Family Datasheet

5-61SPI Implementation Options ....................................................................................245

5-62Require d Comm ands and Opcodes................. .. .. ................................ .. .. .. .................247

5-63Intel® ICH7 Standard SPI Commands .............. .. .. .. ............. ....................... ...............247

5-64Flash Protection Mechanism Summary.......................................................................248

6-1 PCI Devices and Functions.......................................................................................254

6-2 Fixed I/O Ranges Decoded by Intel® ICH7.................................................................256

6-3 Variable I/O Decode Ranges..... .. .. .. ............. .............................................................258

6-4 Memory Decode Ranges from Processor Perspective....................................................259

7-1 Chipset Configuration Register Memory Map (Memory Space).......................................263

8-1 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) ...........................303

8-2 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ..........................310

8-3 Data Register Structure...........................................................................................314

8-4 Intel® ICH7 Integrated LAN Controller CSR Space Register Address Map........................315

8-5 Self-Test Results Format .........................................................................................320

8-6 Statistical Counters............................................ .. ... .. ..................... .. .. .. ...................327

8-7 ASF Register Address Map .......................................................................................329

9-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0)...................................................345

10-1LPC Interface PCI Register Address Map (LPC I/F—D31:F0)..........................................363

10-2DMA Registers .......................................................................................................385

10-3PIC Registers (LPC I/F—D31:F0)...............................................................................396

10-4APIC Direct Registers (LPC I/F—D31:F0) ...................................................................404

10-5APIC Indirect Registers (LPC I/F—D31:F0).................................................................404

10-6RTC I/O Registers (LPC I/F—D31:F0) ........................................................................409

10-7RTC (Standard) RAM Bank (LPC I/F—D31:F0) ............................................................410

10-8Processor Interface PCI Register Address Map (LPC I/F—D31:F0)..................................415

10-9Power Manag e me nt PCI Reg i ster Address Map (PM—D31 :F0) ............ .. .. .. ............. .. ......418

10-10APM Register Map.................................................................................................430

10-11ACPI and Legacy I/O Register Map..........................................................................431

10-12TCO I/O Register Address Map ...............................................................................456

10-13Registers to Control GPIO Address Map....................................................................463

11-1UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3) .............................469

11-2USB I/O Registers .............. .. .......... ... .. ..................... .. .. ..................... .. .. .................479

11-3Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation..................482

12-1SATA Controller PCI Register Address Map (SATA–D31:F2) ..........................................489

12-2Bus Master IDE I/O Register Address Map..................................................................519

12-3AHCI Register Address Map......................................................................................523

12-4Generic Host Controller Register Address Map .... .. ......................................................524

12-5Port [3:0] DMA Register Address Map .......................................................................529

13-1USB EHCI PCI Re g ister Address Map (USB EHCI—D29:F7) ........... ... .. .. ............ ... ..........545

13-2Enhanced Host Controller Capability Registers............................................................561

13-3Enhanced Host Controller Operational Register Address Map ........................................564

13-4Debug Port Register Address Map.............................................................................577

14-1SMBus Controller PCI Register Address Map (SMBUS—D31:F3).....................................583

14-2SMBus I/O Register Address Map..............................................................................588

15-1IDE Controller PCI Register Address Map (IDE-D31:F1) ...............................................601

15-2Bus Master IDE I/O Registers...................................................................................615

16-1AC ‘97 Audio PCI Register Address Map (Audio—D30:F2).............................................619

16-2Intel® ICH7 Audio Mixer Register Configuration..........................................................631

16-3Native Audio Bus Master Control Registers.................................................................633

17-1AC ‘97 Modem PCI Register Address Map (Modem—D30:F3) ........................................647

17-2Intel® ICH7 Modem Mixer Register Configuration........................................................655

17-3Modem Registers....................................................................................................656

18-1PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5).....................................................................665

Intel ® ICH7 Family Datasheet 33

19-1Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)................ .. ............. ....................... ................. 705

19-2Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)................ .. ............. ....................... ................. 728

20-1Memory-Mapped Registers ...................................................................................... 759

21-1Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers)........................................................... 765

22-1 Desktop and Mobile Component Ballout by Signal Name............................................. 776

22-2Intel® ICH7-U Ballout by Signal Name...................................................................... 784

23-1Intel® ICH7 Absolute Maximum Ratings.................................................................... 789

23-2DC Current Characteristics ...................................................................................... 790

23-3DC Current Characteristics (Mobile/Ultra Mobile Only)................................................. 791

23-4DC Characteristic Input Signal Association................................................................. 792

23-5DC Input Characteristics ......................................................................................... 794

23-6DC Characteristic Output Signal Association............................................................... 796

23-7DC Output Characteristics ....................................................................................... 798

23-8Other DC Characteristics......................................................................................... 799

23-9Clock Timings........................................................................................................ 801

23-10PCI Interface Timing............................................................................................. 803

23-11IDE PIO Mode Timings .......................................................................................... 804

23-12IDE Multiword DMA Timings................................................................................... 804

23-13Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ............................................................ 805

23-14Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ............................................................ 807

23-15Universal Serial Bus Timing ................................................................................... 809

23-16SATA Interface Timings (Desktop and Mobile Only)................................................... 810

23-17SMBus Tim i ng............ .. .. .......... .. ... .......... .. .. ........... .. .......... ... .. .......... .. .. ........... .. .. 810

23-19LPC Tim i ng...................... .. ........... .. .. .......... .. .. ........... .. .. ........... .. .. ........... .. .......... 811

23-20Miscellaneous Timings........................................................................................... 811

23-18AC ’97 / Intel® High Definition Audio Timing.............. .............................................. 811

23-21SPI Timings (Desktop and Mobile Only). .................................................................. 812

23-22(Power Sequencing and Reset Signal Timings. .......................................................... 812

23-23Power Management Timings .................................................................................. 814

25-1XOR Test Pattern Example ...................................................................................... 840

25-2XOR Chain 1 (REQ[4:1]# = 0000 )............................................... ............................. 841

25-3XOR Chain 2 (REQ[4:1]# = 0001 )............................................... ............................. 842

25-4XOR Chain 3 (REQ[4:1]# = 0010 )............................................... ............................. 843

25-5XOR Chain 4-1 (REQ[4:1]# = 0011)......................................................................... 844

25-6XOR Chain 4-2 (REQ[4:1]# = 0011)......................................................................... 845

25-7XOR Chain 5 (REQ[4:1]# = 0100 ).......................... .................................................. 846

34 Intel ® ICH7 Family Datasheet

Revision History

Revision Description Date

-001 • Initial release April 2005

-002 • Added specificaitons for ICH7DH, ICH7-M, and ICH7-M DH January 2006

-003 • Added specifications for the ICH7-U

• Added Documentation Changes/Specification Changes from Spec Update Revision -020. April 2007

Intel ® ICH7 Family Datasheet 35

Intel® ICH7 Family Features

Direct Media Interface

— 10 Gb/s each direction, full duplex

— Transp arent to software

PCI Express* (Desktop and Mobile Only)

— 4 PCI Ex pr es s ro ot po rts

— NEW: 2 Additional PCI Express root ports (ICH7 R/

Digital Home only) configurable as x1 only

— Supports PCI Express 1.0a

— Ports 1-4 can be statically configured as 4x1, or 1x4.

— Support for full 2.5 Gb/s bandwidth in each direction

per x1 lane

— Module based Hot-Plug supported

(e.g., ExpressCard*) (Desktop and Mobile Only)

PCI Bus Interface

— Supp or ts PCI Rev 2.3 Specification at 33 MHz

— New: Six available PCI REQ/GNT pairs (3 pairs on

Ultra Mobile)

— Support for 64-bit addressing on PCI using DAC

protocol

Integrated Serial AT A Host Controller (Desktop and Mobile

Only)

— Four ports (desktop only) or two ports (Mobile only)

— NEW: Data transfer rates up to 3.0 Gb/s

(300 MB/s) (Desktop Only)

— Integrated AHCI controller

(RAID, Digital Home and Mobile only)

Intel® Matrix Storage Technology

(RAID and Digital Home only)

— Configures the ICH7 SATA controller as a RAID

controller supporting RAID 0/1/10 (RAID and ICH7

DH only)

— Configures the ICH7 SATA controller as a RAID

controller supporting RAID 0/1 (ICH7-M DH)

— NEW: Support for RAID 5 (RAID and ICH7 DH only)

Integrated IDE Controller

— Independent timing of up to two drives (one drive on

Ultra Mobile)

— Ultra ATA/100/66/33, BMIDE and PIO modes

— Tri-state modes to enable swap bay

— Supports ATA/ATAPI-7

Intel® High Definition Audio Interface

— PC I Ex pr es s en dp oint

— Independent Bus Master logic for eigh t general purpose

streams: four input and four output

— Support three external Codecs

— Supports variable length stream slots

— Supports multichannel, 32-bit sample depth and 192

kHz sample rate output

— Provides mic array support

— Allows for non-48 kHz sampling output

— Support for ACPI Device States

— NEW: Docking Suppor t (Mobile Only)

— NEW: Low Voltage Mode (Mobile/Ultra Mobile Only)

AC-Link for Audio an d Telephony CODECs (Desktop and

Mobile Only)

— Support for three AC ‘97 2.3 codecs.

— Independent bus master logic for 8 channels (PCM In/

Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/

Out, S/PDIF Out)

— Support for up to six channels of PCM audio output

(full AC3 decode)

— Supports wake-up events

USB 2.0

— Includes four UHCI Host Con trollers, s uppor ting eight

external ports

— Includes one EHCI Host Controller that supports all

eight ports

— Includes one USB 2.0 High-speed Debug Port

— Supports wake-up from sleeping states S1–S5

— Supports legacy Keyboard/Mouse software

Integrated LAN Controller (Desktop and Mobile Only)

— Integrated ASF Management Controller

— Supports IEEE 802.3

— LAN Connect Interf ace (LCI)

— 10/100 Mb/s Ethernet Support

NEW : Intel Active Managemen t Technology (Desktop and

Mobile Only)

NEW: Intel® Quick Resume Technology Support (Digital

Home Only)

Power Management Logic

— Supports ACPI 3.0

— ACPI-defined power states (C1, S1, S3–S5 for Desktop

and C1–C4, S1, S3–S5 for Mobile/Ultra Mobile)

— ACPI Power Management Timer

— (Mobile/Ultra Mobile Only) Support for “Intel

SpeedStep® Technology” processor power control and

“Deeper Sleep” power state

— PCI CLKRUN# and PME# support

— SMI # gen eration

— All registers readable/restorable for proper resume

from 0 V suspend states

— Support for APM-based legacy power management for

non-ACPI Desktop and Mobile implementations

External Glue Integration

— Integrated Pull-up, Pull-down and Series Termination

resistors on IDE, processor interface

— Integrated Pull-down and Series resistors on USB

Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— Supports LPC DMA (Desktop and Mob ile Only)

36 Intel ® ICH7 Family Datasheet

SMBus

—Flexible SMBus/SMLink architecture to optimize

for ASF

—Provides independent manageability bus through

SMLink interface

—Supports SMBus 2.0 Specification

—Host interface allows processor to com municate

via SMBus

—Slave interface allows an internal or external

Microcontrolle r to access system resources

—Compatible with most two-wire components that

are also I2C compatible

High Precision Event Timers

—Advanced operating system interrupt scheduling

Timers Based on 82C54

—System timer, Refresh request, Spea ker tone

output

Real-Time Clock

—256-byte battery-backed CMOS RAM

—Integrated oscillator components

—Lower Power DC/DC Converter implementation

System TCO Reduction Circuits

—Timers to generate SMI# and Reset upon

detection of system hang

—Timers to detect improper processor reset

—Integrated processor frequency strap logic

—Supports ability to disable external devices

Interrupt Controller

—Supports up to eight PCI interrupt pins

—Supports PCI 2.3 Message Signaled Interrupts

—Two cascaded 82C59 with 15 interrupts

—Integrated I/O APIC capability with 24 interrupts

—Supports Processor System Bus interrupt

delivery

1.05 V operation with 1.5 V and 3.3 V I/O

—5 V tolerant buffers on IDE, PCI, USB and

Legacy signals

NEW: 1.05 V Core Voltage

Integrated 1.05 V Voltage Regulator (INTVR) for

the Suspend and LAN wells (Desktop an d Mobile

Only)

Firmware Hub I/F supports BIOS Memory size up

to 8 MBytes (Desktop and Mobile Only)

NEW: Serial Peripheral Interface (SPI) for Serial

and Shared Flash (Desktop and Mobile Only)

Low Pin Count (LPC) I/F

—Supports two Master/DMA devices.

—Support for Security Device (Trusted Platform

Module) connected to LPC.

GPIO

—TTL, Open-Drain, Inversion

NEW: Package 31 mm x 31 mm 652 mBGA

(Desktop and Mobile Only)

New: Package 15 mm x 15 mm, 452 balls (Ultra

Mobile only)

Desktop Configuration

Intel® PCI Exp r ess

Gigabit Ethernet

Intel®

ICH7

USB 2.0

(Supports 8 USB ports)

System Management

(TCO)

IDE

GPIO

SMBus 2.0/I2C

Power Management

PCI Bus

...

Clock Generators

LAN Connect

AC ’97/Intel® High

Definition Audio

Codec(s)

Firmware Hub

Other ASICs

(Optional)

LPC I/F

Super I/O

SATA (4 ports)

PCI Express* x1

DMI

(To (G)MCH)

TPM

(Optional)

SPI BIOS

Intel ® ICH7 Family Datasheet 37

Mobile Configuration

Ultra Mobile Configuration

Intel®

ICH7-M

USB 2.0

(Supports 8 USB ports)

System Manage ment

(TCO)

IDE

GPIO

SMBus 2.0/I2C

Power Management

PCI Bus

Clock Generators

Cardbus

Controller (&

attached sl ots)

DMI

(To (G)MCH)

LAN Connect

AC’97/Intel® High

Definition Audio

Codec(s)

Flash BIOS

Other ASICs

(Optional)

LPC I/F

Super I/O

SATA (2 ports)

Docking

Bridge

PCI Express x1

TPM

(Optional)

SPI BIOS

Intel®

ICH7-U

USB 2.0

(Supports 8 USB ports)

System Management

(TCO)

IDE

GPIO

SMBus 2.0/I2C

Power Management

PCI Bus

Clock Generators

3 PCI

DMI

(To GMCH)

Flash BIOS

Other ASICs

(Optional)

LPC I/F

Super I/O

Intel® High Definition

Audio Codec(s)

TPM

(Optional)

38 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 39

Introduction

1 Introduction

This document is intended for Original Equipment Manufacturers and BIOS vendors

creating Intel® I/O Controller Hub 7 (ICH7) Family based products. This document is

the datasheet for the following:

•Intel

® 82801GB ICH7 (ICH7)

•Intel

® 82801GR ICH7 RAID (ICH7R)

•Intel

® 82801GDH ICH7 Digital Home (ICH7DH)

•Intel

® 82801GBM ICH7 Mobile (ICH7-M)

•Intel

® 82801GHM ICH7 Mobile Digital Home (ICH7-M DH)

•Intel

® 82801GU ICH7-U Ultra Mobile (ICH7-U)

Section 1.2 provides high-level feature differ ences for the ICH7 Family components.

Note: Throughout this datasheet, I CH7 is used as a general ICH7 term and refers to the

82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH, 8280 1GBM ICH7-M, 82801GHM

ICH7-M DH, and 82801GU ICH7-U components, unless specifically noted otherwise.

Note: Throughout this datasheet, the term “Desktop” refers to an y implementation, be it in a

desktop, server, workstation, etc., unless specifically noted otherwise.

Note: Throughout this datasheet, the terms “Desktop”, “Digital Home” “Mobile”, and “Ultra

Mobile” refer to the following components, unless specifically noted otherwise:

•Desktop refers to the 82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH.

•Digital Home refers to the 82801GDH ICH7DH and 82801GHM ICH7-M DH.

•Mobile refers to the 82801GBM ICH7-M, and 82801GHM ICH7-M DH.

•Ultra Mobile refers to the 82801GU ICH7-U.

Note: “Desktop and Mobile Only” refers to all components in this document except the

82801GU ICH7-U Ultra Mobile component.

This datasheet assumes a working knowledge of the vocabulary and principles of PCI

Express*, USB, IDE, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio),

AC ’97, SMBus, PCI, ACPI and L PC. Although some details of these features are

described within this manual, refer to the individual industry specifications listed in

Table 1-1 for the complete details.

Table 1-1. Industry Specifications

Specification Location

Intel® I/O Controller Hub ICH7 Family Specification

Update http://developer.intel.com//design/

chipsets/specupdt/307014.htm

Intel® I/O Controller Hub ICH7 Family Thermal

Mechanical Guidelines http://developer.intel.com//design/

chipsets/designex/307015.htm

PCI Express* Base Specification, Revision 1.0a http://www.pcisig.com/specifications

Low Pin Count Inte rface Specificati on, Revisio n 1.1

(LPC) http://developer.intel.com/design/

chipsets/industry/lpc.htm

Audio Codec ‘97 Component Specification, Version 2.3

(AC ’97) http://www.intel.com/design/

chipsets/audio/

Introduction

40 Intel ® ICH7 Family Datasheet

Chapter 1. Introduction

Chapter 1 introduces the ICH7 and provides information on manual organization and

gives a general overview of the ICH7.

Chapter 2. Signal Description

Chapter 2 provides a block diagram of the ICH7 interface signals and a detailed

description of each signal. Signals are arranged according to interface and details are

provided as to the drive characteristics (Input/Output, Open Dr ain, etc.) of all signals.

Chapter 3. Intel® ICH7 Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4. Intel® ICH7 and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the ICH7 in an ICH7

based system.

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the ICH7. All PCI buses,

devices and functions in this manual are abbreviated using the following nomenclature;

Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8,

D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For

example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is

abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be

considered to be Bus 0. Note that the ICH7’s external PCI bus is typically Bus 1, but

may be assigned a different number depending upon system configuration.

System Management Bus Specif ication, Version 2.0

(SMBus) http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications

PCI Mobile Design Guide, Revision 1.1 http://www.pcisig.com/specifications

PCI Power Management Specification , Revision 1.1 http://www.pcisig.com/specifications

Universal Serial Bus Specification (USB), Rev ision 2.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version

2.0 (ACPI) http://www.acpi.info/spec.htm

Universal Host Controller Interface, Revision 1.1 (UHCI) http://developer.intel.com/design/

USB/UHCI11D.htm

Enhanced Host Controller Interface Specification for

Universal Serial Bus, Revisi on 1.0 (EHCI) http://developer.intel.com/

technology/usb/ehcispec.htm

Serial ATA Specification, Revision 1.0a http://www.serialata.org/

specifications.asp

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org/

specifications.asp

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet http://standards.ieee.org/

getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI -

6) http://T13.org (T13 1410 D)

IA-PC HPET (High Precis ion Event Timers) Spec ificatio n,

Revision 1.0 http://www.intel.com/

hardwaredesign/hpetspec.htm

Table 1-1. Industry Specifications

Specification Location

Intel ® ICH7 Family Datasheet 41

Introduction

Chapter 6. Register and Memory Mappings

Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the ICH7.

Chapter 7. Chipset Configuration Registers

Chapter 7 provides a detailed description of all registers and base functionality that is

related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI

Express). It contains the root complex register block, which describes the behavior of

the upstream internal link.

Chapter 8. LAN Controller Registers

Chapter 8 provides a detailed description of all registers that reside in the ICH7’s

integrated LAN controller. The integrated LAN controller resides on the ICH7’s external

PCI bus (typically Bus 1) at Device 8, Function 0 (B1:D8:F0).

Chapter 9. PCI-to-PCI Bridge Registers

Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 10. LPC Bridge Registers

Chapter 10 provides a detailed description of all registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers

for many different units within the ICH7 including DMA, Timers, Interrupts, Processor

Interface, GPIO, Power Management, System Management and RTC.

Chapter 11. SATA Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the SATA

controller. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 12. UHCI Controller Registers

Chapter 11 provides a detailed description of all registers that reside in the four UHCI

host controllers. These controllers reside at Device 29, Functions 0, 1, 2, and 3

(D29:F0/F1/F2/F3).

Chapter 13. EHCI Controller Registers

Chapter 13 provides a detailed description of all registers that reside in the EHCI host

controller. This controller resides at Device 29, Function 7 (D29:F7).

Chapter 14. SMBus Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 15. IDE Controller Registers

Chapter 15 provides a detailed description of all registers that reside in the IDE

controller. This controller resides at Device 31, Function 1 (D31:F1).

Chapter 16. AC ’97 Audio Controller Registers

Chapter 16 provides a detailed description of all registers that reside in the audio

controller. This controller resides at Device 30, Function 2 (D30:F2). Note that this

section of the datasheet does not include the native audio mixer registers. Accesses to

the mixer registers are forwarded over the AC-link to the codec where the registers

reside.

Chapter 17. AC ’97 Modem Controller Registers

Chapter 17 provides a detailed description of all registers that reside in the modem

controller. This controller resides at Device 30, Function 3 (D30:F3). Note that this

section of the datasheet does not include the modem mixer registers. Accesses to the

mixer registers are forwarded over the AC -link to the codec where the registers reside.

Chapter 18. Intel® High Definition Audio Controller Registers

Chapter 18 provides a detailed description of all registers that reside in the Intel® High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 19. PCI Express* Port Controller Registers

Chapter 19 provides a detailed description of all registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 5 (D30:F0-F5).

Introduction

42 Intel ® ICH7 Family Datasheet

Chapter 20. High Precision Event Timers Registers

Chapter 20 provides a detailed description of all registers that reside in the multimedia

timer memory mapped register space.

Chapter 21. Serial Peripheral Interface Registers

Chapter 21 provides a detailed description of all registers that reside in the SPI

memory mapped register space.

Chapter 22. Ballout Definition

Chapter 22 provides a table of each signal and its ball assignment in the 652-mBGA

package.

Chapter 23. Electrical Characteristics

Chapter 23 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 24. Package Information

Chapter 24 provides drawings of the physical dimensions and characteristics of the

652-mBGA package.

Chapter 25. Testability

Chapter 25 provides detail about the implementation of test modes provided in the

ICH7.

1.1 Overview

The ICH7 provides extensive I/O support. Functions and capabilities include:

•PCI Express* Base Specification, Revision 1.0a support (Desktop and Mobile Only)

•PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations

(supports up to six Req/Gnt pairs; three pairs on Ultra Mobile).

• ACPI Power Management Logic Support

• Enhanced DMA controller, interrupt controller, and timer functions (Desktop and

Mobile Only)

• Integrated Serial A TA host controller with independent DMA operation on four ports

(Desktop only) or two ports (Mobile Only) and AHCI (ICH7R, ICH7DH, ICH7-M, and

ICH7-M DH Only) support. (SATA not supported on Ultra Mobile)

• Integrated IDE controller supports Ultra ATA100/66/33

• USB host interface with support for eight USB ports; four UHCI host controllers;

one EHCI high-speed USB 2.0 Host controller

• Integrated LAN controller (Desktop and Mobile Only)

•System Management Bus (SMBus) Specification, Version 2.0 with additional

support for I2C devices (Desktop and Mobile Only)

•Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a., AC ’97 Component

Specification, Revision 2.3) which provides a link for Audio and Telephony codecs

(up to 7 channels) (Desktop and Mobile Only)

•Supports Intel High Definition Audio

•Supports Intel

® Matrix Storage Technology (ICH7R, ICH7DH, and Mobile Only)

•Supports Intel

® Active Management Technology (Desktop and Mobile Only)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support (Desktop and Mobile Only)

Intel ® ICH7 Family Datasheet 43

Introduction

The ICH7 incorporates a variety of PCI functions that are divided into six logical devices

(B0:D27, B0:D28, B0:D29, B0:D30, B0:D31 and B1:D8) as listed in Table 1-2. D30 is

the DMI-to-PCI bridge and the AC ’97 Audio and Modem controller functions, D31

contains the PCI-to-LPC bridge, IDE controller, SATA controller, and SMBus controller,

D29 contains the four USB UHCI controllers and one USB EHCI controller, and D27

contains the PCI Express root ports. B1:D8 is the integrated LAN controller.

NOTES:

1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System

Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.

The following sub-sections provide an overview of the ICH7 capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory

Controller Hub / Graphics Memory Controller Hub ((G)MCH) and I/O Controller Hub 7

(ICH7). This high-speed interface integrates advanced priority-based servicing allowing

for concurrent traffic and true isochronous transfer capabilities. Base functionality is

completely software-transparent, permitting current and legacy software to operate

normally.

Table 1-2. PCI Devices and Functions

Bus:Device:Function Function Description

Bus 0:Device 30:Function 0 PCI-to-PCI Bridge

Bus 0:Device 30:Function 2 AC ’97 Audio Controller (Desktop and Mobile Only)

Bus 0:Device 30:Function 3 AC ’97 Modem Controller (Desktop and Mobile Only)

Bus 0:Device 31:Function 0 LPC Controller1

Bus 0:Device 31:Function 1 IDE Controller

Bus 0:Device 31:Function 2 SATA Controller (Desktop and Mobile Only)

Bus 0:Device 31:Function 3 SMBus Controller

Bus 0:Device 29:Function 0 US B UHCI Controller #1

Bus 0:Device 29:Function 1 US B UHCI Controller #2

Bus 0:Device 29:Function 2 US B UHCI Controller #3

Bus 0:Device 29:Function 3 US B UHCI Controller #4

Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller

Bus 0:Device 28:Function 0 PCI Express* Port 1 (Desktop and Mobile Only)

Bus 0:Device 28:Function 1 PCI Express Port 2 (Desktop and Mobile Only)

Bus 0:Device 28:Function 2 PCI Express Port 3 (Desktop and Mobile Only)

Bus 0:Device 28:Function 3 PCI Express Port 4 (Desktop and Mobile Only)

Bus 0:Device 28:Function 4 PCI Express Port 5 (Intel® ICH7R, ICH7DH, and ICH7-M DH

Only)

Bus 0:Device 28:Function 5 PCI Express Port 6 (Intel ICH7R, ICH7DH, and ICH7-M DH Only)

Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller

Bus n:Device 8:Function 0 LAN Controller (Desktop and Mobile Only)

Introduction

44 Intel ® ICH7 Family Datasheet

PCI Express* Interface (Desktop and Mobile Only)

The ICH7R, ICH7DH, ICH7-M DH have six PCI Express root ports and the ICH7 and

ICH7-M have four PCI Express root ports (ports 1-4), supporting the PCI Express Base

Specification, R evision 1 .0a. PC I Express root ports 1–4 can be statically configured as

four x1 ports or ganged together to form one x4 port. Ports 5 and 6 on the ICH7R,

ICH7DH, and ICH7-M DH can only be used as two x1 ports. Each Root Port supports

2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent).

Serial ATA (SATA) Controller (Desktop and Mobile Only)

The ICH7 has an integrated SATA host controller that supports independent DMA

operation on four ports (desktop only) or two ports (mobile only) and supports data

transfer r ates of up to 3.0 Gb/s (300 MB/s). The SAT A controller contains two modes of

operation – a legacy mode using I/O space, and an AHCI mode using memory space.

SATA and PATA can also be used in a combined function mode (where the SATA function

is used with PATA). In this combined function mode, AHCI mode is not used. Software

that uses legacy mode will not have AHCI capabilities.

The ICH7 supports the Serial ATA Specification, Revision 1.0a. The ICH7 also supports

several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0

Specification, Revision 1.0 (AHCI support is required for some elements).

AHCI (Intel® ICH7R, ICH7DH, and Mobile Only)

The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a

new programming interface for SATA host controllers. Platforms supporting AHCI may

take advantage of performance features such as no master/slave designation for S ATA

devices—each device is treated as a master—and hardware-assisted native command

queuing. AHCI also provides usability enhancements such as Hot-Plug (Desktop and

Mobile Only). AHCI requires appropriate software support (e.g., an AHCI driver) and for

some features, hardware support in the SATA device or additional platform hardware.

Intel® Matrix Storage Technology (Intel® ICH7R, ICH7DH, and ICH7-M

DH Only)

The ICH7 provides support for Intel Matrix Storage Technology, providing both AHCI

(see above for details on AHCI) and integr ated RAID functionality. The industry-leading

RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality

(RAID 0/1 functionality for ICH7-M DH) on up to 4 SATA ports of ICH7. Matrix RAID

support is provided to allow multiple RAID levels to be combined on a single set of hard

drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare

support, SMART alerting, and RAID 0 auto replace. Software components include an

Option ROM for pre-boot configuration and boot functionality, a Microsoft* Windows*

compatible driver, and a user interface for configuration and management of the RAID

capability of ICH7.

PCI Interface

The ICH7 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH7

integrates a PCI arbiter that supports up to six external PCI bus masters (three on Ultra

Mobile) in addition to the internal ICH7 requests. This allows for combinations of up to

six PCI down devices (three on Ultra Mobile) and PCI slots.

Intel ® ICH7 Family Datasheet 45

Introduction

IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile)

providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have

independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and

Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources.

The IDE interface integrates 16x32-bit buffers for optimal transfers.

The ICH7’s IDE system contains a single, independent IDE signal channel that can be

electrically isolated. There are integrated series resistors on the data and control lines

(see Section 5.16 for details).

Low Pin Count (LPC) Interface

The ICH7 implements an LPC Interface as described in the LPC 1.1 Specification. The

Low Pin Count (LPC) bridge function of the ICH7 resides in PCI Device 31:Function 0. In

addition to the LPC bridge interface function, D31:F0 contains other functional units

including DMA, interrupt controllers, timers, power management, system management,

GPIO, and RTC.

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

The ICH7 implements an SPI Interface as an alternative interface for the BIOS flash

device. An SPI flash device can be used as a replacement for the FWH.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by -

byte transfers, and channels 5–7 are hardwired to 16-bit, count-by -word transfers. Any

two of the seven DMA channels can be programmed to support fast Type-F transfers.

The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA,

through the ICH7’s DMA controller. LPC DMA is handled through the use of the LDRQ#

lines from peripherals and special encoding on LAD[3:0] from the host. Single,

Demand, V erify, and Increment modes are supported on the LPC interface. Channels 0–

3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a

generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those

found in one 82C54 programmable interval timer. These three counters are combined

to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator

input provides the clock source for these three counters.

The ICH7 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that

incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt

controllers are cascaded so that 14 external and two internal interrupts are possible. In

addition, the ICH7 supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save

and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)

described in the previous section, the ICH7 incorporates the Advanced Programmable

Interrupt Controller (APIC).

Introduction

46 Intel ® ICH7 Family Datasheet

Universal Serial Bus (USB) Controller

The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller that

supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to

480 Mb/s which is 40 times faster than full-speed USB. The ICH7 also contains four

Universal Host Controller Interface (UHCI) controllers that support USB full-speed and

low-speed signaling.

The ICH7 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and

low-speed capable. ICH7’s port-routing logic determines whether a USB port is

controlled by one of the UHCI controllers or by the EHCI controller. See Section 5.19

and Section 5.20 for details.

LAN Controller (Desktop and Mobile Only)

The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides

enhanced scatter-gather bus mastering capabilities and enables the LAN controller to

perform high speed data transfers over the PCI bus. Its bus master capabilities enable

the component to process high-level commands and perform multiple operations; this

lowers processor utilization by off-loading communication tasks from the processor.

Two large transmit and receive FIFOs of 3 KB each help prevent data underruns and

overruns while waiting for bus accesses. This enables the integrated LAN controller to

transmit data with minimum interframe spacing (IFS).

The LAN controller can operate in either full duplex or half duplex mode. In full duplex

mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half

duplex performance is enhanced by a proprietary collision reduction mechanism. See

Section 5.3 for details.

Alert Standard Format (ASF) Management Controller (Desktop and

Mobile Only)

ICH7 integrates an Alert Standard Format controller in addition to the integrated LAN

controller, allowing interface system-monitoring devices to communicate through the

integrated LAN controller to th e network. This makes remote manageability and system

hardware monitoring possible using ASF.

The ASF controller can collect and send various information from system components

such as the processor, chipset, BIOS and sensors on the motherboard to a remote

server running a managem e nt consol e. The controller can also be programmed to

accept commands back from the management console and execute those commands

on the local system.

Intel ® ICH7 Family Datasheet 47

Introduction

RTC

The ICH7 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes

of battery-backed RAM. The real-time clock performs two key functions: keeping track

of the time of day and storing system data, even when the system is powered down.

The RTC operates on a 32.768 KHz crystal and a 3 V battery.

The R TC also supports two lockable memory r anges. By setting bits in the configuration

space, two 8-byte ranges can be locked to read and write accesses. This prevents

unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to

30 days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.

The number of inputs and outputs varies depending on ICH7 configuration.

Enhanced Power Management

The ICH7’s power management functions include enhanced clock control and various

low-power (suspend) states (e.g. , Suspend-to-RAM and Suspend-to-Disk). A hardware-

based thermal management circuit permits software-independent entrance to low-

power states. The IC H7 contains full support for the Advanced Configuration and Power

Interface (ACPI) Specification, Revision 3.0.

Intel® Quick Resume Technology (Digital Home Only)

ICH7 implements Intel Quick Resume Technology that provides the capability to design

a PC with a single power button that reliably and instantly (user's perception) turns the

PC On and Off. When the system is On and the user presses the power button, the

display instantly goes dark, sound is muted, and there is no response to keyboard/

mouse commands (except for keyboard power button). When the system is Off and the

user presses the power button, picture and sound quickly return, and the keyboard/

mouse return to normal functionality, allowing user input.

Intel® Active Management Technology (Intel® AMT) (Desktop and

Mobile Only)

Intel Active Management Technology is the next generation of client manageability via

the wired network. Intel AMT is a set of adv anced manageability features dev eloped as

a direct result of IT customer feedback gained through Intel market research.

Introduction

48 Intel ® ICH7 Family Datasheet

Manageability

In addition to Intel AMT the ICH7 integrates several functions designed to manage the

system and lower the total cost of ownership (TCO) of the system. These system

management functions are designed to report errors, diagnose the system, and recover

from system lockups without the aid of an external microcontroller.

•TCO Timer. The ICH7’s integrated programmable TCO timer is used to detect

system locks. The first expiration of the timer generates an SMI# that the system

can use to recover fro m a software lock. Th e second expir ation of the timer causes

a system reset to recover from a hardware lock.

•Processor Present Indicator. The ICH7 looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the ICH7

will reboot the system.

•ECC Error Reporting. When detecting an ECC error, the host controller has the

ability to send one of several messages to the ICH7. The host controller can

instruct the ICH7 to generate either an SMI#, NMI, SERR#, or TCO interrupt.

•Function Disable. The ICH7 provides the ability to disable the following integr ated

functions: AC ’97 Modem, AC ’97 Audio, IDE, LAN, USB, LPC, Intel HD Audio, SAT A,

or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI

configuration space. Also, no interrupts or power management events are

generated from the disable functions.

•Intruder Detect. The ICH7 provides an input signal (INTRUDER#) that can be

attached to a switch that is activated by the system case being opened. The ICH7

can be programmed to generate an SMI# or TCO interrupt due to an active

INTRUDER# signal.

System Management Bus (SMBus 2.0) (Desktop and Mobile Only)

The ICH7 contains an SMBus Host interface that allows the processor to communicate

with SMBus slaves. This interface is compatible with most I2C devices. Special I2C

commands are implemented.

The ICH7’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). Also, the ICH7 supports slave

functionality, including the Host Notify protocol. Hence, the host con troller s upports

eight command protocols of the SMBus interface (see System Management Bus

(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

ICH7’s SMBus also implements hardware-based Packet Error Checking for data

robustness and the Address Resolution Protocol (ARP) to dynamically provide address

to all SMBus devices.

Intel ® ICH7 Family Datasheet 49

Introduction

Intel® High Definition Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be

used to attach different types of codecs, such as audio and modem codecs. The ICH7

Intel HD Audio digital link shares pins with the AC-link. Concurrent operation of Intel

HD Audio and AC ’97 functionality is not supported. The ICH7 Intel HD Audio controller

supports up to 3 codecs.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate

up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE

levels of audio experience. On the input side, the ICH7 adds support for an arrays of

microphones.

The Intel HD Audio controller uses multi-purpose DMA engines, as opposed to

dedicated DMA engines in AC ’97 (Desktop and Mobile Only), to effectively manage the

link bandwidth and support simultaneous independent s treams on the link. The

capability enables new exciting usage models with Intel HD Audio (e.g., listening to

music while playing multi-player game on the internet.) The Intel HD Audio controller

also supports isochronous data transfers allowing glitch-free audio to the system.

Note: Users interested in providing feedback on the Intel High Definition Audio Specification

or planning to implement the Intel High Definition Audio Specification into a future

product will need to execute the Intel High Definition Audio Specification Developer’s

Agreement. For more information, contact nextgenaudio@intel.com.

AC ’97 2.3 Controller (Desktop and Mobile Only)

The ICH7 integrates an Audio Codec '97 Component Specification, Version 2.3

controller that can be used to attach an audio codec (AC), a modem codec (MC), an

audio/modem codec (AMC) or a combination of ACs and a single MC. The ICH7

supports up to six channels of PCM audio output (full AC3 decode). For a complete

surround-sound experience, six-channel audio consists of: front left, front right, back

left, back right, center, and subwoofer. ICH7 has expanded support for up to three

audio codecs on the AC-link.

In addition, an AC '97 soft modem can be implemented with the use of a modem codec.

Several system opti ons ex i s t when im p lementing AC '97. Th e IC H7 - i ntegrated AC '97

controller allows up to three external codecs to be connected to the ICH7. The system

designer can provide AC '97 modem with a modem codec, or both audio and modem

with up to two audio codecs with a modem codec.

Introduction

50 Intel ® ICH7 Family Datasheet

1.2 Intel® ICH7 Family High-Level Component

Differences

NOTES:

1. Feature capability can be read in D31:F0:Offset E4h.

2. The ICH7 Base (ICH7) supports Ports 1:4; ICH7 RAID (ICH7R) and ICH7 Digital Home

(ICH7DH) supports Ports 1:6.

NOTES:

1. Feature capability can be read in D31:F0:Offset E4h.

Table 1-3. Intel® ICH7 Desktop/Server Family1

Product Name Base

Features

Intel® Matrix

Storage

Technology RAID

0/1/5/10 /

AHCI

6 PCI

Express

Ports

Intel®

AMT

Support

Intel®

Quick

Resume

Technology

Intel® ICH7 Base

(ICH7) Yes No/No No2Yes No

ICH7 Digital

Home (ICH7DH) Yes Yes / Yes Yes2Yes Yes

ICH7 RAID

(ICH7R) Yes Yes / Yes Yes2Yes No

Table 1-4. Intel® ICH7-M Mobile and ICH7-U Ultra Mobile Components1

Product Name Short

Name Base

Features AHCI

Intel® Matrix

Storage

Technology

RAID 0/1

6 PCI

Express*

Ports

Intel®

AMT

Ready

ICH7 Mobile ICH7-M Yes Yes No No Yes

ICH7 Mobile

Digital Home ICH7-M DH Yes Yes Yes Yes Yes

ICH7 Ultra

Mobile ICH7-U Not all

features No No No No

Intel ® ICH7 Family Datasheet 51

Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in

functional groups according to their associated interface. Figure 2-1 shows the

interface signals for the Intel® 82801GB ICH7, 82801GR ICH7R, and 82801GDH

ICH7DH. Figure 2-2 shows the interface signals for the 82801GBM ICH7-M and

82801GHM ICH7-M DH. Figure 2-3 shows the interface signals for the 82801GU ICH7-

The “#” symbol at the end of the signal name indicates that the active, or asserted

state occurs when the signal is at a low voltage level. When “#” is not present, the

signal is asserted when at the high voltage level.

The “Type” for each signal is indicative of the functional operating mode of the signal.

Unless otherwise noted in Section 3.3 or Section 3.4, a signal is considered to be in the

functional operating mode after RTCRST# for signals in the RTC well, RSMRST# for

signals in the suspend well, after PWROK for signals in the core well, and after

LAN_RST# for signals in the LAN well.

The following notations are used to describe the signal type:

IInput Pin

O Output Pin

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input / Output Pin.

OC Open Collector Output Pin.

Signal Description

52 Intel ® ICH7 Family Datasheet

Figure 2-1. Interface Signals Block Diagram (Desktop Only)

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

SLP_S3#

SLP_S4#

SLP_S5#

PWROK

PWRBTN#

RI#

WAKE#

SUS_STAT# / LPCPD#

SUSCLK

LAN_RST#

VRMPWRGD

PLTRST#

AD[31

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ[3:0]#

REQ[4]# / GPIO[22]

REQ[5]# / GPIO[1]

GNT[3:0]#

GNT[4]# / GPIO[48]

GNT[5]# / GPIO[17]

PCICLK

PCIRST#

PLOCK#

SERR#

PME#

PCI

Interface

DCS1#

DCS3#

DA[2:0]

DD[15:0]

DDREQ

DDACK#

DIOR# (DWSTB / RDMARDY#)

DIOW# (DSTOP)

IORDY (DRSTB / WDMARDY#)

IDE

Interface

Power

Mgnt.

RTCX1

RTCX2

CLK14

CLK48

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

RTC

Clocks

Misc.

Signals

INTVRMEN

SPKR

RTCRST#

TP0

TP[2:1]

TP3

General

Purpose

I/O

GPIO[39:38, 34:32, 28:26,

25:24, 20, 18, 16:12, 10:6]

EEPROM

Interface

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

INTRUDER#

SMLINK[1:0]

LINKALERT#

DMI[3:0]TXP, DMI[3:0]TXN

DMI[3:0]RXP, DMI[3:0]RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

ACZ_RST#

ACZ_SYNC

ACZ_BIT_CLK

ACZ_SDOUT

ACZ_SDIN[2:0]

AC '97/

Intel®

High

Definition

Audio

Firmware

Hub

System

Mgnt.

FWH[3:0] / LAD[ 3:0]

FWH[4] / LFRAME#

LAD[3:0] / FWH[3:0]

LFRAME# / FWH[4]

LDRQ[0]#

LDRQ[1]# / GPIO[23]

SMBDATA

SMBCLK

SMBALERT# / GPIO[11]

LAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

Platform

LAN

Connect

SATA[3:0]TXP, SATA[3:0]TXN

SATA[3:0]RXP, SATA[3:0]RXN

SATARBIAS

SATARBIAS#

SATA[3:0]GP/GPIO[37,36,21,19]

SATALED#

SATACLKREQ#/GPIO[35]

Serial ATA

Interface

PCI

Express*

Interface

PETp[6:1], PETn[6:1]

PERp[6:1], PERn[6:1]

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

INIT3_3V#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD / GPIO[49]

Processor

Interface

Interrupt

Interface

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]# / GPIO[5:2]

IDEIRQ

USB

USBP[7:0]P

USBP[7:0]N

OC[4:0]#

OC[5]# / GPIO[29]

OC[6]# / GPIO[30]

OC[7]# / GPIO[31]

USBRBIAS#

USBRBIAS

SPI

SPI_CS#

SPI_MISO

SPI_MOSI

SPI_ARB

SPI_CLK

EL_RSVD / GPIO26

EL_STATE[1:0] /

GPIO[28:27]

Intel® Quick

Resume

Technology

Digital

Home

Only

Intel ® ICH7 Family Datasheet 53

Signal Description

Figure 2-2. Interface Signals Block D iagram (Mobile Only)

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

DPRSTP#

SLP_S3#

SLP_S4#

SLP_S5#

PWROK

PWRBTN#

RI#

WAKE#

SUS_STAT# / LPCPD#

SUSCLK

LAN_RST#

VRMPWRGD

BMBUSY# / GPIO[0]

STP_PCI#

STP_CPU#

BATLOW#

DPRSLPVR

PLTRST#

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ[3:0]#

REQ[4]# / GPIO[22]

REQ[5]# / GPIO[1]

GNT[3:0]#

GNT[4]# / GPIO[48]

GNT[5]# / GPIO[17]

PME#

CLKRUN#

PCICLK

PCIRST#

PLOCK#

SERR#

ICH7_Signals_Mobile

PCI

Interface

DCS1#

DCS3#

DA[2:0]

DD[15:0]

DDREQ

DDACK#

DIOR# (DWSTB / RDMARDY#)

DIOW# (DSTOP)

IORDY (DRSTB / WDMARDY#)

IDE

Interface

Power

Mgnt.

Interrupt

Interface

A20M#

FERR#

IGNNE#

INIT#

INIT3_3#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRG D / GPIO [4 9]

DPSLP#

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]# / GPIO[5:2]

IDEIRQ

USBP[7:0]P

USBP[7:0]N

OC[4:0]#

OC[5]# / GPIO[29]

OC[6]# / GPIO[30]

OC[7]# / GPIO[31]

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLK14

CLK48

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

RTC

Clocks

Misc.

Signals

INTVRMEN

SPKR

RTCRST#

TP[3]

General

Purpose

I/O

GPIO[39:37,25:24,19,1

5:12,10:6]

EEPROM

Interface

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

INTRUDER#

SMLINK[1:0]

LINKALERT#

DMI[3:0]TXP, DMI[3:0]TXN

DMI[3:0]RXP, DMI[3:0]RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

ACZ_RST#, ACZ_SYNC, ACZ_SDOUT

ACZ_SDIN[2:0]

ACZ_BIT_CLK

AZ_DOCK_EN# / GPIO[33]

AZ_DOCK_RST# / GPIO[34]

AC '97/

Intel® High

Definition

Audio

Firmware

Hub

System

Mgnt.

FWH[3:0] / LAD[3:0]

FWH[4] / LFRA M E#

LAD[3:0] / FWH[3:0]

LFRAME# / FWH[4]

LDRQ[0]#

LDRQ[1]# / GPIO[23]

SMBDATA

SMBCLK

SMBALERT# / GPIO[11]

LAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

Platform

LAN

Connect

SATA[2,0]TXP, SATA[2,0]TXN

SATA[2,0]RXP, SATA[2,0]RXN

SATARBIAS

SATARBIAS#

SATA[2,0]GP/GPIO[36,21]

SATALED#

SATACLKREQ#

Serial ATA

Interface

PCI

Express*

Interface PETp[6:1], PETn[6:1]

PERp[6:1], PERn[6:1]

SPI

SPI_CS#

SPI_MISO

SPI_MOSI

SPI_ARB

SPI_CLK

Digital

Home El_RSVD / GPIO26

El_STATE[1:0] /

GPIO[28:27

Digital

Home

Only

Signal Description

54 Intel ® ICH7 Family Datasheet

Figure 2-3. Interface Signals Block Diagram (Ultra Mobile Only)

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

DPRSTP#

SLP_S3#

SLP_S4#

SLP_S5#

PWROK

PWRBTN#

RI#

WAKE#

SUS_STAT# / LPCPD#

SUSCLK

VRMPWRGD

BMBUSY# / GPIO[0]

STP_PCI#

STP_CPU#

BATLOW#

DPRSLPVR

PLTRST#

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ3#

REQ4# / GPIO[22]

REQ5# / GPIO[1]

GNT3]#

GNT4# / GPIO[48]

GNT5# / GPIO[17]

PME#

CLKRUN#

PCICLK

PCIRST#

PLOCK#

SERR#

ICH7 Signals Ultra Mobile

PCI

Interface

DCS1#

DCS3#

DA[2:0]

DD[15:0]

DDREQ

DDACK#

DIOR# (DWSTB / RDMARDY#)

DIOW# (DSTOP)

IORDY ( DRSTB / WDMARDY#)

IDE

Interface

Power

Mgnt.

Interrupt

Interface

A20M#

FERR#

IGNNE#

INIT#

INIT3_3#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD / GPIO[49]

DPSLP#

Processor

Interface

USB

SERIRQ

PIRQ[H:E]# / GPIO[5:2]

IDEIRQ

USBP[7:0]P

USBP[7:0]N

OC[4:0]#

OC[5]# / GPIO[29]

OC[6]# / GPIO[30]

OC[7]# / GPIO[31]

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLK14

CLK48

DMI_CLKP, DMI_CL K N

RTC

Clocks

Misc.

Signals

SPKR

RTCRST#

TP3

General

Purpose

I/O

GPIO[39:37,25:24,19,1

5:12,10:6]

INTRUDER#

LINKALERT#

DMI[1:0]TXP, DMI[1:0]TXN

DMI[1:0]RXP, DMI[1:0]RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

ACZ_RST#, ACZ_SYNC,

ACZ_SDOUT

ACZ_SDIN[2:0]

ACZ_BIT_CLK

Intel®High

Definition

Audio

Firmware

Hub

System

Mgnt.

FWH[3:0] / LAD[3:0]

FWH[4] / LFRAME#

LAD[3:0] / FWH[3:0]

LFRAME# / FWH[4]

LDRQ0#

LDRQ1# / GPIO[23]

SMBDATA

SMBCLK

SMBALERT# / GPIO[11]

Intel ® ICH7 Family Datasheet 55

Signal Description

2.1 Direct Media Interface (DMI) to Host Controller

2.2 PCI Express* (Desktop and Mobile Only)

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI[0:1]TXP,

DMI[0:1]TXN

DMI[2:3]TXP,

DMI[2:3]TXN

(Desktop and

Mobile Only)

O Direct Media Interface Differential Transmit Pai r 0:3

DMI[0:1]RXP,

DMI[0:1]RXN

DMI[2:3]RXP,

DMI[2:3]RXN

(Desktop and

Mobile Only)

I Direct Media Interface Differential Receive Pair 0:3

DMI_ZCOMP I Impedance Compensation Input: Determines DMI input impedance.

DMI_IRCOMP O Impedance/Current Compensati on Output: Determines DMI

output impedance and bias current.

Table 2-2. PCI Express* Signals

Name Type Description

PETp[1:4],

PETn[1:4] O PCI Express* Differential Transmit Pair 1:4

PERp[1:4],

PERn[1:4] I PCI Express Differential Receive Pair 1:4

PETp[5:6],

PETn[5:6]

(Intel® ICH7R/

ICH7DH/ICH7-M DH

Only)

OPCI Express* Differential Transmit Pair 5:6

Re served: ICH7/IC H7-M

PERp[1:4],

PERn[5:6]

(ICH7R/ICH7DH/

ICH7-M DH Only)

IPCI Express Differential Receive Pair 5:6

Re served: ICH7/IC H7-M

Signal Description

56 Intel ® ICH7 Family Datasheet

2.3 Platform LAN Connect Interface (Desktop and

Mobile Only)

2.4 EEPROM Interface (Desktop and Mobile Only)

2.5 Firmware Hub Interface (Desktop and Mobile

Only)

Table 2-3. Platform LAN Connect Interface Signals

Name Type Description

LAN_CLK I LAN I/F Clock: This signal is driven by the Platform LAN Connect

component. The frequency range is 5 MHz to 50 MHz.

LAN_RXD[2:0] I Received Data: The Platform LAN Connect component uses these

signals to transfer data and control info rmation to the integrated LAN

controller. These signals have integrated weak pull-up resistors.

LAN_TXD[2:0] O Transmit Data: The integrated LAN controller uses these signals to

transfer data and control information to the Platform LAN Connect

component.

LAN_RSTSYNC O LAN Reset/Sync: The Platform LAN Connect component’s Reset and

Sync signals are multiplexed onto this pin.

Table 2-4. EEPROM Interface Signals

Name Type Description

EE_SHCLK O EEPROM Shift Clock: This signal is the serial shift clock output to the

EEPROM.

EE_DIN I EEPROM Data In: This signal transfers data from the EEPROM to the

Intel® ICH7. This signal has an integrated pull-up resistor.

EE_DOUT O EEPROM Data Out: This signal transfers data from the ICH7 to the

EEPROM.

EE_CS O EEPROM Chip Select: This is the chip select signal to the EEPROM.

Table 2-5. Firmware Hub Interface Signal s

Name Type Description

FWH[3:0] /

LAD[3:0] I/O Firmware Hub Signals: These signals are multiplexed with the LPC

address signals.

FWH4 /

LFRAME# OFirmware Hub Signals: This signal is multiplexe d with the LPC LFRAME#

signal.

Intel ® ICH7 Family Datasheet 57

Signal Description

2.6 PCI Interface

Table 2-6. PCI Interface Signals (Sheet 1 of 3)

Name Type Description

AD[31:0] I/O

PCI Address/Data: AD[31:0] is a multiplexed address and data bus.

During the first clock of a transaction, AD[31:0] contain a physical

address (32 bits). During subsequent clocks, AD[31:0] contain data. The

Intel® ICH7 will drive all 0s on AD[31:0] during the address phase of all

PCI Special Cycles.

C/BE[3:0]# I/O

Bus Command and Byte Enables: The command and byte enable

signals are multiplexed on the same PCI pins. During the address phase

of a transaction, C/BE[3:0]# define the bus command. During the data

phase, C/BE[3:0]# define the Byte Enables.

All command encodings not shown are reserved. The ICH7 does not

decode reserved values, and therefore will not respond if a PCI master

generates a cycle using one of the reserved values.

DEVSEL# I/O

Device Sele ct: The ICH7 asserts DEVSEL# to claim a PCI transaction.

As an output, the ICH7 asserts DEVSEL# when a PCI master peripheral

attempts an access to an internal ICH7 address or an address destined

DMI (main memory or graphics). As an input, DEVSEL# indicates the

response to an ICH7-initiated transaction on the PCI bus. DEVSEL# is

tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-

stated by the ICH7 until driven by a target device.

FRAME# I/O

Cycle Frame: The current initiator drives FRAME# to indicate the

beginning and duration of a PCI transaction. While the initiator asserts

FRAME#, data transfers continue. Wh en the initiator negates FRAME#,

the transaction is in the final data phase. FRA ME# is an input to the

ICH7 when the ICH7 is th e target, and FRAME# is an output from the

ICH7 when the ICH7 is the initiator. FRAME# remains tri-stated by the

ICH7 until driven by an initiator.

IRDY# I/O

Initiator Ready: IRDY# indicates the ICH7's ability, as an initiator, to

complete the current data phase of the transaction. It is used in

conjunction with TRDY#. A data phase is completed on any clock both

IRDY# and TRDY# are sampled asserted. During a write, IRDY#

indicates the ICH7 has valid data present on AD[31:0]. During a read, i t

indicates the ICH7 is prepared to latch data. IRDY# is an input to the

ICH7 when the ICH7 is the target and an output from the ICH7 when the

ICH7 is an initiator. IRDY# remains tri-stated by t he ICH7 until driven by

an initiator.

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge

0001b Special Cycle

0010b I/O Read

0011b I/O Write

0110b Memory Read

0111b Memory Write

1010b Configuration Read

1011b Configuration Write

1100b Memory Read Multiple

1110b Memory Read Line

1111b Memory Write and Invalidate

Signal Description

58 Intel ® ICH7 Family Datasheet

TRDY# I/O

Target Ready: TRDY# indicates the Intel® ICH7's ability as a target to

complete the current data phase of the transaction. TRDY# is used in

conjunction with IRDY#. A data phase is completed when both TRDY#

and IRDY# are sampled asserted. During a read, TRDY# indicates that

the ICH7, as a target, has placed vali d data on AD[31:0]. During a write,

TRDY# indicat es th e ICH7, as a targe t i s prepared to latch data. TRDY#

is an input to the ICH7 when the ICH7 is the initiator and an output from

the ICH7 when the ICH7 is a target. TRD Y# is tri-stated from the le ading

edge of PLTRST#. TRDY# remains tri-stated by the ICH7 until driven by

a target.

STOP# I/O

Stop: STOP# indicates that the ICH7, as a target, is re qu es ti ng th e

initiator to stop the current transaction. STOP# causes the ICH7, as an

initiator, to stop the current transaction. STOP# is an output when the

ICH7 is a target and an input when the ICH7 is an initiator.

PAR I/O

Calculated/Checked Parity: PAR uses “even” parity calculated on 36

bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH7

counts the number of 1s within the 36 bits plus PAR and the sum is

always even. The ICH7 calculates PAR on 36 bits regardless of the valid

byte enables. The ICH7 generates P AR for address and data phases and

only ensures PAR to be valid one PCI clock after the corresponding

address or data phase. The ICH7 drives and tri-states PAR identically to

the AD[31:0] lines except that the ICH7 delays PAR by exactly one PCI

clock. P AR is an output during the addre ss phase (delay ed one clock) for

all ICH7 initiated transactions. PAR is an output during the data phase

(delayed one clock) when the ICH7 is the initiator of a PCI write

transaction, and when it is the target of a read tr ansaction. ICH7 checks

parity when it is the target of a PCI write transaction. If a parity error is

detected, th e ICH7 will set the appropriate internal status bits, and has

the option to generate an NMI# or SMI#.

PERR# I/O

Parity Error: An external PCI device drives PERR# when it receives

data that has a parity error. The ICH7 drives PERR# when it detects a

parity error. The ICH7 can either generate an NMI# or SMI# upon

detecting a parity error (either detected internally or reported via the

PERR# signal).

REQ[3:0]#

REQ4# /

GPIO22

REQ5# /

GPIO1

PCI Requests: The ICH7 supports up to 6 masters on the PCI bus. The

REQ4# and REQ5# pins can instead be used as a GPIO.

NOTE: REQ[2:0]# are no t on Ultra Mobile.

GNT[3:0]#

GNT4# /

GPIO48

GNT5# /

GPIO17#

PCI Grants: The ICH7 supports up to 6 masters on the PCI bus. The

GNT4# and GNT5# pins can instead be used as a GPIO.

Pull-up resistors are not required on these signals. If pull-ups are used,

they should be tied to the Vcc3_3 power rail. GNT5#/GPIO17 has an

internal pull-up.

NOTE: GNT[2:0]# are not on Ultra Mobile.

PCICLK I

PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all

transactions on the PCI Bus.

NOTE: (Mobile/Ultra Mobile Only) This clock does not stop based on

STP_PCI# signal. PCI Clock only stops based on SLP_S3#.

PCIRST# O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR

of the primary interface PLTRST# signal and the state of the Secondary

Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).

Table 2-6. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Intel ® ICH7 Family Datasheet 59

Signal Description

2.7 Serial ATA Interface (Desktop and Mobile Only)

PLOCK# I/O

PCI Lock: This signal indicates an exclusive bus operation and may

require multiple transactions to complete. The ICH7 asserts P LOCK#

when it performs non-exclusive transactions on the PCI bus. PLOCK# is

ignored when PCI masters are granted the bus in desktop

configurations. Devices on the PCI bus (other than the ICH7 ) are not

permitted to assert the PLOCK# signal in mobile/Ultra Mobile

configurations.

SERR# I/OD Syst em Error: SERR# can be pulsed active by any PCI device that

detects a system error condition. Upon sampling SERR# acti ve, the

ICH7 has the ability to generate an NMI, SMI#, or interrupt.

PME# I/OD

PCI Power Management Event: PCI peripherals drive PME# to wake

the system from low-power s tat es S1–S5. PME# assertion can also be

enabled to generate an SCI from the S0 state. In some case s the ICH7

may drive PME# activ e due to an inte rn al w ak e ev ent . The ICH 7 will not

drive PME# high, but it will be pulled up to VccSus3_3 by an internal

pull-up resistor.

Table 2-7. Serial ATA Interface Signals (Sheet 1 of 2)

Name Type Description

SATA0TXP

SATA0TXN OSerial ATA 0 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 0.

SATA0RXP

SATA0RXN ISerial ATA 0 Differential Receive Pair: These are inbound high-

speed differential signals from Port 0.

SATA1TXP

SATA1TXN

(Desktop Only) OSerial ATA 1 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 1. (Desktop Only)

SATA1RXP

SATA1RXN

(Desktop Only) ISerial ATA 1 Differential Receive Pair: These are inbound high-

speed differential signals from Port 1. (Desktop Only)

SATA2TXP

SATA2TXN OSerial ATA 2 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 2.

SATA2RXP

SATA2RXN ISerial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

SATA3TXP

SATA3TXN

(Desktop Only) OSerial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3. (Desktop Only)

SATA3RXP

SATA3RXN

(Desktop Only) ISerial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3. (Desktop Only)

SATARBIAS O Serial ATA Resistor Bias: These are analog connection point s for

an external resistor to ground.

SATARBIAS# I Serial ATA Resistor Bias Complement: These are analog

connection points for an external resistor to ground.

Table 2-6. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

Signal Description

60 Intel ® ICH7 Family Datasheet

2.8 IDE Interface

SATA0GP /

GPIO21 I

Serial ATA 0 General Purpose: This is an in put pin which can be

configured as an interlock switch corresponding to SATA Port 0.

When used as an interlock switch status indication, this signal should

be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to

indicate that the switch is open.

If interlock switches are not required, this pin can be configured as

GPIO21.

SATA1GP

(Desktop Only)

/ GPIO19 I

Serial ATA 1 General Purpose: Same function as SAT A0GP, except

for SATA Port 1.

If interlock switches are not required, this pin can be configured as

GPIO19.

SATA2GP /

GPIO36 I

Serial ATA 2 General Purpose: Same function as SAT A0GP, except

for SATA Port 2.

If interlock switches are not required, this pin can be configured as

GPIO36.

SATA3GP

(Desktop Only)

/ GPIO37 I

Serial ATA 3 General Purpose: Same function as SAT A0GP, except

for SATA Port 3.

If interlock switches are not required, this pin can be configured as

GPIO37.

SATALED# OC

Serial ATA LED: This is an open-collector output pin driven during

SATA command activity. It is to be connected to external circuitry

that can provide the current to drive a platform LED. When active,

the LED is on. When tri-stated, the LED is off. An external pull-up

resistor to Vcc3_3 is required.

NOTE: An internal pull-up is ena bled only during PLTRST# assertion.

SATACLKREQ#/

GPIO35

(Native)

I/O (GP)

Serial ATA Clock Request: Th is is an open-drain output pin when

configured as SATACLKRE Q#. It is to connect to the system clock

chip. When active, request for SATA Clock running is asserted. When

tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An

external pull-up resistor is required.

Table 2-8. IDE Interface Signals (Sheet 1 of 2)

Name Type Description

DCS1# O IDE Device Chip Selects for 100 Range: Fo r ATA command register

block. This output signal is connected to the corresponding signal on the

IDE connector.

DCS3# O IDE Device Chip Select for 300 Range: For ATA control register

block. This output signal is connected to the corresponding signal on the

IDE connector.

DA[2:0] O

IDE Device Address: These output signals are connected to the

corresponding signals on the IDE connector. They are used to indicate

which byte in either the ATA command block or control block is being

addressed.

DD[15:0] I/O IDE Device Data: These signals directly drive the corresponding

signals on the IDE connector. There is a weak internal pull-down resist or

on DD7.

Table 2-7. Serial ATA Interface Signals (Sheet 2 of 2)

Name Type Description

Intel ® ICH7 Family Datasheet 61

Signal Description

DDREQ I

IDE Device DMA Req uest: This input signal is directly driven from the

DRQ signal on the IDE connector. It is asserted by the IDE device to

request a data transfer, and used in conjunction with the PCI bus master

IDE function and are not associated with any AT compatible DMA

channel. There is a weak internal pull-down resistor on this signal.

DDACK# O

IDE Device DMA Acknowledge: This signal directly drives the DAK#

signal on the IDE connector. DDACK# is asserted by th e Intel ® ICH7 to

indicate to IDE DMA slave devices that a given data transfer cycle

(assertion of DIOR # or DIOW#) is a DMA dat a transfer cy cle. This signal

is used in conjunction with the PCI bus master IDE function and are not

associated with any AT-compatible DMA channel.

DIOR# /

(DWSTB /

RDMARDY#) O

Disk I/O Read (PIO and Non-Ultra DMA): This is the command to

the IDE device th at i t may drive data on to th e D D li ne s . Dat a is latc hed

by the ICH7 on the deassertion edge of DIOR#. The IDE device is

selected either by the ATA register file chip selects (DCS1# or DCS3#)

and the DA lines, or the IDE DMA acknowledge (DDAK#).

Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write

strobe for writes to disk. When writing to disk, ICH7 drives valid data on

rising and falling edges of DWSTB.

Disk DMA R eady (Ultra DMA Reads from Disk): This is the DMA ready for

reads from disk. When reading from disk, ICH7 deasserts RDMARDY# to

pause burst data transfers.

DIOW# /

(DSTOP) O

Disk I/O Write (PIO and Non-Ultra DMA): This is the command to

the IDE device that it may latch data from the DD lines. Data is latc hed

by the IDE device on the deassertion edge of DIOW#. The IDE device is

selected either by the ATA register file chip selects (DCS1# or DCS3#)

and the DA lines, or the IDE DMA acknowledge (DDAK#).

Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.

IORDY /

(DRSTB /

WDMARDY#) I

I/O Channel Ready (PIO): This signal will keep the strobe active

(DIOR# on reads, DIOW# o n writes) longer than the minim um width. It

adds wait-states to PIO transfers.

Disk Read Strobe (Ultra DMA Reads from Disk): When reading from

disk, ICH7 latches data on rising and falling edges of this signal from

the disk.

Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this

is de-asserted by the disk to pause burst data transfers.

Table 2-8. IDE Interface Signals (Sheet 2 of 2)

Name Type Description

Signal Description

62 Intel ® ICH7 Family Datasheet

2.9 LPC Interface

2.10 Interrupt Interface

Table 2-9. LPC Interface Signals

Name Type Description

LAD[3:0] /

FWH[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pul l-

ups are provided.

LFRAME# /

FWH4 OLPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#

LDRQ1# /

GPIO23

(Desktop

and Mobile

only)

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to

request DMA or bus m a ster access. These signals are typically connected

to external Super I/O device. An internal pull-up resistor is provided on

these signals.

LDRQ1# may optionally be used as GPIO.

Table 2-10. Interrupt Signals

Name Type Description

SERIRQ I/O Serial Interrupt Request: This pin implements the serial interrupt

protocol.

PIRQ[D:A]#

(Desktop

and Mobile

only)

I/OD

PCI Interrupt Requests: In non-APIC mode th e PIRQx# signals can be

routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in

the Interrupt Steering section. Each PIRQx# line has a separate Route

Control register.

In APIC mode, these signals are connected to the internal I/O APIC in the

following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17,

PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy

interrupts.

PIRQ[H:E]#

/ GPIO[5:2] I/OD

PCI Interrupt Requests: In non-APIC mode th e PIRQx# signals can be

routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in

the Interrupt Steering section. Each PIRQx# line has a separate Route

Control register.

In APIC mode, these signals are connected to the internal I/O APIC in the

following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21,

PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy

interrupts. If not needed for interrupts, these signals can be used as

GPIO.

IDEIRQ I IDE Inter r u p t Request: This interrupt input is connected to the IDE

drive.

Intel ® ICH7 Family Datasheet 63

Signal Description

2.11 USB Interface

Table 2-11. USB Interface Signals

Name Type Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

I/O

Universal Serial Bus Port [1:0] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports

0 and 1. These ports can be routed to UHCI controller #1 or the EHCI

controller.

NOTE: No external resistors are required on these signals. The

Intel® ICH7 integrates 15 kΩ pull-downs and provides an

output driver impedance of 45 Ω which requires no external

series resistor

USBP2P,

USBP2N,

USBP3P,

USBP3N

I/O

Universal Serial Bus Port [3:2] Differential: These differential

pairs are used to trans mit data/address/command signals for ports 2

and 3. These ports can be routed to UHCI controller #2 or the EHCI

controller.

NOTE: No external resist ors are require d on these signals. The ICH7

integrates 15 kΩ pull-downs and provides an output driver

impedance of 45 Ω which requires no external series resistor

USBP4P,

USBP4N,

USBP5P,

USBP5N

I/O

Universal Serial Bus Port [5:4] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports

4 and 5. These ports can be routed to UHCI controller #3 or the EHCI

controller.

NOTE: No external resist ors are require d on these signals. The ICH7

integrates 15 kΩ pull-downs and provides an output driver

impedance of 45 Ω which requires no external series resistor

USBP6P,

USBP6N,

USBP7P,

USBP7N

I/O

Universal Serial Bus Port [7:6] Differential: These differential

pairs are used to transmit Data/Address/Command signals for ports

6 and 7. These ports can be routed to UHCI controller #4 or the EHCI

controller.

NOTE: No external resist ors are require d on these signals. The ICH7

integrates 15 kΩ pull-downs and provides an output driver

impedance of 45 Ω which requires no external series resistor

OC[4:0]#

OC5# / GPIO29

OC6# / GPIO30

OC7# / GPIO31

Overcurrent Indicators: These signals set corresponding bits in

the USB controllers to indic ate that an overcurrent condition has

occurred.

OC[7:5]# may optionally be used as GPIOs.

NOTE: OC[7:0]# are not 5 V tolerant.

USBRBIAS O USB Resistor Bias: Analog connection point for an external resistor.

Used to set transmit currents and internal load resistors.

USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an

external resistor. Used to set transmit currents and internal load

resistors.

Signal Description

64 Intel ® ICH7 Family Datasheet

2.12 Power Management Interface

Table 2-12. Power Management Interface Signals (Sheet 1 of 3)

Name Type Description

PLTRST# O

Platform Reset: The Intel® ICH7 asserts PLTRST# to reset devices

on the platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, et c.). The

ICH7 asserts PLTRST# during power-up and when S/W initiates a hard

reset sequence through the Reset Control register (I/O Register

CF9h). The ICH7 drives PLTRST# inactive a minimum of 1 ms after

both PWROK and VRMPWRGD are driven high. The ICH7 drives

PLTRST# active a minimum of 1 ms when initiated through the Reset

Control register (I/O Register CF9h).

NOTE: PLTRST# is in the VccSus3_3 well.

THRM# I Thermal Alarm: THRM# is an active low signal generated b y external

hardware to generate an SMI# or SCI.

THRMTRIP# I

Thermal Trip: When low, this signal indicates that a thermal trip from

the processor occurred, and the ICH7 will immediately transition to a

S5 state. The ICH7 will not wait for the processor stop grant cycle

since the proces sor has overheated.

SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. This signal

shuts off power to all non-critical systems when in S3 (Suspend To

RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

SLP_S4# O

S4 Sleep Control: SLP_S4# is for power plane control. This signal

shuts power to all non-critical systems when in the S4 (Suspend to

Disk) or S5 (Soft O ff) state.

NOTE: This pin must be used to control the DRAM power to use the

ICH7’s DRAM power-cycling feature. Refer to

Chapter 5.14.11.2 for details.

SLP_S5# O S5 Sleep Control: SLP_S5# is for power plane control. This signal is

used to shut power off to all non-critical systems when in the S5 (Soft

Off) states.

PWROK I

Power OK: When asserted, PWROK is an indication to the ICH7 that

core power has been stable for 99 ms and that PCICLK has been

stable for 1 ms. An ex ception to this rule is if the system is in S3HOT, in

which PWROK may or may not stay asserted even though PCICLK may

be inactive. PWROK can be driven asynchronously. When PWROK is

negated, the ICH7 asserts PLTRST#.

NOTE: PWROK must deassert for a minimum of three RTC clock

periods for the ICH7 to fully reset the power and properly

generate the PLTRS T # output.

PWRBTN# I

Power Button: The Power Button will cause SMI# or SCI to indicate a

system request to go to a sleep state. If the system is already in a

sleep state, this signal will cause a wake event. If PWRBTN# is

pressed for more than 4 seconds, this will cause an unconditional

transition (power button override) to the S5 state. Override will occur

even if the system is in the S1-S4 states. This signal has an internal

pull-up resistor and has an internal 16 ms de-bounce on the input.

RI#

(Desktop and

Mobile Only) IRing Indicate: This signal is an input from a modem. It can be

enabled as a wake event, and this is preserved across power failures.

Intel ® ICH7 Family Datasheet 65

Signal Description

SYS_RESET# I

System Reset: This pin forces an internal reset after being

debounced. The ICH7 will reset immediately if the SMBus is idle;

otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before

forcing a reset on the system.

RSMRST# I Resume Well Reset: This signal is used for resetting the resume

power plane logic.

LAN_RST#

(Desktop and

Mobile Only) I

LAN Reset: When asserted, the internal LAN controller will be put into

reset. This signal must be asserted for at least 10 ms after the re sume

well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in

mobile) is valid. When deasserted, this signal is an indication that the

resume (LAN for mobile) well power is stable.

NOTE: LAN_RST# should be tied to RSMRST#.

WAKE# I PCI Express* Wake Event: Sideband wake signal on PCI Express

asserted by components requesting wake up.

MCH_SYNC# I MCH SYNC : This input is internally ANDed with the PWROK input.

Connect to the ICH_SYNC# output of (G)MCH.

SUS_STAT# /

LPCPD# O

Suspend Status: This signal is asserted by the ICH7 to indicate that

the system will be entering a low power state soon. This can be

monitored by devices with memory that need to switch from normal

refresh to suspend refresh mode. It can also be used by other

peripherals as an indication that they should isolate their outp uts that

may be going to powered-off planes. This signal is called LPCPD# on

the LPC interface.

SUSCLK O Suspend Clock: This clock is an output of the RTC gener ator circuit to

use by other chips for refresh clock.

VRMPWRGD I VRM Power Good: This should be connected to be the processor’s

VRM Power Good signifying the VRM is stable. This signal is internally

ANDed with the PWROK input.

BM_BUSY#

(Mobile/Ultra

Mobile Only) /

GPIO0

(Desktop Only)

Bus Master Busy: This signal supports the C3 state. It provides an

indication that a bus master device i s busy. When this signal is

asserted, the BM_STS bit will be set. If this signal goes active in a C3

state, it is treated as a break event.

NOTE: This signal is internally synchronized using the PCICLK and a

two-stage synchronizer. It does not need to meet any

particular setup or hold time.

NOTE: In desktop configurations, this signal pin is a GPIO.

CLKRUN#

(Mobile/Ultra

Mobile Only)/

GPIO32

(Desktop Only)

I/O PCI Clock Run: This clock supports the PCI CLKRUN protocol. It

connects to peripherals that need to request clock restart or

prevention of clock stopping.

STP_PCI#

(Mobile/Ultra

Mobile Only) /

GPIO18

(Desktop Only)

Stop PCI Clock: This signal is an output to the external clock

generator for it to turn off the PCI clock. It is used to support PCI

CLKRUN# protocol. If this functionality is not needed, this signal ca n

be configured as a GPIO.

NOTE: Refered to as STPPCI# on Ultra Mobile.

Table 2-12. Power Management Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

66 Intel ® ICH7 Family Datasheet

2.13 Processor Interface

STP_CPU#

(Mobile/Ultra

Mobile Only) /

GPIO20

(Desktop Only)

Stop CPU Clock: This signal is an output to the external clock

generator for it to turn off the processor clock. It is used to support

the C3 state. If this functionality is not needed, this signal can be

configured as a GPIO.

NOTE: Refered to as STPCPU# on Ultra Mobile.

BATLOW#

(Mobile/Ultra

Mobile Only) /

TP0

(Desktop Only)

Battery Low: This signal is an input from battery to indicate that

there is insufficient power to boot the system. Assertion will prevent

wake from S3–S5 state. This signal can also be enabled to cause an

SMI# when asserted.

DPRSLPVR

(Mobile/Ultra

Mobile Only) /

GPIO16

(Desktop Only)

Deeper Sleep - Voltage Regulator: This signal is used to lower the

voltage of VRM during the C4 state. When the signal is high, th e

voltage regulator outputs the lower “Deeper Sleep” voltage. When low

(default), the voltage regulator outputs the higher “Normal” volt age.

DPRSTP#

(Mobile/Ultra

Mobile Only) /

TP1

(Desktop Only)

ODeeper Stop: This is a copy of the DPRSLPVR and it is active low.

Table 2-13. Processor Interface Signals (Sheet 1 of 3)

Name Type Description

A20M# O Mask A20: A20M# will go active based on either setting the appropriate

bit in the Port 92h register, or based on the A20GATE input being active.

CPUSLP# O

CPU Sleep: This signal puts the processor into a state that saves

substantial power compared to Stop-Grant state. However, during that

time, no snoops occur. The Intel® ICH7 can optionally assert the CPUSLP#

signal when going to the S1 state. (Desktop Only)

Reserved. (Mobile/Ultra Mobile Only)

FERR# I

Numeric Coprocessor Error: This signal is tied to the coprocessor error

signal on the processor. FERR# is only used if the ICH7 coprocessor error

reporting function is enabled in the OIC.CEN register (Chipset Config

Registers:Offset 31FFh: bit 1). If FERR# is asserted, the ICH7 generates

an internal IRQ13 to its int errupt controller unit. It is also used to gate the

IGNNE# signal to ensure that IGNNE# is not asserted to the processor

unless FERR# is active. FERR# requires an external weak pull-up to

ensure a high level when the coprocessor error function is disabled.

NOTE: FERR# can be used in some states for notification by the processor

of pending interrupt events. This functionality is independent of

the OIC register bit setting.

Table 2-12. Power Management Interface Signals (Sheet 3 of 3)

Name Type Description

Intel ® ICH7 Family Datasheet 67

Signal Description

IGNNE# O

Ignore Numeric Error: This signal is connected to the ignore error pin

on the processor. IGNNE# is only used if the ICH7 coprocessor error

reporting function is enabled in the OIC.CEN register (Chipset Config

Registers:Offset 31FFh: bit 1). If FERR # is active, indicating a coprocessor

error, a write to the Coprocessor Error register (I/O register F0h) causes

the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is

negated. If FERR# is not asserted when the Coprocessor Error register is

written, the IGNNE# signal is not asserted.

INIT# O Initialization: INIT# is asserted by the ICH7 for 16 PCI clocks to reset

the processor. ICH7 can be configured to support processor Built In Self

Test (BIST).

INIT3_3V#

(Desktop

and Mobile

Only)

OInitiali zat ion 3.3 V: This is the identical 3.3 V copy of INIT# intended

for Firmware Hub.

INTR O CPU Interrupt: INTR is asserted by the ICH7 to signal the processor that

an interrupt request is pending and needs to be serviced. It is an

asynchronous output and normally driven low.

NMI O

Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt

to the processor. The ICH7 can generate an NMI when either SER R# is

asserted or IOCHK# goes active via the SERIRQ# stream. The processor

detects an NMI when it detects a rising edge on NMI. NMI is reset by

setting the corresponding NMI source enable/disable bit in the NMI Status

and Control register (I/O Register 61h).

SMI# O System Management Interrupt: SMI# is an active low output

synchronous to PC ICLK. It is asserted by the ICH7 in response to one of

many enabled hardware or software events.

STPCLK# O

Stop Clock Request: STPCLK# is an active low output synchronous to

PCICLK. It is asserted by the ICH7 in response to one of many hardware

or software events. When the processor samples STPCLK# asserted, i t

responds by stopping its internal clock.

RCIN# I

Keyboard Controller Reset CPU: The keyboard controller can generate

INIT# to the processor. This saves the external OR gate with the ICH7’s

other sources of INIT#. When the ICH7 detects the assertion of this

signal, INIT# is generated for 16 PCI clocks.

NOTE: The ICH7 will ignore RCIN# assertion during transitions to the S1,

S3, S4, and S5 states.

Table 2-13. Processor Interface Signals (Sheet 2 of 3)

Name Type Description

Signal Description

68 Intel ® ICH7 Family Datasheet

2.14 SMBus Interface

2.15 System Management Interface

A20GATE I A20 Gate: A20GA TE is from the keyboard controller. The signal acts as an

alternative method to force the A20M# signal active. It saves the external

OR gate needed with various other chipsets.

CPUPWRGD

/ GPIO49 O

CPU Power Good: This signal should be connected to the processor’s

PWRGOOD input to indicate when the CPU power is valid. This is an output

signal that represents a logical AND of the ICH7’s PWROK an d VRMPWRGD

signals.

This signal may optionally be configured as a GPIO.

DPSLP#

(Mobile/Ultra

Mobile Only)

/ TP2

(Desktop

Only)

Deeper Sleep: DPSLP# is asserted by the ICH7 to the processor. When

the signal is low, the processor enters the deep sleep state by gating off

the processor core clock inside the processor. When the signal is high

(default), the processor is not in the deep sleep state.

Table 2-14. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11 ISMBus Alert: This signal is used to wake the system or generate

SMI#. If not used for SMBALERT#, it can be used as a GPIO.

Table 2-15. System Management Interface Signals

Name Type Description

INTRUDER# I Intruder Detect: This signal can be set to disable the system if the

chasis is detec ted o p en. This signal’s status is readable, so it can be

used like a GPIO if the Intruder Detection is not needed.

SMLINK[1:0]

(Desktop

and Mobile

Only)

I/OD

System Management Link: These signals provide a SMBus link to

optional external system management ASIC or LAN controller. External

pull-ups are required. Note that SMLINK0 corresponds to an SMBus

clock signal, and SMLINK1 corresponds to an SMBus Data signal.

LINKALERT#

(Desktop

and Mobile

Only)

I/OD SMLink Alert: This signal is an output of the integr ated LAN and input

to either the integrated ASF or an external management controller in

order for the LAN’s SMLINK slave to be serviced.

Table 2-13. Processor Interface Signals (Sheet 3 of 3)

Name Type Description

Intel ® ICH7 Family Datasheet 69

Signal Description

2.16 Real Time Clock Interface

2.17 Other Clocks

Table 2-16. Real Time Clock Interface

Name Type Description

RTCX1 Special Crystal Input 1: This signal i s connected to the 32.768 kHz crys tal. If

no external crystal is used, RTCX1 can be driven with the desired clock

rate.

RTCX2 Special Crystal Input 2: This signal i s connected to the 32.768 kHz crys tal. If

no external crystal is used, RTCX2 should be left floating.

Table 2-17. Other Clocks

Name Type Description

CLK14 I Oscillator Clock: This clock signal is used for the 8254 timers. It runs at

14.31818 MHz. This clock is permitted to stop during S3 (or lower)

states.

CLK48 I 48 MHz Clock: This clock signal is used to run th e USB controlle r. It runs

at 48.000 MHz. This clock is permitted to stop during S3 (or lower)

states.

SATA_CLKP

SATA_CLKN

(Desktop

and Mobile

Only)

I100 MHz Differential Clock: These signals are used to run the SATA

controller at 100 MHz. This cl ock is permitted to stop during S3/S4/S5

states.

DMI_CLKP,

DMI_CLKN I100 MHz Differential Clock: These signals are used to run the Direct

Media Interface. They run at 100 MHz.

Signal Description

70 Intel ® ICH7 Family Datasheet

2.18 Miscellaneous Signals

Table 2-18. Miscellaneous Signals

Name Type Description

INTVRMEN

(Desktop and

Mobile Only) IInternal Voltage Regulator Enable: This signal enables the internal

1.05 V Suspend re gul a tor wh en c onn e ct ed t o Vc c RTC. When connecte d

to Vss, the internal regulator is disabled

SPKR O

Speaker: The SPKR signal is the output of counter 2 and is internally

“ ANDed” with P ort 61h bit 1 to provide Speaker Data Enabl e. This signal

drives an external speaker driver device, which in turn drives the

system speaker. Upon PLTRST#, its output state is 0.

NOTE: SPKR is sampled at the rising edge of PWROK as a functional

strap. See Section 2.24.1 for more details. There is a weak

integrated pull-down resistor on SPKR pin.

RTCRST#

(Desktop and

Mobile Only) I

RTC Reset: When asserted, this signal resets register bits in the RTC

well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3 power

state), the RTCRST# input must be high when all other RTC

power planes are on.

2. In the case where the RTC battery is dead or missing on the

platform, the RTCRST# pin must rise before the RSMRST# pin.

TP0

(Desktop

Only) /

BATLOW#

(Mobile/Ultra

Mobile Only)

ITest Point 0: This signal must have an external pull-up to VccSus3_3.

TP1

(Desktop

Only) /

DPRSTP#

(Mobile/Ultra

Mobile Only)

OTest Point 1: Route signal to a test point.

TP2

(Desktop

Only) /

DPSLP#

(Mobile/Ultra

Mobile Only)

OTest Point 2: Route signal to a test point.

TP3 I/O Test Point 3: Route signal to a test point.

Intel ® ICH7 Family Datasheet 71

Signal Description

2.19 AC ’97/Intel® High Definition Audio Link

Note: AC ‘97 is not supported on Ultra Mobile.

Table 2-19. AC ’97/Intel® High Definition Audio Link Signals

Name1,2

NOTES:

1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.

2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This bit selects the mode

of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0 AC ‘97 mode is selected. When set to

1 Intel High Definition Audio mode is selected. The bit defaults to 0 (AC ‘97 mode).

Type Description

ACZ_RST# O AC ’97/Intel® High Definition Audio Reset: This signal is the

master hardware reset to external codec(s).

ACZ_SYNC O AC ’97/Intel High Definition Audio Sync: This signal is a 48 kHz

fixed rate sample sync to the codec(s). It is also used to encode the

stream number.

ACZ_BIT_CLK I/O

AC ’97 Bit Clock Input: This signal is a 12.288 MHz serial data

clock generated by the external codec(s). This signal has an

integrated pull-down resistor (see Note below).

Intel High Definition Audio Bit Clock Output: This signal is a

24.000 MHz serial data clock generated by the Intel High Definition

Audio controll er (the Intel® ICH7). This signal has an integrated pull-

down resistor so that ACZ_BIT_CLK doesn’t float when an Intel High

Definition Audio codec (or no codec) is connected but the signals are

temporarily configured as AC ’97.

ACZ_SDOUT O

AC ’97/Intel Hig h Definition Audi o Serial Data Out: This signal

is the serial TDM data output to the codec(s). This serial output is

double-pumped for a bit rate of 48 Mb/s for Intel High Definition

Audio.

NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a

functional strap. See Section 2.24.1 for more details. There is

a weak integrated pull-down resistor on the ACZ_SDOUT pin.

ACZ_SDIN[2:0] I

AC ’97/Intel High Definition Audio Serial Data In [2:0]: These

signals are serial TDM data inputs from the three codecs. The serial

input is single-pumped for a bit rate of 24 Mb/s for Intel® High

Definition Audio. These signals have integrated pull-down resistors

that are always enabled.

AZ_DOCK_EN#

(Mobile On ly) /

GPIO33 I/O

High Definition Audio Dock Enable: This signal controls the

external Intel HD Audio docking isolation logic. This is an active low

signal. When deas serted, the external docking switch is in isolate

mode. When asserted, the ext ernal docking switch electrically

connects the Intel HD Audio dock signals to the corresponding Intel®

ICH7 signals.

This signal is shared with GPIO33. This signal defaults to GPIO33

mode after PLTRST# reset and will be in the high state after

PLTRST# reset. BIOS is responsible for configuring GPIO33 to

AZ_DOCK_EN# mode.

AZ_DOCK_RST#

(Mobile On ly) /

GPIO34 I/O

High Definition Audio Dock Reset: This signal is a dedicated

AZ_RST# signal for the codec(s) in the dockin g station. Aside from

operating independently from the normal ACZ_RST# signal, it

otherwise works similarly to the ACZ_RST# signal.

This signal is shared with GPIO34. This signal defaults to GPIO34

mode after PL TRST# reset and will be in the low state after PLTRST#

reset. BIOS is responsible for configuring GPIO34 to

AZ_DOCK_RST# mode.

Signal Description

72 Intel ® ICH7 Family Datasheet

2.20 Serial Peripheral Interface (SPI) (Desktop and

Mobile Only)

2.21 Intel® Quick Resume Technology (Intel® ICH7DH

Only)

2.22 General Purpose I/O Signals

Table 2-20. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS# I/O SPI Chip Select: This chip select s ignal is also used as the SPI bus

request signal.

SPI_MISO I SPI Master IN Slave OUT: This signal is the data input pin for

Intel® ICH7.

SPI_MOSI O SPI Master OUT Slave IN: This signal is the data output pin for

ICH7.

SPI_ARB I SPI Arbitration: SPI_ARB is the SPI arbitration signal used to

arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet

Controller when Shared Flash is implemented.

SPI_CLK O SPI Clock: This signal is the SPI clock signal. During idle, the bus

owner will drive the clock signal low. 17.86 MHz.

Signal Name Type Description

EL_RSVD /

GPIO26 I/O

Intel® Quick Resume Techno logy Reserved: This signal is

reserved and should be left as a no connect when Intel Quick

Resume Technology is enable d.

NOTE: This signal cannot be reused as a GPIO when Intel Quick

Resume Technology is enable d.

EL_STATE[1:0] /

GPIO[28:27] I/O Intel Quick Resu m e T echn ology State: Int e l Quick Resume

Technology status signals that may optionally be used to drive front

chassis indicators. See Section 5.26.3 for details.

Table 2-21. General Purpose I/O Signals (Sheet 1 of 3)

Name1,2 Type Tolerance Power

Well Default Description

GPIO49 I/O V_CPU_IO V_CPU_IO Native Multiplexed with CPUPWRGD

GPIO48 I/O 3.3 V Core Native Multiplexed with GNT4#

GPIO[47:40] N/A N/A N/A N/A Not implemented.

GPIO[39:38]

(Desktop and

Mobile Only) I/O 3.3 V Core GPI Unmultiplexed.

GPIO37

(Desktop and

Mobile Only) I/O 3.3 V Core GPI Multiplexed with SATA3GP.

Intel ® ICH7 Family Datasheet 73

Signal Description

GPIO36

(Desktop and

Mobile Only) I/O 3.3 V Core GPI Multiplexed with SATA2GP.

GPIO35

(Desktop and

Mobile Only) I/O 3.3 V Core GPO Multiplexed with SATACLKREQ#.

GPIO34

(Desktop and

Mobile Only) I/O 3.3 V Core GP O Mobile Only: Multip lexed with

AZ_DOCK_RST#.

Desktop Onl y: Unmultiplexed.

GPIO33

(Desktop and

Mobile Only) I/O 3.3 V Core GP O Mobile Only: Multip lexed with

AZ_DOCK_EN#.

Desktop Onl y: Unmultiplexed.

GPIO32

(Desktop Only) I/O 3.3 V Core GPO

Mobile/Ult ra Mobile Only: this

GPIO is not implem ented and is

used instead as CLKRUN#.

Desktop Onl y: Unmultiplexed.

GPIO31 I/O 3.3 V Resume Native Multiplexed with OC7#

GPIO30 I/O 3.3 V Resume Native Multiplexed with OC6#

GPIO29 I/O 3.3 V Resume Native Multiplexed with OC5#

GPIO28

(Desktop and

Mobile Only) I/O 3.3 V Resume GPO

Intel® ICH7, ICH7R, and Mobile

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_STATE1

GPIO27

(Desktop and

Mobile Only) I/O 3.3 V Resume GPO

Intel® ICH7, ICH7R, and Mobile

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_STATE0

GPIO26

(Desktop and

Mobile Only) I/O 3.3 V Resume GPO

Intel® ICH7, ICH7R, and Mobile

Only: Unmultiplexed.

ICH7DH Only: Multiplexed with

EL_RSVD

GPIO25

(Desktop and

Mobile Only) I/O 3.3 V Resume GPO Unmultiplexed.

GPIO24

(Desktop and

Mobile Only) I/O 3.3 V Resume GPO Unmultiplexed. Not cl eared by

CF9h reset event.

GPIO23

(Desktop and

Mobile Only) I/O 3.3 V Core Native Mu lt ipl exed with LDRQ1#

GPIO22 I/O 3.3 V Core Native Multiplexed with REQ4#

GPIO21

(Desktop and

Mobile Only) I/O 3.3 V Core GPI Multiplexed with SATA0GP.

GPIO20

(Desktop Only) I/O 3.3 V Core GPO

Mobile/Ultra Mobile Only: GPIO is

not implemented and is used

instead as STP_CPU#.

Desktop Onl y: Unmultiplexed.

Table 2-21. General Purpose I/O Signals (S heet 2 of 3)

Name1,2 Type Tolerance Power

Well Default Description

Signal Description

74 Intel ® ICH7 Family Datasheet

2.23 Power and Ground

GPIO19

(Desktop and

Mobile Only) I/O 3.3 V Core GPI Multiplexed with SATA1GP.

GPIO18

(Desktop Only) I/O 3.3 V Core GPO

Mobile/Ultr a Mobile Only: GPIO is

not implemented and is used

instead as STP_PCI#.

Desktop On ly: Unmultipl exed.

GPIO17 I/O 3.3 V Core GPO Multiplexed with GNT5#.

GPIO16 I/O 3.3 V Core

Native

(Mobile/

Ultra

Mobile) /

GPO

(Desktop)

Mobile/Ultra Mobile Only:

Natively used as DPRSLPVR.

Desktop On ly: Unmultipl exed.

GPIO[15:12] I/O 3.3 V Resume GPI Unmultiplexed.

GPIO11 I/O 3.3 V Resume Native Multiplexed with SMBALERT#

GPIO[10:8] I/O 3 .3 V Resume GPI Unmultiplexed.

GPIO[7:6] I/O 3.3 V Core GPI Un multiplexed.

GPIO[5:2] I/OD 5 V Core GPI Multiplexed with PIRQ[H:E]#.

GPIO1 I/O 5 V Core GPI Multiplexed with REQ5#.

GPIO0

(Desktop Only) I/O 3.3 V Core GPI Mobile/Ultra Mobile Only:

Multiplexed with BM_BUSY#.

Desktop Only: Unmult iplexed

NOTES:

1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI,

but not both.

2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven

high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core

well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button

Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down.

Table 2-22. Power and Ground Signals (Sheet 1 of 3)

Name Description

Vcc3_3 These pins provide the 3.3 V supply for core well I/O buffers (22pins). This

power may be shut off in S3, S4, S5 or G3 states.

Vcc1_05 These pins provide the 1.05 V supply for core well logic (20 pins). This power

may be shut off in S3, S4, S5 or G3 states.

Vcc1_5_A These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may

be shut off in S3, S4, S5 or G3 states.

Vcc1_5_B These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may

be shut off in S3, S4, S5 or G3 states.

V5REF

(Desktop and

Mobile Only)

These pins provide the reference for 5 V tolerance on core well inputs (2 pins).

This power may be shut off in S3, S4, S5 or G3 states.

Table 2-21. General Purpose I/O Signals (Sheet 3 of 3)

Name1,2 Type Tolerance Power

Well Default Description

Intel ® ICH7 Family Datasheet 75

Signal Description

V5REF1

(Ultra Mobile

Only)

These pins provide the reference for 5 V tolerance on core well inputs (1 pin).

This power may be shut off in S3, S4, S5 or G3 states.

V5REF2

(Ultra Mobile

Only)

These pins provide the reference for 5 V tolerance on core well inputs (1 pin).

This power may be shut off in S3, S4, S5 or G3 states.

VccSus3_3

These pins provide the 3.3 V s uppl y for resume well I/O buffers (24 pins). This

power is not expected to be shut off unless the system is unplugged in desktop

configurations or the main battery is removed or completely drained and AC

power is not available in mobile/Ultra Mobile configurations.

VccSus1_05

These pins provide the 1.05 V supply for resume well logic ( 5 pins). This power

is not expected to be shut off unless the system is unplugged in desktop

configurations or the main battery is removed or completely drained and AC

power is not available in mobile/Ultra Mobile configurations.

This voltage may be generated internally (see Section 2.24.1 for strapping

option). If generated internally, these pins should not be connected to an

external supply.

V5REF_Sus

This pin provides the reference for 5 V tolerance on resume well inputs (1 pin).

This power is not expected to be shut off unless the system is unplugged in

desktop configurations or the main battery is removed or completely drained

and AC power is not available in mobile/Ultra Mobile configurations.

VccLAN3_3

(Mobile Only)

These pins provide the 3.3 V s upply for LAN Connect interface buffers (4 pins).

This is a separate power plane that may or may not be powered in S3–S5 states

depending upon the presence or absence of AC power and network connectivity.

This plane must be on in S0 and S1.

NOTE: In Desktop mode these signals are added to the VccSus3_3 group.

VccLAN1_05

(Mobile Only)

These pins provide the 1.05 V supply for LAN controller logic (2 pins). This is a

separate power plane that may or may not be powered in S3–S5 states

depending upon the presence or absence of AC power and network connectivity.

This plane must be on in S0 and S1.

NOTE: This voltage will be generated internally if VccSus1_05 is generated

internally (see Section 2.24.1 for strapping option). If generated

internally, these pins should not be connected to an external supply.

NOTE: In Desktop mode these signals are added to the VccSus1_05 group.

VccSusHDA

(Mobile/Ultra

Mobile Only)

This pin provides the suspend supply for Intel High Definition Audio (1 pins).

This pin can be either 1.5 V or 3.3 V. This power is not expected to be shut off

unless the main battery is removed or completely drained and AC power is not

available in mobile/Ultra Mobile configurations.

NOTE: In Desktop mode this signal is added to the VccSus3_3 group.

VccHDA

(Mobile/Ultra

Mobile Only)

This pin provides the core supply for Intel High Definition Audio (1 pin). This pin

can be either 1.5 V or 3.3 V. This power may be shut off in S3, S4, S5 or G3

states. This plane must be on in S0 and S1.

NOTE: In Desktop mode these signals are added to the Vcc3_3 group.

Table 2-22. Power and Ground Signals (Sheet 2 of 3)

Name Description

Signal Description

76 Intel ® ICH7 Family Datasheet

2.24 Pin Straps

2.24.1 Functional Straps

The following signals are used for static configuration. They are sampled at the rising

edge of PWROK to select configurations (ex cept as noted), and then revert later to their

normal usage. To invok e the associated mode, th e signal should be driv en at least four

PCI clocks prior to the time it is sampled.

VccRTC

This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the

RTC well (1 pin). This power is not expected to be shut off unless the RTC

battery is removed or completely drained.

NOTE: Implementations shoul d not attempt to clear CMOS by using a jumper to

pull VccRTC low. Clearing CMOS in an Intel® ICH7-based platform can be

done by using a jumper on RTCRST# or GPI.

VccUSBPLL

(Desktop and

Mobile Only)

This pin provides the 1.5 V supply for core well logic (1 pin). This signal is use d

for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be

powered even if USB not used.

VccDMIPLL This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used

for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.

VccSATAPLL

(Desktop and

Mobile Only)

This pin provides the 1.5 V supply for core well logic (1 pin). This signal is use d

for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must

be powered even if SATA not used.

V_CPU_IO These pins are powered by the same supply as the processor I/O voltage (3

pins). This supply is used to drive the processor interface signals listed in

Table 2-13.

Vss Grounds (194 pins).

Table 2-22. Power and Ground Signals (Sheet 3 of 3)

Name Description

Table 2-23. Functional Strap Definitions (Sheet 1 of 3)

Signal Usage When

Sampled Comment

ACZ_SDOUT

XOR Chain

Entrance /

PCI

Express*

Port Config

bit 1

Rising Edge of

PWROK

Allows entrance to XOR Chain testing when TP3

pulled low at rising edge of PWROK. See Chapter 25

for XOR Chain functionality information.

When TP3 not pulled low at rising edge of PWROK,

sets bit 1 of RPC.PC (Chipset Configuration

Registers:Offset 224h). See Section 7.1.34 for

details.

This signal has a weak internal pull-down.

ACZ_SYNC PCI Express

Port Config

bit 0

Rising Edge of

PWROK

This signal has a weak internal pull-down.

Sets bit 0 of RPC.PC (Chipset Configuration

Registers:Offset 224h). See Section 7.1.34 for

details.

EE_CS

(Desktop

and Mobile

Only)

Reserved This signal has a weak internal pull-down.

NOTE: This signal should not be pulled high.

Intel ® ICH7 Family Datasheet 77

Signal Description

EE_DOUT

(Desktop

and Mobile

Only)

Reserved This signal has a weak internal pull-up.

NOTE: This signal should not be pulled low.

GNT2# Reserved This signal has a weak internal pull-up.

NOTE: This signal should not be pulled low.

GNT3# Top-Block

Swap

Override

Rising Edge of

PWROK

The signal has a weak internal pull-up. If the signal

is sampled low, this indicates that the system is

strapped to the “top-block swap” mode (Intel®

ICH7 inverts A16 for all cycles targeting FWH BIOS

space). The status of t his strap is readable via the

Top Swap bit (Chipset Configuration

Registers:Offset 3414h:bit 0). Note that software

will not be able to clear the Top-Swap bit until the

system is rebooted without GNT3# being pulled

down.

GNT5# /

GPIO17#,

GNT4# /

GPIO48

Boot BIOS

Destination

Selection

Rising Edge of

PWROK

This field determines the destination of ac cesse s to

the BIOS memory range. Signals have weak

internal pull-ups. Also controllable via Boot BIOS

Destination bit (Chipset Configuration

Registers:Offset 3410h:bit 11:10)

(GNT5# is MSB)

01 = SPI (Desktop and Mobile Only)

10 = PCI

11 = LPC

GPIO16

(Desktop

Only) /

DPRSLPVR

(Mobile/Ultra

Mobile Only)

Reserved This signal has a weak internal pull-down.

NOTE: This signal should not be pulled high.

GPIO25

DMI AC/DC

Coupling

Selection

(Desktop

Only)

Rising Edge of

RSMRST#

This signal has a weak internal pull-up.The internal

pull-up is disabled within 100 ms after RSMRST#

deasserts.

If the signal is sampled high, the DMI interface is strapped

to operate in DC coupled mode (No coupling capacitors

are required on DMI differential pairs).

If the signal is sampled low, the DMI interface is strapped

to operate in AC coupled mode (Coupling capacitors are

required on DMI differential pairs).

NOTE: Board designer must ensure that DMI

implementation matches the strap selection.

NOTE: The signal must be held low at least 2 us after

RSMRST# deassertion to enable AC coupled

mode.

INTVRMEN

(Desktop

and Mobile

Only)

Integrated

VccSus1_05

VRM

Enable/

Disable

Always Enables integrated VccSus1_05 VRM when sampled

high.

Table 2-23. Functional Strap Definitions (Sheet 2 of 3)

Signal Usage When

Sampled Comment

Signal Description

78 Intel ® ICH7 Family Datasheet

NOTE: See Section 3.1for full details on pull-up/pull-down resistors.

2.24.2 External RTC Circuitry

To reduce RTC well power consumption, the ICH7 implements an internal oscillator

circuit that is sensitive to step voltage changes in VccRTC. Figure 2-4 shows an

example schematic recommended to ensure correct operation of the ICH7 RTC.

NOTE: C1 and C2 depend on crystal load.

LINKALERT#

(Desktop

and Mobile

Only)

Reserved This signal requires an external pull-up resistor.

REQ[4:1]# XOR Chain

Selection Rising Edge of

PWROK See Chapter 25 for functionality information.

SATALED#

(Desktop

and Mobile

Only)

Reserved This signal has a weak internal pull-up enabled only

when PLTRST# is asserted.

NOTE: This signal should not be pulled low.

SPKR No Reboot Rising Edge of

PWROK

The signal has a weak internal pull-down. If the

signal is sampled high, this in dicates that the

system is strapped to the “No Reboot” mode (ICH7

will disable the TCO Timer system reboot feature).

The status of this strap is readable via the NO

REBOOT bit (Chipset Config Registers:Offset

3410h:bit 5).

TP3 XOR Chain

Entrance Rising Edge of

PWROK

See Chapter 25 for functionality information. This

signal has a weak internal pull-up.

NOTE: This signal should not be pulled low unless

using XOR Chain testing.

Table 2-23. Functional Strap Definitions (Sheet 3 of 3)

Signal Usage When

Sampled Comment

Figure 2-4. Example External RTC Circuit

32.768 kHz

Xtal

1 µF

(20% tolerance) C2

15 pF

(5% tolerance)

VCCRTC

RTCX2

RTCX1

Vbatt

1 µF

(20% tolerance)

1 KΩ

VccSus3_3

15 pF

(5% tolerance)

10 MΩ

–

RTCRST#

20 KΩ

Schottky

Diodes

Intel ® ICH7 Family Datasheet 79

Intel® ICH7 Pin State s

3 Intel® ICH7 Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Nominal Notes

ACZ_BIT_CLK, AC ‘97 (Desktop and

Mobile Only) Pull-down 20 kΩ1, 2, 3

ACZ_RST#, AC ‘97 (Desktop and

Mobile Only) Pull-down 20 kΩ1, 2, 4

ACZ_SDIN[2:0], AC ‘97 (Desktop and

Mobile Only) Pull-down 20 kΩ2, 4

ACZ_SDOUT, AC ‘97 (Desktop and

Mobile Only) Pull-down 20 kΩ2, 4, 5

ACZ_SYNC, AC ‘97 (Desktop and Mobile

Only) Pull-down 20 kΩ2, 4, 5

ACZ_BIT_CLK, Intel® High Definition

Audio Pull-Down 20 kΩ2, 6, 7

ACZ_RST#, Intel High Definition Audio None N/A 2

ACZ_SDIN[2:0], Intel High Definition

Audio Pull-down 20 kΩ2, 4

ACZ_SDOUT, Intel High Definition Audio Pull-down 20 kΩ1, 2

ACZ_SYNC, Intel High Definition Audio Pull-down 20 kΩ2, 4

DD7 Pull-down 11.5 kΩ8

DDREQ Pull-down 11.5 kΩ8

DPRSLPVR / GPIO16 Pull-down 20 kΩ4, 9

EE_CS (Desktop and Mobile Only) Pull-down 20 kΩ10, 11

EE_DIN (Desktop and Mobile Only) Pull-up 20 kΩ10

EE_DOUT (Desktop and Mobile Only) Pull-up 20 kΩ10

GNT[1:0] Pull-up 20 kΩ10, 12

GNT[3:2],

GNT4# / GPIO48

GNT5# / GPIO17 Pull-up 20 kΩ10, 19

GPIO25 Pull-up 20 kΩ10, 13

LAD[3:0]# / FHW[3:0]# Pull-up 20 kΩ10

LAN_CLK (Desktop and Mobile Only) Pull-down 100 kΩ14

LAN_RXD[2:0] (Desktop and Mobile

Only) Pull-up 20 kΩ15

LDRQ[0] Pull-up 20 kΩ10

LDRQ1 / GPIO23 Pull-up 20 kΩ10

PME# Pull-up 20 kΩ10

PWRBTN# Pull-up 20 kΩ10

SATALE D# Pull-u p 15 kΩ16

Intel® ICH7 Pin State s

80 Intel ® ICH7 Family Datasheet

NOTES:

1. The pull-down resistors on ACZ_BIT_CLK (AC ‘97) and ACZ_RST# are enabled when

either:

- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or

- Both Function 2 and Function 3 of Device 30 are disabled.

Otherwise, the inte grated Pull-down resistor is disabled.

2. The AC ‘97/Intel High Definition Audio Link signals may either all be configured to be an

AC-Link or an Intel High Definition Audio Link.

3. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ.

4. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.

5. The pull-down resistors on ACZ_SYNC (AC ‘97) and ACZ_SDOUT (AC ‘97) are enabled

during reset and also enabled when either:

- The LSO bit (bit 3) in the AC ’97 Global Control Register (D30:F2:2C) is set to 1, or

- Both Function 2 and Function 3 of Device 30 are disabled.

Otherwise, the inte grated Pull-down resistor is disabled.

6. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.

7. The pull-down on this signal (in Intel High Definition Audio mode) is only enable d wh en in

S3COLD.

8. Simulation data shows that these resistor values can range from 5.7 kΩ to 28.3 kΩ.

9. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

10. Simulation data shows that these resistor values can range from 15 kΩ to 35 kΩ.

11. The pull-down on this signal is only enabled when LAN_RST# is asserted.

12. The internal pull-u p is enabled only when the PCIRST# pin is driven low and the PWROK

indication is high.

13. Internal pull-up is enabled during RSMRST# and is disabled wi thin 100 ms after RSMRST#

de-asserts.

14. Simulation data shows that these resistor values can range from 45 kΩ to 170 kΩ.

15. Simulation data shows that these resistor values can range from 15 kΩ to 30 kΩ.

16. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The

internal pull-up is only enabled only during PLTRST# assertion.

17. Simulation data shows that these resistor values can range from 10 k W to 30 kW.

18. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ

19. The internal pull-up is enabled only when PCIRST# is low.

3.2 IDE Integrated Series Termination Resistors

Table 3-2 shows the ICH7 IDE signals that have integrated series termination resistors.

NOTE: Simulation data i ndicates that the integrated series termination resistors are a nominal

33 Ω but can range from 21 Ω to 75 Ω.

SPI_ARB (Desktop and Mobile Only) Pull-down 20 kΩ10

SPI_CLK (Desktop and Mobile Only) Pull-down 20 kΩ10

SPKR Pull-down 20 kΩ4

TP3 Pull-up 20 kΩ17

USB[7:0] [P,N] Pull-down 15 kΩ18

Table 3-1. Integrated Pull-Up and Pull-Down Resis tors (Sheet 2 of 2)

Signal Resistor Nominal Notes

Table 3-2. IDE Series Termination Resistors

Signal Integrated Series Termination Resistor Value

DD[15:0], DIOW#, DIOR#, DREQ ,

DDACK#, IORDY, DA[2:0], DCS1#,

DCS3#, IDEIRQ approximately 33 Ω (See Note )

Intel ® ICH7 Family Datasheet 81

Intel® ICH7 Pin State s

3.3 Output and I/O Signals Planes and States

Table 3-3 and Table 3-4 show the power plane associated with the output and I/O

signals, as well as the state at various times. Within the table, the following terms are

used:

“High-Z” Tri-state. ICH7 not driving the signal high or low.

“High” ICH7 is driving the signal to a logic 1

“Low” ICH7 is driving the signal to a logic 0

“Defined” Driven to a level that is defined by the function (will be high or

low)

“Undefined” ICH7 is driving the signal, but the value is indeterminate.

“Running” Clock is toggling or signal is transitioning because function not

stopping

“Off” The power plane is off, so ICH7 is not driving

Note that the signal levels are the same in S4 and S5, except as noted.

ICH7 suspend well signal states are indeterminate and undefined and may glitch,

including input signals acting as outputs, prior to RSMRST# deassertion. This does not

apply to LAN_RST#, SLP_S3#, SLP_S4# and SLP_S5#. These signals are determinate

and defined prior to RSMRST# deassertion.

ICH7 core well signal states are indeterminate and undefined and may glitch, including

input signals acting as outputs, prior to PWROK assertion. This does not apply to

FERR# and THRMTRIP#. These signals are de terminate and defined prior to PWROK

assertion.

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 1 of 5)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

S1 S3COLD3S4/S5

PCI Express*

PETp[4:1],

PETn[4:1]

PETp[6:5],

PETn[6:5]

(Intel® ICH7R and

ICH7DH Only)

Core High High4Defined Off Off

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core High High4Defined Off Off

Intel® ICH7 Pin State s

82 Intel ® ICH7 Family Datasheet

PCI Bus

AD[31:0] Core Low Undefined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Off Off

DEVSEL# Core High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z Off Off

GNT[3:0]#

GNT4# / GPIO48

GNT5# / GPIO17 Core High-Z with

Internal Pull-

up High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Off Off

PCIRST# Suspend Low High High Low Low

PERR# Core High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] /

FWH[3:0] Core High High High Off Off

LFRAME# / FWH[4] Core High High High Off Off

LAN Connect and EEPROM Interface

EE_CS Suspend Low Running Defined Defined Defined

EE_DOUT Suspend High High Defined Defined Defined

EE_SHCLK Suspend High-Z Running Defined Defined Defined

LAN_RSTSYNC Suspend High Low Defined Defined Defined

LAN_TXD[2:0] Suspend Low Low Defined Defined Defined

IDE Interface

DA[2:0] Core Undefined Undefined Undefined Off Off

DCS1#, DCS3# Core High High High Off Off

DD[15:8], DD[6:0] Core High-Z High-Z High-Z Off Off

DD[7] Core Low Low Low Off Off

DDACK# Core High High High Off Off

DIOR#, DIOW# Core High High High Off Off

SATA Interface

SATA[3:0]TXP,

SATA[3:0]TXN Core High-Z High-Z Defined Off Off

SATALED# Core High-Z High-Z Defined Off Off

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 2 of 5)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

S1 S3COLD3S4/S5

Intel ® ICH7 Family Datasheet 83

Intel® ICH7 Pin State s

SATARBIAS Core High-Z High-Z High-Z Off Off

SATA3GP / GPIO37

SATA2GP / GPIO36

SATA1GP / GPIO19

SATA0GP / GPIO21

Core Input Input Driven Driven Driven

SATAC LKREQ# /

GPIO35 Core Low Low Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

GPIO[5:2] Core High-Z High-Z High-Z Off Off

SERIRQ Core High-Z High-Z High-Z Off Off

USB Interface

USBP[7:0][P,N] Suspend Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined

OC[7:5]# /

GPIO[31:29] Suspend Input Input Driven Driven Driven

Power Management

PLTRST# Suspend Low High High Low Low

SLP_S3# Suspend Low High High Low Low

SLP_S4# Suspend Low High High High Low

SLP_S5# Suspend Low High High High Low5

SUS_STAT# Suspend Low High High Low Low

SUSCLK Suspend Low Running

Processor Interface

A20M# Core Dependant

on A20GATE

Signal See Note 6 High Off Off

CPUPWRGD /

GPIO49 Core Defined High7High Off Off

CPUSLP# Core High High Defined Off Off

IGNNE# Core High See Note 6 High Off Off

INIT# Core High High High Off Off

INIT3_3V# Core High High High Off Off

INTR Core See Note 6 See Note 8 Low Off Off

NMI Core See Note 6 See Note 8 Low Off Off

SMI# Core High High High Off Off

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 3 of 5)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

S1 S3COLD3S4/S5

Intel® ICH7 Pin State s

84 Intel ® ICH7 Family Datasheet

STPCLK# Core High High Low Off Off

SMBus Interface

SMBCLK, SMBDATA Suspen d High-Z High-Z Defined Defined Defined

System Management Interface

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined

LINKALERT# Suspend High-Z High-Z Defined Defined Defined

Miscellaneous Si gnals

SPKR Core High-Z with

Internal Pull-

down Low Defined Off Off

AC ’97 Interface

ACZ_RST# Suspend Low Low Low Low Low

ACZ_SDOUT Core Low Running Low Off Off

ACZ_SYNC Core Low Running Low Off Off

Intel® High Defi nition Audio Interfac e

ACZ_RST# Suspend Low Low9Running Low Low

ACZ_SDOUT Core High-Z with

Internal Pull-

down Running Low Off Off

ACZ_SYNC Core High-Z with

Internal Pull-

down Running Low Off Off

ACZ_BIT_CLK Core High-Z with

Internal Pull-

down Low9 Low Off Off

Unmultiplexed GPIO Signals

GPIO[7:6, 0] Core Input Input Driven Off Off

GPIO[15:12,10:8] Suspend Input Input Driven Driven Driven

GPIO16 Core Low Low Defined Off Off

GPIO18 Core High See Note 10 Defined Off Off

GPIO20 Core High High Defined Off Off

GPIO24 Suspend No Change No Change Defined Defined Defined

GPIO25 Suspend High High11 Defined Defined Defined

GPIO[28:26] Suspend Low Low Defined Defined Defined

GPIO[33:32] Core High High Defined Off Off

GPIO34 Core Low Low Defined Off Off

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 4 of 5)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

S1 S3COLD3S4/S5

Intel ® ICH7 Family Datasheet 85

Intel® ICH7 Pin State s

NOTES:

1. The states of Vcc3_3 signals are taken at the times During P L TRST# and Immediat ely after

PLTRST#.

2. The states of VccSus3_3 signals are taken at the times During RSMRST# and Immediately

after RSMRST#.

3. In S3HOT, signal states are platform implementation specific, as some external components

and interfaces may be powered when the ICH7 is in the S3HOT state.

4. On the ICH7, PETp/n[4:1] are high u ntil port is enabled by software. On the ICH7R and

ICH7DH, PETp/n[6:1] are high until port is enabled by software.

5. SLP_S5# signals will be high in the S4 state.

6. ICH7 drives these signals High after the processor Reset.

7. CPUPWRGD represents a logical AND of the ICH7’s VRMPWRGD and PWROK signals, and

thus will be driven low by the ICH7 when either VRMPWRGD or PWROK are inactive. During

boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition

from low to High-Z.

8. ICH7 drives these signals Low before PWROK rising and Low after the processor Reset.

9. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be

Running.

10. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset

11. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the

deassertion of the RSMRST# pin.

GPIO[39:38] Core Input Input Driven Off Off

SPI Interface

SPI_CS# Suspend High High High High High

SPI_MOSI Suspend High High High High High

SPI_CLK Suspend Low Low Low Low Low

Intel® Quick Resume Technology Interface (I CH7DH Only)

EL_RSVD / GPIO26 Suspend Low Low Defined Defined Defined

EL_STATE[1:0] /

GPIO[28:27] Suspend Low Low Defined Defined Defined

Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only

Configurations (Sheet 5 of 5)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

S1 S3COLD3S4/S5

Intel® ICH7 Pin State s

86 Intel ® ICH7 Family Datasheet

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 1 of 4)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

C3/C4 S1 S3COLD3S4/

PCI Express* (Mobile Only)

PETp[6:1],

PETn[6:1] Core High High4Defined Defined Off Off

DMI

DMI[3:0]TXP,

DMI[3:0]TXN Core High High4Defined Defined Off Off

PCI Bus

AD[31:0] Core Low Undefined Defined Defined Off Off

C/BE[3:0]# Core Low Undefined Defined Defined Off Off

CLKRUN# Core Low Low Defined Off Off

DEVSEL# Core High-Z High-Z High-Z High-Z Off Off

FRAME# Core High-Z High-Z High-Z High-Z Off Off

GNT[3:0]#

GNT4# / GPIO48

GNT5# / GPIO17 Core High with

Internal Pull-

ups High High High Off Off

IRDY#, TRDY# Core High-Z High-Z High-Z High-Z Off Off

PAR Core Low Undefined Defined Defined Off Off

PCIRST# Suspend Low High High High Low Low

PERR# Core High-Z High-Z High-Z High-Z Off Off

PLOCK# Core High-Z High-Z High-Z High-Z Off Off

STOP# Core High-Z High-Z High-Z High-Z Off Off

LPC Interface

LAD[3:0] /

FWH[3:0] Core High High High High Off Off

LFRAME# /

FWH[4] Core High High High High Off Off

LAN Connect and EEPROM Interface (Mobile Only)

EE_CS LAN Low Running Defined Defined Note 5 Note 5

EE_DOUT LAN High High Defined Defined Note 5 Note 5

EE_SHCLK LAN High-Z Running Defined Defined Note 5 Note 5

LAN_RSTSYNC LAN High Low Defined Defined Note 5 Note 5

LAN_TXD[2:0] LAN Low Low Defined Defined Note 5 Note 5

IDE Interface

DA[2:0] Core Undefined Undefined Undefine

dUndefine

dOff Off

DCS1#, DCS3# Core High High High High Off Off

DD[15:8],

DD[6:0] Core High-Z High-Z Defined High-Z Off Off

Intel ® ICH7 Family Datasheet 87

Intel® ICH7 Pin State s

DD[7] Core Low Low Defined Low Off Off

DDACK# Core High High High High Off Off

DIOR#, DIOW# Core High High High High Off Off

SATA Interface (Mobile Only)

SATA[0]TXP,

SATA[0]TXN

SATA[2]TXP,

SATA[2]TXN

Core High-Z High-Z Defined Defined Off Off

SATALED# Core High-Z High-Z Defined Defined Off Off

SATARBIAS Core High-Z High-Z Defined Defined Off Off

SAT A2GP / GPIO36

SAT A0GP / GPIO21 Core Input Input Driven Driven Driven

SATAC LKREQ# /

GPIO35 Core Low Low Defined Defined Off Off

Interrupts

PIRQ[A:D]#,

PIRQ[H:E]# /

GPIO[5:2] Core High-Z High-Z Defined High-Z Off Off

SERIRQ Core High-Z High-Z Running High-Z Off Off

USB Interfac e

USBP[7:0][P,N] Suspend Low Low Low Low Low Low

USBRBIAS Suspend High-Z High-Z Defined Defined Defined Define

OC[7:5]# /

GPIO[31:29] Suspend Input Input Driven Driven Driven Driven

Power Management

PLTRST# Suspend Low High High High Low Low

SLP_S3# Suspend Low High High High Low Low

SLP_S4# Suspend Low High High High High Low

SLP_S5# Suspend Low High High High High Low6

STP_PCI# Core High High Defined High Low Low

STP_CPU# Core High High Low High Low Low

SUS_STAT# Suspend Low High High High Low Low

DPRSLPVR Core Low Low Low/

High7High Off Off

DPRSTP# Core High High Low/

High7High Off Off

SUSCLK Suspend Low Running

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 2 of 4)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

C3/C4 S1 S3COLD3S4/

Intel® ICH7 Pin State s

88 Intel ® ICH7 Family Datasheet

Processor Interface

A20M# Core Dependant

on A20GATE

Signal See Note 8 Defined High Off Off

CPUPWRGD /

GPIO49 Core See Note 9 High High High Off Off

IGNNE# Core High See Note 8 High High Off Off

INIT# Core High High High High Off Off

INIT3_3V# Core High High High High Off Off

INTR Core See Note 10 See Note 10 Defined Low Off Off

NMI Core See Note 10 See Note 10 Defined Low Off Off

SMI# Core High High Defined High Off Off

STPCLK# Core High High Low Low Off Off

DPSLP# Core High High High/Low High Off Off

SMBus Interface

SMBCLK,

SMBDATA Suspend High-Z High-Z Defined Defined Defined Define

System Management Interface

SMLINK[1:0] Suspend High-Z High-Z Defined Defined Defined Define

LINKALERT# Suspend High-Z High-Z Defined Defined Defined Define

Miscellaneous Signals

SPKR Core High-Z with

Internal Pull-

down Low Defined Defined Off Off

AC ’97 Interface (Mobile Only)

ACZ_RST# Suspend Low Low High Cold

Reset Bit

(High) Low Low

ACZ_SDOUT Core Low Running Running Low Off Off

ACZ_SYNC Core Low Running Running Low Off Off

Intel® High Definition Audio Interface

ACZ_RST# Suspend Low Low11 High TBD Low Low

ACZ_SDOUT Core High-Z with

Internal Pull-

down Running Running Low Off Off

ACZ_SYNC Core High-Z with

Internal Pull-

down Running Running Low Off Off

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 3 of 4)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

C3/C4 S1 S3COLD3S4/

Intel ® ICH7 Family Datasheet 89

Intel® ICH7 Pin State s

NOTES:

1. The states of Vcc3_3 signals are taken at the times during PL TRST# and Immediately after

PLTRST#.

2. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately

after RSMRST#.

3. In S3HOT, signal states are platform implementation specific, as some external components

and interfaces may be powered when the Intel® ICH7 is in the S3HOT state.

4. PETp/n[6:1] high until port is enabled by software.

5. LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3–S5 states

depending upon whether or not the LAN power planes are active.

6. SLP_S5# signals will be high in the S4 state.

7. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled

or low if it is disabled.

8. ICH7 drives these signals High after the processor Reset.

9. CPUPWRGD is an output that represents a logical AND of the Intel® ICH7’s VRMPWRGD

and PWROK signals, and thus will be driven low by ICH7 when either VRMPWRGD or

PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD

will be expected to transition from low to High.

10. IICH7 drives these si gnal s Low before PWROK rising and Low after the processor Reset.

ACZ_BIT_CLK Core High-Z with

Internal Pull-

down Low11 Running Low Off Off

AZ_DOCK_RST# /

GPIO34 Core Low Low11 Defined Defined Off Off

AZ_DOCK_EN# /

GPIO33 Core High High Defined Defined Off Off

Unmultiplexed GPIO Signals

GPIO[7:6] Core Input Input Driven Driven Off Off

GPIO[15:12,10:8] Suspend Input Input Driven Driven Driven Driven

GPIO18 Core High See N o te 12 Driven Driven Off Off

GPIO19 Core Input Input Driven Driven Off Off

GPIO24 Suspend No Change No Change Defined Defined Defined Define

GPIO25 Suspend High High13 Defined Defined Defined Define

GPIO[28:26] Suspend Low Low Defined Defined Defined Define

GPIO[39:37] Core Input Input Driven Driven Off Off

SPI Interface (Mobile Only)

SPI_CS# Suspend High High High High High High

SPI_MOSI Suspend High High High High High High

SPI_ARB Suspend Low Low Low Low Low Low

SPI_CLK Suspend Low Low Low Low Low Low

Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile

Only Configurations (Sheet 4 of 4)

Signal Name Power

Plane

During

PLTRST#1 /

RSMRST#2

Immediately

after

PLTRST#1 /

RSMRST#2

C3/C4 S1 S3COLD3S4/

Intel® ICH7 Pin State s

90 Intel ® ICH7 Family Datasheet

11. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset

HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be

Running.

12. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset

13. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the

deassertion of the RSMRST# pin.

3.4 Power Planes for Input Signals

Table 3-5 and Table 3-6 show the power plane associated with each input signal, as

well as what device drives the signal at various times. Valid states include:

High

Low

Static: Will be high or low, but will not change

Driven: Will be high or low, and is allowed to change

Running: For input clocks

ICH7 suspend well signal states are indeterminate and undefined and may glitch prior

to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and

SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.

ICH7 core well signal states are indeterminate and undefined and may glitch prior to

PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are

determinate and defined prior to PWROK assertion.

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3)

Signal Name Power Well Driver During Reset S1 S3COLD1S4/S5

A20GATE Core External

Microcontroller Static Low Low

ACZ_BIT_CLK

(AC ‘97 Mode) Core AC ’97 Codec Low Low Low

ACZ_SDIN[2:0] (AC ‘97

Mode) Suspend AC ’97 Codec Low Low Low

ACZ_SDIN[2:0] (Intel ®

High Definition Audio

Mode) Suspend Intel® High Definition

Audio Codec Low Low Low

CLK14 Core Clock Generator Running Low Low

CLK48 Core Clock Generator Running Low Low

DDREQ Core I DE Device Static Low Low

DMI_CLKP, DMI_CL KN Core Clock Generator Running Low Low

EE_DIN Suspend EEPROM Component Driven Driven Driven

FERR# Core Processor Static Low Low

PERp[4:1], PERn[4:1]

PERp[6:5], PERn[6:5]

(Intel® ICH7R and

ICH7DH Only)

Core PCI Express* Device Driven Driven Driven

DMI[3:0]RXP,

DMI[3:0]RXN Core (G)MCH Driven Low Low

IDEIRQ Core IDE Static Low Low

INTRUDER# RTC External Switch Driven Driven Driven

Intel ® ICH7 Family Datasheet 91

Intel® ICH7 Pin State s

INTVRMEN RTC External Pull-up or

Pull-down Driven Driven Driven

IORDY Core IDE Device Static Low Low

LAN_CLK Suspend LAN Conn ect

Component Driven Driven Driven

LAN_RST# Sus p end External RC Circuit High High High

LAN_RXD[2:0] Suspend LAN Connect

Component Driven Driven Driven

LDRQ0# Core LPC Devices High Low Low

LDRQ1# / GPIO232Core LPC Devices High Low Low

MCH_SYNC# Core (G)MCH Driven Low Low

OC[7:0]# Suspend External Pull-ups Driven Driven Driven

PCICLK Core Clock Generator Running Low Low

PME# Suspend Internal Pull-up Driven Driven Driven

PWRBTN# Suspend Internal Pull-up Driven Driven Driven

PWROK RT C System Power Supply Driven Low Low

RCIN# Core External

Microcontroller High Low Low

REQ[3:0]#,

REQ4# / GPIO2 22

REQ5# / GPIO1 22Core PCI Master Driven Low Low

RI# Suspend Serial Port Buffer Driven Driven Driven

RSMRST# RTC External RC Circuit High High High

RTCRST# RTC External RC Circuit High High High

SATA_CLKP, SATA_CLKN Core Clock Generator Running Low Low

SATA[3:0]RXP,

SATA[3:0]RXN Core SATA Drive D riven Driven Driven

SATARBIAS# Core External Pull-down Driven Driven Driven

SATA[3:0]GP /

GPIO[31:29,26]2Core External Device or

External Pull-up/Pull-

down Driven Driven Driven

SERR# Core PCI Bus Peripherals High Low Low

SMBALERT# / GPIO112Suspend Ext ernal Pull -up Driven Driven Driven

SYS_RESET# Suspend External Circuit Driven Driven Driven

THRM# Core Thermal Sensor Driven Low Low

THRMTRIP# Core Thermal Sensor Driven Low Low

TP0 Suspend External Pull -up High High High

TP3 Suspend Internal Pull-up High H igh High

USBRBIAS# Suspend External Pull-down Driven Driven Driven

VRMPWRGD Core Processor Voltage

Regulator High Low Low

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 2 of 3)

Signal Name Power Well Driver During Reset S 1 S3COLD1S4/S5

Intel® ICH7 Pin State s

92 Intel ® ICH7 Family Datasheet

NOTES:

1. In S3HOT, signal states are platform implementation specific, as some external components

and interfaces may be powered when the ICH7 is in the S3HOT state.

2. These signals can be configured as outputs in GPIO mode .

WAKE# Suspend External Pull-up Driven Driven Driven

SPI_MISO Suspend External Pull-up Driven Driven Driven

SPI_ARB Suspend Internal Pull-down Low Low Low

Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 3 of 3)

Signal Name Power Well Driver During Reset S1 S3COLD1S4/S5

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 1 of 3)

Signal Name Power

Well Driver During Reset C3/C4 S1 S3COLD1S4/S5

A20GATE Core External

Microcontroller Static Static Low Low

ACZ_BIT_CLK

(AC ‘97 mode)

(Mobile On ly) Core AC ’97 Codec Driven Low Low Low

ACZ_SDIN[2:0]

(AC ‘97 mode)

(Mobile On ly) Suspend AC ’97 Codec Driven Low Low Low

ACZ_SDIN[2:0]

(Intel® High

Definition Audio

Mode)

Suspend Intel® High Definition

Audio Codec Driven Low Low Low

BM_BUSY# /

GPIO01Core Graphics Component

[(G)MCH] Driven High Low Low

BATLOW# Suspend Power Supply High High High High

CLK14 Core Clock Generator Running Running Low Low

CLK48 Core Clock Generator Running Running Low Low

DDREQ Core IDE Device Driven Static Low Low

DMI_CLKP

DMI_CLKN Core Clock Generator Running Running Low Low

EE_DIN

(Mobile On ly) LAN EEPROM Component Driven Driven Note 2 Note 2

FERR# Core Processor Static Static Low Low

PERp[6:1],

PERn[6:1]

(Mobile On ly) Core PCI Express* Device Driven Driven Driven Driven

DMI[3:0]RXP,

DMI[3:0]RXN Core (G)MCH Driven Driven Low Low

IDEIRQ Core IDE Driven Static Low Low

INTRUDER# RTC External Switch Driven Driven Driven Driven

INTVRMEN

(Mobile On ly) RTC External Pull-up or Pull-

down Driven Driven Driven Driven

Intel ® ICH7 Family Datasheet 93

Intel® ICH7 Pin State s

IORDY Core IDE Device Static Static Lo w Low

LAN_CLK

(Mobile Only) LAN LAN Connect

Component Driven Driven Note 2 Note 2

LAN_RST#

(Mobile Only) Suspend Power Supply High High Static Static

LAN_RXD[2:0]

(Mobile Only) LAN LAN Connect

Component Driven Driven Note 2 Note 2

LDRQ0# Core LPC Devices Driven High Low Low

LDRQ1# /

GPIO233Core LPC Devices Driven High Low Low

MCH_SYNC# Core (G)MCH Driven Driven Low Low

OC[7:0]# Suspend External Pull-ups Driven Driven Driven Driven

PCICLK Core Clock Generator Running Running Low Low

PME# Suspend Internal Pull-up D riven Driven Driven Driven

PWRBTN# Suspend Internal Pull-up Driven Driven Driven Driven

PWROK RTC System Power Supply Driven Driven Low Low

RCIN# Core External

Microcontroller High High Low Low

REQ[3:0]#,

REQ4# / GPIO223

REQ5# / GPIO13Core PCI Mast er Driven Driven Low Low

RI# Suspend Serial Port Buffer Driven Driven Driven Driven

RSMRST# RTC External RC Circuit High High High High

RTCRST# RTC External RC Circuit High High High High

SATA_CLKP,

SATA_CLKN

(Mobile Only) Core Clock Generator Running Running Low Low

SATA[0]RXP,

SATA[0]RXN

SATA[2]RXP,

SATA[2]RXN

(Mobile Only)

Core SATA Drive Driven Driven Driven Driven

SATARBIAS#

(Mobile Only) Core External Pull-Down Driven Driven Driven Driven

SATA[2,0]GP

(Mobile Only) Core External Device or

External Pull-up/Pull-

down Driven Driven Driven Driven

SERR# Core PCI Bus Peripherals Driven High Low Low

SMBALERT# /

GPIO113Suspend External Pull-up Driven Driven Driven Driven

SYS_RESET# Suspend External Circuit Driven Driven Driven Driven

THRM# Core Thermal Sensor Driven Driven Low Low

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 2 of 3)

Signal Name Power

Well Driver During Re set C3/C4 S1 S3COLD1S4/S5

Intel® ICH7 Pin State s

94 Intel ® ICH7 Family Datasheet

NOTES:

1. In S3HOT, signal states are platform implementation specific, as some external components

and interfaces may be powered when the Intel® ICH7 is in the S3HOT state.

2. LAN Connect and EEPROM signals will either be “Driven” or “Low” in S3–S5 states

depending upon whether or not the LAN power planes are active.

3. These signals can be configured as outputs in GPIO mode .

THRMTRIP# Core Thermal Sensor Driven Driven Low Low

TP3 Suspend Internal Pull -up High High High High

USBRBIAS# Suspend External Pull-down Driven Driven Driven Driven

VRMPWRGD Core Processor Voltage

Regulator Driven Driven Low Low

WAKE# Suspend External Pull-up Driven Driven Driven Driven

SPI_MISO

(Mobile On ly) Suspend External Pull-up Driven Driven Driven Driven

SPI_ARB

(Mobile On ly) Suspend Internal Pull-down Low Low Low Low

Table 3-6. Power Plane for Input Signals for Mobile/Ultra Mobile Only Configurations

(Sheet 3 of 3)

Signal Name Power

Well Driver During Reset C3/C4 S1 S3COLD1S4/S5

Intel ® ICH7 Family Datasheet 95

Intel® ICH7 and System Clock Domains

4 Intel® ICH7 and System Clock

Domains

Table 4-1 shows the system clock domains. Figure 4-1 and Figure 4-2 show the

assumed connection of the various system components, including the clock generator

in desktop and mobile/ultra mobile systems. For complete details of the system

clocking solution, refer to the system’s clock generator component specification.

Table 4-1. Intel® ICH7 and System Clock Domains

Clock Domain Frequency Source Usage

Intel® ICH7

SATA_CLKP,

SATA_CLKN

(Desktop and

Mobile only)

100 MHz Main Clock

Generator Differential clock pair used for SATA.

ICH7

DMI_CLKP,

DMI_CLKN 100 MHz Main Clock

Generator Differential clock pair used for DMI.

ICH7

PCICLK 33 MHz Main Clock

Generator

Free-running PCI Clock to ICH7. This clock

remains on during S0 and S1 (in desktop) state,

and is expected to be shut off during S3 or

below in desktop configurations or S1 or below

in mobile/ultra mobile configurations.

System PCI 33 MHz Main Clock

Generator

PCI Bus, LPC I/F. These only go to external PCI

and LPC devices. Will stop based on CLKRUN#

(and STP_PCI#) in mobile/ultra mobile

configurations.

ICH7

CLK48 48.000 MHz Main Clock

Generator

Super I/O, USB controllers. Expected to be shut

off during S3 or below in desktop configurations

or S1 or below in mobile/ultra mobile

configurations.

ICH7

CLK14 14.31818

MHz Main Clock

Generator

Used for ACPI timer and Multimedia Timers .

Expected to be shut off during S3 or below in

desktop configurations or S1 or below in mobile/

ultra mobile configurations.

ICH7

ACZ_BIT_CLK

(Desktop and

Mobile only)

12.288 MHz AC ’97 Codec

AC-link. Generated by AC ’97 Codec. Can be

shut by codec in D3. Expected to be shut off

during S3 or below in desktop configurations or

S1 or below in mobi le configurations.

NOTE: For use only in AC ‘97 mode.

LAN_CLK

(Desktop and

Mobile only) 5 to 50 MHz LAN Connect

Component

Generated by the LAN Connect component.

Expected to be shut off during S3 or below in

desktop configurations or S1 or below in mobile

configurations.

SPI_CLK

(Desktop and

Mobile Only) 17.86 MHz ICH

Generated by the LAN Connect component.

Expected to be shut off during S3 or below in

desktop configurations or S1 or below in mobile

configurations.

Intel® ICH7 and System Clock Domains

96 Intel ® ICH7 Family Datasheet

Figure 4-1. Desktop Only Conceptual System Clock Diagram

Figure 4-2. Mobile Only Conceptual Clock Diagram

Intel®

ICH7

PCI

Clocks

(33 MHz)

Clock

Gen. 14 .31818 MHz

48.000 MHz

32 kHz

XTAL SUSCLK# (32 kHz)

LA N Connec t

50 MHz

AC ’97 Codec(s)

12.288 MHz

33 MHz

14.31818 MHz

100 MHz

Diff. Pair 1 to 6

Differential

Clock Fan

Out Device

SATA 100 MHz Diff. Pair

DMI 100 MHz Diff. Pair

PCI Express

100 MHz

Diff. Pair s

High Defini tion Audio Codec(s)

24 MHz

48.000 MHz

Intel®

ICH7-M

32 kHz

XTAL

SUSC LK# (32 kHz)

14.31818 M H z

STP_CPU#

STP_PCI#

PCI Clocks

(33 M Hz )

Clock

Gen. 14.31818 MH z

48 MHz

LAN C onnect

100 MHz Diff. Pa ir

1 to 6

Differential

Clock Fan

Out Device

SATA 100 MHz Diff. Pair

DMI 100 MHz Diff. Pair PCI Express

100 MHz

D iff. Pa irs

AC ’97 Codec(s)

12.288 MHz

High Definition Audio Codec(s)

24 MHz

50 MHz

48.000 MH z

33 M H z

Intel ® ICH7 Family Datasheet 97

Intel® ICH7 and System Clock Domains

Figure 4-3. Ultra Mobile Only Conceptual Clock Diagram

33 MHz

14.31818 MHz

48.000 MHz

STP_CPU#

STP_PCI#

Clock

Generator

Intel®

ICH7-U

PCI Clocks

(33 MHz)

14.31818 MHz

48 MHz

DMI 100 MHz Diff Pair

High Definition Audio Codec(s)

24 MHz

32 kHz

XTAL SUSCLK# (32 kHz)

Intel® ICH7 and System Clock Domains

98 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 99

Functional Description

5 Functional Description

This chapter describes the functions and interfaces of the ICH7 family.

5.1 PCI-to-PCI Bridge (D30:F0)

The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of

the ICH7 implements the buffering and control logic between PCI and Direct Media

Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI

decoder in this device must decode the ranges for the DMI. All register contents are

lost when core well power is removed.

Direct Media Interface (DMI) is the chip-to-chip connection between the Memory

Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub

7 (ICH7). This high-speed interface integrates advanced priority-based servicing

allowing for concurrent traffic and true isochronous transfer capabilities. Base

functionality is completely software transparen t permitting current and legacy software

to operate normally.

To provide for true isochronous transfers and configurable Quality of Service (QoS)

transactions, the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two

channels provide a fixed arbitration scheme where VC1 is the highest priority. VC0 is

the default conduit of traffic for DMI and is always enabled. VC1 must be specifically

enabled and configured at both ends of the DMI link (i.e., the ICH7 and (G)MCH).

Configuration registers for DMI, virtual channel support, and DMI active state power

management (ASPM) are in the RCRB space in the Chipset Config Registers

(Section 7).

5.1.1 PCI Bus Interface

The ICH7 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.

The ICH7 integrates a PCI arbiter that supports up to six external PCI bus masters in

addition to the internal ICH7 requests.

5.1.2 PCI Bridge As an Initiator

The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge

generates the following cycle types:

5.1.2.1 Memory Reads and Writes

The bridge bursts memory writes on PCI that are received as a single packet from DMI.

Table 5-1. PCI Bridge Initiator Cycle Types

Command C/BE# Notes

I/O Read/Write 2h/3h Non-posted

Memory Read/Write 6h/7h Writes are posted

Configuration Read/Write Ah/Bh Non-posted

Special Cycles 1h Posted

Functional Description

100 Intel ® ICH7 Family Datasheet

5.1.2.2 I/O Reads and Writes

The bridge generates single DW I/O read and write cycles. When the cycle completes

on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is

retried, the cycle is kept in the down bound queue and may be passed by a postable

cycle.

5.1.2.3 Configuration Reads and Writes

The bridge generates single DW configuration read and write cycles. When the cycle

completes on the PCI bus, the bridge generates a corresponding completion. If the

cycle is retried, the cycle is kept in the down bound queue and may be passed by a

postable cycle.

5.1.2.4 Locked Cycles

The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI

bridge implements bus lock, which means the arbiter will not grant to an y agent except

DMI while locked.

If a locked read results in a target or master abort, the lock is not established (as per

the PCI Local Bus Specification). Agents north of the ICH7 must not forward a

subsequent locked read to the bridge if they see the first one finish with a failed

completion.

5.1.2.5 Target / Master Aborts

When a cycle initiated by the bridge is master/target aborted, the bridge will not re-

attempt the same cycle. Fo r multiple DW cycles, the bridge increments the address and

attempts the next DW of the transaction. For all non-postable cycles, a target abort

response packet is returned for each DW that w as master or target aborted on PCI. The

bridge drops posted writes that abort.

5.1.2.6 Secondary Master Latency Timer

The bridge implem ents a Master Late nc y Time r vi a the SLT register which, upon

expiration, causes the de-assertion of FRAME# at the next legal clock edge when there

is another active request to use the PCI bus.

5.1.2.7 Dual Address Cycle (DAC)

The bridge will issue full 64-bit dual address cycles for device memory-mapped

registers above 4 GB.

Intel ® ICH7 Family Datasheet 101

Functional Description

5.1.2.8 Memory and I/O Decode to PCI

The PCI bridge in the ICH7 is a subtractive decode agent, which follows the following

rules when forwarding a cycle from DMI to the PCI interface:

• The PCI bridge will positively decode any memory/IO address within its window

registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory

windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows.

• The PCI bridge will subtractively decode any 64-bit memory address not claimed

by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.

• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by

another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) set

• If BCTRL.IE (D 30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively

forward from primary to secondary called out ranges in the IO window per PCI

Local Bus Specification (I/O transactions addressing the last 768 bytes in each,

1-KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively

assuming the above rules.

• If BCTRL.VGA E (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively

forward from primary to secondary I/O and memory ranges as called out in the PCI

Bridge Specification, assuming the above rules are met.

5.1.3 Parity Error Detection and Generation

PCI parity errors can be detected and reported. The following behavioral rules apply:

• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE

(D30:F0:Off set 1Eh:bit 15).

• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) and one of the

parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD

(D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#.

— During a write cycle, the PERR# signal is active, or

— A data parity error is detected while performing a read cycle

• If an address or command parity error is detected on PCI and PCICMD.SEE

(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)

are all set, the bridge will set the PSTS.SSE (D30:F0:Offset 06h:bit 14) and

generate an internal SERR#.

• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is

set, the bridge will generate an internal SERR#

• When bad parity is detected from DMI, bad parity will be driven on all data the

bridge.

• When an address parity error is detected on PCI, the PCI bridge will not claim the

cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle

should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept

of address parity error, so claiming the cycle could result in the rest of the system

seeing a bad transaction as a good transaction.

5.1.4 PCIRST#

The PCIRST# pin is generated under two conditions:

•PLTRST# active

• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1

The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but

not other agents in the system.

Functional Description

102 Intel ® ICH7 Family Datasheet

5.1.5 Peer Cycles

The PCI bridge may be the initiator of peer cycles. Peer cy cles include memory, IO, and

configuration cycle types. Peer cycles are only allowed through VC0, and are enabled

with the following bits:

• BPC.PDE (D30:F0: Off s et 4C h: b i t 2) – Me mo ry and IO c y c l e s

• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles

When enabled for peer for one of the above cycle types, the PCI bridge will perform a

peer decode to see if a peer agent can receive the cycle. When not enabled, memory

cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles

are not claimed.

Configuration cycles hav e special considerations. Under the PCI Local Bus Specification,

these cycles are not allowed to be forwarded upstream through a bridge. However, to

enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are

allowed into the part. The address format of the type 1 cycle is slightly different from a

standard PCI configuration cy cle to allow addressing of extended PCI space. The format

is as follows:

Note: The ICH7’ s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.

5.1.6 PCI-to-PCI Bridge Model

From a software perspective, the ICH7 contains a PCI-to-PCI bridge. This bridge

connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH7

can have its decode ranges programmed by existing plug-and-play software such that

PCI ranges do not conflict with graphics aperture ranges in the Host controller.

Note: All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure

to do so may cause undefined results.

Table 5-2. Type 1 Address Format

Bits Definition

31:27 Reserved (same as th e PCI Local Bus Specification)

26:24 Extended Configuration Address – allows addressing of up to 4K. These

bits are combined with bits 7:2 to get the full register.

23:16 Bus Number (same as the PCI Local Bus Specification)

15:11 Device Number (same as the PCI Local Bus Spe cification)

10:8 Function Number (same as the PCI Local Bus Specification)

7:2 Register (same as the PCI Local Bus Specification)

0 Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.

Intel ® ICH7 Family Datasheet 103

Functional Description

5.1.7 IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the ICH7 asserts

one address signal as an IDSEL. When accessing device 0, the ICH7 asserts AD16.

When accessing Device 1, the ICH7 asserts AD17. This mapping continues all the way

up to device 15 where the ICH7 asserts AD31. Note that the ICH7’s internal functions

(AC ’97 on Desktop/Mobile, Intel High Definition Audio, IDE, USB, SATA on Desktop/

Mobile and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI)

from the external PCI bus. The integrated LAN controller (Desktop and Mobile Only) is

Device 8 on the ICH7’s PCI bus, and hence it uses AD24 for IDSEL.

5.1.8 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to

contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus

cycles to access the PCI configuration space: Configuration Read and Configuration

Write. Memory and I/O spaces are supported directly by the processor. Configuration

space is supported by a mapping mechanism implemented within the ICH7. The PCI

Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration

space, Mechanism 1 and Mechanism 2. The ICH7 only supports Mechanism 1.

Warning: Configuration writes to intern al devices, w hen the devices are disabled, are invalid and

may cause undefined results.

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)

(Desktop and Mobile Only)

There are four root ports available in ICH7, with select ICH7 components (ICH7R,

ICH7DH, and ICH7-M DH) having si x root p orts a dding port 5 and port 6 (see

Section 1.2). These all reside in device 28, and take function 0 – 5. P ort 1 is function 0,

port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and

port 6 is function 5.

Optionally, PCI Express ports 1-4 can be configured as a single one x4 port identified as

port 1. This is accomplished by placing external pull-up resistors on ACZ_SDOUT and

ACZ_SYNC. When these signals are sampled high on PWROK assertion, this will be

registered in the P ort Configuration field of the R oot P ort Configuration R egister and the

corresponding ports will be configured as one x4 port.

5.2.1 Interrupt Generation

The root port generates interrupts on behalf of Hot-Plug and power management

events, w hen enable d. T hese i nterrup ts can ei ther be pin based, or can be MSIs, when

enabled.

When an interrupt is generated via the legacy pin, the pin is internally routed to the

ICH7 interrupt controllers. The pin that is driven is based upon the setting of the

chipset configuration registers. Specifically, the chipset configuration registers used are

the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) register s.

Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”

refers to the Hot-Plug and PME interrupt bits.

Functional Description

104 Intel ® ICH7 Family Datasheet

5.2.2 Power Management

5.2.2.1 S3/S4/S5 Support

Software initiates the tran sitio n to S3/S4/S5 by performing an IO write to the Power

Management Control register in the ICH7. After the IO write completion has been

returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction

Layer Packet) message on it's downstream link. The device attached to the link will

eventually respond with a PME_TO_Ack TLP message followed by sending a

PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.

When all of the ICH7 root ports links are in the L2/L3 Ready state, the ICH7 power

management control logic will proceed with the entry into S3/S4/S5.

Prior to entering S3, software is requ ired to put each device into D3 HOT. When a device

is put into D3HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1

DLLP. Thus, under normal operating conditions when the root ports sends the

PME_Turn_Off message, the link will be in state L1. However, when the root port is

instructed to send the PME_Turn_Off message, it will send it whether or not the link

was in L1. Endpoints attached to the ICH7 can make no assumptions about th e state of

the link prior to receiving a PME_Turn_Off message.

5.2.2.2 Resuming from Suspended State

The root port contains enough circuitry in the resume well to detect a wake event thru

the WAKE# signal and to wake the system. When WAKE# is detected asserted, an

internal signal is sent to the power management controller of the ICH7 to cause the

system to wake up. This internal message is not logged in any register, nor is an

interrupt/GPE generated due to it.

5.2.2.3 Device Initiated PM_PME Message

When the system has returned to a working state from a previous low power state, a

device requesting service will send a PM_PME message continuously, until acknowledge

by the root port. The root port will take different actions depending upon whether this

is the first PM_PME has been received, or whether a previous message has been

received but not yet serviced by the operating system.

If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit

16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into

RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via

Table 5-3. MSI vs. PCI IRQ Actions

Interrupt Register Wire-

Mode Action MSI Action

All bits 0 Wire inacti ve No action

One or more bits set to 1 Wire active Send

message

One or more bits set to 1, new bit gets set to 1 Wire active Send

message

One or more bits set to 1, software clears some (but not all)

bits Wire active Send

message

One or more bits set to 1, software clears all bits Wire inactive No action

Software clears one or more bits, and one or more bits are

set on the same clock Wire active Send

message

Intel ® ICH7 Family Datasheet 105

Functional Description

RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated.

This interrupt can be either a pin or a MSI if MSI is enabled via MC.MSIE (D28:F0/F1/

F2/F3/F4/F5:Offset 82h:bit 0). See Section 5.2.2.4 for SMI/SCI generation.

If this is a subsequent message received (RSTS.PS is already set), the root port will set

RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID

from the message in a hidden register. No other action will be taken.

When the first PME event is cleared by softw are clearing RSTS.PS , the root port will set

RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into

RSTS.RID.

If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power

management controller so that a GPE can be set. If messages have been logged

(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be

generated. This last condition handles the case where the message was received prior

to the operating system re-enabling interrupts after resuming from a low power state.

5.2.2.4 SMI/SCI Generation

Interrupts for power management events are not supported on legacy operating

systems. To support power management on non-PCI Express aware oper ating systems,

PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.

When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/

F5:Offset DCh:bit 31) to be set.

Additionally, BIOS workarounds for power management can be supported by setting

MPC.PMME (D28:F0/F1/F2/F3/F4/F5:Offset D8h:bit 0). When this bit is set, power

management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 0),

and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI

is enabled. The SMI# may occur concurrently with an interrupt or SCI.

5.2.3 SERR# Generation

SERR# may be generated via two path s – through PCI mechanisms involving bits in the

PCI header, or through PCI Express mechanisms involving bits in the PCI Express

capability structure.

Figure 5-1. Generation of SERR# to Platform

PSTS.SSE

SERR#

PCICMD.SEE

Secondary Parity Error

Primary Parity Error

Secondary SERR#

Correctable SERR#

Fatal SERR#

Non-Fatal SERR#

PCI

PCI Express

Functional Description

106 Intel ® ICH7 Family Datasheet

5.2.4 Hot-Plug

Each root port implements a Hot-Plug controller which performs the following:

• Messages to turn on / off / blink LEDs

• Presence and attention button detection

• Interrupt generation

The root port only allows Hot-Plug with modules (e.g., ExpressCard*). Ed ge-connector

based Hot-Plug is not supported.

5.2.4.1 Presence Detection

When a module is plugged in and power is supplied, the physical layer will detect the

presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/

F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE

(D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F 1/F2/F3F4/

F5:Offset 58h:bit 5) are both set, the root port will also generate an interrupt.

When a module is removed (via the physical layer detection), the root port clears

SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root

port will also generate an interrupt.

5.2.4.2 Message Generation

When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits

7:6) or SLCTL.PIC (D28:F0/F1/F2/F3F4/F5:Offset 58h:bits 9:8), the root port will send

a message down the link to change the state of LEDs on the module.

Writes to these fields are non-postable cycles, and the resulting message is a postable

cycle. When receiving one of these writes, the root port performs the following:

• Changes the state in the register.

• Generates a completion into the upstream queue

• Formulates a message for the downstream port if the field is written to regardless

of if the field changed.

• Generates the message on the downstream port

• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/

F2/F3F4/F5:Offset 58h:bit 4) to indicate the command has completed. If

SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 5) are set, the

root port generates an interrupt.

The command completed register (SLSTS.CC) applies only to commands issued by

software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),

or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control

Hence, any write to the Slot Control Register is considered a command and if enabled,

will result in a command complete interrupt. The only exception to this rule is a write to

disable the command complete interrupt which will not result in a command complete

interrupt.

A single write to the Slot Control register is considered to be a single command, and

hence receives a single command complete, even if the write affects more than one

field in the Slot Control Register.

Intel ® ICH7 Family Datasheet 107

Functional Description

5.2.4.3 Attention Button Detection

When an attached device is ejected, an attention button could be pressed by the user.

This attention button press will result in a the PCI Express message

“Attention_Button_Pressed” from the device. Upon receiving this message, the root

port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0).

If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/

F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an

interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is

already set, a new interrupt will not be generated.

5.2.4.4 SMI/SCI Generation

Interrupts for Hot-Plug events are not supported on legacy operating systems. To

support Hot -Plug on non-PCI Express aware oper ating systems, Hot-Plug ev ents can be

routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset

D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS

(D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set.

Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME

(D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can

cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their

corresponding SMSCS bit are:

• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3)

• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

• Attention Button Pressed - SMSCS.HP ABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit

When any of these bits are set, SMI # will be generated. These bits are set regardless

of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur

concurrently with an interrupt or SCI.

Functional Description

108 Intel ® ICH7 Family Datasheet

5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile

Only)

The ICH7’s integrated LAN controller includes a 32-bit PCI controller that provides

enhanced scatter-gather bus mastering capabilities and enables the LAN controller to

perform high-speed data transfers over the PCI bus. Its bus master capabilities enable

the component to process high level commands and perform multiple operations; this

lowers processor utilization by off-loading communication tasks from the processor.

Two large transmit and receive FIFOs of 3 KB each, help prevent data underruns and

overruns while waiting for bus accesses. This enables the integrated LAN controller to

transmit data with minimum interframe spacing (IFS).

The ICH7 integrated LAN controller can operate in either full-duplex or half-duplex

mode. In full- duplex mode the LAN controller adheres with the IEEE 802.3x Flow

Control Specification. Half duplex performance is enhanced by a proprietary collision

reduction mechanism.

The integrated LAN controller also includes an interface to a serial (4-pin ) EEPROM. The

EEPROM provides power-on initialization for hardware and software configuration

parameters.

From a software perspective, the integrated LAN controller appears to reside on the

secondary side of the ICH7’s virtual PCI-to-PCI bridge (see Section 5.1.6). This is

typically Bus 1, but may be assigned a different number, depending upon system

configuration.

The following summarizes the ICH7 LAN controller features:

• Compliance with Advanced Configuration and Power Interface and PCI Power

Management standards

• Support for wake-up on interesting packets and link status change

• Support for remote power-up using Wake on LAN* (WOL) technology

• Deep power-down mode support

• Backward compatible software with 82550, 82557, 82558 a nd 82559

• TCP/UDP checksum off load capabilities

• Support for Intel’s Adaptive Technology

5.3.1 LAN Controller PCI Bus Interface

As a Fast Ethernet controller, the role of the ICH7 integr ated LAN controller is to access

transmitted data or deposit received data. The LAN controller, as a bus master device,

initiates memory cycles via the PCI bus to fetch or deposit the required data.

To perform these actions, the LAN controller is controlled and examined by the

processor via its control and status structures and registers. Some of these control and

status structures reside in the LAN controller and some reside in system memory. For

access to the LAN controller’s Control/Status Registers (CSR), the LAN controller acts

as a slave (in other words, a target device). The LAN controller serves as a slave also

while the processor accesses the EEPROM.

Intel ® ICH7 Family Datasheet 109

Functional Description

5.3.1.1 Bus Slave Operation

The ICH7 integrated LAN controller serves as a target device in one of the following

cases:

• Processor accesses to the LAN controller System Control Block (SCB) Control/

Status Registers (CSR)

• Processor accesses to the EEPROM through its CSR

• Processor accesses to the LAN controller PORT address via the CSR

• Processor accesses to the MDI control register in the CSR

The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the

I/O space. The LAN controller treats accesses to these memory spaces differently.

Control/Status Register (CSR) Accesses

The integrated LAN controller supports zero wait-state single cycle memory or I/O

mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and

64 bytes of I/O space to accomplish this. Based on its needs, the software driver uses

either memory or I/O mapping to access these registers. The LAN controller provides

four valid KB of CSR space that include the following elements:

• System Control Block (SCB) registers

•PORT register

• EEPROM control register

• MDI control register

• Flow control registers

In the case of accessing the Control/Status Registers, the processor is the initiator and

the LAN controller is the target.

Retry Premature Accesses

The LAN controller responds with a Retry to any configuration cycle accessing the LAN

controller before the completion of the automatic read of the EEPROM. The LAN

controller may continue to R etry any configuration accesses until the EEPROM read is

complete. The LAN controller does not enforce the rule that the retried master must

attempt to access the same address again in order to complete any delayed

transaction. Any master access to the LAN controller after the completion of the

EEPROM read is honored.

Error Handling

Data Parity Errors: The LAN controller checks for data parity errors while it is the

target of the transaction. If an error was detected, the LAN controller sets the Detected

Parity Error bit in the PCI Configuration Status register, bit 15. The LAN controller also

asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command

parity error was detected. This gives the initiator the option of recovery.

Target-Disconnect: The LAN controller prematurely terminate a cycle in the following

cases:

• After accesses to its CSR

• After accesses to the configuration space

Functional Description

110 Intel ® ICH7 Family Datasheet

System Error: The LAN controller reports parity error during the address phase using

the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or

the Parity Error Response bit are not set, the LAN controller only sets the Detected

Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity

Error R esponse bits are both set, the LAN controller sets the Signaled System Error bit

(PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and

asserts SERR# for one clock.

The LAN controller, when detecting system error, claims the cycle if it was the target of

the transaction and continues the transaction as if the address was correct.

Note: The LAN controller reports a system error for any error during an address phase,

whether or not it is involved in the current transaction.

5.3.1.2 CLKRUN# Signal (Mobile Only)

The Intel® ICH7 receives a free-running 33 MHz clock. It does not stop based on the

CLKRUN# signal and protocol. When the LAN controller runs cycles on the PCI bus, the

ICH7 makes sure that the STP_PCI# signal is high indicating that the PCI clock will be

running. This is to make sure that any PCI tracker does not get confused by

transactions on the PCI bus with its PCI clock stopped.

5.3.1.3 PCI Power Management

Enhanced support for the power management standard, PCI Local Bus Specification,

Revision 2.3, is provided in the ICH7 integrated LAN controller. The LAN controller

supports a large set of wake-up packets and the capability to wake the system from a

low power state on a link status change. The LAN controller enables the host system to

be in a sleep state and remain virtually connected to the network.

After a power management event or link status change is detected, the LAN controller

wakes the host system. The following sections describe these events, the LAN

controller power states, and estimated power consumption at each power state.

The LAN controller contains power management registers for PCI, and implements four

power states, D0 through D3, which vary from maximum power consumption at D0 to

the minimum power consumption at D3. PCI transactions are only allowed in the D0

state, except for host accesses to the LAN controller’s PCI configuration registers. The

D1 and D2 power management states enable intermediate power savings while

providing the system wake-up capabilities. In the D3COLD state, the LAN controller can

provide wake-up capabilities. W ak e-up indications from the LAN controller are provided

by the Power Management Event (PME#) signal.

5.3.1.4 PCI Reset Signal

The PCIRST# signal may be activated in one of the following cases:

• During S3–S 5 s t ates

• Due to a CF9h reset

If PME is enabled (in the PCI power management registers), PCIRST# assertion does

not affect any PME related circuits (in other words, PCI power management registers

and the wake-up packet would not be affected). While PCIRST# is active, the LAN

controller ignores other PCI signals. The configuration of the LAN controller registers

associated with ACPI wake events is not affected by PCIRST#.

The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication

to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller

PCI Configur ation Space, MAC configuration, and memory structure are initialized while

preserving the PME# signal and its context.

Intel ® ICH7 Family Datasheet 111

Functional Description

5.3.1.5 Wake-Up Events

There are two types of wake-up events: “Interesting” Pa ckets and Link Status Change.

These two events are detailed below.

Note: If the Wake on LAN bit in the EEPROM is not set, wak e-up events are supported only if

the PME Enable bit in the Power Management Control/Status Register (PMCSR) is set.

However, if the Wake on LAN bit in the EEPROM is set, and Wake on Magic Packet* or

Wake on Link Status Change are enabled, the Pow er Management Enable bit is ignored

with respect to these events. In the latter case, PME# would be asserted by these

events.

“Interesting” Packet Event

In the power-down state, the LAN controller is capable of recognizing “interesting”

packets. The LAN controller supports predefined and programmable packets that can

be defined as any of the following:

• ARP Packets (with Multiple IP addresses)

• Direct Packets (with or without type qualification)

•Magic Packet

• Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)

• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)

• Internetwork Package Exchange* (IPX) Diagnostic Packet

This allows the LAN controller to handle various packet types. In general, the LAN

controller supports programmable filtering of any packet in the first 128 bytes.

When the LAN controller is in one of the low power states, it searches for a predefined

pattern in the first 128 bytes of the incoming packets. The only exception is the Magic

Packet, which is scanned for the entire frame. The LAN controller classifies the

incoming packets as one of the following categories:

•No Match: The LAN controller discards the packet and continues to process the

incoming packets.

•TCO Packet: The LAN controller implements perfect filtering of TCO packets. After

a TCO packet is processed, the LAN controller is ready for the next incoming

packet. TCO packets are treated as any other wake-up packet and may assert the

PME# signal if configured to do so.

•Wake-up Packet: The LAN controller is capable of recognizing and storing the first

128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its

tail is discarded by the LAN controller. After the system is fully powered-up,

software has the abilit y to determine the cause of the w ake-up ev ent via the PMDR

and dump the stored data to the host memory.

Magic Packets are an exception. The Magic Packets may cause a power

management event and set an indication bit in the PMDR; however, it is not stored

by the LAN controller for use by the system when it is woken up.

Link Status Change Event

The LAN controller link status indication circuit is capable of issuing a PME on a link

status change from a valid link to an invalid link condition or vice versa. The LAN

controller reports a PME link status ev ent in all power states. If the Wake on LAN bit in

the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR

and the CSMA Configure command.

Functional Description

112 Intel ® ICH7 Family Datasheet

5.3.1.6 Wake on LAN* (Preboot Wake-Up)

The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the

EEPROM is set. At this point, the LAN controller is in the D0u state. When the LAN

controller is in Wake on LAN mode:

• The LAN controller scans incoming packets for a Magic Packet and asserts the

PME# signal for 52 ms when a 1 is detected in Wake on LAN mode.

• The Activity LED changes its functionality to indicates that the received frame

passed Individual Address (IA) filtering or broadcast filtering.

• The PCI Configuration registers are accessible to the host.

The LAN controller switches from Wake on LAN mode to the D0a power state following

a setup of the Memory or I/O Base Address Registers in the PCI configuration space.

5.3.2 Serial EEPROM Interface

The serial EEPROM stores configur ation data for the ICH7 integr ated LAN controller and

is a serial in/serial out device. The LAN controller supports a 64-register or 256-register

size EEPROM and automatically detects the EEPROM’s siz e. The EEPROM should operate

at a frequency of at least 1 MHz.

All accesses, either read or write, are preceded by a command instruction to the

device. The address field is six bits for a 64-register EEPR OM or eight bits for a 256-

EEPROM that indicates the entire address field has been transferred to the device. An

EEPROM read instruction waveform is shown in Figure 5-2.

The LAN controller performs an automatic read of seven words (0h, 1h , 2h, Ah, Bh, Ch,

and Dh) of the EEPROM after the deassertion of Reset.

Figure 5-2. 64-Word EEPROM Read Instruction Waveform

EE_CS

EE_SHCLKK

EE_DIN

EE_DOUT

READ OP code

Intel ® ICH7 Family Datasheet 113

Functional Description

5.3.3 CSMA/CD Unit

The ICH7 integrated LAN controller CSMA/CD unit implements both the IEEE 802.3

Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all

the CSMA/CD protocol functions (e.g. , tr ansmission, reception, collision handling, etc.).

The LAN controller CSMA/CD unit interfaces to the 82562ET/EM/EZ/EX 10/100 Mbps

Ethernet through the ICH7’s LAN Connect interface signals.

5.3.3.1 Full Duplex

When operating in full-duplex mode, the LAN controller can transmit and receive

frames simultaneously. Transmission starts regardless of the state of the internal

receive path. Reception starts when the platform LAN Connect component detects a

valid frame on its receive differential pair. The ICH7 integrated LAN controller also

supports the IEEE 802.3x flow control standard, when in full-duplex mode.

The LAN controller operates in either half -duplex mode or full-duplex mode. For proper

operation, both the LAN controller CSMA/CD module and the discrete platform LAN

Connect component must be set to the same duplex mode. The CSMA duplex mode is

set by the LAN Controller Configure command or forced by automatically tracking the

mode in the platform LAN Connect component. Following reset, the CSMA defaults to

automatically track the platform LAN Connect component duplex mode.

The selection of duplex operation (full or half) and flow control is done in two levels:

MAC and LAN Connect.

5.3.3.2 Flow Control

The LAN controller supports IEEE 802.3x frame-based flow control frames only in both

full duplex and half duplex switched environments. The LAN controller flow control

feature is not intended to be used in shared media environments.

Flow control is optional in full-duplex mode and is selected through software

configuration. There are three modes of flow control that can be selected: frame-based

transmit flow control, frame-based receive flow control, and none.

5.3.3.3 VLAN Support

The LAN controller supports the IEEE 802.1 standard VLAN. All VLAN flows will be

implemented by software. The LAN controller supports the reception of long frames,

specifically frames longer than 1518 bytes, including the CRC, if software sets the Long

Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded.

5.3.4 Media Management Interface

The management interface allows the processor to control the platform LAN Connect

component via a control register in the ICH7 integrated LAN controller. This allows the

software driver to place the platform LAN Connect in specific modes (e.g., full duplex,

loopback, power down, etc.) without the need for specific hardware pins to select the

desired mode. This structure allows the LAN controller to query the platform LAN

Connect component for status of the link. This register is the MDI Control Register and

resides at offset 10h in the LAN controller CSR. The MDI registers reside within the

platform LAN Connect component, and are described in detail in the platform LAN

Connect component’s datasheet. The processor writes commands to this register and

the LAN controller reads or writes the control/status parameters to the platform LAN

Connect component through the MDI register.

Functional Description

114 Intel ® ICH7 Family Datasheet

5.3.5 TCO Functionality

The ICH7 integrated LAN controller supports management communication to reduce

Total Cost of Ownership (TCO). The SMBus is used as an interface between the ASF

controller and the integrated TCO host controller. There are two differen t types of TCO

operation that are supported (only one supported at a time), they are 1) Integrated

ASF Control or 2) external TCO controller support. The SMLink is a dedicated bus

between the LAN controller and the integrated ASF controller (if enabled) or an external

management controller. An EEPROM of 256 words is required to support the heartbeat

command.

5.3.5.1 Advanced TCO Mode

The Advanced TCO functionalities through the SMLink are listed in Table 5-4.

Note: For a complete description on various commands, see the Total Cost of Ownership

(TCO) System Management Bus Interface Application Note (AP-430).

Transmit Command during Normal Operation

To serve a transmit request from the TCO controller, the ICH7 LAN controller first

completes the current transmit DMA, sets the TCO request bit in the PMDR register (see

Section 8.2), and then responds to the TCO controller’s tr ansmit request. F ollowing the

completion of the TCO transmit DMA, the LAN controller increments the Transmit TCO

statistic counter (described in Section 8.2.14). Following the completion of the tr ansmit

operation, the ICH7 increments the nominal tr ansmit statistic counters, clears the TCO

request bit in the PMDR register, and resumes its normal transmit flow . The receive flow

is not affected during this entire period of time.

Receive TCO

The ICH7 LAN controller supports receive flow towards the TCO controller. The ICH7

can transfer only TCO packets, or all packets that passed MAC address filtering

according to its configuration and mode of operation as detailed below. While

configured to transfer only TCO packets, it supports Ethernet type II packets with

optional VLAN tagging.

Force TCO Mode: While the ICH7 is in the force TCO mode, it may receive packets

(TCO or all) directly from the T CO controller. Receiving TCO packets and filtering lev el is

controlled by the set Receive enable command from the TCO controller. Following a

reception of a TCO packet, the ICH7 increments its nominal Receive statistic counters

as well as the Receive TCO counter.

Table 5-4. Advanced TCO Functionality

Power State TCO Controller Functionality

D0 nominal

Transmit

Set Receive TCO Packets

Receive TCO Packets

Re ad Intel® ICH7 status (PM & Link state)

Force TCO Mode

Dx (x>0) D0 functionality plus:

Read PHY registers

Force TCO Mode Dx functionality plus:

Configuration commands

Read/Write PHY registers

Intel ® ICH7 Family Datasheet 115

Functional Description

Dx>0 Power State: While the ICH7 is in a powerdown state, it may receive TCO

packets or all directly to the T CO controller. Receiving T CO packets is enabled by the set

Receive enable command from the TCO controller. Although TCO packet might match

one of the other wake up filters, once it is transferred to the TCO controller, no further

matching is searched for and PME is not issued. While receive to TCO is not enabled, a

TCO packet ma y cause a PME if configured to do so (settin g T C O to 1 in the filter t ype).

D0 Power State: At D0 power state, the ICH7 may transfer TCO packets to the TCO

controller. At this state, TCO packets are posted first to the host memory, then read by

the ICH7, and then posted back to the TCO controller. After the packet is posted to

TCO, the receive memory structure (that is occupied by the TCO packet) is reclaimed.

Other than providing the necessary receive resources, there is no required device

driver intervention with this process. Eventually, the ICH7 increments the receive TCO

static counter, clears the TCO request bit, and resumes normal control.

Read Intel® ICH7 Status (PM and Link State)

The TCO controller is capable of reading the ICH7 power state and link status. F ollowing

a status change, the ICH7 asserts LINKALERT# and then the TCO can read its new

power state.

Set Force TCO Mode

The TCO controller put the ICH7 into the Force TCO mode. The ICH7 is set back to the

nominal operation following a PCIRST#. F o llowing the tr ansition fr om nominal mode to

a TCO mode, the ICH7 aborts transmission and reception and loses its memory

structures. The TCO may configure the ICH7 before it starts tran smission and reception

if required.

Warning: The Force TCO is a destructive command. It causes the ICH7 to lose its memory

structures, and during the Force TCO mode the ICH7 ignores any PCI accesses.

Therefore, it is highly recommended to use this command by the TCO controller at

system emergency only.

5.4 Alert Standard Format (ASF) (Desktop and Mobile

Only)

The ASF controller collects information from various components in the system

(including the processor, chipset, BIOS, and sensors on the motherboard) and sends

this information via the LAN controller to a remote server running a management

console. The controller also accepts commands back from the management console

and drives the execution of those commands on the local system.

The ASF controller is responsible for monitoring sensor devices and sending packets

through the LAN controller SMBus (System Management Bus) interface. These ASF

controller alerting capabilities include system health information such as BIOS

messages, POST alerts, operating system failure notifications, and heartbeat signals to

indicate the system is accessible to the server. Also included are environmental

notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that

something is wrong with the hardware. The pack ets are used as Alert (S .O.S.) packets

or as “heartbeat” status packets. In addition, asset security is provided by messages

(e.g., “cover tamper” and “CPU missing”) that notify of potential system break-ins and

processor or memory theft.

The ASF controller is also responsible for receiving and responding to RMCP (Remote

Management and Control Protocol) packets. RMCP packets are used to perform various

system APM commands (e.g., reset, power-up, power-cycle, and power-down). RMCP

can also be used to ping the system to ensure that it is on the network and running

Functional Description

116 Intel ® ICH7 Family Datasheet

correctly and for capability reporting. A major advantage of ASF is that it provides

these services during the time that software is unable to do so (e.g., during a low-

power state, during boot-up, or during an operating system hang) but are not

precluded from running in the working state.

The ASF controller communicates to the system and the LAN controller logic through

the SMBus connections. The first SMBus connects to the host SMBus controller (within

the ICH7) and any SMBus platform sensors. The SMBus host is accessible by the

system software, including software running on the operating system and the BIOS.

Note that the host side bus may require isolation if there are non- auxiliary devices that

can pull down the bus when un-powered. The second SMBus connects to the LAN

controller. This second SMBus is used to provide a transmit/receive network interface.

The stimulus for causing the ASF controller to send packets can be either internal or

external to the ASF controller. External stimuli are link status changes or polling data

from SMBus sensor devices; internal events come from, among others, a set of timers

or an event caused by software.

The ASF controller provides three local configuration protocols via the host SMBus. The

first one is the SMBus ARP interface that is used to identify the SMBus device and allow

dynamic SMBus address assignment. The second protocol is the ASF controller

command set that allows software to manage an ASF controller compliant interface for

retrieving info, sending alerts, and controlling timers.

ICH7 provides an input and an output EEPROM interface. The EEPROM contains the LAN

controller configuration and the ASF controller configuration/packet information.

5.4.1 ASF Management Solution Features/Capabilities

• Alerting

— Transmit SOS packets from S0–S5 states

— System Health Heartbeats

— SOS Hardware Events

- System Boot Failure (Watchdog Expires on boot)

- LAN Link Loss

- Entity Presence (on ASF power-up)

- SMBus Hung

- Maximum of eight Legacy Sensors

- Maximum of 128 ASF Sensor events

— Watchdog Ti mer for operating system lockup/System Hang/Failure to Boot

— General Push support for BIOS (POST messages)

• Remote Control

— Presence Ping Response

— Configurable Boot Options

— Capabilities Reporting

— Auto-ARP Support

— System Remote Control

- Power-Down

- Power-Up

- Power Cycle

- System Reset

— State-Based Security – Conditional Action on WatchDog Expire

Intel ® ICH7 Family Datasheet 117

Functional Description

• ASF Compliance

— Compliant with the Alert Standard Format (ASF) Specification, Versi on 1.03

- PET Compliant Packets

- RMCP

- Legacy Sensor Polling

- ASF Sensor Polling

- Remote Control Sensor Support

• Advanced Features / Miscellaneous

—SMBus 2.0 compliant

— Optional reset extension logic (for use with a power-on reset)

5.4.2 ASF Hardware Support

ASF requires additional hardware to make a complete solution.

Note: If an ASF compatible device is externally connected and properly configured, the

internal ICH7 ASF controller will be disabled. The external ASF device will have access

to the SMBus controller.

5.4.2.1 Intel® 82562EM/EX

The 82562EM/EX Ethernet LAN controller is necessary. This LAN controller provides the

means of transmitting and receiving data on the network, as well as adding the

Ethernet CRC to the data from the ASF.

5.4.2.2 EEPROM (256 x16, 1 MHz)

To support the ICH7 ASF solution, a larger, 256x16 1 MHz, EEPROM is necessary to

configure defaults on reset and on hard power losses (software un-initiated). The ASF

controller shares this EEPROM with the LAN controller and provides a pass through

interface to achieve this. The ASF controller expects to have exclusiv e access to words

40h through F7h. The LAN controller can use the other EEPROM words. The ASF

controller will default to safe defaults if the EEPROM is not present or not configured

properly (both cause an invalid CRC).

5.4.2.3 Legacy Sensor SMBus Devices

The ASF controller is capable of monitoring up to eight sensor devices on the main

SMBus. These sensors are expected to be compliant with the Legacy Sensor

Characteristics defined in the Alert Standard Format (ASF) Specification, Version 1.03.

5.4.2.4 Remote Control SMBus Devices

The ASF controller is capable of causing remote control actions to Remote Control

devices via SMBus. These remote control actions include Power-Up, Power-Down,

P ower-Cycle, and R eset. The ASF controller supports devices that conform to the Alert

Standard Format (ASF) Specification, Version 1.03, Re mo te Control Devices.

5.4.2.5 ASF Sensor SMBus Devices

The ASF controller is capable of monitoring up to 128 ASF sensor devices on the main

SMBus. However, ASF is restricted by the number of total events which may reduce the

number of SMBus devices supported. The maximum number of events supported by

ASF is 128. The ASF sensors are expected to operate as defined in the Alert Standard

Format (ASF) Specification, Version 1.03.

Functional Description

118 Intel ® ICH7 Family Datasheet

5.4.3 ASF Software Support

ASF requires software support to make a complete solution. The following software is

used as part of the complete solution.

• ASF Configuration driver / application

•Network Driver

• BIOS Support for SMBIOS, SMBus ARP, ACPI

• Sensor Configuration driver / application

Note: Contact your Intel Field Representative for the Client ASF Software Development Kit

(SDK) that includes additional documentation and a copy of the client ASF software

drivers. Intel also provides an ASF Console SDK to add ASF support to a management

console.

5.5 LPC Bridge (w/ System and Management

Functions) (D31:F0)

Note: LPC DMA is not supported on the Ultra Mobile component (ICH7-U).

The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. In addition to

the LPC bridge function, D31:F0 contains other functional units including DMA (Desktop

and Mobile only), Interrupt controllers, Timers, Power Management, System

Management, GPIO, and RTC. In this chapter, registers and functions associated with

other functional units (power management, GPIO, USB, IDE, etc.) are described in their

respective sections.

5.5.1 LPC Interface

The ICH7 implements an LPC interface as described in the Low Pin Count Interface

Specification, Revision 1.1. The LPC interface to the ICH7 is shown in Figure 5-3. Note

that the ICH7 implements all of the signals that are shown as optional, but peripherals

are not required to do so.

Figure 5-3. LPC Interface Diagram

Intel

ICH7

SUS_STAT#

GPI

LPC Device

PCI

CLK PCI

RST# PCI

SERIRQPCI

PME#

LAD [3 :0 ]

LDRQ#

(optional)

LFRAME#

LPCPD#

(optional)

LSMI#

(optional)

PCI Bus

Intel ® ICH7 Family Datasheet 119

Functional Description

5.5.1.1 LPC Cycle Types

The ICH7 implements the following cycle types as described in Table 5-5

NOTES:

1. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer

can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an

address where A0=0). A dword transfer must be dword-aligned (i.e., with an address

where A1 and A0 are both 0)

5.5.1.2 Start Field Definition

NOTE: All other encodings are RESERVED.

Table 5-5. LPC Cycle Types Supported

Cycle Type Comment

I/O Read 1 byte only. Intel® ICH7 breaks up 16- and 32-bit processor cycles into

multiple 8-bit transfers.

I/O Write 1 byte only. ICH7 breaks up 16- and 32-bit proc essor c ycles into mul tiple

8-bit transfers.

DMA Read

(Desktop and

Mobile Only) Can be 1, or 2 bytes

DMA Write

(Desktop and

Mobile Only) Can be 1, or 2 bytes

Bus Master Read Can be 1, 2, or 4 bytes. (See Note 1 below)

Bus Master Write Can be 1, 2, or 4 bytes. (See Note 1 below)

Table 5-6. Start Field Bit Definitions

Bits[3:0]

Encoding Definition

0000 Start of cycle for a generic target

0010 Grant for bus master 0

0011 Grant for bus master 1

1111 Stop/Abort: End of a cycle for a

target.

Functional Description

120 Intel ® ICH7 Family Datasheet

5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)

The ICH7 drives bit 0 of th is field to 0. P eripher als running bus master cycles m ust also

drive bit 0 to 0. Table 5-7 shows the valid bit encodings.

NOTE: All other encodings are RESERVED.

5.5.1.4 SIZE

Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master

cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits.

Bits[1:0] are encoded as listed in Table 5-8.

Table 5-7. Cycle Type Bit Definitions

Bits[3:2] Bit1 Definition

00 0 I/O Read

00 1 I/O Write

10 0 Desktop and Mobile: DMA Read

Ultr a Mobi le : Reserved

10 1 Desktop and Mobile: DMA Write

Ultr a Mobi le : Reserved

11 x Reserved. If a peripheral performing a bus master cycle generates this

value, the Intel® ICH7 aborts the cy c le.

Table 5-8. Transfer Size Bit Definit ion

Bits[1:0] Size

00 8-bit transfer (1 byte)

01 16-bit transfer (2 bytes)

10 Reserved. The Intel® ICH7 does not drive this combination. If a peripheral

running a bus maste r cycle drives this combination, the ICH7 may abort the

transfer.

11 32-bit transfer (4 bytes)

Intel ® ICH7 Family Datasheet 121

Functional Description

5.5.1.5 SYNC

Valid values for the SYNC field are shown in Table 5-9.

NOTES:

1. All other combinations are RESERVED.

2. If the LPC controll er re ceives any SYNC re turned from the device other than short (0101),

long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may

occur. A FWH device is not allowed to assert an Error SYNC.

5.5.1.6 SYNC Time-Out

There are several error cases that can occur on the LPC interface. The ICH7 responds

as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revisi on 1. 1

to the stimuli described therein. There may be other peripheral failure conditions;

however, these are not handled by the ICH7.

5.5.1.7 SYNC Error Indication

The ICH7 responds as defined in section 4.2.1.10 of the Low Pin Count Interface

Specification, Revision 1.1.

Upon recognizing the SYNC field indicating an error, the ICH7 treats this as an SERR by

reporting this into the Device 31 Error Reporting Logic.

Table 5-9. SYNC Bit Definition

Bits[3:0]1,2 Indication

0000 Ready: SYNC achieved with no error. For DMA transfers on desktop and mobile

components, this also indicates DMA request deassertion and no more transfers

desired for that channel.

0101 Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH7

does not use this encoding. Instead, the ICH7 uses the Long Wait encoding (see

next encoding below).

0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This

encoding driven by the ICH7 for bus mast er cycles, rather than the Short Wait

(0101).

1001

Ready More (Used only by peripheral for DMA cy cl e): SYNC achieved with

no error and more DMA transfers desired to continue after this transfer. This

value is valid only on DMA transfers and is not allowed for any other type of

cycle.

Ultra Mobile: Reserved

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or

IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be tr ansferred,

but there is a serious error in this transfer. For DMA transfers on desktop and

mobile comp onents, this not only indicates an error, but also indi cates DMA

request deassertion and no more transfers desired for that channel.

Functional Description

122 Intel ® ICH7 Family Datasheet

5.5.1.8 LFRAME# Usage

The ICH7 follows the usage of LFRAME# as defined in the Low Pin Count Interface

Specification, Revision 1.1.

The ICH7 performs an abort for the following cases (possible failure cases):

• ICH7 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after

four consecutive clocks.

• ICH7 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC

pattern.

• A peripheral drives an invalid address when performing bus master cycles.

• A peripheral drives an invalid value.

5.5.1.9 I/O Cycles

For I/O cycles targeting registers specified in the ICH7’s decode ranges, the ICH7

performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision

1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit tr ansfer, the

ICH7 breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH7

returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with

ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.

5.5.1.10 Bus Master Cycles

The ICH7 supports Bus Master cycles and requests (using LDRQ#) as defined in the

Low Pin Count Interface Specific ation, Revision 1.1. The ICH7 has two LDRQ# inputs,

and thus supports two separate bus master devices. It uses the associated ST ART fields

for Bus Master 0 (0010b) or Bus Master 1 (0011b).

Note: The ICH7 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters

should only perform memory read or memory write cycles.

5.5.1.11 LPC Power Management

CLKRUN# Protocol (Mobile/Ultra Mobile Only)

The CLKRUN# protocol is same as in the PCI Local Bus Specification. Stopping the PCI

clock stops the LPC clock.

LPCPD# Protocol

Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive

LDRQ# low or tri-state it. ICH7 shuts off the LD RQ# inpu t buffers. After driving

SUS_STAT# active, the ICH7 drives LFRAME# low, and tri-states (or drive low)

LAD[3:0].

Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol

where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This

specification explicitly states that this protocol only applies to entry/exit of low power

states which does not include asynchronous reset events. The ICH7 asserts both

SUS_ST A T# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time

when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not

inconsistent with the LPC LPCPD# pr otocol.

Intel ® ICH7 Family Datasheet 123

Functional Description

5.5.1.12 Configuration and Intel® ICH7 Implications

LPC Interface Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH7

includes several decoders. During configuration, the ICH7 must be programmed with

the same decode ranges as the peripheral. The decoders are programmed via the

Device 31:Function 0 configuration space.

Note: The ICH7 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with

similar characteristics (specifically those with a “Retry Read” feature which is enabled)

to an LPC device if there is an outstanding LPC read cycle towards the same PCI device

or bridge. These cycles are not part of normal system operation, but may be

encountered as part of platform validation testing using custom test fixtures.

Bus Master Device Mapping and START Fields

Bus Masters must have a un ique ST AR T field. In th e case of the ICH7 that supports two

LPC bus masters, it drives 0010 for the START field for grants to bus master #0

(requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via

LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular

bus master.

5.5.2 SERR# Generation

Several internal and external sources of the LPC Bridge can cause SERR#, as described

below.

The first class of errors is parity errors related to the backbone. The LPC Bridge

captures generic data parity errors (errors it finds on the backbone) as well as errors

returned on the backbone cycles where the bridge was the master and parity error

response is enabled. If either of these two conditions is met, and with SERR# enable

(PCICMD.SERR_EN) set, SERR# will be captured.

Additionally, if the LPC Bridge receives an error SYNC on LPC bus, an SERR# will also

be generated.

Figure 5-4. LPC Bridge SERR# Generation

SERR#

PCICMD.SERR_EN

(D31:F0: 04h, bi t 8)

PCISTS.DPE

(D31:F0:06h, bit15)

PCISTS.DPED

(D31:F0:06h, bit 8)

PCISTS.SSE

(D31:F0:06h, bit 14)

LPC Error Sync

Received

Functional Description

124 Intel ® ICH7 Family Datasheet

5.6 DMA Operation (D31:F0)

Note: For ICH7-U Ultra Mobile, LPC DMA is not supported.

The ICH7 supports LPC DMA using the ICH7’s DMA controller. The DMA controller has

registers that are fixed in the lower 64 KB of I/O space. The DMA controller is

configured using registers in the PCI configuration space. Th ese registers allow

configuration of the channels for use by LPC DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with

seven independently programmable channels (Figure 5-5). DMA controller 1 (DMA-1)

corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to

channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to

cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for

any other purpose. In addition to accepting requests from DMA slaves, the DMA

controller also responds to requests that software initiates. Software may initiate a

DMA service request by setting any bit in the DMA Channel Request Register to a 1.

Each DMA channel is hardwired to the compatible settings for DMA device size:

channels [3:0] are hardwired to 8-bit, count-by -bytes transfers, and channels [7:5] are

hardwired to 16-bit, count-by-words (address shifted) transfers.

ICH7 provides 24-bit addressing in compliance with the ISA-Compatible specification.

Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16

least-significant bits of the 24-bit address, an ISA-Compatible Page Register which

contains the eight next most significant bits of address.

The DMA controller also features refresh address generation, and autoinitialization

following a DMA termination.

5.6.1 Channel Priority

For priority resolution, the DMA consists of two logical channel groups: channels 0–3

and channels 4–7. Each group may be in either fixed or rotate mode, as determined by

the DMA Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,

a software request for DMA service can be presented through each channel's DMA

Request Register. A software request is subject to the same prioritization as any

hardware request. See the detailed register description for Request Register

programming information in Section 10.2.

Figure 5-5. Intel® ICH7 DMA Controller

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

DMA-1 DMA-2

Intel ® ICH7 Family Datasheet 125

Functional Description

5.6.1.1 Fixed Priority

The initial fixed priority structure is as follows:

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the

highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume

the priority position of channel 4 in DMA-2, t hus taking priority ov er channels 5, 6, and

5.6.1.2 Rotating Priority

R otation allows for “fairness” in priority resolution. The priority chain rotates so that the

last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).

Channels 0–3 rotate as a group of 4. They are placed between channel 5 and channel 7

in the priority list.

Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three

positions in the rotation, while channel group (0–3) comprises the fourth position in the

arbitration.

5.6.2 Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the

High and Low P age Registers. Therefore, if a 24-bit address is 01FFFFh and increments,

the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h

and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is

operating in 16-bit mode, the addresses still do not increment or decrement through

the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a

24-bit address is 01FFFEh and increments, the next address is 000000h, not

0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address

is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register

implementation used in the PC-AT. This mode is set after CPURST is valid.

5.6.3 Summary of DMA Transfer Sizes

Table 5-10 lists each of the DMA device transfer sizes. The column labeled “Current

Byte/Word Count Register” indicates that the register contents represents either the

number of bytes to transfer or the number of 16-bit words to transfer. The column

labeled “Current Address Increment/Decrement” indicates the number added to or

taken from the Current Address register after each DMA transfer cycle. The DMA

Channel Mode Register determines if the Current Address Register will be incremented

or decremented.

High priority Low priority

0, 1, 2, 3 5, 6, 7

Functional Description

126 Intel ® ICH7 Family Datasheet

5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words

The ICH7 maintains compatibility with the implementation of the DMA in the PC A T that

used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device

count-by-words.

Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.

When programming the Current Address Register (when the DMA channel is in this

mode), the Current Address must be programmed to an even address with the address

value shifted right by one bit.

The address shifting is shown in Table 5-11.

NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.6.4 Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as

an autoinitialize channel. When a channel undergoes autoinitialization, the original

values of the Current Page, Current Address and Current Byte/Word Count Registers

are automatically restored from the Base Page, Address, and Byte/Word Count

Registers of that channel following TC. The Base Registers are loaded simultaneously

with the Current Registers by the microprocessor when the DMA channel is

programmed and remain unchanged throughout the DMA service. The mask bit is not

set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor interv en tion, as soon as a valid DREQ

is detected.

5.6.5 Software Commands

There are three additional special software commands that the DMA controller can

execute. The three software commands are:

• Clear Byte Pointer Flip-Flop

•Master Clear

• Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

Table 5-10. DMA Transfer Size

DMA Device Date Size And Word Count Current Byte/Word

Count Register

Current Address

Increment/

Decrement

8-Bit I/O, Count By Bytes Bytes 1

16-Bit I/O, Count By Words (Address

Shifted) Words 1

Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers

Output

Address 8-Bit I/O Programmed

Address (Ch 0–3)

16-Bit I/O Programmed

Address (Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

Intel ® ICH7 Family Datasheet 127

Functional Description

5.7 LPC DMA (Desktop and Mobile Only)

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and

special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment

modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels

5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.

5.7.1 Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the

LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own

dedicated LDRQ# signal (they may not be shared between two separate peripherals).

The ICH7 has two LDRQ# inputs, allowing at least two devices to support DMA or bus

mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral

uses the following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high

during idle conditions.

• The next three bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is

active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is

inactive. The case where ACT is low is rare, and is only used to indicate that a

previous request for that channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least

1 clock. After that one clock, LDRQ# signal can be brought low to the next

encoding sequence.

If another DMA channel also needs to request a transfer, another sequence can be sent

on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel

3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral

can send the encoded request for channel 3. This allows multiple DMA agents behind an

I/O device to request use of the LPC interface, and the I/O device does not need to self -

arbitrate before sending the message.

5.7.2 Abandoning DMA Requests

DMA Requests can be deasserted in two fashions: on error conditions by sending an

LDRQ# message with the ‘ ACT’ bit set to 0, or normally through a SYNC field during the

DMA transfer. This section describes boundary conditions where the DMA request needs

to be removed prior to a data transfer.

There may be some special cases where the peripheral desires to abandon a DMA

transfer. The most likely case of this occurring is due to a floppy disk controller which

has overrun or underrun its FIFO, or software stopping a device prematurely.

Figure 5-6. DMA Requ est Assertion through L DR Q#

Start MSB LSB ACT Start

LCLK

LDRQ#

Functional Description

128 Intel ® ICH7 Family Datasheet

In these cases, the peripheral wishes to stop further DMA activity. It may do so by

sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was

seen by the ICH7, there is no assurance that the cycle has not been granted and will

shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may

still occur. The peripheral can choose not to respond to this cycle, in which case the

host will abort it, or it can choose to complete the cycle no rmally with any r andom data.

This method of DMA deassertion should be prevented whenever possible, to limit

boundary conditions both on the ICH7 and the peripheral.

5.7.3 General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the

host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts

LFRAME# on the LP C I/F and begins the DMA transfer. The general flow for a basic DMA

transfer is as follows:

1. ICH7 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.

2. ICH7 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. ICH7 asserts channel number and, if applicable, terminal count.

4. ICH7 indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read…

— The ICH7 drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16-bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write…

— The ICH7 turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16-bit transfer, the peripheral indicates data ready and transfers the next

byte.

7. The perip he ral turns around the bus.

5.7.4 Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates

the last byte of transfer, based upon the size of the transfer.

For example, on an 8-bit tr ansfer size (SIZE field is 00b), if the TC bit is set, then this is

the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the

second byte is the last byte. The peripheral, therefore, must internalize the TC bit when

the CHANNEL field is communicated, and only signal T C when the last byte of that

transfer size has been transferred.

5.7.5 Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is

similar to a DMA write, where the peripheral is transferring data to main memory. The

indication from the host is the same as a DMA write, so the peripheral will be driving

data onto the LPC interface. However, the host will not transfer this data into main

memory.

Intel ® ICH7 Family Datasheet 129

Functional Description

5.7.6 DMA Request Deassertion

An end of transfer is communicated to the ICH7 through a special SYNC field

transmitted by the peripheral. An LPC device must not attempt to signal the end of a

transfer by deasserting LDREQ#. If a DMA transfer is several bytes (e.g., a transfer

from a demand mode device) the ICH7 needs to know when to deassert the DMA

request based on the data currently being transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred, which

indicates to the ICH7 whether this is the last byte of transfer or if more bytes are

requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of

0000b (ready with no error), or 1010b

(ready with error). These encodings tell the ICH7 that this is the last piece of data

transferred on a DMA read (ICH7 to peripheral), or the byte that follows is the last

piece of data transferred on a DMA write (peripheral to ICH7).

When the ICH7 sees one of these two encodings, it ends the DMA transfer after this

byte and deasserts the DMA request to the 8237. Therefore, if the ICH7 indicated a 16-

bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC

value of 0000b or 1010b. The ICH7 does not attempt to transfer the second byte, and

deasserts the DMA request internally.

If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the

indicated size, then the ICH7 only deasserts the DMA request to the 8237 since it does

not need to end the transfer.

If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of

1001b (ready plus more data). This tells the 8237 that more data bytes are requested

after the current byte has been transferred, so the ICH7 keeps the DMA request active

to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC

value of 1001b to the ICH7, the data will be transferred and the DMA request will

remain active to the 8237. At a later time, the ICH7 will then come back with another

START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the

peripheral.

The peripheral must not assume that the next START indication from the ICH7 is

another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single

mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode

DMA devices can be ensured that they will receive the next START indication from the

ICH7.

Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit

channel (first byte of a 16-bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with

random data on DMA writes (peripher al to memory), and indicates to the 8237 that the

DMA transfer occurred, incrementing the 8237’s address and decrementing its byte

count.

5.7.7 SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and

are ended through a SYNC field during the DMA transfer, the peripheral must obey the

following rule when initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for eight LCLKs after a deassertion is

indicated through the SYNC field. This is needed to allow the 8237, that typically runs

off a much slower internal clock, to see a message deasserted before it is re-asserted

so that it can arbitrate to the next agent.

Functional Description

130 Intel ® ICH7 Family Datasheet

Under default operation, the host only performs 8-bit transfers on 8-bit channels and

16-bit transfers on 16-bit channels.

The method by which this communication between h ost and peripheral through system

BIOS is performed is bey ond the scope of this specification. Since the LPC host and LPC

peripheral are motherboard devices, no “plug-n-play” registry is required.

The peripheral must n ot assume that the host is able to perform tr ansfer sizes that are

larger than the size allowed for the DMA channel, and be willing to accept a SIZE field

that is smaller than what it may currently have buffered.

To that end, it is recommended that future devices that may appear on the LPC bus,

that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus

mastering interface and not rely on the 8237.

5.8 8254 Timers (D31:F0)

The ICH7 contains three counters that have fixed uses. All registers and functions

associated with the 8254 timers are in the core well. The 8254 unit is clocked by a

14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is

typically programmed for Mode 3 operation. The counter produces a square wave with

a period equal to the product of the counter period (838 ns) and the initial count value.

The counter loads the initial count value 1 counter period after software writes the

count value to the counter I/O address. The counter initially asserts IRQ0 and

decrements the count value by two each counter period. The counter negates IRQ0

when the count value reaches 0. It then reloads the initial count value and again

decrements the initial count value by two each counter period. The counter then

asserts IRQ0 when the count value reaches 0, reloads the initial count value, and

repeats the cycle, alternately asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter provides the refresh request signal and is typically programmed for Mode

2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial

count value is loaded one counter period after being written to the counter I/O address.

The REF_TOGGLE bit will hav e a square wave behavior (alternate between 0 and 1) and

will toggle at a rate based on the value in the counter. Programming the counter to

anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3

operation. The counter provides a speaker frequency equal to the counter clock

frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled

by a write to port 061h (see NMI Status and Control ports).

Intel ® ICH7 Family Datasheet 131

Functional Description

5.8.1 Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter.

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4)

of the 16-bit counter.

4. Repeat with other counters.

Only two conventions need to be observed when programming the counters. First, for

each counter, the control word must be written before the initial count is written.

Second, the initial count must follow the count format specified in the control word

(least significant byte only, most significant byte only, or least significant byte and then

most significant byte).

A new initial count may be written to a counter at any time without affecting the

counter's programmed m ode. Counting is affected as described in the mode definitions.

The new count must follow the programmed count format.

If a counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not tr ansfer control between writing the first and second byte

to another routine which also writes into that same counter. Otherwise, the counter will

be loaded with an incorrect count.

The Control Word R e gister at port 43h controls the operation of all three counters.

Several commands are available:

•Control Word Command. Specifies which counter to read or write, the operating

mode, and the count format (binary or BCD).

•Counter Latch Command. Latches the current count so that it can be read by the

system. The countdown process continues.

•Read Back Command. Reads the count value, programmed mode, the current

state of the OUT pins, and the state of the Null Count Flag of the selected counter.

Table 5-12 lists the six operating modes for the interval counters.

Table 5-12. Counter Operating Modes

Mode Function Description

0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to

1 and stays at 1 until counter is reprogrammed.

1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to

1 for one clock time.

2Rate generator (divide by n

counter) Output is 1. Output goes to 0 for one clock time,

then back to 1 and counter is reloaded.

3Square wave output

Output is 1. Output goes to 0 when counter rolls

over, and counter is reloaded. Output goes to 1

when counter rolls over, and counter is reloaded,

etc.

4 Software triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires

for one clock time.

Functional Description

132 Intel ® ICH7 Family Datasheet

5.8.2 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in

progress. There are three methods for reading the counters: a simple read operation,

counter Latch command, and the Read-Back command. Each is explained below.

With the simple read and counter latch command methods, the count must be read

according to the programmed format; specifically, if the counter is programmed for two

byte counts, two bytes must be read. The two bytes do not have to be read one right

after the other. Read, write, or programming operations for other counters may be

inserted between them.

5.8.2.1 Simple Read

The first method is to perform a simple read oper ation. The counter is selected through

port 40h (counter 0), 41h (counter 1), or 42h (counter 2).

Note: Performing a direct read from the counter does not return a determinate value,

because the counting process is asynchronous to read operations. Howev er, in the case

of counter 2, the count can be stopped by writing to the GATE bit in port 61h.

5.8.2.2 Counter Latch Command

The Counter Latch command, written to port 43h, latches the count of a specific

counter at the time the command is received. This command is used to ensure that the

count read from the counter is accurate, particularly when reading a two-byte count.

The count value is then read from each counter’s Count register as was programmed by

the Control register.

The count is held in the latch until it is read or the counter is reprogrammed. The count

is then unlatched. This allows reading the contents of the counters on the fly without

affecting counting in progress. Multiple Counter Latch Commands may be used to latch

more than one counter. Counter Latch commands do not affect the programmed mode

of the counter in any way.

If a Counter is latched and then, some time later, latched again before the count is

read, the second Counter Latch command is ignored. The count read is the count at the

time the first Counter Latch command was issued.

5.8.2.3 Read Back Command

The Read Back command, written to port 43h, latches the count value, programmed

mode, and current states of the OUT pin and Null Count flag of the selected counter or

counters. The value of the counter and its status may then be read by I/O access to the

counter address.

The Read Back command may be used to latch multiple counter outputs at one time.

This single command is functionally equiv alent to sever al counter latch commands, one

for each counter latched. Each counter's latched count is held until it is read or

reprogrammed. Once read, a counter is unlatched. The other counters remain latched

until they are read. If multiple count Read Back commands are issued to the same

counter without reading the count, all but the first are ignored.

The Read Back command may additionally be used to latch status information of

selected counters. The status of a counter is accessed by a read from that counter's

I/O port address. If multiple counter status latch operations are performed without

reading the status, all but the first are ignored.

Intel ® ICH7 Family Datasheet 133

Functional Description

Both count and status of the selected counters may be latched simultaneously. This is

functionally the same as issuing two consecutive, separate Read Back commands. If

multiple count and/or status Read Back commands are issued to the same counters

without any intervening reads, all but the first are ignored.

If both count and status of a counter are latched, the first read operation from that

counter returns the latched status, regardless of which was latched first. The next one

or two reads, depending on wheth er the co unter is programmed for one or two type

counts, returns the latched count. Subsequent reads return unlatched count.

5.9 8259 Interrupt Controllers (PIC) (D31:F0)

The ICH7 incorporates the functionality of two 8259 interrupt controllers that provide

system interrupts for the ISA compatible interrupts. These interrupts are: system

timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and

DMA channels. In addition, this interrupt controller can support the PCI based

interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each

8259 core supports eight interrupts, numbered 0–7. Table 5-13 shows how the cores

are connected.

The ICH7 cascades the slave controller onto the master controller through master

controller interrupt input 2. This means there are only 15 possible interrup t s for the

ICH7 PIC.

Table 5-13. Interrupt Controller Core Connections

8259 8259

Input Typical Interrupt

Source Connected Pin / Function

Master

0 Internal Internal Timer / Counte r 0 output / HPET #0

1 Keyboard IRQ1 via SERIRQ

2 Internal Slave controller INTR output

3 Serial Port A IRQ3 via SERIRQ, PIRQ#

4 Serial Port B IRQ4 via SERIRQ, PIRQ#

5 Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#

6 Floppy Disk IRQ6 via SERIRQ, PIRQ#

7 Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#

Slave

0Internal Real Time

Clock Internal RTC / HPET #1

1 Generic IRQ9 via SERIRQ, SCI, TCO, or PIRQ#

2 Gene ric IRQ10 via SERIRQ, SCI, TCO, or PIRQ#

3 Gene ric IRQ11 via SERIRQ, SCI, TCO, or PIRQ#

4 PS/2 Mouse IRQ12 via SERIRQ, SCI, TCO, or PIRQ#

5Internal State Machine output based on processor FERR#

assertion. May optionally be used for SCI or TCO

interrupt if FERR# not needed.

6IDE cable, SATA IDEIRQ (legacy mode, non-combined or combined

mapped as primary), SAT A Pr imary (legac y mode),

or via SERIRQ or PIRQ#

7IDE cable, SATA IDEIRQ (legacy mode — combined, mapped as

secondary), SATA Secondary (legacy mode) or via

SERIRQ or PIRQ#

Functional Description

134 Intel ® ICH7 Family Datasheet

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,

IRQ8#, and IRQ13.

Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH7. In the

following descriptions of the 8259s, the interrupt levels are in reference to the signals

at the internal interface of the 8259s, after the required inversions have occurred.

Therefore, the term “high” indicates “active,” which means “low” on an originating

PIRQ#.

5.9.1 Interrupt Handling

5.9.1.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each

interrupt level. These bits are used to determine the interrupt vector returned, and

status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR.

5.9.1.2 Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host

bridge into a PCI Interrupt Acknowledge Cycle to the ICH7. The PIC translates this

command into two internal INT A# pulses expected by the 8259 cores. The PIC uses the

first internal INT A# pulse to freeze the state of the in terrupts for priority resolution. On

the second INTA# pulse, the master or slave sends the interrupt vector to the

processor with the acknowledged interrupt code. This code is based upon bits [7:3] of

the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

Table 5-14. Interrupt Status Registers

Bit Description

IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt

line in edge mode, and by an active high level in level mode. This bit is set whether or

not the interrupt is masked. However, a masked interrupt will not generate INTR.

ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,

when an interrupt acknowledge cycle is seen, and the vector returned is for that

interrupt.

IMR Interrupt Mask Register. This bit determines whether an interrupt is masked.

Masked interrupts will not generate INTR.

Table 5-15. Content of Interrupt Vector Byte

Master, Slave Interrupt Bits [7:3] Bits [2:0]

IRQ7,15

ICW2[7:3]

111

IRQ6,14 110

IRQ5,13 101

IRQ4,12 100

IRQ3,11 011

IRQ2,10 010

IRQ1,9 001

IRQ0,8 000

Intel ® ICH7 Family Datasheet 135

Functional Description

5.9.1.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge

cycle. The cycle is translated into a PCI interru pt acknowledge cycle by the host

bridge. This command is broadcast over PCI by the ICH7.

4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH7 converts it

into the two cycles that the internal 8259 pair can respond to. Each cycle appears

as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded

interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR

bit is set and the corresponding IRR bit is reset. On the trailing edge of the first

pulse, a slave identification code is broadcast by the master to the slave on a

private, internal three bit wide bus. The slave controller uses these bits to

determine if it must respond with an interrupt vector during the second INTA#

pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the

interrupt vector. If no interrupt request is present because the request was too

short in duration, the PIC returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of

the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate

EOI command is issued at the end of the interrupt subroutine.

5.9.2 Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the ICH7, this is a four

byte sequence. The four initialization command words are referred to by their

acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the

I/O memory space: 20h for the master controller, and A0h for the slave controller.

5.9.2.1 ICW1

An I/O write to the master or sla ve contro ller base address with data bit 4 equ al to 1 is

interpreted as a write to ICW1. Upon sensing this write, the ICH7 PIC expects three

more byte writes to 21h for the master controller, or A1h for the slave controller, to

complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following

automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high

transition to generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special mask mode is cleared and Status Read is set to IRR.

Functional Description

136 Intel ® ICH7 Family Datasheet

5.9.2.2 ICW2

The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the

interrupt vector that will be released during an interrupt acknowledge. A different base

is selected for each interrupt controller.

5.9.2.3 ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to

cascade the slave controller. Within the ICH7, IRQ2 is used. Therefore, bit 2 of

ICW3 on the master controller is set to a 1, and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an

interrupt acknowledge cycle. On interrupt acknowledge cycles, the master

controller broadcasts a code to the slave controller if the cascaded interrupt won

arbitration on the master controller. The slave controller compares this

identification code to the value stored in its ICW3, and if it matches, the slave

controller assumes responsibility for broadcasting the interrupt vector.

5.9.2.4 ICW4

The final write in the sequence (ICW4) must be programmed for both controllers. At

the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in

an Intel Architecture-based system.

5.9.3 Operation Command Words (OCW)

These command words reprogram the Interrupt controller to operate in various

interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,

and controls the EOI function.

• OCW3 is sets up ISR/IRR reads, enables/disables the special mask mode (SMM),

and enables/disables polled interrupt mode.

5.9.4 Modes of Operation

5.9.4.1 Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being

the highest. When an interrupt is acknowledged, the highest priority request is

determined and its vector placed on the bus. Additionally, the ISR for the interrupt is

set. This ISR bit remains set until: the processor issues an EOI command immediately

before returning from the service routine; or if in AEOI mode, on the trailing edge of

the second INTA#. While the ISR bit is set, all further interrupts of the same or lower

priority are inhibited, while higher levels generate another interrupt. Interrupt priorities

can be changed in the rotating priority mode.

Intel ® ICH7 Family Datasheet 137

Functional Description

5.9.4.2 Special Fully-Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has

to be conserved within each slave. In this case, the special fully-nested mode is

programmed to the master controller. This mode is similar to the fully-nested mode

with the following exceptions:

• When an interrupt request from a certain slave is in service, this slave is not locked

out from the master's priority logic and further interr upt requests from higher

priority interrupts within the slave are recognized by the master and initiate

interrupts to the processor. In the normal-nested mode, a slave is masked out

when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the

interrupt serviced was the only one from that slave. This is done by sending a Non-

Specific EOI command to the slave and then reading its ISR. If it is 0, a non-

specific EOI can also be sent to the master.

5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority.

Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a

device receives the lowest priority after being serviced. In the worst case, a device

requesting an interrupt has to wait until each of seven other devices are serviced at

most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on

Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode

which is set by (R=1, SL=0, EOI=0).

5.9.4.4 Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programmin g the bo ttom priorit y. F or

example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest

priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:

R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it

is independent of the EOI command. Priority changes can be executed during an EOI

command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1

and LO–L2=IRQ level to receive bottom priority.

5.9.4.5 Poll Mode

Poll mode can be used to conserve space in the interrupt vector table. Multiple

interrupts that can be serviced by one interrupt service routine do not need separate

vectors if the service routine uses the poll command. Poll mode can also be used to

expand the number of interrupts. The polling interrupt service routine can call the

appropriate service routine, instead of providing the interrupt vectors in the vector

table. In this mode, the INTR output is not used and the microprocessor internal

Interrupt Enable flip-flop is reset, disabling its inte rrupt input. Service to devices is

achieved by software using a Poll command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as

an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads

the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte

returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary

code of the highest priority level in bits 2:0.

Functional Description

138 Intel ® ICH7 Family Datasheet

5.9.4.6 Cascade Mode

The PIC in the ICH7 has one master 8259 and one slave 8259 cascaded onto the

master through IRQ2. This configuration can handle up to 15 separate priority levels.

The master controls the slaves through a three bit internal bus. In the ICH7, when the

master drives 010b on this bus, the slave controller takes responsibility for returning

the interrupt vector. An EOI command must be issued twice: once for the master and

once for the slave.

5.9.4.7 Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge

for the entire controller. In the ICH7, this bit is disabled and a new register for edge and

level triggered mode selection, per interrupt input, is included. This is the Edge/Level

control Registers ELCR1 and ELCR2.

If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition

on the corresponding IRQ input. The IRQ input can remain high without generating

another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high

level on the corresponding IRQ input and there is no need for an edge detection. The

interrupt request must be removed before the EOI command is issued to prevent a

second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until

after the falling edge of the first internal INTA#. If the IRQ input goes inactive before

this time, a default IRQ7 vector is returned.

5.9.4.8 End of Interrupt (EOI) Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC

before returning from a service routine, the EOI command; or automatically when AEOI

bit in ICW4 is set to 1.

5.9.4.9 Normal End of Interrupt

In normal EOI, software writes an EOI command before leaving the interrupt service

routine to mark the interrupt as completed. There are two forms of EOI commands:

Specific and

Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest

ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of

the PIC within the ICH7, as the interrupt being serviced currently is the interrupt

entered with the interrupt acknowledge. When the PIC is operated in modes that

preserve the fully nested structure, software can determine which ISR bit to clear by

issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if

the PIC is in the special mask mode. An EOI command must be issued for both the

master and slave controller.

5.9.4.10 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the

trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this

mode should be used only when a nested multi-level interrupt structure is not required

within a single PIC. The AEOI mode can only be used in the master controller and not

the slave controller.

Intel ® ICH7 Family Datasheet 139

Functional Description

5.9.5 Masking Interrupts

5.9.5.1 Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register

(IMR). This register is programmed through OCW1. Each bit in the IMR masks one

interrupt channel. Masking IRQ2 on the master controller masks all requests for service

from the slave controller.

5.9.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under softw are control. For example, the

routine may wish to inhibit lower priority requests for a portion of its execution but

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask

issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority

requests. In the special mask mode, any interrupts may be selectively enabled by

loading the Mask Register with the appropriate pattern. The special mask mode is set

by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.

5.9.6 Steering PCI Interr upts

The ICH7 can be programmed to allow PIRQA#-PIRQH# (PIRQE#–PIRQH# on Ultra

Mobile) to be internally routed to interrupts 3–7, 9–12, 14 or 15. The assignment is

programmable through the through the PIRQx Route Control registers, located at 60–

63h and 68–6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to

the same IRQx input. If interrupt steering is not required, the Route registers can be

programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts

on a PCI board to share a single line across the connector. When a PIRQx# is routed to

specified IRQ line, software must change the IRQ's corresponding ELCR bit to level

sensitive mode. The ICH7 internally in verts the PIRQx# line to send an active high level

to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer

be used by an active high device (through SERIRQ). However, active low interrupts can

share their interrupt with PCI interrupts.

Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external

PIRQ to be asserted. The ICH7 receives the PIRQ input, like all of the other external

sources, and routes it accordingly.

Functional Description

140 Intel ® ICH7 Family Datasheet

5.10 Advanced Programmable Interrupt Controller

(APIC) (D31:F0)

In addition to the standard ISA-compatible PIC described in the previous chapter, the

ICH7 incorporates the APIC. While the st and ard interrupt controller is intended for use

in a uni-processor system, APIC can be used in either a uni-processor or multi-

processor system.

5.10.1 Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these

differences are:

•Method of Interrupt Transmission. The I/O APIC transmits interrupts through

memory writes on the normal datapath to the processor, and interrupts are handled

without the need for the processor to run an interrupt acknowledge cycle.

•Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the

interrupt number. For example, interrupt 10 can be given a higher priority than

interrupt 3.

•More Interrupts. The I/O APIC in the ICH7 supports a total of 24 interrupts.

•Multiple Interrup t Contro llers. The I/O APIC architecture allows for multiple I/O

APIC devices in the system with their own interrupt vectors.

5.10.2 Interrupt Mapping

The I/O APIC within the ICH7 supports 24 APIC interrupts. Each interrupt has its own

unique vector assigned by software. The interrupt vectors are mapped as follows, and

match “Config 6” of the Multi-Processor Specification.

Table 5-16. APIC Interrupt Mapping (Sheet 1 of 2)

IRQ #1Via

SERIRQ Direct

from Pin Via PCI

Message Internal Modules

0 No No No Cascade from 8259 #1

1Yes No Yes

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

3Yes No Yes

4Yes No Yes

5Yes No Yes

6Yes No Yes

7Yes No Yes

8NoNoNoRTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO2

12 Yes No Yes

13 No No No FERR# logic

14 Yes Yes3Yes ID EIRQ (legacy mode, non-combined or

combined mapped as primary), SATA Primary

(legacy mode)

15 Yes Yes Yes IDEIRQ (legacy mode — combined, mapped as

secondary), SATA Secondary (legacy mode)

Intel ® ICH7 Family Datasheet 141

Functional Description

NOTES:

1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0

through 15 receive active-high internal interrupt sources, while interrupts 16 through 23

receive acti ve-low internal interrupt sources.

2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other

devices to ensure the proper operation of HPET #2. ICH7 hardware does not prevent

sharing of IRQ 11.

3. IDEIRQ can only be driven directly from the pin when in legacy IDE mode.

5.10.3 PCI / PCI Express* Message-Based Interrupts

When external devices through PCI / PCI Express wish to generate an interrupt, they

will send the message defined in the PCI Express* Base Specification, Revision 1.0a for

generating INTA# – INTD#. These will be translated internal assertions/de-assertions

of INTA# – INTD#.

5.10.4 Front Side Bus Interrupt Delivery

For processors that support Front Side Bus (FSB) interrupt delivery, the ICH7 requires

that the I/O APIC deliver interrupt messages to the processor in a parallel manner,

rather than using the I/O APIC serial scheme.

This is done by the ICH7 writing (via DMI) to a memory location that is snooped by the

processor(s). The processor(s) snoop the cycle to know which interrupt goes active.

The following sequence is used:

1. When the ICH7 detects an interrupt event (active edge for edge-triggered mode or

a change for level-triggered mode), it sets or resets the internal IRR bit associated

with that interrupt.

2. Internally, the ICH7 requests to use the bus in a way that automatically flushes

upstream buffers. This can be internally implemented similar to a DMA device

request.

3. The ICH7 then delivers the message by performing a write cycle to the appropriate

address with the appropriate data. The address and data formats are described

below in Section 5.10.4.4.

Note: FSB Interrupt Delivery compatibility with processor clock control depends on the

processor, not the ICH7.

16 PIRQA# PIRQA#

Yes

Internal devices are routable; see

Section 7.1.41 though Section 7.1.50.

NOTE: PIRQA#–PIRQD# are not on Ultra

Mobile.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

20 N/A PIRQE#

Yes Option for SCI, TCO, HPET #0,1,2. Other

internal devices are routable; see

Section 7.1.41 through Section 7.1.50.

21 N/A PIRQF#

22 N/A PIRQG#

23 N/A PIRQH#

Table 5-16. APIC Interrupt Mapping (Sheet 2 of 2)

IRQ #1Via

SERIRQ Direct

from Pin Via PCI

Message Internal Modules

Functional Description

142 Intel ® ICH7 Family Datasheet

5.10.4.1 Edge-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on

the interrupt.

5.10.4.2 Level-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on

the interrupt. If after the EOI the interrupt is still active, then another “ Assert Message”

is sent to indicate that the interrupt is still active.

5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery

Capabilities Indication: The capability to support Front Side Bus interrupt delivery is

indicated via ACPI configuration techniques. This involves the BIOS creating a data

structure that gets reported to the ACPI configuration software.

5.10.4.4 Interrupt Message Format

The ICH7 writes the message to PCI (and to the Host controller) as a 32-bit memory

write cycle. It uses the formats shown in Table 5-17 and Table 5-18 for the address and

data.

The local APIC (in the processor) has a delivery mode option to interpret Front Side Bus

messages as a SMI in which case the processor treats the incoming interrupt as a SMI

instead of as an interrupt. This does not mean that the ICH7 has any wa y to have a SMI

source from ICH7 power management logic cause the I/O APIC to send an SMI

message (there is no way to do this). The ICH7’s I/O APIC can only send interrupts due

to interrupts which do not include SMI, NMI or INIT. This means that in IA32/IA64

based platforms, Front Side Bus interrupt message format delivery modes 010

(SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used

and is not supported. Only the hardware pin connection is supported by ICH7.

Table 5-17. Interrupt Message Address Format

Bit Description

31:20 Will allways be FEEh

19:12 Destination ID: T his is the same as bits 63:56 of the I /O Redirect ion Table entry for

the interrupt associated with this message.

11:4 Extended Destination ID: This is the same as bits 55:48 of the I/O Redirection

Table entry for the interrupt associated with this message.

Redirection Hint: This bit is used by the proc essor host bridge to allow the interrupt

message to be redirected.

0 = The message will be delivered to the agent (processor) listed in bits 19:12.

1 = The message will be delivered to an agent with a lower interrupt priority This can

be derived from bits 10:8 in the Data Field (see below).

The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated

with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the

Redirection Hint bit will be 0

Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the

Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical

destination mode is used, and the redirection is l imited on ly to t hose proc essors that

are part of the logical group as based on the logical ID.

1:0 Will always be 00.

Intel ® ICH7 Family Datasheet 143

Functional Description

5.11 Serial Interrupt (D31:F0)

The ICH7 supports a serial IRQ scheme. This allows a single signal to be used to report

interrupt requests. The signal used to transmit this information is shared between the

host, the ICH7, and all peripherals that support serial interrupts. The signal line,

SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is

used by all PCI signals. This means that if a device has driven SERIRQ low, it will first

drive it high synchronous to PCI clock and release it the following PCI clock. The serial

IRQ protocol defines this sustained tri-state signaling in the following fashion:

•S – Sample Phase. Signal driven low

•R – Recovery Phase. Signal driven high

•T – Turn-around Phase. Signal released

The ICH7 supports a message for 21 serial interrupts. These represent the 15 ISA

interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and

IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts

(20–23).

Note: When the IDE controller is enabled or the SATA controller (Desktop and Mobile Only) is

configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA

legacy interrupts, which cannot be shared, i.e. through the Serial Interrupt pin. If

IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior

may occur. For example, IRQ14/15 may not be detected by ICH7's interrupt controller.

5.11.1 Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These

two modes are: Continuous, where the ICH7 is solely responsible for generating the

start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the

start frame.

Table 5-18. Interrupt Message Data Format

Bit Description

31:16 Will always be 0000h.

15 Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O

Redirection Table for that interrupt.

14 Delivery Status: 1 = Assert, 0 = Deassert. Only Assert me ss ages are s ent. This bit

is always 1.

13:12 Will always be 00

11 Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the

I/O Redirection Table for that interrupt.

10:8

Delivery Mode: This is the same as the corresponding bits in the I/O Redirection

Table for that interrupt.

000 = Fixed 100 = NMI

001 = Lowest Priority 101 = INIT

010 = SMI/PMI 110 = Reserved

011 = Reserved 111 = ExtINT

7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for

that interrupt.

Functional Description

144 Intel ® ICH7 Family Datasheet

The mode that must first be entered when enabling the serial IRQ protocol is

continuous mode. In this mode, the ICH7 asserts the start frame. This start fr ame is 4,

6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in

Device 31:Function 0 configuration space. This is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the

SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a

peripheral drives the SERIRQ signal low . The ICH7 senses the line low and continues to

drive it low for the remainder of the Start Frame. Since the first PCI clock of the start

frame was driven by the peripheral in this mode, the ICH7 drives the SERIRQ line low

for 1 PCI clock less than in continuous mode. This mode of oper ation allows for a quiet,

and therefore lower power, operation.

5.11.2 Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start

counting frames based on the rising edge of SERIRQ. Each of the IRQ/DAT A fr ames has

exactly 3 phases of 1 clock each:

•Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, then

the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due

to pull-up resistors (there is no internal pull-up resistor on this signal, an external

pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 fr ames

indicates that an active-high ISA interrupt is not being requested, but a low level

during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low

interrupt is being requested.

•Recovery Phase. During this phase, the device drives the SERIRQ line high if in

the Sample Phase it was driven low. If it was not driven in the sample phase, it is

tri-stated in this phase.

•Turn-around Phase. The device tri-states the SERIRQ line

5.11.3 Stop Frame

After all data frames, a Stop Frame is driven by the ICH7. The SERIRQ signal is driven

low by the ICH7 for 2 or 3 PCI clocks. The number of clocks is determined by the

SERIRQ configuration register. The number of clocks determines the next mode:

5.11.4 Specific Interrupts Not Supported via SERIRQ

There are three interrupts seen through the serial stream that are not supported by the

ICH7. These interrupts are generated internally, and are not sharable with other

devices within the system. These interrupts are:

• IRQ0. Heartbeat interrupt ge nerated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of

FERR#.

The ICH7 ignores the state of these interrupts in the serial stream, and does not adjust

their level based on the level seen in the serial stream.

Table 5-19. Stop Frame Explanation

Stop Frame Width Next Mode

2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame

3 PCI clocks Continuous Mode. Only the host (Intel® ICH7) may initiate a Star t

Frame

Intel ® ICH7 Family Datasheet 145

Functional Description

5.11.5 Data Frame Format

Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the

output from the ICH7 is ANDed with the PCI input signal. This way, the interrupt can be

signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are

shared).

Table 5-20. Data Frame Format

Data

Frame # Interrupt Clocks Past

Start

Frame Comment

1IRQ0 2

Ignored. IRQ0 can only be generated via the internal

8524

2IRQ1 5

3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.

4IRQ3 11

5IRQ4 14

6IRQ5 17

7IRQ6 20

8IRQ7 23

9 IRQ8 26 Ignored. IRQ8# can only be generated internally.

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#

15 IRQ14 44 Not attached to PATA or SATA logic

16 IRQ15 47 Not attached to PATA or SATA logic

17 IOCHCK# 50 Same as ISA IOCHCK# going active.

18 PCI INTA# 5 3 Drive PIRQA#

19 PCI INTB # 56 Drive PIRQB#

20 PCI INTC# 59 Drive PIRQC#

21 PCI INTD# 62 Drive PIRQD#

Functional Description

146 Intel ® ICH7 Family Datasheet

5.12 Real Time Clock (D31:F0)

The Re al Time Clock (RT C) module provides a battery backed-up d ate and time keeping

device with two banks of static RAM with 128 bytes each, although the first bank has

114 bytes for general purpose usage. Three interrupt features are available: time of

day alarm with once a second to once a month range, periodic rates of 122 µs to

500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of

week, month, and year are counted. Daylight savings compensation is available. The

hour is represented in twelve or twenty-four hour format, and data can be represen ted

in BCD or binary format. The design is functionally compatible with the Motorola

MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is

divided to achieve an update every second. The lower 14 bytes on the lower RAM block

has very specific functions. The first ten are for time and date information. The next

four (0Ah to 0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour

mode (12 or 24 hour) as selected in register B. It is up to the programmer to make

sure that data stored in these locations is within the reasonable values ranges and

represents a possible date and time. The exception to these ranges is to store a value

of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions

must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.

The SET bit must be 1 while programming these locations to avoid clashes with an

update cycle. Access to time and date information is done through the RAM locations. If

a RAM read from the ten time and date bytes is attempted during an update cycle, the

value read do not necessarily represent the true contents of those locations. Any RAM

writes under the same conditions are ignored.

Note: The leap year determination for adding a 29th day to February does not take into

account the end-of-the-century exceptions. The logic simply assumes that all years

divisible by 4 are leap years. According to the Ro yal Observ atory Greenwich, y ears that

are divisible by 100 are typically not leap years. In every fourth century (years divisible

by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note

that the year 2100 will be the first time in which the current RT C implementation would

incorrectly calculate the leap-year.

The ICH7 does not implem ent month/year alarms.

5.12.1 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and

the divide chain is properly configured. During this procedure, the stored time and date

are incremented, overflow is checked, a matching alarm condition is checked, and the

time and date are rewritten to the RAM locations. The update cycle will start at least

488 µs after the UIP bit of register A is asserted, and the entire cycle does not take

more than 1984 µs to complete. The time and date RAM locations (0–9) are

disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations

can safely occur at two times. When a updated-ended interrupt is detected, almost 999

ms is available to read and write the valid time and date data. If the UIP bit of Register

A is detected to be low, there is at least 488 µs before the update cycle begins.

Warning: The overflow conditions for leap years and daylight savings adjustments are based on

more than one date or time item. To ensure proper operation wh en adjusting the time,

the new time and data values should be set at least two seconds before one of these

conditions (leap year, daylight savings time adjustments) occurs.

Intel ® ICH7 Family Datasheet 147

Functional Description

5.12.2 Interrupts

The real-time clock interrupt is internally routed within the ICH7 both to the I/O APIC

and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the

ICH7, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is

ignored. However, the High Performance Event Timers can also be mapped to IRQ8#;

in this case, the RTC interrupt is blocked.

5.12.3 Lockable RAM Ranges

The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the

configuration space. If the locking bits are set, the corresponding r ange in the RAM will

not be readable or writable. A write cycle to those locations will have no effect. A read

cycle to those locations will not return the location’s actual value (resultant value is

undefined).

Once a range is locked, the range can be unlocked only by a hard reset, which will

invoke the BIOS and allow it to relock the RAM range.

5.12.4 Century Rollover

The ICH7 detects a rollover when the Year byte (RTC I/O space, index offset 09h)

transitions form 99 to 00. Upon detecting the rollover, the ICH7 sets the

NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this

causes an SMI#. The SMI# handler can update registers in the RTC RAM that are

associated with century value. If the system is in a sleep state (S1–S5) when the

century rollover occurs, the ICH7 also sets the NEWCENTURY_STS bit, but no SMI# is

generated. When the system resumes from the sleep state, BIOS should check the

NEWCENTURY_STS bit and update the century value in the RTC RAM.

5.12.5 Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an ICH7-based platform can be done by using a jumper on

RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

Using RTCRST# to Clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,

the state of those configuration bits that reside in the RTC power well. When the

RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set

and those configuration bits in the RTC power well will be set to their default state.

BIOS can monitor the state of this bit, and manually clear the RT C CMOS array once the

system is booted. The normal position would cause R T CRST# to be pulled up through a

weak pull-up resistor. Table 5-21 shows which bits are set to their default state when

R TCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved

and then replaced—all while the system is powered off. Then, once booted, the

RTC_PWR_STS can be detected in the set state.

Functional Description

148 Intel ® ICH7 Family Datasheet

Table 5-21. Configuration Bits Reset by RTCRST# A ssertion (Sheet 1 of 2)

Bit Name Register Location Bit(s) Default

State

Alarm Interrupt Enable

(AIE)

Regi ster B (Gener al

Configuration)

(RTC_REGB)

I/O space (RTC Index +

0Bh) 5X

Alarm Flag (AF) Register C (Flag

(RTC_REGC)

I/O space (RTC Index +

0Ch) 5X

SWSMI_RATE_SEL

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 7:6 0

SLP_S4# Minimum

Assertion Width

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 5:4 0

SLP_S4# Assertion

Stretch Enable

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 3 0

RTC Power Statu s

(RTC_PWR_STS)

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 2 0

Power Failu re

(PWR_FLR)

General PM

Configuration 3

(GEN_PMCON_3)

D31:F0:A4h 1 0

AFTERG3_EN

General PM

Configuration 3

GEN_PMCON_3

D31:F0:A4h 0 0

Power Button Override

Status

(PRBTNOR_STS)

Power Management 1

Status Register

(PM1_STS) PMBase + 00h 11 0

RTC Event Enable

(RTC_EN)

Power Management 1

Enable Register

(PM1_EN) PMBase + 02h 10 0

Sleep Type (SLP_TYP) Power Management 1

Control (PM1_CNT) PMBase + 04h 12:10 0

PME_EN General Purpose

Event 0 Enables

BATLOW_EN

(Mobile/Ultra Mobile

Only)

General Purpose

Event 0 Enables

RI_EN General Purpose

Event 0 Enables

Intel ® ICH7 Family Datasheet 149

Functional Description

Using a GPI to Clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the

setting of this GPI on system boot-up , and manually clear the CMOS arr a y.

Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The

system is booted with the jumper in new position, then powered back down. The

jumper is replaced back to the normal position, then the system is rebooted again.

Warning: Clearing CMOS, using a jumper on VccRTC, must not be implemented.

5.13 Processor Interface (D31:F0)

The ICH7 interfaces to the processor with a variety of signals

• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,

IGNNE#, CPUSLP# (supported only on desktop platforms), CPUPWRGD

• Standard Input from processor: FERR#

• Intel SpeedSte p® technology output to processor: CPUPWRGOOD (In mobile/Ultra

Mobile configurations)

Most ICH7 outputs to the processor use standard buffers. The ICH7 has separate

V_CPU_IO signals that are pulled up at the system level to the processor voltage, and

thus determines VOH for the outputs to the processor.

5.13.1 Processor Interface Signals

This section describes each of the signals that interface between the ICH7 and the

processor(s). Note that the behavior of some signals may vary during processor reset,

as the signals are used for frequency strapping.

5.13.1.1 A20M# (Mask A20)

The A20M# signal is active (low) when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0

• The A20GATE input signal is a 0

The A20GATE input signal is expected to be generated by the external microcontroller

(KBC).

NEWCENTURY_STS TCO1 Status Register

(TCO1_STS) TCOBas e + 04h 7 0

Intruder Dete ct

(INTRD_DET) TCO2 Status Register

(TCO2_STS) TCOBas e + 06h 0 0

Top Swap (TS) Backed Up Control

Registers:Offset 3414h 0X

PA T A Reset State (PRS)

(Mobile/Ultra Mobile

Only)

Backed Up Control

Registers:Offset 3414h 11

Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)

Bit Name Register Location Bit(s) Default

State

Functional Description

150 Intel ® ICH7 Family Datasheet

5.13.1.2 INIT# (Initialization)

The INIT# signal is active (driven low) based on any one of sev eral events described in

Table 5-22. When any of these events occur, INIT# is driven low for 16 PCI clocks, then

driven high.

Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if

INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after

STPCLK# goes inactiv e .

This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as

INIT3_3V# is functionally identical to INIT#, but signaling at 3.3 V.

5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error)

The ICH7 supports the coprocessor error function with the FERR#/IGNNE# pins. The

function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset

31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If

FERR# is driven active by the processor, IRQ13 goes active (internally). When it

detects a write to the COPROC_ERR register (I/O Register F0h), the ICH7 negates the

internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven

inactive. IGNNE# is not driven active unless FERR# is active.

Table 5-22. INIT# Going Active

Cause of INIT# Going Active Comment

Shutdown special cycle from processor.

PORT92 write, where INIT_NOW (bit 0) tr ansitions

from a 0 to a 1.

PORTCF9 write, where SYS_RS T (bit 1) was a 0

and RST_CPU (bit 2) transitions from 0 to 1.

RCIN# input signal goes low. RCIN# is expected

to be driven by the external microcontroller

(KBC).

0 to 1 transition on RCIN# must occur

before the Intel® ICH7 will arm INIT# to be

generated again.

NOTE: RCIN# signal is expected to be high

during S3HOT and low during

S3COLD, S4, and S5 states.

Transition on the RCIN# signal in

those states (or the transition to

those states ) may not necessarily

cause the INIT# signal to be

generated to the processor.

CPU BIST To enter BIST, software sets CPU_BIST_EN

bit and then does a full processor reset

using the CF9 register.

Intel ® ICH7 Family Datasheet 151

Functional Description

If COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an

internal IRQ13, nor will the write to F0h generate IGNNE#.

5.13.1.4 NMI (Non-Maskable Interrupt)

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in

Table 5-23.

5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)

The ICH7 power management logic controls these active-low signals. Refer to

Section 5.14 for more information on the functionality of these signals.

Note: CPU Sleep (CPUSLP#) is supported only on desktop platforms.

5.13.1.6 CPU Power Good (CPUPWRGOOD)

This signal is connected to the processor’s PWRGOOD input. This signal represents a

logical AND of the ICH7’s PWROK and VRMPWRGD signals.

5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only)

This active-low signal controls the internal gating of the processor’s core clock. This

signal asserts before and deasserts after the STP_CPU# signal to effectively stop the

processor’s clock (internally) in the states in which STP_CPU# can be used to stop the

processor’s clock externally.

Figure 5-7. Coprocessor Error Timing Diagram

FERR#

Internal IRQ13

I/O Write to F0h

IGNNE#

Table 5-23. NMI Sources

Cause of NMI Comment

SERR# goes active (either inter nally,

externally via SERR# signal, or via

message from (G)MCH)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, bit 11).

IOCHK# goes active via SERIRQ# stream

(ISA system Error)

Can instead be routed to generate an SCI, through

the NMI2SCI_EN bit (Device 31:Function 0, TCO

Base + 08h, bit 11).

Functional Description

152 Intel ® ICH7 Family Datasheet

5.13.2 Dual-Processor Issues (Desktop Only)

5.13.2.1 Signal Differences

In dual-processor designs, some of the processor signals are unused or used differently

than for uniprocessor designs.

5.13.2.2 Power Management

For multiple-processor (or Multiple-core) configurations in which more than one Stop

Grant cycle ma y be gener ated, the (G)MCH is expected to count Stop Gr ant cy cles and

only pass the last one through to the ICH7. This prevents the ICH7 from getting out o f

sync with the processor on multiple STPCLK# assertions.

Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be

connected to both processors. However, for ACPI implementations, the BIOS must

indicate that the ICH7 only supports the C1 state for dual-processor designs.

In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by

the processors. The ICH7 also has the option to assert the processor’s SLP# signal

(CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the

transition to the S1 state), the processors will not be executing code that is likely to

delay the Stop-Grant cycles.

In going to the S3, S4, or S5 states, the system will appear to pass through the S1

state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both

processors will lose power. Upon exit from those states, the processors will have their

power restored.

Table 5-24. DP Signal Differences

Signal Difference

A20M# / A20GATE Generally not used, but still supported by Intel® ICH7.

STPCLK# Used for S1 State as well as preparation for entry to S3–S5

Also allows for THERM# based throttling (not via ACPI control methods).

Should be connected to both processors.

FERR# / IGNNE# Generally not used, but still supported by ICH7.

Intel ® ICH7 Family Datasheet 153

Functional Description

5.14 Power Management (D31:F0)

5.14.1 Features

• Support for Advanced Configuration and Power Interface, Version 2.0 (ACPI)

providing power and thermal management

— ACPI 24-Bit Timer

— Software initiated throttling of processor performance for Thermal and Power

Reduction

— Hardware Override to throttle processor performance if system too hot

—SCI and SMI# Generation

• PCI PME# signal for Wake Up from Low-Power states

• System Clock Control

— (Mobile/Ultra Mobile Only) ACPI C2 state: Stop Grant (using STPCLK# signal)

halts processor’s instruction stream

— (Mobile/Ultra Mobile Only) ACPI C3 State: Ability to halt processor clock (but

not memory clock)

— (Mobile/Ultra Mobile Only) ACPI C4 State: Ability to lower processor voltage.

— (Mobile/Ultra Mobile Only) CLKRUN# Protocol for PCI Clock Starting/Stopping

• System Sleep State Control

— ACPI S1 state: Stop Grant (using STPCLK# signal) halts processor’s instruction

stream (only STPCLK# active, and CPUSLP# optional)

— ACPI S3 state — Suspend to RAM (STR)

— ACPI S4 state — Suspend-to-Disk (STD)

— ACPI G2/S5 state — Soft Off (SOFF)

— Power Fa ilure Detection and Recovery

• Streamlined Legacy Power Management for APM-Based Systems

5.14.2 Intel® ICH7 and System Power States

Table 5-25 shows the power states defined for ICH7-based platforms. The state names

generally match the corresponding ACPI states.

Table 5-25. General Power States for Systems Using Intel® ICH7 (Sheet 1 of 2)

State/

Substates Legacy Name / Description

G0/S0/C0

Full On: Processor operating. Individual devices may be shut down to save

power. The different processor operating levels ar e de fined by Cx states, as

shown in Table 5-26. W ithin the C0 state, the Intel® ICH7 can throttle the

processor using the STPCLK# signal to reduce power consumption. The throttling

can be initiated by software or by the operating system or BIOS.

G0/S0/C1 Auto-Halt: Processor has executed an AutoHalt instruction and is not executing

code. The processor snoops the bus and maintains cache coherency.

G0/S0/C2

(Mobile/Ultra

Mobile Only)

Stop-Grant: The STPCLK# signal goes active to the processor. The processor

performs a Stop-Grant cycle, halts its instruction stream, and remains in that

state until the STPCLK# signal goes inactive. In the Stop-Grant state, the

processor snoops the bus and maintains cache coherency.

Functional Description

154 Intel ® ICH7 Family Datasheet

Table 5-26 shows the transitions rules among the various states. Note that transitions

among the various states may appear to temporarily transition through intermediate

states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/

C2 states. These intermediate transitions and states are not listed in the table.

G0/S0/C3

(Mobile/Ultra

Mobile Only)

Stop-Clock: The STPCLK# signal goes active to the processor. The processor

performs a Stop-Grant cycle, halts its instruction stream. ICH7 then asserts

DPSLP# followed by STP_CPU#, which forces the clock generator to stop the

processor clock. This is also used for Intel SpeedStep® technology support.

Accesses to memory (b y graphics, PCI, or inte rnal units) is not permitt ed while in

a C3 state.

G0/S0/C4

(Mobile/Ultra

Mobile Only)

Stop-Clock with Lower Processor Voltage: This closely resembles the G0/

S0/C3 state. However, after the ICH7 has asserted STP_CPU#, it then lowers the

voltage to the processor. This reduces the leakage on the processor. Prior to

exiting the C4 state, the ICH7 increases the voltage to the processor.

G1/S1

Stop-Grant: Similar to G0/S0/C2 state. ICH7 also has the option to assert the

CPUSLP# signal to further reduce processor power consumption (Desktop only).

Note: The behavior for this state is slightly different when supporting iA64

processors.

G1/S3 Suspend-To-RAM (STR): The system context is mai ntained in system DRAM,

but power is shut off to non-critical circuits. Memory is retained, and refreshes

continue. All clocks stop except RTC clock.

G1/S4 Suspend-To-Disk (S TD): The context of the system is maintained on the disk.

All power is then shut off to the system except for the logic required to resume.

G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except

for the logic required to restart. A full boot is required when waking.

Mechanical OFF (MOFF): System context not maintained. All power is shut off

except for the RT C. No “W ake” events are possible, because the system does not

have any power. This state occurs if the user removes the batteries, turns off a

mechanical switch, or if the system power supply is at a level that is insufficient

to power the “waking” logic. When system power returns, transition will depends

on the state just prior to the entry to G3 and the AFTERG3 bit in the

GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-33 for more details.

Table 5-25. General Power States for Systems Using Intel® ICH7 (Sheet 2 of 2)

State/

Substates Legacy Name / Description

Intel ® ICH7 Family Datasheet 155

Functional Description

NOTES:

1. Some wake events can be preserved through power failure.

2. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is

inactive in mobile/Ultra Mobile configurations.

Table 5-26. State Transition Rules for Intel® ICH7

Present

State Transition Trigger Next State

G0/S0/C0

• Processor halt instruction

•Level 2 Read

• Level 3 Read (Mobile/Ultra Mobile

Only)

• Level 4 Read (Mobile/Ultra Mobile

Only)

•SLP_EN bit set

• Power Button Override

• Mechanical Off/Power Failure

•G0/S0/C1

•G0/S0/C2

• G0/S0/C2, G0/S0/C3 or G0/S0/C4 -

depending on C4onC3_EN bit

(D31:F0:Offset A0h:bit 7) and

BM_STS_ZERO_EN bit (D31:F0:Offset

A9h:bit 2) (Mobile/Ultra Mobile Only)

• G1/Sx or G2/S5 state

•G2/S5

•G3

G0/S0/C1

• Any Enabled Break Eve nt

•STPCLK# goes active

• Power Button Override

• Power Failure

•G0/S0/C0

•G0/S0/C2

•G2/S5

•G3

G0/S0/C2

(Mobile/

Ultra

Mobile

Only)

• Any Enabled Break Eve nt

• Power Button Override

• Power Failure

• Previously in C3/C4 and bus masters

idle

•G0/S0/C0

•G2/S5

•G3

• C3 or C4 - depending on PDME bit (D31:F0:

Offset A9h: bit 4)

G0/S0/C3

(Mobile/

Ultra

Mobile

Only)

• Any Enabled Break Eve nt

• Any Bus Master Event

• Power Button Override

• Power Failure

• Previously in C4 and bus masters idle

•G0/S0/C0

• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:

bit 3) is set, else G0/S0/C0

•G2/S5

•G3

• C4 - depending on PDME bit (D31:F0: Offset

A9h: bit 4

G0/S0/C4

(Mobile/

Ultra

Mobile

Only)

• Any Enabled Break Eve nt

• Any Bus Master Event

• Power Button Override

• Power Failure

•G0/S0/C0

• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:

bit 3) is set, else G0/S0/C0

•G2/S5

•G3

G1/S1,

G1/S3, or

G1/S4

•Any Enabled Wake Event

• Power Button Override

• Power Failure

• G0/S0/C0 (See Note 2)

•G2/S5

•G3

G2/S5 •Any Enabled Wake Event

• Power Failure • G0/S0/C0 (See Note 2)

•G3

G3 •Power Returns • Optional to go to S0/C0 (reboot) or G2/S5

(stay off until power bu tton pressed or other

wake event). (See Note 1 and 2)

Functional Description

156 Intel ® ICH7 Family Datasheet

5.14.3 System Power Planes

The system has several independent power planes , as described in Table 5-27. Note

that when a particular power plane is shut off, it should go to a 0 V level.

5.14.4 SMI#/SCI Generation

On any SMI# event taking place, ICH7 asserts SMI# to the processor, which causes it

to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is

set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI#

is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating

system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the

8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed

to level mode for that interrupt.

Table 5-27. System Power Plane

Plane Controlled

By Description

CPU SLP_S3#

signal

The SLP_S3# signal can be used to cut the power to the processor

completely. For mobile/Ultra Mobile systems, the DPRSLPVR

support allows lowering the processor’s voltage during the C4

state.

S3HOT: The new S3HOT state keeps more of the platform logic,

including the Intel® ICH7 core well, powered to reduce the cost of

external power plane logic. SLP_S3# is only used to remove power

to the processor and to shut system clocks. This impact s the board

design, but there is no specific ICH7 bit or strap needed to indicate

which option is selected.

MAIN

SLP_S3#

signal

(S3COLD)

SLP_S4#

signal

(S3HOT)

S3COLD: When SLP_S3# goes active, power can be shut off to any

circuit not required to wake the system from the S3 state. Since

the S3 state requires that the memory context be preserved,

power must be retained to the main memory.

The processor, devices on the PCI bus, LPC I/F, and graphics will

typically be shut off when the Main power plane is shut, although

there may be small subsections powered.

S3HOT: SLP_S4# is used to cut the main power well, rather than

using SLP_S3#. This impacts the board design, but there is no

specific ICH7 bit or strap needed to indicate which option is

selected.

MEMORY

SLP_S4#

signal

SLP_S5#

signal

When the SLP_S4# goes active, power can be shut off to any

circuit not required to wake the system from the S4. Since the

memory context does not need to be preserved in the S4 st ate,

the power to the memory can also be shut down.

When SLP_S5# goes active, power can be shut to any circuit not

required to wake the system from the S5 state. Since the memory

context does not need to be preserved in the S5 state, the power

to the memory c an also be shut.

DEVICE[n] GPIO Individual subsystems may have their own power plane. For

example, GPIO signals may be used to control the power to disk

drives, audio amplifiers, or the display screen.

Intel ® ICH7 Family Datasheet 157

Functional Description

In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or

23. The interrupt polarity changes depending on whether it is on an interrupt shareable

with a PIRQ or not (see Section 10.1.14). The interrupt remains asserted until all SCI

sources are removed.

Table 5-28 shows which events can cause an SMI# and SCI. Note that some ev ents can

be programmed to cause either an SMI# or SCI. The usage of the event for SCI

(instead of SMI#) is typically associated with an ACPI -based system. Each SMI# or SCI

source has a corresponding enable and status bit.

Table 5-28. Causes of SMI# and SCI (Sheet 1 of 2)

Cause1-5 SCI SMI Additional Enables Where Reported

PME# Yes Yes PME_EN=1 PME_STS

PME_B0 (internal EHCI

controller) Yes Yes PME_B0_EN=1 PME_B0_STS

PCI Express* PME Messages

(Desktop and Mobile) Yes Yes PCI_EXP_EN=1

(Not enabled for SMI) PCI_EXP_STS

PCI Express Hot Plug

Message (Desktop and

Mobile) Yes Yes HOT_PLUG_EN=1

(Not enabled for SMI) HOT_PLUG_STS

Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS

Power Button Ov erride 6) Yes No None PRBTNOR_STS

RTC Alarm Yes Yes RTC_EN=1 RTC_STS

Ring Indicate Yes Yes RI_EN=1 RI_STS

AC ’97 wakes (Desktop and

Mobile) Yes Yes AC97_EN=1 AC97_STS

USB#1 wakes Yes Yes U SB1_EN=1 USB1_STS

USB#2 wakes Yes Yes U SB2_EN=1 USB2_STS

USB#3 wakes Yes Yes U SB3_EN=1 USB3_STS

USB#4 wakes Yes Yes U SB4_EN=1 USB4_STS

THRM# pin active Yes Yes THRM_EN=1 THRM_STS

ACPI Timer overflow (2.34

sec.) Yes Yes TMROF_EN=1 TMROF_STS

Any GPI7Yes Yes GPI[x]_Route=10 (SCI)

GPI[x]_Route=01 (SMI)

GPE0[x]_EN=1

GPI[x]_STS

GPE0_STS

TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS

TCO SCI message from

(G)MCH Yes No none MCHSCI_STS

TCO SMI Logic No Yes TCO_EN=1 TCO_STS

TCO SMI — Year 2000

Rollover No Yes none NEWCENTURY_STS

TCO SMI — TCO TIMEROUT No Yes no ne TIMEOUT

TCO SMI — OS writes to

TCO_DAT_IN register No Yes none OS_TCO_SMI

TCO SMI — Message from

(G)MCH No Yes none MCHSMI_STS

Functional Description

158 Intel ® ICH7 Family Datasheet

NOTES:

1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.

2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).

3. GBL_SMI_EN must be 1 to enable SMI.

4. EOS must be written to 1 to re-enable SMI for the next 1.

5. IICH7 must have SMI# fully enabled when ICH7 is also enabled to trap cycles. If SMI# is

not enabled in conjunction with the trap enabling, then hardware behavior is undefined.

6. When a power button override first occurs, the system will transition immediat ely to S5.

The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)

is not cleared prior to setting SCI_EN.

7. Only GPI[15:0] may generate an SMI# or SCI.

TCO SMI — NMI occurred

(and NMIs mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS

TCO SMI — INTRUDER#

signal goes active No Yes INTRD_SEL=10 INTRD_DET

TCO SMI — Change of the

BIOSWP bit from 0 to 1 No Yes BLD=1 BIOSWR_STS

TCO SMI — Write attempted

to BIOS No Yes BIOSWP=1 BIOSWR_STS

BIOS_RLS written to Yes No GBL_EN=1 GBL_STS

GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS

Write to B2h register No Yes APMC_EN = 1 APM_STS

Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS

64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS

Enhanced USB Legacy

Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS

Enhanced USB Intel Specific

Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS

UHCI USB Legacy logic No Yes LEGACY_USB _E N=1 LEGACY_USB_STS

Serial IRQ SMI reported No Yes none SERIRQ_SMI_STS

Device monitors match

address in its range No Yes none DEVMON_STS,

DEVACT_STS

SMBus Host Control le r No Yes SMB_SMI_EN

Host Controller Enabled SMBus host status

reg.

SMBus Slave SMI message No Yes none SMBUS_SMI_STS

SMBus SMBALERT# signal

active No Yes none SMBUS_SMI_STS

SMBus Host Notify message

received No Yes HOST_NOTIFY_INTREN SMBUS_SMI_STS

HOST_NOTIFY_STS

(Mobile/Ultra Mobile Only)

BATLOW# assertion Yes Yes BATLOW_EN=1. BATLOW_STS

Access microcontroller 62h/

66h No Yes MCSMI_EN MCSMI_STS

SLP_EN bit written to 1 No Yes SMI_ON_SLP_EN=1 SMI_ON_SLP_EN_STS

Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2)

Cause1-5 SCI SMI Additional Enables Where Reported

Intel ® ICH7 Family Datasheet 159

Functional Description

5.14.4.1 PCI Express* SCI (Desktop and Mobile Only)

PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using

messages. When a PME message is received, the ICH7 will set the PCI_EXP_STS bit. If

the PCI_EXP_EN bit is also set, the ICH7 can cause an SCI via the GPE1_STS register.

5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only)

PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1

generating a wake event.

5.14.5 Dynamic Processor Clock Control

The ICH7 has extensive control for dynamically starting and stopping system clocks.

The clock control is used for tr ansitions among the v arious S0/Cx states, and processor

throttling. Each dynamic clock control method is described in this section. The various

sleep states may also perform types of non-dynamic clock control.

The ICH7 supports the ACPI C0 and C1 states (in desktop) or C0, C1, C2, C3 and C4 (in

mobile/Ultra Mobile) states.

The Dynamic Processor Clock control is handled using the following signals:

• STPCLK#: Used to halt processor instruction stream.

• (Mobile/Ultra Mobile Only) STP_CPU#: Used to stop processor’s clock

• (Mobile/Ultra Mobile Only) DPSLP#: Used to force Deeper Sleep for processor.

• (Mobile/Ultra Mobile Only) DPRSLPVR: Used to lower voltage of VRM during C4

state.

• (Mobile/Ultra Mobile Only) DPRSTP#: Used to lower voltage of VRM during C4 state

The C1 state is entered based on the processor performing an auto halt instruction.

(Mobile/Ultra Mobile Only) The C2 state is e nte red base d on the processor reading the

Level 2 register in the ICH7. It can also be entered from C3 or C4 states if bus masters

require snoops and the PUME bit (D31:F0: Offset A9h: bit 3) is set.

(Mobile/Ultra Mobile Only) The C3 state is e nte red base d on the processor reading the

Level 3 register in the ICH7 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit

7). This state can also be entered after a temp orary return to C2 from a prior C3 or C4

state.

(Mobile/Ultra Mobile Only) The C4 state is e nte red base d on the processor reading the

Level 4 register in the ICH7, or by reading the Level 3 register when the C4onC3_EN bit

is set. This state can also be entered after a temporary return to C2 from a prior C4

state.

A C1 state in desktop only or a C1, C2, C3, or C4 state in mobile/Ultra Mobile only ends

due to a Break event. Based on the break event, the ICH7 returns the system to C0

state.

(Mobile/Ultra Mobile Only) Table 5-29 lists the possible break events from C2 , C3, or

C4. The break events from C1 are indicated in the processor’s datasheet.

Functional Description

160 Intel ® ICH7 Family Datasheet

5.14.5.1 Transition Rules among S0/Cx and Throttling States

The following priority rules and assumptions apply among the various S0/Cx and

throttling states:

• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This

is because the processor can only perform one register access at a time and Sleep

states have higher priority than thermal throttling.

• When the SLP_EN bit is set (system going to a S1–S5 sleep state), the THTL_EN

and FORCE_THTL bits can be internally treated as being disabled (no throttling

while going to sleep state).

• (Mobile/Ultra Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level

2, Level 3, or Level 4 read then occurs, the system should immediately go and sta y

in a C2, C3, or C4 state until a break event occurs. A Level 2, Level 3, or Level 4

read has higher priority than the software initiated throttling.

• (Mobile/Ultra Mobile Only) After an exit from a C2, C3, or C4 state (due to a Break

event), and if the THTL_EN or FORCE_THTL bits are still set the system will

continue to throttle STPCLK#. Depending on the time of break event, the first

transition on STPCLK# active can be delayed by up to one THRM period (1024 PCI

clocks = 30.72 µs).

• The Host controller must post Stop-Grant cycles in such a way that the processor

gets an indication of the end of the special cycle prior to the ICH7 observing the

Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a

sufficient period after the processor observes the response phase.

• (Mobile/Ultra Mobile Only) If in the C1 state and the STPCLK# signal goes active,

the processor will generate a Stop-Gr ant cycle, and the system should go to the C2

state. When STPCLK# goes inactive, it should return to the C1 state.

Table 5-29. Break Events (Mobile/Ultra Mobile Only)

Event Breaks

from Comment

Any unmasked interrupt goes

active C2, C3, C4 IRQ[0:15] when using the 8259s, IRQ[0:23]

for I/O APIC. Since SCI is an interrupt, any SCI

will also be a break event.

Any internal event that cause an

NMI or SMI# C2, C3, C4 Many possible sources

Any internal event that cause

INIT# to go active C2, C3, C4 Could be indicated by the keyboard controller

via the RCIN inpu t signal.

Any bus master request

(internal, external or DMA, or

BM_BUSY#) goes active and

BM_RLD=1 (D31:F0:Offset

PMBASE+04h: bit 1)

C3, C4

Need to wake up processor so it can do snoops

NOTE: If the PUME bit (D31 :F0: Offset A9h: bit

3) is set, then bus master activity will

NOT be treated as a break event.

Instead, there will be a return only to

the C2 state.

Processor Pending Break Event

Indication C2, C3, C4 Only available if FERR# enabled for break event

indication (See FERR# Mux Enable in GCS,

Chipset Config Registers:Offset 3410h:bit 6)

Intel ® ICH7 Family Datasheet 161

Functional Description

5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only)

Due to the new DMI protocol, if there is any bus master activity (other than true isoch),

then the C0-to-C3 transition will pause at the C2 state. ICH7 will keep the processor in

a C2 state until:

• ICH7 does not detect bus master activity.

• A break event occurs. In this case, the ICH7 will perform the C2 to C0 sequence.

Note that bus master traffic is not a break event in this case.

To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be

set. This will cause the BM_STS bit to read as 0 even if some bus master activity is

present. If this is not done, then the software may avoid even attempting to go to the

C3 or C4 state if it sees the BM_STS bit as 1.

If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH7 will treat bus master

activity as a break event. When reaching the C2 state, if there is any bus master

activity, the ICH7 will return the processor to a C0 state.

5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only)

When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH7 enables a mode of

operation where standard (non-isoch) bus master activity will not be treated as a full

break event from the C3 or C4 states. Instead, these will be treated merely as bus

master events and return the platform to a C2 state, and thus allow snoops to be

performed.

After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even

if the ARB_DIS bit is set.

5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only)

After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)

is set, the platform can return to a C3 or C4 state (depending on where it was prior to

going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will

keep the processor in a C2 state until:

• Bus masters are no longer active.

• A break event occurs. Note that bus master traffic is not a break event in this case.

5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)

The PCI clock can be dynamically controlled independent of any other low -power state.

This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile

Design Guide, and is transparent to software.

The Dynamic PCI Clock control is handled using the following signals:

• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run

• STP_PCI#: Used to stop the system PCI clock

Note: The 33 MHz clock to the ICH7 is “free-running” and is not affected by the STP_PCI#

signal.

Functional Description

162 Intel ® ICH7 Family Datasheet

5.14.6.1 Conditions for Checking the PCI Clock

When there is a lack of PCI activity the ICH7 has the capability to stop the PCI clocks to

conserve power. “PCI activity” is define d as any activity that would require the PCI

clock to be running.

Any of the following conditions will indicate that it is not okay to stop the PCI clock:

• Cycles on PCI or LPC

• Cycles of any internal device that would need to go on the PCI bus

•SERIRQ activity

Behavioral Description

• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH7

deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.

5.14.6.2 Conditions for Maintaining the PCI Clock

PCI masters or LPC devices that wish to maintain the PCI clock running will observ e the

CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.

• When the ICH7 has tri-stated the CLKRUN# signal after deasserting it, the ICH7

then checks to see if the signal has been re-asserted (externally).

• After observing the CLKRUN# signal asserted for 1 clock, the ICH7 again starts

asserting the signal.

• If an internal device needs the PCI bus, the ICH7 asserts the CLKRUN# signal.

5.14.6.3 Conditions for Stopping the PCI Clock

• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,

the ICH7 stops the PCI clock by asserting the STP_PCI# signal to the clock

synthesizer.

5.14.6.4 Conditions for Re-Starting the PCI Clock

• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.

• When the ICH7 observes the CLKRUN# signal asserted for 1 (free running) clock,

the ICH7 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free

running) clocks.

• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the

ICH7 again starts driving CLKRUN# asserted.

If an internal source requests the clock to be re-started, the ICH7 re-asserts CLKRUN#,

and simultaneously deasserts the STP_PCI# signal.

5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only)

If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA (Mobile

only) or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices

running DMA or bus master cycles will not need to assert CLKRUN#, since the ICH7

asserts it on their behalf.

The LDRQ# in puts are ignored by the ICH 7 when the PCI clock is stopped to the LPC

devices in order to avoid misinterpreting the request. The ICH7 assumes that only one

more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.

Upon deassertion of STP_PCI#, the ICH7 assumes that the LPC device receives its first

clock rising edge corresponding to the ICH7’s second PCI clock rising edge after the

deassertion.

Intel ® ICH7 Family Datasheet 163

Functional Description

5.14.7 Sleep States

5.14.7.1 Sleep State Overview

The ICH7 directly supports different sleep states (S1–S5) that are entered by setting

the SLP_EN bit, or due to a P ower Button press. The entry to the Sleep states are based

on several assumptions:

• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because

the processor can only perform one register access at a time. A request to Sleep

has higher priority than throttling.

• Prior to setting the SLP_EN bit, the software turns off processor-controlled

throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN

bit disables thermal throttling (since S1–S5 sleep state has higher priority).

• The G3 state cannot be entered via any software mechanism. The G3 state

indicates a complete loss of power.

5.14.7.2 Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type

in the SLP_TYP field, and then setting the SLP_EN bit. The hardw are then attempts

to gracefully put the system into the corresponding Sleep state.

• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button

Override event. In this case the transition to the S5 state is less graceful, since

there are no dependencies on obse rving Stop-Grant cycles from the processor or

on clocks other than the RTC clock.

5.14.7.3 Exiting Sleep States

Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the

system to a full on state (S0), although some non-critical subsystems might still be

shut off and have to be brought back manually. For example, the hard disk may be shut

off during a sleep state, and have to be enabled via a GPIO pin before it can be used.

Upon exit from the ICH7-controlled Sleep states, the WAK_STS bit is set. The possible

causes of Wake Events (and their restrictions) are shown in Table 5-31.

Note: (Mobile/Ultra Mobile Only) If the BA TL OW# signal is asserted, ICH7 does not attempt to

wake from an S1–S5 state, even if the power button is pressed. This prevents the

system from waking when the battery power is insufficient to wake the system. Wake

events that occur while BATLOW# is asserted are latched by the ICH7, and the system

wakes after BATLOW# is de-asserted.

Table 5-30. Sleep Types

Sleep

Type Comment

S1 Intel® ICH7 asserts the STPCLK# signal. It also has the option to assert CPUSLP#

signal (only supported on desktop platforms). This lowers the processor’s power

consumption. No snooping is possible in this state.

S3 ICH7 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical

circuits. P ower is only retai ned to devices needed to wake from this sleeping state,

as well as to the memory.

S4 ICH7 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to

the memory subsystem. Only devices needed to wake from this state should be

powered.

S5 Same power state as S4. ICH7 asserts SLP_S3#, SLP_S4# and SLP_S5#.

Functional Description

164 Intel ® ICH7 Family Datasheet

NOTES:

1. If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events

are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in

Table 5-55), and Hard Reset System (See Command Type 4 in Table 5-55).

2. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and

SLP_TYP bits via software, or if there is a power failure.

3. When the WAKE# pin is active and the PCI Ex press device is enabled to wake the system,

the ICH7 will wake the platform.

Table 5-31. Causes of Wake Events

Cause States Can

Wake From1How Enabled

RTC Alarm S1–S52Set RTC_EN bit in PM1_EN register

Power Button S1–S5 Always enabled as Wake event

GPI[0:15] S1–S52

GPE0_EN register

NOTE: GPIs that are in th e core well are not capable of waking

the system from sleep states where the core well is not

powered.

Classic USB S1–S5 Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in

GPE0_EN register

LAN

(Desktop and

Mobile only) S1–S5 Will use PME#. Wake enable set with LAN logic.

RI# S1–S52Set RI_EN bit in GPE0_E N register

AC ‘97 / Intel®

High Definition

Audio S1–S52Set AC97_EN bit in GPE0_EN register

Primary PME# S1–S5 PME_B0_EN bit in GPE0_EN register

Secondary PME# S1–S5 Set PME_EN bit in GPE0_EN register.

PCI_EXP_WAKE#

(Desktop and

Mobile only) S1–S5 PCI_EXP_WAKE bit3

PCI_EXP PME

Message

(Desktop and

Mobile only)

S1 Must use the PCI Express* WAKE# pin rather than messages

for wake from S3,S4, or S5.

SMBALERT# S1–S5 Always enabled as Wake event

SMBus Slave

Message S1–S5 Wake/SMI# command always enabled as a Wake event.

Note: SMBus Slave M essage can wake the system from S1–

S5, as well as from S5 due to Power Button Override.

SMBus Host

Notify mes s age

received S1–S5 HOST_NOTIFY_WKEN bit SMBus Slave Command register.

Report ed in the SM B_ WAK_ST S bit in the GPE O_STS register.

Intel ® ICH7 Family Datasheet 165

Functional Description

It is important to understand that the various GPIs hav e different levels of functionality

when used as wake events. The GPIs that reside in the core power well can only

generate wake events from sleep states where the core well is powered. Also, only

certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in

ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events.

The latency to exit the various Sleep states varies greatly and is heavily dependent on

power supply design, so much so that the exit latencies due to the ICH7 are

insignificant.

5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (Desktop and

Mobile only)

PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using

the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go

active in the GPE_STS register.

PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using

messages. When a PME message is received, ICH7 will set the PCI_EXP_STS bit.

5.14.7.5 Sx-G3-Sx, Handling Power Failures

Depending on when the power failure occurs and ho w the system is designed, different

transitions could occur due to a power failure.

The AFTER_G3 bit provides the ability to program whether or not the system should

boot once power returns after a power loss event. If the policy is to not boot, the

system remains in an S5 state (unless previously in S4). There are only three possible

events that will wake the system after a power failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the ICH7 exits G3 after power

returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-

standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a

wake event, it is important to keep this signal powered during the power loss

event. If this signal goes low (active), when power returns the RI_STS bit is set and

the system interprets that as a wake event.

3. RTC Alarm: The RT C_EN bit is in the R TC well and is preserved after a power loss.

Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

The ICH7 monitors both PWROK and RSMRST# to detect for power failures. If PWROK

goes low, the PWRO K_FL R bit is set. If RSMRST # goe s low, PWR_FLR is set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power

loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.

Table 5-32. GPI Wake Events

GPI Power Well Wake From Notes

GPI[12, 7:0] Core S1 ACPI

Compliant

GPI[15:13,11:8] Resume S1–S5 ACPI

Compliant

Functional Description

166 Intel ® ICH7 Family Datasheet

5.14.8 Thermal Management

The ICH7 has mechanisms to assist with managing thermal problems in the system.

5.14.8.1 THRM# Signal

The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#

signal going active, the ICH7 generates an SMI# or SCI (depending on SCI_EN).

If the THRM_POL bit is set low, when the THRM# signal goes low , the THRM_STS bit

will be set. This is an indicator that the thermal threshold has been exceeded. If the

THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be

generated (depending on the SCI_EN bit being set).

The power management software (BIOS or ACPI) can then take measures to start

reducing the temperature. Examples include shutting off unwanted subsystems, or

halting the processor.

By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated

when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to

turn off the cooling methods.

Note: THRM# assertion does not cause a TCO event message in S3 or S4. The level of the

signal is not reported in the heartbeat message.

5.14.8.2 Processor Initiated Passive Cooling

This mode is initiated by software setting the THTL_EN (PMBASE+10h:bit 4) or

FORCE_THTL (PMBASE+10h:bit 8) bits.

Software sets the THTL_DTY (PMBASE+10h:bits 3:1) or THRM_DTY (PMBASE+10h:bits

7:5) bits to select throttle ratio and THTL_EN or FORCE_THTL bits to enable the

throttling.

Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of

87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as

little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and

cooling) of the processor depends on the instruction stream, because the processor is

allowed to finish the current instruction. Furthermore, the ICH7 waits for the STOP-

GRANT cycle before starting the count of the time the STPCLK# signal is active.

Table 5-33. Transitions Due to Power Failure

State at Power Failure AFTERG3_EN bit Transition When Power Returns

S0, S1, S3 1

0S5

S4 1

0S4

S5 1

0S5

Intel ® ICH7 Family Datasheet 167

Functional Description

5.14.8.3 THRM# Overrid e Software Bit

The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI

software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH7

starts throttling using the ratio in the THRM_DTY field.

When this bit is cleared the ICH7 stops throttling, unless the THTL_EN bit is set

(indicating that ACPI software is attempting throttling).

If both the THTL_EN and FORCE_THTL bits are set, then the ICH7 should use the duty

cycle defined by the THRM_DTY field, not the THTL_DTY field.

5.14.8.4 Active Cooling

Active cooling involves fans. The GPIO signals from the ICH7 can be used to turn on/off

a fan.

5.14.9 Event Input Signals and Their Usage

The ICH7 has various input signals that trigger specific events. This section describes

those signals and how they should be used.

5.14.9.1 PWRBTN# (Power Button)

The ICH7 PWRBTN# signal operates as a “Fixed Power Button” as described in the

Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16

ms de-bounce on the input. The state transition descriptions are included in Table 5-34.

Note that the transitions start as soon as the PWRBTN# is pressed (but after the

debounce logic), and does not depend on when the Power Button is released.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled), the Power Button is not a wake event. Refer to Power Button Override

Function section below for further detail.

Table 5-34. Transitions Due to Power Button

Present

State Event Transition/Action Comment

S0/Cx PWRBTN# goes low SMI# or SCI generated

(depending on SCI_EN) Software typically initiates a

Sleep state

S1–S5 P WRBTN# goes low Wake Event. Transitions to

S0 state Standar d wake up

G3 PWRBTN# pressed None No effect since no power

Not latched nor detected

S0–S4 PWRBTN# held low

for at least 4

consecutive seconds

Unconditional transition to

S5 state

No dependence on processor

(e.g., Stop-Grant cycles) or

any othe r subsystem

Functional Description

168 Intel ® ICH7 Family Datasheet

Power Button Override Function

If PWRBTN# is observ ed active for at least four consecutive seconds, the state machine

should unconditionally transition to the G2/S5 state, regardless of present state (S0–

S4), even if PWROK is not active. In this case, the transition to the G2/S5 state sho uld

not depend on any particular response from the processor (e.g., a Stop-Grant cycle),

nor any similar dependency from any other subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or

has been released. The status is taken after the de-bounce, and is readable via the

PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has

occurred. The

4-second timer starts counting when the ICH7 is in a S0 state. If the PWRBTN# signal

is asserted and held active when the system is in a suspend state (S1–S5), the

assertion causes a wake event. Once the system has resumed to the S0 state, the 4-

second timer starts.

Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width

(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it

is conceivable that the user will press and continue to hold the P ower Button waiting for

the system to awake. Since a

4-second press of the Power Button is already defined as an Unconditional Power down ,

the power button timer will be forced to inactive while the power-cycle timer is in

progress. Once the

power-cycle timer has expired, the Power Button awakes the system. Once the

minimum SLP_S4# power cycle expires, the P ower Button must be pressed for another

4 to 5 seconds to create the Override condition to S5.

Sleep Button

The Advanced Configuration and Power Interface, Version 2.0b defines an optional

Sleep button. It differs from the power button in that it only is a request to go from S0

to S1–S4 (not S5). Also , in an S5 state, the Power Button can wak e the system, but the

Sleep Button cannot.

Although the ICH7 does not include a specific sign al designated as a Sleep Button, one

of the GPIO signals can be used to create a “Control Method” Sleep Button. See the

Advanced Configuration and Power Interface, Version 2.0b for implementation details.

5.14.9.2 RI# (Ring Indicator)

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.

Table 5-35 shows when the wake event is generated or ignored in different states. If in

the G0/S0/Cx states, the ICH7 generates an interrupt based on RI# active, and the

interrupt will be set up as a Break event.

Note: Filtering/Debounce on RI# will not be done in ICH7. It can be in modem or external.

Table 5-35. Transitions Due to RI# Signal

Present State Event RI_EN Event

S0 RI# Active X Ignored

S1–S5 RI# Active 0

1Ignored

Wake Event

Intel ® ICH7 Family Datasheet 169

Functional Description

5.14.9.3 PME# (PCI Power Management Event)

The PME# signal comes from a PCI device to request that the system be restarted. The

PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs

when the PME# signal goes from high to low. No event is caused when it goes from low

to high.

There is also an internal PME_B0 bit. This is separate from the external PME# signal

and can cause the same effect.

5.14.9.4 SYS_RESET# Signal

When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the

ICH7 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to

go idle. If the SMBus is idle when the pin is detected active, the reset occurs

immediately; otherwise, the counter starts. If at an y point during the count the SMBus

goes idle the reset occurs. If , however, the counter expires and the SMBus is still active,

a reset is forced upon the system even though activity is still occurring.

Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the

SYSRESET# input r emains asserted or not. It cannot occur again until SYS_RESET#

has been detected inactive after the debounce logic, and the system is back to a full S0

state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then

SYS_RESET# will result in a full power cycle reset.

5.14.9.5 THRMTR IP# Signal

If THRMTRIP# goes active, the processor is indicating an overheat condition, and the

ICH7 immediately transitions to an S5 state. However, since the processor has

overheated, it does not respond to the ICH7’s STPCLK# pin with a stop grant special

cycle. Therefore, the ICH7 does not wait for one. Immediately upon seeing THRMTRIP#

low , the ICH7 initiates a tr ansition to the S5 state, driv e SLP_ S3#, SLP_S4 #, SLP_S5 #

low, and set the CTS bit. The transition looks like a power button override.

It is extremely important that when a THRMTRIP# event occurs, the ICH7 power down

immediately without following the normal S0 -> S5 path. This path may be taken in

parallel, but ICH7 must immediately enter a power down state. It does this by driving

SLP_S3#, SLP_S4#, and SLP_S5# imme diately after sampling THRMTRIP# active.

If the processor is running extremely hot and is heating up, it is possible (although v ery

unlikely) that components around it, such as the ICH7, are no longer executing cycles

properly. Therefore, if THRMTRIP# goes active, and the ICH7 is relying on state

machine logic to perform the power down, the state machine may not be working, and

the system will not power down.

The ICH7 follows this flow for THRMTRIP#.

1. At boot (PLTRST# low), THR MTRIP# ignored.

2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,

SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts.

3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay

active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the

thermal trip event.

4. If S5 state reached, go to step #1, otherwise stay here. If the ICH7 does not reach

S5, the ICH7 does not reboot until power is cycled.

Functional Description

170 Intel ® ICH7 Family Datasheet

During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and

PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry,

power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or

PWROK = 0, or VRMPWRGD/VGATE = 0.

Note: A thermal trip event will:

• Set the AFTERG3_EN bit

• Clear the PWRBTN_STS bit

• Clear all the GPE0_EN register bits

• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave

receiving message and not set due to SMBAlert

5.14.9.6 BM_BUSY# (Mobile/Ultra Mobile Only)

The BM_BUSY# signal is an input from a graphics component to indicate if it is busy. If

prior to going to the C3 state, the BM_BUSY# signal is active, then the BM_STS bit will

be set. If after going to the C3 state, the BM_BUSY# signal goes back active, the ICH7

will treat this as if one of the PCI REQ# signals went active. This is treated as a break

event.

5.14.10 ALT Access Mode

Before entering a low power state, several registers from powered down parts may

need to be saved. In the majority of cases, this is not an issue, as registers have read

and write paths. However, several of the ISA compatible registers are either read only

or write only. To get data out of

write-only registers, and to restore data into read-only registers, the ICH7 implements

an ALT access mode.

If the ALT access mode is entered and exited after reading the registers of the ICH7

timer (8254), the timer starts counting faster (13.5 ms). The following steps listed

below can cause problems:

1. BIOS enters ALT access mode for reading the ICH7 timer related registers.

2. BIOS exits ALT access mode.

3. BIOS continues through the execution of other needed steps and passes control to

the operating system.

After getting control in step #3, if the operating system does not reprogr am the system

timer again, the timer ticks may be happening faster than expected. For example DOS

and its associated software assume that the system timer is running at 54.6 ms and as

a result the time-outs in the software may be happening faster than expected.

Operating systems (e.g., Microsoft Windows* 98, Windows* 2000, and Windows NT*)

reprogram the system timer and therefore do not encounter this problem.

For some other loss (e.g., Microsoft MS-DOS*) the BIOS should restore the timer back

to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT

access mode before entering the suspend state it is not necessary to restore the timer

contents after the exit from ALT access mode.

Intel ® ICH7 Family Datasheet 171

Functional Description

5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode

The registers described in Table 5-36 have read paths in ALT access mode. The access

number field in the table indicates which register will be returned per access to that

port.

Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)

Restore Data Restore Data

I/O

Addr # of

Rds Access Data I/O

Addr # of

Rds Access Data

00h 2 1DMA Chan 0 base address low

byte

40h 7

1Timer Counter 0 status, bits

[5:0]

2DMA Chan 0 base address high

byte 2Timer Counter 0 base count

low byte

01h 2 1DMA Chan 0 base count low

byte 3Timer Counter 0 base count

high byte

2DMA Chan 0 base count high

byte 4Timer Counter 1 base count

low byte

02h 2 1DMA Chan 1 base address low

byte 5Timer Counter 1 base count

high byte

2DMA Chan 1 base address high

byte 6Timer Counter 2 base count

low byte

03h 2 1DMA Chan 1 base count low

byte 7Timer Counter 2 base count

high byte

2DMA Chan 1 base count high

byte 41h 1 Timer Counter 1 status, bits

[5:0]

04h 2 1DMA Chan 2 base address low

byte 42h 1 Timer Counter 2 status, bits

[5:0]

2DMA Chan 2 base address high

byte 70h 1 Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

05h 2 1DMA Chan 2 base count low

byte C4h 2 1DMA Chan 5 base address low

byte

2DMA Chan 2 base count high

byte 2DMA Chan 5 base address

high byte

06h 2 1DMA Chan 3 base address low

byte C6h 2 1DMA Chan 5 base count low

byte

2DMA Chan 3 base address high

byte 2DMA Chan 5 base count high

byte

07h 2 1DMA Chan 3 base count low

byte C8h 2 1DMA Chan 6 base address low

byte

2DMA Chan 3 base count high

byte 2DMA Chan 6 base address

high byte

Functional Description

172 Intel ® ICH7 Family Datasheet

NOTES:

1. Bits 5, 3, 1, and 0 return 0.

2. The OCW1 register must be read before entering ALT access mode.

08h 6

1 DMA Chan 0–3 Command2

CAh 2 1DMA Chan 6 base count low

byte

2 DMA Chan 0–3 Request 2 DMA Chan 6 base count high

byte

3DMA Chan 0 Mode:

Bits(1:0) = 00 CCh 2 1DMA Chan 7 base address low

byte

4DMA Chan 1 Mode:

Bits(1:0) = 01 2DMA Chan 7 base address

high byte

5DMA Chan 2 Mode:

Bits(1:0) = 10 CEh 2 1DMA Chan 7 base count low

byte

6DMA Chan 3 Mode: Bits(1:0)

= 11. 2DMA Chan 7 base count high

byte

20h 12

1 PIC ICW2 of Master controller

D0h 6

1 DMA Chan 4–7 Command1

2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request

3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode: Bits(1:0)

= 00

4PIC OCW1 of Master

controller24DMA Chan 5 Mode: Bits(1:0)

= 01

5 PIC OCW2 of Master controller 5 DMA Chan 6 Mode: Bits(1:0)

= 10

6 PIC OCW3 of Master controller 6 DMA Chan 7 Mode: Bits(1:0)

= 11.

7 PIC ICW2 of Slave controller

8 PIC ICW3 of Slave controller

9 PIC ICW4 of Slave controller

10 PIC OCW1 of Slave controller1

11 PIC OCW2 of Slave controller

12 PIC OCW3 of Slave controller

Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)

Restore Data Restore Data

I/O

Addr # of

Rds Access Data I/O

Addr # of

Rds Access Data

Intel ® ICH7 Family Datasheet 173

Functional Description

5.14.10.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must ha ve certain values written in order for

the PIC to operate properly. Therefore, there is no need to return these values in ALT

access mode. When reading PIC registers from 20h and A0h, the reserved bits shall

return the values listed in Table 5-37.

5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode

The registers described in Table 5-38 have write paths to them in ALT access mode.

Software restores these values after returning from a powered down state. These

registers must be handled special by software. When in normal mode, writing to the

base address/count register also writes to the current address/count register.

Therefore, the base address/count must be written first, then the part is put into ALT

access mode and the current address/count register is written.

5.14.11 System Power Supplies, Planes, and Signals

5.14.11.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#

The usage of SLP_S3# and SLP_S4# depends on whether the platform is configured for

S3HOT and S3COLD.

S3HOT

The SLP_S3# output signal is used to cut power only to the processor and associated

subsystems and to optionally stop system clocks.

S3COLD

The SLP_S3# output signal can be used to cut power to the system core supply, since it

only goes active for the STR state (typically mapped to ACPI S3). Power must be

maintained to the ICH7 resume well, and to any other circuits that need to generate

Wake signals from the STR state.

Table 5-37. PIC Reserved Bits Return Values

PIC Reserved Bits Value Returned

ICW2(2:0) 000

ICW4(7:5) 000

ICW4(3:2) 00

ICW4(0) 0

OCW2(4:3) 00

OCW3(7) 0

OCW3(5) Reflects bit 6

OCW3(4:3) 01

Table 5-38. Register Write Accesses in ALT Access Mode

I/O Address Register Write V alue

08h DMA Status Register for channels 0–3.

D0h DMA Status Register for channels 4–7.

Functional Description

174 Intel ® ICH7 Family Datasheet

Cutting power to the core may be done via the power supply, or by external FETs to the

motherboard.

The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core

supply, as well as power to the system memory, since the context of the system is

saved on the disk. Cutting power to the memory may be done via the power supply, or

by external FETs to the motherboard.

The SLP_S4# output signal is used to remove power to additional subsystems th at are

powered during SLP_S3#.

SLP_S5# output signal can be used to cut power to the system core supply, as well as

power to the system memory, since the context of the system is saved on the disk.

Cutting power to the memory may be done via the power supply, or by external FETs to

the motherboard.

5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing

The system memory suspend voltage regulator is controlled by the Glue logic. The

SLP_S4# signal should be used to remove power to system memory rather than the

SLP_S5# signal. The SLP_S4# logic in the ICH7 provides a mechanism to fully cycle

the power to the DRAM and/or detect if the power is not cycled for a minimum time.

Note: To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#

Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled

by the SLP_S4# signal.

5.14.11.3 PWRO K Signal

The PWROK input should go active based on the core supply voltages becoming valid.

PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached

their nominal values.

Note:

1. SYSRESET# is recommended for implementing the system reset button. This saves

external logic that is needed if the PWROK input is used. Additionally, it allows for

better handling of the SMBus and processor resets, and avoids improperly

reporting power failures.

2. If the PWROK input is used to implement the system reset button, the ICH7 does

not provide any mechanism to limit the amount of time that the processor is held in

reset. The platform must externally ensure that maximum reset assertion

specifications are met.

3. If a design has an active-low reset button electrically AND’d with the PWROK signal

from the power supply and the processor’s voltage regulator module the ICH7

PWROK_FLR bit will be set. The ICH7 treats this internally as if the RSMRST# signal

had gone active. However, it is not treated as a full power failure. If PWROK goes

inactive and then active (but RSMRST# stays high), then the ICH7 reboots

(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low

before PWROK goes high, then this is a full power failure, and the reboot policy is

controlled by the AFTERG3 bit.

4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that

are less than one RTC clock period may not be detected by the ICH7.

5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.

Intel ® ICH7 Family Datasheet 175

Functional Description

5.14.11.4 CPUPWRGD Signal

This signal is connected to the processor’s VRM via the VRMPWRGD signal and is

internally AND’d with the PWROK signal that comes from the system power supply.

5.14.11.5 VRMPWRGD Signal

VRMPWRGD is an input from the regulator indicating that all of the outputs from the

regulator are on and within specification. VRMPWRGD may go active before or after the

PWROK from the main power supply. ICH7 has no dependency on the order in which

these two signals go active or inactive.

5.14.11.6 BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)

The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not

sufficient power. It also causes an SMI# if the system is already in an S0 state.

5.14.11.7 Controlling Leakage and Power Consumption

during Low-Power States

To control leakage in the system, various signals tri-state or go low during some low-

power states.

General principles:

• All signals going to powered down planes (either internally or externally) must be

either tri-stated or driven low.

• Signals with pull-up resistors should not be low during low-power states. This is to

avoid the power consumed in the pull-up resistor.

• Buses should be halted (and held) in a known state to avoid a floating input

(perhaps to some other device). Floating inputs can cause extra power

consumption.

Based on the above principles, the following measures are taken:

• During S3 (STR), all signals attached to powered down planes are tri-stated or

driven low.

Functional Description

176 Intel ® ICH7 Family Datasheet

5.14.12 Clock Generators

The clock generator is expected to provide the frequencies shown in Table 5-39.

5.14.12.1 Clock Control Signals from Intel® ICH7 to Clock

Synthesizer (Mobile/Ultra Mobile Only)

The clock generator is assumed to have a direct connection from the following ICH7

signals:

• STP_CPU#: Stops processor clocks in C3 and C4 states

• STP_PCI#: Stops system PCI clocks (not the ICH7 free-running 33 MHz clock) due

to CLKRUN# protocol

• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop

clocks in S3HOT and on the way to S3COLD to S5.

Table 5-39. Intel® ICH7 Clock Inputs

Clock

Domain Frequency Source Usage

SATA_CLK

(Desktop and

Mobile Only)

100 MHz

Differential Main Clock

Generator Used by SATA controller. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

DMI_CLK 100 MHz

Differential Main Clock

Generator Used by DMI and PCI Express*. Stopped in S3 ~ S5

based on SLP_S3# assertion.

PCICLK 33 MHz Main Clock

Generator

Desktop Only: Free-running PCI Clock to Intel® ICH7.

Stopped in S3 ~ S5 based on SLP_S3# assertion.

Mobile Only: Free-running (not affected by STP_PCI#

PCI Clock to ICH7. This is not the system PCI clock.

This clock must keep running in S0 while the system

PCI clock may stop based on CLKRUN# protocol.

Stopped in S3 ~ S5 based on SLP_S3# assertion.

CLK48 48.000

MHz Main Clock

Generator

Used by USB controllers and Int el® High Definition

Audio controller. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

CLK14 14.318

MHz Main Clock

Generator Used by ACPI timers. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

ACZ_BIT_CLK

(Desktop and

Mobile)

12.288

MHz AC ’97

Codec

AC-link. Control policy is determined by the clock

source.

NOTE: Becomes clock output when Intel High

Definition Audio is enabled.

LAN_CLK

(Desktop and

Mobile Only)

0.8 to

50 MHz LAN

Connect LAN Connect Interface. Control policy is determined by

the clock source.

Intel ® ICH7 Family Datasheet 177

Functional Description

5.14.13 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various

hardware mechanisms. The scheme relies on the concept of detecting when individual

subsystems are idle, detecting when the whole system is idle, and detecting when

accesses are attempted to idle subsystems.

However, the operating system is assumed to be at least APM enabled. Without APM

calls, there is no quick way to know when the system is idle between keystrokes. The

ICH7 does not support burst modes.

5.14.13.1 APM Power Management (Desktop Only)

The ICH7 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and

Enable register, generates an SMI# once per minute. The SMI handler can check for

system activity by reading the DEVA CT_STS register. If none of the system bits are set,

the SMI handler can increment a software counter. When the counter reaches a

sufficient number of consecutiv e minutes with no activity, the SMI handler can then pu t

the system into a lower power state.

If there is activity, various bits in the DEVACT_STS register will be set. Software clears

the bits by writing a 1 to the bit position.

The DEVACT_STS register allows for monitoring various internal devices, or Super I/O

devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions

on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.

5.14.13.2 Mobile APM Power Management (Mobile/Ultra Mobile Only)

In mobile/ultra mobile systems, there are additional requirements associated with

device power management. To handle this, the ICH7 has specific SMI# traps available.

The following algorithm is used:

1. The periodic SMI# timer checks if a device is idle for the required time. If so, it puts

the device into a low-power state and sets the associated SMI# trap.

2. When software (n ot the SMI# handler) attempts to access the device, a tr ap occurs

(the cycle does not really go to the device and an SMI# is generated).

3. The SMI# handler turns on the device and turns off the trap

The SMI# handler exits with an I/O restart. This allows the original software to

continue.

Functional Description

178 Intel ® ICH7 Family Datasheet

5.15 System Management (D31:F0)

The ICH7 provides various functions to make a system easier to manage and to lower

the Total Cost of Ownership (TCO) of the system. In addition, ICH7 provides integr ated

ASF Management support. Features and functions can be augmented via external A/D

converters and GPIO, as well as an external microcontroller.

The following features and functions are supported by the ICH7:

• Processor present detection

— Detects if processor fails to fetch the first instruction after reset

• Various Error detection (such as ECC Errors) Indicated by host controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed

— INTRUDER# allowed to go active in any power state, including G3

• Detection of bad Firmware Hub programming

— Detects if data on first read is FFh (indicates unprogrammed Firmware Hub)

• Ability to hide a PCI device

— Allows software to hide a PCI device in terms of configuration space through

the use of a device hide register (See Section 7.1.56)

• Integrated ASF Management support (Desktop and Mobile Only)

Note: Voltage ID from the processor can be read via GPI signals.

5.15.1 Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management

functionality be provided without the aid of an external microcontroller.

5.15.1.1 Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor

fails to fetch the first instruction after reset, the TCO timer times out twice and the

ICH7 asserts PLTRST#.

5.15.1.2 Handling an Intruder

The ICH7 has an input signal, INTRUDER#, that can be attached to a switch that is

activated by the system’ s case being open. This input has a two R TC clock debounce. If

INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the

TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH7 to

cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition

to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by

clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI

if the intruder function is not required.

Intel ® ICH7 Family Datasheet 179

Functional Description

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written

as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes

inactive. Note that this is slightly different than a classic sticky bit, since most sticky

bits would remain active indefinitely when the signal goes active and would

immediately go inactive when a 1 is written to the bit.

Note: The INTRD_DET bit resides in the ICH7’s RTC well, and is set and cleared

synchronously with the RTC clock. Thus, when softw are attem pts to clear INTRD_DET

(by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65

µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be

asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set.

Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET

bit, the bit remains set and the SMI is generated again immediately. The SMI handler

can clear the INTRD_SEL bits to avoid further SMIs. Howev er, if the INTRUDER# signal

goes inactive and then active again, there will not be further SMIs, since the

INTRD_SEL bits would select that no SMI# be generated.

5.15.1.3 Detecting Improper Firmware Hub Programming

The ICH7 can detect the case where the Firmware Hub is not programmed. This results

in the first instruction fetched to have a value of FFh. If this occurs, the ICH7 sets the

BAD_BIOS bit, which can then be reported via the Heartbeat and Event reporting using

an external, Alert on LAN* enabled LAN controller (See Section 5.15.2).

5.15.2 Heartbeat and Event Reporting via SMBus (Desktop and

Mobile Only)

The ICH7 integrated LAN controller supports ASF heartbeat and event reporting

functionality when used with the 82562EM or 82562EX Platform LAN Connect

component. This allows the integrated LAN controller to report messages to a network

management console without the aid of the system processor. This is crucial in cases

where the processor is malfunctioning or cannot function due to being in a low-power

state.

All heartbeat and event messages are sent on the SMBus interface. This allows an

external LAN controller to act upon these messages if the internal LAN controller is not

used.

The basic scheme is for the ICH7 integrated LAN controller to send a prepared Ethernet

message to a network management console. The prepared message is stored in the

non-volatile EEPROM that is connected to the ICH7.

Messages are sent by the LAN controller either because a specific event has occurred,

or they are sent periodically (also known as a heartbeat). The event and heartbeat

messages have the exact same format. The event messages are sent based on events

occurring. The heartbeat messages are sent every 30 to 32 seconds. When an event

occurs, the ICH7 sends a new message and increments the SEQ[3:0] field. For

heartbeat messages, the sequence number does not increment.

Functional Description

180 Intel ® ICH7 Family Datasheet

The following rules/steps apply if the system is in a G0 state and the policy is for the

ICH7 to reboot the system after a hardware lockup:

1. On detecting the lockup, the SECOND_TO_STS bit is set. The ICH7 may send up to

1 Event message to the LAN controller. The ICH7 then attempts to reboot the

processor.

2. If the reboot at step 1 is successful then the BIOS should clear the

SECOND_TO_STS bit. This prevents any further Heartbeats from being sent. The

BIOS may then perform addition recovery/boot steps. (See note 2, below.)

3. If the reboot attempt in step 1 is not successful, the timer will timeout a third time.

At this point the system has lock ed up and was unsuccessful in rebooting. Th e ICH7

does not attempt to automatically reboot again. The ICH7 starts sending a

message every heartbeat period

(30–32 seconds). The heartbeats continue until some external intervention occurs

(reset, power failure, etc.).

4. After step 3 (unsuccessful reboot after third timeout), if the user does a Power

Button Override, the system goes to an S5 state. The ICH7 continues sending the

messages every heartbeat period.

5. After step 4 (power button override after unsuccessful reboot) if the user presses

the Power Button again, the system should wake to an S0 state and the processor

should start executing the BIOS.

6. If step 5 (power button press) is successful in waking the system, the ICH7

continues sending messages every heartbeat period until the BIOS clears the

SECOND_TO_STS bit. (See note 2)

7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7

continues sending a message every heartbeat period. The ICH7 does not attempt

to automatically reboot again. The ICH7 starts sending a message every heartbeat

period (30–32 seconds). The heartbeats continue until some external intervention

occurs (reset, power failure, etc.).

(See note 3)

8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using

a button that pulses PWROK low or via the message on the SMBus slave I/F), the

ICH7 attempts to reset the system.

9. After step 8 (reset attempt) if the reset is successful, the BIOS is run. The ICH7

continues sending a message every heartbeat period until the BIOS clears the

SECOND_TO_STS bit. (See note 2)

10.After step 8 (reset attempt), if the reset is unsuccessful, the ICH7 continues

sending a message every heartbeat period. The ICH7 does not attempt to reboot

the system again without external intervention. (See note 3)

The following rules/steps apply if the system is in a G0 state and the policy is for the

ICH7 to not reboot the system after a hardware lockup.

1. On detecting the lockup the SECOND_T O_STS bit is set. The ICH7 sends a message

with the Watchdog (WD) Event status bit set (and any other bits that must also be

set). This message is sent as soon as the lockup is detected, and is sent with the

next (incremented) sequence number.

2. After step 1, the ICH7 sends a message every heartbeat period until some external

intervention occurs.

3. Rules/steps 4–10 apply if no user intervention (resets, power button presses,

SMBus reset messages) occur after a third timeout of the watchdog timer. If the

intervention occurs before the third timeout, then jump to rule/step 11.

4. After step 3 (third timeout), if the user does a Power Button Override, the system

goes to an S5 state. The ICH7 continues sending heartbeats at this point.

Intel ® ICH7 Family Datasheet 181

Functional Description

5. After step 4 (power button override), if the user presses the power button again,

the system should wake to an S0 state and the processor should start executing

the BIOS.

6. If step 5 (power button press) is successful in waking the system, the ICH7

continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See

note 2)

7. If step 5 (power button press) is unsuccessful in waking the system, the ICH7

continues sending heartbeats. The ICH7 does not attempt to reboot the system

again until some external intervention occu rs (reset, power failure, etc.). (See note

8. After step 3 (third timeout), if a reset is attempted (using a button that pulses

PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to

reset the system.

9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH7 continues sending

heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)

10.If step 8 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats.

The ICH7 does not attempt to reboot the system again without external

intervention. Note: A system that has locked up and can not be restarted with

power button press is probably broken (bad power supply, short circuit on some

bus, etc.)

11.This and the following rules/steps apply if the user intervention (power button

press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog

timer.

12.After step 1 (second timeout), if the user does a Power Button Override, the system

goes to an S5 state. The ICH7 continues sending heartbeats at this point.

13.After step 12 (power button override), if the user presses the power button again,

the system should wake to an S0 state and the processor should start executing

the BIOS.

14.If step 13 (power button press) is successful in waking the system, the ICH7

continues sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See

note 2)

15.If step 13 (power button pre ss) is unsuccessful in waking the system, the ICH7

continues sending heartbeats. The ICH7 does not attempt to reboot the system

again until some external intervention occu rs (reset, power failure, etc.). (See note

16.After step 1 (second timeout), if a reset is attempted (using a button that pulses

PWROK low or via the message on the SMBus slave I/F), the ICH7 attempts to

reset the system.

17.If step 16 (reset attempt) is successful, the BIOS is run. The ICH7 continues

sending heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)

18.If step 16 (reset attempt), is unsuccessful, the ICH7 continues sending heartbeats.

The ICH7 does not attempt to reboot the system again without external

intervention. (See note 3)

If the system is in a G1 (S1–S4) state, the ICH7 sends a heartbeat message every 30–

32 seconds. If an event occurs prior to the system being shutdown, the ICH7

immediately sends an event message with the next incremented sequence number.

After the event message, the ICH7 resumes sending heartbeat messages.

Functional Description

182 Intel ® ICH7 Family Datasheet

Note: Notes for previous two numbered lists.

1. Normally, the ICH7 does not send heartbeat messages while in the G0 state

(except in the case of a lockup). However, if a hardware event (or heartbeat)

occurs just as the system is transitioning into a G0 state, the hardware continues to

send the message even though the system is in a G0 state (and the status bits may

indicate this).

These messages are sent via the SMBus. The ICH7 abides by the SMBus rules

associated with collision detection. It delays starting a message until the bus is idle,

and detects collisions. If a collision is detected the ICH7 waits until the bus is idle,

and tries again.

2. WARNING: It is important the BIOS clears the SECOND_T O_STS bit, as the alerts

interfere with the LAN device driver from working properly. The alerts reset part of

the LAN controller and would prevent an operating system’s device driver from

sending or receiving some messages.

3. A system that has locked up and can not be restarted with power button press is

assumed to have broken hardware (bad power supply, short circuit on some bus,

etc.), and is beyond ICH7’s recovery mechanisms.

4. A spurious alert could occur in the following sequence:

— The processor has initiated an alert using the SEND_NOW bit

— During the alert, the THRM#, INTRUDER# or GPIO11 changes state

— The system then goes to a non-S0 state.

Once the system transitions to the non-S0 state, it may send a single alert with an

incremental SEQUENCE number.

5. An inaccurate alert message can be generated in the following scenario

— The system successfully boots after a second watchdog Timeout occurs.

— PWROK goes low (typically due to a reset button press) or a power button

override occurs (before the SECOND_TO_STS bit is cleared).

— An alert message indicating that the processor is missing or locked up is

generated with a new sequence number.

Table 5-40 shows the data included in the Alert on LAN messages.

Table 5-40. Heartbeat Message Data (Sheet 1 of 2)

Field Comment

Cover Tamper Status 1 = This bit is set if the intruder detect bit is set ( INTRD_DET).

Temp Event Status 1 = This bit is set if the Intel® ICH7 THERM# input signal is asserted.

Processor Missing Event

Status 1 = This bit is set if the processor failed to fetch its first instruction.

TCO Timer Event Status 1 = This bit is set when the TCO timer expires.

Software Event Status 1 = This bit is set when software writes a 1 to the SEND_NOW bit.

Unprogrammed

Firmware Hub Event

Status

1 = First BIOS fetch returned a value of FFh, indicating that the

Firmware Hub has not yet been programmed (still erased).

GPIO Status 1 = This bit is set when GPIO11 signal is high.

0 = This bit is cleared when GPIO11 signal is low.

An event message is triggered on an transition of GPIO11.

Intel ® ICH7 Family Datasheet 183

Functional Description

5.16 IDE Controller (D31:F1)

The ICH7 IDE controller features one sets of interface signals that can be enabled, tri-

stated or driven low.

The IDE interfaces of the ICH7 can support several types of data transfers:

•Programmed I/O (PIO): Processor is in control of the data transfer.

•8237 style DMA: DMA protocol that resembles the DMA on the IS A bus, although

it does not use the 8237 in the ICH7. This protocol off loads the processor from

moving data. This allows higher transfer rate of up to 16 MB/s.

•Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 33 MB/s.

•Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 66 MB/s.

•Ultra ATA/10 0: DMA protocol that redefines signals on the IDE cable to allow both

host and target throttling of data and transfer rates of up to 100 MB/s.

Note: ICH7-U Ultra Mobile only supports one IDE device.

5.16.1 PIO Transfers

The ICH7 IDE controller includes both compatible and fast timing modes. The fast

timing modes can be enabled only for the IDE data ports. All other transactions to the

IDE registers are run in single transaction mode with compatible timings.

Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1); one

device (connector drive 0) on ICH7-U Ultra Mobile. The IDE_TIMP and IDE_TIMS

Registers permit different timing modes to be programmed for drive 0 and drive 1 of

the same connector.

The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each

drive by programming the IDE I/O Configuration register and the Synchronous DMA

Control and Timing registers. When a drive is enabled for synchronous DMA mode

operation, the DMA tr ansfers are executed with the synchronous DMA timings. The PIO

transfers are executed using compatible timings or fast timings if also enabled.

SEQ[3:0] This is a sequence number. It initially is 0, and increme n ts each time

the ICH7 sends a new message. Upon reaching 1111, the sequence

number rolls over to 0000. MSB (SEQ3) sent first.

System Power State 00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first

MESSAGE1 Will be the same as the MESSAGE1 Register. MSB sent first.

MESSAGE2 Will be the same as the MESSAGE2 Register. MSB sent first.

WDSTATUS Will be the same as the WDSTATUS Register. MSB sent first.

Table 5-40. Heartbeat Message Data (Sheet 2 of 2)

Field Comment

Functional Description

184 Intel ® ICH7 Family Datasheet

5.16.1.1 PIO IDE Timing Modes

IDE data port transaction latency consists of startup latency, cycle latency, and

shutdown latency. Startup latency is incurred when a PCI master cycle targeting the

IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup

latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of

the read and write strobes (DIOR# and DIOW#).

Cycle latency consists of the I/O command strobe assertion length and recovery time.

Recovery time is provided so that transactions may occur back-to-back on the IDE

interface (without incurring startup and shutdown latency) without violating minimum

cycle periods for the IDE interface. The command strobe assertion width for the

enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,

or 5 PCI clocks. The recovery time is selected by the IDE_TIM R egister and may be set

to 1, 2, 3, or 4 PCI clocks.

If IORDY is asserted when the initial sample point is reached, no wait-states are added

to the command strobe assertion length. If IORDY is negated when the initial sample

point is reached, additional wait-states are added. Since the rising edge of IORDY must

be synchronized, at least two additional PCI clocks are added.

Shutdown latency is incurred after outstanding scheduled IDE data port transactions

(either a non-empty write post buffer or an outstanding read prefetch cycles) have

completed and before other transactions can proceed. It provides hold time on the

DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and

DIOW#). Shutdown latency is two PCI clocks in duration.

The IDE timings for various transaction types are shown in Table 5-41.

5.16.1.2 IORDY Masking

The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point

(ISP) on a drive by drive basis via the IDETIM Register.

5.16.1.3 PIO 32-Bit IDE Data Port Accesses

A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two

back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is

enabled for all timings, not just enhanced timing. For compatible timings, a shutdown

and startup latency is incurred between the two, 16-bit halves of the IDE transaction.

This ensures that the chip selects are deasserted for at least two PCI clocks between

the two cycles.

Table 5-41. IDE Transaction Timings (PCI Clocks)

IDE Transaction Type Startup

Latency

IORDY

Sample

Point (ISP)

Recovery Time

(RCT) Shutdown

Latency

Non-Data Port Compatible 4 11 22 2

Data Port Compatible 3 6 14 2

Fast Timing Mode 2 2–5 1–4 2

Intel ® ICH7 Family Datasheet 185

Functional Description

5.16.1.4 PIO IDE Data Port Prefetching and Posting

The ICH7 can be programmed via the IDETIM registers to allow data to be posted to

and prefetched from the IDE data ports.

Data prefetching is initiated when a data port read occurs. The read prefetch eliminates

latency to the IDE data ports and allows them to be performed back to back for the

highest possible PIO data transfer r ates. The first data port read of a sector is called the

demand read. Subsequent data port reads from the sector are called prefetch reads.

The demand read and all prefetch reads much be of the same size (16 or 32 bits) –

software must not mix 32-bit and 16-bit reads.

Data posting is performed for writes to the IDE data ports. The transaction is completed

on the PCI bus after the data is received by the ICH7. The ICH7 then runs the IDE cycle

to transfer the data to the driv e. If the ICH7 write buffer is non-empty and an unrelated

(non-data or opposite channel) IDE transaction occurs, that transaction will be stalled

until all current data in the write buffer is transferred to the drive. Only 16-bit buffer

writes are supported.

5.16.2 Bus Master Function

The ICH7 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master

channel is provided for the IDE connector. By performing the IDE data transfer as a PCI

Bus master, the ICH7 off-loads the processor and improves system performance in

multitasking environments. For Desktop and Mobile, both devices attached to the

connector can be programmed for bus master transfers, but only one device can be

active at a time.

5.16.2.1 Physical Region Descriptor Format

The physical memory region to be transferred is described by a Physical Region

Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.

The data transfer proceeds until all regions described by the PRDs in the table have

been transferred.

Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8

bytes in length. The first 4 bytes specify the byte address of a physical memory region.

This memory region must be DW ord-aligned and must not cross a 64-KB boundary. The

next two bytes specify the size or transfer count of the region in bytes (64-KB limit per

region). A value of 0 in these two bytes indicates 64-KB (thus the minimum transfer

count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in

the Descriptor table. Bus master operation terminates when the last descriptor has

been retired.

When the Bus Master IDE controller is reading data from the memory regions, bit 1 of

the Base Address is masked and byte enables are asserted for all read tr ansfers. When

writing data, bit 1 of the Base Address is not masked and if set, will cause the lower

Word byte enables to be deasserted for the first DWord transfer. The write to PCI

typically consists of a 32-byte cache line. If valid data ends prior to end of the cache

line, the byte enables will be deasserted for invalid data.

The total sum of the byte counts in every PRD of the descriptor table must be equal to

or greater than the size of the disk transfer request. If greater than the disk transfer

request, the driver must terminate the bus master transaction (by setting bit 0 in the

Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal

transfer completion.

Functional Description

186 Intel ® ICH7 Family Datasheet

5.16.2.2 Bus Master IDE Timings

The timing modes used for Bus Master IDE transfers are identical to those for PIO

transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to

program fast timing mode for DMA transactions only. This is useful for IDE devices

whose DMA transfer timings are faster than its PIO transfer timings. The IDE device

DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is

deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI

clock and no more transfers take place until DMA request is asserted again.

5.16.2.3 Interrupts

The ICH7 can generate interrupts based upon a signal coming from the PAT A device, or

due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and

active high. The PATA host controller generates IDEIRQ.

When the ICH7 IDE controller is operating independently from the SATA controller

(D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA

controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in

turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV

(D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is

emulating the logical secondary channel (MAP.MV = 1h), the PAT A channel will emulate

the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA

controller in combined mode is emulating the logical primary channel (MAP.MV=2h),

IDEIRQ will generate IRQ15.

Note: IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.

Note: The combined mode is not supported on ICH7-U Ultr a Mobile. ICH7-U does not contain

a SATA controller.

Figure 5-8. Physical Region Descriptor Table Entry

EOT Reserved Byte Count [15:1]

Memory Region Physical Base Address [31:1]

Byte 3Byte 2Byte 1Byte 0

Memory

Region

Main Memory

Intel ® ICH7 Family Datasheet 187

Functional Description

5.16.2.4 Bus Master IDE Operation

To initiate a bus master transfer between memory and an IDE device, the following

steps are required:

1. Software prepares a PRD table in system memory. The PRD table must be DWord-

aligned and must not cross a 64-KB boundary.

2. Software provides the starting address of the PRD Table by loading the PRD Table

Pointer Register. The direction of the data transfer is specified by setting the Read/

Write Control bit. The interrupt bit and Error bit in the Status register are cleared.

3. Software issues the appropriate DMA transfer command to the disk device.

4. The bus master function is engaged by software writing a 1 to the Start bit in the

Command Register. The first entry in the PRD table is fetched and loaded into two

registers which are not visible by software, the Current Base and Current Count

registers. These registers hold the current value of the address and byte count

loaded from the PRD table. The value in these registers is only valid when there is

an active command to an IDE device.

5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.

6. The controller transfers data to/from memory responding to DMA requests from the

IDE device. The IDE device and the host controller may or may not throttle the

transfer sever al times. When the last data transfer for a region has been completed

on the IDE interface, the next descriptor is fetched from the table. The descriptor

contents are loaded into the Current Base and Current Count registers.

7. At the end of the transfer, the IDE device signals an interrupt.

8. In response to the interrupt, software resets the Start/Stop bit in the command

determine if the transfer completed successfully.

The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data

transfers terminate when the physical region described by the last PRD in the table has

been completely transferred. The active bit in the Status Register is reset and the

DDRQ signal is masked.

The buffer is flushed (when in the write state) or invalidated (when in the read state)

when a terminal count condition exists; that is, the current region descriptor has the

EOL bit set and that region has been exhausted. The buffer is also flushed (write state)

or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register

is set. Software that reads the status register and finds the Error bit reset, and either

the Active bit reset or the Interrupt bit set, can be assured that all data destined for

system memory has been transferred and that data is valid in system memory.

Table 5-42 describes how to interpret the Interrupt and Active bits in the Status

Functional Description

188 Intel ® ICH7 Family Datasheet

5.16.2.5 Error Conditions

IDE devices are sector based mass storage devices. The drivers handle errors on a

sector basis; either a sector is transferred successfully or it is not. A sector is

512 bytes.

If the IDE device does not complete the transfer due to a hardware or software error,

the command will eventually be stopped by the driv er setting Command Start bit to 0

when the driver times out the disk transaction. Information in the IDE device registers

help isolate the caus e of the probl e m.

If the controller encounters an error while doing the bus master transfers it will stop

the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in

the Bus Master IDE Status register. The controller does not gener ate an interrupt when

this happens. The device driver can use device specific information (PCI Configuration

Space Status register and IDE Drive Register) to determine what caused the error.

Whenever a requested transfer does not complete properly, information in the IDE

device registers (Sector Count) can be used to determine how much of the transfer was

completed and to construct a new PRD table to complete the requested operation. In

most cases the existing PRD table can be used to complete the operation.

5.16.3 Ultra ATA/100/66/33 Protocol

The ICH7 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for

a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to

33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and Ultra ATA/

100 can achieve read transfer rates up to 100 MB/s and write transfer rates up to

88.9 MB/s.

The Ultra ATA/100/6 6/33 definition also incorporates a Cyclic Redundancy Checking

(CRC-16) error checking protocol.

Table 5-42. Interrupt/Active Bit Interac tion Definition

Interrupt Active Description

DMA transfer is in progress. No inte rrupt has been gener ated by the IDE

device.

The IDE device generated an interrupt. The controller exhausted the

Physical Region Descriptors. This is the normal completion case where

the size of the physical memory regions was equal to the IDE device

transfer size.

The IDE device generated an interrupt. The controller has not reached

the end of the physical memory regions. This is a valid completion case

where the size of the physical memory regions was larger than the IDE

device transfer size.

This bit combination signals an error condition. If the Error bit in the

status register is set, then the controller has some problem transferring

data to/from memory. Specifics of the error have to be determined using

bus-specific information. If the Error bit is not set, then the PRD's

specified a smaller size than the IDE transfer size.

Intel ® ICH7 Family Datasheet 189

Functional Description

5.16.3.1 Operation

Initial setup programming consists of enabling and performing the proper configur ation

of the ICH7 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH7, this

consists of enabling synchronous DMA mode and setting up appropriate Synchronous

DMA timings.

When ready to transfer data to or from an IDE device, the Bus Master IDE

programming model is followed. Once programmed, the drive and ICH7 control the

transfer of data via the Ultr a ATA/100/66/33 protocol. The actual data transfer consists

of three phases, a start-up phase, a data transfer phase, and a burst termination

phase.

The IDE device begins the start-up phase by asserting DMARQ signal. When ready to

begin the transfer, the ICH7 asserts DMACK# signal. When DMACK# signal is asserted,

the host controller drives CS0# and CS1# inactive, DA0–DA2 low. F or write cycles, the

ICH7 deasserts STOP, waits for the IDE device to assert DMARDY#, and then drives the

first data word and STROBE signal. For read cycles, the ICH7 tri-states the DD lines,

deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word

and STROBE.

The data transfer phase continues the burst transfers with the data transmitter (ICH7 –

writes, IDE device – reads) providing data and toggling STROBE. Data is transferred

(latched by receiver) on each rising and falling edge of STROBE. The transmitter can

pause the burst by holding STROBE high or low, resuming the burst by again toggling

STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the

transfers by asserting DMARDY#. The ICH7 pauses a burst transaction to prevent an

internal line buffer over or under flow condition, resuming once the condition has

cleared. It may also pause a transaction if the current PRD byte count has expired,

resuming once it has fetched the next PRD.

The current burst can be terminated by either the transmitter or receiver. A burst

termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data.

The ICH7 can stop a burst by asserting STOP, with the IDE device acknowledging by

deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH7

acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a

high level. The ICH7 then drives the CRC value onto the DD lines and deassert

DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH7

terminates a burst transfer if it needs to service the opposite IDE channel, if a

Programmed I/O (PIO) cycle is executed to the IDE channel currently running the

burst, or upon transferring the last data from the final PRD.

Functional Description

190 Intel ® ICH7 Family Datasheet

5.16.4 Ultra ATA/33/66/100 Timing

The timings for Ultra AT A/33/66/100 modes are programmed via the Synchronous DMA

Timing register and the IDE Configuration register. Different timings can be

programmed for each drive in the system. The Base Clock frequency for each drive is

selected in the IDE Configuration register. The Cycle Time (CT) and Ready to Pause

(RP) time (defined as multiples of the Base Clock) are progr ammed in the Synchronous

DMA Timing Register. The Cycle Time repre sents t he minimum pulse width of the data

strobe (STROBE) signal. The Ready to P ause time represents the number of Base Clock

periods that the ICH7 waits from deassertion of DMARDY# to the assertion of STOP

when it desires to stop a burst read transaction.

Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle

Time (CT) must be set for three Base Clocks. The ICH7 thus toggles the write strobe

signal every 22.5 ns, transferring two bytes of data on each strobe edge. This means

that the ICH7 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For

read transfers, the read strobe is driven by the ATA/100 device, and the ICH7 supports

reads at the maximum rate of 100 MB/s.

5.16.5 ATA Swap Bay

To support PATA swap bay, the ICH7 allows the IDE output signals to be tri-stated and

input buffers to be turned off. This should be done prior to the remo val of the drive. The

output signals can also be driven low. This can be used to remove charge built up on

the signals. Configuration bits are included in the IDE I/O Configuration register, offset

54h in the IDE PCI configuration space.

In a PATA swap bay operation, an IDE device is removed and a new one inserted while

the IDE interface is powered down and the rest of the system is in a fully powered-on

state (SO). During a PAT A sw ap ba y oper ation, if the operating system executes cy cles

to the IDE interface after it has been powered down it will cause the ICH7 to hang the

system that is waiting for IORDY to be asserted from the drive.

To correct this issue, the following BIOS procedures are required for performing an IDE

swap:

1. Program IDE SIG_MODE (Configuration register at offset 54h) to 10b (drive low

mode).

2. Clear IORDY Sample P oint Enable (bits 1 or 5 of IDE Timing reg.). This prevents the

ICH7 from waiting for IORDY assertion when the operating system accesses the

IDE device after the IDE drive powers down, and ensures that 0s are always be

returned for read cycles that occur during swap operation.

Warning: Software should not attempt to control the outputs (either tri-state or driving low),

while an IDE transfer is in progress. Unpredictable results could occur, including a

system lockup.

5.16.6 SMI Trapping

Device 31:Function 1: Offset C0h (see Section 15.1.26) contain control for generating

SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–

1F7h and 3F6h). Accesses to one of these ranges with the appropriate bit set causes

the cycle to not be forwarded to the IDE controller, and for an SMI# to be generated. If

an access to the Bus-Master IDE registers occurs while trapping is enabled for the

device being accessed, then the register is updated , an SMI# is generated, and the

device activity status bits (Device 31:Function 1:Offset C4h) are updated indicating

that a trap occurred.

Intel ® ICH7 Family Datasheet 191

Functional Description

5.17 SATA Host Controller (D31:F2) (Desktop and

Mobile Only)

The SATA function in the ICH7 has dual modes of operation to support different

operating system conditions. In the case of Native IDE enabled operating systems, the

ICH7 has separate PCI functions for serial and parallel ATA (“enhanced mode”). To

support legacy operating systems, there is only on e PCI function for both the serial and

parallel ATA ports if functionality from both SATA and PATA devices is desired

(“combined mode”).

The MAP register, Section 12.1.33, provides the ability to share PCI functions. When

sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,

Function 1 (IDE controller) is hidden by software writing to the Function Disable

The ICH7 SATA controller features four (desktop only) / two (mobile only) sets of

interface signals (ports) that can be independently enabled or disabled (they cannot be

tri-stated or driven low). Each interface is supported by an independent DMA controller.

The ICH7 SATA controller interacts with an attached mass storage device through a

The host software follows existing standards and conventions when accessing the

Table 5-43 lists ICH7 SATA Feature support information. Table 5-44 contains

descriptions for the SATA features listed in Table 5-43.

Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface

transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode

reported by the SATA device or the system BIOS.

Table 5-43. SATA Features Support in Intel® ICH7

Feature ICH7 & ICH7 - M

(AHCI/RAID Disabled) ICH7 & ICH7-M

(AHCI/RAID Enabled)

Native Command Queing

(NCQ) N/A Supported

Auto Activate for DMA N/A Supported

Hot Plug Support N/A Supported

Asynchronous Signal

Recovery N/A Supported

3 Gb/s Transfer Rate Supported

(Desktop Only) Supported

(Desktop Only)

ATAPI Asynchronous

Notification N/A Supported

Host Initiated Power

Management N/A Supported

(Mobile Only)

Staggered Spin-Up Supported Supported

Command Completion

Coalescing N/A N/A

Port Multiplier N/A N/A

External SATA N/A N/A

Functional Description

192 Intel ® ICH7 Family Datasheet

5.17.1 Theory of Operation

5.17.1.1 Standard ATA Emulation

The ICH7 contains a set of registers that shadow the contents of the legacy IDE

registers. The behavior of the Command and Control Block registers, PIO, and DMA

data transfers, resets, and interrupts are all emulated.

Note: The ICH7 will assert INTR when the master device completes the EDD command

regardless of the command completion status of the slave device. If the master

completes EDD first, an INTR is generated and BSY will remain '1' until the slave

completes the command. If the slave completes EDD first, BSY will be '0' when the

master completes the EDD command and asserts INTR. Software must wait for busy to

clear (0) before completing an EDD command, as required by the ATA5 through ATA7

(T13) industry standards.

5.17.1.2 48-Bit LBA Operation

The SATA host controller supports 48-bit LBA through the host-to-device register FIS

when accesses are performed via writes to the task file. The SATA host controller will

ensure that the correct data is put into the correct byte of the host-to-device FIS.

There are special considerations when reading from the task file to support 48-bit LBA

operation. Software may need to read all 16-bits. Since the registers are only 8-bits

wide and act as a FIFO, a bit must be set in the device/control register, which is at

offset 3F6h for primary and 376h for secondary (or their native counterparts).

Table 5-44. SATA Feature Description

Feature Description

Native Command Queing

(NCQ) Allows the device to reorder commands for more efficient

data transfers

Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a

DMA Setup only

Hot Plug Support Allows for device detection without power being applied and

ability to connect and disconnect devices without prior

notification to the system

Asynchronous Signal

Recovery Provides a recovery from a loss of signal or establishing

communication afte r hot plug

3 Gb/s Transfer Rate Capable of data transfers up to 3Gb/s

ATAPI Asynchronous

Notification A mechanism for a device to send a notification to the host

that the device requires attention

Host Initiated Power

Management Capability for the host controller to request Partial and

Slumber interface power states

Staggered Spin-Up Enables the host the ability to spin up hard dr ives

sequentially to prevent power load problems on boot

Command Completion

Coalescing

Reduces interrupt and completion overhead by allowing a

specified number of commands to complete and then

generating an interrupt to process the commands

Port Multiplier A mechanism for one active host connection to

communicate with multipl e devices

External SATA Technology that allows for an outside the box connection of

up to 2 meters (when using the cable defined in SATA-IO)

Intel ® ICH7 Family Datasheet 193

Functional Description

If software clears bit 7 of the control register before performing a read, the last item

written will be returned from the FIFO. If software sets bit 7 of the control register

before performing a read, the first item written will be returned from the FIFO.

5.17.2 SATA Swap Bay Support

Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SAT A host controller

without special support from AHCI and the proper board hardware. However, the ICH7

does provide for basic SATA swap bay support using the PSC register configuration bits

and power management flows. A device can be powered down by software and the port

can then be disabled, allowing removal and insertion of a new device.

Note: This SATA swap bay operation requires board hardware (implementation specific),

BIOS, and oper ating system support.

5.17.3 Intel® Matrix Storage Technology Configuration (Intel®

ICH7R, ICH7DH, and ICH7-M DH Only)

The Intel® Matrix Storage Technology offers several diverse options for RAID

(redundant array of independent disks) to meet the needs of the end user. AHCI

support provides higher performance and alleviates disk bottlenecks by taking

advantage of the independent DMA engines that each SATA port offers in ICH7.

• RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for

data intensive applications such as video editing.

• Data security is offered thru RAID Level 1, which performs mirroring.

• RAID Level 10 (ICH7R/ICH7DH only) provides high levels of storage performance

with data protection, combining the fault-tolerance of RAID Level 1 with the

performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates

can be achieved on systems that require both performance and fault-tolerance.

RAID Level 10 requires 4 hard drives, and provid es the c apac ity of two drives.

• RAID Level 5 (ICH7R/ICH7DH only) provides highly efficient storage while

maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it

across all disks, fault tolerance of any single driv e is achieved while only consuming

1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or

a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction

rates, with a medium write rate. RAID 5 is well suited for applications that require

high amounts of storage while maintaining fault tolerance.

By using the ICH7’s built-in Intel Matrix Storage Technology, there is no loss of PCI

resources (request/grant pair) or add-in card slot.

Intel Matrix Storage Technology is not available in all ICH7 components. ICH7-M DH

supports RAID Level 0, 1. See Section 1.2.

Intel Matrix Storage Technology functionality requires the following items:

1. ICH7 component enabled for Intel Matrix Storage Technology (see Section 1.2)

2. Intel® Matrix Storage Manager RAID Option ROM must be on the platform

3. Intel® Matrix Storage Manager drivers, most recent revision.

4. At least two SATA hard disk drives (minimum depends on RAID configuration).

Intel Matrix Storage Technology is not available in the following configurations:

1. The SATA controller in compatible mode.

Functional Description

194 Intel ® ICH7 Family Datasheet

5.17.3.1 Intel® Matrix Storage Manager RAID Option ROM

The Intel Matrix Storage Manager RAID Option ROM is a standard PnP Option ROM that

is easily integrated into any System BIOS. When in place, it provides the following

three primary functions:

• Provides a text mode user interface that allows the user to manage the RAID

configuration on the system in a pre-operating system en vironment. Its feature set

is kept simple to keep size to a minimum, but allows the user to create & delete

RAID volumes and select recovery options when problems occur.

• Provides boot support when using a RAID volume as a boot disk. It does this by

providing Int13 services when a RAID volume needs to be accessed by DOS

applications (such as NTLDR) and by exporting the RAID volumes to the System

BIOS for selection in the boot order.

• At each boot up, provides the user with a status of the RAID volumes and the

option to enter the user interface by pressing CTRL-I.

5.17.4 Power Management Operation

Power management of the ICH7 SATA controller and ports will cover operations of the

host controller and the SATA wire.

5.17.4.1 Power State Mappings

The D0 PCI power management state for device is supported by the ICH7 SATA

controller.

SATA devices may also have multiple power states. From parallel ATA, three device

states are supported through ACPI. They are:

•D0 – Device is working and instantly available.

•D1 – device enters when it receives a ST ANDBY IMMEDIA TE command. Exit latency

from this state is in seconds

•D3 – from the SATA device’s perspective, no different than a D1 state, in that it is

entered via the STANDBY IMMEDIATE command. However, an ACPI method is also

called which will reset the device and then cut its power.

Each of these device states are subsets of the host controller’s D0 state.

Finally, SA TA defines three PHY laye r power states, which have no equiv alent mappings

to parallel ATA. They are:

•PHY READY – PHY logic and PLL are both on and active

•Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer

than 10 ns

•Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to

10 ms.

Since these states have much lower exit latency than the ACPI D1 and D3 states, the

SATA controller defines these states as sub-states of the device D0 state.

Intel ® ICH7 Family Datasheet 195

Functional Description

5.17.4.2 Power State Transitions

5.17.4.2.1 Partial and Slumber State Entry/Exit

The partial and slumber states save interface power when the interface is idle. It would

be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the

interface can have power saved while no commands are pending. The SATA controller

defines PHY layer power management (as performed via primitives) as a driver

operation from the host side, and a device proprietary mechanism on the device side.

The SATA controller accepts device transition types, but does not issue any transitions

as a host. All received requests from a SATA device will be ACKed.

When an operation is performed to the SATA controller such that it needs to use the

SATA cable, the controlle r must check whether the link is in the Partial or Slumber

states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the

SATA device must perform the same action.

5.17.4.2.2 Device D1, D3 States

These states are entered after some period of time when software has determined that

no commands will be sent to this device for some time. The mechanism for putting a

device in these states does not involve any work on the host controller, other then

sending commands over the interface to the device. The command most likely to be

used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.

5.17.4.2.3 Host Controller D3HOT State

After the interface and device have been put into a low power state, the SATA host

controller may be put into a low power state. This is performed via the PCI power

management registers in configuration space. There are two very important aspects to

note when using PCI power manageme nt.

1. When the power state is D3, only accesses to configuration space are allowed. Any

attempt to access the memory or I/O spaces will result in master abort.

2. When the power state is D3, no interrupts may be generated, even if they are

enabled. If an interrupt status bit is pending when the controller transitions to D0,

an interrupt may be generated.

When the controller is put into D3, it is assumed that software has properly shut down

the device and d isabled the ports. Ther efore, there is no need to sustain an y v alues on

the port wires. The interface will be treated as if no device is present on the cable, and

power will be minimized.

When returning from a D3 state, an internal reset will not be performed.

Figure 5-9. SATA Power St ates

Intel® ICH SATA Controller = D0

Device = D3

Power

Resume Latency

Device = D0

PHY =

Ready

Device = D1

PHY =

Slumber

PHY =

Partial PHY =

Off (port

disabled)

PHY =

Slumber PHY =

Off (port

disabled)

PHY =

Slumber PHY =

Off (port

disabled)

Functional Description

196 Intel ® ICH7 Family Datasheet

5.17.4.2.4 Non-AHCI Mode PME# Generation

When in non-AHCI mode (legacy mode) of operation, the SATA controller does not

generate PME#. This includes attach events (since the port must be disabled), or

interlock switch events (via the SATAGP pins).

5.17.4.3 SMI Trapping (APM)

Device 31:Function2:Offset C0h (see Section 12.1.40) contain control for generating

SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–

1F7h, 3F6h, 170–177h, and 376h). If the SA TA controller is in legacy mode and is using

these addresses, accesses to one of these ranges with the appropriate bit set causes

the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated.

If an access to the Bus-Master IDE registers occurs while trapping is enabled for the

device being accessed, then the register is updated , an SMI# is generated, and the

device activity status bits (Section 12.1.41) are updated indicating that a trap

occurred.

5.17.5 SATA LED

The SATALED# output is driven whenever the BSY bit is set in any SATA port. The

SATALED# is an active-low open-collector output. When SATALED# is low, the LED

should be active. When SATALED# is high, the LED should be inactive.

5.17.6 AHCI Operation (Intel® ICH7R, ICH7DH, and Mobile Only)

The ICH7 provides hardware support for Advanced Host Controller Interface (AHCI), a

programming interface for SATA host controllers developed thru a joint industry effort

(AHCI not available on all ICH7 components; see Section 1.2). AHCI defines

transactions between the SATA controller and software and enables advanced

performance and usability with SATA. Platforms supporting AHCI may take advantage

of performance features such as no master/slave designation for SATA devices—each

device is treated as a master—and hardware assisted native command queuing. AHCI

also provides usability enhancements such as Hot-Plug. AHCI requires appropriate

software support (e.g., an AHCI driver) and for some features, hardware support in the

SATA device or additional platform hardware.

The ICH7 supports all of the mandatory features of the Serial ATA Advanced Host

Controller Interface Specification, Revision 1.0 and many optional features, such as

hardware assisted native command queuing, aggressive power management, LED

indicator support, and Hot-Plug thru the use of interlock switch support (additional

platform hardware and software may be re quired depending upon the implementation).

Note: For reliable device removal notification while in AHCI operation without the use of

interlock switches (surprise removal), interface power management should be disabled

for the associated port. See Section 7.3.1 of the AHCI Specification for more

information.

Note: When there are more than two PRD entries for a PIO data transfer that spans multiple

DA T A FISes, the ICH7 does not support intermediate PRD entries that are less than 144

Words in size when the ICH7 is operating in AHCI mode at 1.5 Gb/s.

Intel ® ICH7 Family Datasheet 197

Functional Description

5.17.7 Serial ATA Reference Clock Low Power Request

(SATACLKREQ#)

The 100 MHz Serial A T A R eference Clock (SA TACLKP, SA TACLKN) is implemented on the

system as a ground-terminated low-v oltage differential signal pair driven by the system

Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference

Clock is not needed and may be stopped and tri-stated at the clock chip allowing

system-level power reductions.

The ICH7 uses the SATACLKREQ# output signal to commun icate with the system Clock

Chip to request either SATA clock running or to tell the system clock chip that it can

stop the SATA Reference Clock. ICH7 drives this signal low to request clock running,

and tristates the signal to indicate that the SAT A Reference Clock may be stopped (the

ICH7 does not drive the pin high). When the SATACLKREQ# is tristated by the ICH7,

the clock chip may stop the SAT A R eference Clock within 100 ns, anytime after 100 ns,

or not at all. If the SATA R eference Clock is not already running, it will start within 100

ns after a SATACLKREQ# is driven low by the ICH7.

To enable SATA Reference Clock Low Power Request:

1. Configure GPIO35 to native function

2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28).

Note: The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is

running after system reset.

5.18 High Precision Event Timers

This function provides a set of timers that can be used by the operating system. The

timers are defined such that in the future, the operating system ma y be able to assign

specific timers to used directly by specific applications. Each timer can be configured to

cause a separate interrupt.

ICH7 provides three timers. The three timers are implemented as a single counter each

with its own comparator and v alue register. This counter increases monotonically. Each

individual timer can generate an interrupt when the value in its value register matches

the value in the main counter.

The registers associated with these timers are mapped to a memory space (much like

the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS

reports to the operating system the location of the register space. The hardware can

support an assignable decode space; however, the BIOS sets this space prior to

handing it over to the operating system

(See Section 6.4). It is not expected that the operating system will move the location

of these timers once it is set by the BIOS.

5.18.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified

in the timer resolution fields.

2. Within any 100 microsecond period, the timer reports a time that is up to two ticks

too early or too late. Each tick is less than or equal to 100 ns, so this represents an

error of less than 0.2%.

3. The timer is monotonic. It does not return the same value on two consecutive

reads (unless the counter has rolled over and reached the same value).

Functional Description

198 Intel ® ICH7 Family Datasheet

The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666

MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but

does have the correct aver age period. The accur acy of the main counter is as accurate

as the 14.3818 MHz clock.

5.18.2 Interrupt Mapping

Mapping Option # 1 (Legacy Replacemen t Option)

In this case, the Legacy Replacement Ro ut bit (LEG_RT_CNF) is set. This forces the

mapping found in Table 5-45.

Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Ro ut bit (LEG_RT_CNF) is 0. Each timer has its

own routing control. The supported interrupt values are IRQ 20, 21, 22, and 23.

5.18.3 Periodic vs. Non-Periodic Modes

Non-Periodic Mode

Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only

support 32-bit mode (See Section 20.1.5).

All three timers support non-periodic mode.

Consult Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this

mode.

Periodic Mode

Timer 0 is the only timer that supports periodic mode. Consult Section 2.3.9.2.2 of the

IA-PC HPET Specification for a description of this mode.

The following usage model is expected:

1. Software clears the EN AB LE_CNF bit to prev e n t an y i nterrupts

2. Software Clears the main counter by writing a value of 00h to it.

3. Software sets the TIMER0 _ VAL_SET_CNF bit.

4. Software writes the new value in the TIMER0_COMPARATOR_VAL register

5. Software sets the ENABLE_CNF bit to enable interrupts.

Table 5-45. Legacy Replacement Routing

Timer 8259 Mapping APIC Mapping Comment

0IRQ0 IRQ2

In this case, the 8254 timer will

not cause any interrupts

1IRQ8 IRQ8

In this case, the RTC will not cause

any interrupts.

2 Per IRQ Routing Field. Per IRQ Routing Field

Intel ® ICH7 Family Datasheet 199

Functional Description

The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-

bit write in a 32-bit environment except if only the periodic rate is being changed

during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then

the following software solution will always work regardless of the environment:

1. Set TIMER0_VAL_SET_CNF bit

2. Set the lower 32 bits of the Timer0 Comparator Value register

3. Set TIMER0_VAL_SET_CNF bit

4. 4) Set the upper 32 bits of the Timer0 Comparator Value register

5.18.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the

Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge

or level type for each timer)

The Device Driver code should do the following for an available timer:

1. Set the Overall Enable bit (Offset 04h, bit 0).

2. Set the timer type field (selects one-shot or periodic).

3. Set the interrupt enable

4. Set the comparator value

5.18.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.10 for

information regarding the polarity programming of the I/O APIC for detecting internal

interrupts.

If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can

be shared with PCI interrupts. This may be shared although it’s unlikely for the

operating system to attempt to do this.

If more than one timer is configured to share the same IRQ (using the

TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-

triggered mode. Edge-triggered interrupts cannot be shared.

5.18.6 Handling Interrupts

If each timer has a unique interrupt and the timer has been configured for edge-

triggered mode, then there are no specific steps required. No read is required to

process the interrupt.

If a timer has been configured to level-triggered mode, then its interrupt must be

cleared by the software. This is done by reading the interrupt status register and

writing a 1 back to the bit position for the interrupt to be cleared.

Independent of the mode, software can read the value in the main counter to see how

time has passed between when the interrupt was generated and when it was first

serviced.

If Timer 0 is set up to generate a periodic interrupt, the softw are can check to see how

much time remains until the next interrupt by checking the timer value register.

Functional Description

200 Intel ® ICH7 Family Datasheet

5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors

A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit

instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.

A race condition comes up if a 32-bit processor reads the 64-bit register using two

separate 32-bit reads. The danger is that just after reading one half , the other half rolls

over and changes the first half.

If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before

reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not

want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the

TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper

32-bits are always 0.

5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and

F3)

The ICH7 contains four USB 2.0 full/low-speed host controllers that support the

standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host

Controller (UHC) includes a root hub with two separate USB ports each, for a total of

eight USB ports.

• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs

are not 5 V tolerant, and can be used as GPIs if not needed.

• The ICH7’s UHCI host controllers are arbitrated differently than standard PCI

devices to improve arbitration latency.

• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows

support for USB full-speed signaling rates, instead of USB I/O buffers.

5.19.1 Data Structures in Main Memory

Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1

details the data structures used to communicate control, status, and data between

software and the ICH7.

5.19.2 Data Transfers to/from Main Memory

Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1

describes the details on how HCD and the ICH7 communicate via the Schedule data

structures.

5.19.3 Data Encoding and Bit Stuffing

The ICH7 USB employs NRZI data encoding (Non-Return to Zero Inverted) when

transmitting packets. Full details on this implementation are given in the Universal

Serial Bus Specification, Revision 2.0.

5.19.4 Bus Protocol

5.19.4.1 Bit Ordering

Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,

through to the most significant bit (MSb) last.

Intel ® ICH7 Family Datasheet 201

Functional Description

5.19.4.2 SYNC Field

All packets begin with a synchronization (SYNC) field, which is a coded sequence that

generates a maximum edge transition density. The SYNC field appears on the bus as

IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the

input circuitry to align incoming data with the local clock and is defined to be 8 bits in

length. SYNC serves only as a synchronization mechanism and is not shown in the

following packet diagr ams. The last two bits in the SYNC field are a marker that is used

to identify the first bit of the PID. All subsequent bits in the packet must be indexed

from this point.

5.19.4.3 Packet Field Formats

All packets have distinct start and end of packet delimiters. Full details are given in the

Universal Serial Bus Specification, Revision 2.0, in Section 8.3.1.

5.19.4.4 Address Fields

Function endpoints are addressed using the function address field and the endpoint

field. Full details on this are given in the Universal Serial Bus Specification, Revision

2.0, in Section 8.3.2.

5.19.4.5 Frame Number Field

The frame number field is an 11-bit field that is incremented by the host on a per frame

basis. The fr ame number field rolls ov er upon reaching its maximum v alue of 7FFh, and

is sent only for SOF tokens at the start of each frame.

5.19.4.6 Data Field

The data field may range from 0 to 1023 bytes and must be an integral numbers of

bytes. Data bits within each byte are shifted out LSB first.

5.19.4.7 Cyclic Red undancy Check (CRC)

CRC is used to protect the all no n-PID fields in tok en and data pack ets. In this context,

these fields are considered to be protected fields. Full details on this are given in the

Universal Serial Bus Specification, Revision 2.0, in Section 8.3.5.

5.19.5 Packet Formats

The USB protocol calls out several packet types: token, data, and handshake packets.

Full details on this are given in the Universal Serial Bus Specification, Revision 2.0, in

section 8.4.

5.19.6 USB Interrupts

There are two general groups of USB interrupt sources, those resulting from execution

of transactions in the schedule, and those resulting from an ICH7 operation error. All

transaction-based sources can be masked by software through the ICH7’s Interrupt

Enable register. Additionally, individual transfer descriptors can be marked to generate

an interrupt on completion.

When the ICH7 driv es an inte rrupt for U SB , it internally drives the PIRQA# pin for USB

function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC#

pin for USB function #2, until all sources of the interrupt are cleared. In order to

accommodate some operating systems, the Interrupt Pin register must contain a

different value for each function of this new multi-function device.

Functional Description

202 Intel ® ICH7 Family Datasheet

5.19.6.1 Transaction-Based Interrupts

These interrupts are not signaled until after the status for the last complete transaction

in the frame has been written back to host memory. This ensures that software can

safely process through (Frame List Current Index -1) when it is servicing an interrupt.

CRC Error / Time-Out

A CRC/Time-Out error occurs when a pack et transmitted from the ICH7 to a USB device

or a packet tr ansmitted from a USB device to the ICH7 generates a CRC error. The ICH7

is informed of this event by a time-out from the USB device or by the ICH7’s CRC

checker generating an error on reception of the packet. Additionally, a USB bus time-

out occurs when USB devices do not respond to a transaction phase within 19-bit times

of an EOP. Either of these conditions causes the C_ERR field of the TD to decrement.

When the C_ERR field decrements to 0, the following occurs:

• The Active bit in the TD is cleared

• The Stalled bit in the TD is set

• The CRC/Time-out bit in the TD is set.

• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.

If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware

interrupt will be signaled to the system.

Interrupt on Completion

Transfer Descriptors contain a bit that can be set to cause an interrupt on their

completion. The completion of the transaction associated with that block causes the

USB Interrupt bit in the HC Status Register to be set at the end of the frame in which

the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit

in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is

set to 0 (even if it was set to 0 when initially read).

If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a

hardware interrupt is signaled to the system. The USB Interrupt bit in the HC status

completion is because of errors, the USB Error bit in the HC status register is also set.

Short Packet Detect

A transfer set is a collection of data which requires more than one USB transaction to

completely move the data across the USB . An example might be a large print file which

requires numerous TDs in multiple frames to completely transfer the data. R eception of

a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or

Interrupt transfers signals the completion of the transfer set, even if there are active

TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to

set the USB Interrupt bit in the HC status register at the end of the frame in which this

event occurs. This feature streamlines the processing of input on these transfer types.

If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a

hardware interrupt is signaled to the system at the end of the frame where the event

occurred.

Intel ® ICH7 Family Datasheet 203

Functional Description

Serial Bus Babble

When a device transmits on the USB for a time greater than its assigned Max Length, it

is said to be babbling. Since isochrony can be destroy ed by a babbling device, this error

results in the Active bit in the TD being cleared to 0 and the Stalled and Babble bits

being set to 1. The C_ERR field is not decremented for a babble. The USB Error

Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware

interrupt is signaled to the system.

If an EOF babble was caused by the ICH7 (due to incorrect schedule for instance), the

ICH7 forces a bit stuff error followed by an EOP and the start of the next frame.

Stalled

This event indicates that a device/endpoint returned a STALL handshake during a

transaction or that the transaction ended in an error condition. The TDs Stalled bit is

set and the Active bit is cleared. Reception of a STALL does not decrement the error

counter. A hardware interrupt is signaled to the system.

Data Buffer Error

This event indicates that an overrun of incoming data or a under-run of outgoing data

has occurred for this tr ansaction. This would generally be cau sed by the ICH7 not being

able to access required data buffers in memory within necessary latency requirements.

Either of these conditions causes the C_ERR fie ld of the TD to be decremented.

When C_ERR decrements to 0, the Active bit in the TD is cleared, the Stalled bit is set,

the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the fr am e

and a hardware interrupt is signaled to the system.

Bit Stuff Error

A bit stuff error results from the detection of a sequence of more that six 1s in a row

within the incoming data stream. This causes the C_ERR field of the TD to be

decremented. When the C_ERR field decrements to 0, the Activ e bit in the TD is cleared

to 0, the Stalled bit is set to 1, the USB Error Interrupt bit in the HC Status register is

set to 1 at the end of the frame and a hardware interrupt is signaled to the system.

5.19.6.2 Non-Transaction Based Interrupts

If an ICH7 process error or system error occur, the ICH7 halts and immediately issues a

hardware interrupt to the system.

Resume Received

This event indicates that the ICH7 receiv ed a RE SUME signal from a device on the USB

bus during a global suspend. If this interrupt is enabled in the Interrupt Enable register,

a hardware interrupt is signaled to the system allowing the USB to be brought out of

the suspend state and returned to normal operation.

ICH7 Process Error

The HC monitors certain critical fields during operation to ensure that it does not

process corrupted data structures. These include checking for a valid PID and verifying

that the MaxLength field is less than 1280. If it detects a condition that would indicate

that it is processing corrupted data structures, it immediately halts processing, sets the

HC Process Error bit in the HC Status register and signals a hardware interrupt to the

system.

This interrupt cannot be disabled through the Interrupt Enable register.

Functional Description

204 Intel ® ICH7 Family Datasheet

Host System Error

The ICH7 sets this bit to 1 when a Parity error, Master Abort, or Target Abort occur.

When this error occurs, the ICH7 clears the Run/Stop bit in the Command register to

prevent further execution of the scheduled TDs. This interrupt cannot be disabled

through the Interrupt Enable register.

5.19.7 USB Power Management

The Host controller can be put into a suspended state and its power can be removed.

This requires that certain bits of information are retained in the resume power plane of

the ICH7 so that a device on a port may w ak e the system. Such a device ma y be a fax-

modem, which will wake up the machine to receive a fax or take a voice message. The

settings of the following bits in I/O space will be maintained when the ICH7 enters the

S3, S4, or S5 states.

When the ICH7 detects a resume event on any of its ports, it sets the corresponding

USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system

wakes up and an SCI generated.

5.19.8 USB Legacy Keyboard Operation

When a USB keyboard is plugged into the system, and a standard keyboard is not, the

system may not boot, and MS-DOS legacy softw are will not run, because the keyboard

will not be identified. The ICH7 implements a series of trapping operations which will

snoop accesses that go to the keyboard controller, and put the expected data from the

USB keyboard into the keyboard controller.

Note: The scheme described below assumes that the keyboard controller (8042 or

equivalent) is on the LPC bus.

This legacy operation is performed through SMM space. Figure 5-10 shows the Enable

and Status path. The latched SMI source (60R, 60W, 64R, 64W) is available in the

Status Register. Because the enable is after the latch, it is possible to check for other

events that didn't necessarily cause an SMI. It is the software's responsibility to

logically AND the value with the appropriate enable bits.

Note also that the SMI is generated before the PCI cycle completes (e.g. , before TRDY#

goes active) to ensure that the processor doesn't complete the cycle before the SMI is

observed. This method is used on MPIIX and has been validated.

The logic also needs to block the accesses to the 8042. If there is an external 8042,

then this is simply accomplished by not activating the 8042 CS. This is simply done by

logically ANDing the four enables (60R, 60W, 64R, 64W) with the 4 types of accesses to

determine if 8042CS should go active. An additional term is required for the “pass-

through” case.

The state table for the diagram is shown in Table 5-47.

Table 5-46. Bits Maintained in Low Power States

Command 00h 3 Enter Global Suspend Mode (EGSM)

Status 02h 2 Resume Detect

Port Status and

Control 10h & 12h

2 Port Enabled/Disabled

6 Resume Detect

8Low-speed Device Attached

12 Suspend

Intel ® ICH7 Family Datasheet 205

Functional Description

Figure 5-10. USB Legacy Keyboard Flow Diagram

Table 5-47. USB Legacy Keyboard State Transitions (Sheet 1 of 2)

Current

State Action Data

Value Next

State Comment

IDLE 64h / Write D1h GateState1 Stand ard D1 command. Cycle passed

through to 8042. SMI# doesn't go active.

PSTATE (offset C0, bit 6) goes to 1.

IDLE 64h / Write Not D1h IDLE Bit 3 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 64h / Read N/A IDLE Bit 2 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 60h / Write Don't Care IDLE Bit 1 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

IDLE 60h / Read N/A IDLE Bit 0 in Config Register determines if cycle

passed through to 8042 and if SMI#

generated.

GateState1 60h / Write XXh GateState2

Cycle passed through to 8042, even if trap

enabled in Bit 1 in Config R egister. No SMI#

generated. PSTATE remains 1. If data value

is not DFh or DDh then the 8042 m ay chose

to ignore it.

KBC Accesses

PCI Config

Read , Writ e

60 READ

Cl ear S MI_60_R

EN_SMI_ON_60R

Comb.

Decoder AND

Same for 60W, 64R, 64W

SMI

To Individual

"Cau sed By"

"Bits"

To PIRQD#

To "Caused By" Bit

AND

EN_PIRQD#

USB_IRQ

Clear U SB _IRQ

EN_SMI_ON_IRQ

Functional Description

206 Intel ® ICH7 Family Datasheet

GateState1 64h / Write D1h GateState1

Cycle passed through to 8042, even if trap

enabled via Bit 3 in Config Register. No SMI#

generated. PSTATE remains 1. Stay in

GateState1 because this is part of the

double-trigger sequence.

GateState1 64h / Write Not D1h ILDE

Bit 3 in Config space determines if cycle

passed through to 8042 and if SMI#

generated. PSTATE goes to 0. If Bit 7 in

Config Register is set, then SMI# should be

generated.

GateState1 60h / Read N/A IDLE

This is an invalid sequence. Bit 0 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState1 64h / Read N/A GateState1 Just stay in same state. Generate an SMI# if

enabled in Bit 2 of Config Register. PSTATE

remains 1.

GateState2 64 / Write FFh IDLE

Standard end of sequence. Cycle passed

through to 8042. PSTATE goes to 0. Bit 7 in

Config Space determines if SMI# should be

generated.

GateState2 64h / Write Not FFh IDLE

Improper end of sequence. Bit 3 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState2 64h / Read N/A GateState2 Just stay in same state. Generate an SMI# if

enabled in Bit 2 of Config Register. PSTATE

remains 1.

GateState2 60h / Write XXh IDLE

Improper end of sequence. Bit 1 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

GateState2 60h / Read N/A IDLE

Improper end of sequence. Bit 0 in Config

to 8042 and if SMI# generated. PST A TE goes

to 0. If Bit 7 in Config Register is set, then

SMI# should be generated.

Table 5-47. USB Legacy Keyboard State Transitions (Sheet 2 of 2)

Current

State Action Data

Value Next

State Comment

Intel ® ICH7 Family Datasheet 207

Functional Description

5.20 USB EHCI Host Controller (D29:F7)

The ICH7 contains an Enhanced Host Controller Interface (EHCI) host controller which

supports up to eight USB 2.0 high-speed root ports. USB 2.0 allows data tr ansfers up to

480 Mb/s using the same pins as the eight USB full-speed/low-speed ports. The ICH7

contains port-routing logic that determines whether a USB port is controlled by one of

the UHCI controllers or by the EHCI controller. USB 2.0 based Debug Port is also

implemented in the ICH7.

A summary of the key architectural differences between the USB UHCI host controllers

and the EHCI host controller are shown in Table 5-48.

5.20.1 EHC Initialization

The following descriptions step through the expected ICH7 Enhanced Host Controller

(EHC) initialization sequence in chronological order, beginning with a complete power

cycle in which the suspend well and core well have been off.

5.20.1.1 BIOS Initialization

BIOS performs a number of platform customization steps after the core well has

powered up. Contact your Intel Field Representative for additional ICH7 BIOS

information.

5.20.1.2 Driver Initialization

See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal

Serial Bus, Revision 1.0.

Table 5-48. UHCI vs. EHCI

Parameter USB UHCI USB EHCI

Accessible by I/O space Memory Space

Memory Data Structure Single linked list Separated in to Periodic and Asynchronous

lists

Differential Signal ing Voltage 3.3 V 400 m V

Ports per Controller 2 8

Functional Description

208 Intel ® ICH7 Family Datasheet

5.20.1.3 EHC Resets

In addition to the standard ICH7 hardware resets, portions of the EHC are reset by the

HCRESET bit and the tr ansition from th e D3 HOT device power management state to the

D0 state. The effects of each of these resets are:

If the detailed register descriptions give exceptions to these rules, those exceptions

override these rules. This summary is provid ed to help explain the reasons for the reset

policies.

5.20.2 Data Structures in Main Memory

See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1.0 for details.

5.20.3 USB 2.0 Enhanced Host Controller DMA

The ICH7 USB 2.0 EHC implements three sources of USB packets. They are, in order of

priority on USB during each microframe:

1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),

2. The Periodic DM A engine, and

3. The Asy nc hronous DM A en gi ne . The I CH 7 always performs any currently-pendi ng

debug port transaction at the beginning of a microframe, followed by any pending

periodic traffic for the current microframe. If there is time left in the microframe,

then the EHC performs any pending asynchronous traffic until the end of the

microframe (EOF1). Note that the debug port traffic is only presented on one port

(Port #0), while the other ports are idle during this time.

5.20.4 Data Encoding and Bit Stuffing

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

5.20.5 Packet Formats

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

The ICH7 EHCI allows entrance to USB test modes, as defined in the USB 2.0

specification, including Test J, Test P acket, etc. However, note that the ICH7 Test Pack et

test mode interpacket gap timing may not meet the USB 2.0 specification.

Reset Does Reset Does not Reset Comments

HCRESET bit set.

Memory space

registers except

Structural

Parameters (which is

written by BIOS).

Configuration

registers.

The HCRESET must only affect

registers that the EHCI driver

controls. PCI Configuration

space and BIOS-programmed

parameters can not be reset.

Software writes

the Device Power

State from D3HOT

(11b) to D0

(00b).

Core well registers

(except BIOS-

programmed

registers).

Suspend well

registers; BIOS-

programmed core

well registers.

The D3-to-D0 transition must

not cause wake information

(suspend well) to be lost. It also

must not clear BIOS-

programmed registers because

BIOS may not be i nvo ked

following the D3-to-D0

transition.

Intel ® ICH7 Family Datasheet 209

Functional Description

5.20.6 USB 2.0 Interrupts and Error Conditions

Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial

Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that

cause them. All error conditions that the EHC detects can be reported through the EHCI

Interrupt status bits. Only ICH7-specific interrupt and error-reporting behavior is

documented in this section. The EHCI Interrupts Section must be read first, followed by

this section of the datasheet to fully comprehend the EHC interrupt and error-reporting

functionality.

• Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer

Error can not occur on the ICH7.

• Master Abort and Target Abort responses from hub interface on EHC-initiated read

packets will be treated as Fatal Host Errors. The EHC halts when these conditions

are encountered.

• The ICH7 may assert the interrupts which are based on the interrupt threshold as

soon as the status for the last complete transaction in the interrupt interval has

been posted in the internal write buffers. The requirement in the Enhanced Host

Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the

status is written to memory) is met internally, even though the write may not be

seen on DMI before the interrupt is asserted.

• Since the ICH7 supports the 1024-element Frame List size, the Frame List Rollover

interrupt occurs every 1024 milliseconds.

• The ICH7 delivers interrupts using PIRQH#.

• The ICH7 does no t modify the CERR count on an Interrupt IN when the “Do

Complete-Split” execution criteria are not met.

• For complete-split transactions in the P eriodic list, the “Missed Microfr ame” bit does

not get set on a control-structure-fetch that fails the late-start test. If subsequent

accesses to that control structure do not fail the late-start test, then the “Missed

Microframe” bit will get set and written back.

5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads

If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The

following actions are taken when this occurs:

• The Host System Error status bit is set

• The DMA engines are halted after completing up to one more transaction on the

USB interface

• If enabled (by the Host System Error Enable), then an interrupt is generated

• If the status is Master Abort, then the Received Master Abort bit in configuration

space is set

• If the status is Target Abort, then the Received Target Abort bit in configuration

space is set

• If enabled (by the SERR Enable bit in the function’ s configuration space), then the

Signaled System Error bit in configuration bit is set.

Functional Description

210 Intel ® ICH7 Family Datasheet

5.20.7 USB 2.0 Power Management

5.20.7.1 Pause Feature

This feature allows platforms (especially mobile systems) to dynamically enter low-

power states during brief periods when the system is idle (i.e., between keystrokes).

This is useful for enabling power management features like Intel SpeedStep technology

in the ICH7 mobile/ultra mobile only. The policies for entering these states typically are

based on the recent history of system bus activity to incrementally enter deeper power

management states. Normally, when the EHC is enabled, it regularly accesses main

memory while traversing the DMA schedules looking for work to do; this activity is

viewed by the power management software as a non-idle system, thus preventing the

power managed states to be entered. Suspending all of the enabled ports can prevent

the memory accesses from occurring, but there is an inherent latency overhead with

entering and exiting the suspended state on the USB ports that makes this

unacceptable for the purpose of dynamic power management. As a result, the EHCI

software drivers are allowed to pause the EHC’s DMA engines when it knows that the

traffic patterns of the attached devices can afford the delay. The pause only prevents

the EHC from generating memory accesses; the SOF packets continue to be generated

on the USB ports (unlike the suspended state).

5.20.7.2 Suspend Feature

The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,

Section 4.3 describes the details of Port Suspend and Resume.

5.20.7.3 ACPI Device States

The USB 2.0 function only supports the D0 and D3 PCI Power Management states.

Notes regarding the ICH7 implementation of the Device States:

1. The EHC hardware does not inherently consume any more power when it is in the

D0 state than it does in the D3 state. However, software is required to suspend or

disable all ports prior to entering the D3 state such that the maximum power

consumption is reduced.

2. In the D0 state, all implemented EHC features are enabled.

3. In the D3 state, accesses to the EHC memory-mapped I/O r ange will master abort.

Note that, since the Debug Port uses the same memory range, the Debug Port is

only operational when the EHC is in the D0 state.

4. In the D3 state, the EHC interrupt must not assert for any reason. The internal

PME# signal is used to signal wake events, etc.

5. When the Device Power State field is written to D0 from D3, an internal reset is

generated. See section EHC Resets for general rules on the effects of this reset.

6. Attempts to write any o ther value into the Device Power State field other than 00b

(D0 state) and 11b (D3 state) will complete normally without changing the current

value in this field.

Intel ® ICH7 Family Datasheet 211

Functional Description

5.20.7.4 ACPI System States

The EHC behavior as it relates to other power management states in the system is

summarized in the following list:

— The System is alw ays in the S0 state when the EHC is in the D0 state. However,

when the EHC is in the D3 state, the system may be in any power management

state (including S0).

— When in D0, the Pause feature (See Section 5.20.7.1) enables dynamic

processor low-power states to be entered.

— The PLL in the EHC is disabled when entering the S3HOT state (48 MHz clock

stops), or the S3COLD/S4/S5 states (core power turns off).

— All core well logic is reset in the S3/S4/S5 states.

5.20.7.5 Mobile/Ultra Mobile Only Considerations

The ICH7 USB 2.0 implementation does not behave differently in the mobile

configurations versus the desktop configurations. However, some features may be

especially useful for the mobile configurations.

• If a system (e.g., mobile) does not implement all eight USB 2.0 ports, the ICH7

provides mechanisms for changing the structur al parameters of the EHC and hiding

unused UHCI controllers. See the Intel® ICH7 BIOS Specification for information on

how BIOS should configure the ICH7.

• Mobile/ultra mobile systems may want to minimize the conditions that will w ake the

system. The ICH7 implements the “Wake Enable” bits in the Port Status and

Control registers, as specified in the EHCI spec, for this purpose.

• Mobile/Ultra mobile systems may want to cut suspend well power to some or all

USB ports when in a low-power state. The ICH7 implements the optional Port Wake

Capability Register in the EHC Configuration Space for this platform-specific

information to be communicated to software.

5.20.8 Interaction with UHCI Host Controllers

The Enhanced Host controller shares the eight USB ports with four UHCI Host

controllers in the ICH7. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1

shares ports 2 and 3; the UHC at D29:F2 shares ports 4 an d 5; and the UHC at D29:F3

shares ports 6 and 7 with the EHC. There is very little interaction between the

Enhanced and the UHCI controllers other than the muxing control which is provided as

part of the EHC.Figure 5-11 shows the USB Port Connections at a conceptual level.

5.20.8.1 Port-Routing Logic

Integrated into the EHC functionality is port-routing logic, which performs the muxing

between the UHCI and EHCI host controllers. The ICH7 conceptually implements this

logic as described in Section 4.2 of the Enhanced Host Controller Interface Specification

for Universal Serial Bus, Revision 1.0. If a device is connected that is not capable of

USB 2.0’s high-speed signaling protocol or if the EHCI softw are drivers are not present

as indicated by the Configured Flag, then the UHCI controller owns the port. Owning

the port means that the differential output is driven by the owner and the input stream

is only visible to the owner. The host controller that is not the owner of the port

internally sees a disconnected port.

Functional Description

212 Intel ® ICH7 Family Datasheet

Note that the port-routing logic is the only block of logic within the ICH7 that observes

the physical (real) connect/disconnect information. The port status logic inside each of

the host controllers observes the electrical connect/disconnect information that is

generated by the port-routing logic.

Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and

EHCI host controllers. The other USB functional signals are handled as follows:

• The Overcurrent inputs (OC[7:0]#) are directly routed to both controllers. An

overcurrent event is recorded in both controllers’ status registers.

The Port-Routing logic is implemented in the Suspend power well so that re-

enumeration and

re-mapping of the USB ports is not required following entering and exiting a system

sleep state in which the core power is turned off.

The ICH7 also allows the USB Debug Port traffic to be routed in and out of Port #0.

When in this mode, the Enhanced Host controller is the owner of Port #0.

Figure 5-11. Intel® ICH7-USB Port Connections

UHCI #3

(D29:F3) UCHI #0

(D29:F0)

UHCI #1

(D29:F1)

UHCI #2

(D29:F2)

Enhanced H os t C on troller Logic

Debug

Port

Port 7

Port 3

Port 4

Port 5

Port 6

Port 2

Port 1

Port 0

Intel ® ICH7 Family Datasheet 213

Functional Description

5.20.8.2 Device Connects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision

1.0 describes the details of handling Device Connects in Section 4.2. There are four

general scenarios that are summarized below.

1. Configure Flag = 0 and a full-speed/low-speed-only Device is connected

— In this case, the UHC is the owner of the port both before and after the connect

occurs. The EHC (except for the port-routing logic) does not see the connect

occur. The UHCI driver handles the connection and initialization process.

2. Configure Flag = 0 and a high-speed-capable Device is connected

— In this case, the UHC is the owner of the port both before and after the connect

occurs. The EHC (except for the port-routing logic) not see the connect occur.

The UHCI driver handles the connection and initialization process. Since the

UHC does not perform the high-speed chirp handshake, the device operates in

compatible mode.

3. Configure Flag = 1 and a full-speed/low-speed-only Device is connected

— In this case, the EHC is the owner of the port before the connect occurs. The

EHCI driver handles the connection and performs the port reset. After th e reset

process completes, the EHC hardware has cleared (not set) the Port Enable bit

in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the P ort Owner

bit in the same register, causing the UHC to see a connect event and the EHC to

see an “electrical” disconnect event. The UHCI driver and hardware handle the

connection and initialization process from that point on. The EHCI driver and

hardware handle the perceived disconnect.

4. Configure Flag = 1 and a high-speed-capable Device is connected

— In this case, the EHC is the owner of the port before, and remains the owner

after, the connect occurs. The EHCI driv er handles the connection and performs

the port reset. After the reset process completes, the EHC hardw are has set the

P ort Enable bit in the EHC’s POR TSC register. The port is functional at this point.

The UHC continues to see an unconnected port.

5.20.8.3 Device Disconnects

The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision

1.0 describes the details of handling Device Connects in Section 4.2. There are three

general scenarios that are summarized below.

1. Configure Flag = 0 and the device is disconnected

— In this case, the UHC is the owner of the port both before and after the

disconnect occurs. The EHC (except for the port -routing logic) not see a device

attached. The UHCI driver handles disconnection process.

2. Configure Flag = 1 and a full-speed/low-speed-capable Device is disconnected

— In this case, the UHC is the owner of the port before the disconnect occurs. The

disconnect is reported by the UHC and serviced by the associated UHCI driver.

The port-routing logic in the EHC cluster forces the Port Owner bit to 0,

indicating that the EHC owns the unconnected port.

3. Configure Flag = 1 and a high-speed-capable Device is disconnected

— In this case, the EHC is the owner of the port before, and remains the owner

after, the disconnect occurs. The EHCI hardware and driver handle the

disconnection process. The UHC does not see a device attached.

Functional Description

214 Intel ® ICH7 Family Datasheet

5.20.8.4 Effect of Resets on Port-Routing Logic

As mentioned above, the Port Routing logic is implemented in the suspend power well

so that remuneration and re-mapping of the USB ports is not required following

entering and exiting a system sleep state in which the core power is turned off.

5.20.9 USB 2.0 Legacy Keyboard Operation

The ICH7 must support the possibility of a keyboard downstream from either a full-

speed/low-speed or a high-speed port. The description of the legacy keyboard support

is unchanged from USB 1.1 (See Section 5.19.8).

The EHC provides the basic ability to generate SMIs on an interrupt event, along with

more sophisticated control of the generation of SMIs.

5.20.10 USB 2.0 Based Debug Port

The ICH7 supports the elimination of the legacy COM ports by providing the ability for

new debugger software to interact with devices on a USB 2.0 port.

High-level restrictions and features are:

• Operational before USB 2.0 drivers are loaded.

• Functions even when the port is disabled.

• Works even though non-configured port is default-routed to the UHCI. Note that

the Debug Port can not be used to debug an issue that requires a full-speed/low-

speed device on Port #0 using the UHCI drivers.

• Allows normal system USB 2.0 traffic in a system that may only hav e one USB port.

• Debug Port device (DPD) must be high-speed capable and connect directly to Port

#0 on ICH7 systems (e.g., the DPD cannot be connected to Port #0 thru a hub).

• Debug Port FIFO always makes forward progress (a bad status on USB is simply

presented back to software).

• The Debug Port FIFO is only given one USB access per microframe.

The Debug port facilitates operating system and device driver debug. It allows the

software to communicate with an external console using a USB 2.0 connection.

Because the interface to this link does not go through the normal USB 2.0 stack, it

allows communication with the external console during cases where the operating

system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is

being debugged. Specific features of this implementation of a debug port are:

• Only works with an external USB 2.0 debug device (console)

• Implemented for a specific port on the host controller

• Operational anytime the port is not suspended AND the host controller is in D0

power state.

• Capability is interrupted when port is driving USB RESET

Reset Event Effect on Configure Flag Effect on Port Owner Bits

Suspend Well Reset cleared (0) set (1)

Core Well Reset no effect no effect

D3-to-D0 Reset no effect no effect

HCRESET cleared (0) set (1)

Intel ® ICH7 Family Datasheet 215

Functional Description

5.20.10.1 Theory of Operation

There are two operational modes for the USB debug port:

1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard

host controller driver. In Mode 1, the Debug Port controller is required to generate a

“keepalive” packets less than 2 ms apart to keep the attached debug device from

suspending. The keepalive packet should be a standalone 32-bit SYNC field.

2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit

is 1). In Mode 2, the normal transmission of SOF packets will keep the debug

device from suspending.

Behavioral Rules

1. In both modes 1 and 2, the Debug Port controller must check for software

requested debug transactions at least every 125 microseconds.

2. If the debug port is enabled by the debug driver, and the standard host controller

driver resets the USB port, USB debug transactions are held off for the duration of

the reset and until after the first SOF is sent.

3. If the standard host controller driver suspends the USB port, then USB debug

transactions are held off for the duration of the suspend/resume sequence and until

after the first SOF is sent.

4. The ENABLED_CNT bit in the debug register space is independent of the similar

port control bit in the associated Port Status and Control register.

Table 5-49 shows the debug port behavior related to the state of bits in the debug

registers as well as bits in the associated Port Status and Control register.

Table 5-49. Debug Port Behavior (Sheet 1 of 2 )

OWNER_CNT ENABLED_CT Port

Enable Run /

Stop Suspend Debug Port Behavior

0XXXX

Debug port is not being used.

Normal operation.

10XXX

Debug port is not being used.

Normal operation.

1100X

Debug port in Mode 1. SYNC

keepalives sent plus debug

traffic

1101X

Debug port in Mode 2. SOF

(and only SOF) is sent as

keepalive. Debug traffic is

also sent. Note that no other

normal traffic is sent out this

port, because the port is not

enabled.

11100

Inv alid. Host controller dri ver

should not put the controller

into this state (enabled, not

running and not suspended).

Functional Description

216 Intel ® ICH7 Family Datasheet

5.20.10.1.1 OUT Transactions

An Out transaction sends data to the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is set

The sequence of the transaction is:

1. Software sets the appropriate values in th e foll o wing bits:

— USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— DATA_BUFFER[63:0]

— TOKEN_PID_CNT[7:0]

—SEND_PID_CNT[15:8]

—DATA_LEN_CNT

— WRITE_READ#_CNT (note: this will always be 1 for OUT transactions)

— GO_CNT (note: this will always be 1 to initiate the transaction)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID _CNT field

— USB_ADDRESS_CNT field

— USB_ENDPOINT_CNT field

— 5-bit CRC field

3. After sending the token packet, the debug port controller sends a data packet

consisting of:

—SYNC

— SEND_PID_CNT field

— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER

—16-bit CRC

NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be

included in the packet.

11101

Port is suspended. No debug

traffic sent.

11110

Debug port in Mode 2. Debug

traffic is interspersed with

normal traffic.

11111

Port is suspended. No debug

traffic sent.

Table 5-49. Debug Port Behavior (Sheet 2 of 2)

OWNER_CNT ENABLED_CT Port

Enable Run /

Stop Suspend Debug Port Behavior

Intel ® ICH7 Family Datasheet 217

Functional Description

4. After sending the data packet, the controller waits for a handshake response from

the debug device.

• If a handshake is received, the debug port controller:

— a. Places the received PID in the RECEIVED_PID_STS field

— b. Resets the ERROR_GOOD#_STS bit

— c. Sets the DONE_STS bit

• If no handshake PID is received, the debug port controller:

— a. Sets the EXCEPTION_STS field to 001b

— b. Sets the ERROR_GOOD#_STS bit

— c. Sets the DONE_STS bit

5.20.10.1.2 IN Transactions

An IN transaction receives data from the debug device. It can occur only when the

following are true:

• The debug port is enabled

• The debug software sets the GO_CNT bit

• The WRITE_READ#_CNT bit is reset

The sequence of the transaction is:

1. Software sets the appropriate values in the following bits:

—USB_ADDRESS_CNF

—USB_ENDPOINT_CNF

— TOKEN_PID_CNT[7:0]

—DATA_LEN_CNT

— WRITE_READ#_CNT (note: this will always be 0 for IN transactions)

— GO_CNT (note: this will always be 1 to initiate the transaction)

2. The debug port controller sends a token packet consisting of:

—SYNC

— TOKEN_PID_CNT field

— USB_ADDRESS_CNT field

—USB_ENDPOINT_CNT field

— 5-bit CRC field.

3. After sending the token packet, the debug port controller w aits for a response from

the debug device.

If a response is received:

— The received PID is placed into the RECEIVED_PID_STS field

— Any subsequent bytes are placed into the DATA_BUFFER

— The DATA_LEN_CNT field is updated to show the number of bytes that were

received after the PID.

4. If valid pack et was received from the device that was one byte in length (indicating

it was a handshake packet), then the debug port controller:

— R esets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

Functional Description

218 Intel ® ICH7 Family Datasheet

5. If valid packet w as received from the device that was more than one byte in length

(indicating it was a data packet), then the debug port controller:

— Transmits an ACK handshake packet

— Resets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit

6. If no valid packet is received, then the debug port controller:

— Sets the EXCEPTION_STS field to 001b

— Sets the ERROR_GOOD#_STS bit

— Sets the DONE_STS bit.

5.20.10.1.3 Debug Software

Enabling the Debug Port

There are two mutually exclusive conditions that debug software must address as part

of its startup processing:

• The EHCI has been initialized by system software

• The EHCI has not been initialized by system software

Debug software can determine the current ‘initialized’ state of the EHCI by examining

the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then

system software has initialized the EHCI. Otherwise the EHCI should not be considered

initialized. Debug software will initialize the debug port registers depending on the

state the EHCI. However, before this can be accomplished, debug software must

determine which root USB port is designated as the debug port.

Determining the Debug Port

Debug software can easily determine which USB root port has been designated as the

debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters

0001=port 0).

Debug Software Startup with Non-Initialized EHCI

Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,

the Current Connect Status bit in the appropriate (See Determining the Debug Port)

PORTSC register is set. If the Current Connect Status bit is not set, then debug

software may choose to terminate or it may choose to wait until a device is connected.

If a device is connected to the port, then debug software must reset/enable the port.

Debug software does this by setting and then clearing the Port Reset bit the PORTSC

clearing the Port Reset bit. Due to possible delays, this bit may not change to 0

immediately; reset is complete when this bit reads as 0. Software must not continue

until this bit reads 0.

If a high-speed device is attached, the EHCI will automatically set the Port Enabled/

Disabled bit in the PORTSC register and the debug software can proceed. Debug

software should set the ENABLED_CNT bit in the Debug Port Control/Status register,

and then reset (clear) the P ort Enabled/Disabled bit in the PORTSC register (so that the

system host controller driver does not see an enabled port when it is first loaded).

Intel ® ICH7 Family Datasheet 219

Functional Description

Debug Software Startup with Initialized EHCI

Debug software can attempt to use the debug port if the Current Connect Status bit in

the appropriate (See Determining the Debug Port) PORTSC register is set. If the

Current Connect Status bit is not set, then debug software may choose to terminate or

it may choose to wait until a device is connected.

If a device is connected, then debug software must set the OWNER_CNT bit and then

the ENABLED_CNT bit in the Debug Port Control/Status register.

Determining Debug Peripheral Presence

After enabling the debug port functionality, debug software can determine if a debug

peripheral is attached by attempting to send data to the debug peripheral. If all

attempts result in an error (Exception bits in the Debug Port Control/Status register

indicates a Transaction Error), th en the attached device is not a debug peripheral. If the

debug port peripheral is not present, then debug software may choose to terminate or

it may choose to wait until a debug peripheral is connected.

5.21 SMBus Controller (D31:F3)

The ICH7 provides an System Management Bus (SMBus) 2.0 host controller as well as

an SMBus Slave Interface. The host controller provides a mechanism for the processor

to initiate communications with SMBus peripher als (slaves). The ICH7 is also capable of

operating in a mode in which it can communicate with I2C compatible devices.

The ICH7 can perform SMBus messages with either packet error checking (PEC)

enabled or disabled. The actual PEC calculation and checking is performed in hardware

by the ICH7.

The Slave Interface allows an external master to read from or write to the ICH7. Write

cycles can be used to cause certain events or pass messages, and the read cycles can

be used to determine the state of various status bits. The ICH7’s internal host

controller cannot access the ICH7’s internal Slave Interface.

The ICH7 SMBus logic exists in Device 31:Function 3 configuration space, and consists

of a transmit data path, and host controller. The transmit data path provides the data

flow logic needed to implement the seven different SMBus command protocols and is

controlled by the host controller. The ICH7 SMBus controller logic is clocked by RTC

clock.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host

controller commands through software, except for the new Host Notify command

(which is actually a received message).

The programming model of the host controller is combined into two portions: a PCI

configuration portion, and a system I/O mapped portion. All static configuration, such

as the I/O base address, is done via the PCI configuration space. Real-time

programming of the Host interface is done in system I/O space.

The ICH7 SMBus host controller checks for parity errors as a target. If an error is

detected, the detected parity error bit in the PCI Status Register (Device 31:Function

3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device

31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit

in the PCI Status Register (bit 14) is set.

Functional Description

220 Intel ® ICH7 Family Datasheet

5.21.1 Host Controller

The SMBus host controller is used to send commands to other SMBus slave devices.

Software sets up the host controller with an address, command, and, for writes, data

and optional PEC; and then tells the controller to start. When the controller has finished

transmitting data on writes, or receiving data on reads, it generates an SMI# or

interrupt, if enabled.

The host controller supports 8 command protocols of the SMBus interface (see System

Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,

Receive Byte, Write Byte/W ord, R e ad Byte/Word, Process Call, Block R ead/Write, Block

Write–Block Read Process Call, and Host Notify.

The SMBus host controller requires that the various data and command fields be setup

for the type of command to be sent. When software sets the ST AR T bit, the SMBus Host

controller performs the requested transaction, and interrupts the processor (or

generates an SMI#) when the transaction is completed. Once a START command has

been issued, the values of the “active registers” (Host Control, Host Command,

Transmit Slave Address, Data 0, Data 1) should not be changed or read until the

interrupt status bit (INTR) has been set (indicating the completion of the command).

Any register values needed for computation purposes should be saved prior to issuing

of a new command, as the SMBus host controller updates all registers while completing

the new command.

Using the SMB host controller to send commands to the ICH7’s SMB slave port is

supported. The ICH7 supports the System Management Bus (SMBus) Specification,

Version 2.0. Slave functionality, including the Host Notify protocol, is available on the

SMBus pins. The SMLink and SMBus signals should not be tied together externally.

5.21.1.1 Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to

determine the progress of the command. While the command is in operation, the

HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set

in the Host Status Register. If the device does not respond with an acknowledge, and

the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the

Host Control Register while the command is running, the transaction will stop and the

FAILED bit will be set.

Quick Command

When programmed for a Quick Command, the Transmit Slave Address Register is sent.

The PEC byte is not appended to the Quick Protocol. Software should force the PEC_EN

bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0

when running this command. See section 5.5.1 of the System Management Bus

(SMBus) Specification, Version 2.0 for the format of the protocol.

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command

Registers are sent

For the Receive Byte command, the Transmit Slave Address Register is sent. The data

received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when

running this command.

The Receive Byte is similar to a Send Byte, the only difference is the direction of data

transfer. See sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus)

Specification, Ve rsion 2.0 for the format of the protocol.

Intel ® ICH7 Family Datasheet 221

Functional Description

Write Byte/Word

The first byte of a W rite Byte/Word access is the command code. The next 1 or 2 bytes

are the data to be written. When programmed for a Write Byte/Word command, the

Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,

the Data1 Register is sent on a Write Word command. Software must force the I2C_EN

bit to 0 when running this command. See section 5.5.4 of the System Management Bus

(SMBus) Specification, Version 2.0 for the format of the protocol.

Read Byte/Word

R eading data is slightly more complicated than writing data. First the ICH7 must write a

command to the slave device. Then it must follow that command with a repeated start

condition to denote a read from that device's address. The slave then returns 1 or 2

bytes of data. Software must force the I2C_EN bit to 0 when running this command.

When programmed for the read byte/word command, the Transmit Slave Address and

Device Command Registers are sent. Data is received into the DAT A0 on the read byte,

and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System

Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.

Process Call

The process call is so named because a command sends data and w aits for the slav e to

return a value dependent on that data. The protocol is simply a Write W ord followed by

a Read Word, but without a second command or stop condition.

When programmed for the Process Call command, the ICH7 transmits the Transmit

Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the

device is stored in the DATA0 and DATA1 registers. The Process Call command with

I2C_EN set and the PEC_EN bit set produces undefined results. Software must force

either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For process call command, the value written into bit 0 of the Transmit Slave Address

Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code

(bits 18:11 in the bit sequence) are not sent - as a result, the slave will not

acknowledge (bit 19 in the sequence).

Block Read/Wri te

The ICH7 contains a 32-byte buffer for read and write data which can be enabled by

setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a

single byte of buffering. This 32-byte buffer is filled with write data before

transmission, and filled with read data on reception. In the ICH7, the interrupt is

generated only after a transmission or reception of 32 bytes, or when the entire byte

count has been transmitted/received.

The byte count field is transmitted but ignored by the ICH7 as software will end the

transfer after all bytes it cares about have been sent or received.

For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and

AAC bits to 0 when running this command.

Functional Description

222 Intel ® ICH7 Family Datasheet

The block write begins with a slave address and a write condition. After the command

code the ICH7 issues a byte count describing how many more bytes will follow in the

message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),

followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is

allowed to transfer a maximum of 32 data bytes.

When programmed for a block write command, the Transmit Slave Address, Device

Command, and Data0 (count) registers are sent. Data is then sent from the Block Data

Byte register; the total data sent being the v alue stored in the Data0 Register. On block

read commands, the first byte received is stored in the Data0 register, and the

remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the

System Management Bus (SMBus) Specification, Version 2.0 for the format of the

protocol.

Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.

The ICH7 will still send the number of bytes (on writes) or receive the number of bytes

(on reads) indicated in the DAT A0 register. However, it will not send the contents of the

DATA0 register as part of the message. Also, the Block Write protocol sequence

changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a

result, the slave will not acknowledge (bit 28 in the sequence).

I2C Read

This command allows the ICH7 to perform block reads to certain I2C devices, such as

serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.

However, this does not allow access to devices using the I2C “Combined Format” that

has data bytes after the address. Typically these data bytes correspond to an offset

(address) within the serial memory chips.

Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read

command with the PEC_EN bit set produces undefined results. Software must force

both the PEC_EN and AAC bit to 0 when running this command.

For I2C Read command, the value written into bit 0 of the Transmit Slave Address

Intel ® ICH7 Family Datasheet 223

Functional Description

The format that is used for the command is shown in Table 5-50.

The ICH7 will continue reading data from the peripheral until the NAK is received.

Block Write–Block Read Process Call

The block write-block read process call is a two-part message. The call begins with a

slave address and a write condition. After the command code the host issues a write

byte count (M) that describes how many more bytes will be written in the first part of

the message. If a master has 6 bytes to send, the byte count field will have the value 6

(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.

The second part of the message is a block of read data beginning with a repeated start

condition followed by the slave address and a Read bit. The next byte is the read byte

count (N), which may differ from the write byte count (M). The read byte count (N)

cannot be 0.

The combined data payload must not exceed 32 bytes. The byte length restrictions of

this process call are summarized as follows:

•M ≥ 1 byte

•N ≥ 1 byte

•M + N ≤ 32 bytes

The read byte count does not include the PEC byte. The PEC is computed on the total

message beginning with the first slave address and using the normal PEC

computational rules. It is highly recommended that a PEC byte be used with the Block

Write-Block Read Process Call. Software must do a read to the command register

(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.

Table 5-50. I2C Block Read

Bit Description

1Start

8:2 Slave Address — 7 bits

9Write

10 Acknowledge from slave

18:11 Send DATA1 register

19 Acknowledge from slave

20 Repeated Start

27:21 Slave Address — 7 bits

28 Read

29 Acknowledge from slave

37:30 Data byte 1 from slave — 8 bits

38 Acknowledge

46:39 Data byte 2 from slave — 8 bits

47 Acknowledge

–Data bytes from slave /

Acknowledge

– Data byte N from slave — 8 bits

– NOT Acknowledge

–Stop

Functional Description

224 Intel ® ICH7 Family Datasheet

Note that there is no STOP condition before the repeated START condition, and that a

NACK signifies the end of the read transfer.

Note: E32B bit in the Auxiliary Control register must be set when using this protocol.

See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2. 0

for the format of the protocol.

5.21.2 Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the

SMBDATA line low to signal a start condition. The ICH7 continuously monitors the

SMBDAT A lin e. When the ICH7 is attempting to driv e the bus to a 1 by letting go of the

SMBDA TA line, and it samples SMBDAT A low , th en some other master is driving the bus

and the ICH7 will stop transferring data.

If the ICH7 sees that it has lost arbitration, the condition is called a collision. The ICH7

will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an

interrupt or SMI#. The processor is responsible for restarting the transaction.

When the ICH7 is a SMBus master, it drives the clock. When the ICH7 is sending

address or command as an SMBus master, or data bytes as a master on writes, it drives

data relative to the clock it is also driving. It will not start toggling the clock until the

start or stop condition meets proper setup and hold time. The ICH7 will also provide

minimum time between SMBus transactions as a master.

Note: The ICH7 supports the same arbitration protocol for both the SMBus and the S ystem

Management (SMLINK) interfaces.

5.21.3 Bus Timing

5.21.3.1 Clock Stretching

Some devices may not be able to handle their clock toggling at the rate that the ICH7

as an SMBus master would like. They have the capability of stretching the low time of

the clock. When the ICH7 attempts to release the clock (allowing the c lock to go high),

the clock will remain low for an extended period of time.

The ICH7 monitors the SMBus clock line after it releases the bus to determine whether

to enable the counter for the high time of the clock. While the bus is still low, the high

time counter must not be enabled. Similarly, the low period of the clock can be

stretched by an SMBus master if it is not ready to send or receive data.

5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an

acknowledge, or holds the clock lower than the allowed time-out time, the transaction

will time out. The ICH7 will discard the cycle and set the DEV_ERR bit. The time out

minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH7 will start

after the last bit of data is transferred by the ICH7 and it is waiting for a response.

The 25 ms timeout counter will not count under the following conditions:

1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set

2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that

the system has not locked up).

Intel ® ICH7 Family Datasheet 225

Functional Description

5.21.4 Interrupts / SMI#

The ICH7 SMBus controller uses PIRQB# as its interrupt pin. However, the system can

alternatively be set up to generate SMI# instead of an interrupt, by setting the

SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).

Table 5-52 and Table 5-53 specify how the various enable bits in the SMBus function

control the generation of th e interrupt, Host and Slav e SMI, and Wake internal signals.

The rows in the tables are additive, which means that if more than one row is true for a

particular scenario then the Results for all of the activated rows will occur.

Table 5-51. Enable for SMBALE RT#

Event

INTREN

(Host Control

I/O Register,

Offset 02h,

Bit 0)

SMB_SMI_EN

(Host

Configuration

D31:F3:Offset

40h, Bit 1)

SMBALERT_DIS

(Slave Command

I/O Register,

Offset 11h, Bit 2)

Result

SMBALERT#

asserted low

(always

reported in

Host Status

XX XWake generated

X1 0

Slave SMI#

generated

(SMBUS_SMI_STS)

10 0

Interrupt

generated

Table 5-52. Enables for SMBus Slave Write and SMBus Host Events

Event

INTREN (H os t

Control I/O

02h, Bit 0)

SMB_SMI_EN (Host

Configuration

D31:F3:Offset 40h,

Bit1)

Event

Slave Write to

Wake/SMI#

Command XX

Wake generated when

asleep.

Slave SMI# generated when

awake (SMBUS_SMI_STS).

Slave Write to

SMLINK_SLAVE_S

MI Command XX

Slave SMI# generated when

in the S0 state

(SMBUS_SMI_STS)

Any combination of

Host Status

asserted

0XNone

1 0 Interrupt generated

11Host SMI# generated

Functional Description

226 Intel ® ICH7 Family Datasheet

5.21.5 SMBALERT#

SMBALERT# is multiplexed with GPIO11. When enable and the signal is asserted, The

ICH7 can generate an interrupt, an SMI#, or a wake event from S1–S5.

Note: Any event on SMBALERT# (regardless whether it is programmed as a GPI or not),

causes the event message to be sent in heartbeat mode.

5.21.6 SMBus CRC Generation and Checking

If the AAC bit is set in the Auxiliary Control register, the ICH7 automatically calculates

and drives CRC at the end of the transmitted packet for write cycles, and will check the

CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The

PEC bit must not be set in the Host Control register if this bit is set, or unspecified

behavior will result.

If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the

Auxiliary Status register at offset 0Ch will be set.

5.21.7 SMBus Slave Interface

The ICH7’ s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic will

not generate or handle receiving the PEC byte and will only act as a Legacy Alerting

Protocol device. The slave interface allows the ICH7 to decode cycles, and allows an

external microcontroller to perform specific actions. Key features and capabilities

include:

• Supports decode of three types of messages: Byte Write, Byte Read, and Host

Notify.

• Receive Slave Address register: This is the address that the ICH7 decodes. A

default value is provided so that the slave interface can be used without the

processor having to program this register.

• Receive Slave Data register in the SMBus I/O space that includes the data written

by the external microcontroller.

• Registers that the external microcontroller can read to get the state of the ICH7.

• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due

to the reception of a message that matched the slave address.

— Bit 0 of the Slave Status Register for the Host Notify command

— Bit 16 of the SMI Status Register (Section 10.8.3.13) for all others

Table 5-53. Enables for the Host Notify Command

HOST_NOTIFY_INTRE

N (Slave Control I/O

bit 0)

SMB_SMI_EN

(Host Config

D31:F3:Off40h, Bit

HOST_NOTIFY_WKEN

(Slave Control I/O

bit 1)

Result

0X0None

XX1Wake generated

1 0 X Interrupt generated

11X

Slave SMI#

generated

(SMBUS_SMI_STS)

Intel ® ICH7 Family Datasheet 227

Functional Description

Note: The external microcontroller should not attempt to access the ICH7’ s SMBus slave logic

until either:

• 800 milliseconds after both: RTEST# is high and RSMRST# is high, OR

• the PLTRST# de-asserts

The 800 ms case is based on the scenario where the RTC Battery is dead or missing

such that the RT C Power W ell comes up simultaneously with Suspend W ell. In this case,

the RT C clock ma y tak e a while to stabilize. The ICH7 uses the RTC clock to extend the

internal RSMRST# by ~100 ms. Therefore, if the clock is slow to toggle, this time could

be extended. 800 ms is assumed to be sufficient guardband for this.

If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more

in the middle of a cycle, the ICH7 slave logic' s behavior is undefined. This is interpreted

as an unexpected idle and should be avoided when performing management activities

to the slave logic.

Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus

a translation in the address is needed to accommodate the least significant bit used for

read/write control. For example, if the ICH7 slave address (RCV_SLVA) is left at 44h

(default), the external micro controller would use an address of 88h/89h (write/read).

5.21.7.1 Format of Slave Write Cycle

The external master performs Byte Write commands to the ICH7 SMBus Slave I/F. The

“Command” field (bits 11:18) indicate which register is being accessed. The Data field

(bits 20:27) indicate the value that should be written to that register.

Note: If the ICH7 is sent a ‘Hard Reset Without Cyclin g’ command on SMBus while the system

is in S4 or S5, the reset command will not be executed until the next wake event.

SMBus write commands sent after the Hard Reset Without Cycling command and

before the wake event will be NAK ed by the ICH7. This also applies to any SMBus w ake

commands sent after a Hard Reset Without Cycling command, such that the SMBus

wake command will not cause the system to wake. Any SMBus read that is accepted by

the ICH7 will complete normally. Intel® Active Management Technology is not

impacted as Intel AMT does not use the Hard Reset Without Cycling command while the

system is in S4 or S5.

Table 5-54 has the values associated with the registers.

NOTE: The external microcontroller is responsible to make sure that it does not update the

contents of the data byte registers until they have been read by the system processor. The

ICH7 overwrites the old value with any new value received. A race condition is possible

where the new value is being written to the register just at the time it is being read. ICH7

will not attempt to cover this race condition (i.e., unpredictable result s in this case).

Table 5-54. Slave Write Registers

0Command Register. See Table 5-55 below for legal values written to this register.

1–3 Reserved

4 Data Message Byte 0

5 Data Message Byte 1

6–7 Reserved

8 Reserved

9–FFh Reserved

Functional Description

228 Intel ® ICH7 Family Datasheet

Table 5-55. Command Types

Command

Type Description

0Reserved

WAKE/SMI#. This command wakes the system if it is not already awake. If

system is already awake, an SMI# is generated.

NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is

already awake. The SMI handler should then clear this bit.

2Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and

has the same effect as the Powerbutton Override occurring.

3HARD RESET WITHOUT CYCLING: This command causes a hard reset of the

system (does not include cycling of the power supply). This is equivalent to a write

to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0.

4HARD RESET SYSTEM. This command causes a hard reset of the system

(including cycling of the power supply). This is equivalent to a write to the CF9h

Disable the TCO Messages. This command will disable the Intel® ICH7 from

sending Heartbeat and Event messages (as described in Section 5.15.2). On ce this

command has been executed, Heartbeat and Event message reporting can only be

re-enabled by assertion and deassertion of the RSMRST# signal.

6WD RELOAD: Reload watchdog timer.

7Reserved

SMLINK_SLV_SMI. When ICH7 detects this command type while in the S0 state,

it sets the SMLINK_SLV_SMI_STS bit (see Section 10.9.5). This command should

only be used if the system is in an S0 state. If the message is received during S1–

S5 states, the ICH7 acknowledges it, but the SMLINK_SLV_SMI_STS bit does not

get set.

Note: It is possible that the system transitions out of the S0 state at the same time

that the SMLINK_SLV_SMI command is received. In this case, the

SMLINK_SL V_SMI_STS bit may get set but not serviced before the system goes to

sleep. Once the system returns to S0, the SMI associated with this bit would then

be generated. Software must be able to handle this scenario.

9–FFh Reserved

Intel ® ICH7 Family Datasheet 229

Functional Description

5.21.7.2 Format of Read Command

The external master performs Byte Read commands to the ICH7 SMBus Slave I/F. The

“Command” field (bits 18:11) indicate which register is being accessed. The Data field

(bits 30:37) contain the value that should be read from that register. Table Table 5-56

shows the Read Cy cle Format. Table 5-57 shows the register mapping for the data

byte.

Table 5-56. Read Cycle Format

Bit Description Driven by Comment

1 Start External Microcontroller

8:2 Slave Address - 7

bits External Microcontroller Must match value in R eceiv e Slave

Address register

9 Write External Microcontroller Always 0

10 ACK Intel® ICH7

18:11 Command code - 8

bits External Microcontroller Indicates which register is being

accessed See Table 5-57

19 ACK ICH7

20 Repeated Start External Microcontroller

27:21 Slave Address - 7

bits External Microcontroller Must match value in R eceiv e Slave

Address register

28 Read External Microcontroller Always 1

29 ACK ICH7

37:30 Datay Byte ICH7 Value depends on register being

accessed. See Table 5-57

38 NOT ACK External Microcontroller

39 Stop External Microcontroller

Table 5-57. Data Values for Slave Read Registers

07:0Reserved

12:0

System Power State

000 = S0

001 = S1

010 = Reserved

011 = S3

100 = S4

101 = S5

110 = Reserved

111 = Reserved

17:3Reserved

2 3:0 Frequency Strap Register

27:4Reserved

3 5:0 Watchdog Timer current value

37:6Reserved

Functional Description

230 Intel ® ICH7 Family Datasheet

5.21.7.2.1 Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a Start bit –

Address– Write bit sequence. When the ICH7 detects that the address matches the

value in the Receive Slave Address register, it will assume that the protocol is always

followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In

1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that

the system cover has probably been opened.

1 = BTI Temperature Event occurred. This bit will be set if the

Intel® ICH7’s THRM# input signal is active. Need to take after

polarity control.

Boot-status. This bit will be 1 when the processor does not fetch

the first instruction.

This bit will be set after the TCO timer times out a second time

(Both TIMEOUT and SECOND_TO_STS bits set).

46:4Reserved

The bit will reflect the state of the GPI11/SMBALERT# signal, and

will depend on the GP_INV11 bit. It does not matter if the pin is

configured as GPI11 or SMBALERT#.

• If the GP_INV11 bit is 1, the value of register 4 bit 7 will equal the level

of the GPI11/SMBALERT# pin (high = 1, low = 0).

• If the GP_INV11 bit is 0, the value of register 4 bit 7 will equal the

inverse of the level of the GPI11/SMBALERT# pin (high = 1, low = 0).

Unprogrammed flash BIOS bit. This bit will be 1 to i ndicate th at the

first BIOS fetch returned FFh, that indicates that the flash BIOS is

probably blank.

Reserved (Desktop Only)

Battery Low Status (Mobile/ Ultra Mobile Only). 1 if BATLOW# is ‘0’

Processor Power Failure Status. 1 if the CPUPWR_FLR bit in the

GEN_PMCON_2 register is set.

INIT# due to receiving Shutdown message. This event is visible

from the reception of the shutdown message until a platform reset

is done. Events on si gnal will not create an eve nt message.

LT Range: LT reset indication. Events on signal will not create an

event message.

POWER_OK_BAD: Indicates the failure core power well ramp during

boot/resume. This bit will be active if the SLP_S3# pin is de-

asserted and PWROK pin is not asserted.

Thermal Trip: This bit will shadow the state of CPU Thermal Trip

status bit (CT S). Ev ents on s ignal will not crea te an ev ent m essage.

57Reserved

6 7:0 Contents of the Message 1 register.

7 7:0 Contents of the Message 2 register.

8 7:0 Contents of the WDSTATUS register.

9-FFh 7:0 Reserved

Table 5-57. Data Values for Slave Read Registers

Intel ® ICH7 Family Datasheet 231

Functional Description

other words, if a Start –Address–Read occurs (which is invalid for SMBus R ead or Write

protocol), and the address matches the ICH7’s Slave Address, the ICH7 will still grab

the cycle.

Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–

Re ad sequence beginning at bit 20. Once again, if the Address matches the ICH7’s

Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and

proceed with the Slave Read cycle.

Note: An external microcontroller must not attempt to access the ICH7’s SMBus Slave logic

until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).

5.21.7.3 Format of Host Notify Command

The ICH7 tracks and responds to the standard Host Notify command as specified in the

System Management Bus (SMBus) Specification, Version 2.0. The host address for this

command is fixed to 0001000b. If the ICH7 already has data for a previously-received

host notify command which has not been serviced yet by the host software (as

indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address

byte of the protocol. This allows the host to communicate non-acceptance to the

master and retain the host notify address and data values for the previous cycle until

host software completely services the interrupt.

Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any

necessary reads of the address and data registers.

Table 5-58 shows the Host Notify format.

Table 5-58. Host Notify Format

Bit Description Driven By Comment

1Start External

Master

8:2 SMB Host Address — 7

bits External

Master Always 0001_000

9Write External

Master Always 0

10 ACK (or NACK) Intel® ICH7 ICH7 NACKs if HOST_NOTIFY_STS is 1

17:11 Device Address – 7 bits External

Master

Indicates the address of the master;

loaded into the Notify Device Address

18 Unused — Always 0 External

Master 7-bit-only address; this bit is inserted to

complete the byte

19 ACK ICH7

27:20 Data Byte Low — 8 bits External

Master Loaded into the Notify Data Low Byte

28 ACK ICH7

36:29 Data Byte High — 8 bits External

Master Loaded into the Notify Data High Byte

37 ACK ICH7

38 Stop External

Master

Functional Description

232 Intel ® ICH7 Family Datasheet

5.22 AC ’97 Controller (Audio D30:F2, Modem D30:F3)

(Desktop and Mobile Only)

Note: All references to AC ’97 in this document refer to the AC ’97 Specification, Version 2.3.

For further information on the operation of the AC-link protocol, see the AC ’97

Specification, Version 2.3.

The ICH7 AC ’97 contr o ll er fe atu r es in cl ud e:

• Independent PCI functions for audio and modem.

• Independent bus master logic for dual Microphone input, dual PCM Audio input (2-

channel stereo per input), PCM audio output (2-, 4- or 6-channel audio), Modem

input, Modem output and S/PDIF output.

• 20-bit sample resolution

• Multiple sample rates up to 48 kHz

• Support for 16 codec-implemented GPIOs

• Single modem line

• Configure up to three codecs with three ACZ_SDIN pins

Table 5-59 shows a detailed list of features supported by the ICH7 AC ’97 digital

controller

Table 5-59. Features Supported by Intel® ICH7 (Sheet 1 of 2)

Feature Description

System

Interface

• Isochronous low latency bus master memory interface

• Scatter/gather support for word-aligned buffers in memory

(all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types

are supported)

• Data buffer size in system memory from 3 to 65535 samples per input

• Data buffer size in system memory from 0 to 65535 samples per output

• Independent PCI audio and modem functions with configuration and I/O spaces

• AC ’97 codec registers are shadowed in system memory via driver

• AC ’97 codec register accesses are serialized via semaphore bit in PCI I/O space (new

accesses are not allowed while a prior access is still in progress)

Power

Management • Power management via PCI Power Management

PCI Audio

Function

• Read/write access to audio codec registers 00h–3Ah and vendor registers 5Ah–7Eh

• 20-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear

channels on slots 3,4,6,7,8,9,10,11)

• 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4)

• 16-bit mono mic in w/ or w/o mo no mi x, up to 48 kHz (L, R chann el, sl ots 3,4) (mono

mix supports mono hardware AEC reference for speakerphone)

• 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6)

(supports speech recognition or stereo hardware AEC ref for speakerphone)

• During cold reset ACZ_RST# is held low until after POST and software deasser tion of

ACZ_RST# (supports passive PC_BEEP to speaker connection during POST)

PCI Modem

function

• Read/write access to modem codec registers 3Ch–58h and vendor registers

5Ah–7Eh

• 16-bit mono modem line 1 output and input, up to 48 kHz (slot 5)

• Low latency GPIO[15:0] via hardwired update between slot 12 and PCI I/O register

• Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT

• SCI event generation on ACZ_SDIN[2:0] wake-up signal

Intel ® ICH7 Family Datasheet 233

Functional Description

Note: Throughout this document, references to D31:F5 indicate that the audio function exists

in PCI Device 31, Function 5. References to D31:F6 indicate that the modem function

exists in PCI Device 31, Function 6.

Note: Throughout this document references to tertiary, third, or triple codecs refer to the

third codec in the system connected to the ACZ_SDIN2 pin. The AC ’97 Specification,

Version 2.3 refers to non-primary codecs as multiple secondary codecs. To avoid

confusion and excess v e rbiage, th is datasheet refers to it as the third or tertiary codec.

AC-link

• AC ’97 2.3 AC-link interface

• Variable sample rate output support via A C ’97 SLOTREQ protocol (slots

3,4,5,6,7,8,9,10,11)

• Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6)

• 3.3 V digital operation meets AC ’97 2.3 DC switching levels

• AC-link I/O driver capability meets AC ’97 2.3 triple codec specifications

• Codec register status reads must be returned with data in the next AC-link frame, per

AC ’97 Specification, Version 2.3.

Multiple Codec

• Triple codec addressing: All AC ’97 Audio codec register accesses are addressable to

codec ID 00 (primary), codec ID 01 (secondary), or codec ID 10 (tertiary).

• Modem codec addressing: All AC ‘97 Mod em co de c register accesses ar e ad dr ess a ble

to codec ID 00 (primary) or codec ID 01 (secondary).

• Triple codec receive capability via ACZ_SDIN[2:0] pins

(ACZ_SDIN[2:0] frames are internally validated, synchronized, and OR’d depending

on the Steer Enable bit status in the SDM register)

• ACZ_SDIN mapping to DM A engine mapping capability allows for simultaneous input

from two different audio codecs.

NOTES:

1. Audio Codec IDs are remappable and not limited to 00,01,10.

2. Modem Codec IDs are remappable and limited to 00, 01.

3. When using multiple codecs, the Modem Codec must be ID 01.

Figure 5-12. Intel® ICH7-Based Audio Codec ’97 Specification, Version 2.3

Table 5-59. Features Supported by Intel® ICH7 (Sheet 2 of 2)

Feature Description

udio In (Record)

udio Out (6 Channel Playback)

Mic.2

S/P DIF * O utpu t

Mic.1

Modem

Functional Description

234 Intel ® ICH7 Family Datasheet

5.22.1 PCI Power Management

This Power Management section applies for all AC ’97 controller functions. After a

power management event is detected, the AC ’97 controller wakes the host system.

The following sections describe these events and the AC ’97 controller power states.

Device Power States

The AC ’97 controller supports D0 and D3 PCI Power Management states. The following

are notes regarding the AC ’97 controller implementation of the Device States:

1. The AC ’97 controller hardware does not inherently consume an y more power when

it is in the D0 state than it does in D3 state. However, software can halt the DMA

engine prior to entering these low power states such that the maximum power

consumption is reduced.

2. In the D0 state, all implemented AC ’97 controller features are enabled.

3. In D3 state, accesses to the AC ’97 controller memory -mapped or I/O range results

in master abort.

4. In D3 state, the AC ’97 controller interrupt will not assert for any reason. The

internal PME# signal is used to signal wake events, etc.

5. When the Device Power State field is written from D3HOT to D0, an internal reset is

generated. See Section 17.1 for general rules on the effects of this reset.

6. AC97 STS bit is set only when the audio or modem resume events were detected

and their respective PME enable bits were set.

7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This

causes a wake up event only if the modem controller was in D3

8. Resume events on ACZ_SDIN[2:0] cause resume interrupt status bits to be set

only if their respective controllers are not in D3.

9. Edge detect logic prevents the interrupts from being asserted in case the AC97

controller is switched from D3 to D0 after a wake event.

10.Once the interrupt status bits are set, they will cause PIRQB# if their respective

enable bits were set. One of the audio or the modem drivers will handle the

interrupt.

5.22.2 AC-Link Overview

The ICH7 is an AC ’97 2.3 controller that communicates with companion codecs via a

digital serial link called the AC-link. All digital audio/modem streams and command/

status information is communicated over the AC-link.

The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and

output data streams, as well as control register accesses, employing a time division

multiplexed (TDM) scheme. The AC-link architecture provides for data transfer through

individual frames tr ansmitted in a serial fashion. Each frame is divided into 12 outgoing

and 12 incoming data streams, or slots. The architecture of the ICH7 AC-link allows a

maximum of three codecs to be connected. Figure 5-13 shows a three codec topology

of the AC-link for the ICH7. The AC-link consists of a five signal interface between the

ICH7 and codec(s).

Note: The ICH7’s AC ‘97 controller shares the signal interface with the Intel High Definition

Audio controller. However, only one controller may be enabled at a time.

Intel ® ICH7 Family Datasheet 235

Functional Description

ICH7 core well outputs may be used as strapping options for the ICH7, sampled during

system reset. These signals may have weak pullups/pulldowns; however, this will not

interfere with link operation. ICH7 inputs integrate weak pulldowns to prevent floating

traces when a secondary and/or tertiary codec is not attached. When the Shut Off bit in

the control register is set, all buffers will be turned off and the pins will be held in a

steady state, based on these pullups/pulldowns.

ACZ_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides

the necessary clocking to support the twelve 20-bit time slots. AC-link serial data is

transitioned on each rising edge of ACZ_BIT_CLK. The receiver of AC -link data samples

each serial bit on the falling edge of ACZ_BIT_CLK.

If ACZ_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH7

assumes the primary codec is not present or not working. It sets bit 28 of the Global

Status Register

(I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh

to prevent system hangs.

Figure 5-13. AC ’97 2.3 Controller-Codec Connection

Intel®

ICH7

Primary Codec

AC / MC / AMC

AC97 ICH codec conn

ACZ_SDIN2

ACZ_SDIN1

ACZ_RST#

ACZ_SDOUT

ACZ_SYNC

ACZ_BIT_CLK

Secondary Codec

AC / MC / AMC

Tertiary Codec

AC / MC / AMC

ACZ_SDIN0

Functional Description

236 Intel ® ICH7 Family Datasheet

Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via

the ACZ_SYNC signal, as shown in Figure 5-14. The primary codec drives the serial bit

clock onto the AC-link, which the AC ’97 controller then qualifies with the ACZ_SYNC

signal to construct data frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing

down ACZ_BIT_CLK. ACZ_SYNC remains high for a total duration of 16 ACZ_BIT_CLK

at the beginning of each frame. The portion of the frame where ACZ_SYNC is high is

defined as the tag phase. The remainder of the frame where ACZ_SYNC is low is

defined as the data phase. Each data bit is sampled on the falling edge of

ACZ_BIT_CLK.

The ICH7 has three ACZ_SDIN pins allowing a single, dual, or triple codec

configuration. When multiple codecs are connected, the primary, secondary, and

tertiary codecs can be connected to any ACZ_SDIN line. The ICH7 does not distinguish

between codecs on its ACZ_SDIN[2:0] pins, however the registers do distinguish

between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2] for wake events, etc. If using

a Modem Codec it is recommended to connect it to ACZ_SDIN1.

The ICH7 does not support optional test modes as outlined in the AC ’97 Specification,

Version 2.3.

5.22.2.1 Register Access

In the ICH7 implementation of the AC-link, up to three codecs can be connected to the

SDOUT pin. The following mechanism is used to address the primary, secondary, and

tertiary codecs individually.

The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits

[18:12] of slot 1 are used for the register index. For I/O writes to the primary codec,

the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in Table 5-60.

Slot 1 is used to transmit the register address, and slot 2 is used to transmit data. For

I/O reads to the primary codec, only slot 1 should be valid since only an address is

transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1

and 2 valid bits are set.

The secondary and tertiary codec registers are accessed using slots 1 and 2 as

described above, however the slot v alid bits for slots 1 and 2 are mark ed invalid in slot

0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. This

allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and

bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary

codec. If the register access is targeted to the secondary or tertiary codec, slot 1 an d 2

will contain the address and data for the register access. Since slots 1 and 2 are

marked invalid, the primary codec will ignore these accesses.

Figure 5-14. AC-Link Protocol

SYNC

BIT_CLK

SDIN slot

(

)

Time Slot "Valid"

Bits

20.8uS

(48 KHz)

Slot 1 Slot 2

019 019 0 19 0

Slot 3 Slot 12

81.4 nS

12.288 MHz

slot

(

)

"0""0""0"slot

(

)

("1" = time slot contains valid PCM

Codec

Ready

End of previous

Audio Frame

Tag Phase Data Phase

Intel ® ICH7 Family Datasheet 237

Functional Description

When accessing the codec registers, only one I/O cycle can be pending across the AC-

link at any time. The ICH7 implements write posting on I/O writes across the AC-link

(i.e., writes across the link are indicated as complete before they are actually sent

across the link). In order to prevent a second I/O write from occurring before the first

one is complete, software must monitor the CAS bit in the Codec Access Semaphore

then another codec access (read or write) can go through. The exception to this being

reads to offset 54h/D4h/154h (slot 12) which are returned immediately with the most

recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary, secondary

and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a normal

The controller does not issue back to back reads. It must get a response to the first

read before issuing a second. In addition, codec reads and writes are only executed

once across the link, and are not repeated.

5.22.3 AC-Link Low Power Mode

The AC-link signals can be placed in a low-power mode. When the AC ’97 Powerdown

ACZ_SDIN will be brought to, and held at a logic low voltage level.

Table 5-60. Output Tag Slot 0

Bit Primary

Access

Example

Secondary

Access

Example Description

15 1 1 Frame Valid

14 1 0 Slot 1 Valid, Command Address bit (Primary codec

only)

13 1 0 Slot 2 Va lid, Command Data bit (P rim ary c ode c onl y )

12:

3X X Slot 3–12 Valid

2 0 0 Reserved

1:0 00 01 Codec ID (00 reserved for primary; 01 indicate

secondary; 10 indicate tertiary)

Figure 5-15. AC-Link Powerdown Timing

SDOUT TAG

SYNC

BIT_CLK

Write to

0x20 Data

PR4

slot 12

prev. frame

TAG

slot 12

prev. frame

SDIN

Note:

BIT_CLK not to scale

Functional Description

238 Intel ® ICH7 Family Datasheet

ACZ_BIT_CLK and ACZ_SDIN transition low immediately after a write to the

Powerdown R egister (26h) with PR4 enabled. When the AC ’97 controller driver is at the

point where it is ready to program the AC-link into its low-power mode, slots 1 and 2

are assumed to be the only valid stream in the audio output frame.

The AC ’97 controller also drives ACZ_SYNC, and ACZ_SD OUT low after programming

AC ’97 to this low power, halted mode

Once the codec has been instructed to halt, ACZ_BIT_CLK, a special wake up protocol

must be used to bring the AC-link to the active mode since normal output and input

frames can not be communicated in the absence of ACZ _BIT_CLK. Once in a low -power

mode, the ICH7 provides three methods for waking up the AC-link; external wake

event, cold reset and warm reset.

Note: Before entering any low-power mode where the link interface to the codec is expected

to be powered down while the rest of the system is awake, the software must set the

“Shut Off” bit in the control register.

5.22.3.1 External Wake Event

Codecs can signal the controller to wake the AC-link, and wake the system using

ACZ_SDIN.

The minimum ACZ_SDIN wake up pulse width is 1 us. The rising edge of ACZ_SDIN0,

ACZ_SDIN1 or ACZ_SDIN2 causes the ICH7 to sequence through an AC-link warm

reset and set the AC97_STS bit in the GPE0_STS register to wake the system. The

primary codec must wait to sample ACZ_SYNC high and low before restarting

ACZ_BIT_CLK as diagrammed in Figure 5-16. The codec that signaled the wake event

must keep its ACZ_SDIN high until it has sampled ACZ_SYNC having gone high, and

then low.

The AC-link protocol pro vides for a cold reset and a warm reset. The type of reset used

depends on the system’s current power down state. Unless a cold or register reset (a

write to the Reset register in the codec) is performed, wherein the AC ’97 codec

registers are initialized to their default values, registers are required to keep state

during all power down modes.

Once powered down, activation of the AC-link via re-assertion of the ACZ_SYNC signal

must not occur for a minimum of four audio frame times following the frame in which

the power down was triggered. When AC-link powers up, it indicates readiness via the

codec ready bit.

Figure 5-16. SDIN Wake Signaling

SDOUT TAG

SYNC

BIT_CLK

Write to

0x20 Data

PR4

slot 12

prev. frame

TAG

slot 12

prev. frame

SDIN

TAG Slot 1 Slot 2

Power Down

Frame Wake EventSleep State New Audio

Frame

TAG Slot 1 Slot 2

Intel ® ICH7 Family Datasheet 239

Functional Description

5.22.4 AC ’97 Cold Reset

A cold reset is achieved by asserting ACZ_RST# for 1 µs. By driving ACZ_RST# low,

ACZ_BIT_CLK, and ACZ_SDOUT will be activated and all codec registers will be

initialized to their default power on reset values. ACZ_RST# is an asynchronous AC ’97

input to the codec.

5.22.5 AC ’97 Warm Reset

A warm reset re-activates the AC-link without altering the current codec register

values. A warm reset is signaled by driving ACZ_SYNC high for a minimum of 1 µs in

the absence of ACZ_BIT_CLK.

Within normal frames, ACZ_SYNC is a synchronous AC ’97 input to the codec. However,

in the absence of ACZ_BIT_CLK, ACZ_SYNC is treated as an asynchronous input to the

codec used in the generation of a warm reset.

The codec must not respond with the activation of ACZ_BIT_CLK until ACZ_SYNC has

been sampled low again by the codec. This prevents the false detection of a new frame.

Note: On receipt of wake up sign aling from the codec, the digital controller issues an interrupt

if enabled. Software then has to issue a warm or cold reset to the codec by setting the

appropriate bit in the Global Control Register.

5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec

Software first performs a read to one of the audio codecs. The read request goes out on

ACZ_SDOUT. Since the ICH7 allows one read to be performed at a time on the link,

eventually the read data will come back in on one of the ACZ_SDIN[2:0] lines.

The codec does this by indicating that status data is valid in its TAG, then echoes the

read address in slot 1 followed by the read data in slot 2.

The new function of the ICH7 hardware is to notice which ACZ_SDIN line contains the

read return data, and to set new bits in the new register indicating which ACZ_SDIN

line the register read data returned on. If it returned on ACZ_SDIN[0], bits [1:0]

contain the value 00. If it returned on ACZ_SDIN[1], the bits contain the value 01, etc.

ICH7 hardware can set these bits every time register read data is returned from a

function 5 read. No special command is necessary to cause the bits to be set. The new

driver/BIOS software reads the bits from this register when it cares to, and can ignore

it otherwise. When software is attempting to establish the codec-to-ACZ_SDIN

mapping, it will single feed the read request and not pipeline to ensure it gets the right

mapping, we cannot ensure the serialization of the access.

Functional Description

240 Intel ® ICH7 Family Datasheet

5.23 Intel® High Definition Audio Overview

The ICH7’s Intel High Definition Audio controller shares pins with the AC ’97 controller.

However, only one controller may be enabled at a time.

Note: The ICH7-U Ultra Mobile component does not contain an AC ‘97 controller.

The ICH7’s controller communicates with the external codec(s) over the Intel High

Definition Audio serial link. The controller consists of a set of DMA engines that are

used to move samples of digitally encoded data between system memory and an

external codec(s). The ICH7 implements four output DMA engines and 4 input DMA

engines. The output DMA engines move digital data from system memory to a D-A

converter in a codec. ICH7 implements a single Serial Data Output signal

(ACZ_SDOUT) that is connected to all external codecs. The input DMA engines move

digital data from the A-D converter in the codec to system memory. The ICH7

implements three Serial Digital Input signals (ACZ_SDI[2:0]) supporting up to three

codecs.

Audio software renders outbound and processes inbound data to/from buffers in

system memory. The location of individual buffers is described by a Buffer Descriptor

List (BDL) that is fetched and processed by the controller. The data in the buffers is

arranged in a predefined format. The output DMA engines fetch the digital data from

memory and reformat it based on the programmed sample rate, bit/sample and

number of channels. The data from the output DMA engines is then combined and

serially sent to the external codecs over the Intel High Definition Audio link. The input

DMA engines receive data from the codecs ov er the Intel High Definition Audio link and

format the data based on the programmable attributes for that stream. The data is

then written to memory in the predefined format for software to process. Each DMA

engine moves one stream of data. A single codec can accept or generate multiple

streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can

accept the same output stream processed by a single DMA engine.

Codec commands and responses are also transported to and from the codecs via DMA

engines.

5.23.1 Intel® High Definition Audio Docking (Mobile Only)

5.23.1.1 Dock Sequence

Note that this sequence is followed when the system is running and a docking event

occurs.

1. Since the ICH7 supports docking, the Docking Supported (DCKSTS. DS) bit defaults

to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD

Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST

to effectively turn off the docking feature.

2. After reset in the undocked quiescent state, the Dock A ttach (DCKCTL.DA) bit and

the Dock Mate (DCKSTS.DM) bit are both de-asserted. The AZ_DOCK_EN# signal is

de-asserted and AZ_DOCK_RST# is asserted. BCLK , SYNC and SDO signals ma y or

may not be running at the point in time that the docking event occurs.

3. The physical docking event is signaled to ACPI BIOS software via ACPI control

methods. This is normally accomplished through a GPIO signal on the ICH7 and is

outside the scope of this section.

4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1

and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1

to the DCKCTL.DA bit.

Intel ® ICH7 Family Datasheet 241

Functional Description

5. The HD Audio controller then asserts the AZ_DOCK_EN# signal so that the BCLK

signal begins toggling to the dock codec. AZ_DOCK_EN# shall be asserted

synchronously to BCLK and timed such that BCLK is low, SYNC is low, and SDO is

low. Pull-down resistors on these signals in the docking station discharge the

signals low so that the state of the signal on both sides of the switch is the same

when the switch is turned on. This reduces the potential for charge coupling

glitches on these signals. Note that in the ICH7 the first 8 bits of the Command field

are “reserved” and always driven to 0s. This creates a predictable point in time to

assert AZ_DOCK_EN#. Note that the HD Audio link reset exit specification that

requires that SYNC and SDO be driven low during BCLK startup is not ensured.

Note also that the SDO and BCLK signals may not be low while AZ_DOCK_RST# is

asserted which also does not comply with the specification.

6. After the controller asserts AZ_DOCK_EN# it waits for a minimum of 2400 BCLKs

(100 us) and then de-asserts AZ_DOCK_RST#. This is accomplished in such a way

to meet the HD Audio link reset exit specification. AZ_DOCK_RST# de-assertion

should be synchronous to BCLK and timed such that there are least 4 full BCLKS

from the de-assertion of AZ_DOCK_RST# to the first frame SYNC assertion.

7. The Connect/Turnaround/Address Frame hardware initialization sequence will now

occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high

on the last BCLK cycle of the Frame Sync of a Connect Frame. The appropriate

bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround

and Address Frame initialization sequence then occurs on the dock codec's SDI(s).

8. After this hardware initialization sequence is complete (approximately 32 frames),

the controller hardware sets the DCKST S.DM bit to 1 indicating that the dock is now

mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,

conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD

Audio Bus Driver, which then begins its codec discovery, enumeration, and

configuration process.

9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an

interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs

attached to them. When a corresponding STATESTS bit gets set, an interrupt is

generated. In this case the HD Audio Bus Driver is called directly by this interrupt

instead of being notified by the plug-N-play IRP.

10.HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits

now set in the STATESTS register with the bits that were set prior to the docking

event.

5.23.1.2 Exiting D3/CRST# when Docked

1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted

resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the

dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# de-

asserted) and DOCK_RST# is asserted.

2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits

approximately 7ms, then checks the STATESTS bits to see which codecs are

present.

3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is

still set and the controller hardware sequences through steps to electrically connect

the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#.

This completes within the 7 ms mentioned in step 2).

4. The Bus Driver enumerates the codecs present as indicated via the STATESTS bits.

5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.

Functional Description

242 Intel ® ICH7 Family Datasheet

5.23.1.3 Cold Boot/Resume from S3 When Docked

1. When booting and resuming from S3, PLTRST# switches from asserted to de-

asserted. This clears the DCKCTL.DA bit and the dock state machines. Because the

dock state machines are reset, the dock is electrically isolated (AZ_DOCK_EN# de-

asserted) and DOCK_RST# is asserted.

2. POST BIOS detects that the dock is attach ed and sets the DCKCTL.DA bit to 1. Note

that at this point CRST# is still asserted so the dock state machine will remain in its

reset state.

3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits

approximately 7 ms, then checks the STATESTS bits to see which codecs are

present.

4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is

still set and the controller hardware sequences through steps to electrically connect

the dock by asserting AZ_DOCK_EN# and then eventually de-asserts DOCK_RST#.

This completes within the 7 ms mentioned in step 3).

5. The Bus Driver enumerates the codecs present as i nd icate d via the STATESTS bits .

5.23.1.4 Undock Sequence

There are two possible undocking scenarios. The first is the one that is initiated by the

user that invokes software and gracefully shuts down the dock codecs before they are

undocked. The second is referred to as the “surprise undock” where the user undocks

while the dock codec is running. Both of these situations appear the same to the

controller as it is not cognizant of the “surprise removal”. But both sequences will be

discussed here.

5.23.1.4.1 Normal Undock

1. In the docked qu iescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate

(DCKSTS.DM) bit are both asserted. The AZ_DOCK_EN# signal is asserted and

AZ_DOCK_RST# is de-asserted.

2. The user initiates an undock event through the GUI interface or by pushing a

button. This mechanism is outside the scope of this section of the document. Either

way ACPI BIOS software will be invoked to manage the undock process.

3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to

the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not

capable of halting the stream to the docked codec, ACPI BIOS will initiate the

hardware undocking sequence as described in the n ext step while the dock stream

is still running. From this standpoint, the result is similar to the “surprise undock”

scenario where an audio glitch may occur to the docked codec(s) during the undock

process.

4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the

DCKCTL.DA bit.

5. The HD Audio controller asserts AZ_DOCK_RST#. AZ_DOCK_RST# assertion shall

be synchronous to BCLK. There are no other timing requirements for

AZ_DOCK_RST# assertion. Note that the HD Audio link reset specification

requirement that the last Frame sync be skipped will not be met.

6. A minimum of 4 BCLKs after AZ_DOCK_RST# the controller will de-assert

AZ_DOCK_EN# to isolate the dock codec signals from the ICH7 HD Audio link

signals. AZ_DOCK_EN# is de-asserted synchronously to BCLK and timed such that

BCLK, SYNC, and SDO are low.

7. After this hardware undocking sequence is complete (a maximum of TBD from

DCKCTL.DA being written from “1” to “0”), the controller hardware clears the

DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS software

polls DCKSTS.DM and when it sees DM set, conveys to the end user that physical

undocking can proceed. The controller is now ready for a subsequent docking

event.

Intel ® ICH7 Family Datasheet 243

Functional Description

5.23.1.4.2 Surprise Undock

1. In the surprise undock case the user undocks before software has had the

opportunity to gracefully halt the stream to the dock codec and initiate the

hardware undock sequence.

2. A signal on the docking connector is connected to the switch that isolates the dock

codec signals from the ICH7 HD Audio link signals (DOCK_DET# in the conceptual

diagram). When the undock event begins to occur the switch will be put into isolate

mode.

3. The undock event is communicated to the ACPI BIOS via ACPI control methods that

are outside the scope of this section of the document.

4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD

Audio Bus Driver via plug-N-play IRP. The Bus Driver then posthumously cleans up

the dock codec stream.

5. The HD Audio controller hardware is oblivious to the fact that a surprise undock

occurred. The flow from this point on is identical to the normal undocking sequence

described in section 0 starting at step 3). It finishes with the hardware clearing the

DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is

now ready for a subsequent docking event.

5.23.1.5 Interaction Between Dock/Undock and Power Management States

When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for

initiating the docking sequence if the dock is already attached when PLTRST# is de-

asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de-

asserting CRTS# and detecting and enumerating the codecs attached to the

AZ_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware

signal indicating that a dock is attached. Therefore, a method outside the scope of this

document must be used to cause the POST BIOS to initiate the docking sequence.

When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the

DCKCTL.DA bit is not cleared. Th e dock state machine will be reset such that

AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST# will be asserted and the

DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,

the dock state machine will detect that DCKCTL.DA is set to “1” and will begin

sequencing through the dock process. Note that this does not require any software

intervention.

5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST#

AZ_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As long

as AZ_RST# is asserted, the DOCK_RST# signal will also be asserted.

When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to

their default state (0's), and the dock state machine will be reset such that

AZ_DOCK_EN# will be de-asserted, and AZ_DOCK_RST# will be asserted. After any

PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and

then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting

CRST#.

When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state

machine will be reset such that AZ_DOCK_EN# will be de-asserted, AZ_DOCK_RST#

will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the

CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to

“1” and will begin sequencing through the dock process. Note that this does not require

any software interv ention .

Functional Description

244 Intel ® ICH7 Family Datasheet

5.24 Intel® Active Management Technology (Intel®

AMT) (Desktop and Mobile Only)

Intel Active Management Technology is a set of advanced manageability features

developed as a direct result of IT customer feedback gained through Intel market

research. Reducing the Total Cost of Ownership (TCO) through improved asset tracking,

remote manageability, and fewer desk -side visits were identified as key IT priorities. PT

extends the capabilities of existing management solutions by making the asset

information, remote diagnostics, and recovery capabilities always av ailable, or Out of

Band (OOB), even when the system is in a low-power “off” state or the OS is hung.

5.24.1 Intel® AMT Features

• E-Asset Tag

• OOB HW and SW Inventory Logs

• OOB Alerts

•IDE Redirect

• Serial over LAN for Remote Control

• Remote Diagnostics Execution

•OS Lock-Up Alert

•OS Repair

• Remote BIOS Recovery and Update

5.24.2 Intel® AMT Requirements

Intel AMT is a platform-level solution that uses multiple system components including:

• Intel AMT-Ready ICH7 component for the SMBus, PCI Express, SPI flash bus, and

system sensors

•Intel

® PRO 82573E Gigabit Ethernet Controller with Intel® Active Management

Technology for remote access

• An embedded microcontroller to run OOB firmware/software

• SPI fl ash memory (4 Mb for Intel AMT) to store asset information, management

software code, and logs

• BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can

optionally share same flash memory device)

• Familiar ISV software packages to take advantage of Intel AMT’s platform

management capabilities

Intel ® ICH7 Family Datasheet 245

Functional Description

5.25 Serial Peripheral Interface (SPI) (Desktop and

Mobile Only)

The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially

lower-cost alternative for system flash versus the Firmware Hub on the LPC bus.

The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In

(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select

(CS#).

Communication on the SPI bus is done with a Master – Slave protocol. The typical bus

topology consists of a single SPI Master (ICH7) with a single SPI Slave (flash device).

The Slave is connected to the ICH7 and is implemented as a tri-state bus.

Arbitration has been added that enables an optional shared flash configuration where

the ICH7 shares access to the SPI flash device with the PCI Express based Intel PRO

82573E Gigabit Ethernet Controller. This configuration allows a single larger density

flash device to replace two smaller density flash devices on the motherboard to

potentially reduce bill of material (BOM) costs.

Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected

by the ICH7, LPC based BIOS flash is disabled.

5.25.1 SPI Arbitration between Intel® ICH7 and Inte l PRO

82573E

The Shared Flash implementation consists of two SPI masters (ICH7 and Intel PRO

82573E) that arbitrate for access to a single shared SPI Device. This allows for

consolidation of Non-Volatile memory required by the Intel PRO 82573E GbE device

with the system BIOS offering the potential for BOM and board real estate savings.

The arbitration between Intel PRO 82573E and ICH7 occurs with the addition of an ARB

signal. The SPI flash device is connected to both the Intel PRO 82573E and ICH7 chips

and implemented as a shared tri-state bus; the ARB signal is connected directly from

Intel PRO 82573E to ICH7 and not to the SPI device.

The Shared Flash configuration allows each master to complete write and erase

commands to the SPI Flash, before allowing the other master to take ownership of the

bus

5.25.2 Flash Device Configurations

The ICH7, Intel PRO 82573E GbE LAN with Intel® Active Management Technology, and

SPI flash may be used in multiple configurations. Table 5-61 focuses on these various

configurations involving the ICH7.

Note: The ICH7 SPI interface supports a single Chip Select pin for a single SPI device.

Table 5-61. SPI Implementation Options

Configuration

Intel PRO

82573E with

Intel AMT

Present

Intel PRO

82573E

Firmware with

Intel AMT

System

BIOS

Location

System BIOS

and Intel

AMT Shared

Flash

FWH

Present

Number of

SPI

Device(s)

1NoNoFWHNoYes0

2NoNoSPINoNo1

3YesSPIFWHNoYes1

4YesSPISPINoNo2

5YesSPISPIYesNo1

Functional Description

246 Intel ® ICH7 Family Datasheet

5.25.3 SPI Device Compatibility Requirements

A variety of SPI flash devices exist in the market. In order for a SPI device to be

compatible with the ICH7 it must meet the minimum requirements detailed in the

following sections.

5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements

(Non-Shared Flash Configuration)

A SPI flash device must meet the following minimum requirements to be compatible

with the ICH7 in a non-shared flash configuration:

• Erase size capability of at least one of the following: 64 KB, 32 KB, 4 KB, 2 KB , 512

bytes, or 256 bytes.

• Required command set and associated opcodes (Refer to Section 5.25.4.1).

• Device identification command (Refer to Section 5.25.4.2).

• Device must support multiple writes to a page without requiring a preceding erase

cycle (Refer to Section 5.25.4.3)

• Serial flash device must ignore the upper address bits such that an address of

FFFFFFh simply aliases to the top of the flash memory.

• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising

edge of the clock).

• If the device receives a command that is not supported, the device must complete

the cycle gracefully without any impact on the flash content.

• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits

inside the designated area (page, sector, block, chip, or etc.).

• Minimum density of 4 Mb (Platform dependent based on size of BIOS).

Note: The ICH7 only supports Mode 0 on SPI flash devices

5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware

Configuration Requirements (Shared Flash Configuration)

A SPI flash device must meet the following minimum requirements to be compatible

with the ICH7 and the Intel PRO 82573E GbE with Intel AMT device in a shared flash

configuration:

The following are requirements that are in common with the BIOS only configuration

listed in Section 5.25.3.1:

• Required command set and associated opcodes (Refer to Section 5.25.4.1)

• Device identification command (Refer to Section 5.25.4.2)

• Device must support multiple writes to a page without requiring a preceding erase

cycle (Refer to Section 5.25.4.3)

• Serial flash device must ignore the upper address bits such that an address of

FFFFFFh simply aliases to the top of the flash memory.

• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising

edge of the clock).

• If the device receives a command that is not supported, the device must complete

the cycle gracefully without any impact on the flash content.

• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits

inside the designated area (page, sector, block, chip, or etc.).

Intel ® ICH7 Family Datasheet 247

Functional Description

The following is a list of additional requirements specific to the ICH7 with Intel PRO

82573E configuration:

• Erase size capability of at least one of the following: 4 KBytes (preferred) or 256

bytes.

• Byte write must be supported.

•A serial flash device that requires the Write Enable command must automatically

clear the Write Enable Latch at the end of Data Program instructions

•Status Register bit 0 must be set to 1 when a write or erase is in progress and

cleared to 0 when a write or erase is not in progress.

•Minimum density of 4 Mb for non-BIOS data storage

•Minimum density of 8 Mb for shared flash configurations (4 Mb for n on-BIOS data +

4 Mb for BIOS - platform dependant based on size of BIOS)

Note: The ICH7 only supports Mode 0 on SPI flash devices.

5.25.4 Intel® ICH7 Compatible Command Set

5.25.4.1 Required Command Set for Inter Operability

Table 5-62 contains a list of commands and the associated opcodes that a SPI based

serial flash device must support in order to be interoperable with the serial flash

interface.

5.25.4.2 Recommended Standard Commands

The following table contains a list of standard commands that a SPI device should

support to be compatible with the ICH7. This list only contains standard commands and

is not meant to be an all inclusive list of commands that SPI devices can support.

Table 5-62. Required Commands and Opcodes

Commands OPCODE

Program Data 02h

Read Data 03h

Read Status 05h

Table 5-63. Intel® ICH7 Standard SPI Commands

Commands OPCODE Notes

Write Status 01h If command is supported by a device, 01h must be supported.

Write Disa ble 04h

Write Enable 06h If command is supported by a device, 06h must be supported.

Fast Read 0Bh Intel® ICH7 does not support this command.

JEDEC ID 9Fh Either JEDEC ID (9Fh) or an Identify Device with ABh is required,

not both.

Identify Device ABh Either JEDEC ID (9Fh) or an Identify Device with ABh is required,

not both

Functional Description

248 Intel ® ICH7 Family Datasheet

5.25.4.3 Multiple Page Write Usage Model

The system BIOS and Intel® Active Management Technology firmware usage models

require that the serial flash device support multiple writes (minimum of 512 writes) to

a page (256 bytes) without requiring a preceding erase command. BIOS commonly

uses capabilities such as counters that are typically implemented by using byte writes

to ‘increment’ the bits within a page that have been designated as the counter. The

Intel AMT firmware usage model requires the capability for multiple data updates within

any given page. These data updates occur via byte writes without executing a

preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple

page write usage models apply to sequential and non-sequential data writes.

Note: This usage model requirement is based on any given bit only being written once from a

‘1’ to a ‘0’ without requiring the preceding erase. An erase would be required to change

bits back to the ‘1’ state.

5.25.5 Flash Protection

There are three types of Flash Protection mechanisms:

1. BIOS Range Write Protection

2. SMI#-Based Global Write Protection

3. Shared Flash Address Range Protection

The three mechanisms are conceptually OR’d together such that if any of the

mechanisms indicate that the access should be blocked, then it is blocked. Table 5-64

provides a summary of the Three Mechanisms.

A blocked command will appear to software to finish, except that the Blocked Access

status bit is set in this case.

5.25.5.1 BIOS Range Write Protection

The ICH7 provides a method for blocking writes to specific ranges in the SPI flash when

the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type

information (which can be locked down by the initial Boot BIOS) and the address of the

requested command against the base and limit fields of a Write Protected BIOS range.

Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism

remains in place until the next system reset.

Table 5-64. Flash Protection Mechanism Summary

Mechanism Accesses

Blocked

Range

Specific

Reset-Override

or SMI#-

Override? Equivalent Function on FWH

BIOS Range

Write

Protection Writes Yes Reset Override FWH Sector Protection

Write Protect Writes No SMI# Overri de Same as Write Protect in

previous ICH components for

FWH

BIOS BAR Reads and

Writes Yes Reset Override Not Applicable- Specific to

Flash Sharing

Intel ® ICH7 Family Datasheet 249

Functional Description

5.25.5.2 SMI# Based Global Write Protection

The ICH7 provides a method for blocking writes to the SPI flash when the Write Protect

bit is cleared (i.e., protected ). This is achieved by checking the Opcode type

information (which can be locked down by the initial Boot BIOS) of the requested

command.

The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as

they do for the FWH BIOS.

5.25.5.3 Shared Flash Address Range Protection

The System Flash (BIOS) occupies the top part of the SPI Flash Memory Device when

sharing this space with the LAN and Manageability functions. To prevent the system

from inappropriately accessing or modifying information in the LAN and Manageability

areas, the ICH7 checks outgoing addresses with the BIOS Base Address register and

blocks any cycles with addresses below that value. This includes Direct Memory Reads

to the SPI flash.

Note: Once BIOS has locked down the BIOS BAR, this mechanism remains in place until the

next system reset.

5.26 Intel® Quick Resume Technology (Digital Home

Only)

ICH7 implements the following Intel® Quick Resume Technology (QRT) features:

• Visual Off

• Consumer Electronics (CE) like On/Off

5.26.1 Visual Off

Intel Quick Resume Technology provides a new functional state called Visual Off. In

Visual Off the PC appears to be Off but is actually active and able to run progr am tasks.

The Visual Off state is transparent to the user. It is entered by simply pressing the

power button when the system is On. This turns off the display, sound, front panel

lights and HID devices (e.g. keyboard and mous e) but the PC stays active. P erceptually

to the user, the system appears Off in this state. Pressing the power button again will

turn back On the perceptual components that were “muted” in Visual Off.

From the Visual Off state, the system's power management can place the PC in a low

power suspend state (S3) using existing mechanisms. Again, this is transparent to the

end user.

5.26.2 CE-like On/Off

Intel Quick Resume Technology redefines the PC's power button behavior to switch

between user perceived On and Off states like a consumer electronics (CE) device. For

example when a television is turned off there is no shutdown procedure. The viewer

simply turns it Off. Likewise when a modern television is turned On it returns to the

same channel, volume level, color balance, etc. as when it was tur ned Off. Intel Quick

Resume Technology gives the PC this similar functionality. A simple press of the power

button turns it On or Off. There is no user visible lengthy boot up or shutdown process

as the Visual Off state is used. Therefore, there is no need to exit running applications.

Functional Description

250 Intel ® ICH7 Family Datasheet

Just as televisions may have multiple power buttons (e.g., on the TV and on a remote

control) so may the PC (e.g., a power button on the system unit and another on the

keyboard). However, all power buttons behave the same — On/Off. The PC will not

turn On (wake up) when any key is pressed or the mouse moved just as pressing the

volume button or TV channel button does not cause the TV to turn On. Only a power

button press turns it On and Off.

5.26.3 Intel® Quick Resume Technology Signals (ICH7DH Only)

To provide the end user notification of the system power state, it is recommended that

the front panel LED be used to indicate Visual Off in the same way that the front panel

LED is used to indicate the S3 system state. For example, if in the S3 state the front

panel LED is solid amber, also set the front panel LED to be solid amber upon entrance

into Visual Off.

To provide for platform implementation flexibility, the ICH7DH implements two Intel

Quick Resume Technology (QRT) signals that are multiplexed with GPIOs: EL_STATE0/

GPIO27 and EL_STATE1/GPIO28. The EL_STATE[1:0] pins may be used to control

LED(s) to provide end-user notification of the current system state or may be used as

GPIO pins (independently or combined). See Chapter 14 for further details on

controlling these signals.

The ICH7DH has an additional Intel QRT pin: EL_RSVD/GPIO26. When Intel QRT is

enabled, this signal is used exclusively as EL_RSVD and should be left as no connect.

Note: EL_RSVD should be left as a no connect on motherboards that will implement Intel

QRT.

5.26.4 Power Button Sequence (ICH7DH Only)

When Intel Quick Resume Technology (QRT) is enabled and the user presses the

PWRBTN# to put the system into the Visual Off state, the following sequence is

assumed:

1. User presses the Power Button, which causes the PWRBTN# signal to go low.

2. Intel QR T logic sets the EL_PB_STS bit. If the PWRB TN_INT_EN bit is set, the ICH7

does NOT set the PWRB TN_STS bit at this point.

3. Intel QRT logic causes an SMI or SCI (depending on the SMI_OPTION_CNT bit.)

4. If the Intel QRT logic was set to cause an SMI, the SMI handler executes and then

sets the SCI_NOW_CNT bit.

5. The Intel QRT SCI handler executes.

6. The Intel QRT SCI handler needs to cause th e PWRB TN_STS bit to be set, it can do

so by setting the PWRBTN_EVENT bit.

Note: When PWRBTN_STS is set, the ICH7 causes an SCI and the normal OS handler for

PWRBTN_STS is called.

Intel ® ICH7 Family Datasheet 251

Functional Description

5.27 Feature Capability Mechanism

A new set of registers have been added into ICH7 LPC Interface (Device 31, Function 0,

offset E0h - EBh) that allows the system software or BIOS to easily determine the

features supported by ICH7. These registers can be accessed through LPC PCI

configuration space; thus allowing for convenient single point access mechanism for

chipset feature detection.

This set of registers consists of:

Capability ID (FDCAP)

Capability Length (FDLEN)

Capability Version and Vendor-Specific Capability ID (FDVER)

Feature Vector (FVECT)

Functional Description

252 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 253

6 Register and Memory Mapping

The ICH7 contains registers that are located in the processor’s I/O space and memory

space and sets of PCI configuration registers that are located in PCI configuration

space. This chapter describes the ICH7 I/O and memory maps at the register-set lev el.

bit descriptions are provided in the following chapters. The following notations and

definitions are used in the register/instruction description chapters.

RO Read Only . In some cases, If a register is read only , writes to this

separate registers are located at the same location where a read

accesses one of the registers and a write accesses the other

WO Write Only. In some cases, If a register is write only, reads to

this register location have no effect. However, in other cases,

two separate registers are located at the same location where a

read accesses one of the registers and a write accesses the

other register. See the I/O and memory map tables for details.

R/W Read/Write. A register with this attribute can be read and

written.

R/WC Read/Write Clear. A register bit with this attribute can be read

and written. However, a write of 1 clears (sets to 0) the

corresponding bit and a write of 0 has no effect.

R/WO Read/Write-Once. A register bit with this attribute can be

written only once after power up. After the first write, the bit

becomes read only.

R/WLO R ead/W rite, Lock-Once. A register bit with this attribute can be

written to the non-locked value multiple times, but to the locked

value only once. After the locked v alue has been written, the bit

becomes read only.

Default When ICH7 is reset, it sets its registers to predetermined default

states. The default state represents the minimum functionality

feature set required to successfully bring up the system. Hence,

it does not represent the optimal system configur ation. It is the

responsibility of the system initialization software to determine

configuration, operating parameters, and optional system

features that are applicable, and to program the ICH7 registers

accordingly.

Bold Register bits that are highlighted in bold text indicate that the

bit is implemented in the ICH7. Register bits that are not

implemented or are hardwired will remain in plain text.

All bit(s) or bit-fields must be correctly dealt with by software. On reads, software must

use appropriate masks to extract the defined bits and not rely on reserved bits being

any particular value. On writes, software must ensure that the values of reserved bit

locations are preserved. Any ICH7 configuration register or I/O or memory mapped

location not explicitly indicated in this document must be considered reserved.

254 Intel ® ICH7 Family Datasheet

6.1 PCI Devices and Functions

The ICH7 incorpor ates a variety of PCI functions as shown in Table 6-1. These functions

are divided into six logical devic es (B0:D30, B0:D31, B0:D29, B0:D28, B0:D27 and

B1:D8). D30 contains the DMI interface-to-PCI bridge and the AC ’97 Audio and Modem

controller. D31 contains the PCI-to-LPC bridge, IDE controller, SATA controller, and the

SMBus controller. D29 contains the four USB UHCI controllers and one USB EHCI

controller. D27 contains the Intel High Definition Audio controller. B1:D8 is the

integrated LAN controller.

Note: From a software perspective, the integrated LAN controller resides on the ICH7’s

external PCI bus. This is typically Bus 1, but may be assigned a different number

depending on system configuration.

If for some reason, the particular system platform does not want to support any one of

the Device Functions, with the exception of D30:F0, they can individually be disabled.

The integrated LAN controller will be disabled if no Platform LAN Connect component is

detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the

software. A disabled function will not respond to any register reads or writes, insuring

that these devices appear hidden to software.

NOTES:

1. The LPC controller contains registers that control LPC, Power Management, System

Management, GPIO, processor Interface, RTC, Interrupts, Timers, DMA.

Table 6-1. PCI Devices and Functions

Bus:Device:Function1Function Description

Bus 0:Device 30:Function 0 PCI-to-PCI Bridge

Bus 0:Device 30:Function 2 AC ’97 Audio Controller (Desktop and Mobile Only)

Bus 0:Device 30:Function 3 AC ’97 Modem Controller (Desktop and Mobile Only)

Bus 0:Device 31:Function 0 LPC Controller1

Bus 0:Device 31:Function 1 IDE Controller

Bus 0:Device 31:Function 2 SATA Controller (Desktop and Mobile Only)

Bus 0:Device 31:Function 3 SMBus Controller

Bus 0:Device 29:Function 0 USB UHCI Controller #1

Bus 0:Device 29:Function 1 USB UHCI Controller #2

Bus 0:Device 29:Function 2 USB UHCI Controller #3

Bus 0:Device 29:Function 3 USB UHCI Controller #4

Bus 0:Device 29:Function 7 USB 2.0 EHCI Controller

Bus 0:Device 28:Function 0 PCI Express* Port 1 (Desktop and Mobile Only)

Bus 0:Device 28:Function 1 PCI Express Port 2 (Desktop and Mobile Only)

Bus 0:Device 28:Function 2 PCI Express Port 3 (Desktop and Mobile Only)

Bus 0:Device 28:Function 3 PCI Express Port 4 (Desktop and Mobile Only)

Bus 0:Device 28:Function 4 PCI Express Port 5 (Intel® ICH7R, and ICH7DH, and ICH7-M

Only)

Bus 0:Device 28:Function 5 PCI Express Port 6 (Intel® ICH7R, and ICH7DH, and ICH7-M

Only)

Bus 0:Device 27:F unction 0 Intel® High Definition Audio Controller

Bus n:Device 8:Function 0 LAN Controller (Desktop and Mobile Only)

Intel ® ICH7 Family Datasheet 255

6.2 PCI Configuration Map

Each PCI function on the ICH7 has a set of PCI configuration registers. The register

address map tables for these register sets are included at the beginning of the chapter

for the particular function. Configuration Space registers are accessed through

configuration cycles on the PCI bus by the Host bridge using configuration mechanism

#1 detailed in the PCI Local Bus Specification, Revision 2.3.

Some of the PCI registers contain reserved bits. Software must deal correctly with

fields that are reserved. On reads, software must use appropriate masks to extr act the

defined bits and not rely on reserved bits being any particular value. On writes,

software must ensure that the values of reserved bit position s are pres e rved. That is,

the values of reserv ed bit positions mu st first be read, merged with the new values for

other bit positions and then written back. Note the software does not need to perform

read, merge, write operation for the configuration address register.

In addition to reserved bits with in a register, the configuration space contains reserved

locations. Software should not write to reserved PCI configuration locations in the

device-specific region (above address offset 3Fh).

6.3 I/O Map

The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be

moved, but in some cases can be disabled. Variable ranges can be moved and can also

be disabled.

6.3.1 Fixed I/O Address Ranges

Table 6-2 shows the Fixed I/O decode ranges from the processor perspective. Note that

for each I/O range, there may be separate behavior for reads and writes. DMI (Direct

Media Interface) cycles that go to target r anges that are marked as “R eserved” will not

be decoded by the ICH7, and will be passed to PCI unless the Subtractive Decode P olicy

bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target

ranges, it will be positively decoded by the ICH7 in medium speed.

Address ranges that are not listed or marked “Reserved” are not decoded by the ICH7

(unless assigned to one of the variable ranges).

256 Intel ® ICH7 Family Datasheet

Table 6-2. Fixed I/O Ranges Decoded by Intel® ICH7 (Sheet 1 of 2)

I/O

Address Read Target Write Target Internal Unit

00h–08h DMA Controller DMA Controller DMA

09h–0Eh RESERVED DMA Controller DMA

0Fh DMA Controller DMA Controller DMA

10h–18h DMA Controller DMA Controller DMA

19h–1Eh RESERVED DMA Controller DMA

1Fh DMA Controller DMA Controller DMA

20h–21h Interrupt Controller Interrupt Controller Interrupt

24h–25h Interrupt Controller Interrupt Controller Interrupt

28h–29h Interrupt Controller Interrupt Controller Interrupt

2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt

2E–2F LPC SIO LPC SIO Forwarded to LPC

30h–31h Interrupt Controller Interrupt Controller Interrupt

34h–35h Interrupt Controller Interrupt Controller Interrupt

38h–39h Interrupt Controller Interrupt Controller Interrupt

3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt

40h–42h Timer/Counter Timer/Counter PIT (8254)

43h RESERVED Timer/Counter PIT

4E–4F LPC SIO LPC SIO Forwarded to LPC

50h–52h Timer/Counter Timer/Counter PIT

53h RESERVED Timer/Counter PIT

60h Microcontroller Microcontroller Forwarded to LPC

61h NMI Controller NMI Controller Processor I/F

62h Microcontroller Microcontroller Forwarded to LPC

64h Microcontroller Microcontroller Forwarded to LPC

66h Microcontroller Microcontroller Forwarded to LPC

70h RESERVED NMI and RTC Controller RTC

71h RTC Controller RTC Controller RTC

72h RTC Controller NMI and RTC Controller RTC

73h RTC Controller RTC Controller RTC

74h RTC Controller NMI and RTC Controller RTC

75h RTC Controller RTC Controller RTC

76h RTC Controller NMI and RTC Controller RTC

77h RTC Controller RTC Controller RTC

80h DMA Controller, or LPC, or

PCI DMA Controller and LPC or

PCI DMA

81h–83h DMA Controller DMA Controller DMA

Intel ® ICH7 Family Datasheet 257

NOTES:

1. Only if IDE I/O space is enable d (D31:F1:40 bit 1 5) and the IDE contr oller is in legacy

mode. Otherwise, the target is PCI.

84h–86h DMA Controller DMA Controller and LPC or

PCI DMA

87h DMA Controller DMA Controller DMA

88h DMA Controller DMA Controller and LPC or

PCI DMA

89h–8Bh DMA Controller DMA Controller DMA

8Ch–8Eh DMA Controller DMA Controller and LPC or

PCI DMA

08Fh DMA Controller DMA Controller DMA

90h–91h DMA Controller DMA Controller DMA

92h Reset Generator Reset Generator Processor I/F

93h–9Fh DMA Controller DMA Controller DMA

A0h–A1h Interrupt Controller Interrupt Controller Interrupt

A4h–A5h Interrupt Controller Interrupt Controller Interrupt

A8h–A9h Interrupt Controller Interrupt Controller Interrupt

ACh–ADh Interrupt Controller Interrupt Controller Interrupt

B0h–B1h Interrupt Controller Interrupt Controller Interrupt

B2h–B3h Power Management Power Management Power

Management

B4h–B5h Interrupt Controller Interrupt Controller Interrupt

B8h–B9h Interrupt Controller Interrupt Controller Interrupt

BCh–BDh Interrupt Controller Interrupt Controller Interrupt

C0h–D1h DMA Controller DMA Controller DMA

D2h–DDh RESERVED DMA Controller DMA

DEh–DFh DMA Controller DMA Controller DMA

F0h FERR#/IGNNE# / Interrupt

Controller FERR#/IGNNE# / Interrupt

Controller Processor I/F

170h–177h IDE Controller, SATA

Controller, or PCI IDE Controller, SATA

Controller, or PCI F orw arded to IDE

or SATA

1F0h–1F7h IDE Controller, SATA

Controller, or PCI 1IDE Controller, SATA

Controller, or PCI F orw arded to IDE

or SATA

376h IDE Controller, SATA

Controller, or PCI IDE Controller, SATA

Controller, or PCI F orw arded to IDE

or SATA

3F6h IDE Controller, SATA

Controller, or PCI 1IDE Controller, SATA

Controller, or PCI F orwarded IDE or

SATA

4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt

CF9h Reset Generator Reset Generator Processor I/F

Table 6-2. Fixed I/O Ranges Decoded by Intel® ICH7 (Sheet 2 of 2)

I/O

Address Read Target Write Target Internal Unit

258 Intel ® ICH7 Family Datasheet

6.3.2 Variable I/O Decode Ranges

Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address

Registers (BARs) or other configuration bits in the various PCI configuration spaces.

The PNP software (PCI or ACPI) can use their configuration mechanisms to set and

adjust these values.

Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.

Unpredictable results if the configuration software allows conflicts to occur. The ICH7

does not perform any checks for conflicts.

Table 6-3. Variable I/O Decode Ranges

Range Name Mappable Size

(Bytes) Target

ACPI Anywhere in 64 KB I/O

Space 64 Power Management

IDE Bus Master Anywhere in 64 KB I/O

Space 16 IDE Unit

Native IDE Command Anywhere in 64 KB I/O

Space 8IDE Unit

Native IDE Control Anywhere in 64 KB I/O

Space 4IDE Unit

USB UHCI Controller #1 Anywhere in 64 KB I/O

Space 32 USB Unit 1

USB UHCI Controller #2 Anywhere in 64 KB I/O

Space 32 USB Unit 2

USB UHCI Controller #3 Anywhere in 64 KB I/O

Space 32 USB Unit 3

USB UHCI Controller #4 Anywhere in 64 KB I/O

Space 32 USB Unit 4

SMBus Anywhere in 64 KB I/O

Space 32 SMB Unit

AC ’97 Audio Mixer Anywhere in 64 KB I/O

Space 256 AC ’97 Unit

AC ’97 Audio Bus Master Anywhere in 64 KB I/O

Space 64 AC ’97 Unit

AC ’97 Modem Mixer Anywhere in 64 KB I/O

Space 256 AC ’97 Unit

AC ’97 Modem Bus Master Anywhere in 64 KB I/O

Space 128 AC ’97 Unit

TCO 96 Bytes above ACPI Base 32 TCO Unit

GPIO Anywhere in 64 KB I/O

Space 64 GPIO Unit

Parallel Port 3 Ranges in 64 KB I/O

Space 8 LPC Peripheral

Serial Port 1 8 Ranges in 64 KB I/O

Space 8 LPC Peripheral

Serial Port 2 8 Ranges in 64 KB I/O

Space 8 LPC Peripheral

Floppy Disk Controller 2 Ranges in 64 KB I/O

Space 8 LPC Peripheral

Intel ® ICH7 Family Datasheet 259

NOTE:

1. Decode range size determined by D31:F0:A Dh:bits 5:4

6.4 Memory Map

Table 6-4 shows (from the processor perspective) the memory ranges that the ICH7

decodes. Cycles that arrive from DMI that are not directed to any of the internal

memory targets that decode directly from DMI will be driven out on PCI unless the

Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The ICH7 may then

claim the cycle for the internal LAN controller.

PCI cycles generated by external PCI masters will be positively decoded unless they fall

in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for

PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s r ange, it will

be forwarded up to DMI. Software must not attempt locks to the ICH7’s memory-

mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which

means potential deadlock conditions may occur.

LAN Anywhere in 64 KB I/O

Space 64 LAN Unit

LPC Generic 1 Anywhere in 64 KB I/O

Space 4 to 256 LPC Peripheral

LPC Generic 21Anywhere in 64 KB I/O

Space 4 to 256 LPC Peripheral

LPC Generic 3 Anywhere in 64 KB I/O

Space 4 to 256 LPC Peripheral

LPC Generic 4 Anywhere in 64 KB I/O

Space 4 to 256 LPC Peripheral

I/O Trapping Ranges Anywhere in 64 KB I/O

Space 1 to 256 Trap on Backbone

Table 6-3. Variable I/O Decode Ranges

Range Name Map pable Size

(Bytes) Target

Table 6-4. Memory Decode Ranges from Processor Persp ective (S heet 1 of 2)

Memory Range Target Dependency/Comments

0000 0000h–000D FFFFh

0010 0000h–TOM

(Top of Memory) Main Memory TOM registers in Host controller

000E 0000h–000E FFFFh Firmware Hub Bit 6 in Firmware Hub Decode Enable register

is set

000F 0000h–000F FFFFh Firmware Hub Bit 7 in Firmware Hub Decode Enable register

is set

FEC0 0000h–FEC0 0100h I/O APIC inside

Intel® ICH7

FED4 0000h–FED4 0FFFh TPM on LPC

FFC0 0000h–FFC7 FFFFh

FF80 0000h–FF87 FFFFh Firmware Hub (or

PCI)1Bit 8 in Firmware Hub Decode Enable register

is set

FFC8 0000h–FFCF FFFFh

FF88 0000h–FF8F FFFFh Firmware Hub (or

PCI)1Bit 9 in Firmware Hub Decode Enable register

is set

260 Intel ® ICH7 Family Datasheet

NOTES:

1. PCI is the tar get when the Boot BIOS Destinatio n selection bit is low (Chipset Confi g

Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits

have no effect.

2. Only LAN cycles can be seen on PCI.

3. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High

Precision Event Timers. If attempted, the lock is not honored, which means potential

deadlock conditions may occur.

FFD0 0000h–FFD7 FFFFh

FF90 0000h–FF97 FFFFh Firmware Hub (or

PCI)1Bit 10 in Firmware Hub Decode Enable

FFD8 0000h–FFDF FFFFh

FF98 0000h–FF9F FFFFh Firmware Hub (or

PCI)1Bit 11 in Firmware Hub Decode Enable

FFE0 000h –FFE7 FFFFh

FFA0 0000h–FFA7 FFFFh Firmware Hub (or

PCI)1Bit 12 in Firmware Hub Decode Enable

FFE8 0000h–FFEF FFFFh

FFA8 0000h–FFAF FFFFh Firmware Hub (or

PCI)1Bit 13 in Firmware Hub Decode Enable

FFF0 0000h–FFF7 FFFFh

FFB0 0000h–FFB7 FFFFh Firmware Hub (or

PCI)1Bit 14 in Firmware Hub Decode Enable

FFF8 0000h–FFFF FFFFh

FFB8 0000h–FFBF FFFFh Firmware Hub (or

PCI)1

Always enabled.

The top two, 64 KB blocks of this range can

be swapped, as described in Section 7.4.1.

FF70 0000h–FF7F FFFFh

FF30 0000h–FF3F FFFFh Firmware Hub (or

PCI)1Bit 3 in Firmware Hub Decode Enable register

is set

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh Firmware Hub (or

PCI)1Bit 2 in Firmware Hub Decode Enable register

is set

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh Firmware Hub (or

PCI)1Bit 1 in Firmware Hub Decode Enable register

is set

FF40 0000h–FF4F FFFFh

FF00 0000h–FF0F FFFFh Firmware Hub (or

PCI)1Bit 0 in Firmware Hub Decode Enable register

is set

4 KB anywhere in 4-GB

range Integrated LAN

Controller2Enable via BAR in Device 29:Function 0

(Integrated LAN Controller)

1 KB anywhere in 4-GB

range USB EHCI

Controller 2 Enable via standard PCI mechanism (Device

29, Function 7)

512 B anywhere in 4-GB

range AC ’97 Host

Controller (Mixer) Enable via standard PCI mechanism (Device

30, Function 2)

256 B anywhere in 4-GB

range

AC ’97 Host

Controller (Bus

Master)

Enable via standard PCI mechanism (Device

30, Function 3)

512 B anywhere in 64 -bi t

addressing space

Intel® High

Definition Audio

Host Controller

Enable via standard PCI mechanism (Device

30, Function 1)

FED0 X000h–FED0 X3FFh High Precision

Event Timers 3

BIOS determines the “fixed” location which is

one of four, 1-KB ranges where X (in the first

column) is 0h, 1h, 2h, or 3h.

All other PCI None

Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)

Memory Range Target Dependency/Comments

Intel ® ICH7 Family Datasheet 261

6.4.1 Boot-Block Update Scheme

The ICH7 supports a “top-block swap” mode that has the ICH7 swap the top block in

the Firmware Hu b (the boot block) with another location. This allows for safe update of

the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is

set, the ICH7 will invert A16 for cycles targeting Firmware Hub space. When this bit is

0, the ICH7 will not invert A16. This bit is automatically set to 0 by RTCRST#, but not

by PLTRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block,

and the block immediately below the top block is reserved for doing boot-block

updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top

2. Software checks that the copied block is correct. This could be done by performing

a checksum calculation.

3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the

Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be

directed to FFFE_0000h through FFFE_FFFFh in the Fi rmware Hub, and processor

accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h

through FFFF_FFFFh.

4. Software erases the top block

5. Software writes the new top block

6. Software checks the new top block

7. Software clears the TOP_SWAP bit

8. Software sets the Top_Swap Lock-Down bit

If a power failure occurs at any point after step 3, the system will be able to boot from

the copy of the boot block that is stored in the block below the top. This is because the

TOP_SWAP bit is backed in the RTC well.

Note: The top-block swap mode may be forced by an external strapping option (See

Section 2.24.1). When top-block swap mode is forced in this manner, the TOP_SWAP

bit cannot be cleared by software. A re-boot with the str ap remov e d will be required to

exit a forced top-block swap mode.

Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature

space.

Note: The top-block swap mode has no effect on accesses below FFFE_0000h.

262 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 263

Chipset Configuration Registers

7 Chipset Configuration Registers

This chapter describes all registers and base functionality that is related to chipset

configuration and not a specific interface (e.g., LPC, PCI, or PCI Express*). It contains

the root complex register block that describes the behavior of the upstream internal

link.

This block is mapped into memory space, using register RCBA of the PCI -to-LPC bridge.

Accesses in this space must be limited to 32-(DWord) bit quantities. Burst accesses are

not allowed.

7.1 Chipset Configuration Registers (Memory Space)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2

for details).

Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3)

Offset Mnemonic Register Name Default Type

0000–0003h VCH Virtua l Channel Capability

Header 10010002h RO

0004–0007h VCAP1 Virtual Channel Capability #1 00000801h RO

0008–000Bh VCAP2 Virtual Channel Capability #2 00000001h RO

000C–000Dh PVC Port Virtual Channel Control 0000h R/W, RO

000E–000Fh PVS Port Virtual Channel Status 0000h RO

0010–0013h V0CAP Virtual Channe l 0 Resource

Capability 00000001h RO

0014–0017h V0CTL Virtual Channel 0 Resource

Control 800000FFh R/W, RO

001A–001Bh V0STS Virtual Channel 0 Resource

Status 0000h RO

001C–001Fh V1CAP Virtual Channel 1 Resource

Capability 30008010h R/WO, RO

0020–0023h V1CTL Virtual Channel 1 Resource

Control 00000000h R/W, RO

0026–0027h V1STS Virtual Channel 1 Resource

Status 0000h RO

0100–0103h RCTCL Root Complex Topology

Capability List 1A010005h RO

0104–0107h ESD Element Self Description 00000602h R/WO, RO

0110–0113h ULD Upstream Link Descriptor 00000001h R/WO, RO

0118–011Fh ULBA Upstream Link Base Address 0000000000000000h R/WO

0120–0123h RP1D Root Port 1 Descriptor 01xx0002h R/WO, RO

0128–012Fh RP1BA Root Port 1 Base Address 00000000000E0000h RO

0130–0133h RP2D Root Port 2 Descriptor 02xx0002h R/WO, RO

0138–013Fh RP2BA Root Port 2 Base Address 00000000000E1000h RO

0140–0143h RP3D Root Port 3 Descriptor 03xx0002h R/WO, RO

Chipset Configuration Registers

264 Intel ® ICH7 Family Datasheet

0148–014Fh RP3BA Root Port 3 Base Address 00000000000E2000h RO

0150–0153h RP4D Root Port 4 Descriptor 04xx0002h R/WO, RO

0158–015Fh RP4BA Root Port 4 Base Address 00000000000E3000h RO

0160–0163h HDD Intel® High Definition Audio

Descriptor 05xx0002h R/WO, RO

0168–016Fh HDBA Intel® High Definition Audio

Base Address 00000000000D8000

hRO

0170–0173h RP5D Root Port 5 Descriptor 05xx0002h R/WO, RO

0178–017Fh RP5BA Root Port 5 Base Address 00000000000E4000h RO

0180–0183h RP6D Root Port 6 Descriptor 06xx0002h R/WO, RO

0188–018Fh RP6BA Root Port 6 Base Address 00000000000E5000h RO

01A0–01A3h ILCL Internal Link Capability List 00010006h RO

01A4–01A7h LCAP Link Capabilities 00012441h RO, R/WO

01A8–01A9h LCTL Link Control 0000h R/W

01AA–01ABh LSTS Link Status 0041h RO

0224–0227h RPC Root Port Configuration 0000000xh R/W, RO

0238–023Bh RPFN Root Port Function Number for

PCI Express Root Ports

(Desktop and Mobile only) 00543210h R/WO, RO

1E00–1E03h TRSR Trap Status Register 00h R/WC, RO

1E10–1E17h TRCR Trapped Cycle Re gister 0000000000000000h RO

1E18-1E1Fh TWDR Trapped Write Data Register 0000000000000000h RO

1E80-1E87h IOTR0 I/O Trap Register 0 0000000000000000h R/W, RO

1E88-1E8Fh IOTR1 I/O Trap Register 1 0000000000000000h R/W, RO

1E90-1E97h IOTR2 I/O Trap Register 2 0000000000000000h R/W, RO

1E98-1E9Fh IOTR3 I/O Trap Register 3 0000000000000000h R/W, RO

3000–3001h TCTL TCO Control 00h R/W

3100–3103h D31IP Device 31 Interrupt Pin 00042210h R/W, RO

3104–3107h D30IP Device 30 Interrupt Pin 00002100h R/W, RO

3108–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W

310C–310Fh D28IP Device 28 Interrupt Pin 00004321h R/W

3110–3113h D27IP Device 27 Interrupt Pin 00000001h R/W

3140–3141h D31IR Device 31 Interrupt Route 3210h R/W

3142–3143h D30IR Device 30 Interrupt Route 3210h R/W

3144–3145h D29IR Device 29 Interrupt Route 3210h R/W

3146–3147h D28IR Device 28 Interrupt Route 3210h R/W

3148–3149h D27IR Device 27 Interrupt Route 3210h R/W

31FF–31FFh OIC Other Interrupt Control 00h R/W

3400–3403h RC RTC Configuration 00000000h R/W,

R/WLO

3404–3407h HPTC High Precision Timer

Configuration 00000000h R/W

Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3)

Offset Mnemonic Register Name Default Type

Intel ® ICH7 Family Datasheet 265

Chipset Configuration Registers

7.1.1 VCH—Virtual Channel Capability Header Register

Offset Address: 0000–0003 h Attribute: RO

Default Value: 10010002h Size: 32-bit

7.1.2 VCAP1—Virtual Channel Capability #1 Register

Offset Address: 0004–0007 h Attribute: RO

Default Value: 00000801h Size: 32-bit

3410–3413h GCS General Control and Status 0000000xh R/W,

R/WLO

3414–3414h BUC B acked Up Control

0000001xb

(Mobile/ Ultra Mobi le

Only)

0000000xb

(Desktop Only)

R/W

3418–341Bh FD Function Disable See bit description R/W, RO

341C–341Fh CG Clock Gating (Mobile/Ultra

Mobile Only) 00000000h R/W, RO

Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)

Offset Mnemonic Register Name Default Type

Bit Description

31:20 Next Capability Offset (NCO) — RO.This field indicates the next item in the list.

19:16 Capability Version (CV) — RO. This field indicates support as a version 1 capability

structure.

15:0 Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability

item.

Bit Description

31:12 Reserved

11:10 P ort Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port

arbitration table is 4 bits (to allow up to 8 ports).

9:8 Reference Clock (RC) — RO. Fixed at 100 ns.

7 Reserved

6:4 Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no

additional VCs of low priority with extended capabilities .

3 Reserved

2:0 Extended VC Count (EVC) — RO. This field indicates that there is one additional VC

(VC1) that exists with extended capabi lities.

Chipset Configuration Registers

266 Intel ® ICH7 Family Datasheet

7.1.3 VCAP2—Virtual Channel Capability #2 Register

Offset Address: 0008–000Bh Attribute: RO

Default Value: 00000001h Size: 32-bit

7.1.4 PVC—Port Virtual Channel Control Register

Offset Address: 000C–000D h Attribute: R/W, RO

Default Value: 0000h Size: 16-bit

7.1.5 PVS—Port Virt ual Channel Status Register

Offset Address: 000E–000Fh Attribute: RO

Default Value: 0000h Size: 16-bit

Bit Description

31:24 VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present

for VC arbitration since it is fixed.

23:8 Reserved

7:0 VC Arbitration Capability (AC) — RO. This field indicates that the VC arbitration is

fixed in the root complex. VC1 is highest priority and VC0 is lowest priority.

Bit Description

15:04 Reserved

3:1 VC Arbitration Select (AS) — RO. This field indicates which VC should be programmed

in the VC arbitration table. The root complex takes no action on the setting of this

field since there is no arbitration table.

0Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed

should be loaded into the VC arbitration table. This bit is defined as read/write with

always returning 0 on reads.

Bit Description

15:01 Reserved

0VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the

VC Arbitration table when it is being updated. This field is always 0 in the root

complex since there is no VC arbitration table.

Intel ® ICH7 Family Datasheet 267

Chipset Configuration Registers

7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register

Offset Address: 0010–0013 h Attribute: RO

Default Value: 00000001h Size: 32-bit

7.1.7 V0CTL—Virtual Channel 0 Resource Control Register

Offset Address: 0014–0017 h Attribute: R/W, RO

Default Value: 800000FFh Size: 32-bit

Bit Description

31:24 Port Arbitr ation Table Offset (A T) — RO. This VC impl emen ts n o port arbitration table

since the arbitration is fixed.

23 Reserved

22:16 Maximum Time Slot s (MTS) — RO. This VC implements fixed arbitration, and

therefore this field is not used.

15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable

transactions.

14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not

just advanced packet switching transactions.

13:8 Reserved

7:0 Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed

port arbitration.

Bit Description

31 Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and

cannot be disabled.

30:27 Reserved

26:24 Virtual Channel Identifier (ID) — RO. This field indicates the ID to use for this virtual

channel.

23:20 Reserved

19:17 Port Arbitration Select (PAS) — R/W. This field indicates which port table is being

programmed. The root complex tak es no action on this setting since the arbitration is

fixed and there is no arbitration table.

16 Load Port Arbitration Table (LAT) — RO. The root complex does not im plement an

arbitration table for this virtual channel.

15:8 Reserved

7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates

which transaction classes are mapped to this virtual chann el. When a bit is set, thi s

transaction class is mapped to the virtual channel.

0 Reserved

Chipset Configuration Registers

268 Intel ® ICH7 Family Datasheet

7.1.8 V0STS—Virtual Channel 0 Resource Status Register

Offset Address: 001A–001Bh Attribute: RO

Default Value: 0000h Size: 16-bit

7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register

Offset Address: 001C–001Fh Attribute: R/WO, RO

Default Value: 30008010h Size: 32-bit

Bit Description

15:02 Reserved

1VC Negotiation Pending (NP) — RO. When set, this bit indicates the virtual

channel is still being negotiated with ingress ports.

0Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for this

VC, so this bit is reserved at 0.

Bit Description

31:24 Port Arbitration Table Offset (AT) — RO. This field indicates the location of the port

arbitration table in the root complex. A value of 3h indicates the table is at offset

30h.

23 Reserved

22:16 Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS

based upon the determination of the number of time slots available in the platform.

15 Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are

rejected. This VC is for isochronous transfers only.

14 Advanced Packet Switching (AP S ) — RO. This VC is capable of all transact ions, not

just advanced packet switching transactions.

13:8 Reserved

7:0 Port Arbitration Capability (PAC) — RO. This field indicates the port arbitration

capability is time-based WRR of 128 phases.

Intel ® ICH7 Family Datasheet 269

Chipset Configuration Registers

7.1.10 V1CTL—Virtual Channel 1 Resource Control Register

Offset Address: 0020–0023 h Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

7.1.11 V1STS—Virtual Channel 1 Resource Status Register

Offset Address: 0026–0027 h Attribute: RO

Default Value: 0000h Size: 16-bit

Bit Description

31 Virtual Channel Enable (EN) — R/W.

0 = Disables the VC.

1 = Enables the VC.

30:27 Reserved

26:24 Virtual Channel Identifier (ID) — R/W. This field indicates the ID to use for this

virtual channel.

23:20 Reserved

19:17 Port Arbitration Select (PAS) — R/W. This field indicates which port table is being

programmed. The only permissible value of this field is 4h for the time-based WRR

entries.

16 Load Port Arbitration Table (LAT) — RO/W. When set, the port arbitration table

loaded is based upon the PAS field in this register. This bit always returns 0 when

read.

15:8 Reserved

7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates

which transaction classes are mapped to this virtual chann el. When a bit is set, thi s

transaction class is mapped to the virtual channel.

0 Reserved

Bit Description

15:02 Reserved

1VC Negotiation Pending (NP) — RO.

0 = Virtual channel is Not being negotiated with ingress ports.

1 = The virtual channel is still being negotiated with ingress ports.

Port Arbitration Tables Status (ATS) — RO. This field indicates the coherency

status of the port arbitration table. This bit is set when LAT (offset 000Ch:bit 0) is

written with value 1 and PAS (offset 0014h:bits19:17) has value of 4h. This bit is

cleared after the table has been updated.

Chipset Configuration Registers

270 Intel ® ICH7 Family Datasheet

7.1.12 RCTCL—Root Complex Topology Capabilities List Register

Offset Address: 0100–0103h Attribute: RO

Default Value: 1A010005h Size: 32-bit

7.1.13 ESD—Element Self Description Register

Offset Address: 0104–0107h Attribute: R/WO, RO

Default Value: 00000602h Size: 32-bit

7.1.14 ULD—Upstream Link Descriptor Register

Offset Address: 0110–0113h Attribute: R/WO, RO

Default Value: 00000001h Size: 32-bit

Bit Description

31:20 Next Capability (NEXT) — RO. This field indicates the next item in the list.

19:16 Capability Version (CV) — RO. This field indicates the version of the capability

structure.

15:0 Capability ID (CID) — RO. This field indicates this is a PCI Express* link capability

section of an RCRB.

Bit Description

31:24 Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel® ICH7.

23:16 Component ID (CID) — R/WO. This field indicates the component ID assigned t o

this element by software. This is written once by platform BIOS and is locked until a

platform reset.

15:8 Number of Link Entries (NLE) — RO. This field indicates that one link entry

(corresponding to DMI), 6 root port entries (for the downstream ports), and the

Intel® High Definition Audio device are described by this RCRB.

7:4 Reserved

3:0 Element Type (ET) — RO. This field indicates that the element type is a root complex

internal link.

Bit Description

31:24 Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to

match the port number of the (G)MCH RCRB that is attached to this RCRB.

23:16 Target Component ID (TCID) — R/WO. This field is prog rammed by platform BIOS

to match the component ID of the (G)MCH RCRB that is attached to this RCRB.

15:2 Reserved

1Link Type (LT) — RO. This bit indicates that the link points to the (G)MCH RCRB.

0Link Valid (LV) — RO. This bit indicates that the link entry is valid.

Intel ® ICH7 Family Datasheet 271

Chipset Configuration Registers

7.1.15 ULBA—Upstream Link Base Address Register

Offset Address: 0118–011Fh Attribute: R/WO

Default Value: 0000000000000000h Size: 64-bit

7.1.16 RP1D—Root Port 1 Descriptor Register

Offset Address: 0120–0123 h Attribute: R/WO, RO

Default Value: 01xx0002h Size: 32-bit

7.1.17 RP1BA—Root Port 1 Base Address Register

Offset Address: 0128–012Fh Attribute: RO

Default Value: 00000000000E0000h Size: 64-bit

Bit Description

63:32 Base Address Upper (BAU) — R/WO. This field is programmed by platform BIOS to

match the upper 32-bits of base address of the (G)MCH RCRB that is attached to this

RCRB.

31:0 Base Address Lower (BAL) — R/WO. This field is programmed by platform BIOS to

match the lowe r 32-bi ts of base address of the ( G)M CH RCRB that is attac hed to this

RCRB.

Bit Description

31:24 Target P ort Number (PN) — RO . This field indicates that the target port number is 1h

(root port #1).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

0Link Valid (LV) — RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not

valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #0.

11:0 Reserved

Chipset Configuration Registers

272 Intel ® ICH7 Family Datasheet

7.1.18 RP2D—Root Port 2 Descriptor Register

Offset Address: 0130–0133h Attribute: R/WO, RO

Default Value: 02xx0002h Size: 32-bit

7.1.19 RP2BA—Root Port 2 Base Address Register

Offset Address: 0138–013Fh Attribute: RO

Default Value: 00000000000E1000h Size: 64-bit

7.1.20 RP3D—Root Port 3 Descriptor Register

Offset Address: 0140–0143h Attribute: R/WO, RO

Default Value: 03xx0002h Size: 32-bit

Bit Description

31:24 Target P ort Number (PN) — RO. This field in dicates the target port number is 2h (root

port #2).

23:16 Target Component ID (TCID) — R/WO. This fiel d returns the value of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘01’, ‘10’, or ‘11’, or

FD. PE2D (offset 3418h, bit 17) is set, the link for this root port is no t valid (return 0).

When RPC.PC is ‘00’ and FD.PE2D is cleared, the link for this root port is valid (return

1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #1.

11:0 Reserved

Bit Description

31:24 Target P ort Number (PN) — RO. This field in dicates the target port number is 3h (root

port #3).

23:16 Target Component ID (TCID) — R/WO. This fiel d returns the value of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘11’, or FD.PE3D

(offset 3418h, bit 18) is set, the link for this root port is not valid (return 0). When

RPC.PC is ‘00’, ‘01’, or “10’, and FD.PE3D is cleared, the l ink for this root port is valid

(return 1).

Intel ® ICH7 Family Datasheet 273

Chipset Configuration Registers

7.1.21 RP3BA—Root Port 3 Base Address Register

Offset Address: 0148–014Fh Attribute: RO

Default Value: 00000000000E2000h Size: 64-bit

7.1.22 RP4D—Root Port 4 Descriptor Register

Offset Address: 0150–0153 h Attribute: R/WO, RO

Default Value: 04xx0002h Size: 32-bit

7.1.23 RP4BA—Root Port 4 Base Address Register

Offset Address: 0158–015Fh Attribute: RO

Default Value: 00000000000E3000h Size: 64-bit

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #2.

11:0 Reserved

Bit Description

31:24 Target P ort Number (PN) — RO. This field indicates the target port number is 4h (root

port #4).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

Link Valid (LV) — RO. When RPC.PC (offset 0224h, bits 1:0) is ‘10’ or ‘11’, or

FD.P E4D (offset 3418h, bit 19) i s set, the link for this root port is not val id (return 0).

When RPC.PC is ‘00’ or ‘01’ and FD.PE4D is cleared, the link for this root port is valid

(return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #3.

11:0 Reserved

Chipset Configuration Registers

274 Intel ® ICH7 Family Datasheet

7.1.24 HDD—Intel® High Definition Audio Descriptor Register

Offset Address: 0160–0163h Attribute: R/WO, RO

Default Value: 15xx0002h Size: 32-bit

7.1.25 HDBA—Intel® High Definition Audio Base Address Register

Offset Address: 0168–016Fh Attribute: RO

Default Value: 00000000000D8000h Size: 64-bit

7.1.26 RP5D—Root Port 5 Descriptor Register

Offset Address: 0170–0173h Attribute: R/WO, RO

Default Value: 05xx0002h Size: 32-bit

Bit Description

31:24 Target Port Number (PN) — RO. This field indicates the target port number is 15h

(Intel® High Definition Audio).

23:16 Target Component ID (TCID) — R/WO. This fiel d returns the value of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

0Link Valid (LV) — RO. Whe n FD.ZD (offset 3418h, bit 4) is set, the link to Intel High

Definition Audio is not valid (return 0). When FD.ZD is cleared, the link to Intel High

Definition Audio is valid (return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #27.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #0.

11:0 Reserved

Bit Description

31:24 Target P ort Number (PN) — RO. This field in dicates the target port number is 5h (root

port #5).

23:16 Target Component ID (TCID) — R/WO. This fiel d returns the value of the ESD.CID

(offset 0104h, bits 23:16) fie ld progr ammed by platfo rm BIOS, since the root port is

in the same compone nt as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

0Link Valid (LV) — RO. When FD.PE5D (offset 3418h, bit 20) is set, the link for this

root port is not valid (return 0). When FD .PE5D is cleare d, the link for this root port is

valid (return 1).

Intel ® ICH7 Family Datasheet 275

Chipset Configuration Registers

7.1.27 RP5BA—Root Port 5 Base Address Register

Offset Address: 0178–017Fh Attribute: RO

Default Value: 00000000000E4000h Size: 64-bit

7.1.28 RP6D—Root Port 6 Descriptor Register

Offset Address: 0180–0183 h Attribute: R/WO, RO

Default Value: 06xx0002h Size: 32-bit

7.1.29 RP6BA—Root Port 6 Base Address Register

Offset Address: 0188–018Fh Attribute: RO

Default Value: 00000000000E5000h Size: 64-bit

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #4.

11:0 Reserved

Bit Description

31:24 Target P ort Number (PN) — RO. This field indicates the target port number is 6h (root

port #6).

23:16 Target Compo nent ID (TCID ) — R/WO. This field returns the value of the ESD .CID

(offset 0104h, bi ts 23 :16 ) field progr amm ed by platform BIOS, since the root port is

in the same component as the RCRB.

15:2 Reserved

1 Link Type (LT) — RO. This bit indicates that the link points to a root port.

0Link Valid (LV) — RO. When RPC.PC2 (offset 0224h, bits 1:0) is ‘01’ or FD.PE6D

(offset 3418h, bit 21) is set, the link for this root port is not valid (return 0). When

RPC.PC is ‘00’ and FD.PE6D is cleared, the link for this root port is valid (return 1).

Bit Description

63:32 Reserved

31:28 Reserved

27:20 Bus Number (BN) — RO. This field indicates the root port is on bus #0.

19:15 Device Number (DN) — RO. This field indicates the root port is on device #28.

14:12 Function Number (FN) — RO. This field indicates the root port is on function #5.

11:0 Reserved

Chipset Configuration Registers

276 Intel ® ICH7 Family Datasheet

7.1.30 ILCL—Internal Link Capabilities List Regi ster

Offset Address: 01A0–01A3 h Attribute: RO

Default Value: 00010006h Size: 32-bit

7.1.31 LCAP—Link Capabilities Register

Offset Address: 01A4–01A7 h Attribute: RO/ R/WO

Default Value: 00012441h Size: 32-bit

Bit Description

31:20 Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.

19:16 Capability Version (CV) — RO. This field indicates the version of the capability

structure.

15:0 Capability ID (CID) — RO. This field indicates this is capability for DMI.

Bit Description

31:18 Reserved

17:15

Desktop

Only L1 Exit Latency (EL1) — L1 not supported on DMI.

17:15

Mobile/

Ultra

Mobile

Only

L1 Exit Latency (EL1) — RO. This field is set to 010b to indicate an exit latency of

2us to 4 us.

14:12 L0s Exit Latency (E L0) — R/WO. Th is field indicate s that exit latenc y is 128 ns to less

than 256 ns.

11:10

Desktop

Only

Active State Link PM Support (ASPM) — R/WO. This field indicates that L0s is

supported on DMI.

11:10

Mobile/

Ultra

Mobile

Only

Active State Link PM Support (ASPM) — R/WO. This field indicates the level of active

state power management on DMI.

00 = Neither L0s nor L1s are supported

01 = L0s Entry supported on DMI

10 = L1 Entry supported on DMI

11 = Both L0s and L1 supported on DMI

9:4 Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.

3:0 Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.

Intel ® ICH7 Family Datasheet 277

Chipset Configuration Registers

7.1.32 LCTL—Link Control Register

Offset Address: 01A8–01A 9h Attribute: R/W

Default Value: 0000h Size: 16-bit

7.1.33 LSTS—Link Status Register

Offset Address: 01AA–01ABh Attribute: RO

Default Value: 0041h Size: 16-bit

Bit Description

15:8 Reserved

7Extended Synch (ES) — R/W. When set, this bit forces extended transmission of

FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Mobile/

Ultra Mobile Only) at exit from L1 prior to entering L0.

6:2 Reserved

1:0

Desktop

Only

Active State Link PM Control (APMC) — R/W. This field indicates whether DMI

should enter L0s.

00 = Disabled

01 = L0s entry enabled

10 = Reserved

11 = Reserved

1:0

Mobile/

Ultra

Mobile

Only

Active State Link PM Control (APMC) — R/W. This field indicates whether DMI

should enter L0s or L1 or both.

00 = Disabled

01 = L0s entry enabled

10 = L1 Entry enabled

11 = L0s and L1 Entry enabled

Bit Description

15:10 Reserved

9:4 Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).

Mobile/Ultra Mobile only: The ICH7 may also indicate x2 (000010b), depending on

(G)MCH configuration.

3:0 Link Speed (LS) — RO. Link is 2.5 Gb/s.

Chipset Configuration Registers

278 Intel ® ICH7 Family Datasheet

7.1.34 RPC—Root Port Configuration Register

Offset Address: 0224–0227h Attribute: R/W, RO

Default Value: 0000000yh (y = 00xxb) Size: 32-bit

Bit Description

31:8 Reserved

High Priority Port Enable (HPE ) — R/W.

0 = The high priority path is not enabled.

1 = The port selected by the HPP field in this register is enabled for high priority. It

will be arbitrated above all other VC0 (including integrated VC0) devices.

6:4

High Priority Port (HPP) — R/W. This field controls which port is enabled for high

priority when the HPE bit in this register is set.

111 = Reserved

110 = Reserved

101 = Port 6

100 = Port 5

100 = Port 4

010 = Port 3

001 = Port 2

000 = Port 1

3 Reserved

Port Configuration2 (PC2) — RO. This bit controls how the PCI bridges are

organized in various modes of operation for Ports 5 and 6.

1 = Reserved

0 = 2 x1s, Port 5 (x1), Port 6 (x1)

This bit is in the resume well and is only reset by RSMRST#.

1:0

Port Configuration (PC) — RO. This field controls how the PCI bridges are

organized in various modes of operation. For the following mappings, if a port is not

shown, it is considered a x1 port with no connection.

These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0)

when TP3 is not pulled low at the rising edge of PWROK.

11 = 1 x4, Port 1 (x4)

10 = Reserved

01 = Reserved

00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)

These bits live in the resume well and are only reset by RSMRST#.

Intel ® ICH7 Family Datasheet 279

Chipset Configuration Registers

7.1.35 RPFN—Root Port Function Number for PCI Express Root

Ports (Desktop and Mobile only)

Offset Address: 0238–023Bh Attribute: R/WO, RO

Default Value: 00543210h Size: 32-bit

For the PCI Express root ports, the assignment of a function number to a root port is

not fixed. BIOS may re-assign the function numbers on a port by port basis. This

capability will allow BIOS to disable/hide any root port and have still have functions 0

thru N-1 where N is the total number of enabled root ports.

Port numbers will remain fixed to a physical root port.

The existing root port Function Disable registers operate on physical ports (not

functions).

Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number

assignment and is associated with physical ports.

Bit Description

31:23 Reserved

22:20 Root Port 6 Function Number (RP6FN) — R/WO. These bits set the function

number for PCI Express Root Port 6. This root port function number must be a

unique value from the other root port function numbers.

19 Reserved

18:16 Root Port 5 Function Number (RP5FN) — R/WO. These bits set the function

number for PCI Express Root Port 5. This root port function number must be a

unique value from the other root port function numbers.

15 Reserved

14:12 Root Port 4 Function Number (RP4FN) — R/WO. These bits set the function

number for PCI Express Root Port 4. This root port function number must be a

unique value from the other root port function numbers.

11 Reserved

10:8 Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function

number for PCI Express Root Port 3. This root port function number must be a

unique value from the other root port function numbers.

7 Reserved

6:4 Root Port 2 Function Number (RP2FN) — R/WO. These bits set the function

number for PCI Express Root Port 2. This root port function number must be a

unique value from the other root port function numbers.

3 Reserved

2:0 Root Port 1 Function Number (RP1FN) — R/WO. These bits set the function

number for PCI Express Root Port 1. This root port function number must be a

unique value from the other root port function numbers.

Chipset Configuration Registers

280 Intel ® ICH7 Family Datasheet

7.1.36 TRSR—Trap Status Register

Offset Address: 1E00–1E03h Attribute: R/WC, RO

Default Value: 00000000h Size: 32-bit

7.1.37 TRCR—Trapped Cycle Register

Offset Address: 1E10–1E17h Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves information about th e I/O Cycle that was tr apped and generated the

SMI# for software to read.

7.1.38 TWDR—Trapped Write Data Register

Offset Address: 1E18–1E1Fh Attribute: RO

Default Value: 0000000000000000h Size: 64-bit

This register saves the data from I/O write cycles that are trapped for software to read.

Bit Description

31:4 Reserved

3:0

Cycle Trap SMI# Status (CTSS ) — R/WC. These bits are set by hardware when the

corresponding Cycle Trap register is enabled and a matching cycle is received (and

trapped). These bits are OR’ed together to create a single status bit in the Power

Management register space.

Note that the SMI# and trapping must be enabled in order to set these bits.

These bits are set before the completion is generated for the trapped cycle, thereby

ensuring that the processor can enter the SMI# handler when the instruction

completes. Each status bit is cleared by writing a 1 to the corresponding bit location

in this register.

Bit Description

63:25 Reserved

24 Read/Write# (RWI) — RO.

0 = Trapped cycle was a write cycle.

1 = Trapped cycle was a read cycle.

23:20 Reserved

19:16 Active-high Byte Enables (AHBE) — RO. This is the DWord-aligned byte enables

associated with the trapped cycle. A 1 in any bit location in dicates that the

corresponding byte is enabled in the cycle.

15:2 Trapped I/O Address (TIOA) — RO. This is the DWord-aligned address of the

trapped cycle.

1:0 Reserved

Bit Description

63:32 Reserved

31:0 Trapped I/O Data (TIOD) — RO. DWord of I/O write data. This field is undefined

after trapping a read cycle.

Intel ® ICH7 Family Datasheet 281

Chipset Configuration Registers

7.1.39 IOTRn — I/O Trap Register (0-3)

Offset Address: 1E80–1E87h Register 0 Attribute: R/W, RO

1E88–1E8Fh Register 1

1E90–1E97h Register 2

1E98–1E9Fh Register 3

Default Value: 0000000000000000h Size: 64-bit

These registers are used to specify the set of I/O cycles to be trapped and to enable

this functionality.

Bit Description

63:50 Reserved

49 Read/Write Mask (RWM) — R/W.

0 = The cycle must match the type specified in bit 48.

1 = Trapping logic will operate on both read and write cycles.

Read/Write# (RWIO) — R/W.

0 = Write

1 = Read

NOTE: The value in this field does not matter if bit 49 is set.

47:40 Reserved

39:36 Byte Enable Mask (BEM) — R/W. A 1 in any bit position indicates that any value in

the corresponding byte enable bit in a received cycle will be treated as a match. The

corresponding bit in the Byte Enables field, below, is ignored.

35:32 Byte Enables (TBE) — R/W. Active-high DWord-aligned byte enables.

31:24 Reserved

23:18

Address[7:2] Mask (ADMA) — R/W. A 1 in any bit position indicates that any value

in the corresponding address bit in a received cycle will be treated as a match. The

corresponding bit in the Address field, below, is ignored. The mask is only provided

for the lower 6 bits of the DW ord address, allowing for tr aps on address r anges up to

256 bytes in size.

17:16 Reserved

15:2 I/O Address[15:2] (IOAD ) — R/W. DWord-aligned address

1 Reserved

0Trap and SMI# Enable (TRSE) — R/W.

0 = Trapping and SMI# logic disabled.

1 = The trapping logic specified in this register is enabled.

Chipset Configuration Registers

282 Intel ® ICH7 Family Datasheet

7.1.40 TCTL—TCO Configuration Regist er

Offset Address: 3000–3000h Attribute: R/W

Default Value: 00h Size: 8-bit

Bit Description

7TCO IRQ Enable (IE) — R/W.

0 = TCO IRQ is disabled.

1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.

6:3 Reserved

2:0

TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear.

If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that

interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI

interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and

can be shared with other interrupt.

000 = IRQ 9

001 = IRQ 10

010 = IRQ 11

011 = Reserved

100 = IRQ 20 (only if APIC enabled)

101 = IRQ 21 (only if APIC enabled)

110 = IRQ 22 (only if APIC enabled)

111 = IRQ 23 (only if APIC enabled)

NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching.

NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should

be programmed for active-high reception. When the interrupt is mapped to

APIC interrupts 20 through 23, the APIC should be programmed for active-

low reception.

Intel ® ICH7 Family Datasheet 283

Chipset Configuration Registers

7.1.41 D31IP—Device 31 Interrupt Pin Regi ster

Offset Address: 3100–3103 h Attribute: R/W, RO

Default Value: 00042210h Size: 32-bit

Bit Description

31:16 Reserved

15:12

SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller

drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

11:8

SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as

its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

7:4

PATA Pin (PIP) — R/W. This field indicates which pin the PATA controller drives as

its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

3:0 PCI Bridge Pin (PCIP) — RO. Currently, the PCI bridge does not generate an interrupt,

so this field is read-only and 0.

Chipset Configuration Registers

284 Intel ® ICH7 Family Datasheet

7.1.42 D30IP—Device 30 Interrupt Pin Register

Offset Address: 3104–3107h Attribute: R/W, RO

Default Value: 00002100h Size: 32-bit

Bit Description

31:16 Reserved

15:12

(Desktop

and

Mobile

Only)

AC ‘97 Modem Pin ( AMIP) — R/W. This field indicates which pin the AC ‘97 Modem

controller drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

15:12

(Ultra

Mobile

Only)

Reserved

11:8

(Desktop

and

Mobile

Only)

AC ‘97 Audio Pin (AAIP) — R/W. This field indicates which pin the AC ‘97 audio

controller drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

11:8

(Ultra

Mobile

Only)

Reserved

7:4 Reserved

3:0 LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt,

so this field is read-only and 0.

Intel ® ICH7 Family Datasheet 285

Chipset Configuration Registers

7.1.43 D29IP—Device 29 Interrupt Pin Regi ster

Offset Address: 3108–310Bh Attribute: R/W

Default Value: 10004321h Size: 32-bit

Bit Description

31:28

EHCI Pin (EIP) — R/W. This field indicates which pin the EHCI controller drives as

its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

27:16 Reserved

15:12

UHCI #3 Pin (U3P) — R/W. This field indicates which pin the UHCI controller #3

(ports 6 and 7) drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD# (Default)

5h–Fh = Reserved

11:8

UHCI #2 Pin (U2P) — R/W. This field indicates which pin the UHCI controller #2

(ports 4 and 5) drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h–Fh = Reserved

7:4

UHCI #1 Pin (U1P) — R/W. This field indicates which pin the UHCI controller #1

(ports 2 and 3) drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

3:0

UHCI #0 Pin (U0P) — R/W. This field indicates which pin the UHCI controller #0

(ports 0 and 1) drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Chipset Configuration Registers

286 Intel ® ICH7 Family Datasheet

7.1.44 D28IP—Device 28 Interrupt Pin Register (Desktop and

Mobile Only)

Offset Address: 310C–310Fh Attribute: R/W

Default Value: 00214321h Size: 32-bit

Bit Description

31:24 Reserved

23:20

PCI Express #6 Pin ( P6IP) — R/W. This field indicates which pi n t he P CI Ex p res s*

port #6 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

19:16

PCI Express #5 Pin (P5 I P ) — R/W. This field indicates which pin the PCI Express

port #5 drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

15:12

PCI Express #4 Pin ( P4IP) — R/W. This field indicates which pi n t he P CI Ex p res s*

port #4 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC#

4h = INTD# (Default)

5h–Fh = Reserved

11:8

PCI Express #3 Pin (P3 I P ) — R/W. This field indicates which pin the PCI Express

port #3 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB#

3h = INTC# (Default)

4h = INTD#

5h–Fh = Reserved

7:4

PCI Express #2 Pin (P2 I P ) — R/W. This field indicates which pin the PCI Express

port #2 drives as its interrupt.

0h = No interrupt

1h = INTA#

2h = INTB# (Default)

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Intel ® ICH7 Family Datasheet 287

Chipset Configuration Registers

7.1.45 D27IP—Device 27 Interrupt Pin Regi ster

Offset Address: 3110–3113 h Attribute: R/W

Default Value: 00000001h Size: 32-bit

7.1.46 D31IR—Device 31 Interrupt Route Register

Offset Address: 3140–3141 h Attribute: R/W

Default Value: 3210h Size: 16-bit

3:0

PCI Express #1 Pin (P1IP) — R/W.This field iIndicates which pin the PCI Express

port #1 drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h–Fh = Reserved

Bit Description

31:4 Reserved

3:0

Intel® High Definition Audio Pin (ZIP) — R/W. This field indicates which pin the

Intel High Definition Audio controller drives as its interrupt.

0h = No interrupt

1h = INTA# (Default)

2h = INTB#

3h = INTC#

4h = INTD#

5h-Fh = Reserved

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTD# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: Ultra Mobile. PIRQA#–PIRQD# are not on the ICH7U. Eventhough the register

defaults to a non-ICH7U pin routing, BIOS default sets the register for

PIRQE#–PIRQH#.

11 Reserved

Chipset Configuration Registers

288 Intel ® ICH7 Family Datasheet

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTC# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTB# pin reported for device 31 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h physical pin on the

ICH7 is connected to the INTA# pin reported for device 31 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

Bit Description

Intel ® ICH7 Family Datasheet 289

Chipset Configuration Registers

7.1.47 D30IR—Device 30 Interrupt Route Register

Offset Address: 3142–3143 h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTD# pin reported for device 30 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to a non-

ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTC# pin reported for device 30 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTB# pin reported for device 30 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

3 Reserved

Chipset Configuration Registers

290 Intel ® ICH7 Family Datasheet

7.1.48 D29IR—Device 29 Int errupt Route Register

Offset Address: 3144–3145h Attribute: R/W

Default Value: 3210h Size: 16-bit

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h physical pin on the

ICH7 is connected to the INTA# pin reported for device 30 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTD# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTC# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

7 Reserved

Intel ® ICH7 Family Datasheet 291

Chipset Configuration Registers

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTB# pin reported for device 29 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTA# pin reported for device 29 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

Bit Description

Chipset Configuration Registers

292 Intel ® ICH7 Family Datasheet

7.1.49 D28IR—Device 28 Int errupt Route Register

Offset Address: 3146–3147h Attribute: R/W

Default Value: 3210h Size: 16-bit

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTD# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTC# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

7 Reserved

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTB# pin reported for device 28 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

3 Reserved

Intel ® ICH7 Family Datasheet 293

Chipset Configuration Registers

7.1.50 D27IR—Device 27 Interrupt Route Register

Offset Address: 3148–3149 h Attribute: R/W

Default Value: 3210h Size: 16-bit

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTA# pin reported for device 28 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

Bit Description

15 Reserved

14:12

Interrupt D Pin Route (IDR) — R/W. This field indicates which physical pin on the

Intel® ICH7 is connected to the INTD# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC#

3h = PIRQD# (Default)

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

11 Reserved

10:8

Interrupt C Pin Route (ICR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTC# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB#

2h = PIRQC# (Default)

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are n ot on Ultr a Mobile. Ev enthough the register defaults to

a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.

7 Reserved

Chipset Configuration Registers

294 Intel ® ICH7 Family Datasheet

7.1.51 OIC—Other Interrupt Control Register

Offset Address: 31FF–31FFh Attrib ute: R/W

Default Value: 00h Size: 8-bit

6:4

Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the

ICH7 is connected to the INTB# pin reported for device 27 functions.

0h = PIRQA#

1h = PIRQB# (Default)

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

3 Reserved

2:0

Interrupt A Pin Route (IAR) — R/W. This field indicates whic h physical pin on the

ICH7 is connected to the INTA# pin reported for device 27 functions.

0h = PIRQA# (Default)

1h = PIRQB#

2h = PIRQC#

3h = PIRQD#

4h = PIRQE#

5h = PIRQF#

6h = PIRQG#

7h = PIRQH#

NOTE: PIRQA#–PIRQD# are not on Ultr a Mobile. Eventhough the register defaults to

a non-ICH7U pin routing, BIOS default sets the regist er for PIRQE#–PIRQH#.

Bit Description

7:2 Reserved

Coprocessor Error Enable (CEN) — R/W.

0 = FERR# will not generate IRQ13 nor IGNNE#.

1 = If FERR# is low, th e Intel® ICH7 gener ates IRQ13 internally and holds it until an

I/O port F0h write. It will also drive IGNNE# active.

0APIC Enable (AEN) — R/W.

0 = The internal IOxAPIC is disabled.

1 = Enable s the internal IOxAPIC and its address decode.

Intel ® ICH7 Family Datasheet 295

Chipset Configuration Registers

7.1.52 RC—RTC Configuration Register

Offset Address: 3400–3403 h Attribute: R/W, R/WLO

Default Value: 00000000h Size: 32-bit

7.1.53 HPTC—High Precision Timer Configuration Register

Offset Address: 3404–3407 h Attribute: R/W

Default Value: 00000000h Size: 32-bit

Bit Description

31:5 Reserved

Upper 128 Byte Lock (UL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h–3Fh in the upper 128-byte bank of RT C RAM are locked and cannot be

accessed. Writes will be dropped and reads will not return valid data. This bit is

reset on system reset.

Lower 128 Byte Lock (LL) — R/WLO.

0 = Bytes not locked.

1 = Bytes 38h–3Fh in the lower 128-b yte bank of RT C RAM are lock ed and cannot be

accessed. Writes will be dropped and reads will not return valid data. Bit reset on

system reset.

2Upper 128 Byte Enable (UE) — R/W.

0 = Bytes locked.

1 = The upper 128-byte bank of RTC RAM can be accessed.

1:0 Reserved

Bit Description

31:8 Reserved

Address Enable (AE) — R/W.

0 = Address disabled.

1 = The Intel® ICH7 will decode the High Precision Timer memory address range

selected by bits 1:0 below.

6:2 Reserved

1:0

Address Select (AS) — R/W. This field selects 1 of 4 possible memory address

ranges for the High Precision Timer functionality. The encodin g s are:

00 = FED0_0000h – FED0_03FFh

01 = FED0_1000h – FED0_13FFh

10 = FED0_2000h – FED0_23FFh

11 = FED0_3000h – FED0_33FFh

Chipset Configuration Registers

296 Intel ® ICH7 Family Datasheet

7.1.54 GCS—General Control and Status Register

Offset Address: 3410–3413h Attribute:R/W, R/WLO

Default Value: 00000yy0h (yy = xx0000x0b) Size: 32-bit

Bit Description

31:12 Reserved

11:10

Boot BIOS Straps (BBS): This field determines the destination of accesses to the

BIOS memory range. The default values for these bi ts represent the strap values of

GNT5#/GPIO17 (bit 11 ) and GNT4#/ GPIO48 (bi t 10) (acti ve- high logi c lev els ) at th e

rising edge of PWROK.

When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to

FFFF_FFFFh) is accepted by the primary side of the PCI-to-PCI bridge and forwarded

to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot

from a PCI device. The PCI -to- PCI bridge Memory Space Enable bit does not need to

be set (nor any other bits) for these cycles to go to PCI. Note that BIOS decode r ange

bits and the other BIOS protection bits have no effect when PCI is selected.

When SPI or LPC is selected, the range that is decoded is further qualified by other

configuration bits described in the respective sections.

The value in this field can be overwritten by software as long as the BIOS Interface

Lock-Down (bit 0) is not set.

Server Error Reporting Mode (SERM) — R/W.

0 = The Intel® ICH7 is the final target of all errors. The (G)MCH sends a messages to

the ICH7 for the purpose of generating NMI.

1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this

mode, if the ICH7 detects a fatal, non-fatal, or correctable error on DMI or its

downstream ports, it sends a message to the (G)MCH. If the ICH7 receives an

ERR_* message from the downstream port, it sends that message to the

(G)MCH.

8Reserved

(Mobile/

Ultra

Mobile

Only)

Mobile IDE Configuration Lock Down (MICLD) — R/WLO .

0 = Disabled.

1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system

reset occurs. This prevents rogue software from changing the default state of

the PA TA pins during boot after BIOS configures them. This bi t is write once, and

is cleared by system reset and when returning from the S3/S4/S5 states.

(Desktop

Only) Reserved

(Mobile/

Ultra

Mobile

Only)

FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break

event indication.

0 = Disabled.

1 = The ICH7-M examines FERR# during a C2, C3, or C4 state as a break event.

See Chapter 5.14.5 for a functional description.

Bits 11:10 Description

00b Reserved

01b SPI (supports shared flash with LAN)

10b PCI

11b LPC

Intel ® ICH7 Family Datasheet 297

Chipset Configuration Registers

(Desktop

Only) Reserved

No Reboot (NR) — R/W. This bit is set wh en the “No Reboot” strap (SPKR pin on

Intel® ICH7) is sampled high on PWROK. This bit may be set or cleared by software if

the strap is sampled low but may not override the strap when it indicates “No

Reboot”.

0 = System will reboot upon the second timeout of the TCO timer.

1 = The TCO timer will count down and generate the SMI# on the fi rst timeout, but

will not reboot on the second timeout.

Alternate Access Mode Enable (AME) — R/W.

0 = Disabled.

1 = Alternate access read only registers can be written, and write only registers can

be read. Before entering a low power state, sev eral regi sters from powered down

parts may need to be saved. In the majority of cases, this is not an issue, as

registers have read and write paths. However, several of the ISA compatible

registers are either read only or write only. To get data out of write-only

registers, and to restore data into read-only registers, the ICH7 implements an

alternate access mode. For a list of these registers see Section 5.14.10.

3 Reserved.

Reserved Page Route (RPR) — R/W. This bit determines where to send the

reserved page registers. These addresses are sent to PCI or LPC for the purpose of

generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h,

86h, 88h, 8Ch, 8Dh, and 8Eh.

0 = Writes will be forwarded to LPC, shadowed within the ICH7, and reads will be

returned from the internal shadow

1 = Writes will be forwarded to PCI, shadowed within the ICH7, and reads will be

returned from the internal shadow.

NOTE: If some writes are completed to LPC/PCI to these I/O ranges, and then this

bit is flipped such that writes will now go to the other interface, the reads will

not return what was last written. Shadowing is performed on each interface.

The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are

always decoded to LPC.

1 Reserved

BIOS Interface Lock-Down (BILD) — R/WLO.

0 = Disabled.

1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10)

from being changed. This bit can only be written from 0 to 1 once.

Bit Description

Chipset Configuration Registers

298 Intel ® ICH7 Family Datasheet

7.1.55 BUC—Backed Up Control Register

Offset Address: 3414–3414h Attribute: R/W

Default Value: 0000000xb (Desktop Only) Size: 8-bit

0000001xb (Mobile/Ultra Mobile Only)

All bits in this register are in the RTC well and only cleared by RTCRST#.

Bit Description

7:3 Reserved

CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by

RSMRST#, but not PLTRST# nor CF9h writes.

0 = Disabled.

1 = The INIT# signals will be driven active when CPURST# is active. INIT# and

INIT3_3V# will go inactive with the same timings as the other processor I/F

signals (hold time after CPURST# inactive).

(Mobile/

Ultra

Mobile

Only)

PATA Reset State (PRS) — R/W.

0 = Disabled.

1 = The reset state of the PATA pins will be driven/tri-state.

(Desktop

Only) Reserved

Top Swap (TS) — R/W.

0 = Intel® ICH7 will not invert A16.

1 = ICH7 will invert A16 for cycles going to the BIOS space (but not the feature

space) in the FWH.

If the ICH7 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then

this bit cannot be cleared by software. The strap jumper should be removed and the

system rebooted.

Intel ® ICH7 Family Datasheet 299

Chipset Configuration Registers

7.1.56 FD—Function Disable Register

Offset Address: 3418–341Bh Attribute: R/W, RO

Default Value: See bit description Size: 32-bit

The UHCI functions must be disabled from highest function number to lowest. For

example, if only three UHCIs are wanted, softw are must disable UHCI #4 (UD4 bit set).

When disabling UHCIs, the EHCI Structural P ar ameters Re gisters must be updated with

coherent information in “Number of Companion Controllers” and “N_Ports” fields.

When disabling a function, only the configuration space is disabled. Software must

ensure that all functionality within a controller that is not desired (such as memory

spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.

When a function is disabled, software must not attempt to re-enable it. A disabled

function can only be re-enabled by a platform reset.

Bit Description

31:22 Reserved

PCI Express 6 Disable (PE6D) — R/W. When disabled, the link for this port is put

into the “link down” state.

0 = PCI Express* port #6 is enabled. (Default)

1 = PCI Express port #6 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

PCI Express 5 Disable (PE5D) — R/W. When disabled, the link for this port is put

into the link down state.

0 = PCI Express port #5 is enabled. (Default)

1 = PCI Express port #5 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

PCI Express 4 Disable (PE4D) — R/W. DWhen disabl ed, the li nk for this port is put

into the “link down” state.

0 = PCI Express* port #4 is enabled. (Default)

1 = PCI Express port #4 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

PCI Express 3 Disable (PE3D) — R/W. When disabled, the link for this port is put

into the link down state.

0 = PCI Express port #3 is enabled. (Default)

1 = PCI Express port #3 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

PCI Express 2 Disable (PE2D) — R/W. When disabled, the link for this port is put

into the link down state.

0 = PCI Express port #2 is enabled. (Default)

1 = PCI Express port #2 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

PCI Express 1 Disable (PE1D) — R/W. When disabled, the link for this port is put

into the link down state.

0 = PCI Express port #1 is enabled. (Default)

1 = PCI Express port #1 is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

Chipset Configuration Registers

300 Intel ® ICH7 Family Datasheet

15 EHCI Disable (EHCID) — R/W.

0 = The EHCI is enabled. (Default)

1 = The EHCI is disabled.

LPC Bridge Disable (LBD) — R/W.

0 = The LPC bridge is enabled. (Default)

1 = The LPC bridge is disabled. Unlike the other disables in this register, the follo wing

additional spaces will no longer be decoded by the LPC bridge:

• Memory cycles below 16 MB (1000000h)

• I/O cycles below 64 KB (10000h)

• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF

Memory cy cles in the LPC BIOS r ange below 4 GB will still be decoded when this bit is

set, but the aliases at the top of 1 MB (the E and F segment) no longer will be

decoded.

13:12 Reserved

11 UHCI #4 Disable (U4D) — R/W.

0 = The 4th UHCI (ports 6 and 7) is enabled. (Default)

1 = The 4th UHCI (ports 6 and 7) is disabled.

10 UHCI #3 Disable (U3D) — R/W.

0 = The 3rd UHCI (ports 4 and 5) is enabled. (Default)

1 = The 3rd UHCI (ports 4 and 5) is disabled.

9UHCI #2 Disable (U2D) — R/W.

0 = The 2nd UHCI (p orts 2 and 3) is enabled. (Default)

1 = The 2nd UHCI (ports 2 and 3) is disabled.

8UHCI #1 Disable (U1D) — R/W.

0 = The 1st UHCI (ports 0 and 1) is enabled. (Default)

1 = The 1st UHCI (ports 0 and 1) is disabled.

Hide Internal LAN (HIL) — R/W.

0 = The LAN controller is enabled. (Default)

1 = The LAN controller is disabled and will not decode configuration cycles off of PCI

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1. .

AC ‘97 Modem Disable (AMD) — R/W.

0 = The AC ‘97 modem function is enabled. (Default)

1 = The AC ‘97 modem function is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

AC ‘97 Audio Disable (AAD) — R/W.

0 = The AC ‘97 audio function is enabled. (Default)

1 = The AC ‘97 audio function is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

Intel® High Definition Audio Disable (ZD) — R/W.

0 = The Intel High Definition Audio controller is enabled. (Default)

1 = The Intel High Definition Audio c o ntroller is disabled and its PCI configuration

space is not accessible.

SM Bus Disable (SD) — R/W.

0 = The SM Bus controller is enabled. (Default)

1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/

O space. In the Intel® ICH7, it only disables the configuration space.

Bit Description

Intel ® ICH7 Family Datasheet 301

Chipset Configuration Registers

7.1.57 CG—Clock Gating (Mobile/Ultra Mobile Only)

Offset Address: 341C–341Fh Attribute: R/W, RO

Default Value: 00000000h Size: 32-bit

Serial ATA Disable (SAD) — R/W. Default is 0.

0 = The SATA controller is enabled.

1 = The SATA controller is disabled.

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 1.

1Parallel ATA Disable (P AD ) — R/W.

0 = The PATA controller is enabled. (Default)

1 = The PATA controller is disabled and i ts PCI configuration space is not accessible.

0 Reserved

Bit Description

31 Legacy (LPC) Dynamic Clock Gate Enable — R/W.

0 = Legacy Dynamic Clock Gating is Disabled

1 = Legacy Dynamic Clock Gating is Enabled

30 PATA Dynamic Clock Gate Enable — R/W.

0 = PATA Dynamic Clock Gating is Disable d

1 = PATA Dynamic Clock Gating is Enabled

29:28

USB UHCI Dynamic Clock Gate Enable — R/W.

0 = USB UHCI Dynamic Clock Gating is Disabled

1 = USB UHCI Dynamic Clock Gating is Enabled

0 = Reserved

1 = Reserved

SATA Port 3 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 3 Dynamic Clock Gating is Disabled

1 = SATA Port 3 Dynamic Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

SATA Port 2 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 2 Dynamic Clock Gating is Disabled

1 = SATA Port 2 Dynamic Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

SATA Port 1 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 1 Dynamic Clock Gating is Disabled

1 = SATA Port 1 Dynamic Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

SATA Port 0 Dynamic Clock Gate Enable — R/W.

0 = SATA Port 0 Dynamic Clock Gating is Disabled

1 = SATA Port 0 Dynamic Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

Chipset Configuration Registers

302 Intel ® ICH7 Family Datasheet

AC ‘97 Static Clock Gate Enable — R/W.

0 = AC ‘97 Static Clock Gating is Disabled

1 = AC ‘9 7 Static Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

27:23 Reserved

22 High Definition Audio Dynamic Clock Gate Enable — R/W.

0 = HIgh Definition Audio Dynamic Clock Gating is Disabled

1 = HIgh Definition Audio Dynamic Clock Gating is Enabled

21 High Definition Audio Static Clock Gate Enable — R/W.

0 = HIgh Definition Audio Static Clock Gating is Disabled

1 = HIgh Definition Audio Static Clock Gating is Enabled

20 USB EHCI Static Clock Gate Enable — R/W.

0 = USB EHCI Static Clock Gating is Disabled

1 = USB EHCI Static Clock Gating is Enabled

19 USB EHCI Dynamic Clock Gate Enable — R/W.

0 = USB EHCI Dynamic Clock Gating is Disabled

1 = USB EHCI Dynamic Clock Gating is Enabled

18:17 Reserved

16 PCI Dynamic Gate En able — R/W. Funcitonality reserved. BIOS must ensure bit is

15:4 Reserved

3DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.

0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled

1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled

PCI Express TX Dynamic Clock Gate Enable — R/W.

0 = PCI Express root port TX Dynamic Clock Gating is Disabled

1 = PCI Express root port TX Dynamic Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

1DMI TX Dynamic Clock Gate Enable — R/W.

0 = DMI TX Dynami c Clock Gating is Disabled

1 = DMI TX Dynamic Clock Gating is Enabled

PCI Express Root Port Static Clock Gate Enable — R/W.

0 = PCI Express root port Static Clock Gating is Disabled

1 = PCI Express root port Static Clock Gating is Enabled

NOTE: For ICH7-U Ultra Mobile, this bit must be set to 0.

Bit Description

Intel ® ICH7 Family Datasheet 303

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8 LAN Controller Registers

(B1:D8:F0) (Desktop and

Mobile Only)

Note: LAN is not supported on ICH7-U Ultra Mobile.

The ICH7 integrated LAN controller appears to reside at PCI Device 8, Function 0 on the

secondary side of the ICH7’s virtual PCI-to-PCI bridge. This is typically Bus 1, but may

be assigned a different number depending upon system configuration. The LAN

controller acts as both a master and a slave on the PCI bus. As a master, the LAN

controller interacts with the system main memory to access data for transmission or

deposit received data. As a slave, some of the LAN controller’s control structures are

accessed by the host processor to read or write information to the on-chip registers.

The processor also provides the LAN controller with the necessary commands and

pointers that allow it to process receive and transmit data.

8.1 PCI Configuration Registers

(LAN Controller—B1:D8:F0)

Note: Address locations that are not shown should be treated as Reserved (See Section 6.2

for details).

Table 8-1. LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 1

of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 0000h RO, R/W

06h–07h PCISTS P CI Status 0290h RO, R/WC

08h RID Revision Identification See regi ster

description. RO

0Ah SCC Sub Class Code 00h RO

0Bh BCC Base Class Code 02 RO

0Ch CLS Cache Line Size 00h R/W

0Dh PMLT P rimary Master Latency Timer 00h R/W

0Eh HEADTYP Header Type 00h RO

10h–13h CSR_MEM_BASE CSR Memory–Mapped Base

Address 00000008h R/W, RO

14h–17h CSR_IO_BASE CSR I/O–Mapped Base Address 00000001h R/W, RO

2Ch–2Dh SVID Subsystem Vendor Identification 0000h RO

2Eh–2Fh SID Subsystem Identification 0000h RO

34h CAP_PTR Capabilities Pointer DCh RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin 01h RO

3Eh MIN_GNT Minimum Grant 08h RO

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

304 Intel ® ICH7 Family Datasheet

8.1.1 VID—Vendor Identification Register

(LAN Controller—B1:D8:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

8.1.2 DID—Device Identification Register

(LAN Controller—B1:D8:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

3Fh MAX_LAT Maximum Latency 38h RO

DCh CAP_ID Capability ID 01h RO

DDh NXT_PTR Next Item Pointer 00h RO

DEh–DFh PM_CAP Power Management Capabilities

FE21h

(Desktop Only)

7E21h

(Mobile Only)

E0h–E1h PMCSR Power Management Control/

Status 0000h R/W, RO,

R/WC

E3 PCIDATA PCI Power Management Data 00h RO

Table 8-1. LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) (Sheet 2

of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.

Bit Description

15:0

Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 integrated LAN

controller.

NOTES:

1. If the EEPR OM is not present (or n ot properly programmed), reads to the Device

ID return the default value referred to in the Intel® I/O Controller Hub 7 (ICH7)

Family Specification Update.

2. If the EEPROM is present (and properly programmed) and if the value of word

23h is not 0000h or FFFFh, t he Device ID is loaded from the EEPR OM, word 23h

after the hardware reset. (See Section 8.1.14 - SID, Subsystem ID of LAN

controller for detail)

Intel ® ICH7 Family Datasheet 305

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.1.3 PCICMD—PCI Command Register

(LAN Controller—B1:D8:F0)

Offset Address: 04h–05h Attribute: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

10 Interrupt Disable — R/W.

0 = Enable.

1 = Disables LAN controller to assert its INTA signal.

9Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller

will not run fast back-to-back PCI cycles.

8SERR# Enable (SERR_EN) — R/W.

0 = Disable.

1 = Enable. Allow SERR# to be asserted.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.

Parity Error Response (PER) — R/W.

0 = The LAN controller will ignore PCI parity errors.

1 = The integrated LAN controller will take normal action when a PCI parity error is

detected and will enable generation of parity on DMI.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.

4Memory Write and Invalidate Enable (MWIE) — R/W.

0 = Disable. The LAN controller will not use the Memory Write and Invalidate command.

1 = Enable.

3Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special

cycles.

Bus Master Enable (BME) — R/W.

0 = Disable.

1 = Enable. The Intel® ICH7’s integrated LAN controller may function as a PCI bus

master.

Memory Space Enable (MSE) — R/W.

0 = Disable.

1 = Enable. The ICH7 ’s integrated LAN controller will respond to the memory space

accesses.

I/O Space Enable (IOSE) — R/W.

0 = Disable.

1 = Enable. The ICH7’s integrated LAN controller will respond to the I/O space

accesses.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

306 Intel ® ICH7 Family Datasheet

8.1.4 PCISTS—PCI Status Register

(LAN Controller—B1:D8:F0)

Offset Address: 06h–07h Attribute: RO, R/WC

Default Value: 0290h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = Parity error Not detected.

1 = The Intel® ICH7’s integrated LAN controller has detected a parity error on the PCI

bus (will be set even if Parity Error Response is disabled in the PCI Command

Signaled System Error (SSE) — R/WC.

0 = Integrated LAN controller has not asserted SERR#

1 = The ICH7’ s integrated L AN controller has assert ed SERR#. SERR# can be routed t o

cause NMI, SMI#, or interrupt.

Master Abort Status (RMA) — R/WC.

0 = Master Abort not generated

1 = The ICH7’s integrated LAN controller (as a PCI master) has generated a master

abort.

12 Received Target Abort (RTA) — R/WC.

0 = Target abort not received.

1 = The ICH7’s integr ated LAN controller (as a PCI master) has received a target abort.

11 Signaled Target Abort (STA) — RO. Hardwired to 0. The device will not signal Target

Abort.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01h = Medium timing.

Data Parity Error Detected (DPED) — R/WC.

0 = Parity error not detected (conditions below are not met).

1 = All of the following three conditions have been met:

1. The LAN controller is acting as bus master

2. The LAN controller has asserted PERR# (for reads) or detected PERR# asserted

(for writes)

3. The Parity Error Response bit in the LAN controller’s PCI Command Register is

set.

7Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast

back-to-back transactions.

6 User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.

566 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66

MHz PCI.

Capabilities List (CAP_LIST) — RO.

0 = The EEPROM indicates that the integrated LAN controller does not support PCI

Power Management.

1 = The EEPROM indicates that the integrated LAN controller supports PCI Power

Management.

3Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is

independent from the state of the Interrupt Enable bit in the command register.

2:0 Reserved

Intel ® ICH7 Family Datasheet 307

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.1.5 RID—Revision Identification Register

(LAN Controller—B1:D8:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

8.1.6 SCC—Sub Class Code Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Ah Attribute: RO

Default Value: 00h Size: 8 bits

8.1.7 BCC—Base-Class Code Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Bh Attribute: RO

Default Value: 02h Size: 8 bits

Bit Description

7:0

Revision ID (RID) — RO. This field is an 8-bit value that indicates the revision number

for the integr ated LAN con troll er. The three leas t significant bits in this register may be

overridden by the ID and REV ID fields in the EEPR OM. Refer to the Intel® I/O

Controller Hub 7 (ICH7) Family Specification Update for the value of the Revision ID

Bit Description

7:0 Sub Class Code (SCC) — RO. This 8-bit value specifies th e sub-class of the device as an

Ethernet controller.

Bit Description

7:0 Base Class Code (BCC) — RO. This 8-bit value specifies the base class of the device as

a network controller.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

308 Intel ® ICH7 Family Datasheet

8.1.8 CLS—Cache Line Size Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

8.1.9 PMLT—Primary Master Latency Timer Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Dh Attribute: R/W

Default Value: 00h Size: 8 bits

8.1.10 HEADTYP—Header Type Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:5 Reserved

4:3

Cache Line Size (CLS) — R/W.

00 = Memory Write and Invalidate (MWI) command will not be used by the integrated

LAN controller.

01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a

value of 08h is written to this register).

10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a

value of 10h is written to this register).

11 = Invalid. MWI command will not be used.

2:0 Reserved

Bit Description

7:3 Master Latency Timer Count (MLTC) — R/W. This field defines the number of PCI

clock cycles that the integrated LAN controller may own the bus while acting as bus

master.

2:0 Reserved

Bit Description

7 Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function device.

6:0 Header Type (HTYPE) — RO. This 7-bit field identifi es the header layout of the

configuration space as an Ethernet controller.

Intel ® ICH7 Family Datasheet 309

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base

Address Register (LAN Controller—B1:D8:F0)

Offset Address: 10h–13h Attribute: R/W, RO

Default Value: 00000008h Size: 32 bits

Note: The ICH7’s integrated LAN controller requires one BAR for memory mapping. Software

determines which BAR (memory or I/O) is used to access the LAN controller’s CSR

registers.

8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register

(LAN Controller—B1:D8:F0)

Offset Address: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Note: The ICH7’s integrated LAN controller requires one BAR for memory mapping. Software

determines which BAR (memory or I/O) is used to access the LAN controller’s CSR

registers.

8.1.13 SVID — Subsystem Vendor Identification

(LAN Controller—B1:D8:F0)

Offset Address: 2Ch–2D Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31:12 Base Address (MEM_ADDR) — R/W. This field contains the upper 20 bits of the base

address provides 4 KB of memory-Mapped space for the LAN control ler’s Control/Status

registers.

11:4 Reserved

3Prefetchable (MEM_PF) — RO. Hardwired to 0 to indicate that this is not a pre-fetchable

memory-Mapped address range.

2:1 Type (MEM_TYPE) — RO. Hardwired to 00b to indicate the memory-Mapped address

range may be located anywhere in 32-bit address space.

0Memory-Space Indicator (MEM_SP ACE) — RO . Hardwired to 0 to indicate that this base

address maps to memory space.

Bit Description

31:16 Reserved

15:6 Base Address (IO_ADDR)— R/W. This field provides 64 bytes of I/O-Mapped address

space for the LAN controller’s Control/Status registers.

5:1 Reserved

0I/O Space Indicator (IO_SPACE) — RO. Hardwired to 1 to indicate that this base

address maps to

I/O space.

Bit Description

15:0 Subsystem Vendor ID (SVID) — RO. See Section 8.1.14 for details.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

310 Intel ® ICH7 Family Datasheet

8.1.14 SID — Subsystem Identification

(LAN Controller—B1:D8:F0)

Offset Address: 2Eh–2Fh Attribute: RO

Default Value: 0000h Size: 16 bits

Note: The ICH7’s integrated LAN controller provides support for configurable Subsystem ID

and Subsystem V endor ID fields. After reset, the LAN controller automatically reads

addresses Ah through Ch, and 23h of the EEPROM. The LAN controller checks bits

15:13 in the EEPROM word Ah, and functions according to Table 8-2.

NOTES:

1. The Device ID is loaded from Word 23h only if the value of Word 23h is not 0000h or FFFFh

2. The Revision ID is subject to change according to the silicon stepping.

8.1.15 CAP_PTR — Capabilities Pointer

(LAN Controller—B1:D8:F0)

Offset Address: 34h Attribute: RO

Default Value: DCh Size: 8 bits

8.1.16 INT_LN — Interrupt Line Register

(LAN Controller—B1:D8:F0)

Offset Address: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

15:0 Subsystem ID (SID) — RO.

Table 8-2. Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM

Bits 15:14 Bit

13 Device

ID1Vendor ID Revision ID2Subsystem ID Subsystem

Vendor ID

11b, 10b,

00b X 1051h 8086h 00h 0000h 0000h

01b 0b Word 23h 8086h 00h Word Bh Word Ch

01b 1b Word 23h Word Ch 80h + Word

Ah,

bits 10:8 Word Bh Word Ch

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh to indicate the offset within

configuration space for the location of the Power Management registers.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This field identifies the system interrupt line to

which the LAN controller’s PCI interrupt request pin (as defined in the Interrupt Pin

Intel ® ICH7 Family Datasheet 311

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.1.17 INT_PN — Interrupt Pin Register

(LAN Controller—B1:D8:F0)

Offset Address: 3Dh Attribute: RO

Default Value: 01h Size: 8 bits

8.1.18 MIN_GNT — Minimum Grant Register

(LAN Controller—B1:D8:F0)

Offset Address: 3Eh Attribute: RO

Default Value: 08h Size: 8 bits

8.1.19 MAX_LAT — Maximum Latency Register

(LAN Controller—B1:D8:F0)

Offset Address: 3Fh Attribute: RO

Default Value: 38h Size: 8 bits

8.1.20 CAP_ID — Capability Identification Register

(LAN Controller—B1:D8:F0)

Offset Address: DCh Attribute: RO

Default Value: 01h Size: 8 bits

Bit Description

7:0

Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s

interrupt request is connected to PIRQA#. However, in the Intel® ICH 7 implementation,

when the LAN controller interrupt is generated PIRQE# will go active, not PIRQA#. Note

that if the PIRQE# signal is used as a GPI, the external visibility will be lost (though

PIRQE# will still go active internally).

Bit Description

7:0 Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in

increments of 0.25 μs) that the LAN controller needs to retain ownership of the PCI bus

when it initiates a transaction.

Bit Description

7:0 Maximum Latency (MAX_ LAT) — RO. This field defines how often (in increments of

0.25 μs) the LAN control ler needs to access the PCI bus.

Bit Description

7:0 Capability ID (CAP_ID) — RO. Hardwired to 01h to indicate that the Intel® ICH7’s

integrated LAN controller supports PCI power management.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

312 Intel ® ICH7 Family Datasheet

8.1.21 NXT_PTR — Next Item Pointer

(LAN Controller—B1:D8:F0)

Offset Address: DDh Attribute: RO

Default Value: 00h Size: 8 bits

8.1.22 PM_CAP — Power Management Capabilities

(LAN Controller—B1:D8:F0)

Offset Address: DEh–DFh Attribute: RO

Default Value: FE21h (Desktop Only) Size: 16 bits

7E21h (Mobile Only)

Bit Description

7:0 Next Item Pointer (NXT_PTR) — RO. Hardwired to 00b to indicate that power

management is the last item in the capabilities list.

Bit Description

15:11 PME Support (PME_SUP) — RO. Hardwired to 11111b. This 5-bit field indicates the

power states in which the LAN controller may assert PME#. The LAN controller

supports wake-up in all power states.

10 D2 Support (D2_SUP) — RO. Hardwired to 1 to indicate that the LAN controller

supports the D2 power state.

9D1 Support (D1_SUP) — RO. Hardwired to 1 to indicate that the LAN controller

supports the D1 power state.

8:6 Auxiliary Current (AUX_CUR) — RO. Hardwired to 000b to indicate that the LAN

controller implements the Data regi sters. The auxiliary power consumptio n is the same

as the current consumption reported in the D3 state in the Data register.

Device Specific Initialization (DSI) — RO. Hardwired to 1 to indicate that special

initialization of this function is required (bey ond the standard PCI con figurati on header)

before the generic class device driver is able to use it. DSI is required for the LAN

controller after D3-to-D0 reset.

4 Reserved

3PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that the LAN controller does

not require a clock to generate a power management event.

2:0 Version (VER) — RO. Hardwired to 010b to indicate that the LAN controller complies

with of the PCI Power Manageme nt Specification, Revision 1.1.

Intel ® ICH7 Family Datasheet 313

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.1.23 PMCSR — Power Management Control/

Status Regi ste r (LAN Controller—B1:D8:F0)

Offset Address: E0h–E1h Attribute: RO, R/W, R/WC

Default Value: 0000h Size: 16 bits

Bit Description

PME Status (PME_STAT) — R/WC.

0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and

clears the PME status bit in the Power Management Driver Register. When the

PME# signal is enabled, the PME# signal reflects the state of the PME status bit.

1 = Set upon occurrence of a wake-up event, independent of the state of the PME

enable bit.

14:13 Data Scale (DSCALE) — RO. This field in dicates the data register scaling factor. It

equals 10b for registers 0 through 8 and 00b for registers nine through fifteen, as

selected by the “Data Select” field.

12:9 Data Select (DSEL) — R/ W. T his field is used to select which data is reported through

the Data register and Data Scale field.

PME Enable (PME_EN) — R/W. This bit enables the Intel® ICH7’s integrated LAN

controller to assert PME#.

0 = The d e vice will not assert PME#.

1 = Enable PME# assertion when PME Status is set.

7:5 Reserved

4Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does not

support the ability to monitor the power consumption dynamically.

3:2 Reserved

1:0

Power State (PWR_ S T) — R/W. This 2-bit field is used to determine the current

power state of the integrated LAN controller, and to put it into a new power state. The

definition of the field values is as follows:

00 = D0

01 = D1

10 = D2

11 = D3

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

314 Intel ® ICH7 Family Datasheet

8.1.24 PCIDATA — PCI Power Management Data Register

(LAN Controller—B1:D8:F0)

Offset Address: E3h Attribute: RO

Default Value: 00h Size: 8 bits

The data register is an 8-bit read only register that provides a mechanism for the

ICH7’s integrated LAN controller to report state dependent maximum power

consumption and heat dissipation. The value reported in this register depends on the

value written to the Data Select field in the PMCSR register. The power measurements

defined in this register have a dynamic range of 0 W to 2.55 W with 0.01 W resolution,

scaled according to the Data Scale field in the PMCSR. The structure of the Data

Bit Description

7:0 Power Management Data (PWR_MGT) — RO. State dependent power consumption and

heat dissipation data.

Table 8-3. Data Register Structure

Data Select Data Scale Data Reported

0 2 D0 Power Consumption

1 2 D1 Power Consumption

2 2 D2 Power Consumption

3 2 D3 Power Consumption

4 2 D0 Power Dissipated

5 2 D1 Power Dissipated

6 2 D2 Power Dissipated

7 2 D3 Power Dissipated

Common Function Power

Dissipated

9–15 0 Reserved

Intel ® ICH7 Family Datasheet 315

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2 LAN Control / Status Registers (CSR)

(LAN Controller—B1:D8:F0)

Table 8-4. Intel® ICH7 Integrated LAN Controller CSR Space Register Address Map

Offset Mnemonic Register Name Default Type

00h–01h SCB_STA System Control Block Status Word 0000h R/WC, RO

02h–03h SCB_CMD System Control Block Command

Word 0000h R/W, WO

04h–07h SCB_GENPNT System Control Block General

Pointer 0000 0000h R/W

08h–0Bh Port PORT Interface 0000 0000h R/W (special)

0Ch–

0Dh — Reserved — —

0Eh EEPROM_CNTL EEPROM Control 00 R/W, RO, WO

0Fh — Reserved — —

10h–13h MDI_CNTL Management Data Interface

Control 0000 0000h R/W (special)

14h–17h REC_DMA_BC Receive DMA Byte Count 0000 0000h RO

18h EREC_INTR Early Receive Interrupt 00h R/W

19–1Ah FLOW_CNTL F low Control 0000h RO, R/W

(special)

1Bh PMDR Power Management Driver 00h R/WC

1Ch GENCNTL General Control 00h R/W

1Dh GENSTA Gene ral Status 00h RO

1Eh — Reserved — —

1Fh SMB_PCI SMB via PCI 27h R/W

20h–3Ch — Reserved — —

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

316 Intel ® ICH7 Family Datasheet

8.2.1 SCB_STA—System Control Block Status Word Register

(LAN Controller—B1:D8:F0)

Offset Address: 00h–01h Attribute: R/WC, RO

Default Value: 0000h Size: 16 bits

The ICH7’s integrated LAN controller places the status of its Command Unit (CU) and

Receive Unit (RC) and interrupt indications in this register for the processor to read.

Bit Description

Command Unit (CU) Executed (CX) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Interrupt signaled because the CU has completed executing a command with its

interrupt bit set.

Frame Received (FR) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.

CU Not Active (CNA) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = The Command U nit left the Active state or entered the Idle state. Th ere are 2

distinct s tates of t he CU . When con figured to gener a te CNA interrupt, the interru pt

will be activated when the CU leaves the Active state and enters either the Idle or

the Suspended st ate. When configu red to generate CI in terrupt, an interrupt will be

generated only when the CU enters the Idle state.

Receive Not Ready (RNR) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Interrupt signaled because the Receive Unit left the Ready state. This may be

caused by an RU Abort com mand, a no resources situation, or set suspend bit due

to a filled Receive Frame Descriptor.

Management Data Interrupt (MDI) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Set when a Management Data Interface read or write cycle has completed. The

management data interrupt is enabled through the interrupt enable bit (bit 29 in

the Management Data Interface Control register in the CSR).

Software Interrupt (SWI) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Set when software generates an interrupt.

Early Receive (ER) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Indicates the occurrence of an Early Receive Interrupt.

Flow Control Pause (FCP) — R/WC.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit

position.

1 = Indica tes Flow Co ntrol Pause interrupt.

Intel ® ICH7 Family Datasheet 317

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.2 SCB_CMD—System Co ntrol Block Command Word

Offset Address: 02h–03h Attribute: R/W, WO

Default Value: 0000h Size: 16 bits

The processor places commands for the Command and Receive units in this register.

Interrupts are also acknowledged in this register.

7:6

Command Unit Status (CUS) — RO.

00 = Idle

01 = Suspended

10 = LPQ (Low Priority Queue) active

11 = HPQ (High Priority Queue) active

5:2

Receive Unit Status (RUS) — RO.

1:0 Reserved

Bit Description

Value Status Value Status

0000b Idle 1000b Reserved

0001b Suspended 1001b Suspended with no more RBDs

0010b No Resources 1010b No resources due to no more

RBDs

0011b Reserved 1011b Reserved

0100b Ready 1100b Ready with no RBDs present

0101b Reserved 1101b Reserved

0110b Reserved 1110b Reserved

0111b Reserved 1111b Reserved

Bit Description

15 CX Mask (CX_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of a CX interrupt.

14 FR Mask (FR_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of an FR interrupt.

13 CNA Mask (CNA_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of a CNA interrupt.

12 RNR Mask (RNR_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of an RNR interrupt.

11 ER Mask (ER_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of an ER interrupt.

10 FCP Mask (FCP_MSK) — R/W.

0 = Interrupt not masked.

1 = Disable the generation of an FCP interrupt.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

318 Intel ® ICH7 Family Datasheet

9Software Generated Interrupt (SI) — WO.

0 = No Effect.

1 = Setting this bit causes the LAN co ntroller to generate an interrupt.

Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s

assertion of the INT A# signal. This bit has higher precedence that the Specific Interrupt

Mask bits and the SI bit.

0 = Enable the assertion of INTA#.

1 = Disable the assertion of INTA#.

7:4

Command Unit Command (CUC) — R/W. Valid values are listed below. All other

values are Reserved.

0000 = NOP: Does not affect the current state of the unit.

0001 = CU Start: Start execution of the first command on the CBL. A pointer to the

first CB of the CBL should be placed in the SCB General Pointer before issuing

this command. The CU Start comman d should only be iss ued when th e CU is in

the Idle or Suspended states (not when the CU is in the active state), and all of

the previously issued Command Blocks have been processed and completed by

the CU. Sometimes it is only poss ible to determine that all Command Blocks are

completed by checking that the Complete bit is set in all previously issued

Command Blocks.

0010 = CU Resume: Resume operation of the Command unit by executing the next

command. This command will be ignored if the CU is idle.

0011 = CU HPQ Start: Start execution of the first command on the high priority CBL.

A pointer to the first CB of the HPQ CBL should be placed in the SCB General

POinter before issuing this command.

0100 = Load Dump Counters Address: Indicates to the device where to write dump

data when using the Dump Statistical Counters or Dump and Reset Statistical

Counters commands. This command must be executed at least once before any

usage of the Dump Statistical Counters or Dump and R eset Statisti cal Counters

commands. The address of the dump area must be placed in the General

Pointer register.

0101 = Dump Statistical Counters: Tells the device to dump its statistical counters

to the area designated by the Load Dump Counters Address command.

0110 = Load CU Base: The device’s i nternal CU Base R egister is loaded with the valu e

in the CSB General Pointer.

0111 = Dump and Reset Statistical Counters: Indicates to the device to dump its

statisti cal counters to the area de signated by the Load Dum p Counters Address

command, and then to clear these counters.

1010 = CU Static Resume: Resume operation of the Command unit by executing the

next command. This command will be ignored if the CU is idle. This command

should be used only when the CU is in the Suspended state and has no pending

CU Resume commands.

1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL.

this command will be ignored if the HPQ was not started.

3Reserved

Bit Description

Intel ® ICH7 Family Datasheet 319

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.3 SCB_GENPNT—System Control Block General Pointer

Offset Address: 04h–07h Attribute: R/W

Default Value: 0000 0000h Size: 32 bits

8.2.4 PORT—PORT Interface Register

(LAN Controller—B1:D8:F0)

Offset Address: 08h–0Bh Attribute: R/W (special)

Default Value: 0000 0000h Size: 32 bits

The PORT interface allows the processor to reset the ICH7’s internal LAN controller, or

perform an internal self test. The PORT DWord may be written as a 32-bit entity, two

16-bit entities, or four

8-bit entities. The LAN controller will only accept the command after the high byte

(offset 0Bh) is written; therefore, the high byte must be written last.

2:0

Receive Unit Command (RUC) — R/W. Valid values are:

000 = NOP: Does not affect the current state of the unit.

001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in

the SCB General POinter before using this command. The device pre-fetches

the first RFD and the first RBD (if in flexible mode) in preparation to receive

incoming frames that pass its address filtering.

010 = RU Resume: Resume frame reception (only when in suspended state).

011 = RCV DMA Redirect: Resume the RCV DMA when configured to “Direct DMA

Mode.” The buffers are indicated by an RBD chain which is pointed to by an

offset stored in the General Pointer Register (this offset will be added to the RU

Base).

100 = RU Abort: Abort RU receive operation immediately.

101 = Load Header Data Size (HDS): This value defines the size of the Header

portion of the RFDs or Receive buffers. The HDS value is defined by the lower

14 bits of the SCB General Pointer, so bits 31:15 should always be set to 0’s

when using this command. Once a Load HDS command i s issued, the device

expects only to find Header RFDs, or be used in “RCV Direct DMA mode” until it

is reset. Note that the value of HDS should be an even, non-zero number.

110 = Load RU Base: The device’ s i nternal RU Ba se Register is l oaded with th e value

in the SCB General Pointer.

111 = RBD Resume: Resume frame reception into the RFA. This command should

only be used when the RU is already in the “No Resources due to no RBDs”

state or the “Suspended with no more RBDs” state.

Bit Description

15:0 SCB General Pointer — R/W. The SCB General Pointer register is programmed by

software to point to various data structures in main memory depending on the current

SCB Command word.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

320 Intel ® ICH7 Family Datasheet

Bit Description

31:4 Pointer Field (PORT_PTR) — R/W (special). A 16-byte aligned address must be

written to this fie ld when issuing a Self -Test command to the POR T interface.The r esults

of the Self Test will be written to the address specified by this field.

3:0

PORT Function Selection (PORT_FUNC) — R/W (special). Valid values are listed

below. All other values are reserved.

0000 = PORT Software Reset: Completely resets the LAN controller (all CSR and PCI

registers). This command should not be used when the device is active. If a

PORT Software Reset is desired, software should do a Selective Reset

(described below), wait for the PORT register to be cleared (completion of the

Selective Reset), and then issue the PORT Software Reset command. Software

should wait approximately 10 μs after issuing this command before attempting

to access the LAN controller’s registers again.

0001 = Self Test: The Self-Test begins by issuing an internal S elective Reset followed

by a general internal self-test of the LAN controller. The results of the self-test

are written to memory at the address specified in the Pointer field of this

completing the self-test and writing the results to memory, the LAN controller

will execute a full internal reset and will re-initialize to the default configuration.

Self-Test does not generate an interrupt of similar indicator to the host

processor upon completion.

0010 = Selective Reset: Sets the CU and RU to th e Idle state, but otherwise

maintains the current configuration parameters (RU and CU Base, HDSSize,

Error Counters, Configure information and Individual/Multicast Addresses are

preserved). Software should wait approximately 10 μs after issuing this

command before attempting to access the LAN controller’s registers again.

Table 8-5. Self-Test Results Format

Bit Description

31:13 Reserved

12 General Self-Test Result (SELF_TST) — R/W (special).

0 = Pass

1 = Fail

11:6 Reserved

Diagnose Result (DIAG_RSLT) — R/W (special). This bit provides the result of an

internal diagnostic test of the Serial Subsystem.

0 = Pass

1 = Fail

4 Reserved

the internal Parallel Subsystem registers.

0 = Pass

1 = Fail

ROM Content Result (ROM_RSLT) — R/W (special). This bit pr ovides the resu lt of a

test of the internal microcode ROM.

0 = Pass

1 = Fail

1:0 Reserved

Intel ® ICH7 Family Datasheet 321

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.5 EEPROM_CNTL—EEPROM Control Register

(LAN Controller—B1:D8:F0)

Offset Address: 0Eh Attribute: RO, R/W, WO

Default Value: 00h Size: 8 bits

The EEPROM Control Register is a 16-bit field that enables a read from and a write to

the external EEPROM .

Bit Description

7:4 Reserved

3EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out”

from the perspective of the EEPROM device. This bit contains the value read from the

EEPROM when performing read operations.

2EEPROM Serial Data In (EEDI) — WO. Note that this bit represents “Data In” from

the perspective of the EEPROM device. The value of this bit is written to the EEPROM

when performing write operations.

EEPROM Chip Select (EECS) — R/W.

0 = Drives the Intel® ICH7’s EE_CS signal low to disable the EEPROM. this bit must be

set to 0 for a minimum of 1 μs between consecutive instruction cycles.

1 = Drives the ICH7’s EE_CS signal high, to enable the EEPROM.

EEPROM Serial Clock (EESK) — R/W. Toggling this bit clocks data into or out of the

EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM

component’s minimum clock frequency specification.

0 = Drives the ICH7’s EE_SHCLK signal low.

1 = Drives the ICH7’s EE_SHCLK signal high.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

322 Intel ® ICH7 Family Datasheet

8.2.6 MDI_CNTL—Management Dat a Interface (MDI) Control

Offset Address: 10h–13h Attribute: R/W (special)

Default Value: 0000 0000h Size: 32 bits

The Management Data Interface (MDI) Control register is a 32-bit field and is used to

read and write bits from the LAN Conn ect component. This register may be written as a

32-bit entity, two 16-bit entities, or four 8-bit entities. The LAN controller will only

accept the command after the high byte (offset 13h) is written; therefore, the high

byte must be written last.

8.2.7 REC_DMA_BC—Receive DMA Byte Count Register

(LAN Controller—B1:D8:F0)

Offset Address: 14h–17h Attribute: RO

Default Value: 0000 0000h Size: 32 bits

Bit Description

31:30 These bits are reserved and should be set to 00b.

Interrupt Enable — R/W (special).

0 = Disable.

1 = Enables the LAN controller to assert an interrupt to indicate the end of an MDI

cycle.

28 Ready — R/W (special).

0 = Expected to be reset by software at the same time the command is written.

1 = Set by the LAN controller at the end of an MDI transaction.

27:26

Opcode — R/W (special). These bits de fine the opcode:

00 = Reserved

01 = MDI write

10 = MDI read

11 = Reserved

25:21 LAN Connect Address — R/W (special). This field of bits contains the LAN Connect

address.

20:16 LAN Connect Register Address — R/W (s pecial). This field contains the LAN Connect

15:0

Data — R/W (special). In a write command, software places the data bits in this field,

and the LAN controller transfers the data to the external LAN Connect component.

During a read command, the LAN controller reads these bits serially from the LAN

Connect, and software reads the data from this location.

Bit Description

31:0 Receive DMA Byte Count — RO. This field keeps track of how many bytes of receive

data have been passed into host memory via DMA.

Intel ® ICH7 Family Datasheet 323

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.8 EREC_INTR—Early Receive Interrupt Register

(LAN Controller—B1:D8:F0)

Offset Address: 18h Attribute: R/W

Default Value: 00h Size: 8 bits

The Early Receive Interrupt register allows the internal LAN controller to generate an

early interrupt depending on the length of the frame. The LAN controller will generate

an interrupt at the end of the frame regardless of whether or not Early Receive

Interrupts are enabled.

Note: It is recommended that software not use this register unless receive interrupt latency

is a critical performance issue in that particular software environment. Using this

feature may reduce receive interrupt latency, but will also result in the generation of

more interrupts, which can degrade system efficiency and performance in some

environments.

8.2.9 FLOW_CNTL—Flow Co ntro l Register

(LAN Controller—B1:D8:F0)

Offset Address: 19h–1Ah Attribute: RO, R/W (special)

Default Value: 0000h Size: 16 bits

Bit Description

7:0

Early Receive Count — R/W. When some non-zero value x is programmed into this

INTA# when the byte count indicates that there are x qwords remaining to be received

in the current frame (based on the Type/Length field of the received frame). No Early

Receive interrupt will be generated if a value of 00h (the default value) is programmed

into this r egister.

Bit Description

15:13 Reserved

FC Paused Low — RO.

0 = Cleared when the FC timer reaches 0, or a Pause frame is received.

1 = Set when the LAN controller receives a Pause Low command with a value greater

than 0.

FC Paused — RO.

0 = Cleared when the FC timer reaches 0.

1 = Set when the LAN controller receives a Pause command regardless of its cause

(FIFO reaching Flow Control Threshold, fetching a Receiv e Frame Descriptor with its

Flow Control Pause bit set, or software writing a 1 to the Xoff bit).

10 FC Full — RO.

0 = Cleared when the FC timer reaches 0.

1 = Set when the LAN controller sends a Pause command with a value greater than 0.

Xoff — R/ W (special). This bit shou ld only be us ed if the L AN cont roller is c onfigured t o

operate with IEEE frame-based flow control.

0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register).

1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to

behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff

request due to an “RFD Xoff” bit.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

324 Intel ® ICH7 Family Datasheet

8.2.10 PMDR—Power Management Driver Register

(LAN Controller—B1:D8:F0)

Offset Address: 1Bh Attribute: R/WC

Default Value: 00h Size: 8 bits

The ICH7’s internal LAN controller provides an indication in the PMDR that a wake-up

event has occurred.

Xon — WO. This bit should only be used if the LAN controller is configured to operate

with IEEE frame-based flow control.

0 = This bit always returns 0 on reads.

1 = Writing a 1 to this bit resets the Xoff request to the LAN controller, clearing bit 9 in

this register.

7:3 Reserved

2:0

Flow Control Threshold — R/W. The LAN controller can generate a Flow Control Pause

frame when its Receive FIFO is almost full. The value programmed into this field

determines the number of bytes still available in the Receive FIFO when the Pause

frame is generated.

Bit Description

Bits 2:0 Free Bytes in RX

FIFO Comment

000b 0.50 KB Fast system (recomme nded

default)

001b 1.00 KB

010b 1.25 KB

011b 1.50 KB

100b 1.75 KB

101b 2.00 KB

110b 2.25 KB

111b 2.50 KB Slow system

Bit Description

7Link Status Change Indication — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The link status change bit is set following a change in link status.

Magic Packet — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-

up disable bit in the configuration command and the PME Enable bit in the Power

Management Control/ Status Register.

Interesting Packet — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is se t when an “interesting” packet is received. Interesting packets are

defined by the LAN controller packet filters.

4:3 Reserved

Intel ® ICH7 Family Datasheet 325

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.11 GENCNTL—General Control Register

(LAN Controller—B1:D8:F0)

Offset Address: 1Ch Attribute: R/W

Default Value: 00h Size: 8 bits

2ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.

1TCO Request — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set to 1b when the LAN controller is busy with TCO activity.

PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power

Management Control/Status Register (PMCSR).

0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the

PMCSR and deasserts the PME signal.

1 = Set upon a wake-up event, independen t of the PME Enable bit.

Bit Description

7:4 Reserved. These bits should be set to 0000b.

LAN Connect Software Reset — R/W.

0 = Cleared by software to begin normal LAN Connect operating mode. Software must

not attempt to access the LAN Connect interface for at least 1ms after clearing this

bit.

1 = Software can set this bit to force a reset condition on the LAN Connect interface.

2 Reserved. This bit should be set to 0.

Deep Power-Down on Link Down Enable — R/W.

0 = Disable

1 = Enable. The Intel® ICH7’s internal LAN controller may enter a deep power-down

state (sub-3 mA) in the D2 and D3 power states while the link is down. In this

state, the LAN controller does not keep link integrity. This state is not supported for

point-to-point connection of two end stations.

0 Reserved

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

326 Intel ® ICH7 Family Datasheet

8.2.12 GENSTA—General Status Register

(LAN Controller—B1:D8:F0)

Offset Address: 1Dh Attribute: RO

Default Value: 00h Size: 8 bits

8.2.13 SMB_PCI—SMB via PCI Register

(LAN Controller—B1:D8:F0)

Offset Address: 1Fh Attribute: R/W, RO

Default Value: 27h Size: 8 bits

Software asserts SREQ when it wants to isolate the PCI-accessible SMBus to the ASF

registers/commands. It waits for SGNT to be asserted. At this point SCLI, SDAO, SCL O,

and SDAI can be toggled/read to force ASF controller SMBus transactions without

affecting the external SMBus. After all oper ations are completed, the bus is returned to

idle (SCLO=1b,SDAO=1b, SCLI=1b, SDAI=1b), SREQ is released (written 0b). Then

SGNT goes low to indicate released control of the bus. The logic in the ASF controller

only asserts or deasserts SGNT at times when it determines that it is safe to switch (all

SMBuses that are switched in/out are idle).

When in isolation mode (SGNT=1), software can access the ICH7 SMBus slaves that

allow configuration without affecting the external SMBus. This includes configuration

to the external TCO controller. When SGNT=0, the bit-banging and reads are reflected

on the main SMBus and the PCISML_SDA0, PCISML_SCL0 read only bits.

Bit Description

7:3 Reserved

2Duplex Mode — RO. This bit indicates the wire duplex mode.

0 = Half duplex

1 = Full duplex

1Speed — RO. This bit indicates the wire speed.

0 = 10 Mb/s

1 = 100 Mb/s

0Link Status Indication — RO. This bit indicates the status of the link.

0 = Invalid

1 = Valid

Bit Description

7:6 Reserved

5PCISML_SCLO — RO. SMBus Clock from the ASF controller.

4PCISML_SGNT — RO. SMBus Isolation Grant from the ASF controller.

3PCISML_SREQ — R/W. SMBus Isolation Request to the ASF con tro ller.

2PCISML_SDAO — RO. SMBus Data from the ASF controller.

1PCISML_SDAI — R/W. SMBus Data to the ASF controller.

0PCISML_SCLI — R/W. SMBus Clock to the ASF controller.

Intel ® ICH7 Family Datasheet 327

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.2.14 Statistical Counters (LAN Controller—B1:D8:F0)

The ICH7’s integrated LAN controller provides information for network management

statistics by providing on-chip statistical counters that count a variety of events

associated with both transmit and receive. The counters are updated by the LAN

controller when it completes the processing of a frame (that is, when it has completed

transmitting a frame on the link or when it has completed receiving a frame). The

Statistical Counters are reported to the software on demand by issuing the Dump

Statistical Counters command or Dump and R eset Statistical Counters command in the

SCB Command Unit Command (CUC) field.

Table 8-6. Statistical Counte rs (Sheet 1 of 2 )

ID Counter Description

0Transmit Good

Frames

This counter contains the number of frames that were

transmitted properly on the link. It is updated only after the

actual tr ansmission on the li nk is completed, not when th e frame

was read from memory as is done for the Transmit Command

Block status.

4Transmit Maximum

Collisions (MAXCOL)

Errors

This counter contains the number of frames that were not

transmitted because they encountered the configured maximum

number of collisions.

8Transmit Late

Collisions

(LATECOL) Errors

This counter contains the number of frames that were not

transmitted since they e ncountered a collis ion later than the

configured slot time.

12 Transmit Underrun

Errors

A transmit underrun occurs because the system bus cannot keep

up with the transmission. This counter contains the numb er of

frames that were either not transmitted or retr ansmitted due to a

transmit DMA underrun. If the LAN controller is configured to

retransmit on underrun, this counter may be updated multiple

times for a single frame.

16 Transmit Lost

Carrier Sense (CRS)

This counter contains the number of frames that were

transmitte d by the LAN controller despite the fact that it dete cted

the de-assertion of CRS during the transmission.

20 Transmit Deferred This counter contains the number of frames that were deferred

before transmission due to activity on the link.

24 Transmit Single

Collisions This counter contains the number of transmitted frames that

encountered one c ollision.

28 Transmit Multiple

Collisions This counter contains the number of transmitted frames that

encountered more than one collision.

32 Transmit Total

Collisions

This counter contains the total number of collisions that were

encountered while attempting to transmit. This count includes

late collisions and frames that encountered MAXCOL.

36 Receive Good

Frames

This counter contains the number of frames that were received

properly from the link. It is updated only after the actual

reception from the link is completed and all the data bytes are

stored in memory.

40 Receive CRC Errors

This counter contains the number of aligned frames discarded

because of a CRC error. This counter is updated, if needed,

regardless of the Receive Unit state. The Receive CRC Errors

counter is mutually exclusive of the Receive Alignment Errors

and Receive Short Frame Errors counters.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

328 Intel ® ICH7 Family Datasheet

The Statistical Counters are initially set to 0 by the ICH7’s integrated LAN controller

after reset. They cannot be preset to anything other than 0. The LAN controller

increments the counters by internally reading them, incrementing them and writing

them back. This process is invisible to the processor and PCI bus. In addition, the

counters adhere to the following rules:

• The counters are wrap-around counters. After reaching FFFFFFFFh the counters

wrap around to 0.

• The LAN controller updates the required counters for each frame. It is possible for

more than one counter to be updated as mu ltiple errors can occur in a single fr ame.

• The counters are 32 bits wide and their behavior is fully compatible with the IEEE

802.1 standard. The LAN controller supports all mandatory and recommend

44 Receive Alignment

Errors

This counter contains the number of frames that are both

misaligned (for example, CRS de-asserts on a non-octal

boundary) and contain a CRC error. The counter is updated, if

needed, regardless of the Receive Unit state. The Receive

Alignment Errors counter is mutually exclusive of the Receive

CRC Errors and Receive Short Frame Errors counters.

48 Receive Resource

Errors

This counter contains the nu mber of good frames discarded due

to unavailability of resources. Frames intended for a host whose

Receive Unit is in the No Resources state fall into this category . If

the LAN controller is configured to Save Bad Frames and the

status of the received frame indicates that it is a bad frame, the

Receive Resource Errors counter is not updated.

52 Receive Overrun

Errors

This counter contains the nu mber of frames known to be lost

because the local system bus was not available. If the traffic

problem persists for more than one fr ame, the frames that follow

the first are also lost; however, because there is no lost frame

indicator, they are not counted.

56 Receive Collision

Detect (CDT) This counter contains the nu mber of frames that encountered

collisions during frame reception.

60 Receive Short

Frame Erro rs

This counter contains the nu mber of received frames that are

shorter than the minimum frame length. The Receive Short

Frame Errors counter is mutually exclusive to the Receive

Alignment Errors and R eceive CRC Errors counters. A short frame

will always increment only the Receive Short Frame Errors

counter.

64 Flow Control

Transmit Pause

This counter contains the number of Flow Control frames

transmitted by the L A N controller. This count i ncludes both the

Xof f frames t ransmitted an d Xon (PAUSE(0)) frames transmitted.

68 Flow Control

Receive Pause

This counter contains the number of Flow Control frames

received by the LAN controller. This count includes both the Xoff

frames received and Xon (PAUSE(0)) frames received.

72 Flow Control

Receive

Unsupported

This counter c ontains the number of MAC Control frames

received by the LAN controller that are not Flow Control Pause

frames. T hese frames are vali d MAC control frames that ha ve the

predefined MAC control Type value and a valid address but has

an unsupported opcode.

76 Receiv e TCO Fr ame s This counter contains the number of TCO packets received by the

LAN controller.

78 Transmit TCO

Frames This counter contains the number of TCO packets transmitted.

Table 8-6. Statistical Counters (Sheet 2 of 2)

ID Counter Description

Intel ® ICH7 Family Datasheet 329

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

statistics functions through the status of the receive header and directly through

these Statistical Counters.

The processor can access the counters by issuing a Dump Statistical Counters SCB

command. This provides a “snapshot”, in main memory, of the internal LAN controller

statistical counters. The LAN controller supports 21 counters. The dump could consist

of the either 16, 19, or all 21 counters, depending on the status of the Extended

Statistics Counters and TCO Statistics configur ation bits in the Configuration command.

8.3 ASF Configuration Registers

(LAN Controller—B1:D8:F0)

The ASF registers in this table are accessible through the ICH7 SMBus slave interface.

Table 8-7. ASF Register Address Map

Offset Mnemonic Register Name Default Type

E0h ASF_RID ASF Revision Identification ECh RO

E1h SMB_CNTL SMBus Control 40h R/W

E2h ASF_CNTL ASF Control 00h R/W, RO

E3h ASF_CNTL_EN ASF Control En able 00h R/W

E4h ENABLE Enable 00h R/W

E5h APM APM 08h R/W

E6h–E7h — Reserved — —

E8h WTIM_CONF Watchdog Ti me r Configur at ion 00h R/W

E9h H EART_TIM Heartbeat Timer 02h R/W

EAh RETRAN_INT Retransmission In terval 02h R/W

EBh RETRAN_PC L Retransmission Packet Count Limit 03h R/W

ECh ASF_WTIM1 ASF Watchdog Timer 1 01h R/W

EDh ASF_WTIM2 ASF Watchdog Timer 2 00h R/W

F0h PET_SEQ1 PET Sequence 1 00h R/W

F1h PET_SEQ2 PET Sequence 2 00h R/W

F2h STA Status 40h R/W

F3h FOR_ACT Forced Actions 02h R/W

F4h RMCP_SNUM RMCP Sequence Nu mber 00h R/W

F5h SP_MODE Special Modes x0h R/WC, RO

F6h INPOLL_TCONF Inter-Poll Timer Configuration 10h R/W

F7h PHIST_CLR Poll History Clear 00h R/WC

F8h PMSK1 Polling Mask 1 XXh R/W

F9h PMSK2 Polling Mask 2 XXh R/W

FAh PMSK3 Polling Mask 3 XXh R/W

FBh PMSK4 Polling Mask 4 XXh R/W

FCh PMSK5 Polling Mask 5 XXh R/W

FDh PMSK6 Polling Mask 6 XXh R/W

FEh PMSK7 Polling Mask 7 XXh R/W

FFh PM SK8 Polling Mask 8 XXh R/W

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330 Intel ® ICH7 Family Datasheet

8.3.1 ASF_RID—ASF Revision Identification Register

(LAN Controller—B1:D8:F0)

Offset Address: E0h Attribute: RO

Default Value: ECh Size: 8 bits

8.3.2 SMB_CNTL—SMBus Control Register

(LAN Controller—B1:D8:F0)

Offset Address: E1h Attribute: R/W

Default Value: 40h Size: 8 bits

This register is used to control configurations of the SMBus ports.

Bit Description

7:3 ASF ID — RO. Hardwired to 11101 to identify the ASF controller.

2:0 ASF Silicon Revision — RO. This field provides the silicon revision.

Bit Description

7SMBus Remote Control ASF Enable (SMB_RCASF) — R/W.

0 = Legacy descriptors and operations are used.

1 = ASF descriptors and operations are used.

6SMBus ARP Enable (SMB_ARPEN) — R/W.

0 = Disable.

1 = ASF enables the SMBus ARP protocol.

5:4 Reserved

3SMBus Drive Low (SMB_DRVLO) — R/W.

0 = ASF will not drive the main SMBus signals low while PWR_GOOD = 0.

1 = ASF will drive the main SMBus signals low while PWR_GOOD = 0.

2:0 Reserved

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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.3 ASF_CNTL—ASF Control Register

(LAN Controller—B1:D8:F0)

Offset Address: E2h Attribute: R/W, RO

Default Value: 00h Size: 8 bits

This register contains enables for special modes and SOS events. CTL_PWRLS should

be set if ASF should be expecting a power loss due to software action. Otherwise, an

EEPROM reload will happen when the power is lost.

Bit Description

7SMBus Hang SOS Enabl e (CTL_SMBHG) — R/W.

0 = Disable

1 = Enables SMBus Hang SOS to be sent.

6Watchdog SOS Enable (CTL_WDG) — R/W.

0 = Disable.

1 = Enables Watchdog SOS to be sent.

5Link Loss SOS Enable (CTL_LINK) — R/W.

0 = Disable.

1 = Enables Link Loss SOS to be sent.

OS Hung Status (CTL_OSHUNG) — RO.

1 = This bit will be set to 1 when ASF has de tected a Watchdog Expiration.

NOTE: This condition is only clearable by a PCI RST# assertion (system reset).

3Power-Up SOS Enable (CTL_PWRUP) — R/W.

0 = Disable.

1 = Enables Power-Up SOS to be sent.

2 Reserved

Receive ARP Enab le (CTL_RXARP) — R/W. The LAN controller interface provides a

mode where all packets can be requested.

0 = Disable.

1 = Enable. ASF requests all packets when doing a Receive Enable. This is necessary in

LAN controller to get ARP packets.

NOTE: Changes to this bit will not take effect until the next Receive Enable comman d

to the LAN.

0Power Loss OK (CTL_PWRLS) — R/W.

0 = Power Loss will reload EEPROM

1 = Power Loss will not reload EEPROM

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332 Intel ® ICH7 Family Datasheet

8.3.4 ASF_CNTL_EN—ASF Control Enable Register

(ASF Controller—B1:D8:F0)

Offset Address: E3h Attribute: R/W

Default Value: 00h Size: 8 bits

This register is used to enable global processing as well as polling. GLOBAL ENABLE

controls all of the SMBus processing and packet creation.

Bit Description

7Global Enable (CENA_ALL) — R/W.

0 = Disable

1 = All contr ol and polling enabled

6Receive Enable (CENA_RX) — R/W.

0 = Disable

1 = TCO Receives enabled.

5Transmit Enable (CENA_TX) — R/W.

0 = Disable

1 = SOS and RMCP Transmits enabled

4ASF Polling Enable (CENA_APOL) — R/W.

0 = Disable

1 = Enable ASF Sensor Polling.

3Legacy Polling Enable (CENA_LPOL) — R/W.

0 = Disable

1 = Enable Legacy Sensor Polling.

2:0

Number of Legacy Poll Devices (CENA_NLPOL) — R/W. This 3-bit value indicates

how many of the eight possible polling descriptors are active.

000 = First polling descriptor is active.

001 = First two polling descriptors are active.

...

111 = Enables all eight descriptors.

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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.5 ENABLE—Enable Register

(ASF Controller—B1:D8:F0)

Offset Address: E4h Attribute: R/W

Default Value: 00h Size: 8 bits

This register provides the mechanism to enable internal SOS operations and to enable

the remote control functions.

Bit Description

Enable OSHung ARPs (ENA_OSHARP) — R/W.

0 = Disable

1 = ASF will request all packets when in a OSHung state. This allows ASF to receive

ARP frames and respond as appropriate.

6State-based Securi t y De st in at i on Po rt Se lect (ENA_SB0298 ) — R/W.

0 = State-based security will be honored on packets received on port 026Fh.

1 = Packets received on port 0298h will be honored.

PET VLAN Enable (ENA_VLAN) — R/W.

0 = Disable

1 = Indicates a VLAN header for PET

NOTE: If this bit is set, the PET packet in EEPROM must have the VLAN tag within the

packet.

4 Reserved

3System Power Cycle Enabl e (EN A_ CYCLE) — R/W.

0 = Disable

1 = Enables RMCP Power Cycle action.

2System Power-Down Enable (ENA_DWN) — R/W.

0 = Disable

1 = Enables RMCP Power-Down action.

1System Power-Up Enable (ENA_UP) — R/W.

0 = Disable

1 = Enables RMCP Power-Up action.

0System Reset Enable (ENA_RST) — R/W.

0 = Disable

1 = Enables RMCP Reset action

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334 Intel ® ICH7 Family Datasheet

8.3.6 APM—APM Register

(ASF Controller—B1:D8:F0)

Offset Address: E5h Attribute: R/W

Default Value: 08h Size: 8 bits

This register contains the configuration bit to disable state-based security.

8.3.7 WTIM_CONF—Watchdog Timer Configuration Register

(ASF Controller—B1:D8:F0)

Offset Address: E8h Attribute: R/W

Default Value: 00h Size: 8 bits

This register contains a single bit that enables the Watchdog timer. This bit is not

intended to be accessed by software, but should be configured appropriately in the

EEPROM location for this register default. The bit provides real-time control for

enabling/disabling the Watchdog timer. When set the timer will count down. When

cleared the counter will stop. Timer Start ASF SMBUS messages will set this bit. Timer

Stop ASF SMBus transactions will clear this bit.

Bit Description

7:4 Reserved

3Disable State-based Securi ty (APM_DISSB) — R/W.

0 = State-based security on OSHung is enabled.

1 = State-based security is disabled and actions are not gated by OSHung.

2:0 Reserved

Bit Description

7:1 Reserved

0Timer Enable (WDG_ENA) — R/W.

0 = Disable

1 = Enable Counter

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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.8 HEART_TIM—Heartbeat Timer Register

(ASF Controller—B1:D8:F0)

Offset Address: E9h Attribute: R/W

Default Value: 02h Size: 8 bits

The HeartBeat Timer register implements the heartbeat timer. This defines the period

of the heartbeats packets. It contains a down counting value when enabled and the

time-out value when the counter is disabled. The timer can be configured and enabled

in a single write.

Note: The heartbeat timer controls the heartbeat status packet frequency. The timer is free-

running and the configured time is only valid from one heartbeat to the next. When

enabled by software, the next heartbeat may occur in any amount of time less than the

configured time.

8.3.9 RETRAN_INT—Retransmission Interval Register

(ASF Controller—B1:D8:F0)

Offset Address: EAh Attribute: R/W

Default Value: 02h Size: 8 bits

This register implements the retransmission timer. This is the time between packet

transmissions for multiple packets due to a SOS.

Bit Description

7:1

Heartbeat Timer V alue (HBT_VAL) — R/W. Heartbeat timer load value in

10.7-second resolution. This field can only be written while the timer is disabled.

(10.7 sec – 23 min range). Read as load value when HBT_ENA=0. Read as

decrementing value when HBT_ENA=1. Timer resolution is 10.7 seconds. A value of

00h is invalid.

0Timer Enable (HBT_ENA) — R/W.

0 = Disable

1 = Enable / Reset Counter

Bit Description

7:1

Retransmit Timer Value (RTM_VAL) — R/W. Retransmit timer load val ue 2.7 second

resolution. This field is always writable (2.7 sec – 5.7 min range). Timer is accurate to

+0 seconds, –0.336 seconds. Reads alwa ys show the load value (decreme nt va lue not

shown). A value of 00h is invalid.

0 Reserved

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

336 Intel ® ICH7 Family Datasheet

8.3.10 RETRAN_PCL—Retransmission Packet Count Limit

Offset Address: EBh Attribute: R/W

Default Value: 03h Size: 8 bits

This register defines the number of packets that are to be sent due to an SOS.

8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register

(ASF Controller—B1:D8:F0)

Offset Address: ECh Attribute: R/W

Default Value: 01h Size: 8 bits

This register is used to load the low byte of the timer. When read, it reports the

decrementing value. This register is not intended to be written by softw are, but should

be configured appropriately in the EEPROM location for this register default. Timer Start

ASF SMBus transactions will load values into this register. Once the timer has expired

(0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will

remain at 00h until otherwise changed.

8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register

(ASF Controller—B1:D8:F0)

Offset Address: EDh Attribute: R/W

Default Value: 00h Size: 8 bits

This register is used to load the high byte of the timer. When read, it reports the

decrementing value. This register is not intended to be written by softw are, but should

be configured appropriately in the EEPROM location for this register default. Timer Start

ASF SMBus transactions will load values into this register. Once the timer has expired

(0000h), the timer will be disabled (EDG_ENA=0b) and the value in this register will

remain at 00h until otherwise changed.

Bit Description

7:0 Retransmission Packet Count Limit (RPC_VAL) — R/W. This field provides the

number of packets to be sent for all SOS packets that require retransmissions.

Bit Description

7:0 ASF Watchdog Time r 1 (AWD1_VAL) — R/W. This field provides the low byte of the

ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336 seconds.

Bit Description

7:0 ASF Watchdog Timer 2 (AWD2_VAL) — R/W. This field provides the high byte of

the ASF 1-second resolution timer. The timer is accurate to +0 seconds, –0.336

seconds.

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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.13 PET_SEQ1—PET Sequence 1 Register

(ASF Controller—B1:D8:F0)

Offset Address: F0h Attribute: R/W

Default Value: 00h Size: 8 bits

This register (low byte) holds the current value of the PET seque nc e nu mb er. This field

is read/write-able through this register, and is also automatically incremented by the

hardware when new PET pack ets are gener ated. By policy, software should not write to

this register unless transmission is disabled.

8.3.14 PET_SEQ2—PET Sequence 2 Register

(ASF Controller—B1:D8:F0)

Offset Address: F1h Attribute: R/W

Default Value: 00h Size: 8 bits

This register (high byte) holds the current v alue of the PE T sequence number. This field

is read/write-able through this register, and is also automatically incremented by the

hardware when new PET pack ets are gener ated. By policy, software should not write to

this register unless transmission is disabled.

Bit Description

7:0 PET Sequence Byte 1 (PSEQ1_VAL) — R/W. This field provides the low byte.

Bit Description

7:0 PET Sequence Byte 2 (PSEQ2_VAL) — R/W. This field provides the high byte.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

338 Intel ® ICH7 Family Datasheet

8.3.15 STA—Status Register

(ASF Controller—B1:D8:F0)

Offset Address: F2h Attribute: R/W

Default Value: 40h Size: 8 bits

This register gives status indication about several aspects of ASF.

Bit Description

7EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being

loaded when this bit is a 1.

EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be read

only after the EEC_LOAD bit is a 0.

0 = Valid

1 = Invalid checksum detected for ASF portion of the EEPROM.

5:4 Reserved

3Power Cycle Status (STA_CYCLE) — R/W.

0 = Software clears this bit by writing a 1.

1 = This bit is set when a Power Cycle operation has been issued.

2Power Down St at u s (ST A_DOWN) — R/W.

0 = Software clears this bit by writing a 1

1 = This bit is set when a Power Down operation has been issued.

1Power Up Status (STA_UP) — R/W.

0 = Software clears this bit by writing a 1

1 = This bit is set when a Power Up operation has been issued.

0System Reset Status (STA_RST) — R/W.

0 = Software clears this bit by writing a 1

1 = This bit is set when a System Reset operation has been issued.

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LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.16 FOR_ACT—Forced Actions Register

(ASF Controller—B1:D8:F0)

Offset Address: F3h Attribute: R/W

Default Value: 02h Size: 8 bits

This register contains many different forcible actions including APM functions, flushing

internal pending SOS operations, software SOS operations, software reset, and

EEPROM reload. Writes to this register must only set one bit per-write. Setting multiple

bits in a single write can have indeterminate results.

Note: For bits in this register, writing a 1 invokes the operation. The bits self-clear

immediately.

Bit Description

7Software Reset (FRC_RST) — R/W. This bit is used to reset the ASF controller. It

performs the equivalent of a hardware reset and re-read the EEPROM. This bit self-

clears immediately. Software should wait for the EEC_LOAD bit to clear.

Force EEPROM Reload (FRC_EELD) — R/W. Force Reload of EEPROM without affect

current monitoring state of the ASF controller. This bit se lf-clears immediately.

NOTE: Software registers in EEPROM are not loaded by this action. Software should

disable the ASF controller before issuing this command and wait for STA_LOAD

to clear before enabling again.

Flush SOS (FRC_FLUSH) — R/W. This bit is used to flush any pending SOSes or

history internal to the AS F controller. This is necess ary because the Status regis ter only

shows events that have happened as opposed to SOS events sent. Also, the hi story bits

in the ASF controller are not software visible. Self-cle ars imm edi ate ly.

4 Reserved

3Force AP M Power Cycl e (FRC_ACYC ) — R/W. This mode forces the ASF controller to

initiate a power cycle to the system. The bit self-clears immediately.

2Force APM Hard Power Down (FRC_A HD N) — R/W. This mode forces the ASF

controller to initiate a hard power down of the system immediately. The bit self-clears

immediately.

1Clear ASF Polling History (FRC_CLRAPOL) — R/W. Writing a 1b to this bit position

will clear the Poll History associ ated with all ASF P olling. Wri ting a 0b has no e ffect. This

bit self-clear s imme diat ely.

0Force APM Reset (FRC_ARST) — R/W. This mode forces the ASF controller to initiate

a hard reset of the system immediately. The bit self-clears immediately.

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340 Intel ® ICH7 Family Datasheet

8.3.17 RMCP_SNUM—RMCP Sequence Number Register

(ASF Controller—B1:D8:F0)

Offset Address: F4h Attribute: R/W

Default Value: 00h Size: 8 bits

This register is a means for software to read the current sequence number that

hardware is using in RMCP packets. Software can also change the value. Software

should only write to this register while the GLOBAL ENABLE is off.

8.3.18 SP_MODE—Special Modes Register

(ASF Controller—B1:D8:F0)

Offset Address: F5h Attribute: R/WC, RO

Default Value: x0h Size: 8 bits

The register contains miscellaneous functions.

8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register

(ASF Controller—B1:D8:F0)

Offset Address: F6h Attribute: R/W

Default Value: 10h Size: 8 bits

This register is used to load and hold the value (in increments of 5 ms) for the polling

timer. This value determines how often the ASF polling timer expires which determines

the minimum idle time between sensor polls.

Bit Description

7:0

RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current se quence numbe r

of the RMCP packet being sent or the sequence number of the next RMCP packet to be

sent. This value can be set by software. At reset, it defaults to 00h. If the sequence

number is not FFh, the ASF controller wi ll automatic ally increment this number by one

(or rollover to 00h if incrementing from FEh) after a successful RMCP packet

transmission.

Bit Description

7SMBus Activity Bit (SPE_ACT) — RO.

1 = ASF controller is active with a SMBus transaction. This is an indicator to software

that the ASF controller is still pr ocessing commands on the SMBus.

6Watchdog Status (SPE_WDG) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when a watchdog expiration occurs.

5Link Loss Status (SPE_LNK) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when a link loss occurs (link is down for more than 5 seconds).

4:0 Reserved

Bit Description

7:0 Inter-Poll Timer Configuration (IPTC_VAL) — R/W. This field identifies the time, in

5.24 ms units that the ASF controller will wait between the end of the one ASF Poll Alert

Message to start on the next. The value 00h is invalid and unsupported.

Intel ® ICH7 Family Datasheet 341

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.20 PHIST_CLR—Poll History Clear Regist er

(ASF Controller—B1:D8:F0)

Offset Address: F7h Attribute: R/WC

Default Value: 00h Size: 8 bits

This register is used to clear the history of the Legacy Poll operations. ASF maintains

history of the last poll data for each Legacy Poll operation to compare against the

current poll to detect changes. By setting the appropriate bit, the history for that

Legacy Poll is cleared to 0s.

8.3.21 PMSK1—Polling Mask 1 Register

(ASF Controller—B1:D8:F0)

Offset Address: F8h Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #1 Data Mask.

Bit Description

7Clear Polling Descriptor 8 History (PHC_POLL8) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #8. Writing a 0b

has no effect.

6Clear Polling Descriptor 7 History (PHC_ POLL7) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #7. Writing a 0b

has no effect.

5Clear Polling Descriptor 6 History (PHC_ POLL6) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #6. Writing a 0b

has no effect.

4Clear Polling Descriptor 5 History (PHC_POLL5) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #5. Writing a 0b

has no effect.

3Clear Polling Descriptor 4 History (PHC_ POLL4) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #4. Writing a 0b

has no effect.

2Clear Polling Descriptor 3 History (PHC_POLL3) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #3. Writing a 0b

has no effect.

1Clear Polling Descriptor 2 History (PHC_ POLL2) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #2. Writing a 0b

has no effect.

0Clear Polling Descriptor 1 History (PHC_POLL1) — R/WC. Writing a 1b to this bit

position will clear the Poll History associated with Polling Descriptor #1. Writing a 0b

has no effect.

Bit Description

7:0 Polling Mask fo r Po lling Descriptor #1 (POL1_MSK) — R/W. This field is used to

read and write the data mask for Polling Descriptor #1. Software should only access

this register when the ASF controller is GLOBAL DISABLED.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

342 Intel ® ICH7 Family Datasheet

8.3.22 PMSK2—Polling Mask 2 Register

(ASF Controller—B1:D8:F0)

Offset Address: F9h Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #2 Data Mask.

8.3.23 PMSK3—Polling Mask 3 Register

(ASF Controller—B1:D8:F0)

Offset Address: FAh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #3 Data Mask.

8.3.24 PMSK4—Polling Mask 4 Register

(ASF Controller—B1:D8:F0)

Offset Address: FBh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #4 Data Mask.

Bit Description

7:0 Polling Mask for Polling Descriptor #2 (POL2_MSK) — R/W. This field is used to

read and write the data mask for Polling Descriptor #2. Software should only access

this register when the ASF controller is GLOBAL DISABLED.

Bit Description

7:0 Polling Mask for Polling Descriptor #3 (POL3_MSK) — R/W. This register is used

to read and write the data mask for Polling Descriptor #3. Softwa re shoul d only access

this register when the ASF controller is GLOBAL DISABLED.

Bit Description

7:0 Polling Mask for Polling Descriptor #4 (POL4_MSK) — R/W. This register is used

to read and write the data mask for Polling Descriptor #4. Softwa re shoul d only access

this register when the ASF controller is GLOBAL DISABLED.

Intel ® ICH7 Family Datasheet 343

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

8.3.25 PMSK5—Polling Mask 5 Register

(ASF Controller—B1:D8:F0)

Offset Address: FCh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #5 Data Mask.

8.3.26 PMSK6—Polling Mask 6 Register

(ASF Controller—B1:D8:F0)

Offset Address: FDh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #6 Data Mask.

8.3.27 PMSK7—Polling Mask 7 Register

(ASF Controller—B1:D8:F0)

Offset Address: FEh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #7 Data Mask.

Bit Description

7:0 Polling Mask for Polling Descriptor #5 (POL5_MSK) — R/W. This register is used

to read and write the data mask for Polling Descriptor #5. Software should only access

this regis ter when the ASF controller is GLOBAL DISABLED.

Bit Description

7:0 Polling Mask for Polling Descriptor #6 (POL6_MSK) — R/W. This register is used

to read and write the data mask for Polling Descriptor #6. Software should only access

this regis ter when the ASF controller is GLOBAL DISABLED.

Bit Description

7:0 Polling Mask fo r Polling Descriptor #7 (POL7_MSK) — R/W. This register is used

to read and write the data mask for Polling Descriptor #7. Software should only access

this register when the ASF controller is GLOBAL DISABLED.

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)

344 Intel ® ICH7 Family Datasheet

8.3.28 PMSK8—Polling Mask 8 Register

(ASF Controller—B1:D8:F0)

Offset Address: FFh Attribute: R/W

Default Value: XXh Size: 8 bits

This register provides software an interface for the Polling #8 Data Mask.

Bit Description

7:0 Polling Mask for Polling Descriptor #8 (POL8_MSK) — R/W. This register is used

to read and write the data mask for P ollin g Descriptor #8. Software should only access

this register when the ASF controller is GLOBAL DISABLED.

Intel ® ICH7 Family Datasheet 345

PCI-to-PCI Bridge Registers (D30:F0)

9 PCI-to-PCI Bridge Registers

(D30:F0)

The ICH7 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements

the buffering and control logic between PCI and the backbone. The arbitration for the

PCI bus is handled by this PCI device.

9.1 PCI Configuration Registers (D30:F0)

Note: Address locations that are not shown should be treated as Reserved (see Section 6.2

for details).

Table 9-1. PCI Bridge Register Address Map (P CI-PCI—D30:F0)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PSTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See

description RO

09h-0Bh CC Class Code 00060401h RO

0Dh PMLT Primary Master Latency Timer 00h RO

0Eh HEADTYP Header Type 81h RO

18h-1Ah BNUM Bus Number 000000h R/W, RO

1Bh SMLT Secondary Master Latency Timer 00h R/W, RO

1Ch-1Dh IOBASE_LIMIT I/O Base and Limit 0000h R/W, RO

1Eh–1Fh SECSTS Secondary Status 0280h R/WC, RO

20h–23h MEMBASE_LIMIT Memory Base and Limit 00000000h R/W, RO

24h–27h PREF_MEM_BASE

_LIMIT Prefetchable Memory Base and Limit 00010001h R/W, RO

28h–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W

2Ch–2Fh PMLU32 Prefetchable Memory Limit Uppe r 32

Bits 00000000h R/W

34h CAPP Capability List Pointer 50h RO

3Ch-3Dh INTR Interrupt Information 0000h R/W, RO

3Eh–3Fh BCTRL Bridge Control 0000h R/WC, RO

40h–41h SPDH Secondary PCI Device Hiding 00h R/W, RO

44h-47h DTC Delayed Transaction Control 00000000h R/W, RO

48h-4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO

4Ch-4Fh BPC Bridge Policy Configuration 00001200h R/W RO

50–51h SVCAP Subsystem V endor Capability P ointer 000Dh RO

54h-57h SVID Subsystem Vendor IDs 00000000 R/WO

PCI-to-PCI Bridge Register s (D30:F0)

346 Intel ® ICH7 Family Datasheet

9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.

Bit Description

15:0 Device ID — RO.This is a 16-bit value assigned to the PCI bridge. Refer to the Intel®

I/O Controller Hub 7 (ICH7) Family Specification Update for the value of the Device

ID Register.

Bit Description

15:11 Reserved

10 Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to

disable

9Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

SERR# Enable (SERR_EN) — R/W.

0 = Disable.

1 = Enable the Intel® ICH7 to generate an NMI (or SMI# if NMI routed to SMI#) when

the D30:F0 SSE bit (offset 06h, bit 14) is set.

7Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

Parity Error Response (PER) — R/W.

0 = The ICH7 ignores parity errors on the PCI bridge.

1 = The ICH7 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are

detected on the PCI bridge.

5VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a.

4Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI

Express* Base Specification, Revisi on 1.0a

3Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base

Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.

Intel ® ICH7 Family Datasheet 347

PCI-to-PCI Bridge Registers (D30:F0)

9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)

Offset Address: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

2Bus Master Enable (BME) — R/W.

0 = Disable

1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.

Memory Space Enable (MSE) — R/W. Controls the response as a target for memory

cycles targeting PCI.

0 = Disable

1 = Enable

I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles

targeting PCI.

0 = Disable

1 = Enable

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = Parity error Not detected.

1 = Indicates that the Intel® ICH7 detected a parity error on the internal backbone.

This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set .

PCI-to-PCI Bridge Register s (D30:F0)

348 Intel ® ICH7 Family Datasheet

Signaled System Error (SSE) — R/WC. Several internal and external sources of the

bridge can cause SERR#. The first class of errors is parity errors related to the

backbone. The PCI bridge captures generic data parity errors (errors it finds on the

backbone) as well as errors returned on backbone cycles where the bridge was the

master. If either of these two conditions is met, and the primary side of the bridge is

enabled for parity error response, SERR# will be captured as shown below.

As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge

captures generic data parity errors (errors it finds on PCI) as well as errors returned on

PCI cycles where the bridge was the master. If either of these two conditions is met,

and the secondary side of the bridge is enabled for parity error response, SERR# will be

captured as shown below.

The final class of errors is system bus errors. There are three status bits associated with

system bus er rors, each with a corresponding enable. The diagram capturing this is

shown below.

After checking for the three above classes of errors, an SERR# is generated, and

PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown

below.

13 Received Master Abort (RMA) — R/WC.

0 = No master abort received.

1 = Set when the bridge receives a master abort status from the backbone.

12 Received Target Abort (RTA) — R/WC.

0 = No target abort received.

1 = Set when the bridge receives a target abort status from the backbone.

Bit Description

Intel ® ICH7 Family Datasheet 349

PCI-to-PCI Bridge Registers (D30:F0)

9.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

9.1.6 CC—Class Code Register (PCI-PCI—D30:F0)

Offset Address: 09h-0Bh Attribute: RO

Default Value: 060401h Size: 24 bits

Signaled Target Abort (STA) — R/WC.

0 = No signaled target abort

1 = Set when the bridge generates a c ompleti on pack et wi th tar get abort statu s on the

backbone.

10:9 Reserved.

Data Parity Error Detected (DPD) — R/WC.

0 = Data parity erro r Not detected.

1 = Set when the bridge receives a completion packet from the backbone from a

previous request, and detects a parity error, and CMD.PERE is set (D3 0:F0:04 bit

6).

7:5 Reserved.

4 Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.

3Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate

interrupts.

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

Bit Description

23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.

15:8 Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI

bridge.

7:0 Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractiv e

decode

PCI-to-PCI Bridge Register s (D30:F0)

350 Intel ® ICH7 Family Datasheet

9.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 81h Size: 8 bits

9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)

Offset Address: 18h-1Ah Attribute: R/W, RO

Default Value: 000000h Size: 24 bits

Bit Description

7:3 Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base

Specification, Revision 1.0a.

2:0 Reserved

Bit Description

Multi-Function Device (MFD) — RO. The v alue reported here depends upon the state

of the AC ‘97 function hide (FD) register (Chipset Config Registers:Offset 3418h), per

the following table:

6:0 Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the

configuration space, which is a PCI-to-PCI bridge in this case.

FD.AAD FD.AMD MFD

001

011

101

110

Bit Description

23:16 Subordinate Bus Numb er (SBBN) — R/W. Indicates th e highest PCI bus number

below the bridge.

15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.

7:0 Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.

Intel ® ICH7 Family Datasheet 351

PCI-to-PCI Bridge Registers (D30:F0)

9.1.10 SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)

Offset Address: 1Bh Attribute: R/W, RO

Default Value: 00h Size: 8 bits

This timer controls the amount of time the ICH7 PCI-to-PCI bridge will burst data on its

secondary interface. The counter starts counting down from the assertion of FRAME#.

If the grant is removed, then the expiration of this counter will result in the de-

assertion of FRAME#. If the grant has not been removed, then the ICH7 PCI-to-PCI

bridge may continue ownership of the bus.

9.1.11 IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 1Ch-1Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

7:3 Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of

PCI clocks, in 8-clock i ncrements, that the In tel® ICH7 remains as master of the bus.

2:0 Reserved

Bit Description

15:12 I/O Limit Address Limit bits[15 :12 ] — R/W. I/O Base bits corresponding to address

lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.

11:8 II/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support

32-bit I/O addressing.

7:4 I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12

for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.

3:0 I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not support

32-bit I/O addressing.

PCI-to-PCI Bridge Register s (D30:F0)

352 Intel ® ICH7 Family Datasheet

9.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)

Offset Address: 1Eh–1Fh Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = Parity error not detected.

1 = Intel ® ICH7 PCI bridge detected an address or data parity error on the PCI bus

14 Received System Error (RSE) — R/WC.

0 = SERR# assertion not received

1 = SERR# assertion is received on PCI.

Received Master Abort (RMA) — R/WC.

0 = No master abo rt.

1 = This bit i s set whenever the bridge is acting as an initiator on the PCI bus and the

cycle is master-aborted. For (G)MCH/ICH7 interface packets that have completion

required, th is must also cause a target abort to be returned and sets PSTS.STA.

(D30:F0:06 bit 11)

Received Target Abort (RTA) — R/WC.

0 = No target abort.

1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is

target-aborted on PCI. For (G)MCH/ICH7 interface packets that have completion

required, this event must also cause a target abort to be returned, and sets

PSTS.STA. (D30:F0:06 bit 11).

Signaled Target Abort (STA) — R/WC.

0 = No target abort.

1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a

target abort.

10:9 DEVSEL# Timing (DEVT) — RO.

01h = Medium decode timing.

Data Parity Error Detected (DPD) — R/WC.

0 = Conditions described below not met.

1 = The ICH7 sets this bit when all of the following three condit ions are met:

• The bridge is the initiator on PCI.

• PERR# is detected asserted or a parity error is detected internally

• BCTRL.PERE (D30:F0:3E bit 0) is set.

7Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI

target logic is capable of receiving fast back-to-back cycles.

6 Reserved

566 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable

only.

4:0 Reserved

Intel ® ICH7 Family Datasheet 353

PCI-to-PCI Bridge Registers (D30:F0)

9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)

Offset Address: 20h–23h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This register defines the base and limit, aligned to a 1-MB boundary, of the non-

prefetchable memory area of the bridge. Accesses that are within the ranges specified

in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside

the ranges specified will be accepted by the bridge if CMD.BME is set.

9.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0)

Offset Address: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32-bit

Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory

area of the bridge. Accesses that are within the ranges specified in this register will be

sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified

will be accepted by the bridge if CMD.BME is set.

Bit Description

31-20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the upper 1-MB aligned value (exclusive) of the range. The

incoming address must be less than this value.

19-16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the lower 1-MB aligned value (inclusive) of the range. The

incoming address must be greater than or equal to this value.

3:0 Reserved

Bit Description

31-20 Prefetchabl e Memory Limi t (PML) — R/W. Thes e bits are co mpared with bits 31:20

of the incoming address to determine the upper 1-MB aligned value (exclusive) of the

range. The incoming address must be less than this value.

19-16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing.

15:4 Prefetchabl e Me mory B ase ( PMB) — R/W. These bits are compared with bits 31:20

of the incoming address to determine the lower 1-MB aligned value (inclusive) of the

range. The incoming address must be greate r than or equal to this value.

3:0 64-bit Indicat or (I64B) — RO. Indicates support for 64-bit addressing.

PCI-to-PCI Bridge Register s (D30:F0)

354 Intel ® ICH7 Family Datasheet

9.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits

Offset Address: 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Offset Address: 2C–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)

Offset Address: 34h Attribute: RO

Default Value: 50h Size: 8 bits

9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)

Offset Address: 3Ch–3Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the

prefetchable address base.

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the

prefetchable address limit.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the

capabilities list is at 50h in configuration space.

Bit Description

15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.

7:0

Interrupt Line (ILINE) — R /W. Software writte n val ue to indicate which int errupt line

(vector) the interrupt is connected to. No hardware action is taken on this registe r.

Since the bridge does not gener ate an interrupt , BIOS should progr am this valu e to FFh

as per the PCI bridge specification.

Intel ® ICH7 Family Datasheet 355

PCI-to-PCI Bridge Registers (D30:F0)

9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)

Offset Address: 3Eh–3Fh Attribute: R/WC, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:12 Reserved

Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on

the primary interface in response to the DTS bit being set:

0 = Do not generate SER R# on a secondary timer discard

1 = Generate SERR# in response to a secondary timer discard

10 Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard

timer (see the SDT bit below) expires for a delayed transaction in the hard state.

Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI

clock cycles that the Intel® ICH7 waits for an initiator on PCI to repeat a delayed

transaction request. The counter starts once the delayed transaction data is has been

returned by the system and is in a buffer in the ICH7 PCI bridge. If the master has not

repeated the transaction at least once before the counter expires, the ICH7 PCI bridge

discards the transaction from its queue.

0 = The PCI master timeout value is between 215 and 216 PCI clocks

1 = The PCI master timeout value is between 210 and 211 PCI clocks

8Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.

7Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate

fast back-to-back cycles on the PC I bus.

Secondary Bus Reset (SBR) — R/W. This bit controls PCIRST# assertion on PCI.

0 = Bridge de-asserts PCIRST#

1 = Bridge asserts PCIRST#. When PCIRST# is asserted, th e delayed transaction

buffers, posting buffers, and the PCI bus are initialized back to reset conditions.

The rest of the part and the configuration registers are not affected.

Master Abort Mode (MAM) — R/W. This bit controls the ICH7 PCI bridge’s behavior

when a master abort occurs:

Master Abort on (G)MCH/ICH7 Interconnect (DMI):

0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on

writes.

1 = Bridge returns a target abort on PCI.

Master Abort PCI (non-locked cycles):

0 = Normal completion status will be returned on the (G)MCH/ICH7 interconnect.

1 = Target abort completion status will be returned on the (G)MCH/ICH7 inte rconnect.

NOTE: All locked reads will return a completer abort completion status on the (G)MCH/

ICH7 interconnect.

4VGA 16-Bit Deco de (V16D) — R/W. This bit controls enables the ICH7 PCI bridge to

provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias

addresses every 1 KB. This bit requires the VGAE bit in this register be set.

PCI-to-PCI Bridge Register s (D30:F0)

356 Intel ® ICH7 Family Datasheet

9.1.20 SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)

Offset Address: 40h–41h Attribute: R/W, RO

Default Value: 00h Size: 16 bits

This register allows software to hide the PCI devices, either plugged into slots or on the

motherboard.

VGA Enable (VGAE) — R/W. When set to a 1, the ICH7 PCI bridge forwards the

following tr ansactions to PCI r egardless of th e v alue of the I/O base and li mit registers .

The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE

(D30:F0:04 bit 0) being set.

• Memory addresses: 000A0000h-000BFFFFh

• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address

must be 0, and bits [15:10] of the address are ignored (i.e., aliased).

The same holds true from secon dary acce sses t o the pri mary inter face in rev erse. That

is, when the bit is 0, memory and I/O addresses on the secondary interface between

the above ranges will be claimed.

ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the

I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is

set, the ICH7 PCI bridge will block any forwarding from primary to secondary of I/O

transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).

SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface

SERR# assertions on the primary interface. When set, the PCI bridge will forward

SERR# pin.

• SERR# is asserted on the secondary interface.

• This bit is set.

• CMD.SEE (D30:F0:04 bit 8) is set.

Parity Error Response Enable (PERE) — R/W.

0 = Disable

1 = The ICH7 PCI bridge is enabled for parity error reporting based on parity errors on

the PCI bus.

Bit Description

15:8 Reserved

7Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7

(AD[23])

6Hide Device 6 (HD 6) — R/W, RO. Same as bit 0 of this register, except for device 6

(AD[22])

5Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5

(AD[21])

4Hide Device 4 (HD 4) — R/W, RO. Same as bit 0 of this register, except for device 4

(AD[20])

3Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3

(AD[19])

Intel ® ICH7 Family Datasheet 357

PCI-to-PCI Bridge Registers (D30:F0)

9.1.21 DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)

Offset Address: 44h–47h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

2Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2

(AD[18])

1Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1

(AD[17])

Hide Device 0 (HD0) — R/W, RO.

0 = The PCI configuration cycles for this slot are not affected.

1 = Intel ® ICH7 hides device 0 on the PCI bus. This is done by masking the IDSEL

(keeping it low) for configuration cycles to that device. Since the device wil l not see

its IDSEL go acti ve, it will not respond to PCI configuration cycl es and the

processor will think the device is not present. AD[16 ] is used as IDSEL for device 0.

Bit Description

Discard Delayed Transactions (DDT) — R/W.

0 = Logged delayed transactions are kept.

1 = The Intel® ICH7 PCI bridge will discard any dela yed transactions it has lo gged. This

includes transactions in the pending queue, and any transactions in the active

queue, whether in the hard or soft DT state. The prefetchers will be disabled and

return to an idle state.

NOTE: If a transaction is runni ng on P CI at the t ime t h is bit i s s et, that transact ion wi ll

continue until either the PCI master disconnects (by de-asserting FRAME#) or

the PCI bridge disconne cts (by asserting STOP#). This bit is cleared by the PCI

bridge when the delayed transaction queues are empty and have returned to an

idle state. Software sets this bit and polls for its completion

Block Delayed Transactions (BDT) — R/W.

0 = Delayed transaction s accepted

1 = The ICH7 PCI bridge will not accept incoming transactions which will result in

delayed transactions. It will blindly retry these cycles by asserting STOP#. All

postable cycles (memory writes) will still be accepted.

29: 8 Reserved

7: 6

Maximum Delayed Transactions (MDT) — R/W. This field controls the maximum

number of delayed transactions that the ICH7 PCI bridge will run. Encodings are:

00 =) 2 Active, 5 pendi n g

01 =) 2 active, no pending

10 =) 1 active, no pending

11 =) Reserved

5 Reserved

Auto Flush After Disconnect Enable (AFADE) — R/W.

0 = The PCI bridge will retain any fetched data until required to discard by producer/

consumer rules.

1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-

asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI

transfer.

PCI-to-PCI Bridge Register s (D30:F0)

358 Intel ® ICH7 Family Datasheet

Never Prefetch (NP) — R/W.

0 = Prefetch ena bled

1 = The ICH7 will only fetc h a single DW and will not enable prefetching, regardless of

the command being an Memory read (MR), Memory read line (MRL), or Memory

read multiple (MRM).

Memory Read Multiple Prefetch Disable (MRMPD) — R/W.

0 = MRM commands will fetch multiple cache lines as defined by the prefetch

algorithm.

1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte

aligned cache line.

Memory Read Line Prefetch Disable (MRLPD) — R/W.

0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.

1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned

cache line.

0Memory Read Prefetch Disabl e (MRPD) — R/W.

0 = MR commands will fetch up to a 64-byte aligned cache line.

1 = Memory read (MR) commands will fetch only a single DW.

Bit Description

Intel ® ICH7 Family Datasheet 359

PCI-to-PCI Bridge Registers (D30:F0)

9.1.22 BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)

Offset Address: 48h–4Bh Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:17 Reserved

PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the

PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the

chipset is the agent driving PERR#. It remains asserted until cleared by software

writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the

Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and

be a source for the NMI logic.

This bit can be used by software to determine the source of a system problem.

15:7 Reserved

6:4

Number of Pending Transactions (NPT) — RO. This field indicates to debug

software how many transactions are in the pending queue. Possible values are:

000 = No pending transaction

001 = 1 pending transaction

010 = 2 pending transactions

011 = 3 pending transactions

100 = 4 pending transactions

101 = 5 pending transactions

110 - 111 = Reserved

NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than

‘00’.

3:2 Reserved

1:0

Number of Active Transactions (NAT) — RO. This field indicates to debug software

how many transactions are in the active queue. Possible values are:

00 = No active transaction s

01 = 1 active transaction

10 = 2 active transactions

11 = Reserved

PCI-to-PCI Bridge Register s (D30:F0)

360 Intel ® ICH7 Family Datasheet

9.1.23 BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)

Offset Address: 4Ch–4Fh Attribute: R/W, RO

Default Value: 00001200h Size: 32 bits

Bit Description

31:14 Reserved

13:8

Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number

of PCI clocks after internally enqueuing an upstream memory read request at which

point the PCI target logic should insert wait states in order to optimize lead-off latency.

When the master returns after this threshol d has been reached and data has not

arrived in the Delayed Transaction completion queue, then the PCI target lo gic will

insert wait states instead of immediately retrying the cycle. The PCI target logic will

insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or

STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived

yet).

Note that the starting event for this Read Latency Timer is not explicitly visible

externally.

A value of 0h disables this policy completely such that wait states will not be inserted

on the read lead-off data phase.

The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks

less than the typical idle lead-off latency expected for desktop Intel® ICH7 systems.

This value may need to be changed by BIOS, depending on the platform.

Subtractive Decode Policy (SDP) — R/W.

0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any

other device on the backbone (primary interface) to the PCI bus (secondary

interface).

1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the

corresponding Space Enable bit is set in the Command register.

NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI.

PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR#

Assertion status bit (in the Bridge Proprietary Status register) will result in an internal

SERR# assertion on the primary side of the bridge (if also enabled by the SERR#

Enable bit in the primary Command register). SERR# is a source of NMI.

Secondary Discard Timer Testmode (SDTT) — R/W.

0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E,

bit 9)

1 = The secondary discard timer will expire after 128 PCI clocks.

4:3 Reserved

Peer Decode Enable (PDE) — R/W.

0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O

cycles are not claimed.

1 = The PCI bridge will perform peer decode on an y memory or I/O cy cle from PCI that

falls outside of the memory and I/O window registers

1Reserved

0Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will

report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are

set, and CMD.SEE (D30:F0:04 bit 8) is set.

Intel ® ICH7 Family Datasheet 361

PCI-to-PCI Bridge Registers (D30:F0)

9.1.24 SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)

Offset Address: 50h–51h Attribute: RO

Default Value: 000Dh Size: 16 bits

9.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)

Offset Address: 54h–57h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

Bit Description

15:8 Next Capability (NEXT ) — RO. Value of 00h indicates this is the last item in the list.

7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem

vendor capability.

Bit Description

31:16 Subsystem Ident ifier (SID) — R/WO . This field in dicates the subsystem as id entified

by the vendor. This field is write once and is locked down until a bridge reset occurs

(not the PCI bus reset).

15:0 Subsystem Vendor Iden tifier (SVID) — R/WO. This field indicates the manufacturer

of the subsystem. This fi eld is wri te once an d is locked down until a bridge reset occurs

(not the PCI bus reset).

PCI-to-PCI Bridge Register s (D30:F0)

362 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 363

LPC Interface Bridge Registers (D31:F0)

10 LPC Interface Bridge Registers

(D31:F0)

The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. This function

contains many other functional units, such as DMA and Interrupt controllers, Timers,

Power Management, System Management, GPIO, RTC, and LPC Configuration

Registers.

Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.)

are described in their respective sections.

10.1 PCI Configuration Registers (LPC I/F—D31:F0)

Note: Address locations that are not shown should be treated as Reserved.

Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 0007h R/W, RO

06h–07h PCISTS PCI Status 0200h R/WC, RO

08h RID Revision Identification See register

description. RO

09h PI Programmi ng Int erface 00h RO

0Ah SCC Sub Class Code 01h RO

0Bh BCC Base Class Code 06h RO

0Dh PLT Primary Latency Timer 0 0h RO

0Eh HEADTYP Header Type 80h RO

2Ch–2Fh SS Sub System Identifiers 00000000h R/WO

34h CAPP Capability List Pointer E0h RO

40h–43h PMBASE ACPI Base Address 00000001h R/W, RO

44h ACPI_CNTL ACPI Control 00h R/W

48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO

4C GC GPIO Control 00h R/W

60h–63h PIRQ[n]_ROUT PIRQ[A–D] Ro uting Control

(Desktop and Mobile Only) 80h R/W

64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO

68h–6Bh PIRQ[n]_ROUT PIRQ[E–H] Routing Control 80h R/W

80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W

82h–83h LPC_EN LPC Interface Enables 0000h R/W

LPC Interface Bridge Registers (D31:F 0 )

364 Intel ® ICH7 Family Datasheet

10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16-bit

Lockable: No Power Well: Core

10.1.2 DID—Device Identification Register (LPC I/F—D31:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16-bit

Lockable: No Power Well: Core

84h–87h GEN1_DEC LPC Interface Generic Decode

Range 1 00000000h R/W

88h–8Bh GEN2_DEC LPC Interface Generic Decode

Range 2 00000000h R/W

8Ch–8Eh GEN3_DEC LPC Interface Generic Decode

Range 3 00000000h R/W

90h–93h GEN4_DEC LPC Interface Generic Decode

Range 4 00000000h R/W

A0h–CFh — Power Management (See

Section 10.8.1)——

D0h–D3h FWH_SEL1 Firmware Hub Select 1 00112233h R/W, RO

D4h–D5h FWH_SEL2 Firmware Hub Select 2 4567h R/W

D8h–D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 FFCFh R/W, RO

DCh BIOS_CNTL BIOS Control 00h R/WLO, R/W

E0h–E1h FDCAP Feature Detection Capability ID 0009h RO

E2h FDLEN Feature Detection Capability

Length 0Ch RO

E3h FDVER Feature Detection Version 10h RO

E4h–EBh FDVCT Feature Vector See

Description RO

F0h–F3h RCBA Root Complex Base Address 00000000h R/W

Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. Thi s is a 16-bit value assigned to the Intel ® ICH7 LPC bridge. Refer

to the Intel® I/O Controller Hub 7 (ICH7) Family Specificatio n Update for the value of

the Device ID Register.

Intel ® ICH7 Family Datasheet 365

LPC Interface Bridge Registers (D31:F0)

10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0007h Size: 16-bit

Lockable: No P ower Well: Core

10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)

Offset Address: 06–07h Attribute: RO, R/WC

Default Value: 0210h Size: 16-bit

Lockable: Noh Power Well: Core

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15:10 Reserved

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

Parity Error Response Enable (PERE) — R/W.

0 = No action is taken when detecting a parity error.

1 = Enables the Intel® ICH7 LPC bridge to respond to parity errors detected on

backbone interface.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.

1 Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.

0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.

Bit Description

Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity

error on the internal backbone. Set even if th e PCICMD.P ERE bit (D31:F0:04 , bit 6) is

0 = Parity Error Not detected.

1 = Parity Error detected.

14 Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system

error to the internal SERR# logic.

Master Abort Status (RM A) — R/WC.

0 = Unsupported request status not received.

1 = The bridge received a completion with unsupported request status from the

backbone.

12 Received Target Abort (RTA) — R/WC.

0 = Completion abort not received.

1 = Completion with completion abort received from the backbone.

LPC Interface Bridge Registers (D31:F 0 )

366 Intel ® ICH7 Family Datasheet

10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)

Offset Address: 09h Attribute: RO

Default Value: 00h Size: 8 bits

Signaled Target Abort (STA) — R/WC.

0 = Target abort Not generated on the backbone.

1 = LPC bridge generated a completion packet with target abort status on the

backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Medium Timing.

Data Parity Error Detected (DPED) — R/WC.

0 = All conditions list ed below Not met.

1 = Set when all three of the following conditions are met:

• LPC bridge receives a completion packet from the backbone from a previous request,

• Parity error has been detected (D31:F0:06, bit 15)

• PCICMD.PERE bit (D31:F0:04, bit 6) is set.

7Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal

backbone.

6 Reserved.

566 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on internal

backbone.

4 Capabilities List (CLIST) — RO. Capability list exis ts on the LPC bridge.

3 Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.

2:0 Reserved.

Bit Description

7:0 Revision ID (RID) — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family

Specification Update for the value of the Revision ID Register.

Bit Description

7:0 Programming Interface — RO.

Intel ® ICH7 Family Datasheet 367

LPC Interface Bridge Registers (D31:F0)

10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)

Offset Address: 0Bh Attribute: RO

Default Value: 06h Size: 8 bits

10.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)

Offset Address: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

10.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)

Offset Address: 0Eh Attribute: RO

Default Value: 80h Size: 8 bits

Bit Description

7:0 Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC

bridge.

01h = PCI-to-ISA bridge.

Bit Description

7:0 Base Class Code — RO. 8-bit value that indicates the type of device for the LPC

bridge.

06h = Bridge device.

Bit Description

7:3 Master Latency Count (MLC) — Reserved.

2:0 Reserved.

Bit Description

7 Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.

6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration

space.

LPC Interface Bridge Registers (D31:F 0 )

368 Intel ® ICH7 Family Datasheet

10.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)

Offset Address: 2Ch–2Fh Attribute: R/WO

Default Value: 00000000h Size: 32 bits

This register is initialized to logic 0 by the assertion of PLTRST#. This register can be

written only once after PLTRST# de-assertion.

10.1.12 CAPP—Capability List Pointer (LPC I/F—D31:F0)

Offset Address: 34h Attribute: RO

Default Value: E0h Size: 8 bits

Power Well: Core

10.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)

Offset Address: 40h–43h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These

registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.

Bit Description

31:16 Subsystem ID (SSID) — R/WO This is written b y BIOS . No hardw are actio n tak en on

this value.

15:0 Subsystem Vendor ID (SSVID) — R/WO This is written by BIOS. No hardware actio n

taken on this value.

Bit Description

7:0 Capability Pointer (CP) — RO. Indicates the offset of the first item.

Bit Description

31:16 R eserved

15:7 Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and

TCO logic. This is placed on a 128-byte boundary.

6:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.

Intel ® ICH7 Family Datasheet 369

LPC Interface Bridge Registers (D31:F0)

10.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)

Offset Address: 44h Attribute: R/W

Default Value: 00h Size: 8 bit

Lockable: No U sage: ACPI, Legacy

Power Well: Core

10.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F —

D31:F0)

Offset Address: 48h–4Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bit

Bit Description

ACPI Enable (ACPI_EN) — R/W.

0 = Disable.

1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the

ACPI power management function is enabled. Note that the APM power

management ranges (B2/B3h) are always enabled and are not affected by this bit.

6:3 Reserved

2:0

SCI IRQ Sele ct (SCI_IRQ_SEL) — R/W.

Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI

must be routed to IRQ9–11, and th at interrupt is no t shar able with the SERIRQ stream,

but is shareable with other PCI inte rrupts. If using the APIC, the SCI can also be

mapped to IRQ20–23, and can be shared with other interrupts.

NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be

programmed for active-high reception. When the interrupt is mapped to APIC

interrupts 20 through 23, the APIC should be programmed for active-low

Bits SCI Map

000b IRQ9

001b IRQ10

010b IRQ11

011b Reserved

100b IRQ20 (Only available if APIC enabled)

101b IRQ21 (Only available if APIC enabled)

110b IRQ22 (Only available if APIC enabled)

111b IRQ23 (Only available if APIC enabled)

Bit Description

31:16 Reserved. Always 0.

15:6 Base Address (BA) — R/W. Provides the 64 bytes of I/O space for GPIO.

5:1 Reserved. Always 0.

0 RO. Hardwired to 1 to indicate I/O space.

LPC Interface Bridge Registers (D31:F 0 )

370 Intel ® ICH7 Family Datasheet

10.1.16 GC—GPIO Control Register (LPC I/F — D31:F0)

Offset Address: 4Ch Attribute: R/W

Default Value: 00h Size: 8 bit

10.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) (Desktop and Mobile Only)

Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W

PIRQC – 62h, PIRQD – 63h

Default Value: 80h Size: 8 bit

Lockable: No Power Well: Core

Bit Description

7:5 Reserved.

GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed

to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.

0 = Disable.

1 = Enable.

3:0 Reserved.

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts

specified in bits[3:0].

1 = The PIRQ is not routed to the 8259.

NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are

being used. The value of this bit may subsequently be changed by the OS

when setting up for I/O APIC interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

Intel ® ICH7 Family Datasheet 371

LPC Interface Bridge Registers (D31:F0)

10.1.18 SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0)

Offset Address: 64h Attribute: R/W, RO

Default Value: 10h Size: 8 bit

Lockable: No P ower Well: Core

Bit Description

7Serial IRQ Enable (SIRQEN) — R/W.

0 = The buffer is input only and internally SERIRQ will be a 1.

1 = Serial IRQs wi ll be recognized. The SERIRQ pin will be configured as SERIRQ.

Serial IRQ Mode Select (SIRQMD) — R/W.

0 = The serial IRQ machine will be in quiet mode.

1 = The serial IRQ machine will be in continuous mode.

NOTE: F or sys tems u sing Q uiet Mode, thi s bit s hould be set to 1 (Con tin uous Mo de) for

at least one frame after coming out of reset before switching back to Quiet

Mode. Failure to do so will result in the Intel® ICH7 not recognizing SERIRQ

interrupts.

5:2 Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the

SERIRQ frame as 21 frames.

1:0

Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the

SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In

continuous mode, the ICH7 will drive the start fr ame for the number of cloc ks specifie d.

In quiet mode, th e ICH7 will drive the start frame for the number of clocks specified

minus one, as the first clock was driven by the peripheral.

00 = 4 clocks

01 = 6 clocks

10 = 8 clocks

11 = Reserved

LPC Interface Bridge Registers (D31:F 0 )

372 Intel ® ICH7 Family Datasheet

10.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)

Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W

PIRQG – 6Ah, PIRQH – 6Bh

Default Value: 80h Size: 8 bit

Lockable: No Power Well: Core

Bit Description

Interrupt Routing Enable (IRQEN) — R/W.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified

in bits[3:0].

1 = The PIRQ is not routed to the 8259.

NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are

being used. The value of this bit may subsequently be changed by the OS when

setting up for I/O APIC interrupt delivery mode.

6:4 Reserved

3:0

IRQ Routing — R/W. (ISA compatible.)

Value IRQ Value IRQ

0000b Reserved 1000b Reserved

0001b Reserved 1001b IRQ9

0010b Reserved 1010b IRQ10

0011b IRQ3 1011b IRQ11

0100b IRQ4 1100b IRQ12

0101b IRQ5 1101b Reserved

0110b IRQ6 1110b IRQ14

0111b IRQ7 1111b IRQ15

Intel ® ICH7 Family Datasheet 373

LPC Interface Bridge Registers (D31:F0)

10.1.20 LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0)

Offset Address: 80h Attribute: R/W

Default Value: 0000h Size: 16 bit

Bit Description

15:13 Reserved

12 FDD Decode Range — R/W. Determines which range to decode for the FDD Port

0 = 3F0h – 3F5h, 3F7h (Primary)

1 = 370h – 375h, 377h (Secondary)

11:10 Reserved

9:8

LPT Decode Range — R/W. This field determines which range to decode for the LPT

Port.

00 = 378h – 37Fh and 778h – 77Fh

01 = 278h – 27Fh (port 279h is read only) and 678h – 67Fh

10 = 3BCh –3BEh and 7BCh – 7BEh

11 = Reserved

7Reserved

6:4

COMB Decode Rang e — R/W. This field determines which range to decode for the

COMB Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

3Reserved

2:0

COMA Decode Range — R/W. This field determines which range to decode for the

COMA Port.

000 = 3F8h – 3FFh (COM1)

001 = 2F8h – 2FFh (COM2)

010 = 220h – 227h

011 = 228h – 22Fh

100 = 238h – 23Fh

101 = 2E8h – 2EFh (COM4)

110 = 338h – 33Fh

111 = 3E8h – 3EFh (COM3)

LPC Interface Bridge Registers (D31:F 0 )

374 Intel ® ICH7 Family Datasheet

10.1.21 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)

Offset Address: 82h – 83h Attribute: R/W

Default Value: 0000h Size: 16 bit

Power Well: Core

Bit Description

15:14 Reserved

CNF2_LPC_EN — R/W. Microcontroller Enable # 2.

0 = Disable.

1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This

range is used for a microcontroller.

CNF1_LPC_EN — R/W. Super I/O Enable.

0 = Disable.

1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This

range is used for Super I/O devices.

MC_LPC_EN — R/W. Microcontroller Enable # 1.

0 = Disable.

1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This

range is used for a microcontroller.

KBC_LPC_EN — R/W. Keyboard Enable.

0 = Disable.

1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This

range is used for a microcontroller.

GAMEH_LPC_EN — R/W. High Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This

range is used for a gameport.

GAMEL_LPC_EN — R/W. Low Gameport Enable

0 = Disable.

1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This

range is used for a gameport.

7:4 Reserved

FDD_LPC_EN — R/W. Floppy Drive Enable

0 = Disable.

1 = Enables the decoding of the FDD range to th e LPC interface. This ran ge is select ed

in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).

LPT_LPC_EN — R/W. Parallel Port Enable

0 = Disable.

1 = Enables the decoding of the LPT r ange to the LPC interface. Thi s range is selected in

the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).

COMB_LPC_EN — R/W. Com Port B Enable

0 = Disable.

1 = Enables the decoding of the COMB range to the LPC interface. This range is

selected in the LPC_COM Decode Range Register (D31:F0:80h, bit s 6:4) .

COMA_LPC_EN — R/W. Com Port A Enable

0 = Disable.

1 = Enables the decoding of the COMA range to the LPC interface. This range is

selected in the LPC_COM Decode Range Register (D31:F0:80h, bit s 3:2) .

Intel ® ICH7 Family Datasheet 375

LPC Interface Bridge Registers (D31:F0)

10.1.22 GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0)

Offset Address: 84h – 87h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

10.1.23 GEN2_DEC—LPC I/F Generic Decode Range 2Register

(LPC I/F—D31:F0)

Offset Address: 88h – 8Bh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2

Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is

aligned on a 128-byte boundary, and must have address lines 31:16 as 0.

NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.

1Reserved

0Generic Decode Range 1 Enable (GEN1_EN) — R/W.

0 = Disable.

1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.

NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.

1Reserved

0Generic Decode Range 2Enable (GEN2_EN) — R/W.

0 = Disable.

1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F

LPC Interface Bridge Registers (D31:F 0 )

376 Intel ® ICH7 Family Datasheet

10.1.24 GEN3_DEC—LPC I/F Generic Decode Range 3Register

(LPC I/F—D31:F0)

Offset Address: 8Ch – 8Eh Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

10.1.25 GEN4_DEC—LPC I/F Generic Decode Range 4Register

(LPC I/F—D31:F0)

Offset Address: 90h – 93h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 3Base Ad dress (GEN3_BASE) — R/W.

NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.

1 Reserved

0Generic Decode Range 3Enable (GEN3_EN) — R/W.

0 = Disable.

1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F

Bit Description

31:24 Reserved

23:18

Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates

that any value in the corresponding address bit in a received cycle will be treated as a

match. The corresponding bit in the Address field, below, is ignored. The mask is only

provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to

256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 4Base Ad dress (GEN4_BASE) — R/W.

NOTE: The Intel® ICH7 does not provide decode down to the word or byte level.

1 Reserved

0Generic Decode Range 4Enable (GEN4_EN) — R/W.

0 = Disable.

1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F

Intel ® ICH7 Family Datasheet 377

LPC Interface Bridge Registers (D31:F0)

10.1.26 FWH_SEL1—Firmware Hub Select 1 Register

(LPC I/F—D31:F0)

Offset Address: D0h–D3h A ttribute: R/W, RO

Default Value: 00112233h Size: 32 bits

Bit Description

31:28

FWH_F8_IDSEL — RO. IDSEL for two 512-KB Firmware Hub memory ranges and one

128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field

addresses the following memory ranges:

FFF8 0000h – FFFF FFFFh

FFB8 0000h – FFBF FFFFh

000E 0000h – 000F FFFFh

27:24

FWH_F0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFF0 0000h – FFF7 FFFFh

FFB0 0000h – FFB7 FFFFh

23:20

FWH_E8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFE8 0000h – FFEF FFFFh

FFA8 0000h – FFAF FFFFh

19:16

FWH_E0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFE0 0000h – FFE7 FFFFh

FFA0 0000h – FFA7 FFFFh

15:12

FWH_D8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFD8 0000h – FFDF FFFFh

FF98 0000h – FF9F FFFFh

11:8

FWH_D0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFD0 0000h – FFD7 FFFFh

FF90 0000h – FF97 FFFFh

7:4

FWH_C8_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFC8 0000h – FFCF FFFFh

FF88 0000h – FF8F FFFFh

3:0

FWH_C0_IDSEL — R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The

IDSEL programmed in this field addresse s th e fo llo win g memory ranges:

FFC0 0000h – FFC7 FFFFh

FF80 0000h – FF87 FFFFh

LPC Interface Bridge Registers (D31:F 0 )

378 Intel ® ICH7 Family Datasheet

10.1.27 FWH_SEL2—Firmware Hub Select 2 Register

(LPC I/F—D31:F0)

Offset Address: D4h–D5h Attribute: R/W

Default Value: 4567h Size: 16 bits

10.1.28 FWH_DEC_EN1—Firmware Hub Decode E n able Register

(LPC I/F—D31:F0)

Offset Address: D8h–D9h Attribute: R/W, RO

Default Value: FFCFh Size: 16 bits

Bit Description

15:12

FWH_70_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF70 0000h – FF7F FFFFh

FF30 0000h – FF3F FFFFh

11:8

FWH_60_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF60 0000h – FF6F FFFFh

FF20 0000h – FF2F FFFFh

7:4

FWH_50_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF50 0000h – FF5F FFFFh

FF10 0000h – FF1F FFFFh

3:0

FWH_40_IDSEL — R/W. IDSEL for two, 1-M Firmware Hub memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF40 0000h – FF4F FFFFh

FF00 0000h – FF0F FFFFh

Bit Description

FWH_F8_EN — RO. This bit enables decoding two 512-KB Firmware Hub memory

ranges, and one

128-KB memory range.

0 = Disable

1 = Enable the following ranges for the Firmware Hub

FFF80000h – FFFFFFFFh

FFB80000h – FFBFFFFFh

FWH_F0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFF00000h – FFF7FFFFh

FFB00000h – FFB7FFFFh

FWH_E8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFE80000h – FFEFFFFh

FFA80000h – FFAFFFFFh

Intel ® ICH7 Family Datasheet 379

LPC Interface Bridge Registers (D31:F0)

FWH_E0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub:

FFE00000h – FFE7FFFFh

FFA00000h – FFA7FFFFh

FWH_D8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFD80000h – FFDFFFFFh

FF980000h – FF9FFFFFh

FWH_D0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFD00000h – FFD7FFFFh

FF900000h – FF97FFFFh

FWH_C8_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFC80000h – FFCFFFFFh

FF880000h – FF8FFFFFh

FWH_C0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory

ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FFC00000h – FFC7FFFFh

FF800000h – FF87FFFFh

FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at

F0000h – FFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the Firmware Hub

F0000h – FFFFFh

FWH_Legacy_E_EN — R/W. This enables the decoding of the legacy 128-K range at

E0000h – EFFFFh.

0 = Disable.

1 = Enable the following legacy ranges for the Firmware Hub

E0000h – EFFFFh

5:4 Reserved

FWH_70_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF70 0000h – FF7F FFFFh

FF30 0000h – FF3F FFFFh

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

380 Intel ® ICH7 Family Datasheet

Note: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC

or SPI (Desktop and Mobile Only). The concept of Feature Space does not apply to SPI-

based flash. The ICH7simply decodes these ranges as memory accesses when enabled

for the SPI flash interface.

FWH_60_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF60 0000h – FF6F FFFFh

FF20 0000h – FF2F FFFFh

FWH_50_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF50 0000h – FF5F FFFFh

FF10 0000h – FF1F FFFFh

FWH_40_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.

0 = Disable.

1 = Enable the following ranges for the Firmware Hub

FF40 0000h – FF4F FFFFh

FF00 0000h – FF0F FFFFh

Bit Description

Intel ® ICH7 Family Datasheet 381

LPC Interface Bridge Registers (D31:F0)

10.1.29 BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0)

Offset Address: DCh Attribute: R/WLO, R/W, RO

Default Value: 00h Size: 8 bit

Lockable: No P ower Well: Core

Bit Description

7:5 Reserved

4Top Swap Status (TSS)— RO: This bit provides a read-only path to view the

state of the Top Swap bit that is at offset 3414h, bit 0.

3:2

(Desktop

and Mobile

Only)

SPI Read Configuration (SRC)— R/W: This 2-bit field controls two policies

related to BIOS reads on the SPI interface:

Bit 3- Prefetch Enabl e

Bit 2- Cache Disabl e

Settings are summarized below:

3:2

(Ultra

Mobile

Only)

Reserved

BIOS Lock Enable (BLE) — R/WLO.

0 = Setting the BIOSWE will not cause SMIs.

1 = Enable s setting the BIOSWE bit to cause S M Is. Once set, th is bit can only be

cleared by a PLTRST#

BIOS Write Enable (BIOSWE) — R/W.

0 = Only read cycles permitted to Firmware Hub or SPI flash.

1 = Access to the BIOS sp ace is en abled for both read and write cycl es. Wh en this

bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI#

is generated. This ensures that only SMI code can update BIOS.

NOTE: Writes to the Firmware Hub’s Feature Space are not blocked when the

BIOSWE is cleared in order to all ow access to regist ers. The F eatu re Space

is the second range that is located 4 MB below the BIOS range for each

Firmware Hub.

Bits 3:2 Description

00b No prefetching, but caching enabled. 64B demand reads

load the read buffer cache with “valid” data, allowing repeated

code fetches to the same line to co mplete quickly

01b No prefetching and no caching. One-to-one correspondence

of host BIOS reads to SPI cycles. This value can be used to

invalidate the cache.

10b Prefetchin g and Caching en abled. This mode is used for long

sequences of short reads to consecutive address es (i.e.,

shadowing).

11b Reserved. This is an invalid configuration, caching must be

enabled when prefetch ing is enabled.

LPC Interface Bridge Registers (D31:F 0 )

382 Intel ® ICH7 Family Datasheet

10.1.30 FDCAP—Feature Detection Capability ID

(LPC I/F—D31:F0)

Offset Address: E0h-E1h Attribute: RO

Default Value: 0009h Size: 16 bit

Power Well: Core

10.1.31 FDLEN—Feature Detection Capability Length

(LPC I/F—D31:F0)

Offset Address: E2h Attribute: RO

Default Value: 0Ch Size: 8 bit

Power Well: Core

10.1.32 FDVER—Feature Detection Version

(LPC I/F—D31:F0)

Offset Address: E3h Attribute: RO

Default Value: 10h Size: 8 bit

Power Well: Core

Bit Description

15:8 Next Item Pointer (NEXT): Configuration offset of the next Capability Item. 00h

indicates t h e last item in the Capability List.

7:0 Capability ID: Indicates a Vendor Specific Capability

Bit Description

7:0 Capability Length: Indicates the length of this Vendor Specific capability , as required by

PCI Spec.

Bit Description

7:4 Vendor-Specific Capability ID: A value of 1h in this 4-bit field identifies this Capability

as Feature Detection Type. This field allows software to differentiate the Feature

Detection Capability from other Vendor-Specific capabilities

3:0 Capability Version: This field indicates the version of the Feature Detection capability

Intel ® ICH7 Family Datasheet 383

LPC Interface Bridge Registers (D31:F0)

10.1.33 FDVCT—Feature Vector Register (LPC I/F—D31:F0)

Offset Address: E4h–EBh Attribute: RO

Default Value: See Description Size: 64 bit

Power Well: Core

Bit Description

63:33 Reserved

(Desktop

and Mobile

Only)

Intel® Active Management Technology Capability— RO:

0 = Capable

1 = Disabled

(Ultra

Mobile

Only)

Reserved

31:22 Reserved

(Desktop

Only)

Intel® ICH7DH Only:

Intel® Quick Resume Technology Capability— RO:

0 = Capable

1 = Disabled

ICH7 and ICH7R Only:

Reserved

(Mobile/

Ultra Mobile

Only)

Reserved.

20:19 Reserved

(Desktop

and Mobile

Only)

SATA RAID 5 Capability— RO:

0 = Capable

1 = Disabled

(Ultra

Mobile) Reserved

17:10 Reserved

(Mobile/

Utlra Mobile

Only)

Mobile Features Capability— RO:

0 = Disabled

1 = Capable

(Desktop

Only) Reserved

8 Reserved

(Desktop

and Mobile

Only)

PCI Express* 6 x1 Capability— RO:

0 = Capable

1 = Disabled - 4 PCI Express x1 Ports available

LPC Interface Bridge Registers (D31:F 0 )

384 Intel ® ICH7 Family Datasheet

10.1.34 RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)

Offset Address: F0h Attribute: R/W

Default Value: 00000000h Size: 32 bit

(Ultra

Mobile

Only)

Reserved

6 Reserved

(Desktop

and Mobile

Only)

SATA RAID 0/1/10 Capability— RO:

0 = Capable

1 = Disabled

(Ultra

Mobile

Only)

Reserved

4 Reserved

(Desktop

and Mobile

Only)

SATA AHCI Capability— RO:

0 = Capable

1 = Disabled

(Ultra

Mobile

Only)

Reserved

2:0 Reserved

Bit Description

31:14 Base Address (BA) — R/W. Base Address for the root complex register block decode

range. This address is aligned on a 16-KB boundary.

13:1 Reserved

0Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed

as the Root Complex Register Block.

Intel ® ICH7 Family Datasheet 385

LPC Interface Bridge Registers (D31:F0)

10.2 DMA I/O Registers (LPC I/F—D31:F0)

Table 10-2. DMA Registers (Sheet 1 of 2)

Port Alias Register Name Default Type

00h 10h Channel 0 DMA Base & Current Address Undefined R/W

01h 11h Channel 0 DMA Base & Current Count Undefined R/W

02h 12h Channel 1 DMA Base & Current Address Undefined R/W

03h 13h Channel 1 DMA Base & Current Count Undefined R/W

04h 14h Channel 2 DMA Base & Current Address Undefined R/W

05h 15h Channel 2 DMA Base & Current Count Undefined R/W

06h 16h Channel 3 DMA Base & Current Address Undefined R/W

07h 17h Channel 3 DMA Base & Current Count Undefined R/W

08h 18h Channel 0–3 DMA Command Undefined WO

Channel 0–3 DMA Status Undefined RO

0Ah 1Ah Channel 0–3 DM A Write Single Mask 000001XXb WO

0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO

0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO

0Dh 1Dh Channel 0–3 DM A Master Clear Undefined WO

0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO

0Fh 1Fh Channel 0–3 DM A Write All Mask 0Fh R/W

80h 90h Reserved Page Undefined R/W

81h 91h Channel 2 DMA Memory Low Page Undefined R/W

82h — Channel 3 DMA Memory Low Page Undefined R/W

83h 93h Channel 1 DMA Memory Low Page Undefined R/W

84h–86h 94h–96h Reserved Pa ges Undefined R/W

87h 97h Channel 0 DMA Memory Low Page Undefined R/W

88h 98h Reserved Page Undefined R/W

89h 99h Channel 6 DMA Memory Low Page Undefined R/W

8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W

8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W

8Ch–8Eh 9Ch–9Eh Reserved Page Undefined R/W

8Fh 9Fh Refresh Low Page Undefined R/W

C0h C1h Channel 4 DMA Base & Current Address Undefined R/W

C2h C3h Channel 4 DMA Base & Current Count Undefined R/W

C4h C5h Channel 5 DMA Base & Current Address Undefined R/W

C6h C7h Channel 5 DMA Base & Current Count Undefined R/W

C8h C9h Channel 6 DMA Base & Current Address Undefined R/W

CAh CBh Channel 6 DMA Base & Current Count Undefined R/W

CCh CDh Channel 7 DMA Base & Current Address Undefined R/W

LPC Interface Bridge Registers (D31:F 0 )

386 Intel ® ICH7 Family Datasheet

10.2.1 DMABASE_CA—DMA Base and Current Address

Registers (LPC I/F—D31:F0)

I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W

Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bit (per channel),

Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit

Ch. #7 = CCh; quantities

Default Value: Undef

Lockable: No Power Well: Core

CEh CFh Channel 7 DMA Base & Current Count Undefined R/W

D0h D1h Channel 4–7 DMA Command Undefined WO

Channel 4–7 DMA Status Undefined RO

D4h D5h Channel 4–7 DMA Write Single Mask 000001XXb WO

D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO

D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO

DAh DBh Channel 4–7 DMA Master Clear Undefined WO

DCh DDh Channel 4–7 DMA Clear Mask Undefined WO

DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W

Table 10-2. DMA Registers (Sheet 2 of 2)

Port Alias Register Name Default Type

Bit Description

15:0

Base and Current Address — R/W. This register determines the address for the

transfers to be performed. The address specified points to two separate registers. On

writes, the value is stored in the Base Address register and copied to the Current

Address register. On reads, the value is returned from the Current Address register.

The address increments/decrements in the Current Address register after each transfer,

depending on the mode of the transfer. If the channel is in auto-initialize mode, the

Current Address register will be reloaded from the Base Address register after a

terminal count is generated.

For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit

location. Bit 15 will be shifted into Bit 16.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte

pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should

be cleared to ensure that the low byte is accessed first.

Intel ® ICH7 Family Datasheet 387

LPC Interface Bridge Registers (D31:F0)

10.2.2 DMABASE_CC—DMA Base and Current Count Registers

(LPC I/F—D31:F0)

I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W

Ch. #2 = 05h; Ch. #3 = 07h Size: 16-bit (per channel),

Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit

Ch. #7 = CEh; quantities

Default Value: Undefined

Lockable: No Power Well: Core

10.2.3 DMAMEM_LP—DMA Memory Low Page Registers

(LPC I/F—D31:F0)

I/O Address: Ch. #0 = 87h; Ch. #1 = 83h

Ch. #2 = 81h; Ch. #3 = 82h

Ch. #5 = 8Bh; Ch. #6 = 89h

Ch. #7 = 8Ah; Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No P ower Well: Core

Bit Description

15:0

Base and Current Count — R/W. This register determines the number of transfers to

be performed. The address specified points to two separate registers. On writes, the

value is stored in the Base Count register and copied to the Current Count register. On

reads, the value is returned from the Current Count register.

The actual number of transfers is one more than the number programmed in the Base

Count Register (i.e., programming a c ount of 4h results in 5 transfers). The count is

decrements in the Current Count register after each transfer. When the value in the

initialize mode, the Current Count register will be reloaded from the Base Count

For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the

number of bytes to be tr ansferred. For tr an sfers to/fro m a 16-bit sl ave ( channels 5–7),

the count register indicates the number of words to be transferred.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte

pointer flip/flop. Before accessing a count register, the byte point er flip/flop should be

cleared to ensure that the low byte is accessed first.

Bit Description

7:0

DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction

with the DMA controller's Current Address Register to define the complete 24-bit

address for the DMA channel. This register remains static throughout the DMA transfer.

Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is

replaced by the bit 15 shifted out from the current address register.

LPC Interface Bridge Registers (D31:F 0 )

388 Intel ® ICH7 Family Datasheet

10.2.4 DMACMD—DMA Command Re gister (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: WO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

10.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 08h;

Ch. #4–7 = D0h Attribute: RO

Default Value: Undefined Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:5 Reserved. Must be 0.

DMA Group Arbitration Priority — WO. Each channel group is individually assign ed

either fixed or rotating arbitration priority. At part reset, each group is initialized in

fixed priority.

0 = Fixed prior ity to the channel group

1 = Rotating priority to the group.

3 Reserved. Must be 0.

DMA Channel Group Enable — WO. Both channel groups are enabled following part

reset.

0 = Enable the DMA channel group.

1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, wh ich is

cascaded through channel 4.

1:0 Reserved. Must be 0.

Bit Description

7:4

Channel Request Status — RO. When a valid DMA request is pending for a channel,

the corresponding bit is set to 1. When a DMA request is not pending for a particular

channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or

a software request. Note that channel 4 is the cascade channel, so the request status of

channel 4 is a logical OR of the request status for channels 0 through 3.

4 = Channel 0

5 = Channel 1 (5)

6 = Channel 2 (6)

7 = Channel 3 (7)

3:0

Channel Terminal Count S tatus — RO. When a channel reaches terminal count (T C),

its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4

is programmed for cascade, so the TC bit response for channel 4 is irrelevant:

0 = Channel 0

1 = Channel 1 (5)

2 = Channel 2 (6)

3 = Channel 3 (7)

Intel ® ICH7 Family Datasheet 389

LPC Interface Bridge Registers (D31:F0)

10.2.6 DMA_WRSMSK—DMA Write Single Mask Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Ah;

Ch. #4–7 = D4h Attribute: WO

Default Value: 0000 01xx Size: 8-bit

Lockable: No P ower Well: Core

Bit Description

7:3 Reserved. Must be 0.

Channel Mask Select — WO.

0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].

Therefore, only one channel can be masked / unmasked at a time.

1 = Disable DREQ for the selected channel.

1:0

DMA Channel Select — W O. These bits select the DMA Channel Mode Register to

program.

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

LPC Interface Bridge Registers (D31:F 0 )

390 Intel ® ICH7 Family Datasheet

10.2.7 DMACH_MODE—DMA Channel Mode Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Bh;

Ch. #4–7 = D6h Attribute: WO

Default Value: 0000 00xx Size: 8-bit

Lockable: No Power Well: Core

Bit Description

7:6

DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four

different modes:

00 = Demand mode

01 = Single mode

10 = Reserved

11 = Cascade mode

Address Increment/Decrement Select — WO. This bit controls address increment/

decrement during DMA transfers.

0 = Address increment. (default after part reset or Master Clear)

1 = Address decrement.

Autoinitialize Enable — WO.

0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.

A part reset or Master Clear disables autoinitialization.

1 = DMA restores the Base Ad dress and Count registers to the current registers

following a terminal count (TC).

3:2

DMA Transfer Type — WO. These bits represent the direction of the DMA transfer.

When the channel is programmed for cascade mode, (bits[7: 6] = 11) the tr ansfe r type

is irrelevant.

00 = Verify – No I/O or memory strobes generated

01 = Write – Data transferred from the I/O devices to memory

10 = Read – Data transferred from memory to the I/O device

11 = Invalid

1:0

DMA Channel Select — W O. These bits select the DMA Channel Mode Register that

will be written by bits [7:2].

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

Intel ® ICH7 Family Datasheet 391

LPC Interface Bridge Registers (D31:F0)

10.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Ch;

Ch. #4–7 = D8h Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No P ower Well: Core

10.2.9 DMA Master Clear Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Dh;

Ch. #4–7 = DAh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

10.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Eh;

Ch. #4–7 = DCh Attribute: WO

Default Value: xxxx xxxx Size: 8-bit

Lockable: No P ower Well: Core

Bit Description

7:0

Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the

I/O port address. Writing to this register i nitiali zes the byt e pointer fl ip/flop t o a known

state. It clears the internal latch used to address the upper or lower byte of the 16-bit

Address and Word Count Registers. The latch is also cleared by part reset and by the

Master Clear command. This command precedes the first access to a 16-bit DMA

controller register. The first access to a 16-bit regist er will then access the significant

byte, and the second access automatically accesses the most significant byte.

Bit Description

7:0 Master Clear — WO. No specific patter n. Enabled with a write to the port. Th is has the

same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer

flip/flop registers are cleared and the Mask Register is set.

Bit Description

7:0 Clear Mask Register — WO. No specific pattern. Command enabled with a write to the

port.

LPC Interface Bridge Registers (D31:F 0 )

392 Intel ® ICH7 Family Datasheet

10.2.11 DMA_WRMSK—DMA Write All Mask Register

(LPC I/F—D31:F0)

I/O Address: Ch. #0–3 = 0Fh;

Ch. #4–7 = DEh Attrib ute: R/W

Default Value: 0000 1111 Size: 8-bit

Lockable: No Power Well: Core

10.3 Timer I/O Registers (LPC I/F—D31:F0)

Bit Description

7:4 Reserved. Must be 0.

3:0

Channel Mask Bits — R/W. This register permits all four channels to be

simultaneously enabled/disabled instead of enabling/disabling each channel

individually, as is the cas e with the Mask Register – Write Single Mask Bit. In addition,

this register has a read path to allow the status of the channel mask bits to be read. A

channel's mask bi t is automatically set to 1 when the Current Byte/W ord Count R egister

reaches terminal count (unless the channel is in auto-initialization mode).

Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0

enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master

Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.

Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked

Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked

Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked

Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked

NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channel’s

0 – 3 through channel 4.

Port Aliases Register Name Default Value Type

40h 50h Counter 0 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 0 Counter Access Port Undefined R/W

41h 51h Counter 1 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 1 Counter Access Port Undefined R/W

42h 52h Counter 2 Interval Time Status Byte

Format 0XXXXXXXb RO

Counter 2 Counter Access Port Undefined R/W

43h 53h

Timer Control Word Undefined WO

Timer Control Word Register XXXXXXX0b WO

Counter Latch Command X0h WO

Intel ® ICH7 Family Datasheet 393

LPC Interface Bridge Registers (D31:F0)

10.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0)

I/O Address: 43h Attribute: WO

Default Value: All bits undefined Size: 8 bits

This register is programmed prior to any counter being accessed to specify counter

modes. Following part reset, the control words for each register are undefined and each

counter output is 0. Each timer must be programmed to bring it into a known state.

There are two special commands that can be issued to the counters through this

commands are chosen, several bits within this register are redefined. These register

formats are described below:

RDBK_CMD—Read Back Command (LPC I/F—D31:F0)

The Read Back Command is used to determine the count value, programmed mode,

and current states of the OUT pin and Null count flag of the selected counter or

counters. Status and/or count may be latched in an y or all o f the counters by selecting

the counter during the register write. The count and status remain latched until read,

and further latch commands are ignored until the count is read. Both count and status

of the selected counters may be latched simultaneously by setting both bit 5 and bit 4

Bit Description

7:6

Counter Select — WO. The Counter Selection bits select the counter the control word

acts upon as shown below. The Read Back Command is selected when bits[7:6] are

both 1.

00 = Counter 0 select

01 = Counter 1 select

10 = Counter 2 select

11 = Read Back Command

5:4

Read/Write Select — WO. These bits are the read/write control bits. The actual

counter programming is done through the counter port (40h for counter 0, 41h for

counter 1, and 42h for counter 2).

00 = Counter Latch Co mmand

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Counter Mode Selection — WO. These bits select one of six possible modes of

operation for the selected counter.

0Binary/BCD Countdown Select — WO.

0 = Binary countdown is used. The largest possible binary count is 216

1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104

t Va

ue Mo

000b Mode 0 Out signal on end of count (=0)

001b Mode 1 Hardware retriggerable one-

shot

x10b Mode 2 Rate generator (divide by n

counter)

x11b Mode 3 Square wave output

100b Mode 4 Software triggered strobe

101b Mode 5 Hardware triggered strobe

LPC Interface Bridge Registers (D31:F 0 )

394 Intel ® ICH7 Family Datasheet

to 0. If both are latched, the first read operation from that counter returns the latched

status. The next one or two reads, depending on whether the counter is programmed

for one or two byte counts, returns the latched count. Subsequent reads return an

unlatched count.

LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0)

The Counter Latch Command latches the current cou nt v alue. This command is used to

insure that the count read from the counter is accurate. The count value is then read

from each counter's count register through the Counter Ports Access Ports Register

(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read

according to the programmed format, i.e., if the counter is programmed for two byte

counts, two bytes must be read. The two bytes do not have to be read one right after

the other (read, write, or programming operations for other counters may be inserted

between the reads). If a counter is latched once and then latched again before the

count is read, the second Counter Latch Command is ignored.

Bit Description

7:6 Read Back Command. Must be 11 to select the Read Back Command

5Latch Count of Selected Counters.

0 = Current count value of the selected counters will be latched

1 = Current count will not be latched

4Latch Status of Selected Counters.

0 = Status of the sele cted counters will be latched

1 = Status will not be latched

3Counter 2 Select.

1 = Counter 2 count and/or status will be latched

2Counter 1 Select.

1 = Counter 1 count and/or status will be latched

1Counter 0 Select.

1 = Counter 0 count and/or status will be latched.

0 Reserved. Must be 0.

Bit Description

7:6

Counter Selection. These bits select the counter for latching. If “11” is written, then

the write is interpreted as a read back command.

00 = Counter 0

01 = Counter 1

10 = Counter 2

5:4 Counter Latch Command.

00 = Selects the Counter Latch Command.

3:0 Reserved. Must be 0.

Intel ® ICH7 Family Datasheet 395

LPC Interface Bridge Registers (D31:F0)

10.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register

(LPC I/F—D31:F0)

I/O Address: Counter 0 = 40h,

Counter 1 = 41h, Attribute: RO

Counter 2 = 42h Size: 8 bits per counter

Default Value: Bits[6:0] undefined, Bit 7=0

Each counter's status byte can be read following a Re ad Back Command. If latch status

is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the

next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for

counter 1, and 42h for counter 2) returns the status byte. The status byte returns the

following:

Bit Description

7Counter OUT Pin State — RO.

0 = OUT pin of the counter is also a 0

1 = OUT pin of the counter is also a 1

Count Register Status — RO. This bit indicates when the last count written to the

Count Register (CR) has been loaded into the counting element (CE). The exact time

this happens depends on the counter mode, but unti l the count is loaded into the

counting elemen t (CE), the count value will be incorrect.

0 = Count has been transferred from CR to CE and is available for reading.

1 = Null Count. Count has not been transferred from CR to CE and is not yet available

for reading.

5:4

Read/Write Selection Status — RO. These bits reflect the read/wri te selection made

through bits[5:4] of the control register. The binary codes returned during the status

read match the co des used to program the counter read/write selection.

00 = Counter Latch Co mmand

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

3:1

Mode Selection Status — RO. These bits return the counter mode programming. The

binary code returned matches the code used to program the counter mode, as listed

under the bit function above.

000 = Mode 0 — Out signal on end of count (=0)

001 = Mode 1 — Hardware retriggerable one-shot

x10 = Mode 2 — Rate generator (divide by n counter)

x11 = Mode 3 — Square wave output

100 = Mode 4 — Software triggered strobe

101 = Mode 5 — Hardware triggered strobe

0Countdown Type Status — RO. This bit reflects the current countdown type.

0 = Binary countdown

1 = Binary Coded Decimal (BCD) countdown.

LPC Interface Bridge Registers (D31:F 0 )

396 Intel ® ICH7 Family Datasheet

10.3.3 Counter Access Ports Register (LPC I/F—D31:F0)

I/O Address: Counter 0 – 40h,

Counter 1 – 41h, Attribute: R/W

Counter 2 – 42h

Default Value: All bits undefined Size: 8 bit

10.4 8259 Interrupt Controller (PIC) Registers

(LPC I/F—D31:F0)

10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)

The interrupt controller registers are located at 20h and 21h for the master controller

(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers

have multiple functions, depending upon the data written to them. Table 10-3 shows

the different register possibilities for each address.

Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers

section (Chapter 5.9).

Bit Description

7:0

Counter Port — R/W. Each counter port address is used to program the 16-bit Count

defined with the Interval Counter Control R e gister at port 43h. The counter port i s also

used to read the current count from the Count Register, and return the status of the

counter programming following a Read Back Command.

Table 10-3. PIC Registers (LPC I/F—D31:F0)

Port Aliases Register Name Default

Value Type

20h 24h, 28h,

2Ch, 30h,

34h, 38h, 3Ch

Master PIC ICW1 Init. Cmd Word 1 Undefined WO

Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

21h

25h, 29h,

2Dh, 31h,

35h, 39h,

3Dh

Master PIC ICW2 Init. Cmd Word 2 Undefined WO

Master PIC ICW3 Init. Cmd Word 3 Undefined WO

Master PIC ICW4 Init. Cmd Word 4 01h WO

Master PIC OCW1 Op Ctrl Word 1 00h R/W

A0h

A4h, A8h,

ACh, B0h,

B4h, B8h,

BCh

Slave PIC ICW1 Init. Cmd Word 1 Undefined WO

Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO

Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO

A1h

A5h, A9h,

ADh, B1h,

B5h, B9h,

BDh

Slave PIC ICW2 Init. Cmd Word 2 Undefined WO

Slave PIC ICW3 Init. Cmd Word 3 Undefined WO

Slave PIC ICW4 Init. Cmd Word 4 01h WO

Slave PIC OCW1 Op Ctrl Word 1 00h R/W

4D0h – Master PIC Edge/Level Triggered 00h R/W

4D1h – Slave PIC Edge/Level Triggered 00h R/W

Intel ® ICH7 Family Datasheet 397

LPC Interface Bridge Registers (D31:F0)

10.4.2 ICW1—Initialization Command Word 1 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 20h Attribute: WO

Slave Controller

– A0h Size: 8 bit /controller

Default Value: All bits undefined

A write to Initialization Command Word 1 starts the interrupt controller initialization

sequence, during which the following occurs:

1. The Interrupt Mask register is cleared.

2. IRQ7 input is assigned priority 7.

3. The slave mode address is set to 7.

4. Special mask mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to

complete the initialization sequence.

Bit Description

7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.

000 = Should be programmed to “000”

4ICW/OCW Select — WO.

1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4

sequence.

3Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level

triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).

2ADI — WO.

0 = Ignored fo r the Intel® ICH7. Should be programmed to 0.

1Single or Cascade (SNGL) — WO.

0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.

0ICW4 Write Required (IC4) — WO.

1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be

programmed.

LPC Interface Bridge Registers (D31:F 0 )

398 Intel ® ICH7 Family Datasheet

10.4.3 ICW2—Initialization Command Word 2 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 21h Attribute: WO

Slave Controller

– A1h Size: 8 bit /controller

Default Value: All bits undefined

ICW2 is used to initialize the interrupt controller with the five most significant bits of

the interrupt vector address. The value programmed for bits[7:3] is used by the

processor to define the base address in the interrupt vector table for the interrupt

routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h

for the master controller and 70h for the slave controller.

10.4.4 ICW3—Master Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)

Offset Address: 21h Attribute: WO

Default Value: All bits undefined Size: 8 bits

Bit Description

7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the

interrupt vector table for the interrupt routines associated wit h each interrupt request

level input.

2:0

Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.

During an interrupt acknowledge c ycle, t hese bits are programmed by the interrupt

controller with the interrupt to be serviced. This is combined with bits [7:3] to form the

interrupt vector driven onto the data bus during the second INTA# cycle. Th e c ode i s a

three bit binary code:

Code Master Interrupt Slave Interrupt

000b IRQ0 IRQ8

001b IRQ1 IRQ9

010b IRQ2 IRQ10

011b IRQ3 IRQ11

100b IRQ4 IRQ12

101b IRQ5 IRQ13

110b IRQ6 IRQ14

111b IRQ7 IRQ15

Bit Description

7:3 0 = These bits must be programmed to 0.

Cascaded Interrupt Controller IRQ Connectio n — WO. This bit indicates that the

slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through

the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2.

IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR

signal is asserted to the processor, and the returning interrupt acknowledge returns the

interrupt vector for the slave controller.

1 = This bit must always be programmed to a 1.

1:0 0 = These bits must be programmed to 0.

Intel ® ICH7 Family Datasheet 399

LPC Interface Bridge Registers (D31:F0)

10.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register (LPC I/F—D31:F0)

Offset Address: A1h Attribute: WO

Default Value: All bits undefined Size: 8 bits

10.4.6 ICW4—Initialization Command Word 4 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 021h Attribute: WO

Slave Controller

– 0A1h Size: 8 bits

Default Value: 01h

Bit Description

7:3 0 = These bits must be programmed to 0.

2:0

Slave Identific ation Code — WO. These bits are compared against the slave

identification code broadcast by the master controller from the trail ing edge of the first

internal INT A# pulse to the trailing edge of the second internal INT A# pulse. These bits

must be programmed to 02h to match the code broadcast by the master controller.

When 02h is broadcast by the master controller during the INTA# sequence, the slave

controller assum es responsibility for broadcasting the interrupt vector.

Bit Description

7:5 0 = These bits must be programmed to 0.

4Special Fully Nested Mode (SFNM) — WO.

0 = Should normally be disabled by writing a 0 to this bit.

1 = Special fully nested mode is programmed.

3Buffered Mode (BUF) — WO.

0 = Must be programmed to 0 for the Intel® ICH7. This is non-buffered mode.

2Master/Slave in Buffered Mode — WO. Not used.

0 = Should always be programmed to 0.

1Automatic End of Interrupt (AEOI) — WO.

0 = This bit should normally be programmed to 0. This is the normal end of interrupt.

1 = Automatic End of Interrupt (AEOI) mode is programmed.

0Microprocessor Mode — WO.

1 = Must be programmed to 1 to indicate that the controller is operating in an Intel

Architecture-bas ed system.

LPC Interface Bridge Registers (D31:F 0 )

400 Intel ® ICH7 Family Datasheet

10.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Offset Address: Master Controller – 021h Attribute: R/W

Slave Controller

– 0A1h Size: 8 bits

Default Value: 00h

10.4.8 OCW2—Operational Control Word 2 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Size: 8 bits

Default Value: Bit[4:0]=undefined, Bit[7:5]=001

Following a part reset or ICW initialization, the controller enters the fully nested mode

of operation. Non-specific EOI without rotation is the default. Both rotation mode and

specific EOI mode are disabled following initialization.

Bit Description

7:0

Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the

corresponding IRQ line is masked. When a 0 is written to any bit in this register, the

corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by

the controller. Masking IRQ2 on the ma ster controller will also mask the interrupt

requests from the slave controller.

Bit Description

7:5

Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and

End of Interrupt modes and combinations of the two.

000 = Rotate in Auto EOI Mode (Cle ar)

001 = Non-specific EOI comma n d

010 = No Operation

011 = *Specific EOI Command

100 = Rotate in Auto EOI Mode (Set)

101 = Rotate on Non-Specific EOI Comman d

110 = *Set Priority Command

111 = *Rotate on Specific EOI Command

*L0 – L2 Are Used

4:3 OCW2 Select — WO. When selecting OCW2, bits 4:3 = “00”

2:0

Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt

level acted u pon when the SL bit is active. A simple binary co de, outlined below , select s

the channel for the com mand to act upon. When the SL bit is inactiv e, these bits do not

have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.

Code Interrupt Level Code Interrupt Level

000b IRQ0/8 000b IRQ4/12

001b IRQ1/9 001b IRQ5/13

010b IRQ2/10 010b IRQ6/14

011b IRQ3/11 011b IRQ7/15

Intel ® ICH7 Family Datasheet 401

LPC Interface Bridge Registers (D31:F0)

10.4.9 OCW3—Operational Control Word 3 Register

(LPC I/F—D31:F0)

Offset Address: Master Controller – 020h Attribute: WO

Slave Controller

– 0A0h Size: 8 bits

Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined,

Bit[5,1]=1

Bit Description

7 Reserved. Must be 0.

Special Mask Mode (SMM) — WO.

1 = The Special Mask Mode can be used by an interrupt service routine to dyna mi ca l ly

alter the system priority structure while the routine is executing, through selective

enabling/disabling of the other ch annel's mask bits. Bit 5, the ESMM bit, must be

set for this bit to have any meaning.

5Enable Special Mask Mo de (E SMM) — WO.

0 = Disable. The SMM bit becomes a “don't care”.

1 = Enable the SMM bit to set or rese t the Special Mask Mode.

4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01

Poll Mode Command — WO.

0 = Disable. Poll Command is not issued.

1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt

acknowledge cycle. An encoded byte is driven onto the data bus, representing the

highest priority level requesting service.

1:0

affect the register read selection. When bit 1=1, bit 0 selects the register status

returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR

will be read. Following ICW initialization, the default OCW3 port address read will be

“read IRR”. To retain the current selection (read ISR or r ead IRR), always write a 0 to

bit 1 when programming this register. The selected register can be read repeatedly

without reprogramming OCW3. To select a new status register, OCW3 must be

reprogrammed prior to attempting the read.

00 = No Action

01 = No Action

10 = Read IRQ Register

11 = Read IS Regis ter

LPC Interface Bridge Registers (D31:F 0 )

402 Intel ® ICH7 Family Datasheet

10.4.10 ELCR1—Master Controller Edge/Level Triggered Register

(LPC I/F—D31:F0)

Offset Address: 4D0h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade

channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),

cannot be put into level mode.

Bit Description

7IRQ7 ECL — R/W.

0 = Edge.

1 = Level.

6IRQ6 ECL — R/W.

0 = Edge.

1 = Level.

5IRQ5 ECL — R/W.

0 = Edge.

1 = Level.

4IRQ4 ECL — R/W.

0 = Edge.

1 = Level.

3IRQ3 ECL — R/W.

0 = Edge.

1 = Level.

2:0 Reserved. Must be 0.

Intel ® ICH7 Family Datasheet 403

LPC Interface Bridge Registers (D31:F0)

10.4.11 ELCR2—Slave Controller Edge/Level Triggered Register

(LPC I/F—D31:F0)

Offset Address: 4D1h Attribute: R/W

Default Value: 00h Size: 8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In

level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,

IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level

mode.

Bit Description

7IRQ15 ECL — R/W.

0 = Edge

1 = Level

6IRQ14 ECL — R/W.

0 = Edge

1 = Level

5 Reserved. Must be 0.

4IRQ12 ECL — R/W.

0 = Edge

1 = Level

3IRQ11 ECL — R/W.

0 = Edge

1 = Level

2IRQ10 ECL — R/W.

0 = Edge

1 = Level

1IRQ9 ECL — R/W.

0 = Edge

1 = Level

0 Reserved. Must be 0.

LPC Interface Bridge Registers (D31:F 0 )

404 Intel ® ICH7 Family Datasheet

10.5 Advanced Programmable Interrupt Controller

(APIC)(D31:F0)

10.5.1 APIC Register Map (LPC I/F—D31:F0)

The APIC is accessed via an indirect addressing scheme. Two registers are visible by

software for manipulation of most of the APIC registers. These registers are mapped

into memory space. The registers are shown in Table 10-4.

Table 10-5 lists the registers which can be accessed within the APIC via the Index

For example, softw are should not access byte 2 from the Data register before accessing

bytes 0 and 1. The hardware will not attempt to recover from a bad programming

model in this case.

10.5.2 IND—Index Register (LPC I/F—D31:F0)

Memory Address FEC0_0000h Attribute: R/W

Default Value: 00h Size: 8 bits

The Index Register will select which APIC indirect register to be manipulated by

software. The selector values for the indirect registers are listed in Table 10-5. Software

will program this register to select the desired APIC internal register

Table 10-4. APIC Direct Registers (LPC I/F—D31:F0)

Address Mnemoni

cRegister Name Size Type

FEC0_0000h IND Index 8 bits R/W

FEC0_0010h DAT Data 32 bits R/W

FECO_0040h EOIR EOI 32 bits WO

Table 10-5. APIC Indirect Registers (LPC I/F—D31:F0)

Index Mnemonic Register Name Size Type

00 ID Identification 32 bits R/W

01 VER Version 32 bits RO

02–0F — Reserved — RO

10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO

12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO

... ... ... ... ...

3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO

40–FF — Reserved — RO

Bit Description

7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.

Intel ® ICH7 Family Datasheet 405

LPC Interface Bridge Registers (D31:F0)

10.5.3 DAT—Data Register (LPC I/F—D31:F0)

Memory Address FEC0_0010h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This is a 32-bit register specifying the data to be read or written to the register pointed

to by the Index register. This register can only be accessed in DWord quantities.

10.5.4 EOIR—EOI Register (LPC I/F—D31:F0)

Memory Address FEC0h_0040h Attribute: WO

Default Value: N/A Size: 32 bits

The EOI register is present to provide a mechanism to maintain the level triggered

semantics for level-triggered interrupts issued on the parallel bus.

When a write is issued to this register, the I/O APIC will check the lower 8 bits written

to this register, and compare it with the vector field for each entry in the I/O

Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit

14) for that I/O Redirection Entry will be cleared.

Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more

than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.

The interrupt which was prematurely reset will not be lost because if its input remained

active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced

at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the

ICH7.

Note: To provide for future expansion, the processor should always write a value of 0 to Bits

31:8.

Bit Description

7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the

APIC indirect register (Figure 10-5) pointed to by the Index register (Memory Address

FEC0_0000h).

Bit Description

31:8 R eserved. To provide for future expansion, the processor should alwa ys write a value of

0 to Bits 31:8.

7:0

Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC

will check this field, and compare it with the vector field for each entry in the I/O

Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection

Entry will be cleared.

LPC Interface Bridge Registers (D31:F 0 )

406 Intel ® ICH7 Family Datasheet

10.5.5 ID—Identification Register (LPC I/F—D31:F0)

Index Offset: 00h Attribute: R/W

Default Value: 00000000h Size: 32 bits

The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the

APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.

10.5.6 VER—Version Register (LPC I/F—D31:F0)

Index Offset: 01h Attribute: RO

Default Value: 00170020h Size: 32 bits

Each I/O APIC contains a hardwired Version Register that identifies different

implementation of APIC and their ve rsions. The maximum redirection entry information

also is in this register, to let software know how many interrupt are supported by this

APIC.

Bit Description

31:28 R eserved

27:24 APIC ID — R/W. Software must program this value before using the APIC.

23:16 Reserved

15 Scratchpad Bit.

14:0 Reserved

Bit Description

31:24 Reserved

23:16

Maximum Redirection Entries — RO. This field is the en try number (0 being the lo west

entry) of the highest entry in the redirection table. It is equal to the number of

interrupt input pins minus one and is in the range 0 through 239. In the Intel® ICH7

this field is hardwired to 17h to indicate 24 interrupts.

15 PRQ — RO. This bit indicate that the IOxAPIC does not implement the Pin Assertion

14:8 Reserved

7:0 Version — RO. This is a version number that identifies the implementation version.

Intel ® ICH7 Family Datasheet 407

LPC Interface Bridge Registers (D31:F0)

10.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0)

Index Offset: 10h–11h (vector 0) through Attribute:R/W, RO

3E–3Fh (vector 23)

Default Value: Bit 16 = 1,. All other bits undefined Size: 64 bits each, (accessed

as two 32 bit quantities)

The Redirection Table has a dedicated entry for each interrupt input pin. The

information in the Redirection Table is used to translate the interrupt manifestation on

the corresponding interrupt pin into an APIC message.

The APIC will respond to an edge triggered interrupt as long as the interrupt is held

until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery

status bit internally to the I/O APIC is set. The state machine will step ahead and wait

for an acknowledgment from the APIC unit that the interrupt message was sent. Only

then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new

edge will only result in a new invocation of the handler if its acceptance by the

destination APIC causes the Interrupt Request Register bit to go from 0 to 1.

(In other words, if the interrupt was not already pending at the destination.)

Bit Description

63:56

Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an

APIC ID. In this case, bits 63:59 should be programmed by software to 0.

If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination

address of a set of processors.

55:48 Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only

when in Processor System Bus mode. They become bits 11:4 of the address.

47:17 Reserved

Mask — R/W.

0 = Not masked: An edge or level on this interrupt pin results in the delivery of the

interrupt to the destination.

1 = Masked: Interrupts are not delivered nor held pending. Setting this bit aft er the

interrupt is accepted by a local APIC has no effect on that interrupt. This behavior

is identical to the device withdrawing the interrupt before it is posted to the

processor. It is software's responsibility to deal with the case where the mask bit is

set after the interrupt message has been accepted by a local APIC unit but before

the interrupt is dispensed to the processor.

Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that

triggers an interrupt.

0 = Edge triggered.

1 = Level triggered.

Remote IRR — R/W. This bit is used for level triggered interrupts; its meaning is

undefined for edge triggered interrupts.

0 = Reset when an EOI message is received from a local APIC.

1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.

Interrupt Input Pin Polarity — R/W. This bit specifies the po larity of each in terrupt

signal connected to the interrupt pins.

0 = Active high.

1 = Active low.

Delivery Status — RO. This field contains the current status of the delivery of this

interrupt. Writes to this bit have no effect.

0 = Idle. No activity for this interrupt.

1 = Pending. Interrupt has been injected, but delivery is not complete.

LPC Interface Bridge Registers (D31:F 0 )

408 Intel ® ICH7 Family Datasheet

NOTE: Delivery Mode encoding:

000 = Fixed. Deliver the signal on the INTR s ignal of all processor cores listed in the destinati on.

Trigger Mode can be edge or level.

001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is

executing at the lowest priority among all the processors listed in the specified

destination. Trigger Mode can be edge or level.

010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge

triggered. The vector information is igno red but must be progr ammed to all 0’s for future

compatibility: not supported

011 = Reserved

100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.

Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is

programmed as leve l triggered. For proper operation this redirection table entry must be

programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the

redirection table is incorrectly set to level, the loop count will continue counting through

the redirection table addresses. Once the count for the NMI pin is reached again, th e

interrupt will be sent again: not supported

101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the

INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated

as an edge triggered interrupt even if programmed as level triggered. For proper

operation this redir ection table entry must be programmed to edge triggered. The INIT

delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level,

the loop count will continue coun ting through the redirection table addresses. Once the

count for the INIT pin is reached again, the interrupt will be sent again: not supported

110 = Reserved

111 = ExtINT. Delive r the signal to the IN TR signal of all processor cores listed in the des tination

as an interrupt that originated in an externally connected 8259A compatible interrupt

controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the

external controll er that is expected to supply the vector. Requires the interrupt to be

programmed as edge triggered.

Destination Mode — R/W. This field determines the interpretation of the Destination

field.

0 = Physical. Destination APIC ID is identified by bits 59:56.

1 = Logical. Destinations are identified by matching bit 63:56 with the Logical

Destination in the Destination Format Register and Logical Destination Register in

each Local APIC.

10:8

Delivery Mode — R/W. This field specifies how the APICs listed in the destination field

should act upon reception of this signal. Certain Delivery Mode s will only operate as

intended when used in c on j unction with a specific trigger mode. These encodings are

listed in the no te below:

7:0 Vector — R/W. This field contains the interrupt vector for this interrupt. Values range

between 10h and FEh.

Bit Description

Intel ® ICH7 Family Datasheet 409

LPC Interface Bridge Registers (D31:F0)

10.6 Real Time Clock Registers (LPC I/F—D31:F0)

10.6.1 I/O Register Address Map (LPC I/F—D31:F0)

The RTC internal registers and RAM are organized as two banks of 128 bytes each,

called the standard and extended banks. The first 14 bytes of the standard bank

contain the R TC time and date inform ation along with four registers, A–D , that are used

for configuration of the RTC. The extended bank contains a full 128 bytes of battery

backed SRAM, and will be accessible even when the RTC module is disabled (via the

RTC configuration register). Registers A–D do not physically exist in the RAM.

All data movement between the host processor and the real-time clock is done through

registers mapped to the standard I/O space. Th e register map appears in Table 10-6.

NOTES:

1. I/O locations 70h and 71h are the standard legacy location for the real-time clock.

The map for this bank is shown in Table 10-7. Locations 72h and 73h are for

accessing the extended RAM. The extended RAM bank is also accessed using an

indexed scheme. I/O address 72h is used as the address pointer and I/O address

73h is used as the data register. Index addresses above 127h are not valid. If the

extended RAM is not needed, it may be disabled.

2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When

writing to this address, software must first read the v alue, and then write the same

value for bit 7 during the sequential address write. Note that port 70h is not

directly readable. The only way to read this register is through Alt Access mode.

Although R TC Index bits 6:0 are readable fr om port 74h, bit 7 will alwa ys return 0.

If the NMI# enable is not changed during normal operation, software can

alternatively read this bit once and then retain the value for all subsequent writes

to port 70h.

Table 10-6. RTC I/O Registers (LPC I/F—D31:F0)

I/O

Locations If U128E bit = 0 Function

70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register

71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register

72h and 76h Extended RAM Index Register (if enabled)

73h and 77h Extended RAM Target Register (if enabled)

LPC Interface Bridge Registers (D31:F 0 )

410 Intel ® ICH7 Family Datasheet

10.6.2 Indexed Regist ers (LPC I/F—D31:F0)

The RTC contains two sets of indexed registers that are accessed using the two

separate Index and Target registers (70/71h or 72/73h), as shown in Table 10-7.

Table 10-7. RTC (Standard) RAM Bank (LPC I/F—D31:F0)

Index Name

00h Seconds

01h Seconds Alarm

02h Minutes

03h Minute s Al arm

04h Hours

05h Hours Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Register A

0Bh Register B

0Ch Register C

0Dh Register D

0Eh–7Fh 114 Bytes of User RAM

Intel ® ICH7 Family Datasheet 411

LPC Interface Bridge Registers (D31:F0)

10.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0)

RTC Index: 0A Attribute: R/W

Default Value: Undefined Size: 8-bit

Lockable: No P ower Well: RTC

This register is used for general configuration of the RTC functions. None of the bits

are affected by RSMRST# or any other Intel® ICH7 reset signal.

Bit Description

Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.

0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm

information in RAM is always available when the UIP bit is 0.

1 = The update is soon to occur or is in progress.

6:4

Division Chain Sele ct (DV[2:0]) — R/W. These three bits control the divider chain

for the oscillator, and are not affected by RSMRST# or any other reset signal. DV2

corresponds to bit 6.

010 = Normal Operation

11X = Divider Reset

101 = Bypass 15 stages (test mode only)

100 = Bypass 10 stages (test mode only)

011 = Bypass 5 stages (test mode only)

001 = Invalid

000 = Invalid

3:0

Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain.

The selected tap can generate a periodic interrupt if the PIE bit is set in Register B.

Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be

used, these bits should all be set to 0. RS3 corresponds to bit 3.

0000 = Interrupt does not toggle

0001 = 3.90625 ms

0010 = 7.8125 ms

0011 = 122.070 µs

0100 = 244.141 µs

0101 = 488.281 µs

0110 = 976.5625 µs

0111 = 1.953125 ms

1000 = 3.90625 ms

1001 = 7.8125 ms

1010 = 15.625 ms

1011 = 31.25 ms

1100 = 62.5 ms

1101 = 125 ms

1110 = 250 ms

1111= 500 ms

LPC Interface Bridge Registers (D31:F 0 )

412 Intel ® ICH7 Family Datasheet

10.6.2.2 RTC_REGB—Register B (General Configuration)

(LPC I/F—D31:F0)

RTC Index: 0Bh Attribute: R/W

Default Value: U0U00UUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not

affected by RSMRST# nor any other reset signal.

0 = Update cycle occurs normally once each second.

1 = A current update cycle will abort and subsequent update cycles will not occur until

SET is returned to 0. When set is one, the BIOS may initialize time and calendar

bytes safely.

NOTE: This bit should be set then cleared early in BIOS POST after each powerup

directly after coin-cell battery insertion.

Periodic Interrupt Enable (P IE) — R/W. This bit is cleared by RSMRST#, but not on

any other reset.

0 = Disable.

1 = Enable. Allows an interrupt to occ ur with a time base set with the RS bits of registe r

Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any

other reset.

0 = Disable.

1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the

update cycle. An alarm can occur once a se cond, one an hour, once a day, or one a

month.

Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but

not on any other reset.

0 = Disable.

1 = Enable. Allows an interrupt to occur when the update cycl e ends.

3Square Wave Enable (SQWE) — R/W. This bit serves no function in the Intel® ICH7.

It is left in this register bank to provide compatibility with the Motorola 146818B. The

ICH7 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.

Intel ® ICH7 Family Datasheet 413

LPC Interface Bridge Registers (D31:F0)

10.6.2.3 RTC_REGC—Register C (Flag Register)

(LPC I/F—D31:F0)

RTC Index: 0Ch Attribute: RO

Default Value: 00U00000 (U: Undefined) Size: 8-bit

Lockable: No P ower Well: RTC

Writes to Register C have no effect.

Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.

This bit is not affected by RSMRS T # nor any other reset signal.

0 = BCD

1 = Bin ary

Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is

not affected by RSMRST# nor any other reset signal.

0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and

PM as one.

1 = Twenty-four hour mode.

Daylight Savings Enable (DSE) — R/W. This bit tr iggers two special hour updates per

year. The days for the hour adjustment are those specifie d in U nite d Stat es fe deral law

as of 1987, which is different than previous ye ars. This bit is not affected by RSMRST#

nor any other reset signal.

0 = Daylight Savings Time updates do not occur.

1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to

3:00:00 AM.

b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it

is changed to 1:00:00 AM. The time must increment normally for at least two

update cycles (seconds) previous to these conditions for the time change to occur

properly.

Bit Description

7 Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).

This bit also cau ses the R T C Interrupt to be asserted. This bit is cleared upon RSMRST#

or a read of Register C.

Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of

0 = If no taps are specified via the RS bits in Register A, this flag wi ll not be set.

1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is

5Alarm Flag (AF) — RO.

0 = This bit is cleared upon RTCRST# or a read of Register C.

1 = Alarm Flag will be set after all Alarm values match the current time.

4Update-Ended Flag (UF) — RO.

0 = The bit is cleared upon RSMRST# or a read of Register C.

1 = Set immediately following an update cycle for each second.

3:0 Reserved. Will always report 0.

LPC Interface Bridge Registers (D31:F 0 )

414 Intel ® ICH7 Family Datasheet

10.6.2.4 RTC_REGD—Register D (Flag Register)

(LPC I/F—D31:F0)

RTC Index: 0Dh Attribute: R/W

Default Value: 10UUUUUU (U: Undefined) Size: 8-bit

Lockable: No Power Well: RTC

Bit Description

Valid RAM and Time Bit (VRT) — R/W.

0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for

read cycles.

1 = This bit is hardwired to 1 in the RTC power well.

6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.

5:0

Date Alarm — R/W. These bits store the date of month alarm v alue. If set to 000000b,

then a don’t care state is assumed. The host must configure the date alarm for these

bits to do anything, yet they can be written at any time. If the date alarm is not

enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B.

These bits are not affect ed by any reset assertion.

Intel ® ICH7 Family Datasheet 415

LPC Interface Bridge Registers (D31:F0)

10.7 Processor Interface Registers (LPC I/F—D31:F0)

Table 10-8 is the register address map for the processor interface registers.

10.7.1 NMI_SC—NMI Status and Control Register

(LPC I/F—D31:F0)

I/O Address: 6 1h Attribute: R/W, RO

Default Value: 00h Size: 8-bit

Lockable: No P ower Well: Core

Table 10-8. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)

Offset Mnemonic Register Name Default Type

61h NMI_SC NMI Status and Control 00h R/W, RO

70h NMI_EN NMI Enable 80h R/W (special)

92h PORT92 Fast A20 and Init 00h R/W

F0h COPROC_ERR Coprocessor Error 00h R/W

CF9h RST_CNT Reset Control 00h R/W

Bit Description

SERR# NMI Source Status (SERR#_NMI_STS) — RO.

1 = Bit is set if a PCI agent detec ted a system err or and pulses the PCI SERR# line and

if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2

to 0. To reset the interrupt, se t bit 2 to 1 and th en set i t to 0. When writi ng to port

61h, this bit must be 0.

NOTE: This bit is set by any of the Intel® ICH7 internal sources of SERR; this includes

SERR assertions forwarded from the secondary PCI bus, errors on a PCI

Express* port, or other internal functions that generate SERR#.

IOCHK# NMI Source St a t us (IOCHK_N MI_STS) — RO.

1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3

(IOCHK_NMI_EN) is cleared. This interrupt source is enable d by setting bit 3 to 0.

To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h,

this bit must be a 0.

Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current

state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI

reset for this bit to have a determinate value. When writing to port 61h, this bit must

be a 0.

4Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or

1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to

port 61h, this bit must be a 0.

3IOCHK# NM I E n a b l e (IOCHK_NMI _E N ) — R/W.

0 = Enabled.

1 = Disabled and cleared.

LPC Interface Bridge Registers (D31:F 0 )

416 Intel ® ICH7 Family Datasheet

10.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

I/O Address: 70h Attribute: R/W (special)

Default Value: 80h Size: 8-bit

Lockable: No Power Well: Core

Note: The R T C Index fiel d is write-on ly for normal oper ation. This field can only be read in Alt-

Access Mode. Note, however, that this register is aliased to Port 74h (documented in),

and all bits are readable at that address.

10.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)

I/O Address: 92h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Core

2PCI SERR# Enable (PCI_SERR_EN) — R/W.

0 = SERR# NMIs are enabled.

1 = SERR# NMIs are disabled and cleared.

1Speaker Data Enable (SPKR_DAT_EN) — R/W.

0 = SPKR output is a 0.

1 = SPKR output is equivalent to the Counter 2 OUT signal value.

0Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.

0 = Disable

1 = Enable

Bit Description

Bits Description

7NMI Enable (NMI_EN) — R/W (special).

0 = Enable NMI sources.

1 = Disable All NMI sources.

6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to

the RTC to select which register or CMOS RAM address is being accessed.

Bit Description

7:2 Reserved

Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE

input signal to generate A20M# to the processor.

0 = A20M# signal can potentially go active.

1 = This bit is set when INIT# goes active.

0INIT_NOW — R/W. When this bit trans itions from a 0 to a 1, the Inte l® ICH7 will force

INIT# active for 16 PCI clocks.

Intel ® ICH7 Family Datasheet 417

LPC Interface Bridge Registers (D31:F0)

10.7.4 COPROC_ERR—Coprocessor Error Register

(LPC I/F—D31:F0)

I/O Address: F0h Attribute: R/W

Default Value: 00h Size: 8-bits

Lockable: No P ower Well: Core

10.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0)

I/O Address: CF9h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No P ower Well: Core

Bits Description

7:0

Coprocessor Error (COPROC_ERR) — R/W. Any value written to this register will

cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to

generat e an internal IRQ13, the COPROC_ERR _EN bit (Device 31:Function 0, Offset D0,

Bit 13) must be 1. Reads to this register always return 00h.

Bit Description

7:4 Reserved

Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,

SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),

after PWROK going low (with RSMRST# high), or after two TCO timeouts.

0 = Intel® ICH7 will keep SLP_S3#, SLP_S4# and SLP_S5# high.

1 = ICH7 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.

NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)

in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.

2Reset CPU (RST_CPU) — R/W. When this bi t transitions from a 0 to a 1, it initiates a

hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).

System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to

the processor.

0 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a soft reset by activating

INIT# for 16 PCI clocks.

1 = When RST_CPU bit goes from 0 to 1, the ICH7 performs a hard reset by activating

PLTRST# and SUS_STAT# active for about 5-6 milliseconds, however the

SLP_S3#, SLP_S4# and SLP_S5# will NOT go active. The ICH7 main power well is

reset when this bit is 1. It also resets the resume well bits (except for those noted

throughout the datasheet).

0 Reserved

LPC Interface Bridge Registers (D31:F 0 )

418 Intel ® ICH7 Family Datasheet

10.8 Power Management Registers (PM—D31:F0)

The power management registers are distributed within the PCI Device 31: Function 0

space, as well as a separate I/O range. Each register is described below. Unless

otherwise indicate, bits are in the main (core) power well.

Bits not explicitly defined in each register are assumed to be reserved. When writing to

a reserved bit, the value should always be 0. Software should not attempt to use the

value read from a reserved bit, as it may not be consistently 1 or 0.

10.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)

Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0.

It includes only those registers dedicated for power management. Some of the

registers are only used for Legacy Power management schemes.

Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)

Offset Mnemonic Register Name Default Type

A0h GEN_PMCON_1 General Power Management

Configuration 1 0000h R/W, RO,

R/WO

A2h GEN_PMCON_2 General Power Management

Configuration 2 00h R/W, R/

A4h GEN_PMCON_3 General Power Management

Configuration 3 00h R/W, R/

A9h Cx-STATE_CNF Cx State Configuration (Mobile/Ultra

Mobile Only). 00h R/W

AAh C4-TIMING_CNT C4 Timing Control (Mobile/Ultra Mobile

Only). 00h R/W

ABh BM_BREAK_EN BM_BREAK_EN 00h R/W

ADh MSC_FUN Miscellaneous Functionality 00h R/W

B0h EL_STS Intel® Quick Resume Technology Status

B1h-B2h EL_CNTL1 Intel Quick R esume T echno logy Control 1

B3h EL_CNTL2 Intel Quick Resume Technology Control 2

B8–BBh GPI_ROUT GPI Route Control 0000000

0h R/W

Intel ® ICH7 Family Datasheet 419

LPC Interface Bridge Registers (D31:F0)

10.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0)

Offset Address: A0h Attribute: R/W, RO, R/WO

Default Value: 0000h Size: 16-bit

Lockable: No U sage: ACPI, Legacy

Power Well: Core

Bit Description

15:11 Reserved

(Desktop

and

Mobile

Only)

BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated

with the PCI Express* ports.

0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to

go active.

1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to go

active.

(Ultra

Mobile

Only)

Reserved

9PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.

0 = Low.

1 = Hig h.

8 Reserved

(Desktop

Only) Reserved

(Mobile/

Ultra

Mobile

Only)

Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when

software does a LVL3 read, the Intel® ICH7-M/ICH7-U transitions to the C4 state.

6i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,

not an IA_32 processor. This may be used in v arious state machines where the re are

behavioral differences.

(Desktop

Only)

CPU SLP# Enable (CPUSLP_EN) — R/W.

0 = Disable.

1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the

processor power.

(Mobile/

Ultra

Mobile

Only)

Reserved

SMI_LOCK — R/WO . When this bit is set , writes to the GLB_SMI_EN bit (P MBASE +

30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to

SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by

PLTRST#).

3:2

(Desktop

Only) Reserved

LPC Interface Bridge Registers (D31:F 0 )

420 Intel ® ICH7 Family Datasheet

10.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0)

Offset Address: A2h Attrib ute: R/W, R/WC

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Resume

(Mobile/

Ultra

Mobile

Only)

Intel SpeedStep Enable (SS_EN) — R/W.

0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be

visible (reads to SS_CNT will return 00h and writes will have no effect).

1 = Intel SpeedStep technology logi c is enabled.

(Mobile/

Ultra

Mobile

Only)

PCI CLKRUN# Enable (CLKRUN_EN) — R/W.

0 = Disable. Intel® ICH7-M/ICH7-U drives the CLKRUN# signal low.

1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and

STP_PCI# signals.

NOTE: when the SLP_EN# bit is set, the ICH7 drives the CLKRUN# signal low

regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and

LPC clocks continue running during a transition to a sleep state.

1:0

Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control

the rate at which periodic SMI# is generated.

00 = 1 minute

01 = 32 seconds

10 = 16 seconds

11 = 8 seconds

Bit Description

DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any

way. BIOS is expected to set this bit prior to starting the DRAM init ialization sequence

and to clear this bit after completing the DRAM initialization sequence. BIOS can detect

that a DRAM initialization sequence was interrupted by a reset by reading this bit during

the boot sequence.

• If the bit is 1, then the DRAM initialization was interrupted.

• This bit is reset by the assertion of the RSMRST# pin.

6:5

CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the

processor needs to lock it s PLLs. This is used wherever timing t270 (Chapter 23)

applies.

00 = min 30.7 µs (Default)

01 = min 61.4 µs

10 = min 122.8 µs

11 = min 245.6 µs

It is the responsibili ty of the BIOS to program the co rrect value in this field prio r to the

first transition to C3 or C4 states (or performing Intel SpeedStep® technology

transitions).

NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1: 0) act as an override to th es e

bits.

NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write

Intel ® ICH7 Family Datasheet 421

LPC Interface Bridge Registers (D31:F0)

NOTE: VRM PW ROK is sampled using the RTC clock. Therefore, low times that are less than one

RTC clock period may not be detected by the ICH7.

System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.

0 = SYS_RESET# button Not pressed.

1 = ICH7 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to

read this bit and clear it, if it is set.

NOTE: This bit is also reset by RSMRST# and CF9h resets.

CPU Thermal Trip Status (CTS) — R/W C .

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the

system is in an S0 or S1 state.

NOTES:

1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the

shutdown and reboot associated with the CPUTHRMTRIP# event.

2. The CF9h reset in the description refers to CF9h type core well reset which

includes SYS_RST#, PWROK/VRMPWRGD low , SMBus hard reset, T CO Timeout.

This type of reset will clear CTS bit.

Minimum SLP_S4# Assertion Width Violation Status — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time

programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset

A4h:bits 5:4). The ICH7 begins the timer when SLP_S4# is asserted during S4/S5

entry, or when the RSMRST# input is deasserted during G3 exit. Note that this bit

is functional regardless of the value in the SLP_S4# Assertion Stretch Enable

(D31:F0:Offset A4h:bit 3).

NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some

cases before the default value is readable.

CPU Power Failure (C PUPWR_FLR) — R/WC.

0 = Software (typically BIOS) clears this bit by writing a 0 to it.

1 = Indicates that the VRMPWRGD signal from the processor’ s VRM went low while the

system was in an S0 or S1 state.

NOTE: VRMPWRGD is sampl ed using the RTC clock. Therefore, low times that are less

than one RTC clock period may not be detected by the ICH7.

PWROK Failure (PWROK_FLR) — R/WC.

0 = Software clears this bit by writing a 1 to it , or when the system goes into a G3

state.

1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1

state. The bit will be cleared only by software by writing a 1 to this bit or when the

system goes to a G3 state.

NOTE: See Chapter 5.14.11.3 for more details about the PWROK pin functionality.

NOTE: In the case of true PWROK failure, PWROK will go low first before the

VRMPWRGD.

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

422 Intel ® ICH7 Family Datasheet

10.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0)

Offset Address: A4h Attrib ute: R/W, R/WC

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: RTC

Bit Description

7:6

SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.

Valid values are:

00 = 1.5 ms ± 0.6 ms

01 = 16 ms ± 4 ms

10 = 32 ms ± 4 ms

11 = 64 ms ± 4 ms

These bits are not cleared by any type of reset except RTCRST#.

5:4

SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum

assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely

power-cycled.

Valid values are:

11 = 1 to 2 seconds

10 = 2 to 3 seconds

01 = 3 to 4 seconds

00 = 4 to 5 seconds

This value is used in two ways:

1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set

for BIOS to read when S0 is entered.

2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal

from deasserting within this minimum time period after asserting.

RTCRST# forces this field to the conservative default state (00b)

SLP_S4# Assertion Stretch Enable — R/W.

0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.

1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this

This bit is cleared by RTCRST#

Intel ® ICH7 Family Datasheet 423

LPC Interface Bridge Registers (D31:F0)

NOTE: RSMRST# is sampled using the RT C clock. Therefore, low times that are less than one RT C

clock period may not be detected by the ICH7.

2RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates

a weak or missing battery. The bit is not cleared by any type of reset. The bit will

remain set until the software clears it by writing a 0 back to this bit position.

Power Failure (PWR_FLR) — R/WC. This bit is in t he RTC well, and is not cleared by

any type of reset except RTCRST#.

0 = Indicates that the trickle current has not failed since th e last time the bit was

cleared. Software clears this bit by writing a 1 to it.

1 = Indicates that the trickle current (from the main battery or trickle supply) was

removed or failed.

NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on

RTCRST# or GPI, or using SAFEMODE strap. Implementations should not

attempt to clear CMOS by using a jumper to pull VccRTC low.

AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied

after a power failure (G3 state). This bit is in the RTC well and is not cleared by any

type of reset except writes to CF9h or RTCRST#.

0 = System will return to S0 state (boot) after power is re-applied.

1 = System wil l return to the S5 state (exce pt if it w as in S4, i n which case it will return

to S4). In the S5 state, the only enabled wake event is the Power Button or any

enabled wake event that was preserved through the power failure.

NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

424 Intel ® ICH7 Family Datasheet

10.8.1.4 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile/Ultra Mobile Only)

Offset Address: A9h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

This register is used to enable new C-state related modes.

Bit Description

7SCRATCHPAD (SP) — R/W.

6:5 Reserved

Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME

bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.

0 = The Int el® ICH7-M/ICH7-U wi ll not attempt to au tomatically re turn to a previous

C3 or C4 state.

1 = When this bit is a 1 and ICH7-M/ICH7-U observes that there are no bus master

requests, it can return to a previous C3 or C4 state.

NOTE: This bit is separate from the PUME bit to cover cases where latency issues

permit POPUP but not PO PDOWN.

Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH7-M/ICH7-U

behaves like ICH5, in that bus master traffic is a break event, and it will return from

C3/C4 to C0 based on a break event. See Chapter 5.14.5 for additional details on this

mode.

0 = The ICH7 will treat Bus master traffic a break event, and will return from C3/C4 to

C0 based on a break event.

1 = When this bit is a 1 and ICH7 observes a bus master request, it will take the

system from a C3 or C4 state to a C2 state and auto enable bus masters. This will

let snoops and memory access occur.

Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.

0 = The ICH7 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from

PCI, PCI Express* and internal bus masters.

1 = When this bit is a 1, ICH7 will not set the BM_STS if there is bus master activity

from PCI, PCI Express and internal bus masters.

NOTES:

1. If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the

BM_STS bit will remain set. Software will still need to clear the BM_STS bit.

2. It is expected that if the PUME bit (this register, bit 3) is set, the

BM_STS_ZERO_EN bit should also be set. Setting one without the other would

mainly be for debug or errata workaround.

3. BM_STS will be set by LPC DMA (Mobile Only) or LPC masters, even if

BM_STS_ZERO_EN is set.

1:0 Reserved

Intel ® ICH7 Family Datasheet 425

LPC Interface Bridge Registers (D31:F0)

10.8.1.5 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile/Ultra Mobile Only)

Offset Address: AAh Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No U sage: ACPI, Legacy

Power Well: Core

This register is used to enable C-state related modes.

Bit Description

7:4 Reserved

3:2

DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the Intel®

ICH7-M/ICH7-U waits for from the deassertion of DPRSLPVR to the deassertion of

STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize

when exiting from a C4 state. This changes the value for t266.

1:0

DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#

deassertion time (t270). Normally this value is determined by the

CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,

then the values in this regist er have higher priority. It is software’s responsibility to

program these fields in a consistent manner.

Bits t266min t266max Comment

00b 95 µs 101 µs Default

01b 22 µs 28 µs Value used for “Fast ” VRMs

10b 34 µs 40 µs Recommended Value

11b Reserved

Bit

t270

00b Use value in CPU_PLL_LOCK_TIME field (default is 30 µs)

01b 20 µs

10b 15 µs (Recommended Value)

11b 10 µs

LPC Interface Bridge Registers (D31:F 0 )

426 Intel ® ICH7 Family Datasheet

10.8.1.6 BM_BREAK_EN Register (PM—D31:F0) (Mobile/Ultra Mobile Only)

Offset Address: ABh Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI, Legacy

Power Well: Core

Bit Description

IDE_BREAK_EN — R/W.

0 = Parallel IDE or Serial ATA traffic will not act as a break event.

1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STS-

ZERO_EN and POPUP_EN bits are set. Parallel IDE or Serial ATA master activity

will cause BM_STS to be set and will cause a break from C3/C4.

(Mobile

Only)

PCIE_BREAK_EN — R/W.

0 = PCI Express* traffic will not act as a break event.

1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and

POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set

and will cause a break from C3/C4.

(Ultra

Mobile

Only)

Reserved

PCI_BREAK_EN — R/W.

0 = PCI traffic will not act as a break event.

1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN

bits are set. PCI master activity will cause BM_STS to be set and will cause a

break from C3/C4.

4:3 Reserved

EHCI_BREAK_EN — R/W.

0 = EHCI traffic will not act as a break event.

1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN

bits are set. EHCI master activity will cause BM_STS to be set and will cause a

break from C3/C4.

UHCI_BREAK_EN — R/W.

0 = UHCI traffic will not act as a break event.

1 = USB traffic from any of the internal UHCIs acts as a break event, even if the

BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause

BM_STS to be set and will cause a break from C3/C4.

ACAZ_BREAK_EN — R/W.

0 = AC ‘97 or Intel® High Definition Audio traffic will not act as a break event.

1 = AC ‘97 or Intel High Definition Audio traffic acts as a break event, even if the

BM_STS-ZERO_EN and POPUP_EN bits are set. AC ‘97 or Intel High Defi nition

Audio master activity will cause BM _STS to be set and will cause a break from

C3/C4.

NOTE: For ICH7-U Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not

supported.

Intel ® ICH7 Family Datasheet 427

LPC Interface Bridge Registers (D31:F0)

10.8.1.7 MSC_FUN— Miscellaneous Functionality Register

(PM—D31:F0)

Offset Address: ADh Attribute: R/W

Default Value: 00h Size: 8-bit

Power Well: Resume

10.8.1.8 EL_STS—Intel® Quick Resume Technology Status Register (PM—

D31:F0) (ICH7DH Only)

Offset Address: B0h Attribute: R/WC, RO

Default Value: 00h Size: 8-bit

Power Well: Resume

Bit Description

7:2 Reserved

1:0 USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short Single-

Ended Zero (SE0) condition on the USB ports from being interpreted by the UHCI host

controller as a disconnect. BIOS should set to 11b.

Bit Description

7:5 Reserved

EL_SCI_NOW_STS— R/WC: This bit goes active when software writes a 1 to

EL_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the Intel

Quick Resume Technology (QRT) software to transition the reaction to an Intel QRT

event from an SMI# handler to an SCI handler. This bit remains set until a 1 is wri tten

to this bit position.

Once a 1 is written to this bit position, the logic will “re-arm” to allow the bit to be set

on the next write of 1 to SCI_NOW_CNT (Offset B1h:Bit 8).

EL_PB_SCI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from

high-to-low (post-debounce). It can be enabled to cause an SCI that will allow the

Intel QR T software to see when the power button has been pressed. It is a separate bit

from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide

any indication to other (i.e. Intel QRT) software.

The Intel QRT software clears EL_PB_SCI_STS by writing a 1 to this bit position.

2 Reserved

EL_PB_SMI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from

high-to-low (post-debounce). It can be enabled to cause an SMI# that will allow the

Intel QR T software to see when the power button has been pressed. It is a separate bit

from PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide

any indication to other (i.e., Intel QRT) software.

The Intel QRT software clears EL_PB_SMI_STS by writing a 1 to this bit position.

0 Reserved.

LPC Interface Bridge Registers (D31:F 0 )

428 Intel ® ICH7 Family Datasheet

10.8.1.9 EL_CNT1—Intel® Quick Resume Technology Control 1 Register (PM—

D31:F0) (ICH7DH Only)

Offset Address: B1h-B2h Attribute: R/W, RO, WO

Default Value: F000h Size: 16-bit

Power Well: Resume

Bit Description

15:10 Reserved

SMI_OPTION_CNT—R/W:

0 = Disable. Platform do es Not generate an SMI when an Intel Quick Resume

Technology (QRT) event occurs

1 = Enable. Platform generates an SMI when an Intel QRT event occurs (rather than

generating an SCI). The SMI hand ler can cause th e SCI by setting the

SCI_NOW_CNT.

8SCI_NOW_CNT—WO: When software writes a 1 to this bit, it causes

EL_SCI_NOW_STS (Offset B0:Bit 4) to assert (whic h can be enabled to cause an SCI).

This allows the SMI handler to cause the SCI.

PWRBTN_INT_EN—R/W:

0 = Disable.

1 = Enable. The Intel QRT logic is enabled to intercept the power button to cause the

Intel QRT SMI or SCI, and not immediately setting the PWRBTN_ST S bit. The Inte l

QRT soft ware will lat er se t the PWRBTN_STS bit by s e tti ng th e P WRBTN_EVNT bit.

NOTE: This bit is effective only in S0.

PWRBTN_EVNT—WO: When this bit is set to 1 by software, the PWRBTN_STS bit is

set to 1. This allows software to communicate P WR_BTN event to OS.

NOTES:

1. Power Button override still possible

2. Software does not need to clear this bit, as it is treated as an event

5:4

EL_STATE1_CNT[1:0]—R/W: These bits controls the EL_STATE1 pin. The

EL_STATE[1:0] pins can be used to control a multi color LED to indicate the platform

power states to user. If EL_LED_OWN is 0 then these bits have no impact.

00 = Low

01 = High

10 = Blinking. Note that the blink rate is ~ 1 Hz

11 = Reserved. Software must not set this combination

3:2

EL_STATE0_CNT[1:0]—R/W: These bits controls the EL_STATE0 pin. The

EL_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform

power states to user. If EL_LED_OWN is 0 then these bits have no impact.

00 = Low

01 = High

10 = Blinking. Note that the blink rate is ~ 1 Hz

11 = Reserved. Software must not set this combination

1EL_LED_OWN—R/W: Software sets this bit to 1 to configure the multiplexed pins t o

be EL_STATE[1:0] rather than GPIO[28:27].

0 Reserved

Intel ® ICH7 Family Datasheet 429

LPC Interface Bridge Registers (D31:F0)

10.8.1.10 EL_CNT2—Intel® Quick Resume Technology Control 2 Register (PM—

D31:F0) (ICH7DH Only)

Offset Address: B3h Attribute: R/W, RO

Default Value: 00h Size: 8-bit

Power Well: RTC

10.8.1.11 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0)

Offset Address: B8h – BBh Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Resume

Note: GPIOs that are not implemented will not have the corresponding bits implemented in

this register.

Bit Description

7:1 Reserved

Intel Quick Resume Technology Enable (EL_EN)—R/W: This bit enables Intel

Quick Resume Technology.

0 = Disabled

1 = Enabled

When this bit is 0, the R/W bits of Intel Quick Resume Technology Control Registers

(EL_CNT1, EL_CNT2) scratchpad with no effect on hardware functions. Also, WO bits

have no effect on hardware functions.

BIOS software is expected to set this bit after booting. Default value for this bit is 0.

Bit Description

31:30 GPIO15 Route — R/W. See bits 1:0 for description.

Same pattern for GPIO14 through GPIO3

5:4 GPIO2 Route — R/W. See bits 1:0 for description.

3:2 GPIO1 Route — R/W. See bits 1:0 for description.

1:0

GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the

GPIO[n]_STS bit i s set. If the GPIO0 is not set to an input, th is field has no effect.

If the system is in an S1–S5 state and if the G PE0_EN bit is also set, th en the GPIO can

cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.

00 = No effect.

01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)

10 = SCI (if corresponding GPE0_EN bit is also set)

11 = Reserved

LPC Interface Bridge Registers (D31:F 0 )

430 Intel ® ICH7 Family Datasheet

10.8.2 APM I/O Decode

Table 10-10 shows the I/O registers associated with APM support. This register space is

enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved

(fixed I/O location).

10.8.2.1 APM_CNT—Advanced Power Management Control Port

I/O Address: B2h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

10.8.2.2 APM_STS—Advanced Power Management Status Port

I/O Address: B3h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: Legacy Only

Power Well: Core

Table 10-10. APM Register Map

Address Mnemonic Register Name Default Type

B2h APM_CNT Advanced Power Management Control Port 00h R/W

B3h APM_STS Advanced Power Management Status Port 00h R/W

Bit Description

7:0 Used to pass an APM command be tween the OS and the SMI handler. Writes to this

port not only store data in the APMC register, but also generates an SMI# when the

APMC_EN bit is set.

Bit Description

7:0 Used to pass data between t he OS and the SMI handler. Basically, this is a scratchpad

Intel ® ICH7 Family Datasheet 431

LPC Interface Bridge Registers (D31:F0)

10.8.3 Power Management I/O Registers

Table 10-11 shows the registers associated with ACPI and Legacy power management

support. These registers are enabled in the PCI Device 31: Function 0 space

(PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers

are defined to support the ACPI 2.0 specification, and use the same bit names.

Note: All reserved bits and registers will always return 0 when read, and will have no effect

when written.

Table 10-11. ACPI and Legacy I/O Register Map (Sheet 1 of 2)

PMBASE

+ Offset Mnemonic Register Name ACPI Pointer Default Type

00h–01h PM1_STS PM1 Status PM1a_EVT_BLK 0000h R/WC

02h–03h PM1_EN PM1 Enable PM1a_EVT_BLK+2 0000h R/W

04h–07h PM1_CNT PM1 Control PM1a_CNT_BLK 00000000h R/W, WO

08h–0Bh PM1_TMR PM1 Timer PMTMR_BLK xx000000h RO

0Ch–0Fh — Reserved — — —

10h–13h PROC_CNT Processor Control P_BLK 00000000h R/W, RO, WO

14h–16h — Reserved (Desktop Only) — — —

14h LV2 Level 2 (Mobile/Ultra

Mobile Only) P_BLK+4 00h RO

15h LV3 Level 3 (Mobile/Ultra

Mobile Only) P_BLK+5 00h RO

16h LV4 Level 4 (Mobile/Ultra

Mobile Only) P_BLK+6 00h RO

17h–1Fh — Reserved — — —

20h — Reserved (Desktop Only) — — —

20h PM2_CNT PM2 Cont rol (Mobile/

Ultra Mobile Only) PM2a_CNT_BLK 00h R/W

28h–2Bh GPE0_STS General Purpose Event 0

Status GPE0_BLK 00000000h R/WC

2Ch–2Fh GPE0_EN General Purpose Event 0

Enables GPE0_BLK+4 00000000h R/W

30h–33h SMI_EN SMI# Control and Enable 00000000h R/W, WO,

R/W (special)

34h–37h SMI_STS SMI Status 00000000h R/WC, RO

38h–39h ALT_GP_SMI_EN Alternate GPI SMI Enable 0000h R/W

3Ah–3Bh ALT_GP_SMI_ST

SAlternate GPI SMI Status 0000h R/WC

3Ch–41h — Reserved — — —

42h GPE_CNTL General Purpose Event

Control 00h RO, R/W

43h — Reserved — — —

44h–45h DEVACT_STS Device Activity Status 0000h R/WC

46h–4Fh — Reserved

LPC Interface Bridge Registers (D31:F 0 )

432 Intel ® ICH7 Family Datasheet

10.8.3.1 PM1_STS—Power Management 1 Status Register

I/O Address: PMBASE + 00h

(ACPI PM1a_EVT_BLK) Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–15: Resume,

except Bit 11 in RTC

If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN

already in an S0 state when the event occurs), the ICH7 will also generate an SCI if the

SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.

Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but

can cause an SMI# or SCI.

50h — Reserved (Desktop Only)

50h SS_CNT

Intel SpeedStep®

Technology Control

(Mobile/Ultra Mobile

Only)

01h R/W (special)

51h–5Fh — Reserved — — —

54h–57h C3_RES C3-Residency Register

(Mobile/Ultra Mobile

Only) — 00000000h RO, R/W

60h–7Fh — Reserved for TCO — — —

Table 10-11. ACPI and Legacy I/O Register Map (Sheet 2 of 2)

PMBASE

+ Offset Mnemonic Register Name ACPI Pointer Default Type

Intel ® ICH7 Family Datasheet 433

LPC Interface Bridge Registers (D31:F0)

Bit Description

Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused

by a CF9 write, but is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN

bit) and an enabled wake event occurs. Upon s etting this bi t, the Int el® ICH7 will

transition the system to the ON state.

If the AFTERG3_EN bit is not set and a power failure (such as removed batteries on a

mobile/Ultra Mobile platform) occurs without the SLP_EN bit set, the system will

return to an S0 state when power returns, and the WAK_STS bit will not be set.

If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit

having been set, the system will go into an S5 state when power returns, and a

subsequent wake event will cause the WAK_STS bit to be set. Note that any

subsequent wake event would have to be caused by either a Power Button press, or

an enabled wake event that was preserved through the power failure (enable bit in

the RTC well).

(Desktop

and

Mobile

Only)

PCI Express Wake Status (PCIEXPWAK_STS) — R/WC.

0 = Software clears this bit b y writing a 1 to it. If the W AKE# pin is st ill act ive during

the write or the PME mes sage received indication h a s not been cleared in the

root port, then the bit will remain active (i.e. all inputs to this bit are level-

sensitive).

1 = This bit is set by hardware to indicate that the system woke due to a PCI Express

wakeup event. This wakeup event can be caused by th e P C I Express WAKE# pin

being active or receipt of a PCI Express PME message at a root port. This bit is

set only when one of these events causes the system to transition from a non-S0

system power state to the S0 system power state. This bit is set independent of

the state of the PCIEXP_WAKE_DIS bit.

NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping

state. Thus, if the bit is 1 and the system is put into a sleeping state, the

system will not automatically wake.

(Ultra

Mobile

Only)

Reserved

13:12 Reserved

Power Button Override Status (PRBTNOR_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set any time a P owe r Button Overr ide occ urs (i.e ., the power button is

pressed for at least 4 consecutive seconds), or due to the corresponding bit in

the SMBus slave message. The power button override causes an unconditional

transition to the S5 state, as well as sets the AFTERG# bit. The BIOS or SCI

handler clears this bit by writing a 1 to it. This bit is not affected by hard resets

via CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved

through power failures. Note that if this bit is still asserted when the global

SCI_EN is set then an SCI will be generated.

RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a

CF9 write, but is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8#

signal). Additionally if the RTC_EN bit (PMBAS E + 02h, bit 10) is set, the setti ng

of the RTC_STS bit will generate a wake event.

9 Reserved

LPC Interface Bridge Registers (D31:F 0 )

434 Intel ® ICH7 Family Datasheet

Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard

resets caused by a CF9 write.

0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears

the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to

the S5 state with only PWRBTN# enabled as a wake event.

This bit can be cleared by software by writing a one to the bit position.

1 = This bit is set by hardware when the PWRBTN# signal is asserted Low,

independent of any other enable bit.

In the S0 state, whil e PWRBTN_EN and PWRBTN_STS are both set, an SCI (or

SMI# if SCI_EN is not set) will be generated.

In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and

PWRBTN_STS are both set, a wake event is generated.

NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is

sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN#

signal must go inactive and active again to set the PWRBTN_STS bit.

7:6 Reserved

Global Status (GBL _STS) — R/WC.

0 = The SCI handler should then clear this bit by writing a 1 to the bit location.

1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI

handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and

set this bit.

(Desktop

Only) Reserved

(Mobile/

Ultra

Mobile

Only)

Bus Master Status (BM_STS) — R/WC. This bit will n ot cause a wak e event, SCI or

SMI#.

0 = Software clears this bit by writing a 1 to it.

1 = Set by t he Intel® ICH7-M/ICH7-U when a bus master requests access to main

memory . Bus master activity is detected by any of the PCI Requests being active,

any internal bus master request being active, the BM_BUSY# s ignal being active,

or REQ-C2 message received while in C3 or C4 state.

NOTES:

1. If the BM_STS_ZERO_EN bit is set, then this bit will generally report as a 0.

LPC DMA (Mobile Only) and bus master activity will always set the BM _STS

bit, even if the BM _STS_ZERO_EN bit is set.

3:1 Reserved

Timer Overflow Status (TMROF_STS) — R/WC.

0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.

1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered

from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit

(PMBASE + 02h, bit 0) is set, then the setting o f the TMROF_STS bit will

additionally generate an SCI or SMI# (depending on the SCI_EN).

Bit Description

Intel ® ICH7 Family Datasheet 435

LPC Interface Bridge Registers (D31:F0)

10.8.3.2 PM1_EN—Power Management 1 Enable Register

I/O Address: PMBASE + 02h

(ACPI PM1a_EVT_BLK + 2) Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–9, 11–15: Resume,

Bit 10: RTC

Bit Description

15 Reserved

(Desktop

and

Mobile

Only)

PCI Express Wake Disable(PCIEXPWAK_DIS) — R/W. M odification of this bit

has no impact on the value of the PCIEXP_WAKE_STS bit.

0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake

the system.

1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from

waking the system.

(Ultra

Mobile

Only)

Reserved

13:11 Reserved

RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC

event to wake after a power failure. This bit is not cleared by any reset other than

RTCRST# or a Power Button Override event.

0 = No SCI (or SMI#) or wake event is gener ated then R TC_STS (PMBA SE + 00h, bit

10) goes active.

1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RT C_STS

bit goes active.

9 Reserved.

Power Button Enable (PW RBTN _ EN ) — R/W. This bit is used to enable the

setting of the PWRBTN_STS bit to generate a power management event (SMI#,

SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8)

being set by the assertion of the power button. The Power Button is always enabled

as a Wake event.

0 = Disable.

1 = Enable.

7:6 Reserved.

Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit

(PMBASE + 00h, bit 5) are set, an SCI is raised.

0 = Disable.

1 = Enable SCI on GBL_STS going active.

4:1 Reserved.

Timer Overflow Interrupt Enable (TMROF_ E N) — R/W. Works in conjunction

with the SCI_EN bit (PMBASE + 04h, bit 0) as described below:

TMROF

EN SCI

EN Eff

TMROF

STS i

0 X No SMI# or SCI

10 SMI#

11 SCI

LPC Interface Bridge Registers (D31:F 0 )

436 Intel ® ICH7 Family Datasheet

10.8.3.3 PM1_CNT—Po wer Management 1 Control

I/O Address: PMBASE + 04h

(ACPI PM1a_CNT_BLK) Attribute: R/W, WO

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Bits 0–7: Core,

Bits 8–12: RTC,

Bits 13–15: Resume

Bit Description

31:14 Reserved.

13 Sleep Enable (SLP_EN) — WO. Setting t hi s bit cau se s th e system to sequenc e in to

the Sleep state de fined by the SLP_TYP field.

12:10

Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system

should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.

9:3 Reserved.

Global Release (GBL_RLS) — WO.

0 = This bit always reads as 0.

1 = ACPI software writes a 1 to this bit to r a i se an ev e n t to the BIOS. BIOS software

has a corresponding enable and status bits to control its ability to receive ACPI

events.

(Desktop

Only) Reserved

(Mobile/

Ultra

Mobile

Only)

Bus Master Reload (BM_RLD) — R/W. This bit i s treated as a scratchpad bit. This

bit is reset to 0 by PLTRST#

0 = Bus master requests will not cause a break from the C3 state.

1 = Enable Bus Master requests (internal, external or BM_BUSY#) to cause a break

from the C3 state.

If software fails to set this bit be fore going to C3 state, the Intel® ICH7-M/ICH7-U will

still return to a snoopable state from C3 or C4 states due to bus master activity.

SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for

various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in

GPE0_STS.

0 = These events will generate an SMI#.

1 = These events will generate an SCI.

Code Master Interrupt

000b ON: Typically maps to S0 state.

001b Asserts STPCLK#. Puts proce ssor in Stop-Grant state. Optional to

assert CPUSLP# to put processor in sleep state: T ypically, maps to S1

state.

010b Reserved

011b Reserved

100b Reserved

101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.

110b Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to

S4 state.

Soft Off Assert SLP S3# SLP S4# and SLP S5#: Typically maps to

Intel ® ICH7 Family Datasheet 437

LPC Interface Bridge Registers (D31:F0)

10.8.3.4 PM1_TMR—Power Management 1 Timer Register

I/O Address: PMBASE + 08h

(ACPI PMTM R _BL K )Attribute: RO

Default Value: xx000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Core

10.8.3.5 PROC_CNT—P rocessor Control Register

I/O Address: PMBASE + 10h

(ACPI P_BLK) Attribute: R/W, RO, WO

Default Value: 00000000h Size: 32-bit

Lockable: No (bits 7:5 are write once)Usage: ACPI or Legacy

Power Well: Core

Bit Description

31:24 Reserved

23:0

Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This

counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0

during a PCI reset, and then continues counting as long as the s yste m is in the S0

state. After an S1 state, the counter will not be reset (it will continue counting from the

last value in S0 state.

Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the

TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur

every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI

interrupt is also generated.

Bit Description

31:18 Reserved

Throttle Status (THTL_STS) — RO.

0 = No clock throttling is occurring (maximum processor performance).

1 = Indicates that the clock state machine is throttling the processor performance. This

could be due to the THT_EN bit or the FORCE_THTL bit being set.

16:9 Reserved

Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force

the thermal throttling function.

0 = No forced throttling.

1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no

SMI# is generated.

LPC Interface Bridge Registers (D31:F 0 )

438 Intel ® ICH7 Family Datasheet

7:5

THRM_DTY — WO. This write-once field determines the duty cycle of the throttling

when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage

of time the STPC LK# signal is asserted while in the throttle mode. The STPCLK#

throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in

the C0 state. For mobile/Ultra Mobile only, If in the C2, C3, or C4 state, no throttling

occurs.

Once the THRM_DTY field is written, any subsequent writes will have no effect until

PLTRST# goes active.

THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-

controlled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.

0 = Disable

1 = Enable

3:1

THTL_DTY — R/W. This field determines the duty cycle of the throttling when the

THTL_EN bit is set. The duty cycle indica tes the approximate percentage of time the

STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle

period is 1024 PCICLKs.

0 Reserved

Bit Description

THRM

DTY Th

ttl

PCI Cl

000b 50% (Default) 512

001b 87.5% 896

010b 75.0% 768

011b 62.5% 640

100b 50% 512

101b 37.5% 384

110b 25% 256

111b 12.5% 128

THTL

DTY Th

ttl

PCI Cl

000b 50% (Default) 512

001b 87.5% 896

010b 75.0% 768

011b 62.5% 640

100b 50% 512

101b 37.5% 384

110b 25% 256

111b 12.5% 128

Intel ® ICH7 Family Datasheet 439

LPC Interface Bridge Registers (D31:F0)

10.8.3.6 LV2 — Level 2 Register (Mobile/Ultra Mobile Only)

I/O Address: PMBASE + 14h

(ACPI P_BLK+4) Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by Intel® iA64 processors or systems with more than 1

logical processor, unless appropriate semaphoring software has been put in place to ensure

that all threads/processors are ready for the C2 state when the “read to this regi ster”

instruction occurs.

10.8.3.7 LV3—Level 3 Register (Mobile/Ultra Mobile Only)

I/O Address: PMBASE + 15h (ACPI P_BLK + 5)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a

LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and

LVL3 registers (which is not permitted), the Intel® ICH7-M/ICH7-U will ignore the LVL3

read, and only perform a C2 transition.

NOTE: This register should not be used by iA64 processors or systems with more than 1 logical

processor, unless appropriate semaphoring software has been put in place to ensure that

all threads/processors are ready for the C3 state when the “read to this register”

instruction occurs.

10.8.3.8 LV4—Level 4 Register (Mobile/Ultra Mobile Only)

I/O Address: PMBASE + 16h (ACPI P_BLK + 6)

Attribute: RO

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

NOTE: This register should not be used by iA64 processors or systems with more than 1 logical

processor, unless appropriate semaphoring software has been put in place to ensure that

all threads/processors are ready for the C4 state when the “read to this register”

instruction occurs.

Bit Description

7:0

Reads to this register return all 0s, writes to this register have no effect. Reads to this

cause the STPC LK# signal to go active, and stay a ctive until a break event occ urs.

Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.

Bit Description

7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this

persists until a break event occurs.

Bit Description

7:0 Reads to this register return all 0s, writes to this register have no effect. Reads to this

persists until a break event occurs.

LPC Interface Bridge Registers (D31:F 0 )

440 Intel ® ICH7 Family Datasheet

10.8.3.9 PM2_CNT—Power Management 2 Control Register (Mobile/Ultra

Mobile Only)

I/O Address: PMBASE + 20h

(ACPI PM2_BLK) Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI

Power Well: Core

10.8.3.10 GPE0_STS—General Purpose Event 0 Status Register

I/O Address: PMBASE + 28h

(ACPI GPE0_BLK) Attribute: R/WC

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Resume

This register is symmetrical to the General Purpose Ev ent 0 Enab l e Register. Unless

indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit

get set, the ICH7 will generate a W ak e Event. Once back in an S0 state (or if already in

an S0 state when the event occurs), the ICH7 will also generate an SCI if the SCI_EN

bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are

reset by a CF9h write; bits 15:0 are not. All are reset by RSMRST#.

Bit Description

7:1 Reserved

Arbiter Disable (ARB_DIS) — R/W. This bit is a scratchpad bit for legacy software

compatibility. Software typically sets this bit to 1 prior to entering a C3 or C4 state.

When a transition to a C3 or C4 state occurs, Intel® ICH7-M/ICH7-U will autom atically

prevent any internal or external non-Isoch bus masters from initiating any cycles up to

the (G)MCH. This blocking starts immediately upon the ICH7 sending the Go–C3

message to the (G)MCH. The blocking stops when the Ack-C2 message is received.

Note that this is not really blocking, in that messages (such as from PCI Express*) are

just queued and held pending.

Bit Description

31:16

GPIOn_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = These bits are set any time the corresponding GPIO is set up as an input and the

corresponding GPIO signal is high (or low if the correspondin g GP_INV bit is s et).

If the corresponding enable bit is set in the GPE0_EN register, then when the

GPIO[n]_STS bit is set:

• If the system is in an S1–S5 state, the event will also wake the system.

• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused

depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.

NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16

corresponds to GPIO0.

15 Reserved

USB4_STS — R/WC.

0 = Disable.

1 = Set by hardware and can be reset by writing a one to this bit position or a

resume well rese t. Th is bi t i s se t when USB UHCI con tr oll er #4 needs to cause a

wake. Additi onall y if the USB4 _EN bit is se t, the s etti ng of the USB4_ST S bit wi ll

generate a wake event.

Intel ® ICH7 Family Datasheet 441

LPC Interface Bridge Registers (D31:F0)

PME_B0_STS — R/WC. This bit will be set to 1 by the Intel® ICH7 when any internal

device with PCI Power Management capabilities on bus 0 asserts the equivalent of the

PME# signal. Additionally, if the PME_B0_EN bit is set, and the s ystem is in an S0

state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if

SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4 state

(or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit

will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be

generated. If the system is in an S5 state due to power button override, then the

PME_B0_STS bit will not cause a wake event or SCI.

The default for this bit is 0. Writing a 1 to this bit position clears this bit.

USB3_STS — R/WC.

0 = Disable.

1 = Set by hardware and can be reset by writing a one to this bit position or a

resume well reset. This bit is set when USB UHCI controller #3 needs to cause a

wake. Additional ly if th e USB3_ EN bi t is s et, the settin g of the USB3_STS bi t will

generate a wake event.

PME_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN

bit is set, and the system is in an S0 state, then the setting of the PME_STS bit

will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and

the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and

SLP_EN), then the setting of the PME_STS bit wi ll gener ate a wak e event, and an

SCI will be generated. If the system is in an S5 state due to power button

override or a power failure, then PME_STS will not cause a wake event or SCI.

(Desktop

Only)

Intel® ICH7DH Only:

EL_SCI_STS — R/WC. In Desktop Mode, when Intel Quick Resume Technology

feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or

EL_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit

position.

In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit

will be treated as Reserved.

ICH7 and ICH7R Only:

Reserved

(Mobile/

Ultra

Mobile

Only)

BATLOW_STS — R/WC. (Mobile/Ultra Mobile Only) Software clears this bit by

writing a 1 to it.

0 = BATLOW# Not asserted

1 = Set by hardware when the BATLOW# signal is asserted.

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

442 Intel ® ICH7 Family Datasheet

PCI_EXP_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware to indicate that:

• The PME event message was received on one or more of the PCI Express* ports (Desktop and

Mobile Only)

• An Assert PMEGPE message received from the (G)MCH via DMI

NOTES:

1. The PCI WAKE# pin has no impact on this bit.

2. If the PCI_E XP_STS bit went act ive due to an Asse rt PMEGPE message, t hen a

Deassert PMEGPE message must be received prior to the software write in

order for the bit to be cleared.

3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the

level-triggered SCI will remain active.

4. A race condition exists where the PCI Express device sends another PME

message because the PCI Express device was not servic ed within the time

when it must resend the message. This may result in a spurious interrupt,

and this is comprehended and approved by the PCI Express* Specification,

Revision 1.0a. The window for this race condition is approximately

95–105 milliseconds.

8RI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the RI# input signal goes active.

SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus con troll er can

independently cause an SMI# or SCI, so this bit does not need to do so (unlike the

other bits in this register). Software clears this bit by writing a 1 to it.

0 = Wake event Not caused by the ICH7 ’s SMBus logic.

1 = Set by hardware to indicate that the wake event was caused by the ICH7’s

SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the

system is already awake. The SMI handler should then c lear this bit.

NOTES:

1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the

system is in the S0 state. Therefore, to avoid an instant wake on subsequent

transitions to sleep states, software must clear this bit after each reception of

the Wake/SMI# command or just prior to entering the sleep state.

2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be

cleared by internal logic when a THRMTRIP# event happens or a Power

Button Ove rride event. Ho wever, THRMTRIP# or P ower Button O verride ev ent

will not clear SMB_WAK_STS if it is set due to SMBALERT# signal going

active.

3. The SMBALE RT_STS bit (D31:F3:I/O Of fset 00h:Bit 5) should be cleared by

software before the SMB_WAK_STS bit is cleared.

6TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = TOC logic did Not cause SCI.

1 = Set by hardware when the TCO logic causes an SCI.

Bit Description

Intel ® ICH7 Family Datasheet 443

LPC Interface Bridge Registers (D31:F0)

AC97_STS — R/WC. Th is bit will be set t o 1 when the codecs are attempting to w ake

the system and the PME events for the codecs are armed for wakeup. A PME is armed

by programming the appropriate PMEE bit in the Power Management Control and

Status register at bit 8 of offset 54h in each AC ’97 function.

0 = Software clears this bit by writing a 1 to it.

1 = Set by hardware when the codecs are attempti ng to wake the system. The

AC97_STS bit gets set only from the following two cases:

1. The PMEE bit for the function is set, and o The AC -link bit clock has been shut

and the routed ACZ_SDIN line is high (for audio, if routing is disabled, no

wake events are allowed).

2. For modem, if audio routing is disabled, then the wake event is an OR of all

ACZ_SDIN lines. If routing is enabled, then the wake event for modem is the

remaining non-routed ACZ_SDIN line), or o GPI Status Change Interrupt bit

(NABMBAR + 30h, bit 0) is 1.

NOTES:

1. This bit is not affected by a hard reset caused by a CF9h write.

2. This bit is also used for Intel® High Definition Audio when ICH7 is configured

to use the Intel High Definition Audio host controller rather than the AC97

host controller.

3. For ICH7 Ultra Mobile, only Intel High Definition is supported, AC ‘97 is not

supported.

USB2_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = USB UHCI controller 2 does Not need to cause a wake.

1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. W ake event

will be generated if the corresponding USB2_EN bit is set.

USB1_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = USB UHCI controller 1 does Not need to cause a wake.

1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. W ake event

will be generated if the corresponding USB1_EN bit is set.

2SWGPE_STS — R/WC.

The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.

(Desktop

and

Mobile

Only)

HOT_PLUG_STS — R/WC.

0 = This bit is cleared by writing a 1 to this bit position.

1 = When a PCI Express * Hot-Plug event occurs. This will cause an SCI i f the

HOT_PLUG_EN bit is set in the GEP0_EN register.

(Ultra

Mobile

Only)

Reserved

Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by

writing a 1 to it.

0 = THRM# signal Not driven active as defined by the THRM_POL bit

1 = Set by hardware anytime the THRM# signal is driven active as defined by the

THRM_POL bit. Addi tionally, if the THRM_EN bit is set, then the setting of the

THRM_STS bit will also generate a power management event (SCI or SMI#).

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

444 Intel ® ICH7 Family Datasheet

10.8.3.11 GPE0_EN—General Purpose Event 0 Enables Register

I/O Address: PMBASE + 2Ch

(ACPI GPE0_BLK + 4) Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI

Power Well: Bits 0–7, 9, 12, 14–31 Resume,

Bits 8, 10–11, 13 RTC

This register is symmetrical to the General Purpose Event 0 Status Register. All the bits

in this register should be cleared to 0 based on a Power Button Override or processor

Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RT C sell bits

are cleared by RTCRST#.

Bit Description

31:16

GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to

cause a SCI, and/or wake event. These bits are cleared by RSMRST#.

NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16

corresponds to GPIO0.

15 Reserved

USB4_EN — R/W.

0 = Disable.

1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS

bit is set anytime USB UHCI controller #4 signals a wake event. Break events are

handled via the USB interrupt.

PME_B0_EN — R/W.

0 = Disable

1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an

SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from

S5 (if entered via SLP_TYP an d S LP_EN) or power failure, but not Power Button

Override. This bit defaults to 0.

NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.

USB3_EN — R/W.

0 = Disable.

1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS

bit is set anytime USB UHCI controller #3 signals a wake event. Break events are

handled via the USB interrupt.

PME_EN — R/W.

0 = Disable.

1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.

PME# can be a wake event from the S1 – S4 state or from S5 (if entered via

SLP_EN, but not power button override).

(Desktop

Only)

ICH7DH Only:

EL_SCI_EN — R/W. In Desktop Mode with Intel Quick Resume Technology feature

enabled, this bit enables the EL_SCI_STS signal to cause an SCI (depending on the

SCI_EN bit) when it is asserted.

In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit

will be treated as Reserved.

ICH7 and ICH7R Only:

Reserved

Intel ® ICH7 Family Datasheet 445

LPC Interface Bridge Registers (D31:F0)

(Mobile/

Ultra

Mobile

Only)

BATLOW_EN — R/W. (Mobile/Ultra Mobile Only)

0 = Disable.

1 = Enables the BA TLOW# signal to cause an SMI# or SCI (depending on the SCI_EN

bit) when it goes low. This bit does not prevent the BATLOW# signal from

inhibiting the wake even t.

(Desktop

and

Mobile

Only)

PCI_EXP_EN — R/W.

0 = Disable SCI generation upon PCI_EXP_STS bit being set.

1 = Enables Intel® ICH7 to cause an SCI when PCI_EXP_STS bit is set. This is used to

allow the PCI Express* ports, including the link to the (G)MCH, to cau se an SCI

due to wake/PME events .

(Ultra

Mobile

Only)

Reserved. Must be programmed to 0.

RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not

affected by a hard reset caused by a CF9h write.

0 = Disable.

1 = Enables the setting of the RI_STS to generate a wake event.

7Reserved

6TCOSCI_EN — R/W.

0 = Disable.

1 = Enables the setting of the TCOSCI_STS to generate an SCI.

AC97_EN — R/W.

0 = Disable.

1 = Enables the setting of the AC97_STS to generate a wake event.

NOTE: This bit is also used for Intel® High Definition Audio when the Intel High

Definition Audio host controller is enabled rather than the AC97 host

controller.

4USB2_EN — R/W.

0 = Disable.

1 = Enables the setting of the USB2_STS to generate a wake event.

3USB1_EN — R/W.

0 = Disable.

1 = Enables the setting of the USB1_STS to generate a wake event.

SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS

bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is

written to a 1, hardware will set SWGPE_STS (acts as a level input)

If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated

If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1, then an

SMI# will be generated

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

446 Intel ® ICH7 Family Datasheet

(Desktop

and

Mobile

Only)

HOT_PLUG_EN — R/W.

0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.

1 = Enables the Intel® ICH7 to cause an SCI when the HOT_PLUG_STS bit is set. This

is used to allow the PCI Express ports to cause an SCI due to hot-plug events.

(Ultra

Mobile

Only)

Reserved

THRM_EN — R/W.

0 = Disable.

1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set

the THRM_STS bit and generate a power management event (SCI or SMI).

Bit Description

Intel ® ICH7 Family Datasheet 447

LPC Interface Bridge Registers (D31:F0)

10.8.3.12 SMI_EN—SMI Control and Enable Register

I/O Address: PMBASE + 30h Attribute: R/W, R/W (special), WO

Default Value: 00000000h Size: 32 bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

Note: This register is symmetrical to the SMI status register.

Bit Description

31:26 Reserved

Intel® ICH7DH Only:

EL_SMI_EN — R/W.

0 = Disable

1 = Software sets this bit to enable Intel Quick Resume Technology logic t o cause

SMI#

ICH7 and ICH7R and Mobile/Ultra Mobile Only:

Reserved

24:19 Reserved

18 INTEL_USB2_EN — R/W.

0 = Disable

1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.

17 LEGACY_USB2_EN — R/W.

0 = Disable

1 = Enables legacy USB2 logic to cause SMI#.

16:15 Reserved

PERIODIC_EN — R/W.

0 = Disable.

1 = Enables the Intel® ICH7 to generate an SMI# when the PERIODIC_STS bit

(PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).

TCO_EN — R/W.

0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is

set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN

bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.

1 = Enables the TCO logic to generate SMI#.

NOTE: This bit cannot be written once the TCO_LOCK bit is set.

12 Reserved

MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.

0 = Disable.

1 = Enables ICH7 to trap accesses to the microcontroller range (62h or 66h) and

generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH7 on

PCI, but not forwarded to LPC.

10:8 Reserved

LPC Interface Bridge Registers (D31:F 0 )

448 Intel ® ICH7 Family Datasheet

BIOS Release (BIOS_RLS) — WO.

0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.

1 = Enables the generation of an SCI interrupt for ACPI software when a one is

written to this bit position by BIOS software.

NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.

Software must take great care not to set the BIOS_RLS bit (which causes

GBL_STS to be set) if the SCI handler is not in place.

Software SMI# Tim er Enable (S WS MI _ TM R _ EN ) — R/W.

0 = Disable. Clearing the SWSMI _TMR_EN bit before the timer expires will reset

the timer and the SMI# will not be generated.

1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout

period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is

set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by

software.

5APMC_EN — R/W.

0 = Disable. Writes to the APM_CNT register will not cause an SMI#.

1 = Enable s writes to the APM_CNT register to cause an SMI#.

SLP_SMI_EN — R/W.

0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0

before the software attempts to transition the system into a sleep state by

writing a 1 to the SLP_EN bit.

1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an

SMI#, and the system will not transition to the sleep state based on that write

to the SLP_EN bit.

3LEGACY_USB_EN — R/W.

0 = Disable.

1 = Enables legacy USB circuit to cause SMI#.

BIOS_EN — R/W.

0 = Disable.

1 = Enables the generation of SMI# when ACPI software writes a 1 to the

GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit

(D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to

GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# wil l

be generated when BIOS_EN gets set.

End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI

signal to the proce ssor. This bit must be se t for the Intel® ICH7 to assert SMI# low

to the processor after SMI# has been asserted previously.

0 = Once th e ICH7 asserts SMI# low, the EOS bit is automatically cleared.

1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks before

its assertion. In the SMI handler, the processor should clear all pending SMIs

(by servicing the m and then clearin g their respecti ve status bits ), set the EOS

bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon

detection of an SMI event and the setting of a SMI status bit.

NOTE: ICH7 is able to genera te 1st SMI after reset even though EO S bit is not se t.

Subsequent SMI require EOS bit is set.

GBL_SMI_EN — R/W.

0 = No SMI# will be generated by ICH7. This bit is reset by a PCI reset event.

1 = Enables the generation of SMI# in the system upon any enabled SMI e vent.

NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.

Bit Description

Intel ® ICH7 Family Datasheet 449

LPC Interface Bridge Registers (D31:F0)

10.8.3.13 SMI_STS— SMI Status Register

I/O Address: PMBASE + 34h Attribute: RO, R/WC

Default Value: 00000000h Size: 32-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Core

Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH7 will cause an

SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs

of other registers that have enable bits). The ICH7 uses the same GPE0_EN register (I/

O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI ge neral purpose

input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec.

Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS,

and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns

off the enabled bit for any GPIx inpu t sign als that are not indicated as SCI general-

purpose events at boot, and exit from sleeping states. BIOS should define a dummy

control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.

Bit Description

31:27 Reserved

(Desktop

and Mobile

Only)

SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit

is read only because the sticky st atus and enable bits associat ed with this function

are located in the SPI registers.

(Ultra

Mobile

Only)

Reserved

(Desktop

Only)

Intel® ICH7DH Only:

EL_SMI_STS — RO. This bit will be set if the Intel Quick Resume Technology logic

is generating an SMI#. Writing a 1 to this bit clears this bit t o ‘0’.

ICH7 and ICH7R Only:

Reserved.

(Mobile

Only) Reserved

24:22 Reserved

MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the

SMI. This will occur when the processor or a bus master accesses an assigned

for details on the specific cause of the SMI.

(Desktop

and Mobile

Only)

PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due

to a PCI Express PME event or Hot-Plug event.

(Ultra

Mobile

Only)

Reserved

19 Reserved

LPC Interface Bridge Registers (D31:F 0 )

450 Intel ® ICH7 Family Datasheet

INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of eac h of

the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the

corresponding enable bits. This bit will not be active if the enable bits are not set.

Writes to this bit will have no effect.

LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical O R o f each

of the SMI status bits in the USB2 Legacy Support Register ANDed with the

corresponding enable bits. This bit will not be active if the enable bits are not set.

Writes to this bit will have no effect.

SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by

writing a 1 to it.

0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software

must wait at least 15.63 us aft er the initial assertio n of this bit before clearing

it.

1 = Indicates that the SMI# was caused by:

1. The SMBus Slave receiving a message that an SMI# should be caused, or

2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the

SMBALERT_DIS bit is cleared, or

3. The SMBus Slave receiving a Host Notify message and the

HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or

4. The ICH7 detecting the SMLINK_SLAVE_SMI command while in the S0

state.

SERIRQ_SMI_STS — RO.

0 = SMI# was not caused by th e SERIRQ decoder.

1 = Indicates that the SMI# was caused by the SERIRQ decoder.

NOTE: This is not a sticky bit

PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the

PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the Intel® ICH7

generates an SMI#.

TCO_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = SMI# not caused by TCO logic.

1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake

event.

Device Monitor Status (DEVMON_STS) — RO.

0 = SMI# not caused by Device Monitor.

1 = Set if bit 0 of th e DE VACT_STS regis t er (P MB ASE + 44h) is set. The bi t is not

sticky, so writes to this bit will have no effect.

Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit

by writing a 1 to it.

0 = Indicates that there has been no access to the power management

microcontroller range (62h or 66h).

1 = Set if there has been an access to the power management microcontroller

range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC

Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11).

Note that th is implementation assumes that the Microcontroller is on LPC. If

this bit is set, and the MCSMI_EN bit is also set, the ICH7 will generate an

SMI#.

Bit Description

Intel ® ICH7 Family Datasheet 451

LPC Interface Bridge Registers (D31:F0)

GPI_STS — RO. This bit is a logical O R of the bits in the ALT_GP_SMI_ S TS

registers) and have the corresponding bit set in the ALT_GP_SMI_EN register.

Bits that are not routed to cause an SMI# will have no effect on this bit.

0 = SMI# was not generated by a GPI assertion.

1 = SMI# was generated by a GPI assertion.

GPE0_STS — RO. This bit is a logical OR of the bits 14:10, 8:2, and 0 in the

GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in

the GPE0_EN regist er (PMBASE + 2Ch).

0 = SMI# was not generated by a GPE0 event.

1 = SMI# was generated by a GPE0 event.

PM1_STS_REG — RO . This is an ORs of the bits in the ACPI PM1 Status Register

(offset PMBASE+00h) that can cause an SMI#.

0 = SMI# was not generated by a PM1_STS event.

1 = SMI# was generated by a PM1_STS event.

7 Reserved

6SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = Software SMI# Timer has Not expired.

1 = Set by the hardware when the Software SMI# Timer expires.

APM_STS — R/WC. Software clears this bit by writing a 1 to it.

0 = No SMI# generated by write access to APM Control register with APMCH_EN

bit set.

1 = SMI# was generated by a write access to the APM Control register with the

APMC_EN bit set.

SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit location.

0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.

1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when

SLP_SMI_EN bit is also set.

LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in

the USB Legacy K eyboard/Mou se Control R egisters ANDed with the corresponding

enable bits. This bit will not be active if the enable bits are not set.

0 = SMI# was not generated by USB Legacy event.

1 = SMI# was generated by USB Legacy event.

BIOS_STS — R/WC.

0 = No SMI# generated due to ACPI software requesting attention.

1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS

bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit

(D31:F0:PMBase + 30h:bit 2) and the BIOS _STS bit are set, an SMI# will be

generated. The BIOS_STS bit is cleared when software writes a 1 to its bit

position.

1:0 R eserved

Bit Description

LPC Interface Bridge Registers (D31:F 0 )

452 Intel ® ICH7 Family Datasheet

10.8.3.14 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register

I/O Address: PMBASE +38h Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Resume

10.8.3.15 ALT_GP_SMI_STS—Alternate GPI SMI Status Register

I/O Address: PMBASE +3Ah Attrib ute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: ACPI or Legacy

Power Well: Resume

Bit Description

15:0

Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding

GPIO to cause an SMI#. For these bits to have any effect, the following must be true.

• The corresponding bit in the ALT_GP_SMI_EN register is set.

• The corresponding GPI must be routed in the GPI_ROUT regis t er to cause an SMI.

• The corresponding GPIO must be implemented.

NOTE: Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to

GPIO0.

Bit Description

15:0

Alternate GPI SMI Status — R/WC. These bits report the status of the corres ponding

GPIOs.

0 = Inactive. Software clears this bit by writing a 1 to it.

1 = Active

These bits are sticky. If the following conditions are true , then an SMI# will be

generated and the GPE0_STS bit set:

• The corresponding bit in the ALT_GPI_SMI_EN register ( P MBASE + 38h) is set

• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.

• The corresponding GPIO must be implemented.

All bits are in the resume well. Default for these bits is dependent on the state of the

GPIO pins.

Intel ® ICH7 Family Datasheet 453

LPC Interface Bridge Registers (D31:F0)

10.8.3.16 G PE_CNTL— General Purpose Control Regi ster

I/O Address: PMBASE +42h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI or Legacy

Power We ll: Resume

Bit Description

7:2 Reserved

SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS

bit. This bit is used by hardw a re as th e le v e l i nput si gn al for the SWG PE_STS bit in the

GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to

SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set

back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of

1 will clear SWGPE_STS to 0.

THRM#_POL — R/W. This bit controls the polarity of the THRM # pin needed to set the

THRM_STS bit.

0 = Low value on the THRM# signal will set the THRM_STS bit.

1 = HIGH value on the THRM# signal will set the THRM_STS bit.

LPC Interface Bridge Registers (D31:F 0 )

454 Intel ® ICH7 Family Datasheet

10.8.3.17 DEVACT_STS — Device Activity Status Register

I/O Address: PMBASE +44h Attribute: R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Usage: Legacy Only

Power Well: Core

Each bit indicates if an access has occurred to the corresponding device’ s trap range, or

for bits 6:9 if the corresponding PCI interrupt is active. This register is used in

conjunction with the Periodic SMI# timer to detect any system activity for legacy power

management. The periodic SMI# timer indicates if it is the right time to read the

DEVACT_STS register (PMBASE + 44h).

Note: Software clears bits that are set in this register by writing a 1 to the bit position.

Bit Description

15:13 Reserved

KBC_ACT_STS — R/WC. KBC (60/64h).

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit

location.

11:10 Reserved

PIRQDH_ACT_STS — R/WC. PIRQ[D or H].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of t he corresponding PCI inte rrupts has been active. Clear this bit by

writing a 1 to the bit location.

PIRQCG_ACT_STS — R/WC. PIRQ[C or G].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of t he corresponding PCI inte rrupts has been active. Clear this bit by

writing a 1 to the bit location.

PIRQBF_ACT_STS — R/WC. PIRQ[B or F].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of t he corresponding PCI inte rrupts has been active. Clear this bit by

writing a 1 to the bit location.

PIRQAE_ACT_STS — R/WC. PIRQ[A or E].

0 = The corresponding PCI interrupts have not been active.

1 = At least one of t he corresponding PCI inte rrupts has been active. Clear this bit by

writing a 1 to the bit location.

5:1 Reserved

IDE_ACT_STS — R/WC. IDE Primary Drive 0 and Drive 1.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. The enable bit is in the ATC register

(D31:F1:Offset C0h). Clear this bit by writing a 1 to the bit location.

Intel ® ICH7 Family Datasheet 455

LPC Interface Bridge Registers (D31:F0)

10.8.3.18 SS_CNT— Intel SpeedStep® Technology

Control Register (Mobile/Ultra Mobile Only)

I/O Address: PMBASE +50h Attribute: R/W (special)

Default Value 01h Size: 8-bit

Lockable: No Usage: ACPI/Legacy

Power Well: Core

Note: Writes to this register will initiate an Intel SpeedStep technology transition that

involves a temporary transition to a C3-like state in which the STPCLK# signal will go

active. An Intel SpeedStep technology transition always occur on writes to the

SS_CNT register, even if the value written to SS_STATE is the same as the previous

value (after this “transition” the system would still be in the same Intel SpeedStep

technology state). If the SS_EN bit is 0, then writes to this register will have no effect

and reads will return 0.

10.8.3.19 C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only)

I/O Address: PMBASE +54h Attribute: R/W/RO

Default Value 00000 000h Si ze: 32-bit

Lockable: No Usage: ACPI/Legacy

Power Well: Core

The value in this field increments at the same rate as the Power Management Timer.

This field increments while STP_CPU# is active (i.e. the CPU is in a C3 or C4 state). This

field will roll over in the same way as the Power Management Timer, however the most

significant bit is NOT sticky.

Bit Description

7:1 Reserved

SS_STATE (Intel SpeedStep® technology State) — R/W (Special). When this bit is

read, it returns the last value written to this register. By convention, this will be the

current Intel Spee dStep technology state. W rites to this regi ster causes a change to the

Intel SpeedStep technology state indicated by the value written to this bit. If the new

value for SS_STATE is the same as the previous value, then transition wi ll still occur.

0 = High power state.

1 = Low power state

NOTE: This is only a convention because the transi tion is the same regardless of the

value written to this bit.

Bit Description

31:24 Reserved

23:0

C3_RESIDENCY — RO. The value in this field increments at the same rate as the Power

Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automa tically

resets to 0 at the point when the L vl3 or L vl4 read occurs. If the C3_RESIDENCY_MODE

bit is set, the register does not reset when the Lvl3 or Lvl4 read occurs. In either mode,

it increments while STP_CPU# is active (i.e., the processor is in a C3 or C4 state). This

field will roll over in the same way as the P M Timer, however the most significant bit is

NOT sticky.

Software is responsible for reading this field before performing the Lvl3/4 transition.

Software must also check for rollover if the maximum time in C3/C4 could be

exceeded.

NOTE: Hardware reset is the only reset of this counter field.

LPC Interface Bridge Registers (D31:F 0 )

456 Intel ® ICH7 Family Datasheet

10.9 System Management TCO Registers (D31:F0)

The TCO logic is accessed via registers mapped to the PCI configuration space

(Device 31:Function 0) and the system I/O space. For TCO PCI Configur ation registers,

see LPC Device 31:Function 0 PCI Configuration registers.

TCO Register I/O Map

The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE v alue, which

is, PMBASE + 60h in the PCI configuration space. The following table shows the

mapping of the registers within that 32-byte range. Each register is described in the

following sections.

10.9.1 TCO_RLD—TCO Timer Reload and Current Value Register

I/O Address: TCOBASE +00h Attribute: R/W

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Core

Table 10-12. TCO I/O Register Address Map

TCOBASE

+ Offset Mnemonic Register Name Default Type

00h–01h TCO_RLD TCO Timer Reload and Current

Value 0000h R/W

02h TCO_DAT_IN TCO Data In 00h R/W

03h TCO_DAT_OUT TCO Data Out 00h R/W

04h–05h TCO1_STS TCO1 Status 0000h R/WC, RO

06h–07h TCO2_STS TCO2 Status 0000h R/W, R/WC

08h–09h TCO1_CNT TCO1 Control 0000h

R/W,

R/W

(special),

R/WC

0Ah–0Bh TCO2_CNT TCO2 Control 0008h R/W

0Ch–0Dh TCO_MESSAGE1,

TCO_MESSAGE2 TCO Message 1 and 2 00h R/W

0Eh TCO_WDCNT Watchdog Control 00h R/W

0Fh — Reserved — —

10h SW_IRQ_GEN Software IRQ Generation 11h R/W

11h — Reserved — —

12h–13h TCO_TMR TCO Timer Initial Value 0004h R/W

14h–1Fh — Reserved — —

Bit Description

15:10 Reserved

9:0 TCO Timer Value — R/W. Reading this register will return the current count of the TCO

timer. Writing any value to this register will reload the timer to prevent the timeout.

Intel ® ICH7 Family Datasheet 457

LPC Interface Bridge Registers (D31:F0)

10.9.2 TCO_DAT_IN—TCO Data In Register

I/O Address: TCOBASE +02h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No P ower Well: Core

10.9.3 TCO_DAT_OUT—TCO Data Out Register

I/O Address: TCOBASE +03h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No P ower Well: Core

10.9.4 TCO1_STS—TCO1 Status Register

I/O Address: TCOBASE +04h Attribute: R/W C, RO

Default Value: 0000h Size: 16-bit

Lockable: No P ower Well: Core

(Except bit 7, in RTC)

Bit Description

7:0 TCO Data In Value — R/W. This data register field is used for passing commands from

the OS to the SMI handler. Writes to this register will cause an SMI and set the

SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).

Bit Description

7:0

TCO Data Out Value — R/W. This data register field is used for passing commands

from the SMI handl er to the OS. W rites to this regis ter will set the T C O_INT_STS bit in

the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL

bits.

Bit Description

15:13 Reserved

DMISERR_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Intel ® ICH7 received a DMI special cycle message via DMI indicating that it wants

to cause an SERR#. The software must read the (G)MCH to determin e the reason

for the SERR#.

11 Reserved

DMISMI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH7 rec eived a DMI special cycle message via DMI i n dicating that it wants to

cause an SMI. The software must read the (G)MCH to determine the reason for the

SMI.

DMISCI_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH7 rec eived a DMI special cycle message via DMI i n dicating that it wants to

cause an SCI. The software must read the (G)MCH to determine the reason for the

SCI.

LPC Interface Bridge Registers (D31:F 0 )

458 Intel ® ICH7 Family Datasheet

BIOSWR_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = ICH7 sets this bit and generates and SMI# to indicate an in valid att empt to write to

the BIOS. This occurs when either:

a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or

b) any write is attempted to the BIOS and the BIOSWP bit is also set.

NOTE: On write cycles att empted to the 4 MB lower alias to the BIOS space, the

BIOSWR_STS will not be set.

NEWCENTURY_STS — R/WC. This bit is in the RTC well.

0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.

1 = This bit is set when the Year byte (RT C I/O s pace, index offset 09h ) roll s o v er from

99 to 00. Setting this bit will cause an SMI# (but not a wake event).

NOTE: The NEWCENTURY_STS bit is not valid when the R TC battery is first installed (or

when RTC power has not been maintained). Software can determine if RTC

power has not been maintained by checking the RTC_PWR_STS bit

(D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If

RTC power is determined to have not been maintained, BIOS should set the

time to a legal value and then clear the NEWCENTURY_STS bit.

The NEWCENTUR Y_STS bit may tak e up to 3 R TC clocks for the bit to be cleared

after a 1 is written to the bit to clear it. After writing a 1 to this bit, software

should not exit the SMI handle r until verifying that the bit has actually been

cleared. This will ensure that the SMI is not re-ente r ed.

6:4 Reserved

3TIMEOUT — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by ICH7 to indicate that the SMI was caused by the TCO timer reaching 0.

TCO_INT_STS — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register

(TCOBASE + 03h).

SW_TCO_SMI — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE +

02h).

NMI2SMI_STS — RO.

0 = Cleared by clearing the associated NMI status bit.

1 = Set by the ICH 7 wh en an SMI# occurs because an event occurred that would

otherwise have caused an NMI (because NMI2SMI_EN is set).

Bit Description

Intel ® ICH7 Family Datasheet 459

LPC Interface Bridge Registers (D31:F0)

10.9.5 TCO2_STS—TCO2 Status Register

I/O Address: TCOBASE +06h Attribute: R/W , R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Resume

(Except Bit 0, in RTC)

Bit Description

15:5 Reserved

SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to

go directly into pre-determined sleep state. This av oids r ace conditions. Softw are clears

this bit by writing a 1 to it.

0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit

from S3–S5 states.

1 = Intel ® ICH7 sets this bit to 1 when it receives the SMI message on the SMLink's

Slave Interface.

3 Reserved

BOOT_STS — R/WC.

0 = Cleared by ICH7 based on RSMRST# or by software writing a 1 to this bit. Note

that software should first clear the SECOND_T O_ST S bit before writing a 1 to clear

the BOOT_STS bit.

1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not

fetched the first instruction.

If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the

ICH7 will reboot using t he ‘safe’ multiplier (1111). This allows the system to recover

from a processor frequency multiplier that is too high, and allows the BIOS to check the

BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the

BIOS knows that th e pro cessor has been programmed to an invalid multiplie r.

SECOND_TO_STS — R/WC.

0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.

1 = ICH7 sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently)

set and a second timeout occurred before the TCO_RLD register wa s written. If this

bit is set and the NO_REBOOT config bit is 0, then the ICH7 will reboot the system

after the second timeout. The reboot is done by asserting PLTRST#.

Intrude r Detect (INTRD_DET) — R/WC.

0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.

1 = Set by ICH7 to indicate that an intrusion was detected. This bit is set even if the

system is in G3 state.

NOTE: This bit has a recovery ti me. After writing a 1 to this bit position (to clear it ), the

bit may be read back as a 1 for up 65 microseconds before it is read as a 0.

Software must be aware of this recovery time when reading this bit after

clearing it.

NOTE: If the INTRUDER# sign al is active when the software attempts to clear the

INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again

immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah,

bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes

inactive and then active again, there will not be further SMI’s (because the

INTRD_SEL bits would select that no SMI# be generated).

NOTE: If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is

written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input

signal goes inactive. Note that this is slightly different than a classic sticky bit,

since most sticky bits would remain active indefinitely when the signal goes

active and would immediately go inactive when a 1 is written to the bit.

LPC Interface Bridge Registers (D31:F 0 )

460 Intel ® ICH7 Family Datasheet

10.9.6 TCO1_CNT—TCO1 Control Register

I/O Address: TCOBASE +08h Attribute: R/W, R/W (special), R/WC

Default Value: 0000h Size: 16-bit

Lockable: No Power Well: Core

Bit Description

15:13 Reserved

TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the

TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it

can not be cleared by software writing a 0 to this bit location. A core-well reset is

required to change this bit from 1 to 0. This bit defaults to 0.

TCO Timer Halt (TCO_TMR_HLT) — R/W.

0 = The TCO Timer is enabled to count.

1 = The TCO Timer will halt. It will not count, and thus cann ot reach a value that will

cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent

rebooting and prevent Alert On LAN event messages from being tr ansmitted on the

SMLINK (but not Alert On LAN* heartbe a t messages).

SEND_NOW — R/W (special).

0 = The Int el® ICH7 will clear this bit when it has comple ted sending the mess age.

Software must not set this bit to 1 again until the ICH7 has set it back to 0.

1 = ICH7 sends an Alert On LAN Event message over the SMLINK interface, with the

Software Ev en t bit se t.

Setting the SEND_NOW bit causes the ICH7 integrated LAN controller to reset, which

can have unpredictable side-effects. Unless software protects against these side

effects, software should not attempt to set this bit.

NMI2SMI_EN — R/W.

0 = Normal NMI functionality.

1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent

upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the

following table:

NMI_NOW — R/WC.

0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear

this bit. Another NMI will not be generated until the bit is cleared.

1 = Writ ing a 1 t o th is bit c auses an NMI. This allows the BIOS o r SMI handler to force

an entry to the NMI handler.

7:0 Reserved

NMI_EN GBL_SMI_EN Description

0b 0b No SMI# at all because GBL_SMI_EN = 0

0b 1b SMI# will be caused due to NMI events

1b 0b No SMI# at all because GBL_SMI_EN = 0

1b 1b No SMI# due to NMI because NMI_EN = 1

Intel ® ICH7 Family Datasheet 461

LPC Interface Bridge Registers (D31:F0)

10.9.7 TCO2_CNT—TCO2 Control Register

I/O Address: TCOBASE +0Ah Attribute: R/W

Default Value: 0008h Size: 16-bit

Lockable: No Power Well: Resume

10.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers

I/O Address: TCOBASE +0Ch (Message 1) Attribute: R/W

TCOBASE +0Dh (Message 2)

Default Value: 00h Size: 8-bit

Lockable: No Power Well: Resume

Bit Description

15:6 Reserved

5:4

OS_POLICY — R/W. OS-based software writes to these bits to select the policy that

the BIOS will use afte r the platform resets due the WDT. The following convention is

recommended for the BIOS and OS:

00 = Boot normally

01 = Shut down

10 = Don’t load OS. Hold in pre-boot state and use LAN to determine next step

11 = Reserved

NOTE: These are just scratchpad bits. They sh ould not be reset when the TCO logic

resets the plat form due to Watchdog Timer.

GPIO11_ALERT_DISABLE — R/W. At reset (via RSMRST# asserted) this bit is set

and GPIO11 alerts are disabled.

0 = Enable.

1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus

slave.

2:1

INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes

active.

00 = No interrupt or SMI#

01 = Interrupt (as selected by TCO_INT_SEL).

10 = SMI

11 = Reserved

0 Reserved

Bit Description

7:0 TCO_MESSAGE[n] — R/W. The value written into this register will be sent out via th e

SMLINK interface in the MESSAGE fi eld of th e Aler t On LAN message. BI OS can writ e to

this register to indicate its boot progress which can be monitored externally.

LPC Interface Bridge Registers (D31:F 0 )

462 Intel ® ICH7 Family Datasheet

10.9.9 TCO_WDCNT—TCO Watchdog Control Register

Offset Address: TCOBASE + 0Eh Attribute: R/W

Default Value: 00h Size: 8 bits

Power Well: Resume

10.9.10 SW_IRQ_GEN—Software IRQ Generation Register

Offset Address: TCOBASE + 10h Attribute: R/W

Default Value: 11h Size: 8 bits

Power Well: Core

10.9.11 TCO_TMR—TCO Timer Initial Value R egister

I/O Address: TCOBASE +12h Attribute: R/W

Default Value: 0004h Size: 16-bit

Lockable: No Power Well: Core

Bit Description

7:0

Watchdog Status (WDSTATUS) — R/W. The value written to this register will be

sent in the Alert On LAN message on the SMLINK interface. It can be used by the BIOS

or system management software to indicate more details on the boot progress. This

Bit Description

7:2 Reserved

1IRQ12_CAUSE — R/W. The state of this bit is logi cally ANDed with the IRQ12 signal as

receive d by the Intel® ICH7’s SERIRQ logic. This bit must be a 1 (default) if the ICH7 is

expected to receive IRQ12 assertions from a SERIRQ device.

0IRQ1_CAUSE — R/W. The st ate of this bit is logically ANDed with th e IRQ1 signal as

received by the ICH7’s SERIRQ logic. This bit must be a 1 (default) if the ICH7 is

expected to receive IRQ1 assertions from a SERIRQ device.

Bit Description

15:10 Reserved

9:0

TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the

TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not

be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows

timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of

± 1 tick (0.6s).

The TCO Timer will only count down in the S0 state.

Intel ® ICH7 Family Datasheet 463

LPC Interface Bridge Registers (D31:F0)

10.10 General Purpose I/O Registers (D31:F0)

The control for the general purpose I/O signals is handled through a separate 64-byte

I/O space. The base offset for this space is selected by the GPIOBASE register.

GPIO Register I/O Address Map

Table 10-13. Registers to Control GPIO Address Map

GPIOBASE

+ Offset Mnemonic Register Name Default Access

General Registers

00h–03h GPIO_USE_SEL GPIO Use Select

1F3FF7FFh

(desktop

only) /

1F2AF7FFh

(mobile/Ultra

Mobile only)

R/W

04h–07h GP_IO_SEL GPIO Input/Output Select E0E8FFFFh R/W

08h–0Bh — Reserved — —

0Ch–0Fh GP_LVL GPIO Level for Input or Output 02FE0000h R/W

10h–13h Reserved — —

Output Control Registers

14h–17h — Reserved — —

18h–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W

1Ch–1Fh — Reserved — —

Input Control Registers

20–2Bh — Reserved — —

2C–2Fh GPI_INV GPIO Signal Invert 00000000h R/W

30h–33h GPIO_USE_SEL2 GPIO Use Select 2 [63:32]

000300FFh

(desktop

only) /

000300FEh

(mobile/Ultra

Mobile only)

R/W

34h–37h GP_IO_SEL2 GPIO Input/Output Select 2

[63:32] 000000F0h R/W

38h–3Bh GP_LVL2 GPIO Level for Input or Output 2

[63:32] 00030003h R/W

LPC Interface Bridge Registers (D31:F 0 )

464 Intel ® ICH7 Family Datasheet

10.10.1 GPIO_USE_SEL—GPIO Use Select Register

Offset Address: GPIOBASE + 00h Attribute: R/W

Default Value: 1F3FF7F Fh (Des ktop only) Size: 32-bit

1F2AF7FFh (Mobile/Ultra Mobile only)

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

10.10.2 GP_IO_SEL—GPIO Input/Output Select Register

Offset Address: GPIOBASE +04h Attribute: R/W

Default Value: E0E8FFFFh Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

Bit Description

31:0

GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding

GPIO (if it exists) to be used as a GPIO, rather than for the native function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

NOTES:

1. The following bits are always 1 because they are unmuxed: 6:10,12:15, 24:25

2. The following bits are not implemented because they are determined by the

Desktop Only /Mobile Only/Ultra Mobile configuration: 16, 18, 20, 32

3. If GPIO[n] does not exist, then t he bit in this register will always read as 0 and

writes will have no effect.

4. After a full reset (RSMRST#) all multiplexed signals in the resume and core

wells are configured as their default function. After just a PLTRST#, the GPIO in

the core well are configured as their default function.

5. When configured to GPIO mode, the multiplexing logic will present the inactive

state to native logic that uses the pin as an input.

6. All GPIOs are reset to the default state by CF9h reset except GPIO24

Bit Description

31:0

GP_IO_SEL[31:0] — R/W. When configured in native mode (GPIO_USE_SEL[n] is

0), writes to these bits have no effect. The value reported in this register is undefined

when programmed as native mode.

0 = Output. The corresponding GPIO signal is an output.

1 = Input. The corresponding GPIO signal is an input.

Intel ® ICH7 Family Datasheet 465

LPC Interface Bridge Registers (D31:F0)

10.10.3 GP_LVL—GPIO Level for Input or Output Register

Offset Address: GPIOBASE +0Ch Attribute: R/W

Default Value: 02FE0000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

10.10.4 GPO_BLINK—GPO Blink Enable Register

Offset Address: GPIOBASE +18h Attribute: R/W

Default Value: 00040000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

NOTE: (Desktop Only) GPIO18 will blink by default immediately after reset. This signal could be

connected to an LE D to i ndicate a failed bo ot (by pr ogr amming BIOS to clear GP_BLINK18

after successful POST).

Bit Description

31:0

GP_LVL[31:0]— R/W: If GPIO[n] is programmed to be an output (via the

corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit

can be updated by software to drive a high or low value on the output pin. 1 = high,

0 = low.

If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the

state of the input signal (1 = high, 0 = low.) and writes will have no effect.

When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have

no effect. The value reported in this register is undefined when programmed as

native mode.

Bit Description

31:0

GP_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding

GPIO signal is programmed as an input.

0 = The corresponding GPIO will function normally.

1 = If the corresponding GPIO is programmed as an output, the output signal will

blink at a rate of approximately once per second. The high and low times have

approximately 0. 5 se cond s e ach . The GP _LVL bit is not altered when this bit is

set.

The value of the corresponding GP_LVL bit remains unchanged during the blink

process, and does not effect the blink in any way. The GP_LVL bit is not altered

when programmed to blink. It will remain at its previous value.

These bits correspond to GPIO in the Resume well. These bits revert to the default

value based on RSMRST# or a write to the CF9h register (but not just on

PLTRST#).

LPC Interface Bridge Registers (D31:F 0 )

466 Intel ® ICH7 Family Datasheet

10.10.5 GPI_INV—GPIO Signal Invert Register

Offset Address: GPIOBASE +2Ch Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lockable: No Power Well: Core for 0:7, 16:23,

Resume for 8:15, 24:31

10.10.6 GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]

Offset Address: GPIOBASE +30h Attribute: R/W

Default Value: 000300FFh (Desktop Only) Size: 32-bit

000300FEh (Mobile/Ultra Mobile Only)

Lockable: No Power Well: CPU I/O for 17, Core for

16, 7:0

Bit Description

31:0

GP_INV[n] — R/W. Input Inversion: This bit only has effect if the corresponding

GPIO is used as an input and used by the GPE logic, where the polarity matters. When

set to 1, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit

has no effect on the value that is reported in the GP_LVL register.

These bits are used to allow both active-low and active-high inputs to cause SMI# or

SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI

clocks to ensure detection by the Intel® ICH7. In the S3, S4 or S5 state s th e input

signal must be active for at least 2 RTC clocks to ensure detection. The setting of these

bits has no effect if the corresponding GPIO is programmed as an output. These bits

correspond to GPI that are in the resume well, and will be reset to their default values

by RSMRST# or by a write to the CF9h register.

0 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input

pin to be high.

1 = The corresponding GPI_STS bit is set when the ICH7 detects the state of the input

pin to be low.

Bit Description

17:16,

7:0

GPIO_USE_SEL2[49:48, 39:32] Bits[17: 16, 7:0]— R/W. Each bi t in this registe r

enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the

native function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

After a full reset (RSMRST#), all multiplexed signals in the resume and core wells are

configured as a GPIO rather than as their native function. After just a PLTRST#, the

GPIO in the core well are configured as GPIO.

NOTES:

1. The following bits are not implemented be cause there is no corresponding

GPIO: 31:18, 15:8.

2. The following bits are n ot implemented because they are determined by the

Desktop/Mobile/Ultra Mobile configuration: 0

Intel ® ICH7 Family Datasheet 467

LPC Interface Bridge Registers (D31:F0)

10.10.7 GP_IO_SEL2—GPIO Input/Output Select 2

Offset Address: GPIOBASE +34h Attribute: R/W

Default Value: 000000F0h Size: 32-bit

Lockable: No Power W ell: CPU I/O for 17, Core for

16, 7:0

10.10.8 GP_LVL2—GPIO Level for Input or Output 2

Offset Address: GPIOBASE +38h Attribute: R/W

Default Value: 00030003h Size: 32-bit

Lockable: No Power W ell: CPU I/O for 17, Core for

16:0

Bit Description

31:18,

15:8 Always 0. No corresponding GPIO.

17:16,

7:0

GP_IO_SEL2[49:48, 39:32] — R/W.

0 = GPIO signal is programmed as an output.

1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is

programmed as an input.

Bit Description

31:18,

15:8 Reserved. Read -only 0

17:16,

7:0

GP_LVL[49:48, 39:32] — R/W.

If GPIO[n] is progr am med to be an output (via t he correspondin g bit in the GP _IO_SEL

high or low value on the output pin. 1 = high, 0 = low.

If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the

state of the input signal (1 = high, 0 = low.) and writes will have no effect.

When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no

effect. The value reported in this register is undefined when programmed as native

mode.

LPC Interface Bridge Registers (D31:F 0 )

468 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 469

UHCI Controllers Registers

11 UHCI Controllers Registers

11.1 PCI Configuration Registers

(USB—D29:F0/F1/F2/F3)

Note: Register address locations that are not shown in Table 11-1 and should be treated as

Reserved (see Section 6.2 for details).

NOTE: Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update for the value

of the Revision ID Register

Table 11-1. UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2/F3)

Offset Mnemonic Register Name Function 0

Default Function 1

Default Function 2

Default Function 3

Default Type

00–01h VID Vendor Identification 8086h 8086h 8086h 8086h RO

02–03h DID Device Identification See register

description See register

description

See

description

See

description RO

04–05h PCICMD PCI Command 0000h 0000h 0000h 0000h R/W, RO

06–07h PCISTS PCI Status 0280h 0280h 0280h 0280h R/WC, RO

08h RID Revision Identification See register

description

See

description

See

description

See

description RO

09h PI Programming

Interface 00h 00h 00h 00h RO

0Ah SCC Sub Class Code 03h 03h 03h 03h RO

0Bh BCC Base Class Code 0Ch 0Ch 0Ch 0Ch RO

0Dh MLT Master Latency Timer 00h 00h 00h 00h RO

0Eh HEADTYP Header Type 80h 00h 00h 00h RO

20–23h BASE Base Address 00000001h 000000 01h 00000001h 00000001h R/W, RO

2C–2Dh SVID Subsystem Vendor

Identification 0000h 0000h 0000h 0000h R/WO

2E–2Fh SID Subsystem

Identification 0000h 0000h 0000h 0000h R/WO

3Ch INT_LN Interrupt Line 00h 00h 00h 00h R/W

3Dh INT_PN Interrupt P in See register

description.

See

description.

See

description.

See

description. RO

60h USB_RELNUM Serial Bus Release

Number 10h 10h 10h 10h RO

C0–C1h USB_LEGKEY USB Legacy

Keyboard/Mouse

Control 2000h 2000h 2000h 2000h R/W, RO

R/WC

C4h USB_RES USB Resume Enable 00h 00h 00h 00h R/W

C8h CWP Core Well Policy 00h 00h 00h 00h R/W

UHCI Controllers Registers

470 Intel ® ICH7 Family Datasheet

11.1.1 VID—Vendor Identification Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

11.1.2 DID—Device Identification Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 02h–03h Attribute: RO

Default Value: UHCI #1 = See bi t description Size: 16 bits

UHCI #2 = See bit description

UHCI #3 = See bit description

UHCI #4 = See bit description

11.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/

F3)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel

Bit Description

15:0 Device ID — RO. This is a 16 -bit value assigned to the Intel® ICH7 USB universal host

controllers. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fa mily Specificatio n Update

for the value of the Device ID Register.

Bit Description

15:11 Reserved

Interrupt Disable — R/W.

0 = Enable. The function is able to generate its interrupt to the interrupt controller.

1 = Disable . The function is not capable of generating interrupts.

NOTE: The corresponding Interrupt Status bit is not affected by the interrupt enable.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8 SERR# Enable — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6 Parity Error Response (PER) — RO. Hardwired to 0.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2Bus Master Enable (BME) — R/W.

0 = Disable

1 = Enable. Intel® ICH7 can act as a master on the PCI bus for USB transfers.

1 Memory Space Enable (MSE) — RO. Hardwired to 0.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disable

1 = Enable accesses to the USB I/O registers. The Base Address register for USB s hould

be programmed before this bit is set.

Intel ® ICH7 Family Datasheet 471

UHCI Controllers Registers

11.1.4 PCISTS—PCI Status Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 06 h–07h Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

11.1.5 RID—Revision Identification Register

(USB—D29:F0/F1/F2/F3)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Set when a data parity error data parity error is detected on writes to the UHCI

14 Reserved as 0b. Read Only.

13 Received Master Abort (RMA) — R/WC.

0 = No master abort generated by USB.

1 = USB, as a master, generated a master abort.

12 Reserved. Always read as 0.

Signaled Target Abort (STA) — R/WC.

0 = Intel ® ICH7 did Not terminate transaction for USB function with a target abort.

1 = USB function is targeted with a transaction that the ICH7 terminates with a target

abort.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for

DEVSEL# assertion. These read only bits indicate the ICH7's DEVSEL# timing when

performing a positive decode. ICH7 generates DEVSEL# with medium timing for USB.

8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.

7 Fast Back to Back Cap a ble (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable — RO. Hardwired to 0.

4 Capabilities List — RO. Hardwired to 0.

Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the

input of the enable/disable logic.

0 = Interrupt is de-asserted.

1 = Interrupt is asserted.

The value reported in this bit is independent of the value in the Interrupt Enable bit.

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

UHCI Controllers Registers

472 Intel ® ICH7 Family Datasheet

11.1.6 PI—Programming Interface Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

11.1.7 SCC—Sub Class Code Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

11.1.8 BCC—Base Class Code Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 0Bh Attribute: RO

Default Value: 0Ch Size: 8 bits

Bit Description

7:0 Programming Interface — RO.

00h = No specific register level programming interface defined.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = USB host controller.

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial Bus controller.

Intel ® ICH7 Family Datasheet 473

UHCI Controllers Registers

11.1.9 MLT—Master Latency Timer Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

11.1.10 HEADTYP—Header Type Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 0Eh Attribute: RO

Default Value: FN 0: 80h Size: 8 bits

FN 1: 00h

FN 2: 00h

FN 3: 00h

For functions 1, 2, and 3, this register is hardwired to 00h. For function 0, bit 7 is

determined by the v alues in the USB Function Disable bits (11:8 of the Function Disable

Bit Description

7:0 Master Latency Timer (MLT) — RO. The USB controller is implemented internal to the

Intel® ICH7 and not arbitr ated as a PCI device. Therefore the dev ice does not require a

Master Latency Timer.

Bit Description

Multi-Function Device — RO.

0 = Single-function device.

1 = Multi-function device.

Since the upper functions in this device can be individually hidden, this bit is based on

the function-disable bits in Chipset Config Space: Offset 3418h as follows:

6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration

layout.

D29:F7_Disa

ble (bit 15) D29:F3_Disa

ble (bit 11) D29:F2_Disa

ble (bit10) D29:F1_Disa

ble (bit 9)

Multi-Function

Device (this

bit)

0b X X X 1

X0bX X 1

XX0bX 1

XXX0b 1

1111 0

UHCI Controllers Registers

474 Intel ® ICH7 Family Datasheet

11.1.11 BASE—Base Address Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

11.1.12 SVID — Subsystem Vendor Identification Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

11.1.13 SID — Subsystem Identification Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Bit Description

31:16 Reserved

15:5 Base Address — R/W. Bits [15:5] correspond to I/O address signals AD [15:5],

respectively. This gives 32 bytes of relocatable I/O space.

4:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate that the base address

field in this register maps to I/O space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/WO. BIOS sets the value in this register to identify

the Subsystem Vendor ID. The USB_SVID register, in combination wit h the USB

Subsystem ID register, enables the operating system to distinguish each subsystem

from the others.

NOTE: The software can write to this register only once per core well reset. Writes

should be done as a single, 16-bit cycle.

Bit Description

15:0

Subsystem ID (SID) — R/WO. BIOS sets the value in this register to identify the

Subsystem ID. The SID register, in combination with the SVID register (D29:F0/F1 /F2/

F3:2C), enables the operating syst em to distinguish e ach subsystem from other(s). Th e

value read in this register is the same as what was written to the IDE_SID register.

NOTE: The software can write to this register only once per core well reset. Writes

should be done as a single, 16-bit cycle.

Intel ® ICH7 Family Datasheet 475

UHCI Controllers Registers

11.1.14 INT_LN—Interrupt Line Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

11.1.15 INT_PN—Interrupt Pin Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 3Dh Attribute: RO

Default Value: Function 0: See Descripti on Size: 8 bits

Function 1: See Description

Function 2: See Description

Function 3: See Description

11.1.16 USB_RELNUM—Serial Bus Release Number Register

(USB—D29:F0/F1/F2/F3)

Address Offset: 60h Attribute: RO

Default Value: 10h Size: 8 bits

Bit Description

7:0 Interrupt Line (INT_LN) — RO. This data is not u sed by the Intel® ICH7. It is to

communicate to software the interrupt line that the interrupt pin is connected to.

Bit Description

7:0

Interrupt Line (INT_LN) — RO. This value tells the software which interrupt pin each

USB host controller uses. The upper 4 bits are hardwired to 0000b; the lower 4 bits are

determine by the Interrupt Pin default values that are programmed in the memory-

mapped configuration space as follows:

Function 0 D29IP.U0P (Chipset Config Registers:Offset 3108:bits 3:0)

Function 1 D29IP.U1P (Chipset Config Registers:Offset 3108:bits 7:4)

Function 2 D29IP.U2P (Chipset Config Registers:Offset 3108:bits 11:8)

Function 3 D29IP.U3P (Chipset Config Registers:Offset 3108:bits 15:12)

NOTE: This does not determine the mapping to the PIRQ pins.

Bit Description

7:0 Serial Bus Release Number — RO .

10h = USB controller su pports the USB Specification, Release 1.0.

UHCI Controllers Registers

476 Intel ® ICH7 Family Datasheet

11.1.17 USB_LEGKEY—USB Legacy Keyboard/Mouse Control

Address Offset: C0h–C1h Attribute: R/W, R/WC, RO

Default Value: 2000h Size: 16 bits

This register is implemented separately in each of the USB UHCI functions. However,

the enable and status bits for the trapping logic are OR’d and shared, respectively,

since their functionality is not specific to any one host controller.

Bit Description

SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if

the event occurred. Note that even if the corresponding enable bit is not set in bit 7,

then this bit will still be active. It is up to the SMM code to use the enable bit to

determine the exact cause of the SMI#.

0 = Sof tware clears this bit by writing a 1 to th e bit location in any of the contr ollers.

1 = Event Occurred

14 Reserved

PCI Interrupt Enable (USBPIRQEN) — R/W. This bit is used to prevent the USB

controller from generating an in terrupt due to transactions on its ports. Note that, when

disabled, it will probably be configured to generate an SMI using bit 4 of this register.

Default to 1 for compatibility with older USB software.

0 = Disable

1 = Enable

SMI Caused by USB Interrupt (SMIBYUSB) — RO. This bit indicates if an interrupt

event occ urred from this con troller. The interrupt from the controller i s taken before the

enable in bit 13 has any effect to create this read-only bit. Note that even if the

corresponding enable bit is not set in Bit 4, this bit may still be active. It is up to the

SMM code to use the enable bit to determine the exact cause of the SMI#.

0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit

will have no effect.

1 = Event Occurred.

SMI Caused by Port 64 Write (TRAPBY64W) — R/ WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will

still be active. It is up to the SMM code to use the enable bit to determine the exact

cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h

writes to complete without setting this bit.

0 = Sof tware clears this bit by writing a 1 to th e bit location in any of the contr ollers.

1 = Event Occurred.

SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will

still be active. It is up to the SMM code to use the enable bit to determine the exact

cause of the SMI#.

0 = Sof tware clears this bit by writing a 1 to th e bit location in any of the contr ollers.

1 = Event Occurred.

SMI Caused by Port 60 Write (TRAPBY60W) — R/ WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will

still be active. It is up to the SMM code to use the enable bit to determine the exact

cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h

writes to complete without setting this bit.

0 = Sof tware clears this bit by writing a 1 to th e bit location in any of the contr ollers.

1 = Event Occurred.

Intel ® ICH7 Family Datasheet 477

UHCI Controllers Registers

SMI Caused by Port 60 Read ( TRAPBY60R) — R/WC. This bit indicates if the event

occurred. Note that even if the corresponding enable bit is n ot set in the bit 0, then this

bit will still be active. It is up to the SMM code to use the enable bit to determine the

exact cause of the SMI#.

0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.

1 = Event Occurred.

SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI

at the end of a pass-through. This can occur if an SMI is generated in the middle of a

pass-through, and needs to be serviced later.

0 = Disable

1 = Enable

Pass Through State (PSTATE) — RO.

0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to

1 = Indicates that the state mach ine is in the middle of an A20GATE pass-through

sequence.

A20Gate Pass-Through Enable (A20PASSEN) — R/W.

0 = Disable.

1 = Enable. Allows A20GA TE seque nce Pass-Through function. A specifi c cycle sequence

involving writes to port 60h and 64h does not result in the setting of the SMI status

bits.

4SMI on USB IRQ Enable (USBSMIEN) — R/W.

0 = Disable

1 = Enable. USB interrupt will cause an SMI event.

3SMI on Port 64 Writes Enable (64WEN) — R/W.

0 = Disable

1 = Enable . A 1 in bit 11 will cause an SMI event.

2SMI on Port 64 Reads Enable (64REN) — R/W.

0 = Disable

1 = Enable . A 1 in bit 10 will cause an SMI event.

1SMI on Port 60 Writes Enable (60WEN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 9 will cause an SMI event.

0SMI on Port 60 Reads Enable (60REN) — R/W.

0 = Disable

1 = Enable. A 1 in bit 8 will cause an SMI event.

Bit Description

UHCI Controllers Registers

478 Intel ® ICH7 Family Datasheet

11.1.18 USB_RES—USB Resume Enable Register

(USB—D29:F0/F1/F2/F3)

Address Offset: C4h Attribute: R/W

Default Value: 00h Size: 8 bits

11.1.19 CWP—Core Well Policy Register

(USB—D29:F0/F1/F2/F3)

Address Offset: C8h Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

7:2 Reserved

PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.

0 = The USB controller will not look at this port for a wakeup event.

1 = The USB controller will monitor this port for remote wakeup and connect/

disconnect events.

PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.

0 = The USB controller will not look at this port for a wakeup event.

1 = The USB controller will monitor this port for remote wakeup and connect/

disconnect events.

Bit Description

7:1 Reserved

Static Bus Master Status Policy Enable (SBMSPE) — R/W.

0 = The UHCI host controller dynamically sets the Bus Master status bit (Power

Management 1 Statu s Register,[PMBASE+00h], bit 4) based on the memory

accesses that are scheduled. For mobile/Ultra Mobile only, the default setting

provides a more accurate indication of snoopable memory accesses in order to help

with software-invoked entry to C3 and C4 power states.

1 = The UHCI host controller statically forces the Bus Master Status bit in power

management space to 1 whenever the HCHalted bit (USB Status Register,

Base+02h, bit 5) is cleared.

NOTE: The PCI Power Management registers are enabled in the PCI Device 31:

Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte

aligned).

Intel ® ICH7 Family Datasheet 479

UHCI Controllers Registers

11.2 USB I/O Registers

Some of the read/write register bits that deal with changing the state of the USB hub

ports function such that on read back they reflect the current state of the port, and not

necessarily the state of the last write to the register. This allows the software to poll the

state of the port and wait until it is in the proper state before proceeding. A host

controller reset, global reset, or port reset will immediately terminate a transfer on the

affected ports and disable the port. This affects the USBCMD register, bit 4 and the

PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.

NOTES:

1. These registers are WORD writable only. Byte writes to these registers have unpredictable

effects.

Table 11-2. USB I/O Registers

BASE +

Offset Mnemonic Register Name Default Type

00–01h USBCMD USB Command 0000h R/W

02–03h USBSTS USB Status 0020h R/WC

04–05h USBINTR USB Interrupt Enable 0000h R/W

06–07h FRNUM Frame Number 0000h R/W (see Note 1)

08–0Bh FRBASEADD Frame List Base Address Undefined R/W

0Ch SOFMOD Start of Frame Modify 40h R/W

0D–0Fh — Reserved — —

10–11h PORTSC0 Port 0 Status/Control 0080h R/W C, RO, R/W

(see Note 1)

12–13h PORTSC1 Port 1 Status/Control 0080h R/W C, RO, R/W

(see Note 1)

UHCI Controllers Registers

480 Intel ® ICH7 Family Datasheet

11.2.1 USBCMD—USB Command Regi ster

I/O Offset: Base + (00h–01h) Attribute: R/W

Default Value: 0000h Size: 16 bits

The Command Register indicates the command to be executed by the serial bus host

controller. Writing to the register causes a command to be executed. The table

following the bit description provides additional information on the operation of the

Run/Stop and Debug bits.

Bit Description

15:7 Reserved

Loop Back Test Mode — R/W.

0 = Disable loop back t e st mode.

1 = Intel® ICH7 is in loop back test mode. When both ports are connected together, a

write to one port will be seen on the other port and the data will be stored in I/O

offset 18h.

Max Packet (M AX P) — R/W. This bit selects the maximum packet size that can be

used for full speed bandwidth reclamation at the end of a frame. This value is used by

the host co ntroller to de termine wh ether it should initiate another tr ansaction based on

the time remaining in the SOF counter. Use of reclamation packets larger than the

programmed size will cause a Babble error if executed during the critical window at

frame end. The Babble error results in the offending endpoint being stalled. Software is

responsible for ensuring that any packet which could be executed under bandwidth

reclamation be within this size limit.

0 = 32 bytes

1 = 64 bytes

Configure Flag (CF) — R/W. This bit has no effect on the hardware. It is provided only

as a semaphore service for software.

0 = Indicates that software has not completed host controller configuration.

1 = HCD software sets this bit as the last action in its process of configuring the host

controller.

Software Debug (SWDBG) — R/W. The SWDBG bit must only be manipulated when

the controller is in the stopped state. This can be determined by checking the HCHalted

bit in the USBSTS register.

0 = Normal Mode.

1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after

the completion of each U SB transaction. The next transaction is executed when

software sets the Run/Stop bit back to 1.

Force Global Resume (FGR) — R/W.

0 = Software re sets this bit to 0 after 20 ms has elapsed to stop sending the Global

Resume signal. At that time all USB devices should be ready for bus activity. The 1

to 0 transition causes the po rt to send a low speed EOP signal. This bit will remain

a 1 until the EOP has completed.

1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1

when a resume event (connect, disconnect, or K-state) is detected while in global

suspend mode.

Intel ® ICH7 Family Datasheet 481

UHCI Controllers Registers

Enter Global Suspend Mode (EGSM) — R/W.

0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes

this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or

after writing bit 4 to 0.

1 = Host controller enters the Global Suspend mode. No USB transactions occur during

this time. The Host controller is able to receive resume signals from USB and

interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared

prior to setting this bit.

Global Re s e t (GRESET) — R/W.

0 = This bit is reset by the software after a mi nimum of 10 ms h as elapsed as spe cified

in Chapter 7 of the USB Specificatio n.

1 = Global R eset. The host contr oller sends the global reset s ignal on the USB and then

resets all its logic, including the internal hub registers. The hub registers are reset

to their power on state. Chip Hardware Reset has the same effect as Global Reset

(bit 2), except that the host controller does not send the Global Reset on USB.

Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers

are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET

affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port.

HCRESET resets the state machines of the host controller including the Connect/

Disconnect state machine (one for ea ch port). When the Connect/Disconnect state

machine is rese t, the output that signals connect/disconnect are negated to 0,

effectively signaling a disconnect, even if a device is attached to the port. This virtual

disconnect causes the port to be disabled. This disconnect and disabling of the port

causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the

PORT SC (D29:F0/ F1/F2/F3: BASE + 10h) to get set. The dis connect also causes bit 8 of

PORTSC to reset. About 64 bit times after HCRESET goes to 0, the connect and low-

speed detect will take place, and bits 0 and 8 of the PORTSC will change accordingly.

0 = Reset by the host controller when the reset process is complete.

1 = Reset . When this bit is set, the host controller module resets its internal timers,

counters, state machines, etc. to their initial value. Any transaction currently in

progress on USB is immediately terminated.

Run/Stop (RS) — R/W. When set to 1, the ICH7 proceeds with execution of the

schedule. The ICH7 continues execution as long as this bit is set. When this bit is

cleared, the ICH7 complete s the current tr ans action on th e USB and then h alts. The HC

Halted bit in the status register indicates when the host controller has finished the

transaction and has entered the stopped state. The host controller clears this bit when

the following fatal errors occur: consistency check failure, PCI Bus errors.

0 = Stop

1 = Run

NOTE: This bit should only be cleared if there are no active Transaction Descriptors in

the executable schedule or software will reset the host controller prior to setting

this bit again.

Bit Description

UHCI Controllers Registers

482 Intel ® ICH7 Family Datasheet

When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1),

the single stepping software debug operation is as follows:

To Enter Software Debug Mode:

1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0.

2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1.

3. HCD sets up the correct command list and Start Of Fr ame value for starting point in

the Frame List Single Step Loop.

4. HCD sets Run/Stop bit to 1.

5. Host controller executes next active TD, sets Run/Stop bit to 0, and stops.

6. HCD reads the USBCMD register to check if the single step execution is completed

(HCHalted=1).

7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to

end Software De bu g mod e.

8. HCD ends Software Debug mode by setting SWDBG bit to 0.

9. HCD sets up normal command list and Frame List table.

10.HCD sets Run/Stop bit to 1 to resume normal schedule execution.

In Software Debug mode, when the Run/Stop bit is set, the host controller starts.

When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the

HCHalted bit in the USBSTS register (bit 5) is set.

The SW Debug mode skips over inactive TDs and only halts after an active TD has been

executed. When the last active TD in a frame has been executed, the host controller

waits until the next SOF is sent and then fetches the first TD of the next frame before

halting.

Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation

SWDBG

(Bit 5) Run/Stop

(Bit 0) Description

If executing a command, the host controller completes the command

and then stops. The 1.0 ms frame counter is reset and command list

execution resumes from start of frame using the frame list pointer

selected by the current value in the FRNU M register. (While Run/

Stop=0, the FRNUM register (D29:F0/F1/F2/F3:BASE + 06h) can be

reprogrammed).

Execution of the command list resumes from Start Of Frame using the

frame list pointer selected by the current value in the FRNUM register.

The host controller remains running until the Run/Stop bit is cleared

(by software or hardware).

If executing a command, the host controller completes the command

and then stops and the 1.0 ms frame counter is frozen at its current

value. All status are preserved. The host controller begins execution

of the command list from where it left off when the Run/Stop bit is

set.

Execution of the command list resumes from where the previous

execution stopped. The Run/Stop bit is set to 0 by the host controller

when a TD is being fetched. This causes the host controller to stop

again after the executio n of the TD (single step). When the host

controller has completed execution, the HC Halted bi t in the Status

Intel ® ICH7 Family Datasheet 483

UHCI Controllers Registers

This HCHalted bit can also be used outside of Software Debug mode to indicate when

the host controller has detected the Run/Stop bit and has completed the current

transaction. Outside of the Softw are Debug mode, setting the Run/Stop bit to 0 always

resets the SOF counter so that when the Run/Stop bit is set the host controller starts

over again from the frame list location pointed to by the Frame List Index (see FRNUM

11.2.2 USBSTS—USB Status Register

I/O Offset: Base + (02h–03h) Attribute: R/WC

Default Value: 0020h Size: 16 bits

This register indicates pending interrupts and various states of the host controller. The

status resulting from a transaction on the serial bus is not indicated in this register.

Bit Description

15:6 Reserved

HCHalted — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller has stopped executing as a result of the Run/Stop bit being set

to 0, either by software or by the host controller hardware (debug mode or an

internal error). Default.

Host Controller Process Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller has detected a fatal error. This indicates that the host controller

suffered a consistency check failure while processing a Transfer Descriptor. An

example of a consistency check failure would be finding an invalid PID field while

processing the packet header portion of the TD. When this error occurs, the host

controller clears the Run/Stop bit in the Command register (D29:F0/F1/F2/

F3:BASE + 00h, bi t 0) t o prev ent further schedule execution. A hardware interrupt

is generated to the system.

Host System Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = A serious error occurred during a host system access involving the host controller

module. In a PCI system, conditions that set this bit to 1 include PCI Parity error,

PCI Master Abort, and PCI Target Abort. When this error occurs, the host controller

clears the Run/Stop bit in the Command register to prevent further execution of

the scheduled TDs. A hardware interrupt is generated to the system.

Resume Detect (RSM_DET) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller received a “RESUME” signal from a USB device. This is only

valid if the Host controller is in a global suspend state (Command register, D29:F0/

F1/F2/F3:BASE + 00h, bit 3 = 1).

USB Error Interrupt — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Completion of a USB transaction resulted in an error condition (e.g., error counter

underflow). If the TD on which the error interrupt occurred also had its IOC bit

(D29:F0/F1/ F2/F3:BASE + 04h, bit 2) set, both this bit and Bit 0 are set.

USB Interrupt (USBINT) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The host controller sets this bit when the cause of an interrupt is a completion of a

USB transaction whose Transfer Descriptor had its IOC bit set. Also set when a

short packet is detected (actual length field in TD is less than maximum length field

in TD), and short packet detection is enabled in that TD.

UHCI Controllers Registers

484 Intel ® ICH7 Family Datasheet

11.2.3 USBINTR—USB Interrupt Enable Register

I/O Offset: Base + (04h–05h) Attribute: R/W

Default Value: 0000h Size: 16 bits

This register enables and disables reporting of the corresponding interrupt to the

software. When a bit is set and the corresponding interrupt is active, an interrupt is

generated to the host. Fatal errors (host controller processor error, (D29:F0/F1/F2/

F3:BASE + 02h, bit 4, USBS TS Register) cannot be disabled by the host controller.

Interrupt sources that are disabled in this register still appear in the Status Register to

allow the software to poll for events.

11.2.4 FRNUM—Frame Number Register

I/O Offset: Base + (06–07h) Attribute: R/W (Writes must be Word Writes)

Default Value: 0000h Size: 16 bits

Bits [10:0] of this register contain the current frame number that is included in the

frame SOF packet. This register reflects the count value of the internal frame number

counter. Bits [9:0] are used to select a particular entry in the Frame List during

scheduled execution. This register is updated at the end of each frame time.

This register must be written as a word. Byte w ri tes are not supported. Th is regis t e r

cannot be written unless the host controller is in the ST OPPED state as indicated by the

HCHalted bit (D29:F0/F1/F2/F3:BASE + 02h, bit 5). A write to this register while the

Run/Stop bit is set (D29:F0/F1/F2/F3:BASE + 00h, bit 0) is ignored.

Bit Description

15:5 Reserved

4Scratchpad (SP) — R/W.

3Short Packet Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

2Interrupt on Complete Enable (IOC) — R/W.

0 = Disabled.

1 = Enabled.

1Resume Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

0Timeout/CRC Interrupt Enable — R/W.

0 = Disabled.

1 = Enabled.

Bit Description

15:11 Reserved

10:0

Frame List Current Index/Frame Number — R/W. This field provides the frame

number in the SOF Frame. The value in this register increments at the end of each time

frame (approximately every 1 ms). In addition, bits [9: 0] are used for the Frame List

current index and correspond to memory address signals [11:2].

Intel ® ICH7 Family Datasheet 485

UHCI Controllers Registers

11.2.5 FRBASEADD—Frame List Base Address Register

I/O Offset: Base + (08h–0Bh) Attribute: R/W

Default Value: Undefined Size: 32 bits

This 32-bit register contains the beginning address of the Frame List in the system

memory. HCD loads this register prior to starting the schedule execution by the host

controller. When written, only the upper 20 bits are used. The lower 12 bits are written

as 0’s (4-KB alignment). The contents of this register are combined with the frame

number counter to enable the host controller to step through the Frame List in

sequence. The two least significant bits are always 00. This requires DWord-alignment

for all list entries. This configuration supports 1024 Frame List entries.

Bit Description

31:12 Base Address — R/W. These bits correspond to memory address signals [31:12],

respectively.

11:0 Reserved

UHCI Controllers Registers

486 Intel ® ICH7 Family Datasheet

11.2.6 SOFMOD—Start of Frame Modify Register

I/O Offset: Base + (0Ch) Attribute: R/W

Default Value: 40h Size: 8 bits

This 1-byte register is used to modify the v alue used in the generation of SOF tim ing on

the USB. Only the 7 least significant bits are used. When a new value is written into

these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be

used to adjust out any offset from the clock source that generates the clock that drives

the SOF counter. This register can also be used to maintain real time synchronization

with the rest of the system so that all devices have the same sense of real time. Using

this register, the frame length can be adjusted across the full range required by the

USB specification. Its initial programmed value is system dependent based on the

accuracy of hardware USB clock and is initialized by system BIOS. It may be

reprogrammed by USB system software at any time. Its value will take effect from the

beginning of the next frame. This register is reset upo n a host controller reset or global

reset. Software must maintain a copy of its value for reprogramming if necessary.

Bit Description

7 Reserved

6:0

SOF Timing Value — R/W. Guidelines for the modification of frame time are contained

in Chapter 7 of the USB Specification. The SOF cycle time (number of SOF counter clock

periods to generate a SOF frame length) is equal to 11936 + value in this field. The

default value is decimal 64 which gives a SOF cycle time of 12000. For a 12 MHz SOF

counter clock input, this produces a 1 ms Frame pe riod. The following table indicate s

what SOF Timing Value to program into this field for a certain frame period.

Frame Lengt

(

# 12 MHz

Clocks) (decimal) SOF T

ng Va

(

s reg

ster

)

(decimal)

11936 0

11937 1

——

11999 63

12000 64

12001 65

——

12062 126

12063 127

Intel ® ICH7 Family Datasheet 487

UHCI Controllers Registers

11.2.7 PORTSC[0,1]—Port Status and Control Register

I/O Offset: Port 0/2/4/6: Base + (10h–11h) Attribute: R/WC, RO,

Port 1/3/5/7: Base + (12h–13h) R/W (Word writes only)

Default Value: 0080h Size: 16 bits

Note: For Function 0, this applies to ICH7 USB ports 0 and 1; for Function 1, this applies to

ICH7 USB ports 2 and 3; for Function 2, this applies to ICH7 USB ports 4 and 5; and for

Function 3, this applies to ICH7 USB ports 6 and 7.

After a power-up reset, global reset, or host controller reset, the initial conditions of a

port are: no device connected, Port disabled, and the bus line status is 00 (single-

ended 0).

Port Reset and Enable Sequence

When software wishes to reset a USB device it will assert the Port Reset bit in the Port

Status and Control register. The minimum reset signaling time is 10 mS and is enforced

by software. To complete the reset sequence, software clears the port reset bit. The

Intel UHCI controller must re-detect the port connect after reset signaling is complete

before the controller will allow the port enable bit to de set by software. This time is

approximately 5.3 uS. Software has several possible options to meet the timing

requirement and a partial list is enumerated below:

• Iterate a short wait, setting the port enable bit and reading it back to see if the

enable bit is set.

• Poll the connect status bit and wait for the hardw are to recogniz e the connect prior

to enabling the port.

• W ait longer than the hardw are detect time after clearing the port reset and prior to

enabling the port.

Bit Description

15:13 Reserved — RO.

Suspend — R/W. This bit should not be written to a 1 if global suspend is active (bit

3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states as

follows:

When in suspend state, downstream propagation of data is blocked on this port, except

for single-ended 0 resets (global reset and port reset). The blocking occurs at the end

of the current transaction, if a transaction was in progress when this bit was written to

1. In the suspend state, the port is sensitive to resume detection. Note that the bit

status does not change until the port is suspended and that there may be a delay in

suspending a port if there is a transaction currently in progress on the USB.

1 = Port in suspend state.

0 = Port not in suspend state .

NOTE: Normally, if a t ransaction is in progress when this bit is set, the port will be

suspended when the c urrent transaction completes. However, in the case of a

specific error condition (out transaction with babble), the Intel® ICH7 may

11 Overcurrent Indica to r — R/WC. Set by hardware.

0 = Software clears this bit by writing a 1 to it.

1 = Overcurrent pin has gone from inactive to active on this port.

Bits [12, 2] Hub State

X,0 Disable

0, 1 Enable

1, 1 Suspend

UHCI Controllers Registers

488 Intel ® ICH7 Family Datasheet

10 Overcurrent Active — RO. This bit is set and cleared by hardware.

0 = Indicates that the overcurrent pin is inactive (high).

1 = Indicates that the overcurrent pin is active (low).

9Port Reset — R/W.

0 = Port is not in Reset.

1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.

8Low Speed Device Attache d (LS) — RO.

0 = Full speed device is attached.

1 = Low speed device is attached to this port.

7 Reserved — RO. Always read as 1.

Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume

signaling. The host controller sets this bit to a 1 if a J-to-K transition is detected for at

least 32 microseconds while the port is in the Suspend state. The ICH7 will then reflect

the K-state back onto the bus as long as the bit remains a 1, and the port is still in the

suspend state (bit 12,2 are ‘11’). Writing a 0 (from 1) causes the port to send a low

speed EOP. This bit will remain a 1 until the EOP has completed.

0 = No resum e (K-state) detected/driven on port.

1 = Resume detected/ driven on port.

5:4 Line Status — RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical

levels. These bits are used for fault detect and recovery as well as for USB diagnostics.

This field is updated at EOF2 time (See Chapter 11 of the USB Specification).

Port Enable/Disable Change — R/WC. Fo r the root hub, this bit ge ts set only when a

port is disabled due to disconnect on that port or due to the appropriate conditions

existing at the EOF2 point (See Chapter 11 of the USB Specification).

0 = No change. Software clears this bit by writing a 1 to the bit location.

1 = Port enabled/disabled status has changed.

Port Enabled/Disabled (PORT_EN) — R/W. Ports can be enabled by host software

only. Ports can be disabled by either a fault condition (disconnect even t or other fault

condition) or by host software. Note that the bit status does not change until the port

state actually changes and that there may be a delay in disabling or enabling a port if

there is a transaction currently in progress on the USB.

0 = Disable

1 = Enable

Connect Status Change — R/WC. This bi t indicates that a change has oc curred in the

port’s Current Connect Status (see bit 0). The hub device sets this bit for any changes

to the port device connect status, even if system software has not cleared a connect

status change. If, for example, the insertion status changes twice before system

software has cleared the changed condition, hub hardware will be setting” an already-

set bit (i.e., the bit will remain set). However, the hub transfers the change bit only

once when the host controller requests a data transfer to the Status Change endpoint.

System software is responsible for determining state change history in such a case.

0 = No change. Software clears this bit by writing a 1 to it.

1 = Change in Current Connect Status.

Current Connect Status — RO. This value reflects the current state of the port, and

may not correspond directly to the event that caused the Connect Status Change bit

(Bit 1) to be set.

0 = No device is present.

1 = Device is present on port.

Bit Description

Intel ® ICH7 Family Datasheet 489

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12 SATA Controller Registers

(D31:F2) (Desktop and Mobile

Only)

Note: SATA is not supported on ICH7-U Ultra Mobile.

12.1 PCI Configuration Registers (SATA–D31:F2)

Note: Address locations that are not shown should be treated as Reserved.

All of the SATA registers are in the core well. None of the registers can be locked.

Table 12-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See registe r

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 02B0h R/WC, RO

08h RID Revision Identification See regis ter

description. RO

09h PI Programming Interface See register

description.

See

description

0Ah SCC Sub Class Code See register

description

See

description

0Bh BCC Base Class Code 01h RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO

14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO

18h–1Bh SCMD_BAR Secondary Command Block Base

Address 00000001h R/W, RO

1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO

20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO

24h–27h ABAR AHCI Base Address 00000000h See

description

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAP Capabilities Pointer 80h RO

3Ch INT_LN Interrupt Line 00h R/W

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

490 Intel ® ICH7 Family Datasheet

NOTE: The ICH7 SATA controller is not arbitrated as a PCI device; therefore, it does no t need a

master latency timer.

3Dh INT_PN Interrupt Pin See register

description. RO

40h–41h IDE_TIMP Primary IDE Timing 0000h R/W

42h–43h IDE_TIMS Secondary IDE Timing 0000h R/W

44h SIDETIM Slave IDE Timing 00h R/W

48h SDMA_CNT Synchronous DMA Control 00h R/W

4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W

54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W

70h–71h PID PCI Power Management Capability ID See register

description RO

72h–73h PC PCI Power Management Capabilities 4002h RO

74h–75h PMCS PCI Power Management Control and

Status 0000h R/W, RO,

R/WC

80h–81h MSICI Message Signaled Interrupt Capability

ID 7005h RO

82h–83h MSIMC Message Signaled Interrupt Message

Control 0000h RO, R/W

84h–87h MSIMA Message Signaled Interrupt Message

Address 00000000h RO, R/W

88h–89h MSIMD Message Signaled Interrupt Message

Data 0000h R/W

90h MAP Address Map 00h R/W

92h–93h PCS Port Control and Status 0000h R/W, RO,

R/WC

94h–97h SIR SATA Initialization Register 00000000h R/W

A0h SIRI SATA Indexed Registers Index 00h R/W

A4h STRD SATA Indexed Register Data XXXXXXXXh R/W

A8h–ABh SCAP0 SATA Capability Register 0 00100012h RO

ACh–AFh SCAP1 SATA Capability Register 1 00000048h RO

C0h ATC APM Trapping Control 00h R/W

C4h ATS ATM Trapping Status 00h R/WC

D0h–D3h SP Scratch Pad 00000000h R/W

E0h–E3h BFCS BIST FIS Control/Status 00000000h R/W, R/WC

E4h–E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W

E8h–EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W

Table 12-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Type

Intel ® ICH7 Family Datasheet 491

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.1 VID—Vendor Identification Register (SATA—D31:F2)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bit

Lockable: No P ower Well: Core

12.1.2 DID—Device Identification Register (SATA—D31:F2)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bit

Lockable: No P ower Well: Core

12.1.3 PCICMD—PCI Command Register (SATA–D31:F2)

Address Offset: 04h–05h Attribute: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to In tel. Intel VID = 80 86 h

Bit Description

15:0

Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 SATA controller.

NOTE: The value of this fiel d will change dependent upon the value of the MAP

Update and Section 12.1.33

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no

effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt and MSI is not

enabled.

1 = Internal INTx# messages will not be generated.

9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.

8 SERR# Enable (SERR_EN) — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Reserved as 0.

Parity Error Response (PER) — R/W.

0 = Disabled. SATA controller will not generate PERR# when a data parity error is

detected.

1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.

5 VGA Palette Snoop (VPS) — RO. Reserved as 0.

4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.

3 Special Cycle Enable (SCE) — RO. Reserved as 0.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

492 Intel ® ICH7 Family Datasheet

12.1.4 PCISTS — PCI Status Register (SATA–D31:F2)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 02B0h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

2Bus Master Enable (BME) — R/W. This bit controls the ICH7’s ability to act as a PCI

master for IDE Bus Maste r transfers. This bit does not impact the generation of

completions for split transaction commands.

Intel® ICH7R/ICH7DH/ICH7-M/ICH7-M DH Only:

Memory Space Enable (MSE) — R/W / RO. This bit controls access to the SATA

controller’s target memory space (for AHCI).

NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO).

Software is responsible for clearing this bit before entering combined mode.

ICH7 Only:

For the 82801GB ICH7, this bit is RO as 0, unless the SCRAE bit (offset 94h:bit 9) is

set.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as

well as the Bus Master I/O registers.

1 = Enable. Note that the Base Address register for the Bus Master registers should be

programmed before this bit is set.

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No parity error detected by SATA controller.

1 = SATA controller detects a parity error on its interface.

14 Signaled System Err or (S SE) — RO. Reserved as 0.

13 Received Master Abort (RMA) — R/WC.

0 = Maste r abort Not generated.

1 = SATA controller, as a master, generated a master abort.

12 Reserved as 0 — RO.

11 Signaled Target Abort (STA) — RO. Reserved as 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Hardwired; Controls the device selec t time for t he S ATA controller’ s PCI interface.

Data Parity Error Detected (DPED) — RO. For Intel® ICH7, this bit can only be set

on read completions received from SiBUS where there is a parity error.

0 = Data parity error Not detected.

1 = SATA controller, as a master, either detects a parity error or sees the parity error

line asserted, and the parity error response bit (bit 6 of the command register) is

set.

7Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.

6User Definable Features (UDF ) — RO. Reserved as 0.

566MHz Capable (66MHZ_CAP) — RO. Reserved as 1.

Intel ® ICH7 Family Datasheet 493

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.5 RID—Revision Identification Register (SATA—D31:F2)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

12.1.6 PI—Programming Interface Register (SATA–D31:F2)

12.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h

Address Offset: 09h Attribute: R/W, RO

Default Value: See bit description Size: 8 bits

4Capabilities List (CAP_LI ST) — RO. This bit indicates the presence of a capabilities

list. The mi nimum requiremen t for the capabili ties list must be PCI power management

for the SATA controller.

Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.

0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the

command register [offset 04h]).

1 = Interrupt is to be asserted

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

Bit Description

7 This read-onl y bit i s a 1 to indicate that the ICH7 supports bus master operation

6:4 Reserved. Will always return 0.

Secondary Mode Native Capable (SNC) — RO.

0 = Secondary controller only supports legacy mode.

1 = Secondary controller supports both legacy and native modes.

When MAP.MV (D31:F2:Offse t 90:bits 1:0) is an y v alue other than 00b, this bit reports

as a 0. When MAP.MV is 00b, this bit reports as a 1.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

494 Intel ® ICH7 Family Datasheet

12.1.6.2 When Sub Class Code Regi ster (D31:F2:Offset 0Ah) = 04h

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

12.1.6.3 When Sub Class Code Regi ster (D31:F2:Offset 0Ah) = 06h

Address Offset: 09h Attribute: RO

Default Value: 01h Size: 8 bits

Secondary Mode Native Enable (SNE) — R/W / RO.

Determines the mode that the secondary channel is operating in.

0 = Secondary controller operating in legacy (compatibility) mode

1 = Secondary controller operating in native PCI mode.

When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-

only (RO). Software is responsible for clearing this bit before entering c ombined mode.

When MAP.MV is 00b, this bit is read/write (R/W).

If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by

software. While in theory these bits can be programmed separately, such a

configuration is not supported by hardware.

Primary Mode Native Capable (PNC) — RO.

0 = Primary controller only supports legacy mode.

1 = Primary controller supports both legacy and native modes.

When MAP.MV (D31:F2:Offset 90:bits 1:0) is any v alue other than 00b, this bit reports

as a 0. When MAP.MV is 00b, this bit reports as a 1

Primary Mode Native Enable (PNE) — R/W / RO.

Determines the mode that the primary channel is operating in.

0 = Primary controller operating in legacy (compatibility) mode.

1 = Primary controller operating in native PCI mode.

When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-

only (RO). Software is responsible for clearing this bit before entering c ombined mode.

When MAP.MV is 00b, this bit is read/write (R/W).

If this bit is set by software, then the SNE bit (bit 2 of this regi ster) must also be set by

software. While in theory these bits can be programmed separately, such a

configuration is not supported by hardware.

Bit Description

7:0 Interface (IF) — RO.

When configured as RAID, this register becomes read only 0.

Bit Description

7:0 Interface (IF) — RO.

Indicates the SATA Controller supports AHCI, rev 1.0.

Intel ® ICH7 Family Datasheet 495

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.7 SCC—Sub Class Code Register (SATA–D31:F2)

Address Offset: 0Ah Attribute: RO

Default Value: See bit description Size: 8 bits

12.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2)

Address Offset: 0Bh Attribute: RO

Default Value: 01h Size: 8 bits

12.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:0

Sub Class Code (SCC)

This field specifies the sub-class code of the controller, per the table below:

Intel® ICH7 Desktop Only:

ICH7-M Only:

Intel® Matrix Storage Technology Enabled ICH7 components Only (ICH7R,

ICH7DH, and ICH7-M DH):

SCC

Reg

ster Attr

ute

cc Reg

ster Va

RO 01h (IDE Controller)

MAP.SMS

(D31:F2:Offset 90h:bit 7:6) SCC Register Value

00b 01h (IDE Controller)

01b 06h (AHCI Controller)

MAP.

(D31:F2:Offset 90h:bit 7:6) SCC Register Value

00b 01h (IDE Controller)

01b 06h (AHCI Controller)

10b 04h (RAID Controller)

Bit Description

7:0 Base Class Code (BCC) — RO.

01h = Mass storage device

Bit Description

7:0 Master Latency Timer Count (MLTC) — RO.

00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated

as a PCI device, so it does not need a Master Latency Timer.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

496 Intel ® ICH7 Family Datasheet

12.1.10 PCMD_BAR—Primary Command Block Base Address

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

12.1.11 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

12.1.12 SCMD_BAR—Secondary Command Block Base Address

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space (8

consecutive I/O locations).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space (4

consecutive I/O locations).

1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. This field provides the base address of the I/O space (8

consecutive I/O locations).

2:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Intel ® ICH7 Family Datasheet 497

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.13 SCNL_BAR—Secondary Control Block Base Address

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O spa ce is used in native mode for the Secondary Controller’s Command

Block.

12.1.14 BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16-

byte IO space to provide a software interface to the Bus Master functions. Only 12

bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]

are used to decode the address.

12.1.15 ABAR — AHCI Base Address Register

(SATA–D31:F2)

12.1.15.1 N on AHCI Capable (Intel® ICH7 Feature Supported Components Only)

Address Offset: 24h–27h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:16 Reserved

15:2 Base Address — R/W. This field provides the base address of the I/O space (4

consecutive I/O locations).

1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:16 Reserved

15:4 Base Address — R/W. This field provides the base address of the I/O space (16

consecutive I/O locations).

3:1 Reserved

0Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O

space.

Bit Description

31:0 Reserved

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

498 Intel ® ICH7 Family Datasheet

12.1.15.2 AHCI Capable (Intel® ICH7R, ICH7DH, and Mobile Only)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This register allocates space for the memory registers defined in Section 12.3. For non-

ACHI capable ICH7 components (ICH7), this register is reserved and read only, unless

the SCRAE bit (offset 94h:bit 9) is set, in which case the register follows the definition

given in Section 12.1.15.2.

NOTES:

1. .When the MAP.MV register is programmed for combined mode (00b), this register is RO.

Software is responsible for clearing this bit before entering combined mode.

2. The ABAR register must be set to a value of 0001_0000h or greater.

12.1.16 SVID—Subsystem Vendor Identification Register

(SATA–D31:F2)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

12.1.17 SID—Subsystem Identification Register (SATA–D31:F2)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Bit Description

31:10 Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)

9:4 Reserved

3 Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable

2:1 Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address

space.

0Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register

memory space.

Bit Description

15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. N o hardware

action taken on this value.

Bit Description

15:0 Subsystem ID (SID) — R/WO . V alue is writte n by BIOS. No hardw are action taken on

this value.

Intel ® ICH7 Family Datasheet 499

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.18 CAP—Capabilities Pointer Register (SATA–D31:F2)

Address Offset: 34h Attribute: RO

Default Value: 80h Size: 8 bits

12.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F2)

Address Offset: 3Dh Attribute: RO

Default Value: See Register Description Size: 8 bits

12.1.21 IDE_TIMP — Primary IDE Timing Register (SATA–D31:F2)

Address Offset: Primary: 40h–41h Attribute: R/W

Secondary: 42h–43h

Default Value: 0000h Size: 16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA

transfers. It also controls operation of the buffer for PIO transfers.

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:0

Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is

80h. This value changes to 70h if the MAP. MV register (Dev 31:F2:90h, bits 1:0) in

configuration space indicates that t he SATA function and PATA functions are combined

(values of 10b or 10b) or Sub Class Code (CC. SCC) (Dev 31:F2:0Ah) i s configure as ID E

mode (value of 01).

Bit Description

7:0 Interrupt Line — R/W. This field is used to communi cate to software the inte rrupt line

that the interrupt pin is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config

Registers:Offset 3100h:

bits 11:8).

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

500 Intel ® ICH7 Family Datasheet

Bit Description

IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or

Secondary decode.

0 = Disable.

1 = Enables the Intel® ICH7 to decode the associated Command Blocks (1F0–1F7h for

primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h

for secondary).

This bit effects the IDE decode ranges for both legacy and native-Mode decoding.

NOTE: This bit affects SA T A oper ation in both combined and non-combin ed A TA modes.

See Section 5.17 for more on ATA modes of operation.

14 Drive 1 Timing Register Enable (SITRE) — R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

13:12

IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number

of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

11:10 Reserved

9:8

Recovery Time (RCT) — R/W. The settin g of these bits determines the minimum

number of PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe

of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

Drive 1 DMA Timing Enable (DTE1) — R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to

the IDE data port will run in compatible timing.

6Drive 1 Prefetch/Posting Enable (PPE1) — R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

5Drive 1 IORDY Sample Point Enable (IE1) — R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

Drive 1 Fast Timing Bank (TIME1) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for

the IORDY sample point, and bits 9:8 for the recov e ry ti me. When thi s bit = 1 and

bit 14 = 1, accesses to the data port will use the IORDY sample point and recover

time specified in the slave IDE timing register.

Drive 0 DMA Timing Enable (DTE0) — R/W.

0 = Disable

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the

IDE data port will run in compatible timing.

2Drive 0 Prefetch/Posting Enable (PPE0) — R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the IDE data port for this drive.

Intel ® ICH7 Family Datasheet 501

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.22 IDE_TIMS — Slave IDE Timing Register (SATA–D31:F2)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

1Drive 0 IORDY Sample Point Enable (IE0) — R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bit s 13:12 for the IORDY sample point, and bits

9:8 for the recovery time

Bit Description

7:6

Secondary Drive 1 I ORDY Sample Point ( SI SP1) — R/W. This field determines the

number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample

point, if the access is to drive 1 data port and bit 14 of the IDE timing register for

secondary is set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

5:4

Secondary Drive 1 Recove ry Time (SRCT1) — R/W. This field determines the

minimum number of PCI cl ocks between the last IORDY sample point and the IOR#/

IOW# strobe o f the next cy cle, if the ac cess is to driv e 1 data port and bit 14 of the IDE

timing register for secondary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

3:2

Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the

number of PCI clocks between IOR#/IOW# assertion and the first IORDY sampl e point,

if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is

set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

1:0

Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the

minimum number of PCI cl ocks between the last IORDY sample point and the IOR#/

IOW# strobe o f the next cy cle, if the ac cess is to driv e 1 data port and bit 14 of the IDE

timing register for primary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

502 Intel ® ICH7 Family Datasheet

12.1.23 SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2)

Address Offset: 48h Attribute: R/W

Default Value: 00h Size: 8 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation unless otherwise noted.

Bit Description

7:4 Reserved

3Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for secondary channel drive 1

2Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for secondary drive 0.

1Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 1

0Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 0

Intel ® ICH7 Family Datasheet 503

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.24 SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2)

Address Offset: 4Ah–4Bh Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

Bit Description

15:14 Reserved

13:12

Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of

these bits determines the minimum write strobe cycle t ime (CT). The DMARDY#-to-

STOP (RP) time is also determined by the setting of these bits.

11:10 Reserved

9:8

Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of

these bits determines the minimum write strobe cycle t ime (CT). The DMARDY#-to-

STOP (RP) time is also determined by the setting of these bits.

7:6 Reserved

SCB1 = 0 (33 MHz cl k) SCB1 = 1 (66 MHz clk) FAST_SCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

SCB1 = 0 (33 MHz cl k) SCB1 = 1 (66 MHz clk) FAST_SCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

504 Intel ® ICH7 Family Datasheet

12.1.25 IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2)

Address Offset: 54h–57h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Note: This register is R/W to maintain software compatibility and enable parallel ATA

functionality when the PCI functions are combined. These bits have no effect on SATA

operation, unless otherwise noted.

5:4

Primary Drive 1 Cycle T ime (PCT1) — R/W. For Ultra A TA mode, the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

3:2 Reserved

1:0

Primary Drive 0 Cycle T ime (PCT0) — R/W. For Ultra A TA mode, the setting of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

Bit Description

PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

Bit Description

31:24 Reserved

23:20 Scratchpad (SP2). Intel® ICH7 does not perform any actions on these bits.

19:18

SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE

signal pins for mobile swap bay support.

If the SRS bit (Chipset Config R egister s:Offset 3414h:bit 1) i s 1, the reset states of bi ts

19:18 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tr i-state (Disabl ed)

10 = Drive low (Disabled)

11 = Reserved

Intel ® ICH7 Family Datasheet 505

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

17:16

PRIM_SIG_MODE — R/W. These bits are used to control mode of the Primary IDE

signal pins for mobile swap bay support.

If the PRS bit (Chipset Config Re gisters:Offset 3414h:bit 1) i s 1, the reset states of bits

17:16 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tri-state (Disabled)

10 = Drive low (Disabled)

11 = Reserved

Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in

conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/

100 timings for the Secondary Slave drive.

0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.

1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this

Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in

conjunction with the SCT0 bits (D31:F2: 4Ah, bits 9:8) to enable/di sabl e Ul tra ATA/100

timings for the Secondary Master drive.

0 = Disable Ultra ATA/100 timing for the Secondary Master drive.

1 = Enable Ultra ATA/100 timing for the Secondary Master drive (ov erri des bi t 2 i n this

Fast Primar y D r iv e 1 Base Clock (FAST_PCB1) — R/W. This bit is used in

conjunction with the PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100

timings for the Primary Slave drive.

0 = Disable Ultra ATA/100 timing for the Primary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this

Fast Primar y D r iv e 0 Base Clock (FAST_PCB0) — R/W. This bit is used in

conjunction with the PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100

timings for the Primary Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this

11:8 Reserved

7:4 Scratchpad (SP1). ICH7 does not perform any action on these bits.

3Secondary Driv e 1 B a se Clock (SCB1) — R/W.

0 = 33 MHz base clock for Ultra ATA timing s.

1 = 66 MHz base clock for Ultra ATA timings

2Secondary Drive 0 Base Clock (SCBO) — R/W.

0 = 33 MHz base clock for Ultra ATA timing s.

1 = 66 MHz base clock for Ultra ATA timings

1Primary Driv e 1 Base Clock (PCB1 ) — R/W.

0 = 33 MHz base clock for Ultra ATA timing s.

1 = 66 MHz base clock for Ultra ATA timings

0Primary Driv e 0 Base Clock (PCB0 ) — R/W.

0 = 33 MHz base clock for Ultra ATA timing s.

1 = 66 MHz base clock for Ultra ATA timings

Bit Description

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

506 Intel ® ICH7 Family Datasheet

12.1.26 PID—PCI Power Management Capability Identification

Address Offset: 70h–71h Attribute: RO

Default Value: XX01h Size: 16 bits

12.1.27 PC—PCI Power Management Capabilities Register

(SATA–D31:F2)

Address Offset: 72h–73h Attribute: RO

Default Value: 4002h Size: 16 bits

Bits Description

15:8

Next Capability (NEXT) — RO.

00h — if SCC = 01h (IDE mode).

A8h — for all other values of SCC to point to the next capability structure.

This field is changed to 00h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.

7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.

Bits Description

15:11 PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3HOT state

in the SATA host controller.

10 D2 Supp ort (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported

9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported

8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,

therefore this field is 00 0b.

5Device Specifi c Initialization (D SI) — RO. Hardwired to 0 to indicate that no device-

specific initialization is required.

4 Reserved

3PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is no t required to

generate PME#.

2:0 Version (VER) — RO. Hardwired to 010 to indicates support for Revision 1.1 of the PCI

Power Management Specification.

Intel ® ICH7 Family Datasheet 507

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.28 PMCS—PCI Power Management Control and Status

Address Offset: 74h–75h Attribute: RO, R/W, R/WC

Default Value: 0000h Size: 16 bits

12.1.29 MSICI—Message Signaled Interrupt Capability

Identification (SATA–D31:F2)

Address Offset: 80h–81h Attribute: RO

Default Value: 7005h Size: 16 bits

12.1.30 MSIMC—Message Signaled Interrupt Message Control

(SATA–D31:F2)

Address Offset: 82h–83h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bits Description

15 PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if

this bit and PMEE is set, a PME# will be generated from the SATA controller.

14:9 Reserved

8PME Enable (PMEE) — R/W.

0 = Disable.

1 = Enable. SATA controller generates PME# form D3HOT on a wake event.

7:2 Reserved

1:0

Power State (PS) — R/W. These bits are used both to determine the current power

state of the SATA controller and to set a new power state.

00 = D0 state

11 = D3HOT state

When in the D3HOT state, the controller’s configuration space is available, but the I/O

and memory spaces are not. Additionally, interrupts are blocked.

Bits Description

15:8 Next Pointer (NEXT): Indicates the next item in the list is the PCI power management

pointer.

7:0 Capability ID (CID): Capabilities ID indicates MSI.

Bits Description

15:8 Reserved

764 Bit Address Capable (C64): Capable of generating a 32-bit message only.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

508 Intel ® ICH7 Family Datasheet

12.1.31 MSIMA— Message Signaled Interrupt Message Address

(SATA–D31:F2)

Address Offset: 84h–87h Attribute: RO, R/W

Default Value: 00000000h Size: 32 bits

6:4

Multiple Message Enable (MME): When this field is cleared to ‘000’ (and MSIE is set),

only a single MSI message will be generated for all SATA ports, and bits [15:0] of the

message vector will be driven from MD[15:0].

When this field is set to ‘001’ (and MSIE is set), two MSI messages will be generated.

Bit [15:1] of the message vectors will be driven from MD[15:1] and bit [0] of the

message vector will be driven dependent on which SATA port is the source of the

interrupt: ‘0’ for port 0, and ‘1’ for ports 1, 2 and 3.

When this field is set to ‘010’ (and MSIE is set), four message will be generated, one for

each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:2], while

bits[1:0] wil l be driven dependent on which SA T A port is the sou rce of the interrupt: ‘00’

for port 0, ‘01’ for port 1, ‘10’ for port 2, and ‘11’ for port 3.

Values ‘011b’ to ‘111b’ are reserved. If this field is set to one of these reserved values,

the results are undefined.

3:1 Multiple Message Capable (MMC): Indicates that the ICH7 SATA controller supports

four interrupt messages.

0MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used

to generate interrupts.

Bits Description

MME Value Driven on MSI Memory Write

Bits[15:2] Bit[1] Bit[0]

000 MD[15:2] MD[1] MD[0]

001 MD[15:2] MD[1] Ports 0: 0

Ports 1,2,3: 1

010 MD[15:2]

Port 0: 0

Port 1: 0

Port 2: 1

Port 3: 1

Port 0: 0

Port 1: 1

Port 2: 0

Port 3: 1

011–111 Reserved

Bits Description

31:2 Address (ADDR): Lower 32 bits of the system specified mess age address, always

DWord aligned.

1:0 Reserved

Intel ® ICH7 Family Datasheet 509

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.32 MSIMD—Message Signaled Interrupt Message Data

(SATA–D31:F2)

Address Offset: 88h-89h Attribute: R/W

Default Value: 0000h Size: 16 bits

12.1.33 MAP—Address Map Register (SATA–D31:F2)

Address Offset: 90h Attribute: R/W

Default Value: 00h Size: 8 bits

Bits Description

15:0

Data (DATA) — R/W: This 16-bit field is programmed by system software if MSI is

enabled. Its content is driven onto the lower word of the data bus of the MSI memory

write transaction. Note that when the MME field is set to ‘001’ or ‘010’, bit [0] and bits

[1:0] respectively of the MSI memory write transaction will be driven based on the

source of the interrupt rather than from MD[1:0]. See the description of the MME field.

Bits Description

7:6

SATA Mode Select (SMS) — R/W: Software programs these bits to control the mode

in which the SATA HBA should operate:

00b = IDE mode

01b = AHCI mode

10b = RAID mode

11b = Reserved

NOTES:

1. The SATA Function Device ID will change based on the value of this register.

2. When combined m o de is used (MV Not equal to ‘0’), only IDE mode is allowed.

IDE mode can be selected when AHCI and/or RAID are enabled

3. AHCI mode may only be selected when MV = 0

4. RAID mode may only be selected when MV = 0

5. Program ming these bits with v alues that are in valid (e .g, selecting RAID when in

combined mode) will result in indeterministic behavior by the hardware.

5:2 Reserved.

1:0

Map Value — R/W. Map Value (MV): The value in the bits below indicate the address

range the SATA ports responds to, and whether or not the PAT A and S ATA functions are

combined. When in combined mode, the AHCI memory space is not available and AHCI

may not be used.

00 = Non-combined. P0 is primary master, P2 is the primary slave. P1 is secondary

master, P3 is the secondary slave (des ktop only). P0 is primary master, P2 is the

primary slave (m obile only).

01 = Combined. IDE is primary. P1 is secondary master, P3 is the secondary slave.

(desktop only)

10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary

11 = Reserved

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

510 Intel ® ICH7 Family Datasheet

12.1.34 PCS—Port Control and Status Register (SATA–D31:F2)

Address Offset: 92h–93h Attribute: R/W, R/WC, RO

Default Value: 0000h Size: 16 bits

This register is only used in systems that do not support AHCI. In AHCI enabled

systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set

(Mobile only), and the status of the port is controlled through AHCI memory space.

Bits Description

15:8 Reserved.

(Desktop

Only)

Port 3 Present (P3P) — RO. The status of this bit may change at any time. This bit

is cleared when the port is disabled via P3E. This bit is not cleared upon surprise

removal of a device.

0 = No device detected.

1 = The presence of a device on Port 3 has been detected.

7 (Mobile

Only) Reserved

Port 2 Present (P2P) — RO. The status of this bit may change at any time. This bit

is cleared when the port is disabled via P2E. This bit is not cleared upon surprise

removal of a device.

0 = No device detected.

1 = The presence of a device on Port 2 has been detected.

(Desktop

Only)

Port 1 Present (P1P) — RO. The status of this bit may change at any time. This bit

is cleared when the port is disabled via P1E. This bit is not cleared upon surprise

removal of a device.

0 = No device detected.

1 = The presence of a device on Port 1 has been detected.

5 (Mobile

Only) Reserved

Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bit

is cleared when the port is disabled via P0E. This bit is not cleared upon surprise

removal of a device.

0 = No device detected.

1 = The presence of a device on Port 0 has been detected.

(Desktop

Only)

Port 3 Enabled (P3E) — R/W.

0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes preceden ce over P3CMD.SUD (offset ABAR+298h:bit 1)

3 (Mobile

Only) Reserved

Port 2 Enabled (P2E) — R/W.

0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes preceden ce over P2CMD.SUD (offset ABAR+218h:bit 1)

(Desktop

Only)

Port 1 Enabled (P1E) — R/W.

0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes preceden ce over P1CMD.SUD (offset ABAR+198h:bit 1)

1 (Mobile

Only) Reserved

Intel ® ICH7 Family Datasheet 511

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.35 SIR—SATA Initialization Register

Address Offset: 94h–97h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Port 0 Enabled (P0E) — R/W.

0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.

1 = Enabled. The port can transition between the on, partial, and slumber states and

can detect devices.

NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)

Bits Description

Bit Description

31:29 Reserved

SATA Capability Registers Disable (SCRD).

When this bit is set, the SATA Capability Registers are disabled. That is, SATA

Capability Registers 0 and 1 are both changed to Read Only with the value of

00000000h. Also, the Next Capability bits in the PCI Power Management Capability

Information Register (D31:F2;Offset 70h bits 1 5:8) are changed to 0 0h, to indica te

that the PCI Power Management Capability structure is the last PCI capability

structure in the SATA controller. When this bit is cleared, the SATA Capability

Registers are enabled.

29 Reserved

SATA Clock Request Enabled (SCRE) — R/W.

0 = SATA Clock Request protocol is disabled. SATACLKREQ# pin when in native

function will alwa ys out put '0' to keep the SATA clock running.

1 = SATA Clock Request protocol is enabled. SATACLKREQ# pin when in native

function will behave as the Serial ATA clock request to the system clock chip.

27:24

(Desktop

Only) Reserved

27:24

(Mobile

Only)

SATA Initialization Field 3 (SIF3) — R/W. BIOS shall always program this

23 SATA Initialization Field 2 (SIF2) — R/W. BIOS shall always program this

22:10 Reserved

SCR Access Enable (SCRAE) — R/W. In non-AHCI mode, this bit allows access to

the SATA SCR registers (SStatus, SControl, and SError registers).

0 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset

04h:bit 1) remain as defined.

1 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset

04h:bit 1) are forced to be read/write.

NOTES:

1. Using this mode only allows access to AHCI registers PxSSTS, PxSCTL,

PxSERR. All other AHCI space is reserved when this bit is set.

2. Proper use of this bit requires:

• ABAR must be programmed to a valid BAR; MSE must be set before software can access

AHCI space.

• The Port Imple mented bit (D31:F2, Offset ABAR+0Ch) for the co rrespond ing port has to be

set to allow access to the AHCI port specific PxSSTS, PxSCTL, and PxSERR registers.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

512 Intel ® ICH7 Family Datasheet

12.1.36 SIRI—SATA Indexed Registers Index

Address Offset: A0h Attribute: R/W

Default Value: 00h Size: 8 bits

SATA Indexed R egisters

12.1.37 STRD—SATA Indexed Register Data

Address Offset: A4h Attribute: R/W

Default Value: XXXXXXXXh Siz e: 32 bits

8:0 SATA Initialization Fi eld 1 (SIF1) — R/W. BIOS shall always program this

Bit Description

7:2 Index (IDX) — R/W. This field contains a 6-bit index pointer into the SATA Indexed

1:0 Reserved

Index Name

00h–03h SATA TX Termination Test Register 1 (STTT1)

04h–1Bh Reserved

1Ch–1Fh SATA Test Mode Enable Register (STME)

20h–73h Reserved

74h–77h SATA TX Termination Test Register 2 (STTT2)

78h–FFh Reserved

Bit Description

31:0 Data (DTA) — R/W. This field contains a 32-bit data value that is written to the

Intel ® ICH7 Family Datasheet 513

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.37.1 STTT1— SATA Indexed Registers Index 00h

(SATA TX Termination Test Register 1)

Address Offset: Index 00h–03h Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.1.37.2 STME— SATA Indexed Registers Index C1h

(SATA Test Mode Enable Register)

Address Offset: Index 1Ch–1Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:2 Reserved.

Port 1 TX Termination Test Enable — R/W:

0 = Port 1 TX termination port testing is disabled.

1 = Enables testing of Port 1 TX termination.

NOTE: This bit only to be used for system board testing.

Port 0 TX Termination Test Enable — R/W:

0 = Port 0 TX termination port testing is disabled.

1 = Enables testing of Port 0 TX termination.

NOTE: This bit only to be used for system board testing.

Bit Description

31:19 Reserved.

SATA Test Mode Enable Bit — R/W:

0 = Entrance to Intel® ICH7 SATA test modes are disabled.

1 = This bit allows entrance to ICH7 SATA test modes when set.

NOTE: This bit only to be used for system board testing.

17:0 Reserved.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

514 Intel ® ICH7 Family Datasheet

12.1.37.3 STTT2 — SATA Indexed Registers Index 74h

(SATA TX Termination Test Register 2)

Address Offset: Index 74h – 77h Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.1.38 SCAP0—SATA Capability Register 0 (SATA–D31:F2)

Address Offset: A8h–ABh Attribute: RO

Default Value: 00100012h Size: 32 bits

This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.

Bit Description

31:18 Reserved.

Port 3 TX Termination Test Enable — R/W:

0 = Port 3 TX termination port testing is disabled.

1 = Enables testing of Port 3 TX termination.

NOTE: This bit only to be used for system board testing.

Port 2 TX Termination Test Enable — R/W:

0 = Port 2 TX termination port testing is disabled.

1 = Enables testing of Port 2 TX termination.

NOTE: This bit only to be used for system board testing.

15:0 Reserved.

Bit Description

31:24 Reserved

23:20 Major Revision (MAJREV) — RO: Major revision number of the SATA Capability Pointer

implemented.

19:16 Minor Revision (MINREV) — RO: Minor revision number of the SATA Capability Pointer

implemented.

15:8 Next Capability Pointer (NEXT) — RO: Points to the next capability structure. 00h

indicates this is the last capability pointer.

7:0 Capability ID (CAP)— RO: This value of 12h has been assigned by the PCI SIG to

designate the SATA Capability Structure.

Intel ® ICH7 Family Datasheet 515

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.39 SCAP1—SATA Capability Register 1 (SATA–D31:F2)

Address Offset: ACh–AFh Attribute: RO

Default Value: 00000048h Size: 32 bits

This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.

Bit Description

31:16 Reserved

15:4

BAR Offset (BAROFST) — RO: Indicates the offset into the BAR where the Index/Data

pair are located (in DW ord granularity). The Index and Data I/O regist ers are located at

offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h.

000h = 0h offset

001h = 4h offset

002h = 8h offset

003h = Bh offset

004h = 10h offset

...

FFFh = 3FFFh offset (max 16KB)

3:0

BAR Location (BARLOC) — RO: Indicates the absolute PCI Configuration Register

address of the BAR containing the Index/Data pair (in DWord granularity). The Index

and Data I/O registers reside within the space defined by LBAR in the SATA controller. A

value of 8h indicates offset 20h, which is LBAR.

0000 – 0011b = reserved

0100b = 10h => BAR0

0101b = 14h => BAR1

0110b = 18h => BAR2

0111b = 1Ch => BAR3

1000b = 20h => LBAR

1001b = 24h => BAR5

1010 – 1110b = reserved

1111b = Index/Data pair in PCI Configuration space. This is not supported in Intel®

ICH7.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

516 Intel ® ICH7 Family Datasheet

12.1.40 ATC—APM Trapping Control Register (SATA–D31:F2)

Address Offset: C0h Attribute: R/W

Default Value: 00h Size: 8 bits

12.1.41 ATS—APM Trapping Status Register (SATA–D31:F2)

Address Offset: C4h Attribute: R/WC

Default Value: 00h Size: 8 bits

12.1.42 SP — Scratch Pad Register (SATA–D31:F2)

Address Offset: D0h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:4 Reserved

3Secondary Slave Trap (SST) — R/W. Enables trapping and SMI# assertion on legacy

I/O accesses to 170h–177h and 376h. The active device on the secondary interface

must be device 1 for the trap and/or SMI# to occur.

2Secondary Master Trap (SMT) — R/W. Enables trapping and SMI# assertion on

legacy I/O accesses to 170h–177h and 376h. The active device on the secondary

interface must be device 0 for the trap and/or SMI# to occur.

1Primary Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/

O accesses to 1F0h–1F 7h and 3F6h. The active device on the primary inte rface must be

device 1 for the trap and/or SMI# to occur.

0Primary Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy

I/O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must

be device 0 for the trap and/or SMI# to occur.

Bit Description

7:4 Reserved

3Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the

secondary slave device.

2Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the

secondary master device.

1Primary Slave Trap (PST) — R/WC. Indicates that a trap occurred to the primary

slave device.

0Primary Master Trap (PMT) — R/WC. Indicates that a trap occurred to the primary

master device.

Bit Description

31:0 Data (DT) — R/W. This is a read/write register that is avai lable for software to use. No

hardware action is taken on this register.

Intel ® ICH7 Family Datasheet 517

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.43 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)

Address Offset: E0h–E3h Attribute: R/W, R/WC

Default Value: 00000000h Size: 32 bits

Bits Description

31:14 Reserved

(Desktop

Only)

Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit

field, the Intel® ICH7 initiates a BIST FIS to the device on Port 3, using the

parameters specified in this register and the data specified in BFTD1 and BFTD2. The

BIST FIS will only be initiated if a device on Port 3 is present and ready (not partial/

slumber state). After a BIST FIS is successfully completed, software must disable and

re-enable the port using the PxE bits at offset 92h prior to attempting additional BIST

FISes or to return the ICH7 to a normal operational mode. If the BIST FIS fails to

complete, as indicated by the BFF bit in the register, then software can clear then set

the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS

eventually completes successfully.

(Mobile

Only) Reserved.

Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit

field, the ICH7 initiates a BIST FIS to the device on Port 2, using the parameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will

only be initiated if a device on Port 2 is present and ready (not partial/slumber state).

After a BIST FIS is successfully completed, software must disable and re-enable the

port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to

return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as

indicated by the BFF bit in the register, then software can clear then set the P2BFI bit

to initiate an other BIST FIS. This can be retried until the BIST FIS eventually

completes successfully

BIST FIS Succ essful (BFS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = BIST FIS transmitted by ICH7 received an R_OK completion status from the

device.

NOTE: This bit must be cleared by software prior to initiating a BIST FIS.

BIST FIS Failed (BFF) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = BIST FIS transmitted by ICH7 received an R_ERR completion status from the

device.

NOTE: This bit must be cleared by software prior to initiating a BIST FIS.

(Desktop

Only)

Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit

field, the ICH7 initiates a BIST FIS to the device on Port 1, using the parameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will

only be initiated if a device on Port 1 is present and ready (not partial/slumber state).

After a BIST FIS is successfully completed, software must disable and re-enable the

port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to

return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as

indicated by the BFF bit in the register, then software can clear then set the P1BFI bit

to initiate an other BIST FIS. This can be retried until the BIST FIS eventually

completes successfully

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

518 Intel ® ICH7 Family Datasheet

12.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)

Address Offset: E4h–E7h Attribute: R/W

Default Value: 00000000h Size: 32 bits

(Mobile

Only) Reserved.

Port 0 BIST FIS Initi ate (P0B FI) — R/W . When a rising edge is detect ed on this bit

field, the ICH7 initiates a BIST FIS to the device on Port 0, using the parameters

specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will

only be initiated if a device on Port 0 is present and ready (not partial/slumber state).

After a BIST FIS is successfully completed, software must disable and re-enable the

port using the PxE bits at offset 92h prior to attempting additional BIST FISes or to

return the ICH7 to a normal operational mode. If the BIST FIS fails to complete, as

indicated by the BFF bit in the register, then software can clear then set the P0B FI bit

to initiate another BIST FIS. This can be retried until the BIST FIS eventually

completes successfully

7:2

BIST FIS Parameters. These 6 bits form the contents of the uppe r 6 bits of the BIST

FIS Pattern Definition in any BIST FIS transmitted by the ICH7. This field is not port

specific; its contents will be used for any BIST FIS initiated on port 0, port 1, port 2 or

port 3. The specific bit definitions are:

Bit 7: T – Far End Transmit mode

Bit 6: A – Align Bypass mode

Bit 5: S – Bypass Scrambling

Bit 4: L – Far End Retimed Loopback

Bit 3: F – Far End Analog Loopback

Bit 2: P – Primitive bit for use with Transmit mode

1:0 Reserved

Bits Description

31:0

BIST FIS Transmit Dat a 1 — R/W. The data programmed into this register will form

the contents of the second DWord of any BIST FIS initiated by the Intel® ICH7. This

Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of

the BIST FIS is s et to indicate “Far-End Transmit mode”, this register’s contents will be

transmitted as the BIST FIS 2nd DW regardl ess of whether or not the “T” bit is indicated

in the BFCS register (D31:F2:E0h).

Intel ® ICH7 Family Datasheet 519

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.1.45 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)

Address Offset: E8h–EBh Attribute: R/W

Default Value: 00000000h Size: 32 bits

12.2 Bus Master IDE I/O Registers (D31:F2)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register,

located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O

space registers can be accessed as byte, word, or DWord quantities. Reading reserved

bits returns an indeterminate, inconsistent value, and writes to reserved bits have no

effect (but should not be attempted). These registers are only used for legacy

operation. Software must not use these registers when running AHCI. The description

of the I/O registers is shown in Table 12-2.

Bits Description

31:0

BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form

the contents of the third DWord of any BIST FIS initiated by the Intel® ICH7. This

Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of

the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be

transmitted as the BIST FIS 3rd DW regardl ess of whether or not the “T” bit is indicated

in the BFCS register (D31:F2:E0h).

Table 12-2. Bus Master IDE I/O Register Address Map

BAR+

Offset Mnemonic Register Default Type

00 BMICP Command Register Primary 00h R/W

01 — Reserved — RO

02 BMISP Bus Master IDE Status Register Primary 00h R/W, R/

WC, RO

03 — Reserved — RO

04–07 BMIDP Bus Master IDE Descriptor Table Pointer

Primary xxxxxxxxh R/W

08 BMICS Command Register Secondary 00h R/W

09 — Reserved — RO

0Ah BMISS Bus Master IDE Status Register Secondary 00h R/W, R/

WC, RO

0Bh — Reserved — RO

0Ch–

0Fh BMIDS Bus Master IDE Descriptor Table Pointer

Secondary xxxxxxxxh R/W

10h AIR AHCI Index Register 00000000

hR/W, RO

14h AIDR AHCI Index Data Register xxxxxxxxh R/W

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

520 Intel ® ICH7 Family Datasheet

12.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)

Address Offset: Primary: BAR + 00h Attribute: R/W

Secondary: BAR + 08h

Default Value: 00h Size: 8 bits

Bit Description

7:4 Reserved. Returns 0.

Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master

transfer: This bit must NOT be changed when the bus master funct ion i s ac tive.

0 = Memory reads

1 = Memory writ es

2:1 Reserved. Returns 0.

Start/Stop Bus Master (START) — R/W.

0 = All state information is lost when this bit is cleared. Master mode operation cannot

be stopped and then resumed. If this bit is reset while bus master operation is still

active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus

Master IDE Status register for that IDE channel is set) and the drive has not yet

finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for

that IDE channel is n ot set), the bus master command is said to be aborted and

data transferred from the drive may be discarded instead of being written to

system memory.

1 = Enables bus ma ster operation of the controller. Bus m aster operation does not

actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI

configuration space is also set. Bus master operation begins when this bit is

detected changing from 0 to 1. The controller will transfer data between the IDE

device and memory only when this bit is set. Master operation can be halted by

writing a 0 to this bit.

NOTE: This bit is intended to be cleared by software after the data transfer is

completed, as indicated by either the Bus Master IDE Active bit being cleared or

the Interrupt bit of the Bus Master IDE Status register for that IDE channel

being set, or both. Hardware does not clear this bit automatically. If this bit is

cleared to 0 prior to the DMA data transfer being initiated by the drive in a

Intel ® ICH7 Family Datasheet 521

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)

Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO

Secondary: BAR + 0Ah

Default Value: 00h Size: 8 bits

Bit Description

PRD Interrupt Status (PRDIS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set wh en t h e h os t con troller ex ecution of a PRD that has its P RD_ INT bit

set.

Drive 1 DMA Capable — R/W.

0 = Not Capable.

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 1 for this channel is capable of DMA transfers, and that the controller has

been initialized for opt imum perf ormance. The Intel ® ICH7 does no t us e th is bit . I t

is intended for systems that do not attach BMIDE to the PCI bus.

Drive 0 DMA Capable — R/W.

0 = Not Capable

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 0 for this channel is capable of DMA transfers, and that the controller has

been initialized for optimum performance. The ICH7 does not use this bit. It is

intended for sy stems that do not attach BMIDE to the PCI bus.

4:3 Reserved. Re tur ns 0.

Interrupt — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not

disabled interrupts via the IEN bit of the Device Control Re gister (see chapter 5 of

the Serial ATA Specification, Revision 1.0a).

Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when the controller encounters a target abort or master abort when

transferring data on PCI.

Bus Master IDE Active (ACT) — RO.

0 = This bit is cleared by the ICH7 when the la st transfer for a region is performed,

where EOT for that region is set in the region descriptor. It is also cleared by the

ICH7 when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the

Command register. When this bit is read as a 0, all data transferred from the drive

during the previous bus master command is visible in system memory, unless the

bus master command was aborted.

1 = Set by the ICH7 when the Start bit is written to the Command register.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

522 Intel ® ICH7 Family Datasheet

12.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Address Offset: Primary: BAR + 04h–07h Attribute: R/W

Secondary: BAR + 0Ch–0Fh

Default Value: All bits undefined Size: 32 bits

12.2.4 AIR—AHCI Index Register (D31:F2)

Address Offset: Primary: BAR + 10h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

12.2.5 AIDR—AHCI Index Data Register (D31:F2)

Address Offset: Primary: BAR + 14h Attribute: R/W

Default Value: All bits undefine d Size: 32 bits

Bit Description

31:2 Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to

A[31:2]. The Descri ptor Table must be DWord-aligned. The Descriptor Table must not

cross a 64-K boundary in memory.

1:0 Reserved

Bit Description

31:10 Reserved

9:2 Index (INDEX)— R/W: This Index register is used to select the DWord offset of the

Memory Mapped AHCI register to be accessed. A DWord, Word or Byte access is

specified by the active byte enables of the I/O access to the Data register.

1:0 Reserved

Bit Description

31:0

Data (DATA)— R/W: This Data register is a “window” through which data is read or

written to the AHCI memory mapped registers. A read or write to this Data register

triggers a corresponding read or write to the memory mapped register pointed to by

the Index register. The Index register must be setup prior to the read or write to this

Data register.

Note that a physical regist er is not actually implemented as the data is ac tually stored

in the memory mapped registers.

Since this is not a ph ysical regi ster, the “default” v alu e is the same as the default value

of the register pointed to by Index.

Intel ® ICH7 Family Datasheet 523

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3 AHCI Registers (D31:F2) (Intel® ICH7R, ICH7DH,

ICH7-M, and ICH7-M DH Only)

Note: These registers are AHCI-specific and available only on ICH7 components that support

AHCI (not on the 82801GB ICH7) and when the ICH7 is properly configured. The Serial

A TA Status, Control, and Error registers are special exceptions and may be accessed on

all ICH7 components if properly configured (see section Section 12.1.35 for details).

The memory mapped registers within the SATA controller exist in non-cacheable

memory space. Additionally, locked accesses are not supported. If software attempts to

perform locked transactions to the registers, indeterminate results may occur. Register

accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte

alignment boundary.

The registers are divided into two sections – generic host control and port control. The

port control registers are the same for all ports, and there are as many registers banks

as there are ports.

Table 12-3. AHCI Register Address Map

ABAR +

Offset Mnemon

ic Register

00–1Fh GHC Generic Host Control

20h–FFh — Reserved

100h–17Fh P0PCR Port 0 port control registers

180h–1FFh P1PCR Port 1 port control registers (Intel® ICH7R and ICH7DH Only)

Registers are not available and software must not read or write

registers. (Mobile Only)

200h–27Fh P2PCR Port 2 port control registers

280h–2FFh P3PCR Port 3 port control registers (ICH7R and ICH7DH Only)

Registers are not available and software must not read or write

registers. (Mobile Only)

300h–3FFh — Reserved

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

524 Intel ® ICH7 Family Datasheet

12.3.1 AHCI Generic Host Control Registers (D31:F2)

12.3.1.1 CAP—Host Capabilities Register (D31:F2)

Address Offset: ABAR + 00h–03h Attribute: R/WO, RO

Default Value: DE22FF03h (Desktop Only) Size: 32 bits

DE12FF03h (Mobile Only)

All bits in this register that are R/WO are reset only by PLTRST#.

Table 12-4. Generic Host Controller Register Address Map

ABAR +

Offset Mnemonic Register Default Type

00–03 CAP Host Capabilities

DE22FF03h

(Intel® ICH7R

and ICH7DH

Only)

DE12FF03h

(Mobile Only)

R/WO, RO

04–07 GHC Global ICH7 Control 00000000h R/W

08–0Bh IS Interrupt Status 00000000h R/WC, RO

0Ch–0Fh PI Ports Implemented 00000000h R/WO, RO

10h–13h VS AHCI Version 00010100h RO

Bit Description

Supports 64-bit Addressing (S64A) — RO. Indicates that the SATA controller

can access

64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD

Base, and each PRD en try are read/write.

Supports Command Queue Acceleration (SCQA) — RO. Hardwired to 1 to

indicate that the SATA controller supports SATA command queuing via the DMA

Setup FIS. The Intel® ICH7 handles DMA Setup FISes natively, and can handle

auto-activate optimization through that FIS.

29 Supports SNotification Register (SSNTF): — RO. The ICH7 SATA Controller does

not support the SNotification register.

Supports Interlock Switch (SIS) — R/WO. Indicates whether t he SATA

controller supports interlock switches on its ports for use in Hot-Plug operations.

This value is loaded by platform BIOS prior to OS initialization.

If this bit is set, BIOS must also map the SATAGP pins to the SATA controller

through GPIO space.

Supports Staggered Spin-up (SSS) — R/WO. Indicates whether the SATA

controller supports staggered spin-up on its ports, for use in balancing power

spikes. This value is loaded by platform BIOS prior to OS initialization.

0 = Staggered spin-up not supported.

1 = Staggered spin-up supported.

Supports Aggressive Link Power Management (SALP) — R /WO. Indic a te s

the SATA controller supports auto-generating link requests to the partial or

slumber states when the re are no commands to process.

0 = Aggressive link power management not supported.

1 = Aggressive link power management supported.

Intel ® ICH7 Family Datasheet 525

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

25 Supports Activity LED (SAL) — RO. Indicates that the SATA controller supports

a single output pin (SATALED#) which indicates activity.

Supports Command List Override (SCLO) — R/WO. When set to 1, indicates that

the HBA supports the PxCMD.CL O bit and it's asso ciated fu nction. Whe n cleared to

'0', The HBA is not capable of cl earing th e BSY and DRQ bits in the Status register

in order to issue a software reset if these bits are still set from a previous

operation.

23:20

(Desktop

Only)

Interface Speed Support (ISS) — R/WO. Indicates the maximum speed the

SATA controller can support on its ports.

2h =3.0 Gb/s.

23:20

(Mobile)

Only

Interface Speed Support (ISS) — RO. Indicates the maximum speed the SATA

controller can support on its ports.

1h =1.5 Gb/s.

19 Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI

Revision 1.0 specification

18 Supports Port Selector Acceleration — RO. Port Selectors not supported.

17 Supports Port Multiplier (PMS) — R/WO. ICH7 does not support port multiplier.

BIOS/SW shall write this bit to ‘ 0’ during AHCI initialization.

Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the

AHCI Revision 1.0 specification.

NOTE: Port Multiplier not supported by ICH7.

15 PIO Multipl e DR Q Block (PMD) — R/WO. The SATA controller supports PIO

Multiple DRQ Command Blo ck

14 Slumber State Capable (SSC) — RO. The SATA controller supports the slumber

state.

13 Partial State Capable (PSC) — RO. The SATA controller supports the partial state.

12:8 Number of Command Slots (NCS) — RO. Hardwired to 1Fh to indicate support for

32 slots.

7:5 Reserved. Returns 0.

4:0 Number of Ports (NPS) — RO . Hardwired to 3h to indicate support for 4 ports. Note

that the number of ports indicated in this field may be more than the number of

ports indicated in the PI (ABAR + 0Ch) register.

Bit Description

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

526 Intel ® ICH7 Family Datasheet

12.3.1.2 GHC—Global ICH7 Control Register (D31:F2)

Address Offset: ABAR + 04h–07h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

AHCI Enable (AE) — R/W. When set, indicates that an AHCI driver is loaded and the

controller will be talked to via AHCI mechanisms. This can be used by an Intel® ICH7

that supports both legacy me chanisms (such as SFF-8038i) and AHCI to know when the

controller will not be talked to as legacy.

When set, software will only talk to the ICH7 using AHCI. The ICH7 will not have to

allow command processing via both AHCI and legacy mechanisms. When cleared,

software will only talk to the ICH7 using legacy mechanisms.

Software shall set this bit to 1 before accessing other AHCI registers.

30:2 Reserved. Returns 0.

1Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH7.

0 = All interrupt sources from all ports are disabled.

1 = Interrupts are allowed from the AHCI controller.

HBA Reset (HR) — R/W. Resets ICH7 AHCI controller.

0 = No effect

1 = Causes an internal reset o f th e ICH7 AHCI cont roll er. All state machin es th at re late

to data transfers and queuing return to an idle conditio n, and all ports are re-

initialized via COMRES ET.

NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host

Controller Interface specification.

Intel ® ICH7 Family Datasheet 527

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.1.3 IS—Interrupt Status Register (D31:F2 )

Address Offset: ABAR + 08h–0Bh Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

This register indicates which of the ports within the controller have an interrupt pending

and require service.

Bit Description

31:4 Reserved. Returns 0.

(Mobile

Only) Reserved. Returns 0.

(Intel®

ICH7R and

ICH7DH

Only)

Interrupt Pending Status Port[3] (IPS[3]) — R/WC.

0 = No interrupt pending.

1 = Port 3 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

Interrupt Pending Status Port[2] (IPS[2]) — R/WC

0 = No interrupt pending.

1 = Port 2 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

(Mobile

Only) Reserved. Returns 0.

(ICH7R

and

ICH7DH

Only)

Interrupt Pending Status Port[1] (IPS[1]) — R/WC.

0 = No interrupt pending.

1 = Port 1has an interrupt pending. Software can use this information t o determ ine

which ports require service after an interrupt.

Interrupt Pending Status Port[0] (IPS[0]) — R/WC.

0 = No interrupt pending.

1 = Port 0 has an interrupt pending. Software can use this information to determine

which ports require service after an interrupt.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

528 Intel ® ICH7 Family Datasheet

12.3.1.4 PI—Ports Implemented Register (D31:F2)

Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

This register indicates which ports are exposed to the ICH7. It is loaded by platform

BIOS. It indicates which ports that the device supports are available for software to

use. For ports that are not available, software must not read or write to registers within

that port.

12.3.1.5 VS—AHCI Version (D31:F2)

Address Offset: ABAR + 10h–13h Attribute: RO

Default Value: 00010100h Size: 32 bits

This register indicates the major and minor version of the AHCI specification. It is BCD

encoded. The upper two bytes represent the major version number, and the lower two

bytes represent the minor version number. Example: Version 3.12 would be

represented as 00030102h. The current version of the specification is 1.10

(00010100h).

Bit Description

31:4 Reserved. Return s 0.

(Intel®

ICH7R and

ICH7DH

Only)

Ports Implemented Port 3 (PI3) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

3 (Mobile

Only) Ports Implemented Port 3 (PI3) — RO.

0 = The port is not implemented.

2Ports Implemented Port 2 (PI2)— R/WO.

0 = The port is not implemented.

1 = The port is implemented.

(ICH7R

and

ICH7DH

Only)

Ports Implemented Port 1 (PI1) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

1 (Mobile

Only) Ports Implemented Port 1 (PI1) — RO.

0 = The port is not implemented.

0Ports Implemented Port 0 (PI0) — R/WO.

0 = The port is not implemented.

1 = The port is implemented.

Bit Description

31:16 Major Version Number (MJR) — RO. Indicates the major version is 1

15:0 Minor Version Number (MNR) — RO. Indicates the minor version is 10.

Intel ® ICH7 Family Datasheet 529

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2 Port Registers (D31:F2)

Table 12-5. Port [3:0] DMA Register Address Map (Sheet 1 of 2)

ABAR +

Offset Mnemonic Register

100h–103h P0CLB Port 0 Command List Base Address

104h–107h P0CLBU Port 0 Command Li st Base Address Upper 32-Bits

108h–10Bh P0FB Port 0 FIS Base Address

10Ch–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits

110h–113h P0IS Port 0 Interrupt Status

114h–117h P0IE Port 0 Interrupt Enable

118h–11Ch P0CMD Port 0 Command

11Ch–11Fh — Reserved

120h–123h P0TFD Port 0 Task File Data

124h–127h P0SIG Port 0 Signature

128h–12Bh P0SSTS Port 0 Serial ATA Status

12Ch–12Fh P0SCTL Port 0 Serial ATA Control

130h–133h P0SERR Port 0 Serial ATA Error

134h–137h P0SACT Port 0 Serial ATA Active

138h–13Bh P0CI Port 0 Command Issue

13Ch–17Fh — Reserved

180h–1FFh

(Mobile On ly) —Reserved

Registers are not available and software must

not read from or write to registers.

180h–183h P1CLB Port 1 Command List Base Address

184h–187h P1CLBU Port 1 Command Li st Base Address Upper 32-Bits

188h–18Bh P1FB Port 1 FIS Base Address

18Ch–18Fh P1FBU Port 1 FIS Base Address Upper 32-Bits

190h–193h P1IS Port 1 Interrupt Status

194h–197h P1IE Port 1 Interrupt Enable

198h–19Ch P1CMD Port 1 Command

19Ch–19Fh — Reserved

1A0h–1A3h P1TFD Port 1 Task File Data

1A4h–1A7h P1SIG Port 1 Signature

1A8h–1ABh P1SSTS Port 1 Serial ATA Status

1ACh–1AFh P1SCTL Port 1 Serial ATA Control

1B0h–1B3h P1SERR Port 1 Serial ATA Error

1B4h–1B7h P1SACT Port 1 Serial ATA Active

1B8h–1BB h P1CI Port 1 Command Issue

1BCh–1FFh — Reserved

200h–203h P2CLB Port 2 Command List Base Address

204h–207h P2CLBU Port 2 Command Li st Base Address Upper 32-Bits

208h–20Bh P2FB Port 2 FIS Base Address

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

530 Intel ® ICH7 Family Datasheet

20Ch–20Fh P2FBU Port 2 FIS Base Address Upper 32-Bits

210h–213h P2IS Port 2 Interrupt Status

214h–217h P2IE Port 2 Interrupt Enable

218h–21Ch P2CMD Port 2 Command

21Ch–21Fh — Reserved

220h–223h P2TFD Port 2 Task File Data

224h–227h P2SIG Port 2 Signature

228h–22Bh P2SSTS Port 2 Serial ATA Status

22Ch–22Fh P2SCTL Port 2 Serial ATA Control

230h–233h P2SERR Port 2 Serial ATA Error

234h–237h P2SACT Port 2 Serial ATA Active

238h–23Bh P2CI Port 2 Command Issue

23Ch–27Fh — Reserved

280h–2FFh

(Mobile Only) —Reserved

Registers are not available and software must

not read from or write to registers.

280h–283h P3CLB Port 3 Command List Base Address

284h–287h P3CLBU Port 3 Com mand Li st Base Address Upper 32-Bits

288h–28Bh P3FB Port 3 FIS Base Address

28Ch–28Fh P3FBU Port 3 FIS Base Address Upper 32-Bits

290h–293h P3IS Port 3 Interrupt Status

294h–297h P3IE Port 3 Interrupt Enable

298h–29Ch P3CMD Port 3 Command

29Ch–29Fh — Reserved

2A0h–2A3h P3TFD Port 3 Task File Data

2A4h–2A7h P3SIG Port 3 Signature

2A8h–2ABh P3SSTS Port 3 Serial ATA Status

2ACh–2AFh P3SCTL Port 3 Serial ATA Control

2B0h–2B3h P3SERR Port 3 Serial ATA Error

2B4h–2B7h P3SACT Port 3 Serial ATA Active

2B8h–2BBh P3CI Port 3 Command Issue

2BCh–2FFh — Reserved

Table 12-5. Port [3:0] DMA Register Address Map (Sheet 2 of 2)

ABAR +

Offset Mnemonic Register

Intel ® ICH7 Family Datasheet 531

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.1 PxCLB—Port [3:0] Command List Base Address Register

(D31:F2)

Address Offset: Port 0: ABAR + 10 0h Attribute: R/W, RO

Port 1: ABAR + 180h (ICH7R and ICH7DH Only)

Port 2: ABAR + 200h

Port 3: ABAR + 280h (ICH7R and ICH7DH Only)

Default Value: Undefined Size: 32 bits

12.3.2.2 PxCLBU—Port [3:0] Command List Base Address Upper

32-Bits Register (D31:F2)

Address Offset: Port 0: ABAR + 10 4h Attribute: R/W

Port 1: ABAR + 184h (ICH7R and ICH7DH Only)

Port 2: ABAR + 204h

Port 3: ABAR + 284h (ICH7R and ICH7DH Only)

Default Value: Undefined Size: 32 bits

12.3.2.3 PxFB—Port [3:0] FIS Base Address Register (D31:F2)

Address Offset: Port 0: ABAR + 10 8h Attribute: R/W, RO

Port 1: ABAR + 188h (ICH7R and ICH7DH Only)

Port 2: ABAR + 208h

Port 3: ABAR + 288h (ICH7R and ICH7DH Only)

Default Value: Undefined Size: 32 bits

Bit Description

31:10

Command List Base Address (CLB) — R/W. Indicates the 32-bit bas e for the

command list for this port. This base is used when fetching commands to execute. The

structure pointed to by this address range is 1 KB in lengt h. This address must be 1-KB

aligned as indicated by bits 31:10 being read/write.

Note that these bits are not reset on a HBA reset.

9:0 Reserved — RO

Bit Description

31:0

Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for

the command list base address for this port. This base is used when fetching

commands to execute.

Note that these bits are not reset on a HBA reset.

Bit Description

31:8

FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The

structure pointed to by this address range is 25 6 bytes in length. This address must be

256-byte aligned, as indicated by bits 31:3 being read/write.

Note that these bits are not reset on a HBA reset.

7:0 Reserved — RO

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

532 Intel ® ICH7 Family Datasheet

12.3.2.4 PxFBU—Port [3:0] FIS Base Address Upper 32-Bits

Address Offset: Port 0: ABAR + 10Ch Attribute: R/W

Port 1: ABAR + 18Ch

Port 2: ABAR + 20Ch

Port 3: ABAR + 28Ch

Default Value: Undefined Size: 32 bits

12.3.2.5 PxIS—Port [3:0] Interrupt Status Register (D31:F2)

Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO

Port 1: ABAR + 190h (ICH7R and ICH7DH Only)

Port 2: ABAR + 210h

Port 3: ABAR + 290h (ICH7R and ICH7DH Only

Default Value: 00000000h Size: 32 bits

Bit Description

31:3 FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received

FIS base for this port.

Note that these bits are not reset on a HBA reset.

2:0 Reserved

Bit Description

31 Cold Port Detect Status (CPDS) — RO. Cold presence not supported.

30 Task File Error Status (TFES) — R/WC. This bit is s et whenev er the statu s register i s

updated by the device and the error bit (PxTFD.bit 0) is set.

29 Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Intel® ICH7

encountered an error that it cannot recover from due to a bad software pointer. In PCI,

such an indication would be a target or master abort.

28 Host Bus Data Error Status (HBDS) — R/WC. Indi cates that the ICH7 encountered a

data error (uncorrectable ECC / parity) when reading from or writing to system

memory.

27 Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH7 encountered an

error on the SATA interface which caused the transfer to stop.

26 Interface Non-fatal Error Status (INFS) — R/WC. Indica tes that the ICH7

encountered an error on the SATA interface but was able to continue operation.

25 Reserved

24 Overflow Status (OFS) — R/WC. Indicates that the ICH7 received more bytes from a

device than was specified in the PRD table for the command.

23 Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH7 received

a FIS from a device whose Port Multiplier field did not match what was expected.

NOTE: Port Multiplier not supported by ICH7.

PhyRdy Change Status (PRCS) — RO. When se t to one indicates the int ernal PhyRdy

signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the

other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is

cleared.

Note that the internal PhyRdy signal also transitions when the port interface enters

partial or slumber power management states. Partial and slumber must be disabled

when Surprise R emoval Notificati on is desi red, otherwise the power m ana geme nt stat e

transitions will appear as false insertion and removal events.

Intel ® ICH7 Family Datasheet 533

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.6 PxIE—Port [3:0] Interrupt Enable Register (D31:F2)

Address Offset: Port 0: ABAR + 11 4h Attribute: R/W, RO

Port 1: ABAR + 194h (ICH7R and ICH7DH Only)

Port 2: ABAR + 214h

Port 3: ABAR + 294h (ICH7R and ICH7DH Only)

Default Value: 00000000h Size: 32 bits

This register enables and disables the reporting of the corresponding interrupt to

system software. When a bit is set (‘1’) and the corresponding interrupt condition is

active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still

reflected in the status registers.

21:8 Reserved

Device Interlock Status (DIS) — R/WC. When set, indica tes that a platform interlock

switch has been opened or closed, which may lead to a change in the connection state

of the device.This bit is only valid in systems that support an interlock switch (CAP.SIS

[ABAR+00:bit 28] set).

For systems that do not support an interlock switch, th is bit will always be 0.

Port Connect Change Status (PCS) — RO. This bit reflects the state of

PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this

0 = No change in Current Connect Status.

1 = Change in Current Connect Status.

5Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its

data.

Unknown FIS Interrupt (UFS) — RO. When set to ‘1’ indicates that an unknown FIS

was received and has been copied into system memory. This bit is cleared to ‘0’ by

software clearing the PxSERR.DIAG.F bit to ‘0’. Note that this bit does n ot directly

reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown

FIS is detected, whereas this bit is se t when the FIS is posted to memory. Software

should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may

become out of sync.

3Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received

with the I bit set and has been copied into system memory.

2DMA Setup FIS I n terrupt (DSS) — R/WC. A DMA Setup FIS has been received with

the I bit set and has b een copied into sys tem memory.

1PIO Setup FIS Interrupt ( PSS) — R/WC. A PIO Setup FIS has been received with the

I bit set, it has been copied into system memory, and the data related to that FIS has

been transferred.

0Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has

been received with the I bit set, and has been copied into system memory.

Bit Description

31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect not supported.

30 Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR

(due to a reception of the error register from a received FIS) are set, the Intel® ICH7

will generate an interrupt.

29 Host Bus Fatal Error Enable (HBFE) — R/W. Wh en set, and GHC.IE and PxS.HBFS

are set, the ICH7 will generate an interrupt.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

534 Intel ® ICH7 Family Datasheet

28 Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS

are set, the ICH7 will generate an interrupt.

27 Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and

PxIS.HBDS is set, the ICH7 will generate an interrupt.

26 Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and

PxIS.INFS is set, the ICH7 will generate an interrupt.

25 Reserved - Should be written as 0

24 Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set,

the ICH7 will generate an interrupt.

23 Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and

PxIS.IPMS are set, the ICH7 will generate an interrupt.

NOTE: Should be written as 0. Port Multiplier not supported by ICH7.

22 PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and

PxIS.PRCS is set, the ICH7 shall generate an interrupt.

21:8 Reserved - Should be written as 0

7Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH7 will

generate an interrupt.

For systems that do not support an interlock switch, this bit shall be a read-only 0.

6Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS

are set, the ICH7 will generate an interrupt.

5Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and

PxS.DPS are set, the ICH7 will generate an interrupt

4Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an

unknown FIS is received, the ICH7 will generate this interrupt.

3Set Device Bit s FI S I nterrupt Enable (SDBE) — R/W. When set, and GHC.IE and

PxS.SDBS are se t, the ICH7 will generate an interrupt.

2DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS

are set, the ICH7 will generate an interrupt.

1PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PS S

are set, the ICH7 will generate an interrupt.

0Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set , and

GHC.IE and PxS.DHRS are set, the ICH7 will generate an interrupt.

Bit Description

Intel ® ICH7 Family Datasheet 535

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.7 PxCMD—Port [3:0] Command Register (D31:F2)

Address Offset: Port 0: ABAR + 11 8h Attribute: R/W, RO, R/WO

Port 1: ABAR + 198h (ICH7R and ICH7DH Only)

Port 2: ABAR + 218h

Port 3: ABAR + 298h (ICH7R and ICH7DH Only)

Default Value: 0000w00wh Size: 32 bits

where w = 00?0b (for?, see bit description)

Bit Description

31:28

Interface Communication Control (I CC) — R/W. This is a four bit field which can be

used to control reset and power states of the interface. Writes to this field will cause

actions on the interface, either as primitives or an OOB sequence, and the resulting

status of the interface will be reported in the PxSSTS register (Address offset Port

0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h).

When system software writes a non-reserved value other than No-Op (0h), the ICH7 will

perform the action and update this field back to Idle (0h).

If software writes to this field to change the state to a state the link is already in (e.g.

interface is in the ac tive s tate and a request is made to go t o the activ e state), the ICH7

will take no action and return this field to Idle.

NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or

06h.

Aggressive Slum ber / Partial (ASP) — R/W. When set, and the ALPE bit (bit 26) is

set, the ICH7 will aggressively enter the slumber state when it clears the PxCI register

and the PxSACT register is cleared. When cleared, and th e ALPE bi t i s se t, th e ICH7 wil l

aggressively enter the partial stat e when it clears the PxCI register and the PxSACT

26 Aggressive Link Power Management Enable (ALPE) — R/W. When set, the ICH7

will aggressively enter a lower link power state (partial or slumber) based upon the

setting of the ASP bit (bit 27).

Drive LED on ATA PI En able (DLAE) — R/W. When set, the ICH7 will drive the LED

pin active for AT API commands (PxCLB[CHz.A] set) in addition to A TA commands. When

cleared, the ICH7 will only drive the LED pin active for ATA commands. See

Section 5.17.5 for details on the activity LED.

24 HDevice is ATAPI (ATA PI) — R/W. When set, the connected device is an ATAPI

device. This bit is used by the ICH7 to control whether or not to generate the desk top

LED when commands are active. See Section 5.17.5 for details on the activity LED.

23:20 Reserved

Value Definition

Fh–7h Reserved

6h Slumber: This will cause the Intel® ICH7 to request a transition of the

interface to the slumber state. The SATA device may reject the request

and the interface will remain in its current state

5h–3h Reserved

2h Partial: This will cause the ICH7 to request a transition of the interface

to the partial st ate. The SATA device may reject the request and the

interface will remain in its current state.

1h Active: This will cause the ICH7 to request a transition of the interface

into the active

0h No-Op / Idle: When software reads this value, it indicates the ICH7 is

not in the process of changing the interface stat e or sending a device

reset, and a new link command may be issued.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

536 Intel ® ICH7 Family Datasheet

Interlock Switch Attached to Port (ISP) — R/WO. When interlock switches are

supported in the platform (CAP.SIS [ABAR+00h:bit 28] set), this indicates whether this

particular port has an interlock switch attached. This bit can be used by system software

to enable such features as aggressive power management, as disconnects can always

be detected regardless of PHY state with an interlock switch. When this bit is set, it is

expected that HPCP (bit 18) in this register is also set.

The ICH7 takes no action on the state of th is bit – it is for system software only. For

example, if this bit is cleared, and an interlock switch toggles, the ICH7 still treats it as

a proper interlock switch event.

Note that these bits are not reset on a HBA reset.

Hot Plug Capable Port (HPCP) — R/WO.

0 = Port is not capable of Hot-Plug.

1 = Port is Hot-Plug capable.

This indicate s whether the platform exposes this port to a device which can be Hot-

Plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to

allow the device to be removed (it may be screwed into the chassis, for example). This

bit can be used by system software to indicate a feature such as “eject device” to the

end-user. The ICH7 takes no action on the state of this bit - it is for system software

only. For example, if this bit is cleared, and a Hot-Plug event occurs, the ICH7 still treats

it as a proper Hot-Plug event.

Note that these bits are not reset on a HBA reset.

Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port multiplier is

attached to the ICH7 for this port. When cleared, a port multiplier is not atta ched to this

port.

This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS =

NOTE: Port Multiplier not supported by ICH7.

16 Port Multiplier FIS Based Switching Enable (PMFSE) — RO. The ICH7 does not support

FIS-based switching.

NOTE: Port Multiplier not supported by ICH7.

15 Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are

running. See section 5.2.2 of the Serial ATA AHCI Specification for details on when this

bit is set and cleared by the ICH7.

14 FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port

is running. See section 12.2.2 of the Serial ATA AHCI Specification for details on when

this bit is set and cleared by the ICH7.

Interloc k Sw itch State (ISS) — RO. For systems that support interlock switches (via

CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this

switch is closed, and a 1 indicates the switch is opened.

For systems that do not support interlock switches, or if an interlock switch is not

attached to this port, this bit reports 0.

12:8

Current Command Slot (CCS) — RO. Indicates the current command slot the ICH7 is

processing. This field is valid when the ST bit is set in this register, and is constantly

updated by the ICH7. This field can be updated as soon as the ICH7 recogniz es an active

command slot, or at some point soon after when it begins processing the command.

This field is used by software to determine the current command issue location of the

ICH7. In queued mode, software shall not use this field, as its value does not represent

the current command being executed. Software shall only use PxCI and PxSACT when

running queued commands.

7:5 Reserved

Bit Description

Intel ® ICH7 Family Datasheet 537

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

FIS Receive Enable (FRE) — R/W. When set, the ICH7 may post received FISes into

the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU

(ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by the

ICH7, except for the first D2H (device-to-host) register FIS after the initialization

sequence.

System software m ust not set this bi t until P xFB (PxFBU) have been progr ammed wit h a

valid pointer to the FIS receive area, and if software wishes to move the base, this bit

must first be cleared, and software must wait for the FR bit (bit 14) in this register to be

cleared.

Command List Override (CLO) — R/W. Setting this bit to '1' causes PxTFD.STS.BSY and

PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be transmitted to

the device regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS

been cleared to '0'. A write to this register with a value of '0' shall have no effect.

This bit shall only be se t t o '1' immediately prior to setting the PxCMD.ST bit to '1' f rom

a previous value of '0'. Setting this bit to '1' at any other time is not supported and will

result in indeterminate behavior

2 Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.

Spin-Up Device (SUD) — R/W / RO. This bit i s R/W an d defaults to 0 for systems th at

support staggered spin-up (R/W when CAP.SSS (ABAR+00h:bit 27) is 1) . Bit is RO 1 for

systems that do not support staggered spin-up (when CAP.SSS is 0).

0 = No action.

1 = On an edge detect from 0 to 1, the ICH7 starts a COMRESET initialization sequence

to the device.

Start (ST) — R/W. When set, the ICH7 may process the command list. When cleared,

the ICH7 may not process the command list. Whenever this bit is changed from a 0 to a

1, the ICH7 starts proces sing the command list at entry 0. Whenev er this bit is changed

from a 1 to a 0, the PxCI register is cleared by the ICH7 upon the ICH7 putting the

controller into an idle state.

Refer to section 10.3.1 of the Serial AT A AHCI Specification for important restrictions on

when ST can be set to 1.

Bit Description

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

538 Intel ® ICH7 Family Datasheet

12.3.2.8 PxTFD—P ort [3:0] Task File Data Register (D31:F2)

Address Offset: Port 0: ABAR + 120h Attribute: RO

Port 1: ABAR + 1A0h (ICH7R and ICH7DH Only)

Port 2: ABAR + 220h

Port 3: ABAR + 2A0h (ICH7R and ICH7DH Only)

Default Value: 0000007Fh Size: 32 bits

This is a 32-bit register that copies specific fields of the task file when FISes are

received. The FISes that contain this information are:

D2H Register FIS

PIO Setup FIS

Set Device Bits FIS

12.3.2.9 PxSIG—Port [3:0] Signature Register (D3 1:F2)

Address Offset: Port 0: ABAR + 124h Attribute: RO

Port 1: ABAR + 1A4h (ICH7R and ICH7DH Only)

Port 2: ABAR + 224h

Port 3: ABAR + 2A4h (ICH7R and ICH7DH Only)

Default Value: FFFFFFFFh Size: 32 bits

This is a 32-bit register which contains the initial signature of an attached device when

the first D2H Register FIS is received from that device. It is updated once after a reset

sequence.

Bit Description

31:16 Reserved

15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.

7:0

Status (STS) — RO. Contains the latest copy of the task file status register. Fields of

note in this register that affect AHCI.

Bit Field Definition

7 BSY Indicates the interface is busy

6:4 N/A N ot applicable

3DRQ

Indicates a data transfer is

requested

2:1 N/A N ot applicable

0ERR

Indicates an error during the

transfer

Bit Description

31:0

Signature (S IG) — RO. Contains the signature received from a device on the first D2H

Bit Field

31:24 LBA High Register

23:16 LBA Mid Register

15:8 LBA Low Register

7:0 Sector Count Register

Intel ® ICH7 Family Datasheet 539

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.10 PxSSTS—Port [3:0] Serial ATA Status Register (D31:F2)

Address Offset: Port 0: ABAR + 128h Attribute: RO

Port 1: ABAR + 1A8h (Desktop Only)

Port 2: ABAR + 228h

Port 3: ABAR + 2A8h (Desktop Only)

Default Value: 00000000h Size: 32 bits

This is a 32-bit register that conveys the current state of the interface and host. The

ICH7 updates it continuously and asynchronously. When the ICH7 transmits a

COMRESET to the device, this register is updated to its reset values.

Bit Description

31:12 Reserved

11:8

Interface Power Management (IPM) — RO. Indicates the current interface state:

All other values reserved.

7:4

Current Interface Speed (SPD) — RO. Indicates the negotiated interface

communication speed.

All other values reserved.

Intel® ICH7 supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates

(3.0 Gb/s).

ICH7 Mobile SKUs support Generation 1 communication rates (1.5 Gb/sec ).

3:0

Device Detection (DET) — RO. Indicates the interface device detection and Phy

state:

All other values reserved.

ue Descr

0h Device not present or communication not established

1h Interface in active state

2h Interface in PARTIAL power management state

6h Interface in SLUMBER power management state

escr

0h Device not present or communication not established

1h Generation 1 communication rate negotiated

2h Generation 2 communication rate negotiated

Value Description

0h No device detected and Phy communication not established

1h Device presence detected but Phy communication not est a blished

3h Device presence detected and Phy communication est a blished

4h Phy in offline mode as a result of the interface being disabled or

running in a BI ST loopback mode

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

540 Intel ® ICH7 Family Datasheet

12.3.2.11 PxSCTL — Port [3:0] Serial ATA Control Reg i ster (D31:F2)

Address Offset: Port 0: ABAR + 12Ch Attrib ute: R/W, RO

Port 1: ABAR + 1ACh (Desktop Only

Port 2: ABAR + 22Ch

Port 3: ABAR + 2ACh (Desktop Only)

Default Value: 00000004h Size: 32 bits

This is a 32-bit read-write register by which software controls SATA capabilities. W rites

to the SControl register result in an action being taken by the ICH7 or the interface.

Reads from the register return the last value written to it.

Bit Description

31:20 Reserved

19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI

NOTE: Port Multiplier not supported by Intel® ICH7.

15:12 Select Power Management (SPM) — RO. This field is not used by AHCI

11:8

Interface Po wer Management Tran sitions Allowed (IP M) — R/W. Indicates which

power states the ICH7 is allowed to transition to:

All other values reserved

7:4

Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.

This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.

All other values reserved

ICH7 Supports Generation 1 communication rates (1.5 Gb/sec) and G en 2 rates (3.0

Gb/s).

ICH7 Mobile SKUs support Generation 1 communication rates (1.5 Gb/sec).

3:0

Device Detecti on Initialization (DET) — R/W. Controls the ICH7’s device detection

and interface initialization.

All other values reserved.

When this field is written to a 1h, the ICH7 initiates COMRESET and starts the

initialization process . When the initiali zation is complete, this field shall remain 1h until

set to another value by software.

This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field

while the ICH7 is running results in undefined behavior.

Value Description

0h No interface restrictions

1h Transitions to the PARTIAL state disabled

2h Transitions to the SLUMBER stat e disabled

3h Transitions to both PARTIAL and SLUMBER states disabled

Value Description

0h No speed negotiation restrictions

1h Limit speed negotiation to Generation 1 communication rate

2h Limit speed negotiation to Generation 2 communication rate

Value Description

0h No device detection or initialization action requested

Perform interface communication initialization sequence to

establish com munication. This is functionally equivalent to a hard

reset and results in the interface being reset and communications

re-initialized

4h Disable the Serial ATA interface and put Phy in offline mode

Intel ® ICH7 Family Datasheet 541

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.12 PxSERR—Port [3:0] Serial ATA Error Register (D31:F2)

Address Offset: Port 0: ABAR + 13 0h Attribute: R/WC

Port 1: ABAR + 1B0h (ICH7R and ICH7DH Only)

Port 2: ABAR + 230h

Po rt 3: ABA R + 2B 0h (I CH 7R and ICH7DH Only)

Default Value: 00000000h Size: 32 bits

Bit Description

31:16

Diagnostics (DIAG) — R/WC. Contains diagnostic error information for use by

diagnostic software in validating correct operation or isolating failure modes:

Bits Description

31:27Reserved

26 Exchanged (X): When set to one this bi t indicates a COMINIT signal was

received. This bit is reflected in the interrupt register PxIS.PCS.

25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by

the Transport layer with good CRC, but had a type field that was not recognized.

24 Transport state transition error (T): Indicates that an error has occurred in

the transition from one state to another within the Transport layer since the last

time this bit was cleared.

23 Link Sequence Error (S): Indicates that one or more Link state machine error

conditions was encountered. The Link Layer state machine defines the conditions

under which the link layer detects an erroneous transition.

22 Handshake Erro r (H ) : Indicates that one or more R_ERR handshake response

was received in response to frame transmission. Such errors may be the result of

a CRC error detected by the recipient, a disparity or 8b/10b decoding error, or

other error condition le ading to a negative handshake on a transmitted frame.

21 CRC Error (C) : Indicates that one or more CRC errors occurred with the Link

Layer.

20 Disparity Error (D): This field is not used by AHCI.

19 10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding

errors occurred.

18 Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.

17 Phy Internal Error (I): Indicates that the Phy detected some internal error.

16 PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy

signal changed state since the last time this bit was cleared. In the Intel® ICH7,

this bit will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of

this bit is then reflected in the PxIS.PRCS interrupt status bit and an interrupt will

be generated if enabled. Software clears this bit by writing a 1 to it.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

542 Intel ® ICH7 Family Datasheet

12.3.2.13 P xSACT—Port [3:0] Serial ATA Active (D31:F2)

Address Offset: Port 0: ABAR + 134h Attribute: R/W

Port 1: ABAR + 1B4h (ICH7R and ICH7DH Only)

Port 2: ABAR + 234h

Port 3: ABAR + 2B4h (ICH7R and ICH7DH Only)

Default Value: 00000000h Size: 32 bits

15:0

Error (ERR) — R/WC. The ERR field contains error information for use by host

software in determining the appropriate response to the error condition.

If one or more of bits 11:8 of this register are set, the controller will stop the current

transfer.

Bits Description

15:12Reserved

11 Internal Error (E): The SATA controller failed due to a master or target abort

when attempting to access system memory.

10 Protocol Error (P): A violation of the Serial ATA protocol was detected. Note:

The ICH7 does not set this bit for all protocol violations that may occur on the

SATA link.

9 Persistent Communication or Data Integ rity Erro r (C): A communication

error that was not recovered occurred that is expected to be persistent.

Persistent communications errors may arise from faulty interconnect with the

device, from a device that has been removed or has failed, or a number of other

causes.

8 Transien t Data Integri ty Error (T): A data integrity error occurred that was

not recovered by the interface.

7:2 Reserved

1Recovered Communications Error (M): Communications between the device

and host was temporarily lost but was re-established. This can arise from a

device temporarily being remov ed, from a tempor ary loss of Phy synchronization,

or from other causes and may be derived from the PhyNRdy signal between the

Phy and Link layers.

0Recovered Data Integrity Error (I): A data integrity error occurred that was

recovered by the interface through a retry operation or other recovery action.

Bit Description

31:0

Device Status (DS) — R/W. S ystem software sets this bit for SA TA queuing operations

prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via

the Set Device Bits FIS.

This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is

cleared by software, and as a result of a COMRESET or SRST.

Intel ® ICH7 Family Datasheet 543

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

12.3.2.14 P xCI—Port [3:0] Command Issue Register (D31:F2)

Address Offset: Port 0: ABAR + 13 8h Attribute: R/W

Port 1: ABAR + 1B8h (ICH7R and ICH7DH Only)

Port 2: ABAR + 238h

Port 3: ABAR + 2B8h (ICH7R and ICH7DH Only)

Default Value: 00000000h Size: 32 bits

Bit Description

31:0

Commands Issued (CI) — R/W. This field is set by software to indicate to the Intel®

ICH7 that a command has been built-in system memory for a command slot and may

be sent to the device. When the ICH7 receives a FIS which clears the BSY and DRQ bits

for the command, it clears the corresponding bit in this register for that command slot.

This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is

cleared by software.

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)

544 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 545

EHCI Controller Registers (D29:F7)

13 EHCI Controller Registers

(D29:F7)

13.1 USB EHCI Configuration Registers

(USB EHCI—D29:F7)

Note: Register address locations that are not shown in Table 13-1 should be treated as

Reserved (see Section 6.2 for details).

Note: All configuration registers in this section are in the core well and reset by a core well

reset and the D3-to-D0 warm reset, except as noted.

Table 13-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F7) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Val

ue Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0290h R/W, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 20h RO

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 0Ch R O

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h MEM_BASE Memory Base Address 00000000h R/W, RO

2Ch–2Dh SVID USB EHCI Subsystem Vendor

Identification XXXXh R/W

(special)

2Eh–2Fh SID USB EHCI Subsystem

Identification XXXXh R/W

(special)

34h CAP_PTR Capabilities Pointer 50h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

50h PWR_CAPID PCI Power Management Capability

ID 01h RO

51h NXT_PTR1 Next Item Pointer #1 58h R/W

(special)

52h–53h PWR_CAP Power Managem ent Capabilities C9C2h R/W

(special)

54h–55h PWR_ CNTL_STS P owe r Management Control/ Status 0000h R/W, R/WC,

EHCI Controller Registers (D29:F7)

546 Intel ® ICH7 Family Datasheet

13.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F7)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

13.1.2 DID—Device Identification Register

(USB EHCI—D29:F7)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

58h DEBUG _CAPID Debug Port Capability ID 0Ah RO

59h NXT_PTR2 Next Item Pointer #2 00h RO

5Ah–5Bh DEBUG_BASE Debug Port Base Offset 20A0h RO

60h USB_RELNUM USB Release Number 20h RO

61h FL_ADJ Frame Length Adjustment 20h R/W

62h–63h PWAKE_CAP Port Wake Capabilities 01FFh R/W

64h–67h — Reserved — —

68h–6Bh LEG_EXT_CAP USB EHCI Legacy Support

Extended Capability 00000001h R/W, RO

6Ch–6Fh LEG_EXT_CS USB EHCI Legacy Extended

Support Control/Status 00000000h R/W , R/WC,

70h–73h SPECIAL_SMI Intel Specific USB 2.0 SMI 00000000h R/W, R/WC

74h–7Fh — Reserved — —

80h ACCESS_CNTL Access Control 00h R/W

Table 13-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F7) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Val

ue Type

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 USB EHCI

controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

for the value of the Device ID Register.

Intel ® ICH7 Family Datasheet 547

EHCI Controller Registers (D29:F7)

13.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F7)

Address Offset: 0h4–05h Attribute: R/W , RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable — R/W.

0 = The function is capable of generating interrupts .

1 = The function can not generate its interrupt to the interrupt controller.

Note that the corresponding Interrupt Status bit (D29:F7:06h, bit 3) is not affected by

the interrupt enable.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

SERR# Enable (SERR_EN) — R/W.

0 = Disables EHC’s capability to generate an SERR#.

1 = The Enhanced Host controller (EHC) is capable of generatin g (i nt ern a ll y) SE RR#

when it receive a completion status other than “successful” for one of its DMA-

initiated memory reads on DMI (and subsequently on its internal interface).

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

Parity Error Response (PER) — RO.

1 = EHCI Host Controller will check for correct parity and halt operation when bad parity is detected

during the data phase as recommended by the EHCI specification. If it detects bad parity on

the address or command phases when this bit is set to 1, the host controller does not take the

cycle, halts the host controller (if currently not halted), and sets the host system error bit in the

USBSTS register. Note that this applies to both requests and completions from the system

interface.

This bit must be set in order for the parity errors to generate SERR# .

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2Bus Master Enable (BME) — R/W.

0 = Disables this functionality.

1 = Enables the Intel® ICH7 to act as a master on the PCI bus for USB transfers.

Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory

Space registers.

0 = Disables this functionality.

1 = Enables accesses to the USB 2 .0 registers. The Base Addres s register

(D29:F7:10h) for USB 2.0 should be programmed before this bit is set.

0 I/O Space Enable (IOSE) — RO. Hardwired to 0.

EHCI Controller Registers (D29:F7)

548 Intel ® ICH7 Family Datasheet

13.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F7)

Address Offset: 06h–07h Attribute: R/W, RO

Default Value: 0290h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — RO. Hardwired to 0.

Signaled System Error (SSE) — R/W.

0 = No SERR# signaled by Intel® ICH7.

1 = This bit is set by the ICH7 when it signals SERR# (internally). The SER_EN bit (bit

8 of the Command Register) must be 1 for this bit to be set.

Received Master Abort (RMA) — R/W.

0 = No master abort received by EHC on a memory access.

1 = This bit is set when EHC, as a master, receives a master abort status on a memory

access. This is treated as a Host Error and halts the DMA engines. This event can

optionally generate an SERR# by setting the SERR# Enable bit.

Received Target Abort (RTA) — R/W.

0 = No target abort received by EHC on memory access.

1 = This bit is set when EHC, as a master, receives a target abort status on a memory

access. This is treated as a Host Error and halts the DMA engines. This event can

optionally generate an SERR# by setting the SERR# Enable bit (D29:F7:04h, bit

8).

Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function

responds to a cycle with a target abort. There is no reason for this to happen, so this bit

will be

hardwired to 0.

10:9 DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for

DEVSEL# assertion.

Master Data Parity Error Detected (DPED) — R/W.

0 = No data parity error detected on USB2.0 read completion packet.

1 = This bit is set by the ICH7 when a data parity error is detected on a USB 2.0 read

completion packet on the internal interface to the EHCI host controller and bit 6 of

the Command register is set to 1.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 1 indica ting that offset 34h contains a

valid capabilities pointer.

Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the

input of the enable/disable logic.

0 = This bit will be 0 when the interrupt is de-asserted.

1 = This bit is a 1 when the interrupt is asserted.

The value reported in this bit is independent of the value in the Interrupt Enable bit.

2:0 Reserved

Intel ® ICH7 Family Datasheet 549

EHCI Controller Registers (D29:F7)

13.1.5 RID—Revision Identification Register

(USB EHCI—D29:F7)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

13.1.6 PI—Programming Interface Register

(USB EHCI—D29:F7)

Address Offset: 09h Attribute: RO

Default Value: 20h Size: 8 bits

13.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F7)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

13.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F7)

Address Offset: 0Bh Attribute: RO

Default Value: 0Ch Size: 8 bits

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

Bit Description

7:0 Programming Inte rface — RO. A v alue of 20h indica tes that this USB 2.0 host controller

conforms to the EHCI Specification.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = Universal serial bus host controller.

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial bus controller.

EHCI Controller Registers (D29:F7)

550 Intel ® ICH7 Family Datasheet

13.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F7)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

13.1.10 MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F7)

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

13.1.11 SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F7)

Address Offset: 2Ch–2Dh Attribute: R/W (special)

Default Value: XXXXh Size: 16 bits

Reset: None

Bit Description

7:0 Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI

controller is internally implemented with arbitration on an interface (and not PCI), it

does not need a master latency timer.

Bit Description

31:10 Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10],

respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.

9:4 Reserved

3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.

2:1 Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere

within 32-bit address space.

0Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address

field in this register maps to memory space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/W (s pecial). This register, in combination with th e

USB 2.0 Subsystem ID register, enables the operating system to distinguish each

subsystem from the others.

NOTE: Writ es to t his regis ter are enable d whe n the WRT_RDONLY bit (D29:F7:80h, bit

0) is set to 1.

Intel ® ICH7 Family Datasheet 551

EHCI Controller Registers (D29:F7)

13.1.12 SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F7)

Address Offset: 2Eh–2Fh Attribute: R/W (special)

Default Value: XXXXh Size: 16 bits

Reset: None

13.1.13 CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F7)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

13.1.14 INT_LN—Interrupt Line Register

(USB EHCI—D29:F7)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

13.1.15 INT_PN—Interrupt Pin Register

(USB EHCI—D29:F7)

Address Offset: 3Dh Attribute: RO

Default Value: See Description Size: 8 bits

Bit Description

15:0

Subsystem ID (SID) — R/W (special). BIOS sets the value in this register to identify

the Subsystem ID. This register, in combination with the Subsystem V endor ID register,

enables the operating system to distinguish each subsystem from other(s).

NOTE: Writes to th is regist er are enabled when the WRT_RDONLY bit (D29:F7:80h, bit

0) is set to 1.

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the

USB 2.0 capabilities ranges.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH7. It is used

as a scratchpad register to communicate to software the interrupt line that the

interrupt pi n is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D29IP.EIP (Chipset Config

Regi st ers : Offse t 3108 :bit s 31:28) .

NOTE: Bits 7:4 are always 0h

EHCI Controller Registers (D29:F7)

552 Intel ® ICH7 Family Datasheet

13.1.16 PWR_CAPID—PCI Power Management Capability ID

Address Offset: 50h Attribute: RO

Default Value: 01h Size: 8 bits

13.1.17 NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F7)

Address Offset: 51h Attribute: R/W (special)

Default Value: 58h Size: 8 bits

13.1.18 PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F7)

Address Offset: 52h–53h Attribute: R/W (special)

Default Value: C9C2h Size: 16 bits

Bit Description

7:0 Power Management Capability ID — RO. A value of 01h indicates that this is a PCI

Power Management capabilities field.

Bit Description

7:0

Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which

indicates that the next capability registers begin at config uration offse t 58h . This

BIOS to effectively hide the Debug Port capability registers, if ne cessary. This register

should only be written during system initialization before the plug-and-play software

has enabled any master-initiated traffic. Only values of 58h (Debug Port visible) and

00h (Debug Port invisible) are expected to be programmed in this register.

NOTE: Register not reset by D3-to-D0 warm reset.

Bit Description

15:11

PME Support (PME_SUP) — R/W (special). This 5-bit field indicates the power stat es

in which the function may assert PME#. The Intel® ICH7 EHC does not support the D1

or D2 states. For all other states, the ICH7 EHC is capable of generating PME#.

Software should not need to modify this field.

10 D2 Support (D2_SUP) — R/W (special).

0 = D2 State is not supported

1 = D2 State is supported

9D1 Support (D1_SUP) — R/W (special).

0 = D1 State is not supported

1 = D1 State is supported

8:6 Auxiliary Current (AUX_CUR) — R/W (special). The ICH7 EHC reports 375 mA

maximum suspend well current required when in the D3COLD state. This value ca n be

written by BIOS when a more accurate value is known.

5Device Specific Initialization (DSI)— R/W (special). The ICH7 reports 0, indicating

that no

device-spec if ic initializati on is required.

Intel ® ICH7 Family Datasheet 553

EHCI Controller Registers (D29:F7)

NOTES:

1. Normally, this register is read-only to report capabilities to the power management

software. To report different power management capabilities, depending on the system in

which the ICH7 is used, bits 15:11 and 8:6 in this register are writable when the

WRT_RDONLY bit (D29:F7:80h, bit 0) is set. The value written to this register does not

affect the hardware other than changing the value returned during a read.

2. Reset: core well, but not D3-to-D0 warm reset.

13.1.19 PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F7)

Address Offset: 54h–55h Attribute: R/W, R/WC, RO

Default Value: 0000h Size: 16 bits

4 Reserved

3PME Clock (PME_CLK) — R/W (special). The ICH7 reports 0, indicating that no PCI

clock is required to generate PME#.

2:0 Version (VER) — R/W (special). The ICH7 reports 010b, indicating that it complies

with Revision 1.1 of the PCI Power Management Specification.

Bit Description

PME Status — R/WC.

0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if

enabled).

1 = This bit is set when the Intel® ICH7 EHC would normally assert the PME# signal

independent of the state of the PME_En bit.

NOTE: This bit must be explicitly cleared by the operating system each time the

operating system is loaded.

14:13 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data

12:9 Data Select — RO. Hardwired to 0000b indicating it does not support the associated

Data register.

PME Enable — R/W.

0 = Disable.

1 = Enable. Enable s ICH7 EHC to generate an internal PME signal when PME_Status is

NOTE: This bit must be explicitly cleared by the operating system each time it is

initially loaded.

7:2 Reserved

EHCI Controller Registers (D29:F7)

554 Intel ® ICH7 Family Datasheet

NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.

13.1.20 DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F7)

Address Offset: 58h Attribute: RO

Default Value: 0Ah Size: 8 bits

13.1.21 NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F7)

Address Offset: 59h Attribute: RO

Default Value: 00h Size: 8 bits

13.1.22 DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F7)

Address Offset: 5Ah–5Bh Attribute: RO

Default Value: 20A0h Size: 16 bits

1:0

Power State — R/W. This 2 -bit field is used both to determine the current power state

of EHC function and to set a new power state. The definition of the field values are:

00 = D0 st ate

11 = D3HOT state

If software attempts to write a value of 10b or 01b in to this field, the write operation

must complete normally; however, the data is discarded and no state change occurs.

When in the D3HOT state, the ICH7 must not accept accesses to the EHC memory

range; but the configuration space must still be accessible. When not in the D0 st ate,

the generation of the interrupt output is blocked. Specifically , the PIRQH is not asserted

by the ICH7 when not in the D0 state.

When software changes this value from the D3HOT state to the D0 state, an internal

warm (soft) reset is generated, and software must re-initialize the function.

Bit Description

7:0 Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a

Debug Port Capability structure.

Bit Description

7:0 Next Item Pointer 2 Capability — RO. Hardwired to 00h to indicate there are no more

capability structures in this function.

Bit Description

15:13 BAR Number — RO. Hardwired to 001b to indicate the memory BAR begins at offset

10h in the EHCI configuration space.

12:0 Debug Port Offset — RO. Hardwi red to 0A0h to i ndicate that the Debug Port registers

begin at offset A0h in the EHCI memory range.

Intel ® ICH7 Family Datasheet 555

EHCI Controller Registers (D29:F7)

13.1.23 USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F7)

Address Offset: 60h Attribute: RO

Default Value: 20h Size: 8 bits

13.1.24 FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F7)

Address Offset: 61h Attribute: R/W

Default Value: 20h Size: 8 bits

This feature is used to adjust any offset from the clock source that generates the clock

that drives the SOF counter. When a new value is written into these six bits, the length

of the frame is adjusted. Its initial programmed value is system dependent based on

the accuracy of hardware USB clock and is initialized by system BIOS. This register

should only be modified when the HChalted bit (D29:F7:CAPLENGTH + 24h, bit 12) in

the USB2.0_STS register is a 1. Changing value of this register while the host controller

is operating yields undefined results. It should not be reprogrammed by USB system

software unless the default or B IOS program med v alues are incorrect, or the system is

restoring the register while returning from a suspended state.

These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

7:0 USB Release Number — RO. A value of 20h indicates that this controller follows

Universal Serial Bus (USB) Specificatio n, Revision 2.0.

Bit Description

7:6 Reserved — RO. These bits are reserved for future use and should read as 00b.

5:0

Frame Length Timing Value — R/W. Each decimal value change t o this register

corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter

clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this

field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.

Frame Length (# 480 MHz

Clocks) (decimal) Frame Length Timing Value (this

59488 0

59504 1

59520 2

——

59984 31

60000 32

——

60480 62

60496 63

EHCI Controller Registers (D29:F7)

556 Intel ® ICH7 Family Datasheet

13.1.25 PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F7)

Address Offset: 62–63h Attribute: R/W

Default Value: 01FFh Size: 16 bits

This register is in the suspend power well. The intended use of this register is to

establish a policy about which ports are to be used for wake events. Bit positions 1–8 in

the mask correspond to a physical port implemented on the current EHCI controller. A 1

in a bit position indicates that a device connected below the port can be enabled as a

wake-up device and the port may be enabled for disconnect/connect or overcurrent

events as wake-up events. This is an information-only mask register. The bits in this

specific policy can be established by BIOS initializing this register to a system-specific

value. S ystem software uses the information in this register when enabling devices and

ports for remote wake-up.

These bits are not reset by a D3-to-D0 warm rest or a core well reset.

13.1.26 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F7)

Address Offset: 68–6Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Power Well: Suspend

NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

15:9 Reserved — RO.

8:1 Port Wake Up Capability Mask — R/W. Bit positions 1 through 8 correspond to a

physical port implemented on this host controller. For example, bit position 1

corresponds to port 0, bit position 2 corresponds to port 1, etc.

0Port Wake Implemented — R/W. A 1 in this bit indicates that this register is

implemented to software.

Bit Description

31:25 Reserved — RO. Hardwired to 00h

24 HC OS Owned Semaphore — R/W. System software sets this bit to request ownership

of the EHCI co ntroll er. Ownershi p is obtained when this bi t reads as 1 an d the HC B IOS

Owned Semaphore bit reads as clear.

23:17 Reserved — RO. Hardwired to 00h

16 HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of

the EHCI controller. System BIOS will clear this bit in response to a request for

ownership of the EHCI controller by system software.

15:8 Next EHCI Capability Pointer — RO. Hardwired to 00h to indicate that there are no

EHCI Extended Capability structures in this device.

7:0 Capability ID — RO. Hardwired to 01h to indicate that this EHCI Extended Capability is

the Legacy Support Capability.

Intel ® ICH7 Family Datasheet 557

EHCI Controller Registers (D29:F7)

13.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F7)

Address Offset: 6C–6Fh Attribute: R/W, R/WC, RO

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

31 SMI on BAR — R/WC. Software clears this bit by writing a 1 to it.

0 = Base Address Register (BAR) not written.

1 = This bit is set to 1 when the Base Address Register (BAR) is written.

30 SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it.

0 = PCI Command (PCICMD) Register Not written.

1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written.

SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it.

0 = No HC OS Owned Semaphore bit change.

1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP

28:22 Reserved — RO. Hardwired to 00h

SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async

Advance bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the Interrupt on Async

Advance bit in the USB2.0_STS register.

SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in

the USB2.0_STS register (D29:F7:CAPLENGTH + 24h, bit 4).

NOTE: To clear this bit system software must write a 1 to the Host System Error bit in

the USB2.0_STS register.

SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit

(D29:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.

NOTE: To clear this bit s yste m soft wa re must write a 1 to the Frame List Rollo v er bit in

the USB2.0_STS register.

SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit

(D29:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the P ort Change Detect bit in

the USB2.0_STS register.

SMI on USB Error — RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT)

bit (D29:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.

NOTE: To clear this bit sy stem softw are must wr ite a 1 to the USB Error Interrupt bit in

the USB2.0_STS register.

SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit

(D29:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.

NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the

USB2.0_STS register.

EHCI Controller Registers (D29:F7)

558 Intel ® ICH7 Family Datasheet

SMI on BAR Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on BAR (D29:F7: 6Ch, bit 31) is 1, then the host

controller will issue an SMI.

SMI on PCI Command Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7:6Ch, bit 30) is 1,

then the host controller will issue an SMI.

SMI on OS Ownership Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7:6Ch, bit

29) is 1, the host controller will issue an SMI.

12:6 Reserved — RO. Hardwired to 00h

SMI on Async Advance Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7:6Ch, bit

21) is a 1, the host controller will issue an SMI immediately.

SMI on Host System Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7:6Ch, bit

20) is a 1, the host controller will issue an SMI.

SMI on Frame List Rollover Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7:6Ch,

bit 19) is a 1, the host controller will issue an SMI.

SMI on Port Change Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7:6Ch,

bit 18) is a 1, the host controller will issue an SMI.

SMI on USB Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7:6Ch, bit 17) is a

1, the host controller will issue an SMI immediately.

SMI on USB Complete Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7:6Ch, bit

16) is a 1, the host controller will issue an SMI immediately.

Bit Description

Intel ® ICH7 Family Datasheet 559

EHCI Controller Registers (D29:F7)

13.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29:F7)

Address Offset: 70h–73h Attribute: R/W, R/WC

Default Value: 00000000h Size: 32 bits

Power Well: Suspend

NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.

Bit Description

31:30 Reserved — RO. Hardwired to 00h

29:22

SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.

0 = No Port Owner bit change.

1 = Bits 29:22 correspond to the P ort Owner bits for ports 1 (22) through 8 (29). These

bits are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to

SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.

0 = Power State bits Not modified.

1 = Software modified t he Power State bits in the Power Management Control/Status

(PMCSR) register (D29:F7:54h).

20 SMI on Async — R/WC. Software clears these bits by writing a 1 to it.

0 = No Async Schedule Enable bit change

1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.

19 SMI on Periodic — R/WC. Software clears this bit by writing a 1 it.

0 = No Periodic Schedule Enable bit change.

1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.

18 SMI on CF — R/WC. Software clears this bit by writing a 1 it.

0 = No Configure Flag (CF) change.

1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.

17 SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.

0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared).

1 = HCHalted transitio ns to 1 (as a result of the Run/St op bit being cleared).

16 SMI on HCReset — R/WC. Software clears this bit by writing a 1 it.

0 = HCRESET did Not transitioned to 1.

1 = HCRESET transitioned to 1.

15:14 Reserved — RO. Hardwired to 00h

13:6

SMI on PortOwner Enable — R/W.

0 = Disable.

1 = Enable. When any of these bits are 1 an d the corresponding SMI on PortOwner bits

are 1, then the host controller will issue an SMI. Unused ports should have their

corresponding bits cleared.

SMI on PMSCR Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue

an SMI.

SMI on Async Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue

an SMI

EHCI Controller Registers (D29:F7)

560 Intel ® ICH7 Family Datasheet

13.1.29 ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F7)

Address Offset: 80h Attribute: R/W

Default Value: 00h Size: 8 bits

SMI on Periodic Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will

issue an SMI.

SMI on CF Enable — R/W.

0 = Disable.

1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an

SMI.

SMI on HCHalted Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will

issue an SMI.

SMI on HCReset Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue

an SMI.

Bit Description

7:1 Reserved

WRT_RDONLY — R/W. When set to 1, this bit enables a sele ct group of normally read-

only registers in the EHC fu nction to be written by software. R egisters that may only be

written when this mode is entered are noted in the summary tables and detailed

description as “Read/Write-Special”. The registers fall into two categories:

1. System-configured parameters, and

2. Status bits

Intel ® ICH7 Family Datasheet 561

EHCI Controller Registers (D29:F7)

13.2 Memory-Mapped I/O Registers

The EHCI memory-mapped I/O space is composed of two sets of registers: Capability

Registers and Operational Registers.

Note: The ICH7 EHCI controller will not accept memory transactions (neither reads nor

writes) as a target that are locked transactions. The locked transactions should not be

forwarded to PCI as the address space is known to be allocated to USB.

Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory

range are ignored and result a master abort. Similarly, if the Me mory Space Enable

(MSE) bit (D29:F7:04h, bit 1) is not set in the Command register in configuration

space, the memory range will not be decoded by the ICH7 enhanced host controller

(EHC). If the MSE bit is not set, then the ICH7 must default to allowing any memory

accesses for the range specified in the BAR to go to PCI. This is because the range may

not be v alid and, therefore, th e cy cle must be made available to any other targets that

may be currently using that range.

13.2.1 Host Controller Capability Registers

These registers specify the limits, restrictions and capabilities of the host controller

implementation. Within the host controller capability registers, only the structural

parameters register is writable. These reg is t ers are i mp l em ente d in the s uspe nd well

and is only reset by the standard suspend-well hardw are reset, not by HCRESET or the

D3-to-D0 reset.

NOTE: “Read/Write Special” means that the register is normally read-only, but may be written

when the WRT_RDONLY bit is set. Because these registers are expected to be programmed

by BIOS during initializatio n, their contents must not get modified by HCRESET or D3-to-

D0 internal reset.

13.2.1.1 CAPLENGTH—Capability Registers Length Register

Offset: MEM_BASE + 00h Attribute: RO

Default Value: 20h Size: 8 bits

Table 13-2. Enhanced Host Controller Capability Registers

MEM_BAS

E + Offset Mnemonic Register Default Type

00h CAPLENGTH Capabilities Registers Length 20h RO

02h–03h HCIVERSION Host Controller Interface Version

Number 0100h RO

04h–07h HCSPARAMS Host Controller Structural Parameters 00104208h R/W

(special),

08h–0Bh HCCPARAMS Host Controller Capability Parameters 00006871h RO

Bit Description

7:0

Capability Register Length Value — RO. This register is used as an offset to add to the

Memory Base Register (D29:F7:10h) to find the beginning of the Operational Register

Space. This field is hardwired to 20h indicating that the Operation Registers begin at

offset 20h.

EHCI Controller Registers (D29:F7)

562 Intel ® ICH7 Family Datasheet

13.2.1.2 HCIVERSION—Host Controller Interface Version Number

Offset: MEM_BASE + 02h–03h Attribute: RO

Default Value: 0100h Size: 16 bits

13.2.1.3 HCSPARAMS—Host Controller Structural Parameters

Offset: MEM_BASE + 04h–07h Attribute: R/W (special), RO

Default Value: 00104208h Size: 32 bits

Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.

NOTE: This register is writable when the WRT_RDONLY bit is set.

Bit Description

15:0 Host Controller Interface V ersion Number — RO . This is a two-byte register containin g a

BCD encoding of the version number of interface that this host controller interface

conforms.

Bit Description

31:24 Reserved — RO. Default=0h.

23:20 Debug Port Number (DP_N) — RO (special). Hardwired to 1h indicating that the Debug

Port is on the lowest numbered port on the Intel® ICH7.

19:16 Reserved

15:12

Number of Companion Controllers ( N_CC) — R/W (s pecial). This field indicates the

number of companion controllers associated with this USB EHCI host controller.

A 0 in this field indicates there are no companion host controllers. Port-ownership hand-

off is not supported. Only high-speed devices are supported on the host controller root

ports.

A value of 1 or more in this field indicates there are companion USB UHCI host

controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed

devices are supported on the host controller root ports.

The ICH7 allows the default value of 4h to be over-written by BIOS. When removing

classic controllers, they should be disabled in the following order: Function 3, Function

2, Function 1, and Function 0, which correspond to ports 7:6, 5:4, 3:2, and 1:0,

respectively.

11:8 Number of Ports per Companion Controller (N_PCC) — RO. Hardwired to 2h. This field

indicates the number of ports supported per companion host controller. It is used to

indicate the port routing configuration to system software.

7:4 Reserved. These bits are reserved and default to 0.

3:0

N_PORTS — R/W (special). This field specifies the number of physical downstream

ports implemen te d on t hi s ho st controller. The value of t hi s fie ld de termines how m an y

port registers are addressable in the Oper ational Register Space. V alid values are in the

range of 1h to Fh.

The ICH7 reports 8h by default. However, software may write a value less than 8 for

some platform configurations. A 0 in this field is undefined.

Intel ® ICH7 Family Datasheet 563

EHCI Controller Registers (D29:F7)

13.2.1.4 HCCPARAMS—Host Controller Capability Parameters

Offset: MEM_BASE + 08h–0Bh Attribute: RO

Default Value: 00006871h Size: 32 bits

Bit Description

31:16 Reserved

15:8 EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h,

indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI

configuration space.

7:4

Isochronous Scheduling Threshold — RO. This field indicates, relative to the current

position of the executing host controller, where software can reliably update the

isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates

the number of micro-frames a host controller hold a set of isochronous data structures

(one or more) before flushing the state. When bit 7 is a 1, then host software assumes

the host controller may cache an isochronous data structure for an entire frame. Refer

to the EHCI specification for details on how software uses this information for

scheduling isochronous transfers.

This field is hardwired to 7h.

3 Reserved. These bits are reserved and should be set to 0.

2Asynchronous Schedule Park Capability — RO . This bit is hardwired to 0 indicating that

the host controller does not support this optional feature

Programmable Frame List Flag — RO.

0 = System software must use a frame list length of 1024 elements with this host

controller. The USB2.0_CMD register (D29:F7:CAPLENGTH + 20h, bits 3:2) Frame

List Size field is a read-only register and must be set to 0.

1 = System software can specify and use a smaller frame list and configure the host

controller via the USB2.0_CMD register Frame List Size field. The frame list must

always be aligned on a 4K page boundary. This requirement ensures that the frame

list is always physically contiguous.

64-bit Addressing Capability — RO. This field documents the addressing range

capability of this implementation. The value of this field determines whether software

should use the 32-bit or 64-bit data structures. Values for this field have the following

interpretation:

0 = Data structures using 32-bit address memory pointers

1 = Data structures using 64-bit address memory pointers

This bit is hardwired to 1.

NOTE: Intel® ICH7 only implements 44 bits of addressing. Bits 63:44 w ill always b e 0.

EHCI Controller Registers (D29:F7)

564 Intel ® ICH7 Family Datasheet

13.2.2 Host Controller Operational Registers

This section defines the enhanced host controller operational registers. These registers

are located after the capabilities registers. The operational register base must be

DWord-aligned and is calculated by adding the value in the first capabilities register

(CAPLENGTH) to the base address of the enhanced host controller register address

space (MEM_BASE). Since CAPLENGTH is always 20h, Table 13-3 already accounts for

this offset. All registers are 32 bits in length.

Note: Software must read and write these registers using only DWord accesses.These

registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are

Table 13-3. Enhanced Host Controller Operational Register Address Map

MEM_BAS

E + Offset Mnemonic Register Name Default Special

Notes Type

20h–23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO

24h–27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO

28h–2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W

2Ch–2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W,

30h–33h CTRLDSSEGM

ENT Control Data Structure

Segment 00000000h R/W, RO

34h–37h PERODICLIST

BASE Period Frame List Base

Address 00000000h R/W

38h–3Bh ASYNCLISTAD

DR Current Asynchronous List

Address 00000000h R/W

3Ch–5Fh — Reserved 0h RO

60h–63h CONFIGFLAG Configure Flag 00000000h Suspend R/W

64h–67h PORT0SC Port 0 Status and Control 00003000h Suspend R/W,

R/WC, RO

68h–6Bh PORT1SC Port 1 Status and Control 00003000h Suspend R/W,

R/WC, RO

6Ch–6Fh PORT2SC Port 2 Status and Control 00003000h Suspend R/W,

R/WC, RO

70h–73h PORT3SC Port 3 Status and Control 00003000h Suspend R/W,

R/WC, RO

74h–77h PORT4SC Port 4 Status and Control 00003000h Suspend R/W,

R/WC, RO

78h–7Bh PORT5SC Port 5 Status and Control 00003000h Suspend R/W,

R/WC, RO

7Ch–7Fh PORT6SC Port 6 Status and Control 00003000h Suspend R/W,

R/WC, RO

80h–83h PORT7SC Port 7 Status and Control 00003000h Suspend R/W,

R/WC, RO

84h–9Fh — Reserved Undefined RO

A0h–B3h — Debug Port Registers Undefined See

description

B4h–3FFh — Reserved Undefined RO

Intel ® ICH7 Family Datasheet 565

EHCI Controller Registers (D29:F7)

implemented in the core power well. Unless otherwise noted, the core well registers are

reset by the assertion of any of the following:

• Core well hardware reset

• HCRESET

• D3-to-D0 reset

The second set at offsets MEM_BASE + 60h to the end of the implemented register

space are implemented in the Suspend power well. Unless otherwise noted, the

suspend well registers are reset by the assertion of either of the following:

• Suspend well hardware reset

• HCRESET

13.2.2.1 USB2.0_CMD—USB 2.0 Command Register

Offset: MEM_BASE + 20–23h Attribute: R/W , RO

Default Value: 00080000h Size: 32 bits

Bit Description

31:24 Reserved. These bits are reserved and should be set to 0 when writing this register.

23:16

Interrupt Threshold Control — R/W. System software uses this field to select the

maximum rate at which the host controller will issue interrupts. The only valid values

are defined below. If software writes an invalid value to this register, the results are

undefined.

15:8 Reserved. These bits are reserved and should be set to 0 when writing this register.

11:8 Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host

controller does not support this optional feature.

7Light Host Controller Reset — RO . Hardwired to 0. The Intel® ICH7 does not implement

this opti onal reset.

ue Max

mum Interrupt Interva

00h Reserved

01h 1 micro-frame

02h 2 micro-frames

04h 4 micro-frames

08h 8 micro-frames (default, equates to 1 ms)

10h 16 micro-frames (2 ms)

20h 32 micro-frames (4 ms)

40h 64 micro-frames (8 ms)

EHCI Controller Registers (D29:F7)

566 Intel ® ICH7 Family Datasheet

Interrupt on Async Advance Doorbe ll — R/W. This bit is used as a doorbell by

software to tell the host controller to issue an interrupt the next time it advances

asynchronous schedule .

0 = The host cont roller sets this bit to a 0 after it has set the Interrupt o n Async

Advance status bit (D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register

to a 1.

1 = Software must write a 1 to this bit to ring the doorbell. When the host controller

has evicted all appropriate cached schedule state, it sets the Interrupt on Async

Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance

Enable bit in the USB2.0_INTR register (D29:F7:CAPLENGTH + 28h, bit 5) is a 1

then the host controller will assert an interrupt at the next interrupt threshold. See

the EHCI specification for operational details.

NOTE: Software should not write a 1 to this bit when the asynchronous schedule is

inactive. Doi n g so will yield undefined results.

Asynchronous Schedule Enable — R/W. Default 0b. This bit controls whether the

host controller skips processing the Asynchronous Schedule.

0 = Do not process the Asynchronous Schedule

1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.

Periodic Schedule Enable — R/W. Default 0b. This bit controls whether the host

controller skips processing the Periodic Schedule.

0 = Do not process the Periodic Schedule

1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.

3:2 Frame List Size — RO. The ICH7 hardwires this field to 00b because it only supports

the

1024-element frame list size.

Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset

the host controller. The effects of this on root hub registers are similar to a Chip

Hardware Reset

(i.e., RSMRST# assertion and PWROK deassertion on the ICH7).

When software writes a 1 to this bit, the host controller resets its internal pipelines ,

timers, counters, st ate machines, etc. to their i nitial v alue . Any tr ansa ction currently in

progress on USB is immediately terminated. A USB reset is not driven on downstream

ports.

NOTE: PCI configuration registers and Host controller capability registers are not

effected by this reset.

All operational registers, including port registers and port state machines are set to

their initial v alues. P ort ownership rev erts to the companion hos t controller(s ), with the

side effects described in the EHCI spec. Software must re-initialize the host controller in

order to return the host controller to an operational state.

This bit is set to 0 by the host controller when the reset process is complete. Software

cannot terminate the reset process early by writing a 0 to this register.

Software should not set this bit to a 1 when the HCHalted bit (D29:F7:CAPLENGTH +

24h, bit 12) in the U SB2. 0_STS register is a 0. A tt em pting to reset an activ e ly runn in g

host controller will result in undefined behavior. This reset me be used to leave EHCI

port test modes.

Bit Description

Intel ® ICH7 Family Datasheet 567

EHCI Controller Registers (D29:F7)

NOTE: The Command Register indicates the command to be executed by the serial bus host

controller. Writing to the register causes a command to be executed.

Run/Stop (RS) — R/W.

0 = Stop (default)

1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.

The Host con tr oller continues execution as lon g as this bit is set. When this bit is

set to 0, the Hos t controller c ompletes the curr ent tran saction on the USB and then

halts. The HCHalted bit in the USB2 .0_STS register indicates when the Host

controller has fi nished the transaction and has entered the stopped state.

Software should not write a 1 to this field unless the host controller is in the Halted

state

(i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately

when the Run bit is set.

The following table explains how the different combinations of Run and Halted should

be interpreted:

Memory read cycles initiated by the EHC that receive any status other than Successful

will result in this bit being cleared.

Bit Description

Run/Stop Halted Interpretation

0b 0b In the process of halting

0b 1b Halted

1b 0b Running

1b 1b Invalid - the HCHalted bit clears

immediately

EHCI Controller Registers (D29:F7)

568 Intel ® ICH7 Family Datasheet

13.2.2.2 USB2.0_STS—USB 2 .0 Status Register

Offset: MEM_BASE + 24h–27h Attribute: R/WC, RO

Default Value: 00001000h Size: 32 bits

This register indicates pending interrupts and various states of the Host controller. The

status resulting from a transaction on the serial bus is not indicated in this register. See

the Interrupts description in section 4 of the EHCI specification for additional

information concerning USB 2.0 interrupt conditions.

Note: For the writable bits, software must write a 1 to clear bits that are set. W riting a 0 has

no effect.

Bit Description

31:16 Reserved. These bits are reserved and should be set to 0 when writing this register.

Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the

Asynchronous Schedule.

0 = Status o f the Asynchronous Schedu le is disabled. (Default)

1 = Status of the Asynchronous Schedule is enabled.

NOTE: The Host controller is not required to immediately disable or enable the

Asynchronous Schedule when software transitions the Asynchronous Schedule

Enable bit (D29:F7:CAP LENGTH + 20h, bit 5) in the USB2.0_CMD r egister. When

this bit and the Asynchronous Schedule Enable bit are the same value, the

Asynchronous Schedule is either enabled (1) or disabled (0).

Periodic Schedule St atus ⎯ RO. This bit reports the current real status of the Periodic

Schedule.

0 = Status of the Periodic Schedule is disabled. (Default)

1 = Status of the Periodic Schedule is enabled.

NOTE: The Host controller is not required to immediately disable or enable the Periodic

Schedule when software transitions the Periodic Schedule Enable bit

(D29:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit

and the Periodic Schedule Enable bit are the same v alue, the Pe riodic Schedule is

either enabled (1) or disabled (0).

13 Reclamation ⎯ RO. 0=Default. This read-only status bit is used to detect an empty

asynchronous schedule. The operational model and valid transitions for this bit are

described in Section 4 of the EHCI Specification.

HCHalted ⎯ RO.

0 = This bit i s a 0 when the Run/Stop bit is a 1.

1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the

Run/Stop bit being set to 0, either by software or by the Host controller hardware

(e.g., internal error). (Default)

11:6 Reserved

Interrupt on Async Advance — R/WC. 0=Default. System software can force the host

controller to issue an int errup t the next time the host controller advances the

asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit

(D29:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the

assertion of that interrupt source.

Intel ® ICH7 Family Datasheet 569

EHCI Controller Registers (D29:F7)

Host System Error — R/WC.

0 = No serious error occurred during a host system access involving the Host controller

module

1 = The Host controller sets this bit to 1 when a serious error occurs during a host

system acce ss involving the Host controller module. A hardware interrupt is

generated to the system. Memory read cycles initiated by the EHC that rece ive any

status other than Successful will result in this bit being set.

When this error occurs, the Host controller clears the Run/Stop bit in the

USB2.0_CMDregister (D29:F7:CAPLENGTH + 20h, bit 0) to prevent further

execution of the scheduled TDs. A hardware interrupt is generated to the system (if

enabled in the Interrupt Enable Register).

Frame List Rollover — R/WC.

0 = No Frame List Index rollover from its maximum value to 0.

1 = The Host co ntroller sets this bit to a 1 when the Frame List Index (see Sect ion) rolls

over from its maximum value to 0. Since the Intel® ICH7 only supports the 1024-

entry Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles.

Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary

power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI

HC device, this bit is loaded with the OR of all of the PORTSC change bits (including:

Force port resume, overcurrent change, enable/disable change and connect status

change). Regardless of the implementation, when this bit is readable (i.e., in the D0

state), it must provide a valid view of the Port Status registers.

0 = No change bit transition from a 0 to 1 or No Force P ort R esume bit transition from 0

to 1 as a result of a J-K transition detected on a suspended port.

1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is

set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit

transition from 0 to 1 as a result of a J-K transition detected on a suspended port.

USB Error Interrupt (USBERRINT) — R/WC.

0 = No error condition.

1 = The Host controller sets this bit to 1 when completion of a USB transaction results in

an error condition (e.g., error counter underflow). If the TD on which the error

interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the

EHCI specification for a list of the USB errors that will result in this interrupt being

asserted.

USB Interrupt (USBINT) — R/WC.

0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set.

No short packet is dete cted.

1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion

of a USB transaction whose Transfer Descriptor had its IOC bit set.

The Host controller also sets this bit to 1 when a short packet is detected (actual

number of bytes received was less than the expected number of bytes).

Bit Description

EHCI Controller Registers (D29:F7)

570 Intel ® ICH7 Family Datasheet

13.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register

Offset: MEM_BASE + 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register enables and disables reporting of the corresponding interrupt to the

software. When a bit is set and the corresponding interrupt is active, an interrupt is

generated to the host. Interrupt sources that are disabled in this register still appear in

the USB2.0_STS Register to allow the softw are to poll for events. Each interrupt enable

bit description indicates whether it is dependent on the interrupt threshold mechanism

(see Section 4 of the EHCI specification), or not.

Bit Description

31:6 Reserved. These bits are reserved and should be 0 when writing this register.

Interrupt on Async Advance Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit

(D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt at the next interrupt threshold. The interrupt is

acknowledged by software clearing the Interru pt on Async Advance bit.

Host System Error Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Host System Error Status bit

(D29:F7:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host

controller will issue an interrupt. The interrupt is acknowledged by software

clearing the Host System Error bit.

Frame List Rollover Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the Frame Lis t Rollo ver bit (D29:F7 :CAPLENGTH +

24h, bit 3) in the USB2.0_STS register is a 1, the host controller will issue an

interrupt. The interrupt is acknowledged by software clearing the Frame List

Rollover bit .

Port Change Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the P ort Change Detect bit (D29:F7:CAPLENGTH +

24h, bit 2) in the USB2.0_STS register is a 1, the host controller will issue an

interrupt. The interrupt is acknowledged by software clearing the Port Change

Detect bit.

USB Error Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F7:CAPLENGTH + 24h,

bit 1) in the USB2.0_STS register is a 1, the host controller will issue an interrupt

at the next interrupt threshold. The interrupt is acknowledged by software by

clearing the USBERRINT bit in the USB2.0_STS register.

USB Interrupt Enable — R/W.

0 = Disable.

1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7:CAPLENGTH + 24h, bit 0)

in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the

next interrupt threshold. The interrupt is acknowledged by software by clear ing the

USBINT bit in the USB2.0_STS register.

Intel ® ICH7 Family Datasheet 571

EHCI Controller Registers (D29:F7)

13.2.2.4 FRINDEX—Frame Index Reg ister

Offset: MEM_BASE + 2Ch–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

The SOF frame number v alue for the bus SOF token is derived or alternatively managed

from this register. Refer to Section 4 of the EHCI specification for a detailed explanation

of the SOF value management requirements on the host controller. The value of

FRINDEX must be within 125 µs

(1 micro-frame) ahead of the SOF tok en value. The SOF value may be implemented as

an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is

named SOFV. SOFV updates every 8 micro-frames. (1 millisecond). An example

implementation to achieve this behavior is to increment SOFV each time the

FRINDEX[2:0] increments from 0 to 1.

Software must use the value of FRINDEX to derive the current micro-frame number,

both for

high-speed isochronous scheduling purposes and to provide the get micro-frame

number function required to client drivers. Therefore, the value of FRINDEX and the

value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX.

Writes to FRINDEX must also

write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple

as possible, software should not write a FRINDEX value where the three least

significant bits are 111b or 000b.

Note: This register is used by the host controller to index into the periodic frame list. The

used to select a particular entry in the Periodic Frame List during periodic schedule

execution. The number of bits used for the inde x is fixed at 10 for the ICH7 since it only

supports 1024-entry frame lists. This register must be written as a DWord. Word and

byte writes produce undefined results. This register cannot be written unless the Host

controller is in the Halted state as indicated by the HCHalted bit (D29:F7:CAPLENGTH +

24h, bit 12). A write to this register while the Run/Stop bit (D29:F7:CAPLENGTH + 20h,

bit 0) is set to a 1 (USB2.0_CMD register) produces undefined results. Writes to this

Bit Description

31:14 Reserved

13:0

Frame List Current Index/Frame Number — R/W. The value in this register

increments at the end of each time frame (e.g., micro-frame).

Bits [12:3] are used for the Frame List current index. This means that each location of

the frame list is access ed 8 times (frames or micro-frames) before moving to the next

index.

EHCI Controller Registers (D29:F7)

572 Intel ® ICH7 Family Datasheet

13.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

Offset: MEM_BASE + 30h–33h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

This 32-bit register corresponds to the most significant address bits [63:32] for all

EHCI data structures. Since the ICH7 hardwires the 64-bit Addressing Capability field in

HCCPARAMS to 1, then this register is used with the link pointers to construct 64-bit

addresses to EHCI control data structures. This register is concatenated with the link

pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data

structure link field to construct a 64-bit address. This register allows the host software

to locate all control data structures within the same 4 GB memory segment.

13.2.2.6 PERIODICLISTBASE—Periodi c Frame List Base Address

Offset: MEM_BASE + 34h–37h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This 32-bit register contains the beginning address of the Periodic Frame List in the

system memory. Since the ICH7 host controller operates in 64-bit mode (as indicated

by the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset

08h, bit 0), then the most significant 32 bits of every control data structure address

comes from the CTRLDSSEGMENT register. HCD loads this register prior to starting the

schedule execution by the host controller. The memory structure referenced by this

physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this

controller to step through the Periodic Frame List in sequence.

Bit Description

31:12 Upper Address[63:44] — RO. Hardwired to 0s. The Intel® ICH7 EHC is only capable of

generating addresses up to 16 terabytes (44 bits of address).

11:0 Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when

forming a control data structure address.

Bit Description

31:12 Base Address (Low) — R/W. These bits correspond to memory address signals

[31:12], respectively.

11:0 Reserved. Must be written as 0s. During runtime, the value of these bits are undefined.

Intel ® ICH7 Family Datasheet 573

EHCI Controller Registers (D29:F7)

13.2.2.7 ASYNCLISTADDR —Current Asynchronous List Address

Offset: MEM_BASE + 38h–3Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

This 32-bit register contains the address of the next asynchronous queue head to be

executed. Since the ICH7 host controller operates in 64-bit mode (as indicated by a 1 in

64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then

the most significant 32 bits of every control data structure address comes from the

CTRLDSSEGMENT register (offset 08h). Bits [4:0 ] of this register cannot be modified by

system software and will always return 0’ s when read. The memory structure

referenc ed by this physical memory pointer is assumed to be 32-byte aligned.

13.2.2.8 CONFIGFLAG—Configure Flag Register

Offset: MEM_BASE + 60h–63h Attribute: R/W

Default Value: 00000000h Size: 32 bits

This register is in the suspend power well. It is only reset by hardware when the

suspend power is initially applied or in response to a host controller reset.

13.2.2.9 PORTSC—Port N Status and Control Register

Offset: Port 0: MEM_BASE + 64h–67h

Port 1: MEM_BASE + 68–6Bh

Port 2: MEM_BASE + 6C–6Fh

Port 3: MEM_BASE + 70–73h

Port 4: MEM_BASE + 74–77h

Port 5: MEM_BASE + 78–7Bh

Port 6: MEM_BASE + 7C–7Fh

Port 7: MEM_BASE + 80–83h

Attribute: R/W, R/WC, RO

Default Value: 00003000h Size: 32 bits

A host controller must implement one or more port registers. Software uses the N_P ort

information from the Structural Par am eters Register to determine how many ports

need to be serviced. All ports have the structure defined below. Software must not

write to unreported Port Status and Control Registers.

Bit Description

31:5 Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals

[31:5], respectively. This field may only reference a Queue Head (QH).

4:0 Reserved. These bits are reserved and their value has no effect on operation.

Bit Description

31:1 Reserved. Read from this field will always return 0.

Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process

of configuring the Host controller. This bit controls the default port -routing control logic.

Bit values and side-effects are listed below. See section 4 of the EHCI spec for

operation d e tails.

0 = Port routing control logic default-routes each port to the classic host controllers

(default).

1 = Port routing control logic default-routes all ports to this host controller.

EHCI Controller Registers (D29:F7)

574 Intel ® ICH7 Family Datasheet

This register is in the suspend power well. It is only reset by hardware when the

suspend power is initially applied or in response to a host controller reset. The initial

conditions of a port are:

• No device connected

• Port disabled.

When a device is attached, the port state transitions to the attached state and system

software will process this as with any status change notification. Refer to Section 4 of

the EHCI specification for operational requirements for how change events interact with

port suspend mode.

Bit Description

31:23 Reserved. These bits are reserved for future use and will return a value of 0’s when

read.

Wake on Overcurrent Enable (WKOC_E) — R/W.

0 = Disable. (Default)

1 = Enable. W riting this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the overcurrent

Active bit (bit 4 of this register) is set.

Wake on Disconnect Enable (WKDSCNNT_E) — R/W.

0 = Disable. (Default)

1 = Enable. W riting this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the Current Connect

Status changes from connected to discon ne ct ed (i.e., bit 0 of this regi st er ch ange s

from 1 to 0).

Wake on Connect Enable (WKCNNT_E) — R/W.

0 = Disable. (Default)

1 = Enable. W riting this bit to a 1 enables the setting of the PME Status bit in the Power

Management Control/Status Register (offset 54, bit 15) when the Current Connect

Status changes from di sc onn ect ed to connected (i.e., bit 0 of this register changes

from 0 to 1).

19:16

Port Test Control — R/W. When this field is 0’s, the port is NOT operating in a test

mode. A non-zero value indicates that it is operating in test mode and the specific test

mode is indicated by the specific value. The encoding of the test mode bits are (0110b

– 1111b are reserved):

Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode.

15:14 Reserved — R/W. Should be written to =00b.

Port Owner — R/W. Default = 1b. This bit unconditionally goes to a 0 when the

Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition.

System software uses this field to release ownership of the port to a selected host

controller (in the event that the attached device is not a high-speed device). Software

writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit

means that a companion host controller owns and controls the port. See Section 4 of

the EHCI Specification for operational details.

Value Maximum Interrupt Interval

0000b Test mode not enabled (default)

0001b Test J_STATE

0010b Test K_STATE

0011b Test SE0_NAK

0100b Test Packet

0101b FORCE_ENABLE

Intel ® ICH7 Family Datasheet 575

EHCI Controller Registers (D29:F7)

12 Port Power (PP) — RO . R e ad-on ly with a v al ue of 1. This in dicate s that the port does

have power.

11:10

Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D–

(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to

the port reset and enable sequence. This field is valid only when the port enable bit is 0

and the current connect status bit is set to a 1.

00 = SE0

10 = J-state

01 = K-state

11 = Undefined

9 Reserved. This bit will return a 0 when read.

Port Reset — R/W. Default = 0. When software writes a 1 to this bit (fro m a 0), the

bus reset sequence as defined in the USB Specification, Revision 2.0 is started.

Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep

this bit at a 1 long enough to ensure the reset sequence completes as specified in the

USB Specification, Revision 2.0.

1 = Port is in Reset.

0 = Port is not in Reset.

NOTE: When software writes a 0 to this bit, there may be a delay before the bit status

changes to a 0. The bit s tatus will not read as a 0 until after the reset has

completed. If the port is in high-speed mode after reset is complete, the host

controller will automatically enable this port (e.g., set the Port Enable bit to a

1). A host controller must terminate the reset and stabilize the state of the port

within 2 milliseconds of software transitioning this bit from 0 to 1.

For example: if the port detects that the attached device is high-s peed during

reset, then the host controller must have the port in the enabled state within

2 ms of software writing this bit to a 0. The HCHalted bit (D29:F7:CAPLENGTH

+ 24h, bit 12) in the USB2.0_STS register should be a 0 before software

attempts to use this bit. The host controller may hold Port Reset asserted to a 1

when the HCHalted bit is a 1. This bit is 0 if Port Power is 0

NOTE: System software should not attempt to reset a port if the HCHalted bit in the

USB2.0_STS register is a 1. Doing so will result in undefined behavior.

Suspend — R/W.

0 = Port not in suspend state.(Default)

1 = Port in suspend state.

Port Enabled Bit and Suspend bit of this register define the port states as follows:

When in suspend state, downs tream propagation of data is blocked on this port, except

for port reset. Note that the bit status does not change until the port is suspended and

that there may be a delay in suspending a port depending on the activity on the port.

The host controller will unc onditionally set this bit to a 0 when software sets the Force

Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host

controller.

If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is

a 0) the results are undefined.

Bit Description

Port Enabled Suspend Port State

0XDisabled

10Enabled

11Suspend

EHCI Controller Registers (D29:F7)

576 Intel ® ICH7 Family Datasheet

Force Port Resume — R/W.

0 = No resume (K-state) detected/driven on port. (Default)

1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume

signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected

while the port is in the Suspend state. When this bit transitions to a 1 because a J-

to-K tr ansition is det ected, the P ort Change D etect bit (D29:F 7:CAPLENGTH + 24h,

bit 2) in the USB2.0_STS register is also set to a 1. If software sets this bit to a 1,

the host controller must not set the Port Change Detect bit.

NOTE: When the EHCI controller owns the port, the resume sequence follows the

defined sequence documented in the USB Specification, Revision 2.0. The

resume signaling (Full-spee d 'K') is driven on the port as long as this bit

remains a 1. Software must appropriately time the Resume and set this bit to a

0 when the appropriate amount of tim e has elapsed. Writing a 0 (from 1)

causes the port to return to high-speed mode (forcing the bus below the port

into a high-spee d idle). This bit will remain a 1 until the port has switched to the

high-speed idle.

Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the

port owner. Software clears this bit by writing a 1 to it.

0 = No change. (Default)

1 = There is a change to Overcurrent Active.

Overcurrent Active — RO.

0 = This port does not have an overcurrent co ndition. (Default)

1 = This port currently has an overcurrent condition. This bit will automatically

transi tion from 1 to 0 when the over current condition is removed. The Intel® ICH7

automatically disables the port when the overcurrent active bit is 1.

Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only

when a port is disabled due to the appropriate conditions exist ing at the EOF2 point

(See Chapter 11 of the USB Specification for the definition of a port error). This bit is

not set due to the Disabled-to-Enabled transition, nor due to a disconnect. Software

clears this bit by writing a 1 to it.

0 = No change in status. (Default).

1 = Port enabled/disabled status has changed.

Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a

part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.

Ports can be disabled by either a fault condition (disconnect event or other fault

condition) or by host software. Note that the bit status does not change until the port

state actually changes. There may be a delay in disabling or enabling a port due to

other host controller and bus events.

0 = Disable

1 = Enable (Default)

Connect Status Change — R/WC. This bit indicates a change has occurred in the

port’s Current Connect Status. Software sets this bit to 0 by writing a 1 to it.

0 = No change (Default).

1 = Change in Current Connect Status. The host controller sets this bit for all changes

to the port device connect status, even if system software has not cleared an

existing connect status change. For example, the insertion status ch anges twice

before system software has cleared the changed condition, hub hardware will be

“setting” an already-set bit (i.e., the bit will remain set).

Current Connect Status — RO. This value reflects the current state of the port, and

may not correspond directly to the event that caused the Connect Status Change bit

(Bit 1) to be set.

0 = No devic e is present. (Default)

1 = Device is present on port.

Bit Description

Intel ® ICH7 Family Datasheet 577

EHCI Controller Registers (D29:F7)

13.2.3 USB 2.0-Based De bug Port Register

The Debug port’s registers are located in the same memory area, defined by the Base

Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the

debug port registers (A0h) is declared in the Debug P ort Base Offset Capability Register

at Configuration offset 5Ah (D29:F7:offset 5Ah). The specific EHCI port that supports

this debug capability (port 0) is indicated by a 4-bit field (bits 20–23) in the

HCSPARAMS register of the EHCI controller. The address map of the Debug Port

registers is shown in Table 13-4.

NOTES:

1. All of these re gisters are implemented in the core well and reset by PLTRST#, EHC

HCRESET, and a EHC D3-to-D0 transition.

2. The hardware associated with this register provides no checks to ensure that software

programs the interface correctly. How the hardware behaves when programmed

inappropriately is undefined.

13.2.3.1 CNTL_STS—Control/Status Register

Offset: MEM_BASE + A0h Attribute: R/W, R/WC, RO, WO

Default Value: 0000h Size: 32 bits

Table 13-4. Debug Port Register Address Map

MEM_BASE +

Offset Mnemonic Register Name Default Type

A0–A3h CNTL_STS Control/Status 00000000h R/W, R/WC, RO ,

A4–A7h USBPID USB PIDs 00000000h R/W, RO

A8–ABh DATABUF[3:0] Data Buffer (Bytes 3:0) 00000000h R/W

AC–AFh DATABUF[7:4] Data Buffer (Bytes 7:4) 00000000h R/W

B0–B3h CONFIG Configuration 00007F01h R/W

Bit Description

31 Reserved

OWNER_CNT — R/W.

0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)

1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately

taken away from the companion Classic USB Host controller) If the port was

already owned by the EHCI controller, then setting this bit has no effect. This bit

overrides all of the ownership-related bits in the standard EHCI registers.

29 Reserved

ENABLED_CNT — R/W.

0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the

same conditions where the Port Enable/Disable Change bit (in the PORTSC

1 = Debug port is enabled for operation. Softwa re can directly set this bit if the port is

already enabled in the associated PORTSC register (this is enforced by the

hardware).

27:17 Reserved

EHCI Controller Registers (D29:F7)

578 Intel ® ICH7 Family Datasheet

16 DONE_STS — R/WC. Software can clear this by writing a 1 to it.

0 = Request Not complete

1 = Set by hardware to indicate that the request is complete .

15:12 LINK_ID_STS — RO. This field ident ifies the link interface.

0h = Hardwired. Indicates that it is a USB Debug Port.

11 Reserved. This bit returns 0 when read. Writes have no effect.

10 IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by

software to indi cate that the port is free and may be used by other softw are. This bit is

cleared after reset. (This bit has no effect on hardware.)

9:7

EXCEPTION_STS — RO. This field indicates the exception when the

ERROR_GOOD#_STS bit is set. This field should be ignored if the

ERROR_GOOD#_STS bit is 0.

000 =No Error. (Default)

Note: this shoul d not be se en , sin ce th is f ie ld shou ld on ly be chec ked if there is

an error.

001 =Transaction error: indicates the USB 2.0 transaction had an error (CRC, bad

PID, timeout, etc.)

010 =Hardware error. Request was attempted (or in progress) when port was

suspended or reset.

All Other combinations are reserved

ERROR_GOOD#_STS — RO.

0 = Hardware clears this bit to 0 after the proper completion of a read or write.

(Default)

1 = Error has occurred. Details on the nature of the error are provided in the

Exception field.

GO_CNT — WO.

0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)

1 = Causes hardware to perform a read or write request.

NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior.

WRITE_READ#_CNT — R/W. Software clears this bit to indicate that the current

request is a read. Software sets th is bit to indicate that t he c urr en t re qu es t i s a wri te .

0 = Read (Default)

1 = Write

Bit Description

Intel ® ICH7 Family Datasheet 579

EHCI Controller Registers (D29:F7)

16 DONE_STS — R/WC. Software can clear this by writing a 1 to it.

0 = Request Not complete

1 = Set by hardware to indicate that the request is complete .

15:12 LINK_ID_STS — RO. This field ident ifies the link interface.

0h = Hardwired. Indicates that it is a USB Debug Port.

11 Reserved. This bit returns 0 when read. Writes have no effect.

10 IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by

software to indi cate that the port is free and may be used by other softw are. This bit is

cleared after reset. (This bit has no effect on hardware.)

9:7

EXCEPTION_STS — RO. This field indicates the exception when the

ERROR_GOOD#_STS bit is set. This field should be ignored if the

ERROR_GOOD#_STS bit is 0.

000 =No Error. (Default)

Note: this shoul d not be se en , sin ce th is f ie ld shou ld on ly be chec ked if there is

an error.

001 =Transaction error: indicates the USB 2.0 transaction had an error (CRC, bad

PID, timeout, etc.)

010 =Hardware error. Request was attempted (or in progress) when port was

suspended or reset.

All Other combinations are reserved

ERROR_GOOD#_STS — RO.

0 = Hardware clears this bit to 0 after the proper completion of a read or write.

(Default)

1 = Error has occurred. Details on the nature of the error are provided in the

Exception field.

GO_CNT — WO.

0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)

1 = Causes hardware to perform a read or write request.

NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior.

WRITE_READ#_CNT — R/W. Software clears this bit to indicate that the current

request is a read. Software sets th is bit to indicate that t he c urr en t re qu es t i s a wri te .

0 = Read (Default)

1 = Write

Bit Description

EHCI Controller Registers (D29:F7)

580 Intel ® ICH7 Family Datasheet

NOTES:

1. Software should do Read-Modify- Write operations to this register to preserve the contents

of bits not being modified. This include Reserved bits.

2. To preserve th e usage of RESERVED bits in the future, software should always write the

same value read from the bit until it is defined. Reserved bits will always return 0 when

read.

13.2.3.2 USBPID—USB PIDs Register

Offset: MEM_BASE + A4h Attribute: R/W, RO

Default Value: 0000h Size: 32 bits

This DWord regist er is used to communicate PID information between the USB debug

driver and the USB debug port. The debug port uses some of these fields to generate

USB packets, and uses other fields to return PID information to the USB debug driver.

3:0

DATA_LEN_CNT — R/W. This field is used to indicate the size of the data to be

transferred.

default = 0h.

Fo r write operat ions, this fiel d is set by soft ware to indicate to the hardware how many

bytes of data in Data Buffer are to be transferred to the console. A value of 0h

indicates that a zero-length packet should be se nt. A value of 1–8 indic ates 1 –8 bytes

are to be transferred. Values 9–Fh are invalid and how hardware behaves if used is

undefined.

For read operations, this field is set by hardware to indicate to software how many

bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates

that a zero length packet was returned and the state of Data Buffer is not defined. A

value of 1–8 indicates 1–8 bytes were received. Hardware is not allowed to return

values 9–Fh.

The transferring of data always starts with byte 0 in the data area and moves toward

byte 7 until the transfer size is reached.

Bit Description

31:24 Reserved: These bits will return 0 when read. Writes will have no effect.

23:16

RECEIVED_PID_STS[23:16] — RO. Hardware updates this field with the received

PID for transactions in either direction. When the controller is writing data, this field is

updated with the handshake PID that is received from the device. When the host

controller is reading data, this field is updated with the data packet PID (if the device

sent data), or the h andshake PID (if the device NAKs the request). This field is valid

when the hardware clears the GO_DONE#_CNT bit.

15:8 SEND_PID_CNT[15:8] — R/W. Hardware sends this PID to begin the data packet

when sending data to USB (i.e., WRITE_READ#_CNT is asserted). Software typically

sets this field to either DATA0 or DATA1 PID values.

7:0 TOKEN_PID_CNT[7:0] — R/W. Hardware sends this PID as the Token PID for each

USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID

values.

Intel ® ICH7 Family Datasheet 581

EHCI Controller Registers (D29:F7)

13.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register

Offset: MEM_BASE + A8h–AFh Attribute: R/W

Default Value: 0000000000000000h Size: 64 bits

This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.

13.2.3.4 CONFIG—Configuration Register

Offset: MEM_BASE + B0–B3h Attribute: R/W

Default Value: 00007F01h Size: 32 bits

Bit Description

63:0

DATABUFFER[63:0] — R/W. This field is the 8 bytes of the data buffer. Bits 7:0

correspond to least significant byte (byte 0). Bits 63:56 correspond to the most

significant byte (byte 7).

The bytes in the Data Buffer must be written with data before software initiates a write

request. For a read request, the Data Buffer contains valid data when DONE_STS bit

(offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6)

is cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0)

indicates the number of bytes that are valid.

Bit Description

31:15 Reserved

14:8 USB_ADDRESS_CNF — R/W. This 7-bit field iden tifies the USB device addres s used

by the controller for all Token PID generation. (Default = 7Fh)

7:4 Reserved

3:0 USB_ENDPOINT_CNF — R/W. This 4-bit field identifies the endpoint used by the

controller for all Token PID generation. (Default = 01h)

EHCI Controller Registers (D29:F7)

582 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 583

SMBus Controller Registers (D31:F3)

14 SMBus Controller Registers

(D31:F3)

14.1 PCI Configuration Registers (SMBUS—D31:F3)

NOTE: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

14.1.1 VID—Vendor Identification Register (SMBUS—D31:F3)

Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

Table 14-1. SMBus Controller PCI Register Address Map (SMBUS—D31:F3)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086 RO

02h–03h DID Device Identification See

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0280h RO, R/WC

08h RID Revision Identif ication See

description. RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 05h RO

0Bh BCC Base Class Code 0Ch RO

20h–23h SMB_BASE SMBus Base Address 00000001h R/W, RO

2Ch–2Dh SVID Subsystem Vendor Identification 00h RO

2Eh–2Fh SID Subsystem Identification 00h R/WO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See

description RO

40h HOSTC Host Configuration 00h R/W

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel

SMBus Controller Registers (D31:F3)

584 Intel ® ICH7 Family Datasheet

14.1.2 DID—Device Identification Register (SMBUS—D31:F3)

Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

14.1.3 PCICMD—PCI Command Register (SMBUS—D31:F3)

Address: 04h–05h Attributes: RO, R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 SMBus controller.

Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specificat ion Update for the

value of the Device ID Register.

Bit Description

15:11 Reserved

10 Interrupt Disable — R/W.

0 = Enable

1 = Disables SMBus to assert its PIRQB# signal.

9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W.

0 = Enables SERR# generation.

1 = Disables SERR# generation.

7 Wait Cycle Control (WCC) — RO. Hardwired to 0.

6Parity Error Response (PER) — R/W.

0 = Disable

1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.

5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.

4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Hardwired to 0.

2 Bus Master En able (BME) — RO. Hardwired to 0.

1 Memory Space Enable (MSE) — RO. Hardwired to 0.

I/O Space Enable (IOSE) — R/W.

0 = Disable

1 = Enables access to the SM Bus I/O space registers as defined by the Base Address

Intel ® ICH7 Family Datasheet 585

SMBus Controller Registers (D31:F3)

14.1.4 PCISTS—PCI Status Register (SMBUS—D31:F3)

Address: 06h–07h Attributes: RO, R/WC

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

14.1.5 RID—Revision Identification Register (SMBUS—D31:F3)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Parity error detected.

14 Signaled System Error (SSE) — R/WC.

0 = No system error detected.

1 = System er ror detected.

13 Received Master Abort (RMA) — RO. Hardwired to 0.

12 Received Target Abort (RTA) — RO. Hardwired to 0.

Signaled Target Abort (STA) — R/WC.

0 = Intel® ICH7 did Not terminate transaction for this function with a target abort.

1 = The function is targeted with a transaction that the ICH7 terminates with a target

abort.

10:9 DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL#

assertion for positive decode.

01 = Medium timing.

8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.

7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.

6 User Definable Features (UDF) — RO. Hardwired to 0.

5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list

structures in this function

3Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is

independent from the state of the Interrupt Enable bit in the PCI Command register.

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

SMBus Controller Registers (D31:F3)

586 Intel ® ICH7 Family Datasheet

14.1.6 PI—Programming Interface Register (SMBUS—D31:F3)

Offset Address: 09h Attribute: RO

Default Value: 00h Size: 8 bits

14.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)

Address Offset: 0Ah Attributes: RO

Default Value: 05h Size: 8 bits

14.1.8 BCC—Base Class Code Register (SMBUS—D31:F3)

Address Offset: 0Bh Attributes: RO

Default Value: 0Ch Size: 8 bits

14.1.9 SMB_BASE—SMBUS Base Address Register

(SMBUS—D31:F3)

Address Offset: 20–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32-bits

Bit Description

7:0 Reserved

Bit Description

7:0 Sub Class Code (SCC) — RO.

05h = SM Bus serial controller

Bit Description

7:0 Base Class Code (BCC) — RO.

0Ch = Serial controller.

Bit Description

31:16 Reserved — RO

15:5 Base Address — R/W. This field provides the 32-byte system I/O base address for the

Intel® ICH7 SMB logic.

4:1 Reserved — RO

0 IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.

Intel ® ICH7 Family Datasheet 587

SMBus Controller Registers (D31:F3)

14.1.10 SVID — Subsystem Vendor Identification Register

(SMBUS—D31:F2/F4)

Address Offset: 2Ch–2Dh Attribute: RO

Default Value: 0000h Size: 16 bits

Lockable: No P ower Well: Core

14.1.11 SID — Subsystem Identification Register

(SMBUS—D31:F2/F4)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 00h Size: 16 bits

Lockable: No P ower Well: Core

14.1.12 INT_LN—Interrupt Line Register (SMBUS—D31:F3)

Address Offset: 3Ch Attributes: R/W

Default Value: 00h Size: 8 bits

14.1.13 INT_PN—Interrupt Pin Register (SMBUS—D31:F3)

Address Offset: 3Dh Attributes: RO

Default Value: See description Size: 8 bits

Bit Description

15:0

Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the

Subsystem ID (SID) register, enables the operating system (OS) to dist inguish

subsystems from each other. The value returned by reads to this register is the same as

that which was written by BIOS into the IDE SVID register.

NOTE: Software can write to this register only once per core well reset. Writes should

be done as a single 16-bit cycle.

Bit Description

15:0

Subsystem ID (SID) — RO. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. The

value returned by reads to this register is the same as that which was written by BIOS

into the IDE SID register.

NOTE: Software can write to this register only once per core well reset. Writes should

be done as a single 16-bit cycle.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH7. It is to

communicate to software the interrupt line that the interrupt pin is connect ed to

PIRQB#.

Bit Description

7:0 Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset

configuration space.

SMBus Controller Registers (D31:F3)

588 Intel ® ICH7 Family Datasheet

14.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3)

Address Offset: 40h Attribute: R/W

Default Value: 00h Size: 8 bits

14.2 SMBus I/O Registers

Bit Description

7:3 Reserved

I2C_EN — R/W.

0 = SMBus behavior.

1 = The Intel® ICH7 is enabled to communicate with I2C devices. This will change the

formatting of some commands.

SMB_SMI_EN — R/W.

0 = SMBus interrupts will not generate an SMI#.

1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer

to Section 5.21.4 (Interrupts / SMI#). This bit needs to be set for SMBALERT# to

be enabled.

SMBus Host Enable (HST_EN) — R/W.

0 = Disable the SMBus Host controller.

1 = Enable. The SMB Host controller interface is enabled to execute commands. The

INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host

controller to interrupt or SMI#. Note that the SMB Host controller will not respond

to any new requests until all interrupt requests have been cleared.

Table 14-2. SMBus I/O Register Address Map

SMB_BASE

+ Offset Mnemonic Register Name Default Type

00h HST_STS Host Status 00h R/WC, RO,

R/WC

(special)

02h HST_CNT Host Control 00h R/W, WO

03h HST_CMD Host Command 00h R/W

04h XMIT_SLVA Transmit Slave Address 00h R/W

05h HST_D0 Host Data 0 00h R/W

06h HST_D1 Host Data 1 00h R/W

07h HOST_BLOCK_DB Host Block Data Byte 00h R/W

08h PEC Packet Error Check 00h R/W

09h RCV_SLVA Receive Slave Address 44h R/W

0Ah–0Bh SLV_DATA Receive Slave Data 0000h RO

0Ch AUX_STS Auxiliary Status 00h R/WC, RO

0Dh AUX_CTL Auxiliary Control 00h R/W

0Eh SMLINK_PIN_CTL SMLink Pin Co ntrol (T CO

Compatible Mode)

See

description R/W, RO

Intel ® ICH7 Family Datasheet 589

SMBus Controller Registers (D31:F3)

14.2.1 HST_STS—Host Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8-bits

All status bits are set by hardware and cleared by the software writing a one to the

particular bit position. Writing a 0 to any bit position has no effect.

0Fh SMBUS_PIN_CTL SMBus Pin Control See

description R/W, RO

10h SLV_STS Slave Status 00h R/WC

11h SLV_CMD Slave Command 00h R/W

14h NOTIFY_DADDR Notify Device Address 00h RO

16h NOTIFY_DLOW Notify Data Low Byte 00h RO

17h NOTIFY_DHIGH Notify Data High Byte 00h RO

Table 14-2. SMBus I/O Register Address Map

SMB_BASE

+ Offset Mnemonic Register Name Default Type

Bit Description

Byte Done Status (DS) — R/WC.

0 = Software can clear this by writing a 1 to it.

1 = Host controller received a byte (for Block Read commands) or if it has completed

transmission of a byte (for Block Write commands) when the 32-byte buffer is not

being used. Note that this bit will be se t, ev en on the la st byte of the tr ans fer. This

bit is not set when transmiss ion is due to the LAN int erface heartbeat.

This bit has no meaning for block transfers when the 32-byte buffer is enabled.

NOTE: When the last byte of a block message is received, the host controller will set

this bit. However, it will not immediately set the INTR bit (bit 1 in this register).

When the interrupt handler clears the DS bit, the message is considered

complete, and the host controller will then set the INTR bit (and generate

another interrupt). Thus, for a block message of n bytes, the Intel® ICH7 will

generate n+1 interrupts. The interrupt handler needs to be implemented to

handle these cases.

INUSE_STS — R/WC (special). This bit is used as semaphore among various

independent software threads that may need to use th e ICH7’s SM Bus logic, and has no

other effect on hardware.

0 = After a full PCI reset, a read to this bit returns a 0.

1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will

reset the next read value to 0. Writing a 0 to this bit has no effect. Software can

poll this bit until it reads a 0, and will then own the usage of the host controller.

SMBALERT_STS — R/WC.

0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by

writing a 1 to it.

1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only

cleared by software writing a 1 to the bit position or by RSMRST# going low.

If the signal is programmed as a GPIO, then this bit will not be set.

SMBus Controller Registers (D31:F3)

590 Intel ® ICH7 Family Datasheet

FAILED — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in

response to the KILL bit being set to terminate the host transaction.

3BUS_ERR — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = The source of the interrupt of SMI# was a transaction collision.

DEV_ERR — R/WC.

0 = Software cl ears this bit by writing a 1 to it. The ICH7 will then deassert the

interrupt or SMI#.

1 = The source of the interrupt or SMI# was due to one of the following:

• Invalid Command Field,

• Unclaimed Cycle (host initiated),

• Host Device Time-out Error.

INTR — R/WC (special). This bit can only be set by termination of a command. INTR is

not dependent on the INTREN bit (offset SMBASE + 02h, bit 0) of the Host controller

INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be

generated. Software can poll the INTR bit in this non-interrupt case.

0 = Software cl ears this bit by writing a 1 t o it. The ICH7 then deass erts the interrupt

or SMI# .

1 = The source of the interrupt or SMI# was the succe ssful completion of its last

command.

HOST_BUSY — RO.

0 = Cleared by the ICH7 when the curre nt transaction is completed.

1 = Indicates that the ICH7 is running a command from the host interface. No SMB

registers should be accessed while this bit is set, except the BLOCK DATA BYTE

when the SMB_CMD bits in the Host Control Register are programmed for Block

command or I2C Read command. This is necessary in order to check the

DONE_STS bit.

Bit Description

Intel ® ICH7 Family Datasheet 591

SMBus Controller Registers (D31:F3)

14.2.2 HST_CNT—Host Control Register (SMBUS—D31:F3)

Default Value: 00h Size: 8-bits

Note: A read to this register will clear the byte pointer of the 32-byte buffer.

Bit Description

PEC_EN — R/W.

0 = SMBus host controller does not perform the transaction with the PEC phase

appended.

1 = Causes the host controller to perform the SMBus transaction with the Packet Error

Checking phase appended. For writes, the value of the PEC byte is transferred from

the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. Th is bit

must be written prior to the write in which the START bit is set.

START — WO.

0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status

command.

1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All

registers should be setup prior to writing a 1 to this bit position.

LAST_BYTE — WO. This bit is used for Block Read commands.

1 = Software sets this bit to indicate that the next byte will be the last byte to be

received for the block. This causes the ICH7 to send a NACK (instead of an ACK)

after receiving the last byte.

NOTE: Once the SECOND_TO_STS bit in TCO2_STS regist er (D3 1:F 0, TCOBASE+6h,

bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is

set, the LAST_BYTE bit c annot be c leare d. This pre ven ts the ICH7 from ru nning

some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write).

SMBus Controller Registers (D31:F3)

592 Intel ® ICH7 Family Datasheet

4:2

SMB_CMD — R/W. The bit encoding below indicates which command the ICH7 is to

perform. If enabled, the ICH7 will generate an interrupt or SMI# when the command

has completed If the value is for a non-supported or reserved command, the ICH7 will

set the device error (DEV_ERR) status bit (offset SMBASE + 00h, bit 2) and generate

an interrupt when the ST ART bit is set. The ICH7 will perform no command, and will not

operate until DEV_ERR is cleared.

000 = Quick: The slave address and read/write value (bit 0) are stored in the

transmit slave address register.

001 = Byte: This command uses the transmit slave address and command registers.

Bit 0 of the slave address register determines if this is a read or write

command.

010 = Byte Da ta : This command uses the transmit slave address, command, and

DATA0 registers. Bit 0 of the slave address register determines if this is a read

or write command. If it is a read, the DATA0 register will contain the read data.

011 = Word Data: This command uses the tr ans mit slav e address, command, DA TA0

and DATA1 registers. Bit 0 of the slave address register determines if this is a

read or write command. If it is a read, after the command completes, the

DATA0 and DATA1 registers will contain the read data.

100 = Process Call: This command uses the transmit slave address, command,

DATA0 and DATA1 registers. Bit 0 of the slave address register determines if

this is a read or write command. After the command completes, the DA TA0 and

DATA1 registers will contain the read data.

101 = Block: This command uses the transmit slave address, command, DATA0

registers, and the Block Data Byte register. For block write, the count is stored

in the DA TA0 register and indicates how many bytes of data will be transferred.

For block reads, the count is received and stored in the DATA0 register. Bit 0 of

the slave address register selects if this is a read or write command. For writes,

data is retrieved from the first n (where n is equal to the specified count)

addresses of the SRAM array. For reads, the data is stored in the Block Data

Byte register.

110 = I2C Read: This command uses the transmit slave address, command, DATA0,

DA T A1 re gisters, and the Bl ock Data Byte register. The read data is stored i n the

Block Data Byte register. The ICH7 continues reading data until the NAK is

received.

111 = Block Process: This command uses the transmit slave address, command,

DATA0 and the Block Data Byte register. For block write, the count is stored in

the DATA0 re gister and indicates how many bytes of data will be transferred.

For block read, the count is received and stored in the DATA0 register. Bit 0 of

the slav e addres s r egi st er always indic ate a writ e com mand. For writes, data is

retrieved from the fir st m (where m is equal to the specified count) addresses of

the SRAM array. For reads, the data is stored in the Block Data Byte register.

NOTE: E32B bit in the Auxiliary Control regi ster must be set for this command to work.

KILL — R/W.

0 = Normal SMBus host controller functionality.

1 = Kills the current host transaction taking place, sets the FAILED status bit, and

asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to

allow the SMBus h ost controller to function normally.

INTREN — R/W.

0 = Disable.

1 = Enable the generation of an interrupt or SMI# upon the completion of the

command.

Bit Description

Intel ® ICH7 Family Datasheet 593

SMBus Controller Registers (D31:F3)

14.2.3 HST_CMD—Host Command Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

14.2.4 XMIT_SLVA—Transmit Sla v e Addr ess Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

This register is transmitted by the host controller in the slave address field of the

SMBus protocol.

14.2.5 HST_D0—Host Data 0 Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

14.2.6 HST_D1—Host Data 1 Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Bit Description

7:0 This 8-bit field is tr ansm itt ed by the host controller in the com man d fiel d of the SMBu s

protocol during the execution of any command.

Bit Description

7:1 Address — R/W. This field provides a 7-bit address of the targeted slave.

0RW — R/W. Direction of the host transfer.

0 = Write

1 = Read

Bit Description

7:0

Data0/Count — R/W. This field contains the 8-bit data sent in the D ATA0 field of the

SMBus protocol. F or block write commands, this register reflects the number of bytes to

transfer. This register should be programmed to a value between 1 and 32 for block

counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host

controller does not check or log invalid block counts.

Bit Description

7:0 Data1 — R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus

protocol during the execution of any command.

SMBus Controller Registers (D31:F3)

594 Intel ® ICH7 Family Datasheet

14.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

14.2.8 PEC—Packet Error Check (PEC) Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Bit Description

7:0

Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block

array, depending upon whether the E32B bit is set in the Auxiliary Control register.

When the E32B bit (offset SMBASE + 0Dh, bit 1) is cleared, this is a register containing

a byte of data to be sent on a block write or read from on a block read, just as it

behaved on the ICH3.

When the E32B bit is set, reads and writes to this register are used to access the 32-

byte block data storage array. An internal index pointer is used to address the array,

which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then

increments automatically upon each access to this register. The transfer of block data

into (read) or out of (write) this storage array during an SMBus transaction always

starts at index address 0.

When the E2B bit is set, for writes, software will write up to 32-bytes to this register as

part of the setup for the command. After the Host controller has sent the Address,

Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this

When the E2B bit is cleared for writes, software will place a single byte in this register.

After the host controller has sent the address, command, and byte count fields, it will

send the byte in this regi ster. If there is more dat a to send, s oftw are will writ e the next

series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The

controller will then send the ne xt byte. During the tim e between the last byte being

transmitted to the next byte being transmitted, the controller will insert wait-states on

the interface.

When the E2B bit is set for reads, after receiving the byte count into the Data0 register,

the first series of data bytes go into the SRAM pointed to by this register. If the byte

count has been exhau sted or the 32-byte SRAM has been filled, the controlle r will

generate an SMI# or interrupt (depending on configur ation) an d set the DONE_STS bit.

Software will then read the data. During the time between when the last byte is read

from the SRAM to when the DONE_STS bit is cleared, the controller will insert wait-

states on the interface.

Bit Description

7:0

PEC_DATA — R/W. This 8-bit register is written with the 8-bit CRC value that is used

as the SMBus PEC data prior to a write tr ansaction. F or read transacti ons, the PEC data

is loaded from the SMBus into this register and is then read by software. Softw are must

ensure that the INUSE_STS bit is properly maintained to avoid hav ing this field over-

written by a write transaction following a read transaction.

Intel ® ICH7 Family Datasheet 595

SMBus Controller Registers (D31:F3)

14.2.9 RCV_SLVA—Receive Slave Address Register

(SMBUS—D31:F3)

Default Value: 44h Size: 8 bits

Lockable: No Power Well: Resume

14.2.10 SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Resume

This register contains the 16-bit data value written by the external SMBus master. The

processor can then read the value from this register. This register is reset by RSMRST#,

but not PLTRST#

14.2.11 AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Resume

Bit Description

7Reserved

6:0

SLAVE_ADDR — R/W. This field is the slave address that the Intel® ICH7 decodes for

read and write cycles. the default is not 0, so the SMBus Slave Interface can respond

even before the processor comes up (or if the processor is dead). This register is

cleared by RSMRST#, but not by PLTRST#.

Bit Description

15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.21.7 for a discussion of

this field.

7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.21.7 for a discussion of

this field.

Bit Description

7:2 Reserved

SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible

mode vs. Advanced TCO mode.

0 = Intel® ICH7 is in the compatible TCO mode.

1 = ICH7 is in the advanced TCO mode.

CRC Error (CRCE) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set if a received message contained a CRC error. When this bit is set, the

DERR bit of the host status register will also be set. This bit will be set by the

controller if a software abort occurs i n the middl e of the CR C portion of the cy cl e or

an abort happens after the ICH7 has received the final data bit transmitted by an

external slave.

SMBus Controller Registers (D31:F3)

596 Intel ® ICH7 Family Datasheet

14.2.12 AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Resume

14.2.13 SMLINK_PIN_CTL—SMLink Pin Control Regi ster

(SMBUS—D31:F3)

Default Value: See below Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

This register is only applicable in the TCO compatible mode.

Bit Description

7:2 Reserved

Enable 32-Byte Buffer (E32B) — R/W.

0 = Disable.

1 = Enable. When set, the Host Bloc k Data register is a pointe r into a 32-byte buffer, as

opposed to a single regi ster. This enables the block commands t o transfer or receiv e

up to 32-bytes before the Intel® ICH7 generates an interrupt.

Automatically Append CRC (AAC) — R/W.

0 = ICH7 will Not automatically append the CRC.

1 = The ICH7 will automatically append the CRC. This bit must not be changed during

SMBus transactions or undetermined behavior will result. It should be programmed

only once during the lifetime of the function.

Bit Description

7:3 Reserved

SMLINK_CLK_CTL — R/W.

0 = Intel® ICH7 will drive t he SMLINK0 pin low , independent of what the other SMLINK

logic would otherwise indicate for the SMLINK0 pin.

1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state

of the pin. (Default)

SMLINK1_CUR_STS — RO . This read-only bit has a default value that is depend ent on

an external signal level. This pin returns the value on the SMLINK1 pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

SMLINK0_CUR_STS — RO . This read-only bit has a default value that is depend ent on

an external signal level. This pin returns the value on the SMLINK0 pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

Intel ® ICH7 Family Datasheet 597

SMBus Controller Registers (D31:F3)

14.2.14 SMBUS_PIN_CTL—SMBUS Pin Control Register

(SMBUS—D31:F3)

Default Value: See below Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

14.2.15 SLV_STS—Slave Status Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

All bits in this register are implemented in the 64 kHz clock domain. Therefore,

software must poll this register until a write takes effect before assuming that a write

has completed internally.

Bit Description

7:3 Reserved

SMBCLK_CTL — R/W.

1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of

the pin.

0 = Intel® ICH7 drives the SMBCLK pin low, independent of what the other SMB logic

would otherwise indicate for the SMBCLK pin. (Default)

SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent

on an external signal level. This pin returns the value on the SM B DATA pin . Thi s allows

software to read the current state of the pin.

0 = Low

1 = High

SMBCLK_CUR_STS — RO . This read-o nly bit has a default value that is dependent on

an external signal level. This pin returns the value on the SMBCLK pin. This allows

software to read the current state of the pin.

0 = Low

1 = High

Bit Description

7:1 Reserved

HOST_NOTIFY_STS — R/WC. The Intel® ICH7 sets this bit to a 1 when it has

completely recei ved a successful Host Notify Command on the SMLink pins. Software

reads this bit to determine that the source of the interrupt or SMI# was the reception of

the Host Notify Command. Software clears this bit after reading any information

needed from the Notify address and data registers by writing a 1 to this bit. Note that

the ICH7 will allow the Notify Address and Data registers to be over-written once this

bit has been cleared. When this bit is 1, the ICH7 will NACK the first byte (host address)

of any new “Host Notify” commands on the SMLink. Writing a 0 to t his bi t has no effect .

SMBus Controller Registers (D31:F3)

598 Intel ® ICH7 Family Datasheet

14.2.16 SLV_CMD—Slave Command Register (SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

14.2.17 NOTIFY_DADDR—Notify Device Address Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

Bit Description

7:2 Reserved

SMBALERT_DIS — R/W.

0 = Allows the generation of the interrupt or SMI#.

1 = Software sets this bit to block the generation of the interrupt or SMI# due to the

SMBALERT# source. This bit is logically inverted and ANDed with the

SMBALERT_STS bit (o ffset SMBASE + 00h, bit 5). The resulting signal is distributed

to the SMI# and/or interrupt generation logic. This bit does not effect the wake

logic.

HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a

Host Notify command as a wake event. When enabled this event is “OR”ed in with the

other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General

Purpose Event 0 Status register.

0 = Disable

1 = Enable

HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation

of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This

enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is

generated, either PIRQB# or SMI# is generated, depending on the value of the

SMB_SMI_EN bit (D 31:F3: 40h, bit 1) . If t he HOST_NOTIFY_ST S bit is s et whe n this bit

is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or

SMI#) is logically generated by AND’ing the STS and INTREN bits.

0 = Disable

1 = Enable

Bit Description

7:1

DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during

the Host Notify protocol of the SMBus 2.0 Specification. Sof tw a re should only cons ider

this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to

0Reserved

Intel ® ICH7 Family Datasheet 599

SMBus Controller Registers (D31:F3)

14.2.18 NOTIFY_DLOW—Notify Data Low Byte Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

14.2.19 NOTIFY_DHIGH—Notify Data High Byte Register

(SMBUS—D31:F3)

Default Value: 00h Size: 8 bits

Note: This register is in the resume well and is reset by RSMRST#.

Bit Description

7:0

DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received

during the Host Notify protocol of the SMBus 2.0 specification. Software should only

consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)

is set to 1.

Bit Description

7:0

DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received

during the Host Notify protocol of the SMBus 2.0 specification. Software should only

consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)

is set to 1.

SMBus Controller Registers (D31:F3)

600 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 601

IDE Controller Registers (D31:F1)

15 IDE Controller Registers

(D31:F1)

15.1 PCI Configuration Registers (IDE—D31:F1)

Note: Address locations that are not shown should be treated as Reserved (See Section 6.2

for details).

All of the IDE registers are in the core well. None of the registers can be locked.

NOTE: The ICH7 IDE controller is not arbitrated as a PCI device; therefore, it does not need a

master latency timer.

Table 15-1. IDE Controller PCI Register Address Map (IDE-D31:F1)

Offset Mnemonic Register Name Default Type

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 00h R/W, RO

06h–07h PCISTS PCI Status 0280h R/W, RO

08h RID Revision Identification See register

description. RO

09h PI Programming Interface 8Ah R/W, RO

0Ah SCC Sub Class Code 01h RO

0Bh BCC Base Class Code 01h RO

0Ch CLS Cache Line Size 00h RO

0Dh PMLT Primary Master Latency Timer 00h RO

10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO

14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO

18h–1Bh SCMD_BAR Secondary Command Block Base Address 00000001h R/W, RO

1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO

20h–23h BM_BASE Bus Master Base Address 00000001h R/W, RO

2Ch–2Dh IDE_SVID Subsystem Vendor ID 00h R/WO

2Eh–2Fh IDE_SID Subsystem ID 0000h R/WO

3C INTR_LN Interrupt Line 00h R/W

3D INTR_PN Interrupt Pin See register

description. RO

40h–41h IDE_TIMP Primary IDE Timing 0000h R/W

42h–43h IDE_TIMS Secondary IDE Timing 0000h R/W

44h SLV_IDETIM Slave IDE Timing 00h R/W

48h SDMA_CNT Synchronous DMA Control 00h R/W

4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W

54h IDE_CONFIG IDE I/O Configuration 00000000h R/W

C0h ATC APM Trapping Control 00h R/W

C4h ATS APM Trapping Status 00h R/WC

IDE Controller Registers (D31:F1)

602 Intel ® ICH7 Family Datasheet

15.1.1 VID—Vendor Identification Register (IDE—D31:F1)

Offset Address: 00h–01h Attribute: RO

Default Value: 8086h Size: 16-bit

Lockable: No Power Well: Core

15.1.2 DID—Device Identification Register (IDE—D31:F1)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16-bit

Lockable: No Power Well: Core

15.1.3 PCICMD—PCI Command Register (IDE—D31:F1)

Address Offset: 04h–05h Attribute: RO, R/W

Default Value: 00h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assi gned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 IDE controller. Refer

to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update for the value of

the Device ID Register.

Bit Description

15:11 Reserved

Interrupt Disable (I D) — R/W.

0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy

mode).

1 = Disable. The interrupt will be deasserted.

9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.

8 SERR# Enable (SERR_EN) — RO. Reserved as 0.

7 Wait Cycle Control (WCC) — RO. Reserved as 0.

6 Parity Error Response (PER) — RO. Reserved as 0.

5 VGA Palette Snoop (VPS) — RO. Reserved as 0.

4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.

3 Special Cycle Enable (SCE) — RO. Reserved as 0.

2Bus Master Enable (BME) — R/W. Controls the ICH7’s ability to act as a PCI master

for IDE Bus Master transfers.

1Memory Space Enable (MSE) — R/O.

This controller does not contain a memory space.

0I/O Space Enable (IOSE) — RO.

Intel ® ICH7 Family Datasheet 603

IDE Controller Registers (D31:F1)

15.1.4 PCISTS — PCI Status Register (IDE—D31:F1)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0280h Size: 16 bits

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

15.1.5 RID—Revision Identification Register (IDE—D31:F1)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

Bit Description

15 Detected Parity Error (DPE) — RO. Reserved as 0.

14 Signaled System Error (SSE) — RO. Re served as 0.

13 Received Master Abort (RMA) — R/WC.

0 = Master abort Not generated by Bus Master IDE interface function.

1 = Bus Master IDE interface function, as a master, generated a master abort.

12 Reserved as 0 — RO.

11 Reserved as 0 — RO.

10:9 DEVSEL# Timing Status (DEV_STS) — RO.

01 = Hardwired; however, the Intel® ICH7 does not have a real DEVSEL# signal

associated with the IDE unit, so these bits have no effect.

8 Data Parity Error Detected (DPED) — RO. Reserved as 0.

7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.

6 User Definable Features (UDF) — RO. Reserved as 0.

5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.

4Reserved

Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt

Disable bit in the command register.

0 = Interrupt is cleared.

1 = Interrupt/MSI is asserted.

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

IDE Controller Registers (D31:F1)

604 Intel ® ICH7 Family Datasheet

15.1.6 PI—Programming Interface Register (IDE—D31:F1)

Address Offset: 09h Attribute: RO, R/W

Default Value: 8Ah Size: 8 bits

15.1.7 SCC—Sub Class Code Register (IDE—D31:F1)

Address Offset: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

15.1.8 BCC—Base Class Code Register (IDE—D31:F1)

Address Offset: 0Bh Attribute: RO

Default Value: 01h Size: 8 bits

15.1.9 CLS—Cache Line Size Register (IDE—D31:F1)

Address Offset: 0Ch Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7 This read-only bit is a 1 to indicat e that the Intel® ICH7 supports bus master operation

6:4 Reserved. Hardwired to 000b.

3SOP_MODE_CAP — RO. This read-only bit is a 1 to i ndicate that the secondary

controller supports both legacy and native modes.

SOP_MODE_SEL — R/W. This read/write bit determines the mode that the seco ndary

IDE channel is operating in.

0 = Legacy-PCI mode (default)

1 = Native-PCI mode

1POP_MODE_CAP — RO . This read-only bit is a 1 to indic ate that the primary controller

supports both legacy and native modes.

POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary

IDE channel is operating in.

0 = Legacy-PCI mode (default)

1 = Native-PCI mode

Bit Description

7:0 Sub Class Code (SCC) — RO.

01h = IDE device, in the c ontext of a mass storage device.

Bit Description

7:0 Base Class Code (BCC) — RO.

01 = Mass storage device

Bit Description

7:0 Cache Line Size (CLS) — RO.

00h = Hardwired. The IDE controller is implemented internally so this register has no

meaning.

Intel ® ICH7 Family Datasheet 605

IDE Controller Registers (D31:F1)

15.1.10 PMLT—Primary Master Latency Timer Register

(IDE—D31:F1)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

15.1.11 PCMD_BAR—Primary Command Block Base Address

Address Offset: 10h–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.

15.1.12 PCNL_BAR—Primary Control Block Base Address

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.

Bit Description

7:0 Master Latency Timer Count (MLTC) — RO.

00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as

a PCI device, so it does not need a Master Latency Timer.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).

2:1 Reserved

0 R esource Type Indicator (RTE) — RO . Hardwired to 1 indicating a request for I/O space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).

1 Reserved

0 R esource Type Indicator (RTE) — RO . Hardwired to 1 indicating a request for I/O space.

IDE Controller Registers (D31:F1)

606 Intel ® ICH7 Family Datasheet

15.1.13 SCMD_BAR—Secondary Command Block Base Address

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

15.1.14 SCNL_BAR—Secondary Control Block Base Address

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command

Block.

Bit Description

31:16 Reserved

15:3 Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations). If

this register is programmed, the programmed value must not be less than 100h.

2:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indi cating a request for I/O space.

Bit Description

31:16 Reserved

15:2 Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations). If

this register is programmed, the programmed value must not be less than 100h.

1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 indi cating a request for I/O space.

Intel ® ICH7 Family Datasheet 607

IDE Controller Registers (D31:F1)

15.1.15 BM_BASE — Bus Master Base Address Register

(IDE—D31:F1)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16-

byte I/O space to provide a software interface to the Bus Master functions. Only 12

bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]

are used to decode the address.

15.1.16 IDE_SVID — Subsystem Vendor Identification

(IDE—D31:F1)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 00h Size: 16 bits

Lockable: No P ower Well: Core

15.1.17 IDE_SID — Subsystem Identification Register

(IDE—D31:F1)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No P ower Well: Core

Bit Description

31:16 Reserved

15:4 Base Address — R/W. This field provides the base address of the I/O space (16

consecutive I/O locations).

3:1 Reserved

0 R esource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.

Bit Description

15:0

Subsystem Vendor ID (SVID) — R/WO. The SVID register, in combination with the

Subsystem ID (S ID) register, enables the operating system (OS) to distinguish

subsystems from each other. Software (BIOS) sets the val ue in this register. After that,

the value can be read, but subsequent writes to this register have no effect. The value

written to this regi ster will also be readable via the corresponding SVID registers for the

USB#1, USB#2, and SMBus functions.

Bit Description

15:0

Subsystem ID (S ID) — R/WO. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. Software

(BIOS) sets the value in this register. After that, the value can be read, but subsequent

writes to this register have no effect. The value written to this register will also be

readable via the corresponding SID registers for the USB#1, USB#2, and SMBus

functions.

IDE Controller Registers (D31:F1)

608 Intel ® ICH7 Family Datasheet

15.1.18 INTR_LN—Interrupt Line Register (IDE—D31:F1)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

15.1.19 INTR_PN—Interrupt Pin Register (IDE—D31:F1)

Address Offset: 3Dh Attribute: RO

Default Value: See Register Description Size: 8 bits

15.1.20 IDE_TIMP — IDE Primary Timing Register (IDE—D31:F1)

Address Offset: 40–41h Attribute: R/W

Default Value: 0000h Size: 16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA

transfers. It also controls operation of the buffer for PIO transfers.

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This field is used to communicate to software the

interrupt line that the interrupt pin is connected to.

Bit Description

7:0 Interrupt Pin — RO. This reflects the value of D31IP.PIP (Chipset Config

Registers:Offset 3100h:bits 7:4).

Bit Description

IDE Decode Enable (IDE) — R/W. The IDE I/O Space Enable bit (D31:F1:04h, bit

0) in the Command register must be set in order for this bit to have any effect.

0 = Disable.

1 = Enables the Intel® ICH7 to decode the Command (1F0–1F7h) and Control (3F6h)

Blocks.

This bit also effects the memory decode range for IDE Expansion.

14 Drive 1 Timing Register Enable (SITRE) — R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

13:12

IORDY Sample Point (ISP) — R/W. The setting of these bits determine the

number of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample

point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

11:10 Reserved

9:8

Recovery Time (RCT) — R/W. The setting of these bits determines the minimum

number of PCI clocks between the last IORDY sample point and the IOR#/IOW#

strobe of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

Intel ® ICH7 Family Datasheet 609

IDE Controller Registers (D31:F1)

(Desktop

and

Mobile

Only)

Drive 1 DMA Timing Enable (DTE1) — R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers

to the IDE data port will run in compatible timing.

(Desktop

and

Mobile

Only)

Drive 1 Prefetch/Posting Enable (PPE1) — R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

(Desktop

and

Mobile

Only)

Drive 1 IORDY Sample Point Enable (IE1) — R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

(Desktop

and

Mobile

Only)

Drive 1 Fast Timing Bank (TIME1) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit = 1 and bit 14 = 0, ac cesses to the data port will use bits 13:12 for

the IORDY sample point, and bits 9:8 for the recovery time. When this bit = 1

and bit 14 = 1, accesses to the data port will use the IORDY sample point and

recover time specified in the slave IDE timing register.

7:4

(Ultra

Mobile

Only)

Reserved

Drive 0 DMA Timing Enable (DTE0) — R/W.

0 = Disable

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to

the IDE data port will run in compatible timing.

2Drive 0 Prefetch/Posting Enable (PPE0) — R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the IDE data port for this drive.

1Drive 0 IORDY Sample Point Enable (IE0) — R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0) — R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and

bits 9:8 for the recovery time

Bit Description

IDE Controller Registers (D31:F1)

610 Intel ® ICH7 Family Datasheet

15.1.21 IDE_TIMS — IDE Secondary Timing Register

(IDE—D31:F1)

Address Offset: 42h–43h Attribute: R/W

Default Value: 0000h Size: 16 bits

15.1.22 SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1) (Desktop and Mobile Only)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

IDE Decode Enable (IDE) — R/W. This bit enables/disables the Secondary decode.

The IDE I/O Space Enable bit (D31:F1:04h, bit 0) in the Command register must be

set in order for this bit to have any effect. Additionally, separate configuration bits are

provided (in the ID E I/O Configuration register) to individually disable the secondary

IDE interface signals, even if the IDE Decode Enable bit is set.

0 = Disable.

1 = Enables the Intel® ICH7 to decode the associated Command Blocks (170–177h)

and Control Block (376h). Accesses to these ranges return 00h, as the secondary

channel is not implemented.

14:12 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no funct ionality in the ICH7 si nce a secondary channe l does not

exist.

11 Reserved

10:0 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no funct ionality in the ICH7 si nce a secondary channe l does not

exist.

Bit Description

7:4 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the Intel® ICH7.

3:2

Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the

number of PCI clocks between IOR#/IOW# assertion and the first IORDY sampl e point,

if the access is to drive 1 data port and bit 14 of the IDE timing register for primary is

set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

1:0

Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the

minimum number of PCI cl ocks between the last IORDY sample point and the IOR#/

IOW# strobe o f the next cy cle, if the ac cess is to driv e 1 data port and bit 14 of the IDE

timing register for primary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

Intel ® ICH7 Family Datasheet 611

IDE Controller Registers (D31:F1)

15.1.23 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1)

Address Offset: 48h Attribute: R/W

Default Value: 00h Size: 8 bits

15.1.24 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1)

Address Offset: 4Ah–4Bh Attribute: R/W

Default Value: 0000h Size: 16 bits

Note: For F A ST_PCB1 = 1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.16.4

for details.

Bit Description

7:4 Reserved

3:2 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the Intel® ICH7.

(Desktop

and

Mobile

Only)

Primary Drive 1 Synchronous DMA Mode Enable (PSDE1) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 1.

(Ultra

Mobile

Only)

Reserved

0Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.

0 = Disable (default)

1 = Enable Synchronous DMA mode for primary channel drive 0.

Bit Description

15:14 Reserved

13:12 No Operati on (NOP) — R/ W. These bits are read/wri te for legacy software compatibility,

but have no functionality in the Intel® ICH7.

11:10 Reserved

9:8 No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,

but have no functionality in the ICH7.

7:6 Reserved

IDE Controller Registers (D31:F1)

612 Intel ® ICH7 Family Datasheet

15.1.25 IDE_CONFIG—IDE I/O Configuration Register

(IDE—D31:F1)

Address Offset: 54h Attribute: R/W

Default Value: 00000000h Size: 32 bits

5:4

(Desktop

and

Mobile

Only)

Primary Driv e 1 Cycle Time (PCT 1) — R/W. Fo r Ultra AT A mode, the sett ing of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

5:4

(Ultra

and

Mobile

Only)

Reserved

3:2 Reserved

1:0

Primary Driv e 0 Cycle Time (PCT 0) — R/W. Fo r Ultra AT A mode, the sett ing of these

bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP

(RP) time is also determined by the setting of these bits.

Bit Description

PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

PCB1 = 0 (33 MHz clk) PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1

(133 MHz clk)

00 = CT 4 clocks, RP 6

clocks 00 = Reserved 00 = Reserved

01 = CT 3 clocks, RP 5

clocks 01 = CT 3 clocks, RP 8

clocks 01 = CT 3 clocks, RP 16

clocks

10 = CT 2 clocks, RP 4

clocks 10 = CT 2 clocks, RP 8

clocks 10 = Reserved

11 = Reserved 11 = Reserved 11 = Reserved

Bit Description

31:24 Reserved

23:20 Miscellaneous Scratchpad (MS) — R/W. Previously defined as a scratch pad bit to

indicate to a driver that ATA-100 is supported. This is not used by software as all

they needed to know was located in bits 7:4. See the definitio n of those bits.

19:18 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the Intel® ICH7.

Intel ® ICH7 Family Datasheet 613

IDE Controller Registers (D31:F1)

17:16

SIG_MODE — R/W. These bits are used to control mode of the IDE signal pins for

mobile/Ult ra Mobile swap bay support.

If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of

bits 17:16 will be 01 (tri-state) instead of 00 (normal).

00 = Normal (Enabled)

01 = Tr i-state (Disabl ed)

10 = Drive low (D isabled)

11 = Reserved

15:14 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH7.

(Desktop

and

Mobile

Only)

Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in

conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the

Primary Slave drive.

0 = Disable Ultra ATA/100 timing for the Prim ary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this

(Ultra

Mobile

Only)

Reserved

Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in

conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the

Primary Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra AT A/100 timing for the P rimary Master driv e (o verri des bit 0 in this

11:8 Reserved

7No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH7.

6No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH7.

Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to

tell the IDE driver which cable is plugged into the channel.

0 = 40 conductor cable is present.

1 = 80 conductor cable is present.

4Primary Master Channel Cable Reporting — R/W. Same description as bit 5

3:2 No Operation (NOP) — R/W. These bits are read/write for legacy software

compatibility, but have no functionality in the ICH7.

(Desktop

and

Mobile

Only)

Primary Drive 1 Base Clock (PCB1) — R/W.

0 = 33 M Hz base clock for Ultra ATA ti mings.

1 = 66 M Hz base clock for Ultra ATA ti mings

(Ultra

Mobile

Only)

Reserved

0Primary Drive 0 Base Clock (PCB0) — R/W.

0 = 33 M Hz base clock for Ultra ATA ti mings.

1 = 66 M Hz base clock for Ultra ATA ti mings

Bit Description

IDE Controller Registers (D31:F1)

614 Intel ® ICH7 Family Datasheet

15.1.26 ATC—APM Trapping Control Register (IDE—D31:F1)

Address Offset: C0h Attribute: R/W

Default Value: 00h Size: 8 bits

15.1.27 ATS—APM Trapping Status Register (IDE—D31:F1)

Address Offset: C4h Attribute: R/WC

Default Value: 00h Size: 8 bits

Bit Description

7:2 Reserved

Slave Trap (PST) — R/W.

0 = Disable.

1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and

3F6h. The active device must be the slave device for the trap and/or SMI# to occur.

Master Trap (PMT) — R/W.

0 = Disable.

1 = Enables trapping and SMI# assertion on legacy I/O accesses to 1F0h–1F7h and

3F6h. The active devi ce must be master device for the trap and/or SMI# to occur.

Bit Description

7:2 Reserved

1Slave Trap Status (PSTS) — R/WC.

1 = Trap occurred to the slave device

0Master Trap Status (PMTS) — R/WC.

0 = Trap occurred to the master de vice

Intel ® ICH7 Family Datasheet 615

IDE Controller Registers (D31:F1)

15.2 Bus Master IDE I/O Registers (IDE—D31:F1)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA

master IDE I/O space registers can be accessed as byte, word, or DWord quantities.

Reading reserved bits returns an indeterminate, inconsistent value, and writes to

reserved bits have no effect (but should not be attempted). The description of the I/O

registers is shown in Table 15-2.

15.2.1 BMICP—Bus Master IDE Command Register

(IDE—D31:F1)

Address Offset: BMIBASE + 00h Attribute: R/W

Default Value: 00h Size: 8 bits

Table 15-2. Bus Master IDE I/O Registers

BMIBASE

+ Offset Mnemonic Register Name Default Type

00 BMICP Bus Master IDE Command Primary 00h R/W

01 — Reserved 00h RO

02 BMISP Bus Master IDE Status Primary 00h R/W,

R/WC

03 — Reserved 00h RO

04–07 BMIDP Bus Master ID E Descriptor Table Pointer

Primary xxxxxxxxh R/W

Bit Description

7:4 Reserved. Returns 0.

Read / Write Control (RWC) — R/W. This bit sets the direction of the bus m aster

transfer: This bit must NOT be changed when the bus master function is active.

0 = Me mory read s

1 = Memory writes

2:1 Reserved. Returns 0.

IDE Controller Registers (D31:F1)

616 Intel ® ICH7 Family Datasheet

15.2.2 BMISP—Bus Master IDE Status Register (IDE—D31:F1)

Address Offset: BMIBASE + 02h Attribute: R/W, R/WC

Default Value: 00h Size: 8 bits

Start/Stop Bus Master (START) — R/W.

0 = All state information is lost when this bit is cleared. Master mode operation cannot

be stopped and then resumed. If this bit is reset while bus master operation is still

active (i .e. , the B us Master IDE Activ e bit (BMIBASE + 0 2h, bit 0) of the Bu s Master

IDE Status register for that IDE channel is set) and the drive has not yet finish ed

its data transfer (the Interrupt bit (BMIBASE + 02h , bit 2) in the Bus Master IDE

Status register for that IDE channel is not set), the bus master command is said to

be aborted and data transferred from the drive may be discarded instead of being

written to system memory.

1 = Enables bus ma ster operation of the controller. Bus m aster operation does not

actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI

configuration space is also set. Bus master operation begins when this bit is

detected changing from 0 to 1. The controller will transfer data between the IDE

device and memory only when this bit is set. Master operation can be halted by

writing a 0 to this bit.

NOTE: This bit is intended to be cleared by software after the data transfer is

completed, as indicated by either the Bus Master IDE Active bit being cleared or

the Interrupt bit of the Bus Master IDE Status register for that IDE channel

being set, or both. Hardware does not clear this bit automatically.

Bit Description

PRD Interrupt Status (PRDIS) — R/WC.

0 = When this bit is cleared by software, the interrupt is cleared.

1 = Set when the host controller completes execution of a PRD that has its Interrupt

bit (bit 2 of this register) set.

(Desktop

and

Mobile

Only)

Drive 1 DMA Capable — R/W.

0 = Not Capable.

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 1 for this channel is capable of DMA transfers, and that the controller has

been initialized for optimum performance. The Intel® ICH7 does not use this bit.

It is intended for systems that do not attach BMIDE to the PCI bus.

(Ultra

Mobile

Only)

Reserved

Drive 0 DMA Capable — R/W.

0 = Not Capable

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that

drive 0 for this channel is capable of DMA transfers, and that the controller has

been initialized for optimum performance. The ICH7 does not use this bit. It is

intended for sy stems that do not attach BMIDE to the PCI bus.

4:3 Reserved. Re tur ns 0.

Intel ® ICH7 Family Datasheet 617

IDE Controller Registers (D31:F1)

15.2.3 BMIDP—Bus Master IDE Descriptor Table Pointer Register

(IDE—D31:F1)

Address Offset: BMIBASE + 04h Attribute: R/W

Default Value: All bits undefined Size: 32 bits

Interrupt — R/WC. Software can use this bit to determine if an IDE device has

asserted its in terrupt line (IDEIRQ).

0 = Softwar e clears this bit by writing a 1 to it. If th is bit is cleared while the

interrupt is still active, this bit will remain clear until another assertion edge is

detected on the interrupt line.

1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the

interrupt is mask ed in the 8259 or the internal I/O APIC. When this bit is read as

1, all data transferred from the drive is visible in system memory.

Error — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when the controller encounters a target abort or master abort

when transferring data on PCI.

Bus Master IDE Active (ACT) — RO.

0 = This bit is cleared by the ICH7 when the last transfer for a region is performed,

where EOT for that region is set i n the regi on descriptor. It is also cleared by the

ICH7 when the Start bit is cleared in the Command register. When this bit is read

as 0, all data transferred from the drive during the previous bus master

command is visible in system memory, unless the bus master command was

aborted.

1 = Set by the ICH7 when the Start bit is written to the Command register.

Bit Description

31:2 Address of Descriptor Table (ADDR) — R/W. Corresponds to A[31:2]. The

Descriptor Table must be DWord-aligned. The Descriptor Table must not cross a 64-K

boundary in memory.

1:0 Reserved

IDE Controller Registers (D31:F1)

618 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 619

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16 AC ’97 Audio Controller

Registers (D30:F2) (Desktop

and Mobile Only)

Note: AC ‘97 is not supported on ICH7-U Ultra Mobile.

16.1 AC ’97 Audio PCI Configuration Space

(Audio—D30:F2)

Note: Registers that are not shown should be treated as Reserved.

Table 16-1. AC ‘97 Audio PCI Register Address Map (Audio—D30:F2)

Offset Mnemonic Register Name Default Access

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0280h R/WC, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 00 RO

0Ah SCC Sub Class Code 01h RO

0Bh BCC Base Class Code 04h RO

0Eh HEADTYP Header Type 00h RO

10h–13h NAMBAR Native Audio Mixer Base Address 00000001h R/W, RO

14h–17h NABMBAR Native Audio Bus Mastering Base Address 00000001h R/W, RO

18h–1Bh MMBAR Mixer Base Address (Mem) 00000000h R/W, RO

1Ch–1Fh MBBAR Bus Master Base Address (Mem) 00000000h R/W, RO

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAP_PTR Capabilities Pointer 50h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

40h PCID Programmable Codec ID 09h R/W

41h CFG Configuration 00h R/W

50h–51h PID PCI Power Management Capability ID 0001h RO

52h–53h PC PC -Power Management Capabilities C9C2h R O

54h–55h PCS Power Management Control and Status 0000h R/W, R /

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

620 Intel ® ICH7 Family Datasheet

Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers

except the following BIOS programmed registers as BIOS may not be in voked following

the D3-to-D0 transition. All resume well registers will not be reset by the D3HOT to D0

transition.

Core well registers not reset by the D3HOT to D0 transition:

• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)

• offset 2Eh–2Fh – Subsystem ID (SID)

• offset 40h – Programmable Codec ID (PCID)

• offset 41h – Configuration (CFG)

Resume well registers will not be reset by the D3HOT to D0 transition:

• offset 54h–55h – Power Management Control and Status (PCS)

• Bus Mastering Register: Global Status Register, bits 17:16

• Bus Mastering Register: SDATA_IN MAP register, bits 7:3

16.1.1 VID—Vendor Identification Register (Audio—D30:F2)

Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 Bits

Lockable: No Power Well: Core

16.1.2 DID—Device Identification Register (Audio—D30:F2)

Offset: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 Bits

Lockable: No Power Well: Core

Bit Description

15:0 Vendor ID. This is a 16-bit value assigned to Intel.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigne d to the Intel® ICH7 AC ‘97 Audio

controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

for the value of the Device ID Register.

Intel ® ICH7 Family Datasheet 621

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.1.3 PCICMD—PCI Command Register (Audio—D30:F2)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

PCICMD is a 16-bit control register. Refer to the PCI 2.3 specification for complete

details on each bit.

Bit Description

15:11 Reserved. Read 0.

Interrupt Disable (ID) — R/W.

0 = The INTx# signals may be asserted and MSIs may be generated.

1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate

MSIs.

9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.

8 SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.

7 Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.

6 Parity Error Response (PER) — RO. Not impl em ente d. Hardwired to 0.

5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.

4 Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.

3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

2Bus Master Enable (BME) — R/W. Controls standard PCI bus mastering capabili ties.

0 = Disable

1 = Enable

Memory Space Enable (MSE) — R/W. Enables memory space addresses to the AC ’97

Audio controlle r.

0 = Disable

1 = Enable

I/O Space Enable (IOSE) — R/W. This bit controls access to the AC ’97 Audio

controller I/O space registers.

0 = Disable (Default).

1 = Enable access to I/O space. The Native PCI Mode Base Address register should be

programmed prior to setting this bit.

NOTE: This bit becomes writable when the IOSE bit in offset 41h is set. If at any point

software decides to clear the IOSE bit, software must first clear the IOS bit.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

622 Intel ® ICH7 Family Datasheet

16.1.4 PCISTS—PCI Status Register (Audio—D30:F2)

Offset: 06h–07h Attribute: RO, R/WC

Default Value 0280h Size: 16 bits

Lockable: No Power Well: Core

PCISTS is a 16-bit status register. Refer to the PCI 2.3 specification for complete details

on each bit.

16.1.5 RID—Revision Identification Register (Audio—D30:F2)

Offset: 08h Attribute: RO

Default Value: See bit description Size: 8 Bits

Lockable: No Power Well: Core

Bit Description

15 Detected Parity Error (DPE). Not implemented. Hardwired to 0.

14 Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.

13 Master Abort Status (MAS) — R/WC. Software clears this bit by writing a 1 to it.

0 = No master abort generated.

1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort.

12 Reserved — RO. Will always read as 0.

11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the Intel® ICH7's

DEVSEL# timing when performing a positive decode.

01b = Medium timing.

8 Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.

7Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the

ICH7 as a target is capable of fast back-to-back transactions.

6 UDF Supported — RO. Not implemented. Hardwired to 0.

5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Indicates that the controller contains a capabilities

pointer list. The first item is pointed to by looking at configuration offset 34h.

3Interrupt Status (IS) — RO.

0 = This bit is 0 after the interrupt is cleared.

1 = This bit i s 1 when the INTx# is asserted.

2:0 Reserved.

Bit Description

7:0 Revi si on ID — RO. R efer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification

Update for the value of the Revision ID Register.

Intel ® ICH7 Family Datasheet 623

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.1.6 PI—Programming Interface Register (Audio—D30:F2)

Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

16.1.7 SCC—Sub Class Code Register (Audio—D30:F2)

Address Offset: 0Ah Attribute: RO

Default Value: 01h Size: 8 bits

Lockable: No Power Well: Core

16.1.8 BCC—Base Class Code Register (Audio—D30: F2)

Address Offset: 0Bh Attribute: RO

Default Value: 04h Size: 8 bits

Lockable: No Power Well: Core

16.1.9 HEADTYP—Header Type Register (Audio—D30:F2)

Address Offset: 0Eh A ttribute: RO

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Bit Description

7:0 Programming Interface — RO.

Bit Description

7:0 Sub Class Code (SCC) — RO.

01h = Audio De vice

Bit Description

7:0 Base Class Code (BCC) — RO.

04h = Multimedia device

Bit Description

7:0 Header Type — RO. Hardwired to 00h.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

624 Intel ® ICH7 Family Datasheet

16.1.10 NAMBAR—Native Audio Mixer Base Address Register

(Audio—D30:F2)

Address Offset: 10–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Lockable: No Power Well: Core

The Native PCI Mode Audio function uses PCI Base Address register #1 to request a

contiguous block of I/O space that is to be used for the Native Audio Mixer software

interface. The mixer requires 256 bytes of I/O space. Native Audio Mixer and Modem

codec I/O registers are located from 00h to 7Fh and reside in the codec. Access to

these registers will be decoded by the AC '97 controller and forwarded over the AC -link

to the codec. The codec will then respond with the register value.

In the case of the split codec implementation, accesses to the different codecs are

differentiated by the controller by using address offsets 00h–7Fh for the primary codec

and address offsets 80h–FEh for the secondary codec.

Note: The tertiary codec cannot be addressed via this address space. The tertiary space is

only available from the new MMBAR register. This register powers up as read only and

only becomes write-able when the IOSE bit in offset 41h is set.

For description of these I/O registers, refer to the Audio Codec ‘97 Component

Specification, Version 2.3.

Bit Description

31:16 Hardwired to 0s.

15:8

Base Address — R/W. These bits are used in the I/O space decode of the Nativ e Audio

Mixer interface registers. The number of upper bits that a device actually implements

depends on how much of the address space the device will respond to. For the AC ‘97

mixer, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This

configuration yields a maximum I/O block size of 256 bytes for this base address.

7:1 Reserved. Read as 0s.

0Resource Type Indicator (RTE) — RO. This bit defaults to 0 and changes to 1 if the

IOSE bit is set (D30:F2:Offset 41h, bit 0). When 1, this bit indicates a request for I/O

space.

Intel ® ICH7 Family Datasheet 625

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.1.11 NABMBAR—Native Audio Bus Mastering Base Address

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

Lockable: No Power Well: Core

The Native PCI Mode Audio function uses PCI Base Address register #1 to request a

contiguous block of I/O space that is to be used for the Native Mode Audio software

interface.

Note: The DMA registers for S/PDIF* and Microphone In 2 cannot be addressed via this

address space. These DMA functions are only available from the new MBBAR register.

This register powers up as read only and only becomes write-able when the IOSE bit in

offset 41h is set.

16.1.12 MMBAR—Mixer Base Address Register (Audio—D30:F2)

Address Offset: 18h–1Bh Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Lockable: No Power Well: Core

This BAR creates 512 bytes of memory space to signify the base address of the register

space. The lower 256 bytes of this space map to the same registers as the 256-byte I/

O space pointed to by NAMBAR. The lower 384 bytes are divided as follows:

• 128 bytes for the primary codec (offsets 00–7Fh)

• 128 bytes for the secondary codec (offsets 80–FFh)

• 128 bytes for the tertiary codec (offsets 100h–17Fh).

• 128 bytes of reserved space (offsets 180h–1FFh), returning all 0’s.

Bit Description

31:16 Hardwired to 0s

15:6

Base Address — R/W. These bits are used in the I/O space decode of the Native Audio

Bus Mastering interface registers. The number of upper bits that a device actually

implements depends on how much of the address space the device will resp ond to . For

AC '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are

programmable. This configuration yields a maximum

I/O block size of 64 bytes for this base address.

5:1 Reserved. Read as 0’s.

0Resource Type Indicator (RTE) — RO. This bit defaults to 0 and changes to 1 if the

IOSE bit is set (D30:F2:Offset 41h, bit 0). When 1, this bit indicates a request for I/O

space.

Bit Description

31:9 Base Address — R/W. This field provides the lower 32-bits of the 512-byte memory

offset to use for decoding the primary, secondary, and tertiary codec’s mixer spaces.

8:3 Reserved. Read as 0s.

2:1 Type — RO. Hardwired to 00b to Indicate the base address exists in 32-bit address

space

0Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory

space.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

626 Intel ® ICH7 Family Datasheet

16.1.13 MBBAR—Bus Master Base Address Register

(Audio—D30:F2)

Address Offset: 1Ch–1Fh Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Lockable: No Power Well: Core

This BAR creates 256-bytes of memory space to signify the base address of the bus

master memory space. The lower 64-bytes of the space pointed to by this register

point to the same registers as the MBBAR.

16.1.14 SVID—Subsystem Vendor Identification Register

(Audio—D30:F2)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

The SVID register, in combination with the Subsystem ID register (D30:F2:2Eh),

enable the operating environment to distinguish one audio subsystem from the

other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

Bit Description

31:8 Base Address — R/W. This field provides the I/O offset to use for decoding the PCM In,

PCM Out, and Microphone 1 DMA engines.

7:3 Reserved. Read as 0s.

2:1 Type — RO. Hardwired to 00b to indicate the base address exists in 32-bit address

space

0Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory

space.

Bit Description

15:0 Subsystem Vendor ID — R/WO.

Intel ® ICH7 Family Datasheet 627

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.1.15 SID—Subsystem Identification Register (Audio—D30:F2)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

The SID register, in combination with the Subsystem Vendor ID register (D30:F2:2Ch)

make it possible for the operating environment to distinguish one audio subsystem

from the other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

16.1.16 CAP_PTR—Capabilities Pointer Register (Audio—D30:F2)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

Lockable: No Power Well: Core

This register indicates the offset for the capability pointer.

16.1.17 INT_LN—Interrupt Line Register (Audio—D30:F2)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.

Bit Description

15:0 Subsystem ID — R/WO.

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer

offset is offset 50h

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not us ed by t he Inte l® ICH7. It is used

to communicate to software the interrupt line that the interrupt pin is connected to.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

628 Intel ® ICH7 Family Datasheet

16.1.18 INT_PN—Interrupt Pin Register (Audio—D30:F2)

Address Offset: 3Dh Attribute: RO

Default Value: See Description Size: 8 bits

Lockable: No Power Well: Core

This register indicates which PCI interrupt pin is used for the AC '97 module interrupt.

The AC '97 interrupt is internally OR’d to the interrupt controller with the PIRQB#

signal.

16.1.19 PCID—Programmable Codec Identification Register

(Audio—D30:F2)

Address Offset: 40h Attribute: R/W

Default Value: 09h Size: 8 bits

Lockable: No Power Well: Core

This register is used to specify the ID for the secondary and tertiary codecs for I/O

accesses. This register is not affected by the D3HOT to D0 transition. The value in this

16.1.20 CFG—Configuration Register (Audio—D30:F2)

Address Offset: 41h Attribute: R/W

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

This register is used to specify the ID for the secondary and tertiary codecs for I/O

accesses. This register is not affected by the D3HOT to D0 transition.

Bit Description

7:0 AC '97 Interrupt Routing — RO. This reflects the value of D30IP.AAIP in chipset

configuration space.

Bit Description

7:4 Reserved.

3:2 Tertiary Codec ID (TID) — R/W. These bits define the encoded ID that is used to

address the tertia ry codec I/O space. Bit 1 is th e first bit sent and Bit 0 is the second bit

sent on ACZ_SDOUT during slot 0.

1:0

Secondary Code c ID (S CID) — R/W. These two bits define the encoded ID that is

used to address the sec o ndary codec I/O space. The two bits are the ID that will be

placed on slot 0, bits 0 and 1, upon an I/O access to the secondary codec. Bit 1 is the

first bit sent and bit 0 is the second bit sent on ACZ_SDOUT during slot 0.

Bit Description

7:1 Reserved—RO.

I/O Space Enable (IOSE) — R/W.

0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h

become read only registers. Additionally, bit 0 o f the I/O BARs at offsets 10h and

14h are hardwired to 0 when this bit is 0. This is the default state for the I/O BARs.

BIOS must explicitly set thi s bit to allow a legacy driver to work.

1 = Enable.

Intel ® ICH7 Family Datasheet 629

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.1.21 PID—PCI Power Management Capability Identification

Address Offset: 50h–51h Attribute: RO

Default Value: 0001h Size: 1 6 bits

Lockable: No Power Well: Core

16.1.22 PC—Power Management Capabilities Register

(Audio—D30:F2)

Address Offset: 52h–53h Attribute: RO

Default Value: C9C2h Size: 16 bits

Lockable: No Power Well: Core

This register is not affected by the D3HOT to D0 transition.

Bit Description

15:8 Next Capability (NEXT) — RO. This field indicates that the next item in the list is at

offset 00h.

7:0 Capability ID (CAP) — RO.This field indicates that this pointer is a message signaled

interrupt capability

Bit Description

15:11 PME Support — RO. This field indicates PME# can be generated from all D states.

10:9 Reserved.

8:6 Auxiliary Current — RO. This field reports 375 mA maximum suspend well current

required when in the D3COLD state.

5Device Specifi c Initialization (D SI)—RO. This field indicates that no device-specific

initialization is required.

4 Reserved — RO.

3PME Clock (PMEC) — RO. This field indicates that PCI clock is not required to generate

PME#.

2:0 Version (VER) — RO. This field indicates support for Revision 1.1 of the PCI Power

Management Specification.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

630 Intel ® ICH7 Family Datasheet

16.1.23 PCS—Power Management Control and Status Regi ster

(Audio—D30:F2)

Address Offset: 54h–55h Attribute: R/W, R/WC

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Resume

Bit Description

PME Status (PMES) — R/WC. This bit resides in the resume well. Software clears this

bit by writing a 1 to it.

0 = PME# signal Not asserted by AC ‘97 controller.

1 = This bit is set when the AC ’97 controller would normally assert the PME# signal

independent of the state of the PME_En bit.

14:9 Reserved — RO.

Power Management Event Enable (PMEE) — R/W.

0 = Disable.

1 = Enable. When set, and i f corresponding PMES is also set, the AC '97 controller sets

the AC97_STS bit in the GPE0_STS register

7:2 Reserved—RO.

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the AC ’97 controller and to set a new power state. The values are:

00 = D0 st ate

01 = not supported

10 = not supported

11 = D3HOT state

When in the D3HOT state, the AC ’97 controller’s configuration space is available, but

the I/O and memory spaces are not. Additionally, interrupts are blocked.

If software attempts to write a value of 10b or 01b in to this field, the write operation

must complete normally; however, the data is discarded and no state change occurs.

Intel ® ICH7 Family Datasheet 631

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.2 AC ’97 Audio I/O Space (D30:F2)

The AC ’97 I/O space includes Native Audio Bus Master registers and Native Mixer

registers. For the ICH7, the offsets are import ant as they will determine bits 1:0 of the

TAG field (codec ID).

Audio Mixer I/O space can be accessed as a 16-bit field only since the data packet

length on

AC-link is a word. An y S/W access to the codec will be done as a 16-bit access starting

from the first active byte. In case no byte enables are active, the access will be done at

the first word of the qWord that contains the address of this request.

Table 16-2. Intel® ICH7 Audio Mixer Register Configuration (Sheet 1 of 2)

Primary Offset

(Codec ID =00) Secondary Offset

(Codec ID =01) Tertiary Offset

(Codec ID =10) NAMBAR Exposed Registers

(D30:F2)

00h 80h 100h Reset

02h 82h 102h Master Volume

04h 84h 104h Aux Out Volume

06h 86h 106h Mono Volume

08h 88h 108h Master Tone (R & L)

0Ah 8Ah 10Ah PC_BEEP Volume

0Ch 8Ch 10Ch Phone Volume

0Eh 8Eh 10Eh Mic Volume

10h 90h 110h Line In Volume

12h 92h 112h CD Volume

14h 94h 114h Video Volume

16h 96h 116h Aux In Volume

18h 98h 118h PCM Out Volume

1Ah 9Ah 11Ah Record Select

1Ch 9Ch 11Ch Record Gain

1Eh 9Eh 11Eh Record Gain Mic

20h A0h 120h General Purpose

22h A2h 122h 3D Control

24h A4h 124h AC ’97 RESERVED

26h A6h 126h Powerdown Ctrl/Stat

28h A8h 128h Extended Audio

2Ah AAh 12Ah Extended Audio Ctrl/Stat

2Ch ACh 12Ch PCM Front DAC Rate

2Eh AEh 12Eh PCM Surround DAC Rate

30h B0h 130h PCM LFE DAC Rate

32h B2h 132h PCM LR ADC Rate

34h B4h 134h MIC ADC Rate

36h B6h 136h 6Ch Vol: C, LFE

38h B8h 138h 6Ch Vol: L, R Surround

3Ah BAh 13Ah S/PDIF Control

3Ch–56h BC–D6h 13C–156h Intel RESERVED

58h D8h 158h AC ’97 Reserved

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

632 Intel ® ICH7 Family Datasheet

NOTE:

1. Software should not try to access reserved registers

2. Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of

configuration register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration

3. The tertiary offset is only available through the memory space defined by the MMBAR

The Bus Master registers are located from offset + 00h to offset + 51h and reside in the

AC ’97 controller. Accesses to these registers do not cause the cycle to be forwarded

over the AC-link to the codec. S/W could access these registers as bytes, word, DWord

or qword quantities, but reads must not cross DWord boundaries.

In the case of the split codec implementation, accesses to the different codecs are

differentiated by the controller by using address offsets 00h–7Fh for the primary codec,

address offsets 80h–FFh for the secondary codec and address offsets 100h–17Fh f or the

tertiary codec.

The Global Control (GLOB_CNT) (D30:F2:2Ch) and Global Status (GLOB_STA)

(D30:F2:30h) registers are aliased to the same global registers in the audio and

modem I/O space. Therefore a read/write to these registers in either audio or modem

I/O space affects the same physical register.

Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The six

channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their

own set of Bus Mastering registers. The following register descriptions apply to all six

channels. The register definition section titles use a generic “x_” in front of the register

to indicate that the register applies to all six channels. The naming prefix convention

used in Table 16-3 and in the register description I/O address is as follows:

PI = PCM in channel

PO = PCM out channel

MC = Mic in channel

MC2 = Mic 2 channel

PI2 = PCM in 2 channel

SP = S/PDIF out channel.

5Ah DAh 15Ah Vendor Reserved

7Ch FCh 17Ch Vendor ID1

7Eh FEh 17Eh Vendor ID2

Table 16-2. Intel® ICH7 Audio Mixer Register Configuration (Sheet 2 of 2)

Primary Offset

(Codec ID =00 ) Secondary Offset

(Codec ID =01) Tertiary Offset

(Codec ID =10) NAMBAR Exposed Registers

(D30:F2)

Intel ® ICH7 Family Datasheet 633

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

Table 16-3. Native Audio Bus Master Control Registers (Sheet 1 of 2)

Offset Mnemonic Name Default Access

00h PI_BDBAR PCM In Buffer Descriptor list Base

Address 00000000h R/W

04h PI_CIV PCM In Current Index Value 00h RO

05h PI_LVI PCM In Last Valid Index 00h R/W

06h PI_SR PCM In Status 0001h R/WC, RO

08h PI_PICB PCM In Position in Current Buffer 0000h RO

0Ah P I_PIV PCM In Prefetched Index Value 00h RO

0Bh PI_CR PCM In Control 00h R/W, R/W

(special)

10h PO_BDBAR PCM Out Buffer Descriptor list Base

Address 00000000h R/W

14h PO_CIV PCM Out Current Index Value 00h RO

15h PO_LVI PCM Out Last Valid Index 00h R/W

16h PO_SR PCM Out Status 0001h R/WC, RO

18h P O_PICB PCM In Position In Current Buffer 0000h RO

1Ah PO_PIV PCM Out Prefetched Index Value 00h RO

1Bh PO_CR PCM Out Control 00h R/W, R/W

(special)

20h MC_BDBAR Mic. In Buffer Descriptor List Base

Address 00000000h R/W

24h MC_CIV Mic. In Current Index Value 00h RO

25h MC_LVI Mic. In Last Valid Index 00h R/W

26h MC_SR Mic. In Status 0001h R/WC, RO

28h MC_PICB Mic. In Position In Current Buffer 0000h RO

2Ah MC_PIV Mic. In Prefetched Index Value 00h RO

2Bh MC_CR Mic. In Control 00h R/W, R/W

(special)

2Ch GLOB_CNT Global Control 00000000h R/W, R/W

(special)

30h GLOB_STA Global Status See register

description R/W, R/WC, RO

34h CAS Codec Access Semaphore 00h R/W (special)

40h MC2_BDBAR Mic. 2 Buffer Descriptor List Base

Address 00000000h R/W

44h MC2_CIV Mic. 2 Current Index Value 00h RO

45h MC2_LVI Mic. 2 Last Valid Index 00h R/W

46h MC2_SR Mic. 2 Status 0001h RO, R/WC

48h MC2_PICB Mic 2 Position In Current Buffer 0000h RO

4Ah MC2_PIV Mic. 2 Prefetched Index Value 00h RO

4Bh MC2_CR Mic. 2 Control 00h R/W, R/W

(special)

50h PI2_BDBAR PCM In 2 Buffer Descriptor List Base

Address 00000000h R/W

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

634 Intel ® ICH7 Family Datasheet

Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers

except the registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well

registers will not be reset by the D3HOT to D0 transition.

Core well registers and bits not reset by the D3HOT to D0 transition:

• offset 2Ch–2Fh – bits 6:0 Global Control (GLOB_CNT)

• offset 30h–33h – bits [29,15,11:10,0] Global Status (GLOB_STA)

• offset 34h – Codec Access Semaphore Register (CAS)

Resume well registers and bits will not be reset by the D3HOT to D0 transition:

• offset 30h–33h – bits [17:16] Global Status (GLOB_STA)

54h PI2_CIV PCM In 2 Current Index Value 00h RO

55h PI2_LVI PCM In 2 Last Valid Index 00h R/W

56h PI2_SR PCM In 2 Status 0001h R/WC, RO

58h PI2_PICB PCM In 2 Position in Current Buffer 0000h RO

5Ah PI2_PIV PCM In 2 Prefetched Index Value 00h RO

5Bh PI2_CR PCM In 2 Control 00h R/W, R/W

(special)

60h SPBAR S/PDIF Buffer Descriptor List Base

Address 00000000h R/W

64h SPCIV S/PDIF Current Index Value 00h RO

65h SPLVI S/PDIF Last Valid Index 00h R/W

66h SPSR S/PDIF Status 0001h R/WC, RO

68h SPPICB S/PDIF Position In Current Buffer 0000h RO

6Ah SPPIV S/PDIF Prefetched Index Value 00h RO

6Bh SPCR S/PDIF Control 00h R/W, R/W

(special)

80h SDM SData_IN Map 00h R/W, RO

Table 16-3. Native Audio Bus Master Control Register s (She et 2 of 2)

Offset Mnemonic Name Default Access

Intel ® ICH7 Family Datasheet 635

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.2.1 x_BDBAR—Buffer Descriptor Base Address Register

(Audio—D30:F2)

I/O Address: NABMBAR + 00h (PIBDBAR), Attribute: R/W

NABMBAR + 10h (POBDBAR),

NABMBAR + 20h (MCBDBAR)

MBBAR + 40h (MC2BDBAR)

MBBAR + 50h (PI2BDBAR)

MBBAR + 60h (SPBAR)

Default Value: 00000 000h Size: 32 bits

Lockable: No Power Well: Core

Software can read the register at offset 00h by performing a single 32-bit read from

address offset 00h. Reads across DWord boundaries are not supported.

16.2.2 x_CIV—Current Index Value Register (Audio—D30:F2)

I/O Address: NABMBAR + 04h (PICIV), Attribute: RO

NABMBAR + 14h (POCIV),

NABMBAR + 24h (MCCIV)

MBBAR + 44h (MC2CIV)

MBBAR + 54h (PI2CIV)

MBBAR + 64h (SPCIV)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

NOTE: Reads across DWord boundaries are not supported.

Bit Description

31:3 Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits

31:3. The data should be aligned on 8-byte boundaries. Each buffer descriptor is 8

bytes long and the l ist can contain a maximum of 32 entries.

2:0 Hardwired to 0.

Bit Description

7:5 Hardwired to 0

4:0 Current Index Value [4:0] — RO. These bits represent which buffer descriptor within

the list of 32 descriptors is currently being processed. As each descriptor is processed,

this value is incr emented. The value rolls over after it reaches 31.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

636 Intel ® ICH7 Family Datasheet

16.2.3 x_LVI—Last Valid Index Register (Audio—D30:F2)

I/O Address: NABMBAR + 05h (PILVI), Attribute: R/W

NABMBAR + 15h (POLVI),

NABMBAR + 25h (MCLVI)

MBBAR + 45h (MC2LVI)

MBBAR + 55h (PI2LVI)

MBBAR + 65h (SPLVI)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

NOTE: Reads across DWord boundaries are not supported.

16.2.4 x_SR—Status Register (Audio—D30:F2)

I/O Address: NABMBAR + 06h (PISR), Attribute: R/WC, RO

NABMBAR + 16h (POSR),

NABMBAR + 26h (MCSR)

MBBAR + 46h (MC2SR)

MBBAR + 56h (PI2SR)

MBBAR + 66h (SPSR)

Default Value: 0001h Size: 16 bits

Lockable: No Power Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

boundaries are not supported.

Bit Description

7:5 Hardwired to 0.

4:0 Last Valid Index [4:0] — R/W. This value represents the last valid descriptor in the

list. This value is updated by the software each time it prepares a new buffer and adds

it to the list.

Intel ® ICH7 Family Datasheet 637

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

Bit Description

15:5 Reserved.

FIFO Error (FIFOE) — R/WC. Software clears this bit by writing a 1 to it.

0 = No FIFO error.

1 = FIFO error occurs.

PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers don't

increment, the incoming data is not written into the FIFO, thus is lost.

POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this

case should be the last valid sample.

The Inte l® ICH7 will set the FIFO bit if the under-run or overrun occurs when there are

more valid buffers to process.

Buffer Completion Interrupt Status (BCIS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Set by the hardware after the last sample of a buffer has been processed, AND if

the Interrupt on Completion (IOC) bit is set in the command byte of the buffer

descriptor. It remains active until cleared by software.

Last Valid Buffer Completion Int errupt (LVBCI) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Last valid buffer has been processed. It remains active until cleared by software.

This bit indicates the occurrence o f the event signified by the last valid buffer

being processed. Thus this is an event status bit that can be cleared by software

once this event has been recognized. This event will cause an interrupt if the

enable bit (D30:F2:NABMBAR + 0Bh, bit 2) in the Control Register is set. The

interrupt is cleared when th e software clears this bit.

In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid

buffer has been fetched (not after transmitting it). While in the case of Receives,

this bit is set after the data for the last buffer has been written to memory.

Current Equals Last Valid (CELV) — RO.

0 = Cleared by hardware when controller exists state (i.e. , until a new value is written

to the LVI register.)

1 = Current Index is equal to the value in the Last Valid Index Register

(D30:F2:NABMBAR + 05h), and the buffer pointed to by the CIV has been

processed (i.e., after the last valid buffer has been processed). This bit is very

similar to bit 2, except this bit reflects the state rather than the event. This bit

reflects the state of the controller, and remains set until the controller exits this

state.

DMA Controlle r Halted (DCH) — RO.

0 = Running.

1 = Halted. This could happen because of the Start/Stop bit being cleared and the

DMA engines are idle, or it could happen once the controller has processed the last

valid buffer.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

638 Intel ® ICH7 Family Datasheet

16.2.5 x_PICB—Position In Current Buffer Register

(Audio—D30:F2)

I/O Address: NABMBAR + 08h (PIPICB), Attribute: RO

NABMBAR + 18h (POPICB),

NABMBAR + 28h (MCPICB)

MBBAR + 48h (MC2PICB)

MBBAR + 58h (PI2PICB)

MBBAR + 68h (SPPICB)

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 16-bit read to offset 08h. Reads across DWord boundaries are not

supported.

16.2.6 x_PIV—Prefetched Index Value Register (Audio—D30:F2)

I/O Address: NABMBAR + 0Ah (PIPIV), Attribute: RO

NABMBAR + 1Ah (POPIV),

NABMBAR + 2Ah (MCPIV)

MBBAR + 4Ah (MC2PIV)

MBBAR + 5Ah (PI2PIV)

MBBAR + 6Ah (SPPIV)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 8-bit read to offset 0Ah. R eads acro ss D Word boundaries are not

supported

Bit Description

15:0

Position In Current Buffer [15:0] — RO. These bits represent the number of

samples left to be processed in the current buffer. This means the number of samples

not yet read from memory (in the case of reads from memory) or not yet written to

memory (in the case of writes to memory), irrespective of the number of samples that

have been transmitted/received across

AC-link.

Bit Description

7:5 Hardwired to 0.

4:0 Prefetched Index Val ue [4: 0] — RO. These bi ts represent which buffer descriptor in

the list has been prefetched. The bits in this register are also modulo 32 and roll over

after they reach 31.

Intel ® ICH7 Family Datasheet 639

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.2.7 x_CR—Control Register (Audio—D30:F2)

I/O Address: NABMBAR + 0Bh (PICR), Attribute: R/W, R/W (special)

NABMBAR + 1Bh (POCR),

NABMBAR + 2Bh (MCCR)

MBBAR + 4Bh (MC2CR)

MBBAR + 5Bh (PI2CR)

MBBAR + 6Bh (SPCR)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Software can read the registers at the offset s 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 8-bit read to offset 0Bh. Reads across DWord boundaries are not

supported.

Bit Description

7:5 Reserved.

Interrupt on Completion Enable (IOCE) — R/W. This bit controls whether or not an

interrupt occurs when a buffer completes with the IOC bit set in its descriptor.

0 = Disable. Interrupt will not occur.

1 = Enable.

FIFO Error Interrupt Enable (FEIE) — R/W. This bit controls whether the

occurrence of a FIFO error will cause an interrupt or not.

0 = Disable. Bit 4 in the Status register will be set, but the interrupt will not occur.

1 = Enable. Interrupt will occur.

Last Valid Buffer Interrupt Enable (LVBIE) — R/W. This bit controls whether the

completion of the last valid buffer will cause an interrupt or not.

0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.

1 = Enable.

Reset Registers (RR) — R/W (special ).

0 = Removes reset condition.

1 = Contents of all Bus master related registers to be rese t, except the interrupt

enable bits (bit 4,3,2 of this register). Software needs to set this bit but need not

clear it sin ce the bit is self cl earing. This bit m us t be s e t o nl y wh en t he Run/Pause

bit (D30:F2:2Bh, bit 0) is cleared. Setting it when the Run bit is set will cause

undefined consequences.

Run/Pause Bus Master (RPBM) — R/W.

0 = Pause bus master operation. This results in all state information being retained

(i.e., master mode operation can be stopped and then resumed).

1 = Run. Bus master operation starts.

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

640 Intel ® ICH7 Family Datasheet

16.2.8 GLOB_CNT—Global Control Register (Audio—D30:F2)

I/O Address: NABMBAR + 2Ch Attribute: R/W, R/W (special)

Default Value: 00000000h Size: 32 bits

Lockable: No Power Well: Core

Bit Description

31:30

S/PDIF Slot Map (SSM) — R/W. If the run/pause bus master bit (bit 0 of offset 2Bh)

is set, then the value in these bits indicate which slots S/PDIF data is transmitted on.

Software must ensure that the programming here does not conflict with the PCM

channels being used. If there is a conflict, unpredictable behavior will result — the

hardware will not check for a conflict.

00 = Reserved

01 = Slots 7 and 8

10 = Slots 6 and 9

11 = Slots 10 and 11

29:24 Reserved.

23:22

PCM Out Mode (POM) — R/W. Enables the PCM out channel to use 1 6- or 20-bit audio

on PCM out. This does not affect the microphone of S/PDIF DMA. When greater than

16-bit audio is used, the data structures are aligned as 32-bits per sample, with the

highest order bits representing the data, and the lower order bits as don’t care.

00 = 16 bit audio (default)

01 = 20 bit audio

10 = Reserved. If set, indeterminate behavior will result.

11 = Reserved. If set, indeterminate behavior will result.

21:20

PCM 4/6 Enable — R/W. This field configures PCM Output for 2-, 4- or 6-channel

mode.

00 = 2-channel mode (default)

01 = 4-channel mode

10 = 6-channel mode

11 = Reserved

19:7 Reserved.

ACZ_SDIN2 Interrupt Enable — R/W.

0 = Disable.

1 = Enable an interrupt to occur when the codec on the ACZ_SDIN2 causes a resume

event on the AC-link.

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

ACZ_SDIN1 Interrupt Enable — R/W.

0 = Disable.

1 = Enable an interrupt to occur when the codec on the ACZ_SDIN1 causes a resume

event on the AC-link.

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

ACZ_SDIN0 Interrupt Enable — R/W.

0 = Disable.

1 = Enable an interrupt to occur when the codec on ACZ_SDIN0 causes a resume event

on the AC-link.

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

Intel ® ICH7 Family Datasheet 641

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

NOTE: Reads across DWord boundaries are not supported.

AC-LINK Shut Off (LSO) — R/W.

0 = Normal operation.

1 = Controller disables all outputs which will be pulled low by internal pull down

resistors.

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

AC ’97 Warm Reset — R/W (special).

0 = Normal operation.

1 = W riting a 1 to this bit causes a wa rm reset to occur on the AC-link. The warm reset

will awaken a suspended codec without clearing its internal registers. If software

attempts to perform a warm reset while bit_clk is running, the write will be ignored

and the bit will not change. This bit is self-clearing (it remains set until the reset

completes and bit_clk is seen on the AC-link, after which it clears itself).

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

AC ’97 Cold Reset# — R/W.

0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry.

All data in the controller and the code c will be los t. Softw are needs to cl ear this bit

no sooner than the minimum number of ms have elapsed.

1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1.

The value of this bit is retained after suspends; h ence, if this bit is set to a 1 prior

to suspending, a cold rese t is not generated automatically upon resuming.

NOTE: This bit is in the core well and is not affected by AC ‘97 Audio Function D3HOT to

D0 reset.

GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of

any GPI causes an interrupt.

0 = Bit 0 of the Global Status register is set, but no interrupt is generated.

1 = The change in value of a GPI causes an interrupt and sets bit 0 of the Global Status

NOTE: This bit is not affected by AC ‘97 Audio Function D3HOT to D0 reset.

Bit Description

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

642 Intel ® ICH7 Family Datasheet

16.2.9 GLOB_STA—Global Status Register (Audio—D30:F2)

I/O Address: NABMBAR + 30h Attribute: RO, R/W, R/WC

Default Value: 00x0xxx01110000000000xxxxx00xxxb Size: 32 bits

Lockable: No Power Well: Core

Bit Description

31:30 Reserved.

ACZ_SDIN2 Resume Interrupt (S2RI) — R/WC. This bit indicates a resume event

occurred on ACZ_SDIN2. Software clears this bit by writing a 1 to it.

0 = Resume event did Not occur.

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN2 Codec Ready (S2CR) — RO. R eflects the state of the codec ready bit on

ACZ_SDIN2. Bus masters ignore the condition of the codec ready bits, so software

must check this bit before starting the bus masters. Once the codec is “ready”, it must

not go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Bit Clock Stopped (BCS) — RO. This bit indicates that the bit clock is not running.

0 = Transition is found on BIT_CLK.

1 = Intel® ICH7 detected that there has been no transition on BIT_CLK for four

consecutive PCI clocks.

26 S/PDIF Interrupt (SPINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = S/PDIF out channel interrupt status bits have been set.

25 PCM In 2 Interrupt (P2INT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM In 2 channel status bits have been set.

24 Microphone 2 In Interrupt (M2INT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the Mic in channel interrupts status bits has been set.

23:22

Sample Capabilities — RO . This field indicates the capability to support greater than

16-bit audio.

00 = Reserved

01 = 16 and 20-bit Audio supported (ICH7 value)

10 = Reserved

11 = Reserved

21:20 Multichannel Capabilitie s— RO. This field indicates the capability to support more 4

and 6 channels on PCM Out.

19:18 Reserved.

MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well

and maintains context across power states (except G3). The bit has no hardware

function. It is used by soft ware in conjun ct ion with the AD3 bit to coordinate th e e nt ry

of the two codecs into D3 state.

NOTE: This bit is not affected by D3HOT to D0 Reset.

Intel ® ICH7 Family Datasheet 643

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and

maintains context across power states (except G3). The bit has no hardware function.

It is used by softw are in conjunction with th e MD3 bit to coordinate the en try of the two

codecs into D3 state.

NOTE: This bit is not affected by D3HOT to D0 Reset.

Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read

completions.

0 = A codec read completes normally.

1 = A codec read results in a time -out. The bit remains set until being cleared by

software writing a 1 to the bit location.

NOTE: This bit is not affected by D3HOT to D0 Reset.

14 Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.

13 Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.

12 Bit 1 of slot 12 — RO. Display bit 1 of the most recent slot 12.

ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume

event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.

0 = Resume event did Not occur

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume

event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.

0 = Resume event did Not occur

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in

ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software

must check this bit befo re st arting th e bus master s. Once the codec is “ready”, it must

not go “not ready” spontaneously.

0 = No t Ready.

1 = Ready.

ACZ_SDIN0 Codec Ready (S0CR) — RO . Reflects the state of the codec ready bit in

ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software

must check this bit befo re st arting th e bus master s. Once the codec is “ready”, it must

not go “not ready” spontaneously.

0 = No t Ready.

1 = Ready.

7Microphone In Interrupt (MINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the Mic in channel interrupts status bits has been set.

6PCM Out Interrupt (POINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM out channel interrupts status bits has been set.

5PCM In Interru pt (PIINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM in channel interrupts status bits has been set.

4:3 Reserved

Bit Description

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

644 Intel ® ICH7 Family Datasheet

NOTE: Reads across DWord boundaries are not supported.

16.2.10 CAS—Codec Access Semaphore Register (Audio—D30:F2)

I/O Address: NABMBAR + 34h Attribute: R/W (special)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

NOTE: Reads across DWord boundaries are not supported.

2Modem Out In te rru pt (MOINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the modem out chan nel interrupts status bits has been s et.

1Modem In Interrupt (MIINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the modem in channel interrupts status bits has been set.

GPI Status Change Interrupt (GSCI) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set.

This indicates th at one of the GPI’ s has changed state, and that the new values are

available in slot 12.

This bit is not affected by AC ‘97 Audio Function D3HOT to D0 Reset.

Bit Description

7:1 Reserved.

Codec Access Semaphore (CAS) — R/W (special). This bit is read by software to

check whether a codec access is currently in progress.

0 = No access in progress.

1 = The act of reading this register sets this bit to 1. The driver that read this bit can

then perform an I/O access. Once the access is completed, hardware automatically

clears this bit.

Intel ® ICH7 Family Datasheet 645

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

16.2.11 SDM—SDATA_IN Map Register (Audio—D30:F2)

I/O Address: NABMBAR + 80h Attribute: R/W, RO

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

NOTE: Reads across DWord boundaries are not supported.

Bit Description

7:6

PCM In 2, Microphone In 2 Data In Line (DI2L)— R/W. When the SE bit is set,

these bits in dicates whic h ACZ_SDI N line shoul d be used by the hardw are for decoding

the input slots for PCM In 2 and Microphone In 2. When the SE bit is cl eared, the value

of these bits are irrelevant, and PCM In 2 and Mic In 2 DMA engines are not available.

00 = ACZ_SDIN0

01 = ACZ_SDIN1

10 = ACZ_SDIN2

11 = Reserved

5:4

PCM In 1, Microphone In 1 Data In Line (DI1L)— R/W. When the SE bit is set,

these bits in dicates whic h ACZ_SDI N line shoul d be used by the hardw are for decoding

the input slots for PCM In 1 and Microphone In 1. When the SE bit is cl eared, the value

of these bits are ir relevant, and the PCM In 1 and Mic In 1 engines use the OR’d

ACZ_SDIN lines.

00 = ACZ_SDIN0

01 = ACZ_SDIN1

10 = ACZ_SDIN2

11 = Reserved

Steer Enable (SE ) — R/W. When set, the ACZ_SDIN lines are treated separately and

not OR’d together before being sent to the DMA engines. When cleared, the ACZ_SDIN

lines are OR’d together, and the “Microphone In 2” and “PCM In 2” DMA engines are not

available.

2 Reserved — RO.

1:0

Last Codec Read Data Input (LDI) — RO. When a codec register is read, this

indicates which ACZ_SDIN the read data returned on. Software can use this to

determine how the codecs are mapped. The values are:

00 = ACZ_SDIN0

01 = ACZ_SDIN1

10 = ACZ_SDIN2

11 = Reserved

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)

646 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 647

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17 AC ’97 Modem Controller

Registers (D30:F3) (Desktop

and Mobile Only)

Note: AC ‘97 is not supported on ICH7-U Ultra Mobile.

17.1 AC ’97 Modem PCI Configuration Space (D30:F3)

Note: Registers that are not shown should be treated as Reserved.

Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers

except the following BIOS programmed registers as BIOS ma y not be invoked following

the D3-to-D0 transition. All resume well registers will not be reset by the D3HOT to D0

transition.

Core well registers not reset by the D3HOT to D0 transition:

• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)

• offset 2Eh–2Fh – Subsystem ID (SID)

Resume well registers will not be reset by the D3HOT to D0 transition:

• offset 54h–55h – Power Management Control and Status (PCS)

Table 17-1. AC ‘97 Modem PCI Register Address Map (Modem—D30:F3)

Offset Mnemonic Register Default Access

00h–01h VID Vendor Identification 8086 RO

02h–03h DID Device Identification See register

description RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0290h R/WC, RO

08h RID Revision Identification See register

description RO

09h PI Programming Interface 00h R O

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 07h RO

0Eh HEADTYP Header Type 00h RO

10h–13h MMBAR Modem Mixer Base Address 00000001h R/W, RO

14h–17h MBAR Modem Base Address 00000001h R/W, RO

2Ch–2Dh S VID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAP_PTR Capabilitie s Pointer 50h RO

3Ch INT_LN Interrupt Line 00h R/W

3Dh INT_PN Interrupt Pin See register

description RO

50h–51h PID PCI Power Manage me nt Capabili t y ID 0001h RO

52h–53h PC Power Management Capabilities C9C2h RO

54h–55h PCS Power Management Control and

Status 0000h R/W, R/WC

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

648 Intel ® ICH7 Family Datasheet

17.1.1 VID—Vendor Identification Register (Modem—D30:F3)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086 Size: 16 Bits

Lockable: No Power Well: Core

17.1.2 DID—Device Identification Register (Modem—D30:F3)

Address Offset: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 Bits

Lockable: No Power Well: Core

17.1.3 PCICMD—PCI Command Register (Modem—D30:F3)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification for

complete details on each bit.

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Int el.

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigne d to the Intel® ICH7 AC ‘97 Modem

controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

for the value of the Device ID Register.

Bit Description

15:11 Reserved. Read 0.

Interrupt Disable (ID)— R/W.

0 = The INTx# signals may be asserted and MSIs may be generated.

1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate

MSIs.

9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.

8 SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.

7 Wait Cycle Contr o l (WC C ) — RO. Not implemented. Hardwired to 0.

6 Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.

5 VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.

4 Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.

3 Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.

Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering

capabilities.

0 = Disable

1 = Enable

1Memory Space Enable (MSE) — RO. Hardwired to 0, AC ‘97 does not respond to

memory accesses.

I/O Space Enable (IOSE) — R/W. This bit control s access to the I/O space regis ters.

0 = Disable access. (default = 0).

1 = Enable access to I/O space. The Native PCI Mode Base Address register should be

programmed prior to setting this bit.

Intel ® ICH7 Family Datasheet 649

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.1.4 PCISTS—PCI Status Register (Modem—D30:F3)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0290h Size: 16 bits

Lockable: No P ower Well: Core

PCISTS is a 16-bit status register. R efer to the PCI Local Bus Specification for complete

details on each bit.

Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to

the bit has no effect.

Bit Description

15 Detected Parity Error (DPE) — RO. Not impleme nted. Hardwired to 0.

14 Signaled System Error (SSE) —RO. Not implemented. Hardwired to 0.

13 Master Abort Status (MAS) — R/WC.

0 = Master abort Not generated by bus master AC ‘97 function.

1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.

12 Reserved. Read a s 0.

11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the ICH7's DEVSEL#

timing parameter. These read only bits indicate the ICH7's DEVSEL# timing when

performing a positive decode.

8 Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.

7Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the

ICH7 as a target is capable of fast back-to-back transactions.

6 User Definable Features (UDF) — RO. Not implemente d. Hardwired to 0.

5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Indicate s th at th e c ontroller contains a capabilities

pointer list. The first item is pointed to by looking at configuration offset 34h.

3Interrupt Status (INTS) — RO.

0 = This bit is 0 after the interrupt is cleared.

1 = This bit is 1 when the INTx# is asserted.

2:0 Reserved

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

650 Intel ® ICH7 Family Datasheet

17.1.5 RID—Revision Identification Register (Modem—D30:F3)

Address Offset: 08h Attribute: RO

Default Value: See bit description Size: 8 Bits

Lockable: No Power Well: Core

17.1.6 PI—Programming Interface Register (Modem—D30:F3)

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

17.1.7 SCC—Sub Class Code Register (Modem—D30:F3)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

Lockable: No Power Well: Core

17.1.8 BCC—Base Class Code Register (Modem—D30:F3)

Address Offset: 0Bh Attribute: RO

Default Value: 07h Size: 8 bits

Lockable: No Power Well: Core

17.1.9 HEADTYP—Header Type Register (Modem—D30:F3)

Address Offset: 0Eh Attribute: RO

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Bit Description

7:0 Revision ID — RO. Re fer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification

Update for the value of the Revision ID Register.

Bit Description

7:0 Programming Interface — RO.

Bit Description

7:0 Sub Class Code — RO.

03h = Generic Modem.

Bit Description

7:0 Base Class Code — RO.

07h = Simple Communications controller.

Bit Description

7:0 Header Type — RO.

Intel ® ICH7 Family Datasheet 651

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.1.10 MMBAR—Modem Mixer Base Address Register

(Modem—D30:F3)

Address Offset: 10–13h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Native PCI Mode Modem uses PCI Base Address register #1 to request a

contiguous block of I/O space that is to be used for the Modem Mixer software

interface. The mixer requires 256 bytes of I/O space. All accesses to the mixer registers

are forwarded over the AC-link to the codec where the registers reside.

In the case of the split codec implementation accesses to the different codecs are

differentiated by the controller by using address offsets 00h–7Fh for the primary codec

and address offsets 80h–FEh for the secondary codec.

17.1.11 MBAR—Modem Base Address Register (Modem—D30:F3)

Address Offset: 14h–17h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Modem function uses PCI Base Address register #1 to request a contiguous block

of I/O space that is to be used for the Modem software interface. The Modem Bus

Mastering register space requires 128 bytes of I/O space. All Modem registers reside in

the controller, therefore cycles are not forwarded over the AC-link to the codec.

Bit Description

31:16 Hardwired to 0’s.

15:8

Base Address — R/W. These bits are used in the I/O space decode of the Modem

interface registers. The number of upper bits that a device actually implements

depends on how much of the address space the device will respond to. For the AC ‘97

Modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. This

configuration yields a maximum I/O block size of 256 bytes for this base address.

7:1 Reserved. Read as 0

0 R esource Type Indicator (RTE) — RO. Hardwired to 1indicati ng a request for I/O space.

Bit Description

31:16 Hardwired to 0’s.

15:7

Base Address — R/W. These bits are used in the I/O space decode of the Modem

interface registers. The number of upper bits that a device actually implements

depends on how much of the address space the device will respond to. For the AC ‘97

Modem, the upper 16 bits are hardwired to 0, while bits 15:7 are programmable. This

configuration yields a maximum I/O block size of 128 bytes for this base address.

6:1 Reserved. Read as 0

0Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O

space.

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

652 Intel ® ICH7 Family Datasheet

17.1.12 SVID—Subsystem Vendor Identification Register

(Modem—D30:F3)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

The SVID register, in combination with the Subsystem ID register, enable the operating

environment to distinguish one audio subsystem from the other(s). This register is

implemented as write-once register. Once a value is written to it, the value can be read

back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

17.1.13 SID—Subsystem Identification Register (Modem—D30:F3)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

The SID register, in combination with the Subsystem Vendor ID register make it

possible for the operating environment to distinguish one audio subsystem from

another. This register is implemented as write-once register. Once a value is written to

it, the value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

17.1.14 CAP_PTR—Capabilities Pointer Register (Modem—D30:F3)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

Lockable: No Power Well: Core

This register indicates the offset for the capability pointer.

Bit Description

15:0 Subsystem Vendor ID — R/WO .

Bit Description

15:0 Subsystem ID — R/WO.

Bit Description

7:0 Capabilities P oin ter (CAP_PTR) — RO . This field indicates that the first capability pointer

offset is offset 50h

Intel ® ICH7 Family Datasheet 653

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.1.15 INT_LN—Interrupt Line Register (Modem—D30:F3)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.

17.1.16 INT_PIN—Interrupt Pin Register (Modem—D30:F3)

Address Offset: 3Dh Attribute: RO

Default Value: See description Size: 8 bits

Lockable: No P ower Well: Core

This register indicates which PCI interrupt pin is used for the AC ’97 modem interrupt.

The AC ’97 interrupt is internally OR’d to the interrupt controller with the PIRQB#

signal.

17.1.17 PID—PCI Power Management Capability Identification

Address Offset: 50h Attribute: RO

Default Value: 0001h Size: 1 6 bits

Lockable: No Power Well: Core

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not used by the Intel® ICH7. It is used to

communicate to software the interrupt line that the interrupt pin is connected to.

Bit Description

7:3 Reserved

2:0 Interrupt Pin (INT_PN) — RO. This reflects the value of D30IP. AMIP in chipset

configuration space.

Bit Description

15:8 Next Capability (NEXT ) — RO. This field indicates that this is the last item in the list.

7:0 Capability ID (CAP) — RO. This field indicates that this pointer is a message signaled

interrupt capability.

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

654 Intel ® ICH7 Family Datasheet

17.1.18 PC—Power Management Capabilities Register

(Modem—D30:F3)

Address Offset: 52h Attribute: RO

Default Value: C9C2h Size: 16 bits

Lockable: No Power Well: Core

17.1.19 PCS—Power Management Control and Status Regi ster

(Modem—D30:F3)

Address Offset: 54h Attribute: R/W, R/WC

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Resume

This register is not affected by the D3HOT to D0 transition.

Bit Description

15:11 PME Support — RO. This field indicates PME# can be generated from all D states.

10:9 Reserved.

8:6 Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current

required when in the D3COLD state.

5Device Specific Initialization (DSI) — RO. This bit indicates that no device-spec ific

initialization is required.

4 Reserved — RO.

3PME Clock (PMEC) — RO. This bit in dicates that PCI clock is not required to generate

PME#.

2:0 Version (VS) — RO. This field indicates support for Revision 1.1 of the PCI Power

Management Sp ecification.

Bit Description

PME Status (PMES) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set when the AC ’97 cont roll er would normally assert the PME# signal

independent of the state of the PME_En bit. This bit resides in the resume well.

14:9 Reserved — RO.

PME Enable (PMEE) — R/W.

0 = Disable.

1 = Enable. When set, and if corresponding PMES is also set, the AC '97 controller sets

the AC97_STS bit in the GPE0_STS register.

7:2 Reserved — RO.

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the AC ’97 controller and to set a new power state. The values are:

00 = D0 state

01 = not supported

10 = not supported

11 = D3HOT state

When in the D3HOT state, the AC ’97 controller’s configuration space is available, but

the I/O and memory spaces are not. Additionally, interrupts are blocked.

If software attempts to write a value of 10b or 01b in to this field, the write operation

must complete normally; however, the data is discarded and no state change occurs.

Intel ® ICH7 Family Datasheet 655

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.2 AC ’97 Modem I/O Space (D30:F3)

In the case of the split codec implementation accesses to the modem mixer registers in

different codecs are differentiated by the controller by using address offsets 00h–7Fh

for the primary codec and address offsets 80h–FEh for the secondary codec. Table 17-2

shows the register addresses for the modem mixer registers.

NOTES:

1. Registers in italics are for functions not supported by the ICH7

2. Software should not try to access reserved registers

3. The ICH7 supports a modem codec connected to ACZ_SDIN[2:0], as long as the Codec ID

is 00 or 01. However, the ICH7 does not support more than one modem codec.

The Global Control (GLOB_CNT) and Global Status (GLO B_STA) registers are aliased to

the same global registers in the audio and modem I/O space. Theref ore a read/write to

these registers in either audio or modem I/O space affects the same physical register.

Software could access these registers as bytes, word, DWord quantities, but reads

must not cross DWord boundaries.

These registers exist in I/O space and reside in the AC ’97 controller. The two channels,

Modem in and Modem out, each have their own set of Bus Mastering registers. The

following register descriptions apply to both channels. The naming prefix convention

used is as follows:

MI = Modem in channel

MO = Modem out channel

Table 17-2. Intel® ICH7 Modem Mixer Register Configuration

Primary Secondary Name

00h:38h 80h:B8h Intel RESERVED

3Ch BCh Extended Modem ID

3Eh B Eh Extended Modem Stat/Ctrl

40h C0h Line 1 DAC/ADC Rate

42h C2h Line 2 DAC/ADC Rate

44h C4h Handset DAC/ADC Rate

46h C6h Line 1 DAC/ADC Level Mute

48h C8h Line 2 DAC/ADC Level Mute

4Ah CAh Handset DAC/ADC Level Mute

4Ch CCh GPIO Pin Config

4Eh CEh GPIO Polarit y/Type

50h D0h GPIO Pin Sticky

52h D2h GPIO Pin Wake Up

54h D4h GPIO Pin Status

56h D6h Misc. Modem AFE Stat/Ctrl

58h D8h AC ’97 Reserved

5Ah DAh Vendor Reserved

7Ch F Ch Vendor ID1

7Eh FEh Vendor ID2

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

656 Intel ® ICH7 Family Datasheet

NOTE:

1. MI = Modem in channel; MO = Modem out channel

Note: Internal reset as a result of D3HOT to D0 transition will reset all the core well registers

except the registers shared with the AC ’97 audio controller (GCR, GSR, CASR). All

resume well registers will not be reset by the D3HOT to D0 transition.

Core well registers and bits not reset by the D3HOT to D0 transition:

• offset 3Ch–3Fh – bits [6:0] Global Control (GLOB_CNT)

• offset 40h–43h – bits [29,15,11:10] Global Status (GLOB_STA)

• offset 44h – Codec Access Semaphore Register (CAS)

Resume well registers and bits will not be reset by the D3HOT to D0 transition:

• offset 40h–43h – bits [17:16] Global Status (GLOB_STA)

Table 17-3. Modem Registers

Offset Mnemonic Name Default Access

00h–03h MI_BDBAR Modem In Buffer Descriptor List Base

Address 00000000h R/W

04h MI_CIV Modem In Current Index Value 00h RO

05h MI_LVI Modem In Last Valid Index 00h R/W

06h–07h MI_SR Modem In Status 0001h R/WC, RO

08h–09h MI_PICB Modem In Position In Current Buffer 0000h RO

0Ah MI_PIV Modem In Prefetch Index Value 00h RO

0Bh MI_CR Modem I n Control 00h R/W,

R/W

(special)

10h–13h MO_BDBAR Modem Out Buffer Descriptor List Base

Address 00000000h R/W

14h MO_CIV Modem Out Current Index Value 00h RO

15h MO_LVI Modem Out Last Valid 00h R/W

16h–17h MO_SR Modem Out Status 0001h R/WC, RO

18h–19h MI_PICB Modem In Position In Current Buffer 0000h RO

1Ah MO_PIV Modem Out Prefetched Index 00h RO

1Bh MO_CR Modem Out Control 00h R/W,

R/W

(special)

3Ch–3Fh GLOB_CNT Global Control 00000000h R/W,

R/W

(special)

40h–43h GLOB_STA Global Status 00300000h RO, R/W,

R/WC

44h CAS Codec Access Semaphore 00h R/W

(special)

Intel ® ICH7 Family Datasheet 657

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.2.1 x_BDBAR—Buffer Descriptor List Base Address Register

(Modem—D30:F3)

I/O Address: MBAR + 00h (MIBDBAR), Attribute: R/W

MBAR + 10h (MOBDBAR)

Default Value: 00000 000h S ize: 32bits

Lockable: No P ower Well: Core

Software can read the register at offset 00h by performing a single, 32-bit read from

address offset 00h. Reads across DWord boundaries are not supported.

17.2.2 x_CIV—Current Index Value Register (Modem—D30:F3)

I/O Address: MBAR + 04h (MICIV), Attribute: RO

MBAR + 14h (MOCIV),

Default Value: 00h Size: 8bits

Lockable: No P ower Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

boundaries are not supported.

17.2.3 x_LVI—Last Valid Index Register (Modem—D30:F3)

I/O Address: MBAR + 05h (MILVI), Attribute: R/W

MBAR + 15h (MOLVI)

Default Value: 00h Power Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

boundaries are not supported.

Bit Description

31:3 Buffer Descriptor List Base Address [31:3] — R/W. These bits represent address

bits 31:3. The entries should be aligned on 8-byte boundaries.

2:0 Hardwired to 0.

Bit Description

7:5 Hardwired to 0.

4:0 Current Index Value [4:0] — RO. These bits represent which buffer descriptor

within the li st of 16 descriptors is being processed currently. As each descriptor is

processed, this value is incremented.

Bit Description

7:5 Hardwired to 0

4:0 Last Valid Index [4:0] — R/W. These bits indicate the last valid descriptor in the list.

This value is updated by the software as it prepares new buffers and adds to the list.

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

658 Intel ® ICH7 Family Datasheet

17.2.4 x_SR—Status Register (Modem—D30:F3)

I/O Address: MBAR + 06h (MISR), Attribute: R/WC, RO

MBAR + 16h (MOSR)

Default Value: 0001h Size: 16 bits

Lockable: No Power Well: Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by

performing a single, 32-bit read from address offset 04h. Software can also read this

boundaries are not supported.

Bit Description

15:5 Reserved

FIFO Error (FIFOE) — R/WC.

0 = So ft ware clears this bit by writ ing a 1 to it.

1 = FIFO error occurs.

Modem in: FIFO error indicates a FIFO overrun. The FIFO pointers don't increment,

the incoming data is not written into the FIFO, thereby being lost.

Modem out: FIFO error indicates a FIFO underrun. The sample transmitted in this

case should be the last valid sample.

The Intel® ICH7 will set the FIFOE bit if the under-run or overrun occurs when there

are more valid buffers to process.

Buffer Completion Interrupt Stat u s (BC IS) — R/WC.

0 = So ft ware clears this bit by writ ing a 1 to it.

1 = Set by the hardware after the last sample of a buffer has been processed, AND if

the Interrupt on Completion (IOC) bit is set in the command byte of the buffer

descriptor. Remains active until software clears bit.

Last Valid Buffer Completion Interrupt (LVBCI) — R/WC.

0 = So ft ware clears this bit by writ ing a 1 to it.

1 = Set by hardware when last valid buffer ha s been processed. It remains active until

cleared by software. This bi t in dicate s the occu rrenc e of the ev ent signifi ed by the

last valid buffer being processed. Thus, this is an event status bit that can be

cleared by software once this event has been recogni zed. This event will cau se an

interrupt if the enable bit in the Control Register is set. The interrupt is cleared

when the software clears this bit.

In the case of transmits (PCM out, Modem out) this bit is set, after th e last valid

buffer has been fetched (not after transmitting it). While in the case of Receives,

this bit is set after the data for the last buffer has been written to memory.

Current Equals Last Valid (CELV) — RO.

0 = Hardware clears when controller exists state (i.e., until a new value is written to

the LVI register).

1 = Current Index is equal to the v alue in the Last Valid Index Regist er, AND the buffer

pointed to by the CIV has been processed (i.e., after the last valid buffer has been

processed). This bit is very similar to bit 2, except, this bit reflects the state rather

than the event. This bit reflects the state of the controller, and remains set until

the controller exits this state.

DMA Controll er H a lt ed (DCH) — RO.

0 = Running.

1 = Halted. This could happen because of the Start/Stop bit being cleared and the DMA

engines are idle, or it could happen once the controller has processe d the last v alid

buffer.

Intel ® ICH7 Family Datasheet 659

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.2.5 x_PICB—Position in Current Buffer Register

(Modem—D30:F3)

I/O Address: MBAR + 08h (MIPICB), Attribute: RO

MBAR + 18h (MOPICB),

Default Value: 0000h Size: 16 bits

Lockable: No Power Well: Core

Software can read the registers at the offset s 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 16-bit read to offset 08h. Reads across DWord boundaries are not

supported.

17.2.6 x_PIV—Prefetch Index Value Register

(Modem—D30:F3)

I/O Address: MBAR + 0Ah (MIPIV), Attribute: RO

MBAR + 1Ah (MOPIV)

Default Value: 00h Size: 8 bits

Lockable: No P ower Well: Core

Software can read the registers at the offset s 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 8-bit read to offset 0Ah. Reads across DWord boundaries are not

supported.

Bit Description

15:0 Position In Current Buffer[15:0] — RO. These bits represe nt the number of

samples left to be processed in the current buffer.

Bit Description

7:5 Hardwired to 0

4:0 Prefetched Index Value [4:0] — RO. Thes e bits represent wh ich buffer descriptor in

the list has been prefetched.

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

660 Intel ® ICH7 Family Datasheet

17.2.7 x_CR—Control Register (Modem—D30:F3)

I/O Address: MBAR + 0Bh (MICR), Attribute: R/W, R/W (special)

MBAR + 1Bh (MOCR)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit

read from the address offset 08h. Software can also read this register individually by

doing a single, 8-bit read to offset 0Bh. Reads across DWord boundaries are not

supported.

Bit Description

7:5 Reserved

Interrupt on Completion Enable (IOCE) — R/ W. This bit controls whether or not an

interrupt occ urs when a buffer completes with the IOC bit set in its descriptor.

0 = Disable

1 = En able

FIFO Error Interrupt Enable (FEIE) — R/W. This bit controls whether the

occurrence of a FIFO error will cause an interrupt or not.

0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur.

1 = Enable. Interrupt will occur

Last Valid Buffer Interrupt Enable (LVBIE) — R/W. This bit controls whether the

completion of the last valid buffer will cause an interrupt or not.

0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.

1 = En able

Reset Registers (RR) — R/W (special).

0 = Removes reset condition.

1 = Contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of

this register). Software needs to set this bit. It must be set only when the Run/

Pause bit is cleared. Setting it when the Run bit is set will cause undefined

consequences. This bit is self-clearing (software needs not clear it).

Run/Pause Bus Master (RPBM) — R/W.

0 = Pause bus master operation. This results in all state information being retained

(i.e., master mode operation can be stopped and then resumed).

1 = Run. Bus master operation starts.

Intel ® ICH7 Family Datasheet 661

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

17.2.8 GLOB_CNT—Global Control Register (Modem—D30:F3)

I/O Address: MBAR + 3Ch Attribute: R/W, R/W (special)

Default Value: 00000 000h S ize: 32 bits

Lockable: No Power Well: Core

Note: R eads across D Word boundaries are not supported.

Bit Description

31:5 Reserved.

ACZ_SDIN2 Interrupt Enab l e (S2RE) — R/W.

0 = Disable.

1 = Enable an interrupt to occur when the codec on the ACZ_SD IN2 causes a resume

event on the AC-link.

ACZ_SDIN1 Resume Interrupt Enable (S1RE) — R/W.

0 = Disable.

1 = Enable an interrupt to occur when the codec on the ACZ_SD IN1 causes a resume

event on the AC-link.

ACZ_SDIN0 Resume Interrupt Enable (S0RE) — R/W.

0 = Disable.

1 = Enable an interr upt to occur when the codec on ACZ_SDIN0 causes a resume

event on the AC-link.

AC-LINK Shut Off (LSO) — R/W.

0 = Normal operation.

1 = Controller disables all outputs which will be pulled low by internal pull down

resistors.

AC ’97 Warm Reset — R/W (special).

0 = Normal operation.

1 = Writi ng a 1 to this bit causes a war m reset to occur on the AC -link. The warm res et

will awaken a suspended codec without clearing its internal registers. If software

attempts to perform a warm reset while bit_clk is running, the write will be

ignored and the bit will not change. This bit is self -clear ing (it remains s et until the

reset completes and bit_clk is seen on the AC-link, after which it clears itself).

AC ’97 Cold Reset# — R/W.

0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry.

All data in the controller and the codec will be lost. Software needs to clear this bit

no sooner than the minimum number of ms have elapsed.

1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1.

The valu e of th i s bit is retained after suspen ds ; hen c e, if t his bi t i s s e t t o a 1 prior

to suspending, a cold reset is not generated automatically upon resuming.

NOTE: This bit is in the Core well.

GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of

any GPI causes an interrupt.

0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.

1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global

Status Register.

NOTE: This bit is cleared by the AC ‘97 Modem function D3HOT to D0 reset.

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

662 Intel ® ICH7 Family Datasheet

17.2.9 GLOB_STA—Global Status Register (Modem—D30:F3)

I/O Address: MBAR + 40h Attribute: RO, R/W, R/WC

Default Value: 00300000h Size: 32 bits

Lockable: No Power Well: Core

Bit Description

31:30 Reserved.

ACZ_SDIN2 Resume Interrupt (S2RI) — R/WC. This bit indicates a resume event

occurred on ACZ_SDIN2.

0 = Software clears this bit by writing a 1 to it.

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN2 Codec Ready (S2C R) — RO. This bit reflects the state of the codec

ready bit on ACZ_SDIN2. Bus masters ignore the condition of the codec ready bits, so

software mus t check this bit before s tarting the bus masters. Once the codec is “ ready”,

it must not go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Bit Clock Stopped (BCS) — RO. This bit indicates that the bit clock is not running.

0 = Transition is found on BIT_CLK.

1 = Intel® ICH7 detects that there has been no transition on BIT_CLK for four

consecutive PCI clocks.

26 S/PDIF* Interrupt (SPINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = S/PDIF out channel interrupt status bits have been set.

25 PCM In 2 Interrupt (P2INT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM In 2 channel status bits have been set.

24 Microphone 2 In Interrupt (M2I NT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the Mic in channel interrupts status bits has been set.

23:22

Sample Capabilities — RO. This field indicates the capability to support greater than

16-bit audio.

00 = Reserved

01 = 16 and 20-bit Audio supported (ICH7 value)

10 = Reserved

11 = Reserved

21:20 Multichannel Capabilities — RO. This field indicates the ca pability to support 4 and 6

channels on PCM Out.

19:18 Reserved.

MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well

and maintains context across power states (except G3). The bit has no hardware

function. It is used by software in conjunction with the AD3 bit to coordinate th e entry

of the two codecs into D3 state.

NOTE: This bit is not affected by D3HOT to D0 Reset.

AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and

maintains context across power states (except G3). The bit has no hardware function.

It is used by softw are in conjuncti on with the MD3 bit to c oordinate the entry of th e two

codecs into D3 state.

NOTE: This bit is not affected by D3HOT to D0 Reset.

Intel ® ICH7 Family Datasheet 663

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read

completions. Software clears this bit by writing a 1 to it.

0 = A codec read completes normally.

1 = A codec read results in a time -out.

NOTE: This bit is not affected by D3HOT to D0 Reset.

14 Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.

13 Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.

12 Bit 1 of Slot 12 — RO. Display bit 1 of the most recent slot 12.

ACZ_SDIN1 Resume Interrupt (S1RI) — R/WC. This bit indicates that a resume

event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.

0 = Resume event did Not occur.

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN0 Resume Interrupt (S0RI) — R/WC. This bit indicates that a resume

event occurred on ACZ_SDIN0. Software clears this bit by writing a 1 to it.

0 = Resume event did Not occur.

1 = Resume event occurred.

NOTE: This bit is not affected by D3HOT to D0 Reset.

ACZ_SDIN1 Codec Ready (S1CR) — RO. This bit reflects the state of the codec

ready bit in ACZ_SDIN1. Bus masters ignore the condition of the codec ready bits, so

software must check this bit before starting the bus masters. Once the codec is “ready”,

it must not go “not ready” spontaneously.

0 = No t Ready.

1 = Ready.

ACZ_SDIN0 Codec Ready (S0CR) — RO. This bit reflects the state of the codec

ready bit in ACZ_SDIN 0. Bus masters ignore the condition of the codec ready bits, so

software must check this bit before starting the bus masters. Once the codec is “ready”,

it must not go “not ready” spontaneously.

0 = No t Ready.

1 = Ready.

7Microphone In Interrupt (MINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the Mic in channel interrupts status bits has been set.

6PCM Out Interrupt (POINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM out channel interrupts status bits has been set.

5PCM In Interru pt (PIINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the PCM in channel interrupts status bits has been set.

4:3 Reserved

Bit Description

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)

664 Intel ® ICH7 Family Datasheet

Note: On reads from a codec, the controller will give the codec a maximum of four frames to

respond, after which if no response is received, it will return a dummy read completion

to the processor (with all F’s on the data) and also set the Read Completion Status bit

in the Global Status Register.

Note: Reads across DWord boundaries are not supported.

17.2.10 CAS—Codec Access Semaphore Register

(Modem—D30:F3)

I/O Address: NABMBAR + 44h Attribute: R/W (special)

Default Value: 00h Size: 8 bits

Lockable: No Power Well: Core

Note: Reads across DWord boundaries are not supported.

2Modem Out Interrupt (MOINT) — RO .

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the modem out chan nel interrupts status bits has been s et.

1Modem In Interrupt (MIINT) — RO.

0 = When the specific status bit is cleared, this bit will be cleared.

1 = One of the modem in channel interrupts status bits has been set.

GPI Status Change Interrupt (GSCI) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set.

This indicates that one of the GP I’s changed state, and that the new values are

available in slot 12.

NOTE: This bit is not affected by AC ‘97 Audio Modem function D3HOT to D0 Reset.

Bit Description

7:1 Reserved

Codec Access Semaphore (CAS) — R/W (special). This bit is read by software to

check whether a codec access is currently in progress.

0 = No access in progress.

1 = The act of reading this register sets this bit to 1. The driver that read this bit can

then perform an I/O access. Once the access is completed, hardware automatically

clears this bit.

Intel ® ICH7 Family Datasheet 665

PCI Express* Configuration Registers (Desktop and Mobile Only)

18 PCI Express* Configuration

Registers (Desktop and Mobile

Only)

Note: PCI Express is not supported on ICH7-U Ultra Mobile.

18.1 PCI Express* Configuration Registers

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Note: Register address locations that are not shown in Table 18-1 should be treated as

Reserved.

Table 18-1. PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 1 of 2)

Offset Mnemonic Register Name Function 0–5

Default Type

00h–01h VID Ve ndor Iden ti fic a ti on 8086h RO

02h–03h DID Device Identification See register

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revision Identification See register

description. RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 04h RO

0Bh BCC Base Class Code 06h RO

0Ch CLS Cache Line Size 00h R/W

0Dh PLT Primary Latency Timer 00h RO

0Eh HEADTYP Header Type 81h RO

18h–1Ah BNUM Bus Number 000000h R/W

1Ch–1Dh IOBL I/O Base and Limit 0000h R/W, RO

1Eh–1Fh SSTS Secondary Status 0000h R/WC

20h–23h MBL Memory Base and Limit 00000000h R/W

24h–27h PMBL Prefetchable Memory Base and Limit 00010001h R/W, RO

28h–2Bh PMBU32 Prefetchable Memory Base Upper 32 Bits 00000000h R/W

2Ch–2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W

34h CAPP Capabilities List Pointer 40h RO

3Ch–3Dh INTR Interrupt Information See bit description R/W, RO

3Eh–3Fh BCTRL Bridge Control 0000h R/W

40h–41h CLIST Capabilities List 8010 RO

42h–43h XCAP PCI Express* Capabilities 0041 R/WO, RO

44h–47h DCAP Device Capabilities 00000FE0h RO

48h–49h DCTL Device Control 0000h R/W, RO

4Ah–4Bh DSTS Device Status 0010h R/WC, RO

PCI Express* Configuration Registers (Desktop and Mobile Only)

666 Intel ® ICH7 Family Datasheet

4Ch–4Fh LCAP Link Capabilities See bit description R/W, RO,

R/WO

50h–51h LCTL Link Control 0000h R/W, WO, RO

52h–53h LSTS Link Status See bit description RO

54h–57h SLCAP Slot Capabilities Register 00000060h R/WO, RO

58h–59h SLCTL Slot Control 0000h R/W, RO

5Ah–5Bh SLSTS Slot Status 0000h R/WC, RO

5Ch–5Dh RCTL Root Control 0000h R/W

60h–63h RSTS Root Status 00000000h R/WC, RO

80h–81h MID Message Signaled Interrupt Identifiers 9005h RO

82h–83h MC Message Signaled Interrupt Message Control 0000h R/W, RO

84h–87h MA Message Signaled Interrupt Message Address 00000000h R/W

88h–89h MD Message Signaled Interrupt Message Data 0000h R/W

90h–91h SVCAP Subsystem Vendor Capability A00Dh R O

94h–97h SVID Subsystem Vendor Identification 00000000h R/WO

A0h–A1h PMCAP Power Management Capability 0001h RO

A2h–A3h PMC PCI Power Management Capability C802h RO

A4–A7h PMCS PCI Power Management Control and Status 00000000h R/W, RO

D8–DBh MPC Miscellaneous Port Configuration 00110000h R/W

DC–DFh SMSCS SMI/SCI Status 00000000h R/WC

E1h RPDCGEN Root Port Dynamic Clock Gating Enable

(Mobile/Ultra Mobile Only) 00h R/W

E2–E3h IPWS Intel® PRO/Wireless 3945ABG Status 0000h RO

100–103h VCH Virtual Channel Capability Header 18010002h RO

108h–10Bh VCAP2 Virtual Channel Capability 2 00000001h RO

10Ch–10Dh PVC Port Virtual Channel Control 0000h R/W

10Eh–10Fh P VS Port Virtual Channel Status 0000h RO

110h–113h V0CAP Virtual Channel 0 Resource Capability 00000001h RO

114–117h V0CTL Virtual Channel 0 Resource Control 800000FFh R/W, RO

11A–11Bh V0STS Virtual Channel 0 Resource Status 0000h RO

144h–147h UES Uncorrectable Error Status See bit description R/WC, RO

148h–14Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO

14Ch–14Fh UEV Uncorrectable Error Severity 00060011h RO

150h–153h CES Correctable Error Status 00000000h R/WC

154h–157h CEM Correctable Error Mask 00000000h R/WO

158h–15Bh AECC Advanced Error Capabilities and Control 00000000h RO

170h–173h RES Root Error Status 00000000h R/WC, RO

180h–183h RCTCL Root Complex Topology Capability List 00010005h RO

184h–187h ESD Element Self Description See bit description RO

190h–193h ULD Upstream Link Desc ription 00000001h RO

198h–19Fh ULBA Upstream Link Base Address See bit description RO

318h PEETM PCI Express Extended Test Mode Register 00h RO

Table 18-1. PCI Express* Configuration Registers Address Map

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Sheet 2 of 2)

Offset Mnemonic Register Name Function 0–5

Default Type

Intel ® ICH7 Family Datasheet 667

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.1 VID—Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 00h–01h Attribute: RO

Default Value: 8086h Size: 16 bits

18.1.2 DID—Device Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 02h–03h Attribute: RO

Default Value: Port 1= Bit Description Size: 16 bits

Port 2= Bit Description

Port 3= Bit Description

Port 4= Bit Description

Port 5= Bit Description

Port 6= Bit Description

18.1.3 PCICMD—PCI Command Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the I ntel® ICH7 PCI Express

controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification Update

for the value of the Device ID Register.

Bit Description

15:11 Reserved

Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts on enabled

Hot-Plug and power management events. This bit has no effect on MSI operation.

0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or

power management and MSI is not enabled.

1 = Internal INTx# messages will not be generated.

NOTE: This bit does not affect interrupt forwarding from devices connected to the root

port. Assert_INTx and Deassert_INTx messages will still be forwarded to the

internal interrupt controllers if this bit is set.

9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification.

8SERR# Enable (SEE) — R/W.

0 = Disable.

1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.

7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.

Parity Error Response (PER) — R/W.

0 = Disable.

1 = Indicates that the device is capable of reporting parity errors as a master on the

backbone.

PCI Express* Configuration Registers (Desktop and Mobile Only)

668 Intel ® ICH7 Family Datasheet

18.1.4 PCISTS—PCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 06h–07h Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

5 VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specificati on.

4Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base

Specification.

3 Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specificatio n .

Bus Master Enable (BME) — R/W.

0 = Disable. All cycles from the device are master aborted

1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI

Express* device.

Memory Space Enable (MSE) — R/W.

0 = Disable. Memory cycles within the range specified by the memory base and limit

registers are master aborted on the backbone.

1 = Enable. Allows memory cycles within the range specified by the memory base and

limit registers can be forwarded to the PCI Express device.

I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.

0 = Disable . I/O cycles within the range specified by the I/O base and limit registers

are master aborted on the backbone.

1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit

registers can be forwarded to the PCI Express device.

Bit Description

Detected Parity Error (DPE) — R/WC.

0 = No parity error detected.

1 = Root port received a command or data from the backbone with a parity error. This

is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.

14 Signaled System Error (SSE) — R/WC.

0 = No system error signaled.

1 = Root port signaled a system error to the internal SERR# logic.

Received Master Abort (RMA) — R/WC.

0 = Root port has not receiv ed a com ple tion with un supported request status from the

backbone.

1 = Root port received a completion with unsupported request status from the

backbone.

12 Received Target Abort (RTA) — R/WC.

0 = Root port has not received a completion with completer abort from the backbone.

1 = Root port received a completion with completer abort from the backbone.

Signaled Target Abort (STA) — R/WC .

0 = No target abort received.

1 = Root port forwarded a target abort received from the downstream device onto the

backbone.

10:9 DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base

Specification.

Intel ® ICH7 Family Datasheet 669

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.5 RID—Revision Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Offset Address: 08h Attribute: RO

Default Value: See bit description Size: 8 bits

18.1.6 PI—Programming Interface Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

18.1.7 SCC—Sub Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Ah Attribute: RO

Default Value: 04h Size: 8 bits

Master Data P arity Error Detected (DPED) — R/WC.

0 = No data parity error received.

1 = Root port received a completion with a data parity error on the backbone and

PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.

7Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base

Specification.

6 Reserved

5 66 MHz Capable — Reserved per the PCI Express* Base Specification.

4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.

Interrupt Status — RO. Indicates status of Hot-Plug and power management

interrupts on the root port that result in INTx# message generation.

0 = Interrupt is deasserted.

1 = Interrupt is asserted.

This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the

state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10).

2:0 Reserved

Bit Description

7:0 R evision ID — RO. Refer to the Intel® I/O Controller Hub 7 (ICH7) Fami ly Specification

Update for the value of the Revision ID Register.

Bit Description

7:0 Programming Interface — RO.

00h = No specific register level programming interface defined.

Bit Description

7:0 Sub Class Code (SCC) — RO.

04h = PCI-to-PCI bridge.

PCI Express* Configuration Registers (Desktop and Mobile Only)

670 Intel ® ICH7 Family Datasheet

18.1.8 BCC—Base Class Code Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Bh Attribute: RO

Default Value: 06h Size: 8 bits

18.1.9 CLS—Cache Line Size Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

18.1.10 PLT—Primary Latency Timer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

18.1.11 HEADTYP—Header Type Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 0Eh Attribute: RO

Default Value: 81h Size: 8 bits

Bit Description

7:0 Base Class Code (BCC) — RO.

06h = Indicates the device is a bridge device.

Bit Description

7:0 Base Class Code (BCC) — R/W. This is read/write but contains no functionality, per the

PCI Express* Base Specification.

Bit Description

7:3 Latency Count. Reserved per the PCI Express* Base Specification.

2:0 Reserved

Bit Description

7Multi-Fu nction Devic e — RO.

0 = Single-function devi ce.

1 = Multi-fun ction device.

6:0 Configuration Layout. Hardwired to 01h, which indicate s a PCI-to-PCI bridge.

Intel ® ICH7 Family Datasheet 671

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.12 BNUM—Bus Number Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 18–1Ah Attribute: R/W

Default Value: 000000h Size: 24 bits

18.1.13 IOBL—I/O Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 1Ch–1Dh Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

23:16 Subordinate Bus Numb er (SBBN) — R/W. This field indicates the highest PCI bus

number below the bridge.

15:8 Secondary Bus Number (SCBN) — R/W. This field indicates the bus n umber the

port.

7:0 Primary Bus Number (PBN) — R/W. This field indicates the bus number of the

backbone.

Bit Description

15:12 I/O Limit Address (IOLA) — R/W. This field contains the I/O Base bits

corresponding to address lines 15: 12 for 4-KB ali gnment. Bits 11:0 are assumed to be

padded to FFFh.

11:8 I/O Limit Address Capability (IOLC) — R/O. This field indicates that the bridge does not

support 32-bit I/O addressing.

7:4 I/O Base Address (IOBA) — R/W. This field contains the I/O Base bits

corresponding to address lines 15: 12 for 4-KB ali gnment. Bits 11:0 are assumed to be

padded to 000h.

3:0 I/O Base Address Capability (IOBC) — R/O . This field indicates that the bridge does not

support 32-bit I/O addressing.

PCI Express* Configuration Registers (Desktop and Mobile Only)

672 Intel ® ICH7 Family Datasheet

18.1.14 SSTS—Secondary Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 1Eh–1Fh Attribute: R/WC

Default Value: 0000h Size: 16 bits

Bit Description

15 Detected Parity Error (DPE) — R/WC.

0 = No error.

1 = The port received a poisoned TLP.

14 Received System Error (RSE) — R/WC.

0 = No error.

1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.

13 Received Master Abort (RMA) — R/WC.

0 = Unsupported Request not received.

1 = The port received a completion with “Unsupported R equest” status from the device.

12 Received Target Abort (RTA) — R/WC.

0 = Completion Abort not received.

1 = The port received a completion with “Completion Abort” status from the device.

11 Signaled Target Abort (STA) — R/WC.

0 = Completion Abort not sent.

1 = The port generated a completion with “Completion Abort” status to the device.

10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base

Specification.

Data Parity Error Detected (DPD) — R/WC.

0 = Conditions below did not occur.

1 = Set when the BCTRL.PERE (D28:FO/F 1/F 2/ F3/ F4/ F5: 3E : bi t 0 ) i s s et, an d ei the r of

the following two conditions occurs:

— Port receives completion marked poisoned.

— Port poisons a write request to the secondary side.

7Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base

Specification.

6Reserved

5 Secondary 66 MHz Capable (SC66). Reserved per PCI Express* Base Specification .

4:0 Reserved

Intel ® ICH7 Family Datasheet 673

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.15 MBL—Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 20h–23h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Accesses that are within the ranges specified in this register will be sent to the attached

device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5:04:bit 1) is set. Accesses from the

attached device that are outside the ranges specified will be forwarded to the backbone

if CMD.BME (D28:F0/F1/F2/F3/F4/F5:04:bit 2) is set. The comparison performed is:

MB ≥ AD[31:20] ≤ ML.

18.1.16 PMBL—Prefetchable Memory Base and Limit Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00010001h Size: 32 bits

Accesses that are within the ranges specified in this register will be sent to the device if

CMD.MSE (D28:F0/F1/F2/F3/F4/F5;04, bit 1) is set. Accesses from the device that are

outside the ranges specified will be forwarded to the backbone if CMD .BME (D28:F0/F1/

F2/F3/F4/F5;04, bit 2) is set. The comparison performed is:

PMBU32:PMB ≥ AD[63:32]:AD[31:20] ≤ PMLU32:PML.

Bit Description

31:20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the upper 1-MB aligned value of the range.

19:16 Reserved

15:4 Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming

address to determine the lower 1-MB aligned value of the range.

3:0 Reserved

Bit Description

31:20 Prefetchable Memory Limit (PML) — R/W. These bits are compared wit h bits 31:2 0

of the incoming address to determine the upper 1-MB aligned value of the range.

19:16 64-bit Indicator (I64L) — RO. This field indicates support for 64-bit addressing

15:4 Prefet chab le Memory Base (PMB) — R/W. These bits are compared with bits 31:20

of the incoming address to determine the lower 1-MB aligned value of the range.

3:0 64-bit Indicator (I64B) — RO. This field indicates support for 64-bit addressing

PCI Express* Configuration Registers (Desktop and Mobile Only)

674 Intel ® ICH7 Family Datasheet

18.1.17 PMBU32—Prefetchable Memory Base Upper 32 Bits

Address Offset: 28h–2Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

18.1.18 PMLU32—Prefetchable Memory Limit Upper 32 Bits

Address Offset: 2Ch–2Fh Attribute: R/W

Default Value: 00000000h Size: 32 bits

18.1.19 CAPP—Capabilities List Pointer Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 34h Attribute: R0

Default Value: 40h Size: 8 bits

Bit Description

31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field contains the

Upper 32-bits of the prefetchable address base.

Bit Description

31:0 Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field contains the

Upper 32-bits of the prefetchable address limit.

Bit Description

7:0 Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first

entry in the capabilities list is at 40h in configuration space.

Intel ® ICH7 Family Datasheet 675

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.20 INTR—Interrupt Information Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 3Ch–3Dh Attribute: R/W, RO

Default Value: See bit description Size: 16 bits

Bit Description

15:8

Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root

port. At reset, this register takes on the following values that reflect the reset state of

the D28IP register in chipset configuration space:

NOTE: The value that is programmed into D28IP is always reflected in this register.

7:0 Interrupt Line (ILINE) — R/W. Default = 00h. This field is a software written val ue to

indicate which interrupt line (vector) the interrupt is connected to. No hardware action

is taken on this register.

Port Reset Value

1D28IP.P1IP

2D28IP.P2IP

3D28IP.P3IP

4D28IP.P4IP

5D28IP.P5IP

6D28IP.P6IP

PCI Express* Configuration Registers (Desktop and Mobile Only)

676 Intel ® ICH7 Family Datasheet

18.1.21 BCTRL—Bridge Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 3Eh–3Fh Attribute: R/W

Default Value: 0000h Size: 16 bits

Bit Description

15:12 Reserved

11 Discard Timer SERR# Enable (DTSE). Reserved per PCI Express* Base Specification,

Revision 1.0a

10 Discard Timer Status (DTS). Reserved per PCI Express* Base Specification, Revision

1.0a.

9Secondary Discard Timer (SDT). Reserved per PCI Express* Base Specificat ion,

Revision 1.0a .

8Primary Discard Timer (PDT). Reserved per PCI Express* Base Specification, Revision

1.0a.

7F ast Back to B ack Enable (FBE). R eserved per PCI Express* Base Spe cification, Revision

1.0a.

6Secondary Bus Reset (SBR) — R/W. This bit triggers a hot reset on the PCI Express*

port.

5 Master Abort Mode (MAM): Reserved per Express specification.

VGA 16-Bit Decode (V16) — R/W.

0 = VGA range is enabled.

1 = The I/O aliases of the VGA r ange (see B CTRL:VE definition below), are not enabled,

and only the base I/O ranges can be decoded

VGA Enable (VE)— R/W.

0 = The ranges below will not be claimed off the backbone by the root port.

1 = The following ranges will be claimed off the backbone by the root port:

— Memory ranges A0000h–BFFFFh

— I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination

of 1s

ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the

I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.

0 = The root port will not block any forwarding from the backbone as described below.

1 = The root port will block any forwarding from the backbone to the device of I/O

transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to

3FFh).

SERR# Enable (SE) — R/W.

0 = The messages described below are not forwarded to the backbone.

1 = ERR_C OR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to

the backbone.

Parity Error Response Enable (PERE) — R/W.

0 = Poisoned write TLPs and completions indicating poisoned TLPs will not se t the

SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).

1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the

SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).

Intel ® ICH7 Family Datasheet 677

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.22 CLIST—Capabilities List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 40–41h Attribute: RO

Default Value: 8010h Size: 16 bits

18.1.23 XCAP—PCI Express* Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 42h–43h Attribute: R/WO, RO

Default Value: 0041h Size: 16 bits

Bit Description

15:8 Next Capability (NEXT) — RO. Value of 80h indicates the locati on of the next pointer.

7:0 Capability ID (CID) — RO . This field indicates this is a PCI Express* capability.

Bit Description

15:14 Reserved

13:9 Interrupt Message Number (IMN) — RO. The Intel® ICH7 does not have multiple

MSI interrupt numbers.

8Slot Implemented (SI) — R/WO. This field indicates whether the root port is

connected to a slot. Slot support is platform specific. BIOS progr ams t his field, and it is

maintained until a platform reset.

7:4 Device / Port Type (DT) — RO. This field indicates this is a PCI Express* root port.

3:0 Capability Version (CV) — RO. This field indicates PCI Express 1.0.

PCI Express* Configuration Registers (Desktop and Mobile Only)

678 Intel ® ICH7 Family Datasheet

18.1.24 DCAP—Device Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 44h–47h Attribute: RO

Default Value: 00000FE0h Size: 32 bits

Bit Description

31:28 Reserved

27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported.

25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported.

17:15 Reserved

14 Power Indicator Present (PIP) — RO. This bit indicates no power indicator is

present on the root port.

13 Attention Indicator Present (AIP) — RO. This bit indicates no attention indicator is

present on the root port.

12 Attention Button Present (ABP) — RO. This bit indicates no attention button is

present on the root port.

11:9 Endpoint L1 Acceptable Latency (E1AL) — RO. This field indicates more than 4 µs.

This field essentially has no meaning for root ports since root ports are not endpoints.

8:6 Endpoint L0 Acceptable Latency (E0AL) — RO . This field indicates more than 64 µs.

This field essentially has no meaning for root ports since root ports are not endpoints.

5Extended Tag Field Supported (ETFS) — RO. This bit indicates that 8-bit tag fields

are supported.

4:3 Phantom Functions Supported (PFS) — RO. This field indicates No phantom

functions supported.

2:0 Max Payload Size Supported (MPS) — RO. This field indicates the maximum

payload size supported is 128B.

Intel ® ICH7 Family Datasheet 679

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.25 DCTL—Device Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 48h–49h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15 Reserved

14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0.

11 Enable No Snoop (ENS) — RO. Not supported. The root port will not issue non-snoop

requests.

10 Aux Power PM Enable (A PME) — R/W. Th e OS will set this bit t o 1 if the device

connected has detected aux power. It has no effect on the root port otherwise.

9Phantom Functions Enable (PFE) — RO. Not supported.

8Extended Tag Field Enable (ETFE) — RO. Not supported.

7:5 Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,

regardless of the programming of this field.

4Enable Relaxed Ordering (ERO) — RO. Not supported.

3Unsupported Request Reporting Enable (URE) — R/W.

0 = Disable. The root port will ignore unsupported request errors.

1 = Enable. The root port will generate errors when detecting an unsupported request.

2Fatal Error Reporting Enable (FEE) — R/W.

0 = Disable. The root port will ignore fatal errors.

1 = Enable. The root port will generate errors when detecting a fatal error.

1Non-Fatal Error Reporting Enable (NFE) — R/W.

0 = Disable. The root port will ignore non-fatal errors.

1 = Enable. The root port will generate errors when detecting a non-fatal error.

0Correctable Error Reporting Enable (CE E) — R/W.

0 = Disable. The root port will ignore correctable errors.

1 = Enable. The root port will generate errors when detecting a correctable error.

PCI Express* Configuration Registers (Desktop and Mobile Only)

680 Intel ® ICH7 Family Datasheet

18.1.26 DSTS—Device Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 4Ah–4Bh Attribute: R/WC, RO

Default Value: 0010h Size: 16 bits

Bit Description

15:6 Reserved

5Transactions Pending (TDP) — RO. This bit has no meaning for the root port since

only one transaction may be pending to the Intel® ICH7, so a read of this bit cannot

occur until it has already returned to 0.

4AUX Power Detected (APD) — RO. The root port contains AUX power for wakeup.

3Unsupported Request Detected (URD) — R/WC. This bit indicates an unsupported

request was detected.

Fatal Error Detected (FED) — R/WC. This bit indicates a fatal error was detected.

0 = Fatal has not occurred.

1 = A fatal error occurred from a data link protocol error, link training error, buffer

overf low, or malformed TLP.

Non-Fatal Error Detected (NFED) — R/WC. This bit indicates a non-fatal error was

detected.

0 = Non-fatal has not occurred.

1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,

unsupported requests, completer abort, or completer timeout.

Correctable Error Detected (CED) — R/WC. This bit indicates a correctable error

was detected.

0 = Correctable has not occurred.

1 = The port received an internal correctable error from receiver errors / framing

errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.

Intel ® ICH7 Family Datasheet 681

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.27 LCAP—Link Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 4Ch–4Fh Attribute: R/W, RO

Default Value: See bit description Size: 32 bits

Bit Description

31:24

Port Number (PN) — RO. This field indicates the port number for the root port. This

value is different for each implemented port:

23:21 Reserved

20 Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this port

supports the optional capability of reporting the DL_Active state of the Data Link

Control and Management State Machine.

19:18 Reserved

17:15 L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.

14:12

L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon

common-clock configuration.

NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6

11:10

Active State Link PM Support (APMS) — R/WO. This field indicates what level of

active state link power mana gement is supported on the root port.

Function Port # Value of PN

Field

D28:F0 1 01h

D28:F1 2 02h

D28:F2 3 03h

D28:F3 4 04h

D28:F4 5 05h

D28:F5 6 06h

LCLT

CCC V

f EL0 (th

ese

bit

)

0MPC.UCEL (D28:F0/F1/F2/

F3:D8h:bits20:18)

1MPC.CCEL (D28:F0/F1/F2/

F3:D8h:bits17:15)

Bits Definition

00b Neither L0s nor L1 are supported

01b L0s Entry Supported

10b L1 Entry Supported

11b Both L0s and L1 Entry Supported

PCI Express* Configuration Registers (Desktop and Mobile Only)

682 Intel ® ICH7 Family Datasheet

18.1.28 LCTL—Link Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 50h-51h Attribute: R/W, WO, RO

Default Value: 0000h Size: 16 bits

9:4

Maximum Link Width (MLW) — RO . For the root ports, several values can be taken,

based upon the value of the chipset configuration reg ist er field RPC.PC1 (Chipset

Configuration Registers:Offset 0224h:bits1:0) for Ports 1–4 and RPC.PC2 (Chipset

Configuration Registers:Offset 0224h:bits1:0) for Ports 5 and 6.

3:0 Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.

Bit Description

Value of MLW Field

Port # RPC.PC1=00b RPC.PC1=11b

1 01h 04h

2 01h 01h

3 01h 01h

4 01h 01h

Port # RPC.PC2=00b RPC.PC2=11b

5 01h N/A

6 01h N/A

Bit Description

15:8 Reserved

Extended Synch (ES) — R/W.

0 = Extended synch disabled.

1 = F orces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from

L1 prior to entering L0.

6Common Clock Configuration (CCC) — R/W.

0 = The Intel® ICH7 and device are not using a common reference clock.

1 = The ICH7 and device are operating with a distributed common reference clock.

Retrain Link (RL) — WO.

0 = This bit always returns 0 when read.

1 = The root port will train its downstream link.

NOTE: Software use s LSTS . LT (D28:F0/F1/F2/F3/F 4/F 5:52, bit 11) to ch eck the st atus

of training.

4Link Disable (LD) — R/W.

0 = Link enabled.

1 = The root port will disable the link.

3Read Completion Boundary Control (RCBC) — RO. This bit indicates that the read

completion boundary is 64 bytes.

2Reserved

Intel ® ICH7 Family Datasheet 683

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.29 LSTS—Link Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 52h–53h Attribute: RO

Default Value: See bit description Size: 16 bits

1:0

Active State Link PM Control (APMC) — R/W. This bit indicates whether the root

port should enter L0s or L1 or both.

Bit Description

Bits Definition

00b Disabled

01b L0s Entry is Enabled

10b L1 Entry is Enabled

11b L0s and L1 Entr y Enabled

Bit Description

15:14 Reserved

Data Link Layer Active (DLLA) — RO. D

0 = Data Link Control and Management State Machine is not in the DL_Active state.

(Default)

1 = Data Link Control and Management State Machine is in the DL_Ac tive state.

12 Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel® ICH7 uses

the same reference clock as on the platform and does not generate its own clock.

11 Link Tra ining (LT ) — RO.

0 = Link training completed. (Default)

1 = Link training is occurring.

10 Link Training Error (LTE) — RO. Not supported. Set value is 0b.

9:4

Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the

given PCI Express* link. The contents of this NLW field is undefined if the link has not

successfully trained.

NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported),

000100 = x4 linkwidth

3:0 Link Speed (LS) — RO. This field indica tes the negotiated Link speed of the given PCI

Express* link.

01h = Link is 2.5 Gb/s.

Port # Possible Values

1 000001b, 000010b, 000100b

2 000001b

3 000001b

4 000001b

5 000001b, 000010b

6 000001b

PCI Express* Configuration Registers (Desktop and Mobile Only)

684 Intel ® ICH7 Family Datasheet

18.1.30 SLCAP—Slot Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 54h–57h Attribute: R/WO, RO

Default Value: 00000060h Size: 32 bits

Bit Description

31:19 Physical Slot Number (PSN) — R/WO. This is a value that is unique to the slot

number. BIOS sets this field and it remains set until a platform reset.

18:17 Reserved

16:15

Slot Power L imit S cale ( SLS) — R/W O. T his field spec ifies the sc ale used for the sl ot

power limit value. BIOS sets this field and it remains set un til a platform reset.

Range of Values:

00b = 1.0 x

01b = 0.1 x

10b = 0.01 x

11b = 0.001 x

14:7

Slot Power Limit Value (SLV) — R/WO. This field specifies the upper limit (in

conjunction with SLS value), on the upper limit on power supplied by the slot. The two

values together indicate the amount of power in watts allowed for the slot. Power limit

(in Watts) is calculated by multiplying the value in this field by the value in the Slot

Power Limit Scale field. BIOS sets this field and it remains set until a platform reset.

6Hot Plug Capable (HPC) — RO.

1b = Hot-Plug is supported.

5Hot Plug Surprise (HPS) — RO.

1b = Device may be removed from the slot without prior notification.

4Power Indicator Present (PIP) — RO.

0b = Power indicator LED is not present for this slot.

3Attention Indicator Present (AIP) — RO.

0b = Attention indicator LED is not present for this slot.

2MRL Sensor Present (MSP) — RO.

0b = MRL sensor is not present.

1Power Controlle r Prese n t (PCP) — RO.

0b = Power controller is not implemented for this slot.

0Attention Button Present (ABP) — RO.

0b =Attention button is not implemented for this slot.

Intel ® ICH7 Family Datasheet 685

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.31 SLCTL—Slot Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 58h–59h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:13 Reserved

Link Active Changed Enable (LACE) — RW.

0 = Disable.

1 = Enables generation of a hot plug interrupt when the Data Link Layer Link Active

field (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed.

11 Reserved

10 Power Controller Control (PCC) — RO.This bit has no meaning for module based

Hot-Plug.

9:8

Power Indicator Control (PIC) — R/W. When read, the current state of the power

indicator is returned. When written, the appropriate POWER_INDICATOR_* messages

are sent. Defined encodings are:

7:6

Attention Indicator Control (AIC) — R/W. When read, the current state of the

attention indicator is returned. When written, the appropriate

ATTENTION_INDICATOR_* messages are sent. Defined encodings are:

5Hot Plug Interrupt Enable (HPE) — R/W.

0 = Disable. Hot plug interrupts based on Hot-Plug events is disabled.

1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.

Command Completed Interrupt Enable (CCE) — R/W.

0 = Disable. Hot plug interrupts based on command completions is disabled.

1 = Enables th e generation of a Hot-Plug interrupt when a command is completed by

the Hot-Plug controller.

Presence Detect Changed Enable (PDE) — R/W.

0 = Disable. Hot plug interrupts based on presence detect logic changes is disabled.

1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence

detect logic changes state.

Bits Definition

00b Reserved

01b On

10b Blink

11b Off

Bits Definition

00b Reserved

01b On

10b Blink

11b Off

PCI Express* Configuration Registers (Desktop and Mobile Only)

686 Intel ® ICH7 Family Datasheet

18.1.32 SLSTS—Slot Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 5Ah–5Bh Attribute: R/WC, RO

Default Value: 0000h Size: 16 bits

2MRL Sensor Changed Enable (MSE) — R/W. MSE not supported.

1Power Fault Detected Enable (PFE) — R/W. PFE not supported.

Attention Button Pressed Enable (ABE) — R/W. When set, enables the generation

of a Hot-Plug interrupt when the attention button is pressed.

0 = Disable. Hot plug interrupts based on the attention button being pressed is

disabled.

1 = Enables the generation of a Hot-Plug interrupt when the attention button is

pressed.

Bit Description

15:9 Reserved

Link Active State Changed (LASC) — R/WC.

0 = No Change.

1 = Value reported in Data Link Layer Link Active field of the Link Status register

(D28:F0/F1/F2/ F3/F4/F5:52h:bit 13) is changed. In res ponse to a D ata Link Lay er

State Changed event, software must read Data Link Layer Link Active field of the

Link Status register to determine if the link is active before initiating configuration

cycles to the hot plugged device.

7Reserved

Presence Detect State (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5:42h:bit 8)

is set indicating that this root port spawns a slot), then this bit:

0 = Slot is empty.

1 = Slot has a device connected.

Otherwise; if XCAP.SI is cleared, this bit is always set to 1.

5 MRL Sensor State (MS) — Reserved as the MRL sensor i s not implemented.

Command Completed (CC) — R/WC.

0 = Issued command not completed.

1 = The Hot-Plug controller completed an issued command. This is set when the last

message of a command is sent and indicates that software can write a new

command to the slot controller.

3Presence Detect Changed (PDC) — R/WC.

0 = No change in the PDS bit.

1 = The PDS bit changed states.

2 MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implemented.

1 Power Fault Detected (PFD) — Reserved as a power controller is not implemented.

0Attention Button Pressed (ABP) — R/WC.

0 = The attention button has not been pressed.

1 = The attention button is pressed.

Intel ® ICH7 Family Datasheet 687

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.33 RCTL—Root Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 5Ch–5Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

18.1.34 RSTS—Root Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 60h–63h Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:4 Reserved

PME Interrupt Enable (PIE) — R/W.

0 = Interrupt generation disabled.

1 = Interrupt generation enabled when PCISTS.Interrupt Status (D28:F0/F1/F2/F3/F4/

F5:60h, bit 1 6) is in a set state (either due to a 0 to 1 transition, or due to this b it

being set with RSTS.IS already set).

System Error on Fatal Error Enable (SFE) — R/W.

0 = Disable. An SERR# will not be generated.

1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/

F5:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy

of this root port, including fatal errors in this root port.

System Error on Non-Fatal Error Enable (SNE) — R/W.

0 = Disable. An SERR# will not be generated.

1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/

F5:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the

hierarchy of this root port, including non-fatal errors in this root port.

System Error on Correctable Error Enable (SCE) — R/W.

0 = Disable. An SERR# will not be generated.

1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/

F5:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy

of this root port, including correctable errors in this root port.

Bit Description

31:18 Reserved

PME Pending (PP) — RO.

0 = Indicates no more PMEs are pending.

1 = Indicates another PME is pending (this is implicit because of the definition of this bit

being 1). Hardware will set the PME Status bit again and update the Requestor ID

appropriately. The PME pending bit is cleared by hardware if no more PMEs are

pending.

PME Status (PS) — R/WC.

0 = PM E was not asserted.

1 = PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending

until this bit is cleared.

15:0 PME Requestor ID (RID) — RO. This field indicates the PCI requestor ID of the last

PME requestor. The value in this field is valid only when PS is set.

PCI Express* Configuration Registers (Desktop and Mobile Only)

688 Intel ® ICH7 Family Datasheet

18.1.35 MID—Message Signaled Interrupt Identifiers Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 80h–81h Attribute: RO

Default Value: 9005h Size: 16 bits

18.1.36 MC—Message Signaled Interrupt Message Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 82–83h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

18.1.37 MA—Message Signaled Interrupt Message Address

Address Offset: 84h–87h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

15:8 Next Pointer (NEXT) — RO . This field indicates the location of the next pointer in the

list.

7:0 Capability ID (CID) — RO. Capabilities ID indicates MSI.

Bit Description

15:8 Reserved

764 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.

6:4 Multiple Message Enable (MME) — R/W. These bits are R/W for software

compatibility, but only one message is ever sent by the root port.

3:1 Multiple Message Capable (MMC) — RO. Only one message is required.

MSI Enable (MSIE) — R/W.

0 = Disabled.

1 = Enabled an d traditional interrupt pins are not used to generate interrupts.

NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5:04h:bit 2) must be set for an MSI to be

generated. If CMD .BME is cleared, and this bit is set, no interrupts (not even pin

based) are generated.

Bit Description

31:2 Address (ADDR) — R/W. This field contains the lower 32 bits of the system specified

message address; always DWord aligned.

1:0 Reserved

Intel ® ICH7 Family Datasheet 689

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.38 MD—Message Signaled Interrupt Message Data Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 88h–89h Attribute: R/W

Default Value: 0000h Size: 16 bits

18.1.39 SVCAP—Subsystem Vendor Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 90h–91h Attribute: RO

Default Value: A00Dh Size: 16 bits

18.1.40 SVID—Subsystem Vendor Identification Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 94h–97h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

18.1.41 PMCAP—Power Management Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: A0h–A1h Attribute: RO

Default Value: 0001h Size: 16 bits

Bit Description

15:0 Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is

enabled. Its content i s driven onto the lower word (PCI AD[15:0]) during the data

phase of the MSI memory write transaction.

Bit Description

15:8 Next Capability (NEXT) — RO. This field indicates the location of the next pointer in

the list.

7:0 Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge

subsystem vendor capability.

Bit Description

31:16 Subsystem Identifi er (SID) — R/WO . This field indicate s the subsystem as identified

by the vendor. This field is write once and is locked down until a bridge reset occurs

(not the PCI bus reset).

15:0 Subsystem Vendor Identi fier (SVID) — R/WO. This field indicates the manufacturer

of the subsystem. This field is write once and is locked down unti l a bridge res et occurs

(not the PCI bus reset).

Bit Description

15:8 Next Capability (NEXT) — RO. This field indicates that this is the last item in the list.

7:0 Capability Identifier (CID) — RO. Value of 01h indicates this is a PCI power

management capability.

PCI Express* Configuration Registers (Desktop and Mobile Only)

690 Intel ® ICH7 Family Datasheet

18.1.42 PMC—PCI Power Management Capabilities Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: A2h–A3h Attribute: RO

Default Value: C802h Size: 16 bits

18.1.43 PMCS—PCI Power Management Control and Status

Address Offset: A4h–A7h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:11

PME_Support (PMES) — RO. This field indicates PME# is supported for states D0, D3HOT

and D3COLD. The root port does not generate PME#, but reporting that it does is

necessary for some legacy operating systems to enable PME# in devices connected

behind this root port.

10 D2_Support (D2S) — RO. The D2 state is not supported.

9 D1_Support (D1S) — RO The D1 state is not supporte d .

8:6 Aux_Current (AC) — RO. This field reports 375 mA maximum suspend well current

required when in the D3COLD state.

5Device Specific Initialization (DSI) — RO. This bit indicates that no device-spec ific

initialization is required.

4Reserved

3PME Clock (PMEC) — RO. This bit in dicates that PCI clock is not required to generate

PME#.

2:0 Version (VS) — RO. This field indicates support for Revision 1.1 of the PCI Power

Management Specification.

Bit Description

31:24 Reserved

23 Bus Power / Clock Control Enable (BPCE). Reserved per PCI Express* Base

Specification, Revision 1.0a.

22 B2/B3 Support (B23S). Reserved per PCI Express* Base Specification, Revision 1.0a.

21:16 Reserved

15 PME Status (PMES) — RO. This bit indicates a PME was received on the downstream

link.

14:9 Reserved

PME Enable (PMEE) — R/W. Indicates PME is enabled. The root port takes no action

on this bit, but it must be R/W for some legacy operating systems to enable PME# on

devices connected to this root port.

0 = Disable.

1 = Enable.

NOTE: This bit is sticky and resides in the resume well. The reset for this bit is

RSMRST# which is not asserted during a warm reset.

7:2 Reserved

Intel ® ICH7 Family Datasheet 691

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.44 MPC—Miscellaneous Port Configuration Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: D8h–DBh Attribute: R/W

Default Value: 00110000h Size: 32 bits

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the root port and to set a new power state. The values are:

00 = D0 st ate

11 = D3HOT state

NOTE: Wh en in the D3HOT state, the controller’s configuration space is available, but

the I/O and memory spaces are not. Type 1 configuration cycles are also not

accepted. Interrupts are not required to be blocked as software will disable

interrupts prior to placing the port into D3HOT. If software attempts to write a

‘10’ or ‘01’ to these bits, the write will be ignored.

Bit Description

Power Management SCI Enable (PMCE) — R/W.

0 = Disable. SCI generation based on a power management event is disabled.

1 = Enables the root port to generate SCI whenever a power management event is

detected.

30 Hot Plug SCI Enable (HPCE) — R/W.

0 = Disable. SCI generation based on a Hot-Plug event is disa bled.

1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.

Link Hold Off (LHO)— R/W.

0 = Not in Link Hold Off.

1 = The port will not take any TLP. This is used during loopback mode to fill up the

downstream queue.

Address Translator Enable (ATE) — R/W. This bit is used to enable address

translation via the AT bits in this register during loopback mode.

0 = Disable.

1 = Enable.

27 Reserved.

Invalid Receive Bus Number Che ck Enabl e (IRBNCE) — R/W.

0 = Disable.

1 = Enable. Receive t ransaction lay er will signal an error if the bus number of a Memory

request does not fall within the range between SCBN and SBBN . If this check is

enabled and the request is a memory write, it is tr eated as an Unsupported

Request. If this check is enabled and the request is a non-posted memory read

request, the request is considered a Malf ormed TLP and a fatal error.

NOTE: Messages, IO, Configuration, and Completions are not checked for valid bus

number.

Invalid Receive Range Check Enable (IRRCE) — R/W.

0 = Disable.

1 = Enable. Receive transaction layer will tr eat the TLP as an Unsupported Request

error if the address range of a memory re quest does not outside the range between

prefetchable and non-prefetchable base and limit.

NOTE: Messages, I/O, Configuration, and Completions are not checked for valid

address ranges.

PCI Express* Configuration Registers (Desktop and Mobile Only)

692 Intel ® ICH7 Family Datasheet

BME Receive Check Enable (BMERCE) — R/W.

0 = Disable.

1 = Enable. Receive transaction layer will treat the TLP as an Unsupported Request

error if a memory read or write request is rece ived and the Bus Master Enable bit is

not set.

NOTE: Messages, IO, Configuration, and Completions are not checked for BME.

23:21 Reserved

20:18

Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit

Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/

F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by

BIOS.

17:15

Common Clock Exit Latency (C CEL) — R/W. This value represents the L0s Exit

Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/

F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden

by BIOS.

14:8 Reserved

Port I/OxApic Enable (PAE) — R/W.

0 = Hole is disabled.

1 = A range is opened through the bridge for the following memory addresses:

6:2 Reserved

1Hot Plug SMI Enable (HPME) — R/W.

0 = Disable. SMI generation based on a Hot-Plug event is disabled.

1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.

Power Management SMI Enable (PMME) — R/W.

0 = Disable. SMI generation based on a power management event is disabled.

1 = Enables the root port to generate SMI whenever a power management event is

detected.

Bit Description

Port # Addre ss

1 FEC1_0000h – FEC1_7FFFh

2 FEC1_8000h – FEC1_FFFFh

3 FEC2_0000h – FEC2_7FFFh

4 FEC2_8000h – FEC2_FFFFh

5 FEC3_0000h – FEC3_7FFFh

6 FEC3_8000h – FEC3_FFFFh

Intel ® ICH7 Family Datasheet 693

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.45 SMSCS—SMI/SCI Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: DCh–DFh Attribute: R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

Power Management SCI Status (PMCS) — R/WC.

0 = Interrupt Not needed.

1 = PME control logic needs to generate an interrupt, and this interrupt has been

routed to generate an SCI.

Hot Plug SCI Status (HPCS) — R/WC.

0 = Interrupt Not needed.

1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been

routed to generate an SCI.

29:5 Reserved

Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC.

0 = No change

1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5:5A, bit 8) transitioned from 0-to-1, and

MPC.HPME (D28:F0/F1/F2/ F3/F4/F5:D8, bit 1) is set. When this bit is set, an SMI#

will be generated.

Hot Plug Command Completed SMI Status (HPCCM) — R/WC.

0 = No change

1 = SLSTS.CC (D28:F0/F1/F2/F3/F4/F5:5A, bit 4) transitioned from 0-to-1, and

MPC.HPME (D28:F0/F1/F2/F 3/F4/F5:D8, bi t 1) is set. When this bit is set, an SMI#

will be generated.

Hot Plug Attention Button SMI Status (H PABM) — R/WC.

0 = No change

1 = SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5:5A, bit 0) transitioned from 0-to-1, and

MPC.HPME (D28:F0/F1/F2/F 3/F4/F5:D8, bi t 1) is set. When this bit is set, an SMI#

will be generated.

Hot Plug Presence Detect SMI Status (HPPDM) — R/WC.

0 = No change

1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5:5A, bit 3) transitions from 0-to-1, and

MPC.HPME (D28:F0/F1/F2/F 3/F4/F5:D8, bi t 1) is set. When this bit is set, an SMI#

will be generated.

Power Management SMI Status (PMMS) — R/WC.

0 = No change

1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5:60, bit 16) transitions from 0-to-1, and

MPC.PMME (D28:F0/F1/F2/F3/F4/F5:D8, bit 1) is set.

PCI Express* Configuration Registers (Desktop and Mobile Only)

694 Intel ® ICH7 Family Datasheet

18.1.46 RPDCGEN - Root Port Dynamic Clock Gating Enable

(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)

Address Offset: E1h Attribute: R/W

Default Value: 00h Size: 8-bits

18.1.47 IPWS—Intel® PRO/Wireless 3945ABG Status

(PCI Express—D28:F0/F1/F2/F3/F4/F5) (Mobile Only)

Address Offset: E2h–E3h Attribute: RO

Default Value: 0007h Size: 16 bits

Bits Description

7:4 Reserved. RO

Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW.

0 = Disables dynamic clock gating of the shared resource link clock domain.

1 = Enables dynamic clock gating on the root port shared resouce link clock domain.

Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for

ports 5–6.

Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW.

0 = Disable s dynamic clock gating of the shared resource backbone clock domain.

1 = Enables dynamic clock gating on the root port shared resouce backbone clock

domain.

Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for

ports 5–6.

1Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW.

0 = Disables dynamic clock gating of the root port link clock domain.

1 = Enables dynamic clock gating on the root port link clock domain.

0Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW.

0 = Disables dynamic clock gating of the root port backbone clock domain.

1 = Enables dynamic clock gating on the root port backbone clock domain.

Bit Description

15 Intel PRO/Wireless 3945ABG Status (IPWSTAT) — RO. This bit is set if the link

has trained to L0 in Intel PRO/Wireless 3945ABG mode.

14:0 Reserved

Intel ® ICH7 Family Datasheet 695

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.48 VCH—Virtual Channel Capability Header Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 100h–103h Attribute: RO

Default Value: 18010002h Size: 32 bits

18.1.49 VCAP2—Virtual Channel Capability 2 Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 108h–10Bh Attribute: RO

Default Value: 00000001h Size: 32 bits

18.1.50 PVC—Port Virtual Channel Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 10Ch–10Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

Bit Description

31:20 Next Capability Offset (NCO) — RO. This field indicates the next item in the list.

19:16 Capability Version (CV) — RO. This field indicates that this is v ersion 1 of t he capabi lit y

structure by the PCI SIG.

15:0 Capability ID (CID) — RO. This field indicates that this is the Virtual Channel capability

item.

Bit Description

31:24 VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present for

VC arbitration since it is fixed.

23:0 Reserved.

Bit Description

15:4 Reserved.

3:1 VC Arbitration Select (AS) — R/W. This field indicates which VC should be

programmed in the VC arbitration table. The root port takes no action on the setting of

this field since there is no arbitration table.

0Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table

programmed should be loaded into the VC arbitration table. This bit always returns 0

when read.

PCI Express* Configuration Registers (Desktop and Mobile Only)

696 Intel ® ICH7 Family Datasheet

18.1.51 PVS — Port Virtual Channel Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 10Eh–10Fh Attribute: RO

Default Value: 0000h Size: 16 bits

18.1.52 V0CAP — Virtual Channel 0 Resource Capability Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 110h–113h Attribute: RO

Default Value: 00000001h Size: 32 bits

Bit Description

15:1 Reserved.

0VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of

the VC Arbitration table when it is being updated. This field is always 0 in the root port

since there is no VC arbitration table.

Bit Description

31:24 Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table

since the arbitration is fixed.

23 Reserved.

22:16 Maximum Time Sl ots (MTS) — RO . This VC implem ents fixed ar bitr ation; therefo re, this

field is not used.

15 Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable

transactions.

14 Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not ju st

advanced packet switchin g transactions.

13:8 Reserved.

7:0 Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port

arbitration.

Intel ® ICH7 Family Datasheet 697

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.53 V0CTL — Virtual Channel 0 Resource Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 114h–117h Attribute: R/W, RO

Default Value: 800000FFh Size: 32 bits

18.1.54 V0STS — Virtual Channel 0 Resource Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 11Ah–11Bh Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31 Virtual Channe l Enable (EN) — RO. Always set to 1. Virtual Chan nel 0 cannot be

disabled.

30:27 Reserved.

26:24 Virtual Ch annel Ident ifier (VCID) — RO. This field indicates the ID to use for this virtual

channel.

23:20 Reserved.

19:17 Port Arbitration Select (PAS) — R/W. This field indicates which port table is being

programmed. The root complex takes no action on this setting since the arbitration is

fixed and there is no arbitration table.

16 Load Port Arbitration Table (LA T) — RO. The r oot port does not implement an arbitration

table for this virtual channel.

15:8 Reserved.

7:1

Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates which

transaction classes are mapped to this virtual channel. When a bit is set, this

transaction class is mapped to the virtual channel.

0 Reserved. Transaction class 0 must always be mapped to VC0.

Bit Transaction Cl ass

7 Transaction Class 7

6 Transaction Class 6

5 Transaction Class 5

4 Transaction Class 4

3 Transaction Class 3

2 Transaction Class 2

1 Transaction Class 1

0 Transaction Class 0

Bit Description

15:2 Reserved.

1VC Negotiation Pending (NP) — RO.

0 = Negotiation is not pending.

1 = Virtual Channel is still being negotiated with ingress ports.

0Port Arbitration Tables Status (ATS). There is no port arbitration table for this VC; this

bit is reserved as 0.

PCI Express* Configuration Registers (Desktop and Mobile Only)

698 Intel ® ICH7 Family Datasheet

18.1.55 UES — Uncorrectable Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 144h–147h Attribute: R/WC, RO

Default Value: 00000000000x0xxx0x0x0000000x0000bSize:32 bits

This register maintains its state through a platform reset. It loses its state upon

suspend.

Bit Description

31:21 Reserved

20 Unsupported Request Error Status (URE) — R/WC.

0 = Unsupported request was Not received.

1 = Unsupported request was received.

19 ECRC Error Status (EE) — RO. ECRC is not supported.

18 Malformed TLP Status (MT) — R/WC.

0 = Malformed TLP was Not received.

1 = Malformed TLP was received.

17 Receiver Overflow Status (RO) — R/WC.

0 = Receiver overflow did Not occur.

1 = Receiver overflow occurred.

16 Unexpected Completion Status (UC) — R/WC.

0 = Unexpected completion was Not received.

1 = Unexpected completion was received.

15 Completion Abort Status (CA) — R/WC.

0 = Completer abort was Not received.

1 = Completer abort was received.

14 Completion Timeout Status (CT) — R/WC.

0 = Completion did Not time out.

1 = Completion timed out.

13 Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not

supported.

12 Poisoned TLP Status (PT) — R/WC.

0 = Poisoned TLP was Not received.

1 = Poisoned TLP was received.

11:5 Reserved

4Data Link Protocol Error Status (DLPE) — R/WC.

0 = Data link protocol error did Not occur.

1 = Data link protocol error occurred.

3:1 Reserved

0 Training Error Status (TE) — RO. Training Errors not supported.

Intel ® ICH7 Family Datasheet 699

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.56 UEM — Uncorrectable Error Mask

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 148h–14Bh Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

When set, the corresponding error in the UES register is masked, and the logged error

will cause no action. When cleared, the corresponding error is enabled.

Bit Description

31:21 Reserved

Unsupported Request Error Mask (URE) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

19 ECRC Error Mask (EE) — RO. ECRC is not supported.

Malformed TL P Ma s k (MT) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

Receiver Overflow Mask (RO) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

Unexpected Completion Mask (UC) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

Completion Abort Mask (CA) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

Completion Timeout Mask (CT) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

13 Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not

supported.

Poisoned TLP Mask (PT) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

11:5 Reserved

PCI Express* Configuration Registers (Desktop and Mobile Only)

700 Intel ® ICH7 Family Datasheet

18.1.57 UEV — Uncorrectable Error Severity

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 14Ch–14Fh Attribute: RO

Default Value: 00060011h Size: 32 bits

Data Link Protocol Error Mask (DLPE) — R/WO.

0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

enabled.

1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5:144) is

masked.

3:1 Reserved

0 Training Error Mask (TE) — RO. Training Errors not supported

Bit Description

31:21 Reserved

20 Unsupported Request Error Severity (URE) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

19 ECRC Error Severity (EE) — RO. ECRC is not supported.

18 Malformed TLP Severity (MT) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

17 Receiver Over flo w S everity (RO) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

16 Unexpected Completion Severity (UC) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

15 Completion Abort Severity (CA) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

14 Completion Timeout Severity (CT) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

13 Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not

supported.

12 Poisoned TLP Severity (PT) — RO.

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

11:5 Reserved

4Data Link Protocol Error Severity (DLPE) — RO.

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

3:1 Reserved

0 Training Error Severity (TE) — RO. TE is not supported.

Intel ® ICH7 Family Datasheet 701

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.58 CES — Correctable Error Status Regi ster

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 150h–153h Attribute: R/WC

Default Value: 00000000h Size: 32 bits

18.1.59 CEM — Correctable Error Mask Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 154h–157h Attribute: R/WO

Default Value: 00000000h Size: 32 bits

When set, the corresponding error in the CES register is masked, and the logged error

will cause no action. When cleared, the corresponding error is enabled.

Bit Description

31:13 Reserved

12 Replay Timer Timeout Status (RTT) — R/WC.

0 = Replay timer did Not time out.

1 = Replay timer timed out.

11:9 Reserved

8Replay Number Rollover Status (RNR) — R/WC.

0 = Replay number did Not roll over.

1 = Replay number rolled over.

7Bad DLLP Status (BD) — R/WC.

0 = Bad DLLP was Not received.

1 = Bad DLLP was received.

6Bad TLP Status (BT) — R/WC.

0 = Bad TLP was Not received.

1 = Bad TLP was received.

5:1 Reserved

0Receiver Error Status (RE) — R/WC.

0 = Receiver error did Not occur.

1 = Receiver error occurred.

Bit Description

31:13 Reserved

12 Replay Timer Timeout Mask (RTT) — R/WO.

0 = No mask

1 = Mask for replay timer timeout.

11:9 Reserved

8Replay Number Rollover Mask (RNR) — R/WO.

0 = No mask

1 = Mask for replay number rollover.

7Bad DLLP Mask (BD) — R/WO.

0 = No mask

1 = Mask for bad DLLP reception.

PCI Express* Configuration Registers (Desktop and Mobile Only)

702 Intel ® ICH7 Family Datasheet

18.1.60 AECC — Advanced Error Capabilities and Control Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 158h–15Bh Attribute: RO

Default Value: 00000000h Size: 32 bits

18.1.61 RES — Root Error Status Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 170h–173h Attribute: R/WC, RO

Default Value: 00000000h Size: 32 bits

6Bad TLP Mask (BT) — R/WO.

0 = No mask

1 = Mask for bad TLP reception.

5:1 Reserved

0Receiver Error Mask (RE) — R/WO.

0 = No mask

1 = Mask for receiver errors.

Bit Description

31:9 Reserved

8 ECRC Check Enable (ECE) — RO. ECRC is not supported.

7 ECRC Check Capable (ECC) — RO. ECRC is not supported.

6 ECRC Generation Enable (EGE) — RO. ECRC is not supported.

5 ECRC Generation Capable (EGC) — RO. ECRC is not supported.

4:0 First Error Pointer (FEP) — RO.

Bit Description

31:27 Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error

interrupt allocated.

26:4 Reserved

3Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel® ICH7, only

one error will be captured.

2ERR_FATAL/NONFATAL Received (ENR) — R/WC.

0 = No error message received.

1 = Either a fatal or a non-fatal error message is received.

1Multiple ERR_COR Received (MCR ) — RO. F o r ICH7, only one error wil l be captured.

0ERR_COR Received (CR) — R/WC.

0 = No error message received.

1 = A correctable error message is received.

Intel ® ICH7 Family Datasheet 703

PCI Express* Configuration Registers (Desktop and Mobile Only)

18.1.62 RCTCL — Root Complex Topology Capability List Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 180–183h Attribute: RO

Default Value: 00010005h Size: 32 bits

18.1.63 ESD — Element Self Description Regi ster

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 184h–187h Attribute: RO

Default Value: See Description Size: 32 bits

Bit Description

31:20 Next Capability (NEXT) — RO. This field indicates the next item in the list, in this

case, end of list.

19:16 Capability Version (CV) — RO. This field indicate s the version of the capability

structure.

15:0 Capability ID (CID) — RO. This field indicates this is a root complex topology

capability.

Bit Description

31:24

Port Number (PN) — RO. This field indicates the ingress port number for the root

port. There is a different value per port:

23:16

Component ID (CI D) — RO. This field returns the value of the ESD.CID field (Chipset

Configuration Space: Offset 0104h:bits 23:16) of the chip c onfigur ation sect ion, that is

programmed by platform BIOS, since the root port is in the same component as the

RCRB.

15:8 Number of Link Entries (NLE) — RO. (Default value is 01h). This field indicates one

link entry (corresponding to the RCRB).

7:4 Reserved.

3:0 Element Type (ET) — RO. (Default value is 0h). This field indicates that the elem ent

type is a root port.

Port # Value

1 01h

2 02h

3 03h

4 04h

5 05h

6 06h

PCI Express* Configuration Registers (Desktop and Mobile Only)

704 Intel ® ICH7 Family Datasheet

18.1.64 ULD — Upstream Link Description Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 190h–193h Attribute: RO

Default Value: 00000001h Size: 32 bits

18.1.65 ULBA — Upstream Link Base Address Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 198h–19Fh Attribute: RO

Default Value: See Description Size: 64 bits

18.1.66 PEETM — PCI Express Extended Test Mode Register

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 318h Attribute: RO

Default Value: See Description Size: 8 bits

Bit Description

31:24 Target Port Number (PN) — RO. This field indicates the port number of the RCRB.

23:16

Target Component ID (TCID) — RO. This fi eld returns the v alue of the ESD .CID field

(Chipset Configu ration Sp ace: Offset 0104h: b its 23:16) of th e chip configuration

section, that is programmed by platform BIOS, since the root port is in the same

component as the RCRB.

15:2 Reserved.

1Link Type (LT) — RO. This bit indicates that the link points to the Intel® ICH7 RCRB.

0Link Valid (LV) — RO. This bit indicates that this link entry is valid.

Bit Description

63:32 Base Address Upper (BAU) — RO. The RCRB of the Intel® ICH7 is in 32-bit space.

31:0 Base Address Lower (BAL) — RO. This field matches the RCBA register

(D31:F0:Offset F0h) value in the LPC bridge.

Bit Description

7:3 Reserved

Scrambler Bypass Mode (BAU) — R/W.

0 = Normal operation. Scrambler and descrambler are used.

1 = Bypasses the dat a scr ambler in the tr ansmit direction and the data de-scr ambler in

the receive direction.

NOTE: This functionality intended for debug/testing only.

NOTE: If bypassing scrambler with Intel® ICH7 root port 1 in x4 configuration, each

ICH7 root port must have this bit set.

1:0 Reserved

Intel ® ICH7 Family Datasheet 705

Intel® High Definition Audio Controller Registers (D27:F0)

19 Intel® High Definition Audio

Controller Registers (D27:F0)

The Intel® High Definition Audio controller resides in PCI Device 27, Function 0 on bus

0. This function contains a set of DMA engines that are used to move samples of

digitally encoded data between system memory and external codecs.

Note: All registers in this function (including memory-mapped registers) must be addressable

in byte, word, and D-word quantities. The software must always make register

accesses on natural boundaries (i.e. D-word accesses must be on D-word boundaries;

word accesses on word boundaries, etc.) In addition, the memory-mapped register

space must not be accessed with the LOCK semantic exclusive-access mechanism. If

software attempts ex clusive-access mechanisms to the Intel High Definition Audio

memory-mapped space, the resu lt s are und ef i ned .

Note: Users interested in providing feedback on the Intel High Definition Audio specification

or planning to implement the Intel High Definition Audio specification into a future

product will need to execute the Intel® High Definition Audio Specification Developer’s

Agreement. For more information, contact nextgenaudio@intel.com.

19.1 Intel® High Definition Audio PCI Configuration

Space (Intel® High Definition Audio— D27:F0)

Note: Address locations that are not shown should be treated as Reserved.

Table 19-1. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 1 of 2)

Offset Mnemonic Register Name Default Access

00h–01h VID Vendor Identification 8086h RO

02h–03h DID Device Identific ation See register

description. RO

04h–05h PCICMD PCI Command 0000h R/W, RO

06h–07h PCISTS PCI Status 0010h R/WC, RO

08h RID Revision Identi fic ation See register

description. RO

09h PI Programming Interface 00h RO

0Ah SCC Sub Class Code 03h RO

0Bh BCC Base Class Code 04h RO

0Ch CLS Cache Line Size 00h R/W

0Dh LT L atency Time r 00h RO

0Eh HEADTYP Header Type 00h RO

10h–13h HDBARL Intel® High Definition Audio Lower Base

Address (Memory) 00000004h R/W, RO

14h–17h HDBARU Intel® High Definition Audio Upper Base

Address (Memory) 00000000h R/W

2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO

2Eh–2Fh SID Subsystem Identification 0000h R/WO

34h CAPPTR Capability List Pointer 50h RO

Intel® High Definition Audio Controller Registers (D27:F0)

706 Intel ® ICH7 Family Datasheet

3Ch INTLN Interrupt Line 00h R/W

3Dh INTPN Interrupt Pin See Register

Description RO

40h HDCTL Intel High Definition Audio Control 00h R/W, RO

44h TCSEL Traffic Class Select 00h R/W

4Ch DCKCTL Docking Control (Mobile Only) 00h R/W, RO

4Dh DCKSTS Docking Status (Mobile Only) 80h R/WO, RO

50h–51h PID PCI Power Management Capability ID 6001h RO

52h–53h PC Power Management Capabilities C842 RO

54h–57h PCS Power Management Control and Status 00000000h R/W, RO,

R/WC

60h–61h MID MSI Capability ID 7005h RO

62h–63h MMC MSI Message Control 0080h R/W, RO

64h–67h MMLA MSI Message Lower Address 00000000h R/W, RO

68h–6Bh MMUA SMI Message Upper Address 00000000h R/W

6Ch–6Dh MMD MSI Message Data 0000h R/W

70h–71h PXID PCI Express* Capability Identifiers

(Desktop and Mobile Only) 0010h RO

72h–73h PXC PCI Express Capabilities (Desktop and

Mobile Only) 0091h RO

74h–77h DEVCAP Device Capabilities 00000000h RO, R/WO

78h–79h DEVC Device Control 0800h R/W, RO

7Ah–7Bh DEVS Device Status 0010h RO

100h–103h VCCAP Virtual Channel Enhanced Capability

Header 13010002h RO

104h–107h PVCCAP1 Port VC Capability Register 1 00000001h RO

108h–10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO

10Ch–10D PVCCTL Port VC Control 0000h RO

10Eh–10Fh PVCSTS Port VC Status 0000h RO

110h–103h VC0CAP VC0 Resource Capability 00000000h RO

114h–117h VC0CTL VC0 Resource Control 800000FFh R/W, RO

11Ah–11Bh VC0STS VC0 Resource Status 0000h RO

11Ch–11Fh VCiCAP VCi Resource Capability 00000000h RO

120h–123h VCiCTL VCi Resource Control 00000000h R/W, RO

126h–127h VCiSTS VCi Resource Status 0000h RO

130h–133h RCCAP Root Complex Link Declaration Enhanced

Capability Header 00010005h RO

134h–137h ESD Element Self Description 0F000100h RO

140h–143h L1DESC Link 1 Description 00000001h RO

148h–14Bh L1ADDL Link 1 Lower Address See Register

Description RO

14Ch–14Fh L1ADDU Link 1 Upper Address 00000000h RO

Table 19-1. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 2 of 2)

Offset Mnemonic Register Name Default Access

Intel ® ICH7 Family Datasheet 707

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.1 VID—Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 00h-01h Attribute: RO

Default Value: 8 086h Size: 16 bits

19.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 02h–03h Attribute: RO

Default Value: See bit description Size: 16 bits

Bit Description

15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h

Bit Description

15:0 Device ID — RO. This is a 16-bit value assigned to the Intel® ICH7 Intel High

Definition Audio controller. Refer to the Intel® I/O Controller Hub 7 (ICH7) Family

Specification Update for the value of the Device ID Register.

Intel® High Definition Audio Controller Registers (D27:F0)

708 Intel ® ICH7 Family Datasheet

19.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 04h–05h Attribute: R/W, RO

Default Value: 0000h Size: 16 bits

Bit Description

15:11 Reserved

Interrupt Disable (I D) — R/W.

0= The INTx# signals may be asserted.

1= The Intel® High Definition Audio controller’s INTx# signal will be de-asserted

NOTE: This bit does not affect the generation of MSIs.

9 Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.

8SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the Intel® ICH7 Intel

High Definition Audio Controller.

7 Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.

6 Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.

5 VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.

4Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to

3 Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

Bus Master Enable (BME) — R/W. Controls standard PCI Express* bus mastering

capabilities for Memory and I/O, reads and writes. Note that this bit also controls MSI

generation since MSIs are essentially memory writes.

0 = Disable

1 = Enable

Memory Space Enable (MSE) — R/W. Enables memory space addresses to the

Intel High Definition Audio controller.

0 = Disable

1 = Enable

0I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio

controller does not implement I/O space.

Intel ® ICH7 Family Datasheet 709

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0)

Offset Address: 06h–07h Attribute: RO, R/WC

Default Value: 0010h Size: 16 bits

19.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 08h Attribute: RO

Default Value: See bit description Size: 8 Bits

Bit Description

15 Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.

14 SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.

Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it.

0 = No master abort received.

1 = The Intel® High Definition Audio controller sets this bit when, as a bus master, it

receives a master abort. When set, the Intel High Definition Audio controller

clears the run bit for the channel that received the abort.

12 Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.

11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.

10:9 DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.

8 Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.

7 Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0.

6 Reserved.

5 66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.

4Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller

contains a capabilities pointer list. The first item is pointed to by looking at

configuration offset 34h.

Interrupt Status (IS) — RO.

0 = This bit is 0 after the interrupt is cleared.

1 = This bit is 1 when the INTx# is asserted.

Note that this bit is not set by an MSI.

2:0 Reserved.

Bit Description

7:0 R e vision ID — RO. Re fer to the Intel® I/O Controller Hub 7 (ICH7) Family Specification

Update for the value of the Revision ID Register.

Intel® High Definition Audio Controller Registers (D27:F0)

710 Intel ® ICH7 Family Datasheet

19.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0)

Offset: 09h Attribute: RO

Default Value: 00h Size: 8 bits

19.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Ah Attribute: RO

Default Value: 03h Size: 8 bits

19.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Bh Attribute: RO

Default Value: 04h Size: 8 bits

19.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Ch Attribute: R/W

Default Value: 00h Size: 8 bits

19.1.10 LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Dh Attribute: RO

Default Value: 00h Size: 8 bits

Bit Description

7:0 Program ming Interface — RO.

Bit Description

7:0 Sub Class Code (SCC) — RO.

03h = Audio Device

Bit Description

7:0 Base Class Code (BCC) — RO.

04h = Multimedia device

Bit Description

7:0 Cache Line Size — R/W. Implemented as R/W register, but has no functional impact to

the Intel® ICH7

Bit Description

7:0 Latency Timer — RO. Hardwired to 00

Intel ® ICH7 Family Datasheet 711

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.11 HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 0Eh A ttribute: RO

Default Value: 00h Size: 8 bits

19.1.12 HDBARL—Intel® High Definition Audio Lower Base Address

(Intel® High Definition Audio—D27:F0)

Address Offset: 10h-13h Attribute: R/W, RO

Default Value: 00000004h Size: 32 bits

19.1.13 HDBARU—Intel® High Definition Audio Upper Base Address

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 14h-17h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

7:0 Header Type — RO. Hardwired to 00.

Bit Description

31:14 Lower Base Address (LBA) — R/W. This field contains the base address for the

Intel® High Definiti on Audio controller’s memory mapped configuration registers; 1 6 KB

are requested by hardwiring bits 13:4 to 0s.

13:4 RO. Hardwired to 0s

3 Prefetchable (PREF) — RO. Hardwired to 0 to indicate that this BAR is NOT prefetchable.

2:1 Address Range (ADDRNG) — RO. Hardwired to 10b, indicating that this BAR can be

located anywhere in 64-bit address space.

0Space Type (SPTYP) — RO. Hardwired to 0. Indicates this BAR is located in memory

space.

Bit Description

31:0 Upper Base Address (UBA) — R/W. This field provides the upper 32 bits of the Base

address for the Intel® High Definition Audio controller’s memor y mapped configuration

registers.

Intel® High Definition Audio Controller Registers (D27:F0)

712 Intel ® ICH7 Family Datasheet

19.1.14 SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 2Ch–2Dh Attribute: R/WO

Default Value: 0000h Size: 16 bits

The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),

enable the operating environment to distinguish one audio subsystem from the

other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

19.1.15 SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 2Eh–2Fh Attribute: R/WO

Default Value: 0000h Size: 16 bits

The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch)

make it possible for the operating environment to distinguish one audio subsystem

from the other(s).

This register is implemented as write-once register. Once a value is written to it, the

value can be read back. Any subsequent writes will have no effect.

This register is not affected by the D3HOT to D0 transition.

Bit Description

15:0 Subsystem Vendor ID — R/WO.

Bit Description

15:0 Subsystem ID — R/WO.

Intel ® ICH7 Family Datasheet 713

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.16 CAPPTR—Capabilities Pointer Register (Audio—D30:F2)

Address Offset: 34h Attribute: RO

Default Value: 50h Size: 8 bits

This register indicates the offset for the capability pointer.

19.1.17 INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 3Ch Attribute: R/W

Default Value: 00h Size: 8 bits

19.1.18 INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 3Dh Attribute: RO

Default Value: See Description Size: 8 bits

Bit Description

7:0 Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer

offset is offset 50h (Power Management Capability)

Bit Description

7:0 Interrupt Line (INT_LN) — R/W. This data is not us ed by t he Inte l® ICH7. It is used

to communicate to software the interrupt line that the interrupt pin is connected to.

Bit Description

7:4 Reserved.

3:0 Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config

Regi st ers : Offse t 3110h:

bits 3:0).

Intel® High Definition Audio Controller Registers (D27:F0)

714 Intel ® ICH7 Family Datasheet

19.1.19 HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 40h Attribute: R/W, RO

Default Value: 00h Size: 8 bits

Bit Description

7:4 Reserved.

BITCLK Det ect Cl ear (CLKDETCLR) — R/W.

0 = lock detect circuit is operational and maybe enabled.

1 = Writing a 1 to this bit clears bit 1 (CLKDET#) in this register. CLKDET# bit remains

clear when this bit is set to 1.

NOTE: This bit is not affected by the D3HOT to D0 transition.

BITCLK Detect Enable (CLKDETEN) — R/W.

0 = Latches the current state of bit 1 (CLKDET#) in this register

1 = Enables the clock detection circuit

NOTE: This bit is not affected by the D3HOT to D0 transition.

BITCLK Detected Inverted (CLKDET#) — RO. This bit is modified by hardware.

It is set to 0 when the Intel® ICH7 detects that the BITCLK is toggling, indicating the

presence of an AC’97 codec on the lin k.

NOTES:

1. Bit 2 (CLKDETEN) and bit 3 (CLKDET CLR) in this register control the operation of

this bit and must be manipulated correctly in order to get a valid CLKDET#

indicator.

2. This bit is not affected by the D3HOT to D0 transition.

Intel® High Definition Audio/AC ‘97 Signal Mode — R/W. This bit selects the

shared Intel High Definition Audio/AC ‘97 signals.

0 = AC ’97 mode is selected (Default)

1 = Intel High Definition Audio mode is selected

NOTES:

1. This bit has no effect on the visibility of the Intel High Definition Audio and AC

’97 function configuration space.

2. This bit is in the resume well and only clear on a power -on reset. Software must

not makes assumptions about the reset state of this bit and must set it

appropriately.

3. For the ICH7-U Ultra Mobile, this bit must be programmed to 1.

Intel ® ICH7 Family Datasheet 715

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.20 TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 44h Attribute: R/W

Default Value: 00h Size: 8 bits

This register assigned the value to be placed in the TC field. CORB and RIRB data will

always be assigned TC0.

19.1.21 DCKCTL—Docking Control Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 4Ch Attribute: R/W, RO

Default Value: 00h Size: 8 bits

Bit Description

7:3 Reserved.

2:0

Intel® HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W. This

data, and buffer descriptor transactions.

000 = TC0

001 = TC1

010 = TC2

011 = TC3

100 = TC4

101 = TC5

110 = TC6

111 = TC7

NOTE: These bits are not reset on D3HOT to D0 transition; however, they are reset by

PLTRST#.

Bit Description

7:1 Reserved.

Dock Attach (D A) — R/W / RO:

0 = Software writes a 0 to this bit to initiate the undocking sequence on the

AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the undocking sequence is

complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0.

1 = Software writes a 1 to this bit to initiate the docking sequence on the

AZ_DOCK_EN# and AZ_DOCK_RST# signals. When the docking sequence is

complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1.

NOTE: Software must check the state of the Dock Mated (GSTS.DM) bit prior to writing

to the Dock Attach bit. Software shall only change the DA bit from 0 to 1 when

DM=0. Likewise, software shall only change the DA bit from 1 to 0 when DM=1.

If these rules are not followed, the results are undefined.

NOTE: This bit is Read Only when the DCKSTS.DS bit = 0.

Intel® High Definition Audio Controller Registers (D27:F0)

716 Intel ® ICH7 Family Datasheet

19.1.22 DCKSTS—Docking Status Register

(Intel® High Definition Audio Controller—D27:F0) (Mobile

Only)

Address Offset: 4Dh Attribute: R/WO, RO

Default Value: 80h Size: 8 bits

19.1.23 PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 50h–51h Attribute: RO

Default Value: 6001h Size: 16 bits

19.1.24 PC—Power Management Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 52h–53h Attribute: RO

Default Value: C842h Size: 16 bits

Bit Description

7 BIOS is required to clear this bit.

6:1 Reserved.

0) Reserved.

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 60h. Points to the next capability structure

(MSI)

7:0 Cap ID (CAP) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power

management capability.

Bit Description

15:11 PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3

and D0 states.

10 D2 Supp ort — RO. Hardwired to 0. Indicates that D2 state is not supported.

9 D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported.

8:6 Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current

required when in the D3COLD state.

5Device Specifi c Initialization (D SI) — RO. Hardwired to 0. Indicates that no device

specific initialization is required.

4 Reserved

3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.

2:0 Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power

Management Specification.

Intel ® ICH7 Family Datasheet 717

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.25 PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 54h–57h Attribute: RO, R/W, R/WC

Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Data — RO. Does not apply. Hardwired to 0.

23 Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.

22 B2/B3 Support — RO. Does not apply. Hardwired to 0.

21:16 Reserved.

PME Status (PMES) — R/WC.

0 = Software clears the bit by writing a 1 to it.

1 = This bit is set when the Intel® High Definition Audio controller would normally

assert the PME# si gnal independent of the s tate of the PME_EN bit (bit 8 in this

This bit is in the resume well and only cleared on a power-on reset. Software must not

make assumptions about the reset state of this bit and must set it appropriately.

14:9 Reserved

PME Enable (PMEE) — R/W.

0 = Disable

1 = when set and if corresponding PMES also set, the Intel High Definition Audio

controller sets the AC97_STS bit in the GPE0_STS register (PMBASE +28h). The

AC97_STS bit is shared by AC ’97 and Intel High Definition Audio functions since

they are mutually exclusive.

This bit is in the resume well and only cleared on a power-on reset. Software must not

make assumptions about the reset state of this bit and must set it appropriately.

7:2 Reserved

1:0

Power State (PS) — R/W. This field is used both to determine the current power state

of the Intel High Definition Audio controller and to set a new power state.

00 = D0 state

11 = D3HOT state

Others = reserved

NOTES:

1. If software attempts to write a value of 01b or 10b in to this field, the write

operation must complete normally; however, the data is discarded and no state

change occurs.

2. When in the D3HOT states, the Intel High D efinition Audio controller’s

configuration space is available, but the I/O and memory space are not.

Additionally, interrupts are blocked.

3. When software changes this v alue from D3HOT state to the D0 state, an internal

warm (soft) reset is generated, and software must re-initialize the function.

Intel® High Definition Audio Controller Registers (D27:F0)

718 Intel ® ICH7 Family Datasheet

19.1.26 MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 60h–61h Attribute: RO

Default Value: 7005h Size: 16 bits

19.1.27 MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 62h–63h Attribute: RO, R/W

Default Value: 0080h Size: 16 bits

19.1.28 MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 64h–67h Attribute: RO, R/W

Default Value: 00000000h Size: 32 bits

19.1.29 MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 68h–6Bh Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability

structure.

7:0 Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability

Bit Description

15:8 Reserved

764b Address Capability (64ADD) — RO. Hardwired to 1 indic ating the ability to gener ate

a 64-bit message address

6:4 Multiple Message Enable (MME) — RO. Normally this is a R/W register. However, since

only 1 message is supported, these bits are hardwired to 000 = 1 message.

3:1 Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1

message.

0MSI Enable (ME) — R/W.

0 = an MSI may not be generated

1 = an MSI will be generated instead of an INTx signal.

Bit Description

31:2 Message Lower Address (MLA) — R/W. Lower address used for MSI message.

1:0 Reserved.

Bit Description

31:0 Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI

message.

Intel ® ICH7 Family Datasheet 719

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.30 MMD—MSI Message Data Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 6Ch–6Dh Attribute: R/W

Default Value: 0000h Size: 16 bits

19.1.31 PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only)

Address Offset: 70h-71h Attribute: RO

Default Value: 0010h Size: 16 bits

19.1.32 PXC—PCI Express* Capabilities Register (Desktop and

Mobile Only)

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 72h–73h Attribute: RO

Default Value: 0091h Size: 16 bits

Bit Description

15:0 Message Data (MD) — R/W. Data used for MSI message.

Bit Description

15:8 Next Capability (Next) — RO. Hardwired to 0. Indicates that this is the last capability

structure in the list.

7:0 Cap ID (CAP) — RO. Hardwired to 10h. Indicates that this pointer is a PCI Express*

capability structure

Bit Description

15:14 Reserved

13:9 Interrupt Me ssage Number (IMN) — RO. Hardwired to 0.

8 Slot Implemented (SI) — RO. Hardwired to 0.

7:4 Device/Port Type (DPT) — RO. Hardwire d to 1001b. Indicates that t his is a Root

Complex Integrated endpoint device.

3:0 Capability Version (CV) — RO. Hardwired to 0001b. Indicates version #1 PCI Express

capability

Intel® High Definition Audio Controller Registers (D27:F0)

720 Intel ® ICH7 Family Datasheet

19.1.33 DEVCAP—Device Capabilities Regi ster

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 74h–77h Attribute: R/WO, RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:28 Reserved

27:26 Captured Slot Power Limit Scale (SPLS) — RO. Hardwired to 0.

25:18 Captured Slot Power Limit Value (SPLV) — RO. Hardwired to 0.

17:15 Reserved

14 Power Indicator Present — RO. Hardwired to 0.

13 Attention Indicator Present — RO. Hardwired to 0.

12 Attention Button Present — RO. Hardwired to 0.

11:9 Endpoint L1 Acceptable Laten cy — R/WO.

8:6 Endpoint L0s Acceptable Latency — R/WO.

5 Extended Tag Field Support — RO. Hardwired to 0. Indicates 5-bit tag field support

4:3 Phantom Functions Supported — RO. Hardwired to 0. Indicates that ph antom functions

are not supported

2:0 Max Paylo ad Size Supported — RO. Hardwire d to 0. Indicates 128-B maxi mum payl oad

size capability

Intel ® ICH7 Family Datasheet 721

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.34 DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 78h–79h Attribute: R/W, RO

Default Value: 0800h Size: 16 bits

19.1.35 DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 7Ah–7Bh Attribute: RO

Default Value: 0010h Size: 16 bits

Bit Description

15 Reserved

14:12 Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request

size.

No Snoop Enable (NSNPEN) — R/W.

0 = The Intel® High Definition Audio controller will not set the No Snoop bit. In this

case, isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is

not snooped. Isochronous transfers will use VC0.

1 = The Intel High Defi nition Audio con troller is permitted to set the No Snoop bit in the

Requester Attributes of a bus master transaction. In t hi s ca se , VC0 or VC1 m ay be

used for isochronous transfers.

Note: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.

10 Auxiliary P ower Enable — RO. Hardwired to 0, indicating that Intel High Definition Audio

device does not draw AUX power

9 Phantom F unction Enable — RO. Hardwired to 0 disabling phantom functions.

8 Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag.

7:5 Max Payload Size — RO. Hardwired to 0 indicating 128B.

4 Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering.

3 Unsupported Request Reporting Enable — RO. Not implemented. Hardwired to 0.

2 Fatal Error Reporting Enable — RO. Not implem ente d. Hardwired to 0.

1 Non-Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0.

0 Correctable Error Reporting Enable — RO. Not implemented. Hardwired to 0.

Bit Description

15:6 Reserved

Transactions Pending — RO.

0 = Indicates that completions for all non-posted requests have been received.

1 = Indicates that Intel® High Definition Audio controller has issued non-posted

requests that have not been completed.

4AUX Power Detected — RO . Hardwired to 1 indicating the device is connected to resume

power.

3 Unsupported Request Detected — RO. Not implemented. Hardwired to 0.

2 Fatal Error Detected — RO. Not implemented. Hardwired to 0.

1 Non-Fatal Error Detected — RO. Not implemented. Hardwired to 0.

0 Correctable Error Detected — RO. Not implemented. Hardwired to 0.

Intel® High Definition Audio Controller Registers (D27:F0)

722 Intel ® ICH7 Family Datasheet

19.1.36 VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only)

Address Offset: 100h–103h Attribute: RO

Default Value: 13010002h Size: 32 bits

19.1.37 PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0)

(Desktop and Mobile Only)

Address Offset: 104h–107h Attribute: RO

Default Value: 00000001h Size: 32 bits

19.1.38 PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 108h–10Bh Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:20 Next Capability Offset — RO. Hardwired to 130h. Points to the next capabil ity header

that is the Root Complex Link Declaration Enhanced Capability Header.

19:16 Capability Version — RO. Hardwired to 1h.

15:0 PCI Express* Extended Capability — RO. Hardwired to 0002h.

Bit Description

31:12 Reserved.

11:10 Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.

9:8 Reference Clock — RO. Hardwired to 0 since this is an endpoint device.

7 Reserved.

6:4 Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs

to the low priority VC group.

3 Reserved.

2:0 Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition

to VC0) is supported by the Intel® High Definition Audio controller.

Bit Description

31:24 VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table

is not present.

23:8 Reserved.

7:0 VC Arbitration Capability — RO . Hardwired to 0. These bits are not applicable since the

Intel® High Definition Audio controller reports a 0 in the Low Priority Extended VC

Count bits in the PVCCAP1 register.

Intel ® ICH7 Family Datasheet 723

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.39 PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 10Ch–10Dh Attribute: RO

Default Value: 0000h Size: 16 bits

19.1.40 PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 10Eh-10Fh Attribute: RO

Default Value: 0000h Size: 16 bits

19.1.41 VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 110h–113h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

15:4 Reserved.

3:1 VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However,

these bits are not applicable since the Intel® High Definition Audio co ntroller reports a 0

in the Low Priori ty Extended VC Count bits in th e PVCCAP1 register.

0Load VC Arbitration Ta ble — RO. Hardwired to 0 since an arbitration table is not

present.

Bit Description

15:1 Reserved.

0VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not

present.

Bit Description

31:24 Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

23 Reserved.

22:16 Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

15 Reject Snoop Transactions — RO. Hardwired to 0 since this fiel d is not valid for endpoint

devices.

14 Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

13:8 Reserved.

7:0 Port Arbitr ation Capability — RO . Hardwired to 0 since this field is not valid for endpoint

devices.

Intel® High Definition Audio Controller Registers (D27:F0)

724 Intel ® ICH7 Family Datasheet

19.1.42 VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 114h–117h Attribute: R/W, RO

Default Value: 800000FFh Size: 32 bits

19.1.43 VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 11Ah–11Bh Attribute: RO

Default Value: 0000h Size: 16 bits

Bit Description

31 VC0 Enable — RO. Hardwired to 1 for VC0.

30:27 Reserved.

26:24 VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.

23:20 Reserved.

19:17 Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

16 Load Port Arbitr ation Table — RO. Hardwired to 0 since this fie ld is not vali d for endpoint

devices.

15:8 Reserved.

7:0 TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is alw ays mapped VC0. Bits

[7:1] are implemented as R/W bits.

Bit Description

15:2 Reserved.

1VC0 Negotiation Pending — RO. Hardwired to 0 since this bit does not apply to the

integrated Intel® High Definition Audio device.

0Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

Intel ® ICH7 Family Datasheet 725

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.44 VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 11Ch–11Fh Attribute: RO

Default Value: 00000000h Size: 32 bits

19.1.45 VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 120h–123h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

23 Reserved.

22:16 Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

15 Reject Snoop Transactions — RO. Hardwired to 0 since this fiel d is not valid for endpoint

devices.

14 Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

13:8 Reserved

7:0 Port Arbitr ation Capability — RO . Hardwired to 0 since this field is not valid for endpoint

devices.

Bit Description

VCi Enable — R/W.

0 = VCi is disabled

1 = VCi is enabled

NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.

30:27 Reserved.

26:24 VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by

the Intel® ICH7 hardware, but it is R/W to avoid confusing software.

23:20 Reserved.

19:17 Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

16 Load Port Arbitr ation Table — RO. Hardwired to 0 since this field is not valid for endpoint

devices.

15:8 Reserved.

7:0

TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi

resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1]

are implemented as R/W bits. This field is not us ed by the ICH7 hardware, but it is R/W

to avoid confusing software.

Intel® High Definition Audio Controller Registers (D27:F0)

726 Intel ® ICH7 Family Datasheet

19.1.46 VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 126h–127h Attribute: RO

Default Value: 0000h Size: 16 bits

19.1.47 RCCAP—Root Complex Link Declaration Enhanced

Capability Header Register (Intel® High Definition Audio

Controller—D27:F0) (Desktop and Mobile Only)

Address Offset: 130h–133h Attribute: RO

Default Value: 00010005h Size: 32 bits

19.1.48 ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 134h–137h Attribute: RO

Default Value: 0F000100h Size: 32 bits

Bit Description

15:2 Reserved.

1 VCi Negotiation Pending — RO. Does not apply. Hardwired to 0.

0Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for

endpoint devices.

Bit Description

31:20 Next Capability Offset — RO. Hardwired to 0 indicating this is the last capability.

19:16 Capability Version — RO. Hardwired to 1h.

15:0 PCI Express* Extended Capability ID — RO. Hardwired to 0005h.

Bit Description

31:24 Port Number — RO. Hardwired to 0Fh indicating that the Intel® High Definition Audio

controller is assigned as Port #15d.

23:16 Component ID — RO. This field returns the value of the ESD.CID field of the chip

configuration section. ESD.CID is programmed by BIOS.

15:8 Number of Link Entri es — RO. The Intel High Definition Audio only connects to one

device, the Intel® ICH7 egress port. Therefore thi s field reports a value of 1h.

7:4 Reserved.

3:0 Element Type (ELTYP) — RO. The Intel High Definition Audio controller is an integrated

Root Complex Device. Therefore, the field reports a value of 0h.

Intel ® ICH7 Family Datasheet 727

Intel® High Definition Audio Controller Registers (D27:F0)

19.1.49 L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 140h–143h Attribute: RO

Default Value: 00000001h Size: 32 bits

19.1.50 L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 148h–14Bh Attribute: RO

Default Value: See Register Description Size: 32 bits

19.1.51 L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 14Ch–14Fh Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

31:24 Target Port Number — RO. The Intel High Definition Audio controller targets the Intel®

ICH7’s Port #0.

23:16 Target Component ID — RO. This field retu rns the v alue of the ESD .CID fiel d of the chip

configuration section. ESD.CID is programmed by BIOS.

15:2 Reserved.

1 Link Type — RO. Hardwired to 0 indicating Type 0.

0 Link Valid — RO. Hardwired to 1.

Bit Description

31:14 Link 1 Lower Address — RO . Hardwired to match the RCBA register value in the PCI-LPC

bridge (D31:F0:F0h).

13:0 Reserved.

Bit Description

31:0 Link 1 Upper Address — RO. Hardwired to 00000000h.

Intel® High Definition Audio Controller Registers (D27:F0)

728 Intel ® ICH7 Family Datasheet

19.2 Intel® High Definition Audio Memory-Mapped

Configuration Registers

(Intel® High Definition Audio— D27:F0)

The base memory location for these memory mapped configuration registers is

specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The

individual registers are then accessible at HDBAR + Offset as indicated in the following

table.

These memory mapped registers must be accessed in byte, word, or DWord quantities.

Table 19-2. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 1 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

00h–01h GCAP Global Capabilities 4401h RO

02h VMIN Minor Version 00h RO

03h VMAJ Major Version 01h RO

04h–05h OUTPAY Output Payload Capability 003Ch RO

06h–07h INPAY Input Payload Capability 001Dh RO

08h–0Bh GCTL Global Control 00000000h R/W

0Ch–0Dh WAKEEN Wake Enable 0000h R/W

0Eh–0Fh ST ATESTS State Change Status 0000h R/WC

10h–11h GSTS Global Status 0000h R/WC

12h–13h — Reserved 0000h RO

14h–17h ECAP Extended Capabilities (Mobile/Ultra

Mobile Only) 00000001h RO

1 8h–19h OUTSTRMPAY Output Stream Payload Capability 0030h RO

1Ah–1Bh INSTRMPAY Input Stream Payload Capability 0018h RO

1Ch–1Fh — Reserved 00000000h RO

20h–23h INTCTL Interrupt Control 00000000h R/W

24h–27h INTSTS Interrupt Status 00000000h RO

30h–33h WALCLK Wall Clock Counter 00000000h RO

34h–37h SSYNC Stream Sync hro ni zati on 00000000h R/W

40h–43h CORBLBASE CORB Lower Base Address 00000000h R/W, RO

44h–47h CORBUBASE CORB Upper Base Address 00000000h R/W

48h–49h CORBWP CORB Write Pointer 0000h R/W

4Ah–4Bh CORBRP CORB Read Pointer 0000h R/W

4Ch CORBCTL CORB Control 00h R/W

4Dh CORBST CORB Status 00h R/WC

4Eh CORBSIZE CORB Size 42h RO

50h–53h RIRBLBASE RIRB Lower Base Address 00000000h R/W, RO

54h–57h RIRBUBASE RIRB Upper Base Address 00000000h R/W

Intel ® ICH7 Family Datasheet 729

Intel® High Definition Audio Controller Registers (D27:F0)

58h–59h RIRBWP RIRB Write Pointer 0000h R/W, RO

5Ah–5Bh RINTC NT Re s pons e Int errupt Count 0000h R/W

5Ch RIRBCTL RIRB Control 00h R/W

5Dh RIRBSTS RIRB Status 00h R/WC

5Eh RIRBSIZE RIRB Size 42h RO

60h–63h IC Immediate Command 00000000h R/W

64h–67h IR Immediate Response 00000000h RO

68h–69h IRS Immediate Command Status 0000h R/W, R/

70h–73h DPLBASE DMA Position Lower Base Address 00000000h R/W, RO

74h–77h DPUBASE DMA Position Upper Base Address 00000000h R/W

80–82h ISD0CTL Input Stream Descriptor 0 (ISD0)

Control 040000h R/W, RO

83h ISD0STS ISD0 Status 00h R/WC, RO

84h–87h ISD0LPIB ISD0 Link Position in Buffer 00000000h RO

88h–8Bh ISD0CBL ISD0 Cyclic Buffer Length 00000000h R/W

8Ch–8Dh ISD0LVI ISD0 Last Valid Index 0000h R/W

8Eh–8F ISD0FIFOW ISD0 FIFO Watermark 0004h R/W

90h–91h ISD0FIFOS ISD0 FIFO Size 0077h RO

92h–93h ISD0FMT ISD0 Format 0000h R/W

98h–9Bh ISD0BDPL ISD0 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

9Ch–9Fh ISD0BDPU ISD0 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

A0h–A2h ISD1CTL Input Stream Descriptor 1(ISD01)

Control 040000h R/W, RO

A3h ISD1STS ISD1 Status 00h R /WC, RO

A4h–A7h ISD1LPIB ISD1 Link Position in Buffer 00000000h RO

A8h–ABh ISD1CBL ISD1 Cyclic Buffer Length 00000000h R/W

ACh–ADh ISD1LVI ISD1 Last Valid Index 0000h R/W

AEh–AFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W

B0h–B1h ISD1FIFOS ISD1 FIFO Size 0077h RO

B2–B3h ISD1FMT ISD1 Format 0000h R/W

B8–BBh ISD1BDPL ISD1 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

BCh–BFh ISD1BDPU ISD1 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

C0h–C2h ISD2CTL Input Stream Descriptor 2 (ISD2)

Control 040000h R/W, RO

Table 19-2. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 2 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel® High Definition Audio Controller Registers (D27:F0)

730 Intel ® ICH7 Family Datasheet

C3h ISD2STS ISD2 Status 00h R/WC, RO

Ch4–C7h ISD2LPIB ISD2 Link Position in Buffer 00000000h RO

C8h–CBh ISD2CBL ISD2 Cyclic Buffer Length 00000000h R/W

CCh–CDh ISD2LVI ISD2 Last Valid Index 0000h R/W

CEh–CFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W

D0h–D1h ISD2FIFOS ISD2 FIFO Size 0077h RO

D2h–D3h ISD2FMT ISD2 Format 0000h R/W

D8h–DBh ISD2BDPL ISD2 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

DCh–DFh ISD2BDPU ISD2 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

E0h–E2h ISD3CTL Input Stream Descriptor 3 (ISD3)

Control 040000h R/W, RO

E3h ISD3STS ISD3 Status 00h R/WC, RO

E4h–E7h ISD3LPIB ISD3 Link Position in Buffer 00000000h RO

E8h–EBh ISD3CBL ISD3 Cyclic Buffer Length 00000000h R/W

ECh–EDh ISD3LVI ISD3 Last Valid Index 0000h R/W

EEh–EFh ISD3FIFOW ISD3 FIFO Watermark 0004h R/W

F0h–F1h ISD3FIFOS ISD3 FIFO Size 0077h RO

F2h–F3h ISD3FMT ISD3 Format 0000h R/W

F8h–FBh ISD3BDPL ISD3 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

FCh–FFh ISD3BDPU ISD3 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

100h–102h OSD0CTL Output Stream Descriptor 0 (OSD0)

Control 040000h R/W, RO

103h OSD0STS OSD0 Status 00h R/WC, RO

104h–107h OSD0LPIB OSD0 Link Position in Buffer 00000000h RO

108h–10Bh OSD0CBL OSD0 Cyclic Buffer Length 00000000h R/W

10Ch–10Dh OSD0LVI OSD0 Last Valid Index 0000h R/W

10Eh–10Fh OSD0FIFOW OSD0 FIFO Watermark 0004h R/W

110h–111h OSD0FIFOS OSD0 FIFO Size 00BFh R/W

112–113h OSD0FMT OSD0 Format 0000h R/W

118h–11Bh OSD0BDPL OSD0 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

11Ch–11Fh OSD0BDPU OSD0 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

120h–122h OSD1CTL Output Stream Descriptor 1 (OSD1)

Control 040000h R/W, RO

Table 19-2. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 3 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel ® ICH7 Family Datasheet 731

Intel® High Definition Audio Controller Registers (D27:F0)

123h OSD1STS OSD1 Status 00h R/WC, RO

124h–127h OSD1LPIB OSD1 Link Position in Buffer 00000000h RO

128h–12Bh OSD1CBL OSD1 Cyclic Buffer Length 00000000h R/W

12Ch–12Dh OSD1LVI OSD1 Last Valid Index 0000h R/W

12Eh–12Fh OSD1FIFOW OSD1 FIFO Watermark 0004h R/W

130h–131h OSD1FIFOS OSD1 FIFO Size 00BFh R/W

132h–133h OSD1FMT OSD1 Format 0000h R/W

138h–13Bh OSD1BDPL OSD1 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

13Ch–13Fh OSD1BDPU OSD1 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

140h–142h OSD2CTL Output Stream Descriptor 2 (OSD2)

Control 040000h R/W, RO

143h OSD2STS OSD2 Status 00h R/WC, RO

144h–147h OSD2LPIB OSD2 Link Position in Buffer 00000000h RO

148h–14Bh OSD2CBL OSD2 Cyclic Buffer Length 00000000h R/W

14Ch–14Dh OSD2LVI OSD2 Last Valid Index 0000h R/W

14Eh–14Fh OSD2FIFOW OSD2 FIFO Watermark 0004h R/W

150h–151h OSD2FIFOS OSD2 FIFO Size 00BFh R/W

152h–153h OSD2FMT OSD2 Format 0000h R/W

158h–15Bh OSD2BDPL OSD2 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

15Ch–15Fh OSD2BDPU OSD2 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

160h–162h OSD3CTL Output Stream Descriptor 3 (OSD3)

Control 040000h R/W, RO

163h OSD3STS OSD3 Status 00h R/WC, RO

164h–167h OSD3LPIB OSD3 Link Position in Buffer 00000000h RO

168h–16Bh OSD3CBL OSD3 Cyclic Buffer Length 00000000h R/W

16Ch–16Dh OSD3LVI OSD3 Last Valid Index 0000h R/W

16Eh–16Fh OSD3FIFOW OSD3 FIFO Watermark 0004h R/W

170h–171h OSD3FIFOS OSD3 FIFO Size 00BFh R/W

172h–173h OSD3FMT OSD3 Format 0000h R/W

178h–17Bh OSD3BDPL OSD3 Buffer Descriptor List Pointer-

Lower Base Address 00000000h R/W, RO

17Ch–17Fh OSD3BDPU OSD3 Buffer Description List Pointer-

Upper Base Address 00000000h R/W

Table 19-2. Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0) (Sheet 4 of 4)

HDBAR +

Offset Mnemonic Register Name Default Access

Intel® High Definition Audio Controller Registers (D27:F0)

732 Intel ® ICH7 Family Datasheet

19.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 00h Attribute: RO

Default Value: 4401h Size: 16 bits

19.2.2 VMIN—Minor Version Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 02h Attribute: RO

Default Value: 00h Size: 8 bits

19.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 03h Attribute: RO

Default Value: 01h Size: 8 bits

Bit Description

15:12 Number of Output Stream Supported — RO. Hardwired to 0100b indicating that the

Intel® ICH7 Intel® High Definition Audio controller supports 4 output streams.

11:8 Number of Input Stream Supported — RO. Hardwired to 0100b indicating that the ICH7

Intel High Definition Audio controller supports 4 input streams.

7:3 Number of Bidirectional Stream Supported — RO. Hardwired to 0 indicating that the

ICH7 Intel High Definition Audio controller supports 0 bidirectional stream.

2 Reserved.

1Number of Serial Data Out Signals — RO. Hardwired to 0 indicating that the ICH7 Intel

High Definition Audio controller supports 1 serial data output signal.

064-bit Address Supported — RO. Hardwired to 1b indicating that the ICH7 Intel High

Definition Audio controller supports 64-bit addressing for BDL addresses, data buffer

addressees, and command buffer addresses.

Bit Description

7:0 Minor Version — RO. Hardwired to 0 indicating that the Intel® ICH7 supports minor

revision number 00h of the Intel® High Definition Audio specification.

Bit Description

7:0 Major Version — RO. Hardwired to 01h indicat ing that the Intel® ICH7 supports major

revision number 1 of the Intel® High Definition Audio specification.

Intel ® ICH7 Family Datasheet 733

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 04h Attribute: RO

Default Value: 0 03Ch Size: 16 bits

19.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 06h Attribute: RO

Default Value: 0 01Dh Size: 16 bits

Bit Description

15:7 Reserved.

6:0

Output Payload Capability — RO. Hardwired to 3Ch indicating 60 word payload.

This field indicates the total output payload available on the link. This does not include

bandwidth used for command and control. This measurement is in 16-bit word

quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double

pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for

command and control, leaving 60 words available for data payload.

00h = 0 word

01h = 1 word payload.

.....

FFh = 256 word payload.

Bit Description

15:7 Reserved.

6:0

Input Payload Capability — RO. Hardwired to 1Dh indicating 29 word payload.

This field indicates the total output payload available on the link. This does not include

bandwidth used for response. This measurement is in 16-bit word quantities per 48

MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or 31.25

words in total. 36 bits are used for response, leaving 29 words available for data

payload.

00h = 0 word

01h = 1 word payload.

.....

FFh = 256 word payload.

Intel® High Definition Audio Controller Registers (D27:F0)

734 Intel ® ICH7 Family Datasheet

19.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 08h Attribute: R/W

Default Value: 00000000h Size: 32 bits

Bit Description

31:9 Reserved.

Accept Unsolicited Respon se Enable — R/W.

0 = Unsolicited responses from the codecs are not accepted.

1 = Unsolicited response from the codecs are accepted by the controller and placed

into the Response Input Ring Buffer.

7:2 Reserved.

Flush Control — R/W.

0 = Flush Not in progress.

1 = Writing a 1 to this bit initiates a flush. When the flush completion is received by

the controller, hardware sets the Flush Stat us bit and clea rs this Flush Con trol bit.

Before a flush cycle is initiated, the DMA Position Buffer must be programmed

with a valid memory address by softw are, but the DMA P osition Buffer bit 0 needs

not be set to enable the position reporting mechanism. Also, all streams must be

stopped (the associated RUN bit must be 0).

When the flush is initiated, th e cont roller will flush the pipelines to memory to ensure

that the hardware is ready to transition to a D3 state. Settin g this bit is not a critical

step in the power state transition if the content of the FIFIO s is not critic al.

Controller Reset # — R/W.

0 = W riting a 0 to this bit causes t he Intel High Definition Audio controller to be reset.

All state machines, FIFOs, and non-resume well memory mapped configuration

registers (not PCI configuration registers) in the controller will be reset. The Intel

High Definition Audio link RESET# signal will be asserted, and all other link

signals will be driven to their default values. After the hardware has completed

sequencing into the reset state, it will report a 0 in this bit. Software must read a

0 from this bit to verify the controller is in reset.

1 = Writing a 1 to this bit causes the controller to exit its reset state and deassert the

Intel High Definition Audio link RESET# signal. Softw are is responsible for setting/

clearing this bit such that the minimum Intel High Definition Audio link RESET#

signal assertion pulse width specification is met. When the controller hardware is

ready to begin operation, it will report a 1 in thi s bit. Software must read a 1 from

this bit before accessing any controller registers. This bit defaults to a 0 after

Hardware reset, therefore, software needs to write a 1 to this bit to begin

operation.

NOTES:

1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0

before writing a 0 to this bit in order to assure a clean re-start.

2. When setting or clearing this bit, software must ensure that minimum link

timing requirements (minimum RESET# assert ion time, etc.) are met.

3. When this bit is 0 indicating that the controller is in reset, writes to all Intel

High Definition Audio memory mapped registers are ignored as if the device is

not present. T he only exception is th is register itself. The Global Control

0 if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is

active. If Byte Enable 0 is not active, writes to the Global Control register will

be ignored when CRST# is 0. When CRST# is 0, reads to Intel High Definition

Intel ® ICH7 Family Datasheet 735

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 0Ch A ttribute: R/W

Default Value: 0 000h Size: 16 bits

19.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 0Eh Attribute: R/WC

Default Value: 0 000h Size: 16 bits

Bit Description

15:3 Reserved.

2:0

SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may

generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is

enabled to generate a wake.

Bit 0 is used for SDI0

Bit 1 is used for SDI1

Bit 2 is used for SDI2

NOTE: These bits are in the resume well and only cleared on a power on reset.

Software must not make assumptions abou t the reset state of th ese bits and

must set them appropriately.

Bit Description

15:3 Reserved.

2:0

SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s )

received a state change event. The bits are cleared by writing 1’s to them.

Bit 0 = SDI0

Bit 1 = SDI1

Bit 2 = SDI2

NOTE: These bits are in the resume well and only cleared on a power on reset.

Software must not make assumptions abou t the reset state of th ese bits and

must set them appropriately.

Intel® High Definition Audio Controller Registers (D27:F0)

736 Intel ® ICH7 Family Datasheet

19.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 10h Attribute: R/WC

Default Value: 0000h Size: 16 bits

Bit Description

15:4 Reserved.

(Desktop

/Ultra

Mobile

Only)

Reserved

(Mobile

Only)

Dock Mated Interrupt Status (DMIS) — RW/C.

0 = Software clears this bit by writing a 1 to it.

1 = Dock mating or unmating process has completed. For the docking process, it

indicates that dock is electrically connected and that software may detect and

enumerate the docked codecs. For the undocking process, it indicates that the

dock is electrical ly isolated and that softw are may report to the user that physical

undocking may commence. This bit gets se t to a 1 by hardware when the DM bit

transit ions from 0-to-1 (docking) or from 1-t o-0 (undocking). Note that this bit is

set regardless of the state of the DMIE bit.

(Desktop

/Ultra

Mobile

Only)

Reserved

(Mobile

Only)

Dock Mated (DM) — RO. This bit effectively communicates to software that an

Intel® HD Audio docked codec is physically and electrically attached.

0 = Controller hardware sets this bit to 0 after the undocking sequence triggered by

writing a 0 to the Dock Attach (GCTL.DA) bit is completed (DOCK_EN#

deasserted). This bit indicates to software that the docked codec(s) may be

physically undocked.

1 = Controller hardware sets this bit to 1 after the docking sequence triggered by

writing a 1 to the Dock Attach (GCTL.DA) bit is completed (AZ_DOCK_RST#

deassertion). This bit indicates to software that the docked codec(s) may be

discovered via the STATES TS register and then enumerated.

Flush Status — R/WC.

0 = Flush not completed

1 = This bit is set t o 1 by hardware to indicate that t he flush cycle initiated when th e

Flush Control bit (HDBAR + 08h, bit 1) was set has completed.

NOTE: Software must write a 1 to clear this bit before the next time the Flush Control

bit is set to clear the bit.

0 Reserved.

Intel ® ICH7 Family Datasheet 737

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.10 ECAP—Extended Capabilities

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 14h Attribute: R/WO

Default Value: 0 0000001h Size: 32 bits

19.2.11 OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 18h Attribute: RO

Default Value: 0 030h Size: 16 bits

Bit Description

31:1 Reserved

(Mobile

Only)

Docking Supported (DS)— R/WO. A 1 in dicates that Intel® ICH7 supports Intel® HD

Audio Dockin g. The GCTL.DA bit is on ly writable when this DS bit is 1. Intel HD Audi o

driver software should only branch to its docking routine when this DS bit is 1. BIOS

may clear this bit to 0 to prohibit the Intel HD Audio driver software from attempting

to run the docking routines.

NOTE: This bit is reset to its default value only on a PLTRST#, but not on a CRST# or

D3hot-to-D0 transition.

Bit Description

15:14

Output FIFO Padding Type (OPADTYPE) — RO. This field in dicates how the

controller pads the samples in the controller's buffer (FIFO). Controllers may not pad at

all or may pad to byte or memory container sizes.

0h = Controller pads all samples to bytes

1h = Reserved

2h = Controller pads to memory container size

3h = Controller does not pad and uses samples directly

13:0

Output Stream Payload Capability (O UTSTRM PAY) — RO. This field indicates

maximum number of words per frame for any single outpu t stream. Th is measu rem ent

is in 16 bit word quantities per 48 kHz frame. The maximum supported is 48 Words

(96B); therefore, a value of 30h is reported in this register. The value does not specify

the number of words actually tr ansmitted in the fr ame, but is the siz e of the data in the

controller buffer (FIFO) after the samples are padded as specified by OPADTYPE. Thus,

to compute the support ed streams, eac h sample is padded according to OPAD TYPE and

then multiplied by the number of channels and samples per frame. If this computed

value is larger than OUTSTRMPAY, then that stream is not supported. The value

specified is not affected by striping.

Software must ensure that a format that would cause more Words per frame than

indicated is not programmed into the Output Stream Descriptor Register.

The value may be larger than the OUTPAY register value in some cases.

Intel® High Definition Audio Controller Registers (D27:F0)

738 Intel ® ICH7 Family Datasheet

19.2.12 INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 1Ah Attribute: RO

Default Value: 0018h Size: 16 bits

Bit Description

15:14

Input FIFO Padding Type (IPADTYPE) — RO. This field indicates how the controller

pads the samples in the controller's buffer (FIFO). Controllers may not pad at all or may

pad to byte or memory container sizes.

0h = Controller pads all samples to bytes

1h = Reserved

2h = Controller pads to memory container size

3h = Controller does not pad and uses samples directly

13:0

Input Stream Payload Capability (INSTRMPAY) — RO. This field indicates the

maximum number of W ords per frame for any single input stre am. This measurement is

in 16-bit Word quantities per

48-kHz fr ame. The maxi mum supported is 24 W or ds (48B); therefore, a v alue of 18h is

reported in this register.

The value does not specify the number of words actually transmitted in t he frame, but

is the size of the data as it will be placed into the controller's buffer (FIFO). Thus,

samples will be padded according to IPADTYPE before being stored into controller

buffer. To compute the supported streams, each sample is padded according to

IPADTYPE and then multiplied by the number of channels and samples per frame. If this

computed value is larger than INSTRMPAY, then that stream is not supported. As the

inbound stream tag is not stored with the samples it is not included in the word count.

The value may be larger than INPA Y register value in some cases, although values less

than INPAY may also be invalid due to overhead. Software must ensure that a format

that would cause more Words per frame than indicated is not programmed into the

Input Stream Descriptor Register.

Intel ® ICH7 Family Datasheet 739

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.13 INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 20h Attribute: R/W

Default Value: 0 0000000h Size: 32 bits

Bit Description

Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt

generation.

0 = Disable.

1 = Enable. The Intel® High Definition Audio function is enabled to generate an

interrupt. This control is in addition to any bits in the bus specific address space,

such as the Interrupt Enable bit in the PCI configuration space.

NOTE: This bit is not affected by the D3HOT to D0 transition.

Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for

controller functions.

0 = Disable.

1 = Enable. The controller generates an interrupt when the corresponding status bit

gets set due to a Response Inte rrupt, a Response Buffer Overrun, and State

Change events.

NOTE: This bit is not affected by the D3HOT to D0 transition.

29:8 Reserved

7:0

Stream Interrupt Enable (SIE) — R/W.

0 = Disable.

1 = Enable. When set to 1, th e individual streams are enabled to generate an interrupt

when the corresponding status bits get set.

A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry

being completed, or as a result of a FIFO error (underrun or ove rrun) occurring. Control

over the generation of each of these sources is in the associated Stream Descriptor.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0 = input stream 1

Bit 1 = input stream 2

Bit 2 = input stream 3

Bit 3 = input stream 4

Bit 4 = output stream 1

Bit 5 = output stream 2

Bit 6 = output stream 3

Bit 7 = output stream 4

Intel® High Definition Audio Controller Registers (D27:F0)

740 Intel ® ICH7 Family Datasheet

19.2.14 INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 24h Attribute: RO

Default Value: 00000000h Size: 32 bits

Bit Description

Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in

this register.

NOTE: This bit is not affected by the D3HOT to D0 transition.

Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.

0 = An interrupt condition did Not occur as described be low.

1 = An interrupt condition occurred due to a Response Interrupt, a Response Buffer

Overrun Interrupt, or a SDIN State Change event. The exact cause can be

determined by interrogating other registers. This bit is an OR of all of the stated

interrupt status bits for this register.

NOTES:

1. This bit is set regardless of the state of the corresponding interrupt enable bit,

but a hardware interrupt will not be gener at ed unless the corr es pondin g enable

bit is set.

2. This bit is not affected by the D3HOT to D0 transition.

29:8 Reserved

7:0

Stream Interrupt S tat us (S IS) — RO.

0 = An interrupt condition did Not occur on the corresponding stream.

1 = An interrupt condition occurred on the corresponding stream. This bit is an OR of all

of the stream’s interrupt status bits.

NOTE: These bits are set regardless of the state of the corresponding interrupt enable

bits.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0 = input stream 1

Bit 1 = input stream 2

Bit 2 = input stream 3

Bit 3 = input stream 4

Bit 4 = output stream 1

Bit 5 = output stream 2

Bit 6 = output stream 3

Bit 7 = output stream 4

Intel ® ICH7 Family Datasheet 741

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.15 WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 30h Attribute: RO

Default Value: 0 0000000h Size: 32 bits

19.2.16 SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 34h Attribute: R/W

Default Value: 0 0000000h Size: 32 bits

Bit Description

31:0

Wall Clock Counter — RO. This 32-bit counter field is incremented on each link BCLK

period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0

with a period of approximately 179 seconds.

This counter is enabled while the BCLK bit is set to 1. Software uses this counter to

synchronize between multiple controllers. Will be reset on controller reset.

Bit Description

31:8 Reserved

7:0

Stream Synchronization (SSYNC) — R/W.

0 = Data is Not blocked from being sent on or received from the link

1 = The set bits block data from being sent on or received from the link. Each bit

controls the associat ed stream descriptor (i.e., bit 0 corresponds to the first str eam

descriptor, etc.)

To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits

for the associated stream descriptors are then set to 1 to start the DMA engines. When

all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at

the same time, and transmission or reception of bits to or from the link will begin

together at the start of the next full link frame.

To synchronously stop the streams, first these bits are set, and then the individual RUN

bits in the stream descriptor are cleared by software.

If synchronization is not desired, these bits may be left as 0, and the stream will simply

begin running normally when the stream’s RUN bit is set.

The streams are numbered and the SIE bits assigned sequentially, based on their order

in the register set.

Bit 0 = input stream 1

Bit 1 = input stream 2

Bit 2 = input stream 3

Bit 3 = input stream 4

Bit 4 = output stream 1

Bit 5 = output stream 2

Bit 6 = output stream 3

Bit 7 = output stream 4

Intel® High Definition Audio Controller Registers (D27:F0)

742 Intel ® ICH7 Family Datasheet

19.2.17 CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 40h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

19.2.18 CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 44h Attribute: R/W

Default Value: 00000000h Size: 32 bits

19.2.19 CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 48h Attribute: R/W

Default Value: 0000h Size: 16 bits

Bit Description

31:7

CORB Lower Base Address — R/W. This field is the lower address of the Command

Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B

boundary. This register field must not be written when the DMA engine is running or the

DMA transfer may be corrupted.

6:0 CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This requires the CORB

to be allocated with 128B granularity to allow for cache line fetch optimizations.

Bit Description

31:0 CORB Upper Base Address — R/W. This field is the upper 32 bits of the address of

the Command Output Ring buffer. This regist er field must not be written when th e DMA

engine is running or the DMA transfer may be corrupted.

Bit Description

15:8 Reserved.

7:0

CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this

field in DWord granularity. The DMA engine fetches commands from the CORB until the

Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB).

This register field may be written when the DMA engine is running.

Intel ® ICH7 Family Datasheet 743

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.20 CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4A h Attribute: R/W

Default Value: 0 000h Size: 16 bits

19.2.21 CORBCTL—CORB Co ntr ol Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4Ch A ttribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB

Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware

buffer within the Intel® High Definition Audio controller. The hardware will physically

update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1

to verify that the reset completed correctly. Software must clear this bit back to 0 and

read back the 0 to verify that the clear completed correctly. The CORB DMA engine

must be stopped prior to resetting the Read Pointer or else DMA transfer may be

corrupted.

14:8 Reserved.

7:0

CORB Read Pointer (CORBRP) — RO. Software reads this field to determine how many

commands it can write to the CORB without over-running. The value read indicates the

CORB Read P ointer offset in DW ord gr anularity. The offset entry read from this field has

been successfully fetched by the DMA controller and may be over-written by software.

Supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA

engine is running.

Bit Description

7:2 Reserved.

Enable CORB DMA Engine — R/W. After software writes a 0 to this bit, the hardware

may not stop immediately. The hardware will physically update the bit to 0 when the

DMA engine is truly stopped. Software must read a 0 from this bit to verify that the

DMA engine is truly stopped.

0 = DMA stop

1 = DMA run

CORB Memory Error Interrupt Enab le — R/W.

0 = Disable.

1 = Enable. The controller will generate an interrupt if the CMEI status bit (HDBAR +

4Dh: bit 0) is set.

Intel® High Definition Audio Controller Registers (D27:F0)

744 Intel ® ICH7 Family Datasheet

19.2.22 CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 4Dh Attribute: R/WC

Default Value: 00h Size: 8 bits

19.2.23 CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller —D27:F0)

Memory Address:HDBAR + 4Eh Attribute: RO

Default Value: 42h Size: 8 bits

19.2.24 RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 50h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

Bit Description

7:1 Reserved.

CORB Memory Error Indication (CMEI) — R/WC.

0 = Error Not detected.

1 = The controller has detected an error in the path way between the controller and

memory. This may be an ECC bit error or any other type of detectable data error

which renders the command data fetched invalid.

NOTE: Software can clear this bit by writing a 1 to it. However, this type of error leaves

the audio subsystem in an un-viable state and typically requires a controller

reset by writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0).

Bit Description

7:4 CORB Size Capability — RO. Hardwired to 0100b i ndicating that the ICH7 only supports

a CORB size of 256 CORB entries (1024B).

3:2 Reserved.

1:0 CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B).

Bit Description

31:7

RIRB Lower Base Address — R/W. This field is the lower address of the Response

Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B

boundary. This register field must not be written when the DMA engine is running or the

DMA transfer may be corrupted.

6:0 RIRB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the RIRB to

be allocated with 128-B granularity to allow for cache line fe tc h opti mizat ion s .

Intel ® ICH7 Family Datasheet 745

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.25 RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 54h Attribute: R/W

Default Value: 0 0000000h Size: 32 bits

19.2.26 RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 58h Attribute: R/W, RO

Default Value: 0 000h Size: 16 bits

Bit Description

31:0 RIRB Upper Base Address — R/W. This field is the upper 32 bits of the address of the

Response Input Ring Buffer. This register field must not be written when the DMA

engine is running or the DMA transfer may be corrupted.

Bit Description

RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB

Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write

Pointer or else DMA transfer may be corrupted.

This bit is always read as 0.

14:8 Reserved.

7:0

RIRB Write Pointer (RIRBWP) — RO. This field is the indicates the last valid RIRB entry

written by the DMA controller. Software reads this field to determine how many

responses it can read from the RIRB. The value read indicates the RIRB Write Pointer

offset in 2 DWord RIRB entry units (since ea ch RIRB entry is 2 DWords long). Supports

up to 256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the

DMA engine is running.

Intel® High Definition Audio Controller Registers (D27:F0)

746 Intel ® ICH7 Family Datasheet

19.2.27 RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Ah Attribute: R/W

Default Value: 0000h Size: 16 bits

19.2.28 RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Ch Attribute: R/W

Default Value: 00h Size: 8 bits

Bit Description

15:8 Reserved.

7:0

N Response Interrupt Count — R/W.

0000 0001b = 1 response sent to RIRB

...........

1111 1111b = 255 responses sent to RIRB

0000 0000b = 256 responses sent to RIRB

The DMA engine should be stopped when changing this field or else an interrupt may be

lost.

Note that each re sponse occupies 2 DWords in the RIRB.

This is compared to the total numbe r of responses that hav e been returned, as opposed

to the number of frames in which there were responses. If more than one codec

responds in one frame, then the count is increased by the number of responses

received in the frame.

Bit Description

7:3 Reserved.

Response Overrun Interrupt Control — R/W.

0 = Hardware will Not generated an interrupt as described below.

1 = The hardware will generate an interrupt when the Response Overrun Interrupt

Status bit (HDBAR + 5Dh: bit 2) is set.

Enable RIRB DMA Engine — R/W. After software writes a 0 to this bit, the hardware

may not stop immediately. The hardware will physically update the bit to 0 when the

DMA engine is truly stopped. Software must read a 0 from this bit to verify that the

DMA engine is truly stopp ed.

0 = DMA sto p

1 = DMA run

Response Interrupt Control — R/W.

0 = Disable Interrupt

1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR

when an empty Response slot is encountered on all SDI[x] inputs (whichever

occurs first). The N counter is reset when the interrupt is generated.

Intel ® ICH7 Family Datasheet 747

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.29 RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5D h Attribute: R/WC

Default Value: 00h Size: 8 bits

19.2.30 RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 5Eh Attribute: RO

Default Value: 42h Size: 8 bits

19.2.31 IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 60h Attribute: R/W

Default Value: 0 0000000h Size: 32 bits

Bit Description

7:3 Reserved.

Response Overrun Interrupt Status — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the

incoming responses to memory before additional incoming responses overrun the

internal FIFO . When the o v e rrun occurs, the hardware will drop the responses that

overrun the buffer. An interrupt may be generated if the Response Overrun

Interrupt Control bit is set. Note that this status bit is set even if an interrupt is not

enabled for this event.

1 Reserved.

Response Interrupt — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = Hardware sets this bit to 1 when an interrupt has been generated after N number

of Responses are sent to the RIRB buffer OR when an empty Response slot is

encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit

is set even if an interrupt is not enabled for this event.

Bit Description

7:4 RIRB Size Capabili t y — RO . Hardwired to 0100b indicating that the ICH7 only supports

a RIRB size of 256 RIRB entries (2048B)

3:2 Reserved.

1:0 RIRB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B)

Bit Description

31:0

Immediate Command Write — R/W. The command to be sent to the codec via the

Immediate Command mechanism is written to this register. The command stored in this

the ICB bit (HDBAR + 68h: bit 0)

Intel® High Definition Audio Controller Registers (D27:F0)

748 Intel ® ICH7 Family Datasheet

19.2.32 IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 64h Attribute: RO

Default Value: 00000000h Size: 32 bits

19.2.33 IRS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 68h Attribute: R/W, R/WC

Default Value: 0000h Size: 16 bits

Bit Description

31:0

Immediate Response Read (IRR) — RO. This register contains the response received

from a codec resulting from a command sent via the Immediate Command mech anis m.

If multiple codecs responded in the same time, there is no assurance as to which

response will be latched. Therefore, broadcast-type commands must not be issued via

the Immediate Command mechanism.

Bit Description

15:2 Reserved.

Immediate Result Valid (IRV) — R/WC.

0 = Software must clear this bit by writing a 1 to it before issuing a new command so

that the software may determine when a new response has arrived.

1 = Set to 1 by hardware when a new response is latched into the Immediate Response

response from the Immediate Response register.

Immediate Command Busy (ICB) — R/W. When this bit is read as 0, it indicates that

a new command ma y be iss ued usin g the Immediat e Command me chanism. Wh en this

bit tran sitions from 0-to-1 (via so ftware writing a 1), the c ontroller issues the com mand

currently stored in the Immediate Command register to the codec over the link. When

the corresponding response is latched into the Immediate Response register, the

controller hardware sets the IRV flag and clears the ICB bit back to 0.

NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism

is operating, otherwise the responses conflict. This must be enforced by

software.

Intel ® ICH7 Family Datasheet 749

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.34 DPLBASE—DMA Position Lower Base Address Regi ster

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 70h Attribute: R/W, RO

Default Value: 0 0000000h Size: 32 bits

19.2.35 DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:HDBAR + 74h Attribute: R/W

Default Value: 0 0000000h Size: 32 bits

Bit Description

31:7

DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA P osition Buffer

Base Address. This register field must not be written when any DMA engine is running

or the DMA transfer may be corrupted. This same addres s is us ed by the Flush Control

and must be programmed with a valid value before the Flush Control bit

(HDBAR+08h:bit 1) is se t.

6:1 DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128-

byte buffer alignment for cache line write opti mizat ions .

DMA Position Buffer Enable — R/W.

0 = Disable.

1 = Enable. The controller will write the DMA positions of eac h of the DMA engines to

the buffer in the main memory periodically (typic ally once per frame). Software can

use this value to dtermine what data in memory is valid data.

Bit Description

31:0 DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Posi tion Buffer

Base Address. This register field must not be written when any DMA engine is running

or the DMA transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

750 Intel ® ICH7 Family Datasheet

19.2.36 SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 80h Attribute: R/W, RO

Input Stream[1]: HDBAR + A0h

Input Stream[2]: HDBAR + C0h

Input Stream[3]: HDBAR + E0h

Output Stream[0]: HDBAR + 100h

Output Stream[1]: HDBAR + 120h

Output Stream[2]: HDBAR + 140h

Output Stream[3]: HDBAR + 160h

Default Value: 040000h Size:24 bits

Bit Description

23:20

Stream Number — R/W. This value reflects the Tag associated with the data

being transferred on the link.

When data controlled by this descriptor is sent out over the link, it will have its

stream number encoded on the SYNC signal.

When an input stream is detected on any of the SDI signals that match this value,

the data samples are loaded into FIFO associated with this descriptor.

Note that while a single SDI input may contain data from more than one stream

number, two different SDI inputs may not be configured with the same stream

number.

0000 = Reserved

0001 = Stream 1

........

1110 = Stream 14

1111 = Stream 15

19 Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional

streams; therefore, this bit is hardwired to 0.

(Desktop

and Mobile

Only)

Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is

enabled throug h the PCI Express* registers.

(Ultra

Mobile

Only)

Reserved

17:16 Stripe Control — RO. This bit is only meaningful for input streams; therefore, this

bit is hardwired to 0.

15:5 Reserved

4Descriptor Error Interrupt Enable — R/W.

0 = Disable

1 = An interrupt is generated when the Descriptor Error Status bit is set.

FIFO Error Interrupt Enable — R/W.

0 = Disable.

1 = Enable. This bit controls whether the occurrence of a FIFO error (overrun for

input or underrun for output) will cause an interrupt or not. If this bit is not

set, bit 3 in the Status register will be set, but the interrupt will not occur.

Either way, the samples will be dropped.

Intel ® ICH7 Family Datasheet 751

Intel® High Definition Audio Controller Registers (D27:F0)

Interrupt on Completion Enable — R/W.

0 = Disable.

1 = Enable. This bit controls whether or not an interrupt occurs when a buffer

completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the

Status register will be set, but the interrupt will not occur.

Stream Run (RUN) — R/W.

0 = Disable. The DMA engine associated with this input stream will be disabled.

The hardware will report a 0 in this bit when the DMA engine is actually

stopped. Software must read a 0 from this bit before modifying related control

registers or restarting the DMA engine.

1 = Enable. The DMA engine associated with this input stream will be enabled to

transfer data from the FIFO to the main memory. The SSYNC bit must also be

cleared in order for the DMA engine to run. For output streams, the cadence

generator is reset whenever the RUN bit is set.

Stream Reset (SRST) — R/W.

0 = Writing a 0 causes the corresponding stream to exit reset. When the stream

hardware is ready to begin operation, it will report a 0 in this bit. Software

must read a 0 from this bit before accessing any of the stream registers.

1 = Writing a 1 causes the corresponding stream to be reset. The Stream

Descriptor registers (except the SRST bit itself) and FIFO’s for the

corresponding stream are reset. After the stream hardware has completed

sequencing into the reset state, it will report a 1 in this bit. Software must

read a 1 from this bit to ve rify that the str eam is in reset. The RUN bit must be

cleared before SRST is asserted.

Bit Description

Intel® High Definition Audio Controller Registers (D27:F0)

752 Intel ® ICH7 Family Datasheet

19.2.37 SDSTS—Stream Descriptor Status Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 83h Attribute: R/WC, RO

Input Stream[1]: HDBAR + A3h

Input Stream[2]: HDBAR + C3h

Input Stream[3]: HDBAR + E3h

Output Stream[0]: HDBAR + 103h

Output Stream[1]: HDBAR + 123h

Output Stream[2]: HDBAR + 143h

Output Stream[3]: HDBAR + 163h

Default Value: 00h Size: 8 bits

Bit Description

7:6 Reserved.

FIFO Ready (FIFORDY) — RO.

For output streams, the controller hardware will set this bit to 1 while the output DMA

FIFO contains enough data to maintain the stream on the link. This bit defaults to 0 on

reset because the FIFO is cleared on a reset.

For input streams, the controller hardware will set this bit to 1 when a valid descriptor

is loaded and the engine is ready for the RUN bit to be set.

Descriptor Error — R/WC.

0 = No error detected.

1 = A serious error occurred during the fetch o f a de scri ptor. This could be a result of a

Master Abort, a parity or ECC error on the bus, or any other error which renders

the current Buffer Descriptor or Buffer Descriptor list useless. This error is treated

as a fatal stream error, as the stream cannot cont inue runn ing . Th e RUN bit wil l be

cleared and the stream will stop.

NOTE: Software may attempt to restart the stream engine after addressing the cause

of the error and writing a 1 to this bit to clear it.

FIFO Error — R/WC. The bit is cleared by writing a 1 to it.

0 = No error detected.

1 = FIFO error occurred. This bit is set even if an interrupt is not enabled.

For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set.

When this happens, the FIFO pointers do not increment and the incoming data is no t

written into the FIFO, thereby being lo st.

For an output stream, this indicates a FIFO underrun when there are still buffers to

send. The hardware should not tr ansmi t any thing on the link for the associated stream

if there is not valid data to send.

Buffer Completion Interrupt Status — R/WC.

0 = Last sample of a buffer has Not been processed as described below.

1 = Set to 1 by the hardware after the last sample of a buffer has been processed, AND

if the Interrupt on Completion bit is set in the command byte of the buffer

descriptor. It remains active until software clears it by writing a 1 to it.

1:0 Reserved.

Intel ® ICH7 Family Datasheet 753

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.38 SDLPIB—Stream Descriptor Link Position in Bu ffer

Memory Address:Input Stream[0]: HDBAR + 84 h Attribute:RO

Input Stream[1]: HDBAR + A4h

Input Stream[2]: HDBAR + C4h

Input Stream[3]: HDBAR + E4h

Output Stream[0]: HDBAR + 104h

Output Stream[1]: HDBAR + 124h

Output Stream[2]: HDBAR + 144h

Output Stream[3]: HDBAR + 164h

Default Value: 00000000h Size: 32 bits

19.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 88 h Attribute: R/W

Input Stream[1]: HDBAR + A8h

Input Stream[2]: HDBAR + C8h

Input Stream[3]: HDBAR + E8h

Output Stream[0]: HDBAR + 108h

Output Stream[1]: HDBAR + 128h

Output Stream[2]: HDBAR + 148h

Output Stream[3]: HDBAR + 168h

Default Value: 00000000h Size: 32 bits

Bit Description

31:0 Link Position in Buffer — RO. Indicates the number of bytes that have been received off

the link. This register will count from 0 to the value in the Cyclic Buffer Length regi ster

and then wrap to 0.

Bit Description

31:0

Cyclic Buffer Length — R/W. Indicates the number of bytes in the com plete cyclic

buffer. This register represents an integer number of samples. Link Position in Buffer

will be reset when it reaches this value.

Software may only write to this register after Global R eset, Controller R eset, or Stream

Res et has occurred. This value sh ould be only modified when th e RUN bit is 0. Once the

RUN bit has be en set to enable the engine, s oftware must not write to this register u ntil

after the next reset is asserted, or transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

754 Intel ® ICH7 Family Datasheet

19.2.40 SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 8Ch Attribute: R/W

Input Stream[1]: HDBAR + ACh

Input Stream[2]: HDBAR + CCh

Input Stream[3]: HDBAR + ECh

Output Stream[0]: HDBAR + 10Ch

Output Stream[1]: HDBAR + 12Ch

Output Stream[2]: HDBAR + 14Ch

Output Stream[3]: HDBAR + 16Ch

Default Value: 0000h Size: 16 bits

19.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 8Eh Attribute: R/W

Input Stream[1]: HDBAR + AEh

Input Stream[2]: HDBAR + CEh

Input Stream[3]: HDBAR + EEh

Output Stream[0]: HDBAR + 10Eh

Output Stream[1]: HDBAR + 12Eh

Output Stream[2]: HDBAR + 14Eh

Output Stream[3]: HDBAR + 16Eh

Default Value: 0004h Size: 16 bits

Bit Description

15:8 Reserved.

7:0

Last Valid Index — R/W. The value written to this register indicates the index for the

last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it

will wrap back to the first descriptor in the list and co ntinue proces sing.

This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer

descriptor list before DMA operations can begin).

This value should only be modified when the RUN bit is 0.

Bit Description

15:3 Reserved.

2:0

FIFO Watermark (FIFOW) — R/W. This field indicates the minimum num ber of bytes

accumulated/free in the FIFO before the controller will start a fetch/eviction of data.

010 = 8B

011 = 16B

100 = 32B (Default)

Others = Unsupported

NOTES:

1. When the bit field is programmed to an unsupported size, the hardware sets

itself to the default value.

2. Software mu st read the bit field to test if the v alue is suppo rted after setting the

bit field.

Intel ® ICH7 Family Datasheet 755

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.42 SDFIFOS—Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 90h Attribute: Input: RO

Input Stream[1]: HDBAR + B0h Output: R/W

Input Stream[2]: HDBAR + D0h

Input Stream[3]: HDBAR + F0h

Output Stream[0]: HDBAR + 110h

Output Stream[1]: HDBAR + 130h

Output Stream[2]: HDBAR + 150h

Output Stream[3]: HDBAR + 170h

Default Value: Input Stream: 0077h Size: 16 bits

Output Stream: 00BFh

Bit Description

15:8 Reserved.

7:0

FIFO Size — RO (Input stream), R/W (Output stream). This field indicates the

maximum number of bytes that could be fetched by the controller at one time. This is

the maximum number of bytes that may have been DMA’d into memory but not yet

transmitted on the link, and is also the maximum possible value that the PICB count

will increase by at one time.

The value in this field is different for input and output streams. It is also dependent on

the Bits per Samples setting for the corresponding stream. Following are the values

read/written from/to this register for input and output streams, and for non-padded

and padded bit formats:

Output Stream R/W value:

NOTES:

1. All other values not listed are not supported.

2. When the output stream is programmed to an unsupported size, the hardware

sets itself to the default value (BFh).

3. Software must read the bit field to test if the value is supported after setti ng the

bit field.

Input Stream RO value:

NOTE: The default value is different for input and output streams, and reflects the

default state of the BITS fields (in Stream Descriptor Format registers) for the

corresponding stream.

Value Output Streams

0Fh = 16B 8, 16, 20, 24, or 32 bit Output Streams

1Fh = 32B 8, 16, 20, 24, or 32 bit Output Streams

3Fh = 64B 8, 16, 20, 24, or 32 bit Output Streams

7Fh = 128B 8, 16, 20, 24, or 32 bit Output Streams

BFh = 192B 8, 16, or 32 bit Output Streams

FFh = 256B 20, 24 bit Output Streams

Value Input Streams

77h = 120B 8, 16, 32 bit Input Streams

9Fh = 160B 20, 24 bit Input Streams

Intel® High Definition Audio Controller Registers (D27:F0)

756 Intel ® ICH7 Family Datasheet

19.2.43 SDFMT—Stream Descriptor Format Re gister

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 92h Attribute: R/W

Input Stream[1]: HDBAR + B2h

Input Stream[2]: HDBAR + D2h

Input Stream[3]: HDBAR + F2h

Output Stream[0]: HDBAR + 112h

Output Stream[1]: HDBAR + 132h

Output Stream[2]: HDBAR + 152h

Output Stream[3]: HDBAR + 172h

Default Value: 0000h Size: 16 bits

Bit Description

15 Reserved.

14 Sample Base Rate — R/W

0 = 48 kHz

1 = 44.1 kHz

13:11

Sample Base Rate Multiple — R/W

000 = 48 kHz, 44.1 kHz or less

001 = x2 (96 kHz, 88.2 kHz, 32 kHz)

010 = x3 (144 kHz)

011 = x4 (192 kHz, 176.4 kHz)

Others = Reserved.

10:8

Sample Base Rate Divisor — R/W.

000 = Divide by 1(48 kHz, 44.1 kHz)

001 = Divide by 2 (24 kHz, 22.05 kHz)

010 = Divide by 3 (16 kHz, 32 kHz)

011 = Divide by 4 (11.025 kHz)

100 = Divide by 5 (9.6 kHz)

101 = Divide by 6 (8 kHz)

110 = Divide by 7

111 = Divide by 8 (6 kHz)

7 Reserved.

6:4

Bits per Sample (BITS) — R/W.

000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit

boundaries

001 = 16 bits. The data will be packed in memory in 16-bit quantities on 16-bit

boundaries

010 = 20 bits. The data will be packed in memory in 32-bit quantities on 32-bit

boundaries

011 = 24 bits. The data will be packed in memory in 32-bit quantities on 32-bit

boundaries

100 = 32 bits. The data will be packed in memory in 32-bit quantities on 32-bit

boundaries

Others = Reserved.

3:0

Number of Channels (CHAN) — R/W. Indicates number of channels in each frame of the

stream.

0000 =1

0001 =2

........

1111 =16

Intel ® ICH7 Family Datasheet 757

Intel® High Definition Audio Controller Registers (D27:F0)

19.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer

Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 98h Attribute: R /W,RO

Input Stream[1]: HDBAR + B8h

Input Stream[2]: HDBAR + D8h

Input Stream[3]: HDBAR + F8h

Output Stream[0]: HDBAR + 118h

Output Stream[1]: HDBAR + 138h

Output Stream[2]: HDBAR + 158h

Output Stream[3]: HDBAR + 178h

Default Value: 00000000h Size: 32 bits

19.2.45 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer

Upper Base Address Register (Intel® High Definition Audio

Controller—D27:F0)

Memory Address:Input Stream[0]: HDBAR + 9Ch Attribute: R/W

Input Stream[1]: HDBAR + BCh

Input Stream[2]: HDBAR + DCh

Input Stream[3]: HDBAR + FCh

Output Stream[0]: HDBAR + 11Ch

Output Stream[1]: HDBAR + 13Ch

Output Stream[2]: HDBAR + 15Ch

Output Stream[3]: HDBAR + 17Ch

Default Value: 00000000h Size: 32 bits

Bit Description

31:7 Buffer Descriptor List Pointer Lower Base Address — R/W. This field is the lower

address of the Buffer Descriptor List. This va lue should only be modified when the RUN

bit is 0, or DMA transfer may be corrupted.

6:0 Hardwired to 0 forcing alignment on 128-B boundaries.

Bit Description

31:0 Buffer Descriptor List Pointer Upper Base Address — R/W. This field is the upper

32-bit address of the Buffer Descriptor List. This value should only be modified when

the RUN bit is 0, or DMA transfer may be corrupted.

Intel® High Definition Audio Controller Registers (D27:F0)

758 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 759

High Precision Event Timer Registers

20 High Precision Event Timer

Registers

The timer registers are memory-mapped in a non-indexed scheme. This allows the

processor to directly access each register without having to use an index register. The

timer register space is 1024 bytes. The registers are generally aligned on 64-bit

boundaries to simplify implementation with IA64 processors. There are four possible

memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3)

FED0_2000h., 4) FED0_4000h. The choice of address range will be selected by

configuration bits in the High Precision Timer Configuration Register (Chipset

Configuration Registers:Offset 3404h).

Behavioral Rules:

1. Software must not attempt to read or write across register boundaries. For

example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses

should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.

Any accesses to these offsets will result in an unexpected behavior, and may result

in a master abort. However, these accesses should not result in system hangs. 64-

bit accesses can only be to x0h and must not cross 64-bit boundaries.

2. Software should not write to read-only registers.

3. Software should not expect any particular or consistent value when reading

reserved registers or bits.

20.1 Memory Mapped Registers

Table 20-1. Memory-Mapped Registers (Sheet 1 of 2)

Offset Mnemonic Register Default Type

000–007h GCAP_ID General Capabilities and Identification 0429B17F8

086A201h RO

008–00Fh — Reserved — —

010–017h GEN_CONF General Configuration 0000h R/W

018–01Fh — Reserved — —

020–027h GINTR_STA General Interrupt Status 00000000

00000000h R/WC, R/

028–0EFh — Reserved — —

0F0–0F7h MAIN_CNT Main Counter Value N/A R/W

0F8–0FFh — Reserved — —

100–107h TIM0_CONF Timer 0 Configuration and Capabilities N/A R/W, RO

108–10Fh TIM0_COMP Timer 0 Comparator Value N/A R/W

110–11Fh — Reserved — —

120–127h TIM1_CONF Timer 1 Configuration and Capabilities N/A R/W, RO

128–12Fh TIM1_COMP Timer 1 Comparator Value N/A R/W

130–13Fh — Reserved — —

High Precision Event Timer Registers

760 Intel ® ICH7 Family Datasheet

NOTES:

1. Reads to reserved registers or bits will return a value of 0.

2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision

Event Timers. If attempted, the lock is not honored, which means potential deadlock

conditions may occur.

20.1.1 GCAP_ID—General Capabilities and Identification Register

Address Offset: 00h Attribute: RO

Default Value: 0429B17F8086A201h Size: 64 bits

140–147h TIM2_CONF Timer 2 Configuration and Capabilities N/A R/W, RO

148–14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W

150–15Fh — Reserved — —

160–3FFh — Reserved — —

Table 20-1. Memory-Mapped Registers (Sheet 2 of 2)

Offset Mnemonic Register Default Type

Bit Description

63:32

Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field in dicates the

period at which the counter increments in femptoseconds (10^-15 seconds). This will

return 0429B17Fh when read. This indicates a period of 69841279h fs (69.841279

ns).

31:16 Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to

Intel.

15 Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy

Replac em en t In t erru pt Rout opti on is supported.

14 Reserved. This bit returns 0 when read.

13 Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit

wide.

12:8 Number of Timer Capability (NUM_TIM_CAP) — RO. This field in dicates the number of

timers in this block.

02h = Three timers.

7:0 Re vision Identificat ion (REV_ID) — RO . This indicates which revision of the functi on is

implemented. D efault value will be 01h.

Intel ® ICH7 Family Datasheet 761

High Precision Event Timer Registers

20.1.2 GEN_CONF—General Configuration Register

Address Offset: 010h Attribute: R/W

Default Value: 00000000 00000000h Size: 64 bits

20.1.3 GINTR_STA—General Interrupt Status Register

Address Offset: 020h Attribute: R/W, R/WC

Default Value: 00000000 00000000h Size: 64 bits

Bit Description

63:2 Reserved. These bits return 0 when read.

Legacy Replacement Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the

LEG_RT_CNF bit are both set, then the interrupts will be routed as follows:

• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC

• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC

• Timer 2-n is routed as per the routing in the timer n config registers.

• If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)

will have no impact.

• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers

are used.

• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to

disable the legacy replacement routing.

Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the

timers to generate interrupts.

0 = Disable. The main counter will halt (will not increment) and no interrupts will be

caused by any of these timers. For level-triggered interrupts, if an interrupt is

pending when the ENABLE_CNF bit is changed from 1-to-0, the interrupt status

indications (in the various Txx_INT_STS bits) will not be cleared. Software must

write to the Txx_INT_STS bits to clear the interrupts.

1 = Enable.

NOTE: This bit will default to 0. BIOS can set it to 1 or 0.

Bit Description

63:3 Reserved. These bits will return 0 when read.

2Timer 2 Interrupt Active (T02_INT_STS) — R/W. Same functionality as Timer 0.

1Timer 1 Interrupt Active (T01_INT_STS) — R/W. Same functionality as Timer 0.

Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit

depends on whether the edge or level-triggered mode is used for this timer. (default =

If set to level-triggered mode:

This bit will be set by hardware if the corresponding timer interru p t is active. Once the

bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0

to this bit will have no effect.

If set to edge-triggered mode:

This bit should be ignored by software. Software should always write 0 to this bit.

NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes

will have no effect.

High Precision Event Timer Registers

762 Intel ® ICH7 Family Datasheet

20.1.4 MAIN_CNT—Main Counter Value Register

Address Offset: 0F0h Attribute: R/W

Default Value: N/A Size: 64 bits

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities

Address Offset: Timer 0: 100–107h, Attribute: RO, R/W

Timer 1: 120–127h,

Timer 2: 140–147h

Default Value: N/A Size: 64 bits

Note: The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2.

Bit Description

63:0

Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of

the counter. Writes load the new value to the counte r.

NOTES:

1. Writes to this register should only be done while the counter is halted.

2. Reads to this register return the current value of the main counter.

3. 32-bit counters will always return 0 for the upper 32-bits of this register.

4. If 32-bit software attempts to read a 64-bit counter, it should first h alt the

counter. Since this delays the interrupts for all of the timers, this should be

done only if the conseq uences are understood. It is strongly recommended

that 32-bit software only operate the timer in 32-bit mode.

5. Reads to this register are monotonic. No two consecutive reads return the

same value. The second of two reads always returns a larger value (unless

the timer has rolled over to 0).

Bit Description

63:56 Reserved. These bits will return 0 when read.

55:52,

Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO.

Timer 0, 1: Bits 52, 53, 54, an d 55 in this field (corresponding to IRQ 20, 21, 22,

and 23) have a value of 1. Writes will have no effect.

Timer 2: Bits 43, 52, 53, 54, and 55 i n this field (corresponding to IR Q 11, 20, 21,

22, and 23) have a value of 1. Writes will have no effect.

NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared

with any other devices to ensure the proper operation of HPET #2.

51:44,

42:14 Reserved. These bits return 0 when read.

Intel ® ICH7 Family Datasheet 763

High Precision Event Timer Registers

13:9

Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the

routing for the interrupt to the I/O (x) APIC. Software writes to this field to select

which interrupt i n the I/O (x ) will be use d for this timer’ s interrupt. If the value is not

supported by this particular timer, then the value read back will not match what is

written. The software must only write valid values.

NOTES:

1. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a

different routing, and this bit field has no effect for those two timers.

2. Timer 0,1: Software is responsible to mak e sure it programs a v alid value (20,

21, 22, or 23) for this field. The ICH7 logic does not check the validity of the

value writ te n.

3. Timer 2: Software is responsible to make sure it programs a valid value (11,

20, 21, 22, or 23) for this field. The ICH7 logic does not check the validity of

the value written.

Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set

this bit to force a 64-bit timer to behave as a 32-bit timer. This is typically needed if

software is not willing to halt the main counter to read or write a particular timer, and

the software is not capable of atomic 64-bit operations to the timer. This bit is only

relevant if the timer is operating in 64-bit mode in which case that timer can be

forced to 32-bit mode by setting this bit. When Timer 0 is switched to 32-bit mode,

the upper 32-bits are loaded with 0’s which will remain when the timer is switched

back to 64-bit mode. If the timer is not in 64-bit mode, then this bit will always be

read as 0 and writes will have no effect.

Timer 0: Bit is read/write (default to 0). 0 = 64 bit; 1= 32 bit

Timers 1, 2: Hardwired to 0. Writes have no effect since these timers are 32- b it

only.

7 Reserved. This bit returns 0 when read.

Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only

for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software

is then allowed to directly s et the timer’s accumulat or. Software does not have to

write this bit back to 1 (it automatically clears).

Software should not write a 1 to this bit position if the timer is set to non-periodic

mode.

NOTE: This bit will return 0 when read. Wr ites will only have an effect for Timer 0 if it

is set to periodic mode. Writes will have no effect for Timers 1 and 2.

Timer n Size (TIMERn_SIZE_CAP) — RO . This read only field indicates the size of

the timer.

Timer 0: Value is 1 (64-bits).

Timers 1, 2: Value is 0 (32-bits).

Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the

hardware supports a periodic mode for this timer’s interrupt.

Timer 0: Hardwired to 1 (supports the periodic interrupt).

Timers 1, 2: Hardwired to 0 (does not support periodic interrupt).

Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.

Timer 0: Bit is read/write. 0 = Dis able timer to ge ner ate periodic interrupt; 1 =

Enable timer to generate a periodic interrupt.

Timers 1, 2: Hardwired to 0. Writes have no effect.

Bit Description

High Precision Event Timer Registers

764 Intel ® ICH7 Family Datasheet

NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any

unimplemented registers will return an undetermined value.

20.1.6 TIMn_COMP—Timer n Comparator Value Register

Address Offset: Timer 0: 108h–10Fh,

Timer 1: 128h–12Fh,

Timer 2: 148h–14Fh

Attribute: R/W

Default Value: N/A Size: 64 bit

Timer n Interrupt En able (TIMERn_INT_ENB_CNF ) — R/W. This bit must be set

to enable timer n to cause an interrupt when it times out.

0 = Enable.

1 = Disable (Default). The time r can s t ill count and generate appropriate status bits,

but will not cause an interrupt.

Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.

0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is

generated. If another interrupt occurs, another edge will be generated.

1 = The timer interrupt is level triggered. This means that a level-triggered interrupt

is generated. The interrupt will be he ld active until it is cleared by writing to the

bit in the General Interrupt Status Register. If another interrupt occurs before the

interrupt is cleared, the interrupt will remain active.

0 Reserved. These bits will return 0 when read.

Bit Description

63:0

Timer Compare Value — R/W. R eads to this register return the current va lue of the

comparator

Timers 0, 1, or 2 are configured to non-periodic mode:

Writes to this register load the value against which the main counter should be

compared for this timer.

• When the main counter equals the value last written to this register, the corresponding

interrupt can be generated (if so enabled).

• The value in this register does not change based on the interrupt being generated.

Timer 0 is configured to periodic mode:

• When the main counter equals the value last written to this register, the corresponding

interrupt can be generated (if so enabled).

• After the main counter equals the value in this register, the value in this register is increased

by the value last written to the register.

For example, if the value written to the register is 00000123h, then

1. An interrupt will be generated when the main counter reaches 00000123h.

2. The value in this register will then be adjusted by the hardware to 00000246h.

3. Another interrupt will be generated when the main counter reaches 00000246h

4. The value in this register will then be adjusted by the hardware to 00000369h

• As each periodic interrupt occurs, the value in this register will increment. When the

incremented value is greater than the maximum value possible for this register (FFFFFFFFh

for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around

through 0. F or example, if the current v a lue in a 32-bit timer is FFFF0000h and the last v alue

written to this register is 20000, then after the next interrupt the value will change to

00010000h

Default val ue for each timer is al l 1 s for the bits that are i mpl em en te d. For exampl e,

a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a

default value of FFFFFFFFFFFFFFFFh.

Intel ® ICH7 Family Datasheet 765

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

21 Serial Peripheral Interface

(SPI) (Desktop and Mobile

Only)

The Serial Peripheral Interface resides in memory mapped space. This function contains

registers that allow for the setup and programming of devices that reside on the SPI

interface.

Note: All registers in this function (including memory-mapped registers) must be addressable

in Byte, W ord, and DW ord quantities. The softw are must always make register accesses

on natural boundaries (i.e., DWord accesses must be on DWord boundaries; word

accesses on word boundaries, etc.) In addition, the memory-mapped register space

must not be accessed with the LOCK semantic exclusive-access mechanism. If software

attempts exclusive-access mechanisms to the SPI memory-mapped space, the results

are undefined.

21.1 Serial Peripheral Interface Memory Mapped

Configuration Registers

The SPI Host Interface registers are memory-mapped in the RCRB Chipset Register

Space with a base address (SPIBAR) of 3020h and are located within the range of

3020h to 308Fh. The individual registers are then accessible at SPIBAR + Offset as

indicated in the following table.

These memory mapped registers must be accessed in byte, word, or DWord quantities.

Table 21-1. Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) (Sheet 1 of 2)

SPIBAR +

Offset Mnemonic Register Name Default Access

00h–01h SPIS SPI Status See Register

Description RO, R/WC,

R/WLO

02h–03h SPIC SPI Control 0001h R/W

04h–07h SPIA SPI Address 00000000h R/W

08h–0Fh SPID0 SPI Data 0 See Register

Description R/W

10h–17h SPID1 SPI Data 1 00000000

00000000h R/W

18h–1Fh SPID2 SPI Data 2 00000000

00000000h R/W

20h–27h SPID3 SPI Data 3 00000000

00000000h R/W

28h–2Fh SPID4 SPI Data 4 00000000

00000000h R/W

30h–37h SPID5 SPI Data 5 00000000

00000000h R/W

38h–3Fh SPID6 SPI Data 6 00000000

00000000h R/W

40h–47h SPID7 SPI Data 7 00000000

00000000h R/W

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

766 Intel ® ICH7 Family Datasheet

50h–53h BBAR BIOS Base Address Configuration 00000000h R/W

54h–55h PREOP Prefix Opcode Configuration 0004h R/W

56h–57h OPTYPE Opcode Type Configuration 0000h R/W

58h–5Fh OPMENU Opcode Menu Configuration 00000000

00000005h R/W

60h–63h PBR0 Protected BIOS Range 0 00000000h R/W

64h–67h PBR1 Protected BIOS Range 1 00000000h R/W

68h–6Bh PBR2 Protected BIOS Range 2 00000000h R/W

6Ch–6Fh — Reserved — —

Table 21-1. Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)

SPIBAR +

Offset Mnemonic Register Name Default Access

Intel ® ICH7 Family Datasheet 767

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

21.1.1 SPIS—SPI Status Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 00h A ttribute: RO, R/WC, R/WLO

Default Value: See bit description Size: 16 bits

Bit Description

SPI Configuration Lock-Down — R/WLO.

0 = No Lock-Down (Default)

1 = SPI Static Configuration information in offsets 50h through 6Fh can not be

overwritten. Once set to 1, this bit can only be cleared by a hardware reset.

14:4 Reserved

Blocked Access Status — R/WC.

0 = Not blocked (Default)

1 = Hardware sets this bit to 1 when an access is blocked from running on the SPI

interface due to one of the protection policies or when any of the programmed cycle

registers is writt en while a progr ammed access is already in progress. This bit is set

for both programmed accesses and direct memory reads that get blocked.

NOTE: This bit remains asserted until cleared by software writing a 1 or hardware

reset.

Cycle Done Status— R/WC.

0 = Not done (Default)

1 = The Intel® ICH7 sets this bit to 1 when the SPI Cycle completes (i.e. , SCIP bit is 0)

after software sets the SCGO bit.

NOTE: This bit remains asserted until cleared by software writing a 1 or hardware

reset.

NOTE: Software must make sure this bit is cleared prior to enabling the SPI SMI#

assertion for a new programmed access.

NOTE: This bit gets set after the Status Register Po lling sequence completes after res et

deasserts. It is cleared before and during that sequence.

SPI Access Grant — RO. This bit is used by the software to know when the other SPI

master will not be initiating any long transactions on the SPI bus.

0 = Default

1 = It is set by hardware in response to software setting the SPI Access R equest bit and

completing the Future Pending handshake with the LAN component.

NOTE: This bit is cleared in response to software clearing the SPI Access Request bit.

SPI Cycle In Progress (SCIP) — RO.

0 = Cycle Not in Progress (Default)

1 = Hardware sets this bit when software sets the SPI Cycle Go bit in the Command

Hardware automatically sets and clears this bit so that software can determine

when read data is valid and/or when it is safe to begin programming the next

command.

This bit reports 1b during the Status Register Polling sequence after reset deasserts; it

is cleared when that sequence complete s.

NOTE: Software must only program the next command when this bit is 0.

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

768 Intel ® ICH7 Family Datasheet

21.1.2 SPIC—SPI Control Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 02h Attribute: R/W

Default Value: 4005h Size: 16 bits

Bit Description

15 SPI SMI# Enable — R/W.

0 = Disable.

1 = Enable. The SPI asserts an SMI# request when the Cycle Done Status bit is 1.

DATA Cycle— R/W.

0 = No data is delivered for this cycle, and the DBC and data fields themselves are

don't cares.

1 = There is data that corresponds to this transaction.

13:8

Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or

out during the data portion of the SPI cycle. The valid settings (in decimal) are any

value from 0 to 63. The number of bytes transferred is the value of this field plus 1.

For example, when this field is 000000b, then there is 1 byte to transfer and that

111111b means there are 64 bytes to transfer.

7 Reserved

6:4 Cycle Opcode Po in t er — R/W. This field selects one of the programmed opcodes in

the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic

Cycle Sequence, this determines the second comman d.

Sequence Prefix Opcode Pointer — R/W. This fi eld selects one of the two

programmed prefix opcodes for use when performing an Atomic Cycle Sequence. By

making this programmable, the Intel® ICH7 supports flash devices that have different

opcodes for enabling writes to the data space vs. status register

0 = A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes

Atomic Cycle Sequence (A CS ) — R/W.

0 = No atomic cycle sequence.

1 = When set to 1 along with the SCGO assertion, the ICH7 will execute a sequence of

commands on the SPI interface without allowing the LAN component to arbitrate

and interleave cycles.

SPI Cycle Go (SCGO) — R/W. This bit always returns 0 on reads.

0 = SPI cycle Not started.

1 = A write to this register with a 1 in this bit starts the SPI cycle defined by the other

bits of this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action.

NOTE: Writes to this bit while the Cycle In Progress bit is set are ignored.

NOTE: Other bits in th is register can be programmed for the same transaction when

writing this bit to 1.

SPI Access Request — R/W. This bit is used by software to request that the ot her SPI

master stop initiating long transactions on the SPI bus.

0 = No request.

1 = Request that the other SPI master stop initiating long transactions on the SP I bus.

NOTE: This bit defaults to a 1 and must be cleared by BIOS after completing the

accesses for the boot proc ess.

Intel ® ICH7 Family Datasheet 769

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

21.1.3 SPIA—SPI Address Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 04h A ttribute: R/W

Default Value: 0 0000000h Size: 32 bits

21.1.4 SPID[N] —SPI Data N Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPI Data [0]: SPIBAR + 08hAttribute: R/W

SPI Data [1]: SPIBAR + 10h

SPI Data [2]: SPIBAR + 18h

SPI Data [3]: SPIBAR + 20h

SPI Data [4]: SPIBAR + 28h

SPI Data [5]: SPIBAR + 30h

SPI Data [6]: SPIBAR + 38h

SPI Data [7]: SPIBAR + 40h

Default Value: See Notes 1 and 2 below Size: 64 bits

NOTES:

1. For SPI Data [7:1] Registers Only: Default value is 0000000000000000h.

2. For SPI Data 0 Register default value only: This register is initialized to 0 by the reset

assertion. Howeve r, the least signific ant byt e of this regi ster is loade d with th e first Status

reset. Therefore, bit 0 of this register can be read later to determine if the platform

encountered the boundary case in which the SPI flash was busy with an internal instruction

when the platform reset deasserted.

Bit Description

31:24 Reserved

23:0 SPI Cycle Address (SCA) — R/W. This field is shifted out as th e SPI Address (MSb

first). Bits 23:0 correspond to Address bits 23:0.

Bit Description

63:0

SPI Cycle Data [N] (SCD[N]) — R/W. This field is shifted out as the SPI Data on the

Master-Out Slave-In Data pin during the data portion of the SPI cycl e. The SCD[N]

This register also shifts in the data from the Master-In Slave-Out pin into this register

during the data portion of the SPI cycle.

NOTE: The data is always shifted starting with the least significant byte, msb to lsb,

followed by the next least significant byte, msb to lsb, etc. Specifically, the shift

order on SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-

…8-23-22-…16-31…24 -39..32…etc. Bit 56 is the last bit shifted out/in. There are

no alignment assumptions; byte 0 always represents the value specified by the

cycle address.

NOTE: The data in this register may be modified by the hardware during any

programmed SPI transaction. Direct Memory Reads do not modify the contents

of this register.

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

770 Intel ® ICH7 Family Datasheet

21.1.5 BBAR—BIOS Base Address Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 50h Attribute: R/W

Default Value: 00000000h Size: 32 bits

NOTE: This register is not wri table when th e SPI Configur at ion Lock-Down bit (SPIBAR + 00h:15)

is set.

21.1.6 PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 54h Attribute: R/W

Default Value: 0004h Size: 16 bits

NOTE: This register is not wri table when th e SPI Configur at ion Lock-Down bit (SPIBAR + 00h:15)

is set.

Bit Description

31:24 Reserved.

23:8

Bottom of System Flash — R/W. This field determines the bottom of the System

BIOS. The Intel® ICH7 will not run programmed commands nor memory reads whose

address field is less than this value. This field corresponds to bits 23:8 of the 3-byte

address; bits 7:0 are assumed to be 00h for this vector when comparing to a potential

SPI address.

NOTE: Software must always program 1s into the upper, Don’t Care, bits of this field

based on the flash size. Hardware does not know the size of the flash arra y and

relies upon the correct programming by software. The default value of 0000h

results in all cycles allowed.

NOTE: In the event that this value is programmed below some of the BIOS Memory

segments, described above, this protection policy takes precedence.

7:0 Reserved

Bit Description

15:8 Prefix Opcode 1— R/W. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence.

7:0 Prefix Opcode 0 — R/W. Software programs an SPI opcode into this field that is

permitted to run as the first command in an atomic cycle sequence.

Intel ® ICH7 Family Datasheet 771

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

21.1.7 OPTYPE—Opcode Type Configur ation Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 56h A ttribute: R/W

Default Value: 0 000h Size: 16 bits

Entries in this register correspond to the entries in the Opcode Menu Configuration

Note: The definition below only provides write protection for opcodes that have addresses

associated with them. Therefore, any erase or write opcodes that do not use an address

should be avoided (for example, “Chip Er ase” and “Auto-Address Increment Byte

Program”)

NOTE: This register is not writab le when the SPI Co nfig ur ation Lock-Down bit (SPIBAR + 00h:15)

is set.

Bit Description

15:14 Opcode Type 7 — R/W. See the description for bits 1:0

13:12 Opcode Type 6 — R/W. See the description for bits 1:0

11:10 Opcode Type 5 — R/W. See the description for bits 1:0

9:8 Opcode Type 4 — R/W. See the description for bits 1:0

7:6 Opcode Type 3 — R/W. See the description for bits 1:0

5:4 Opcode Type 2 — R/W. See the description for bits 1:0

3:2 Opcode Type 1 — R/W. See the description for bits 1:0

1:0

Opcode Type 0 — R/W. This field specifies information about the corresponding

Opcode 0. This information allows the hardware to , 1) know whether to use the address

field and, 2) provide BIOS and Shared Flash protection capabilities. The encoding of the

two bits is:

00 = No address associated with this Opcode; Read cycle type

01 = No address associate d with this Opcode; Write cycle type

10 = Address required; Read cycle type

11 = Address required; Write cycle type

Serial Peripheral Interface (SPI) (Desktop and Mobile Only)

772 Intel ® ICH7 Family Datasheet

21.1.8 OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers)

Memory Address:SPIBAR + 58h Attribute: R/W

Default Value: 0000000000000005h Size: 64 bits

Eight entries are av ailable in this register to give BIOS a sufficient set of com mands for

communicating with the flash device, while also restricting what malicious software can

do. This keeps the hardware flexible enough to operate with a wide variety of SPI

devices.

Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu.

Malicious software could then perform writes and erases to the SPI flash without using

the atomic cycle mechanism. This could cause functional failures in a shared flash

environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.

NOTE: This register is not wri table when th e SPI Configur at ion Lock-Down bit (SPIBAR + 00h:15)

is set.

21.1.9 PBR[N]—Protected BIOS Range [N]

(SPI Memory Mapped Configuration Registers)

Memory Address:PBR[0]: SPIBAR + 60h Attribute: R/W

PBR[1]: SPIBAR + 64h

PBR[2]: SPIBAR + 68h

Default Value: 00000000h Size: 32 bits

NOTE: This register is not wri table when th e SPI Configur at ion Lock-Down bit (SPIBAR + 00h:15)

is set.

Bit Description

63:56 Allowable Opcode 7 — R/W. See the description for bits 7:0

55:48 Allowable Opcode 6 — R/W. See the description for bits 7:0

47:40 Allowable Opcode 5 — R/W. See the description for bits 7:0

39:32 Allowable Opcode 4 — R/W. See the description for bits 7:0

31:24 Allowable Opcode 3 — R/W. See the description for bits 7:0

23:16 Allowable Opcode 2 — R/W. See the description for bits 7:0

15:8 Allowable Opcode 1 — R/W. See the description for bits 7:0

7:0 Allowable Opcode 0 — R/W. Software programs an SPI opcode into this field for use

when initiating SPI commands through the Control Register.

Bit Description

31 Write Protection Enable — R/W.

0 = Disable. The base and limit fields are ignored when this bit is cleared.

1 = Enable. The Base and Limit fields in this register are valid.

30:24 Reserved

23:12

Protected Range Limit — R/W. This field corresponds to SPI address bits 23:12 and

specifies the upper limit of the protected range.

NOTE: Any address greater than the value programmed in this field is unaffected by

this protected range.

11:0

Protected Range Ba se — R/W. This field corresponds to SPI address bits 23:12 and

specifies the lower base of the prot ected range.

NOTE: Address bits 11:0 are assumed to be 000h for the base comparison. Any

address less than the value programmed in this field is unaffected by this

protected range.

Intel ® ICH7 Family Datasheet 773

Ballout Definition

22 Ballout Definition

This chapter contains the Intel® ICH7 family ballout information.

22.1 Desktop, Mobile, and Digital Home Component

Ballout

Figure 22-1 and Figure 22-2 are the ballout map of the ICH7 Desktop, Mobile, and

Digital Home components. These components are in a 652 BGA package. Table 22-1 is

a BGA ball list, sorted alphabetically by signal name.

Note:

1. † — Throughout this section, the symbol “†” indicates a signal that is Reserved on

the 82801GB ICH7 base component but is used by other ICH7 Desktop/Mobile/

Digital Home F amily components. This pertains to the signals for PCI Express Ports

5 and 6; these signals are not on the ICH7 base and are reserved (Marked as

“Reserved†”).

2. †† — Throughout this section, the symbol “††” indicates a Digital Home Only

signal. These signals are only on the 82801GDH ICH7DH.

3. * — Throughout this section, the symbol “*” indicates a Mobile Only signal. These

signals are only on the 82801GBM ICH7-M and 82801GHM ICH7-M DH.

4. ** — Throughout this section, the symbol “**” indicates a Desktop Only signal

(82801GB ICH7, 82801GR ICH7R, and 82801GDH ICH7DH).

5. NC = No Connect

Ballout Definition

774 Intel ® ICH7 Family Datasheet

Figure 22-1. Desktop and Mobile Component Ballout (Topview–Left Side)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

AVcc1_5_A OC6# /

GPIO30 PIRQA# Vss Vcc3_3 AD27 IRDY# AD26 PCICLK AD20 AD19 DEVSEL# REQ4# /

GPIO22 GNT4# /

GPIO48

BVss CLK48 OC7# /

GPIO31 PIRQB# PIRQD# AD29 Vcc3_3 Vss AD25 SERR# Vss AD12 Vcc3_3 Vss

CVccUSBPLL Vss OC5# /

GPIO29 OC1# PIRQC# Vss AD28 GPIO1 /

REQ5# PERR# Vcc3_3 AD17 C/BE1# AD13 AD9

DUSBRBIAS USBRBIAS# OC0# OC3# OC2# AD31 REQ0# GPIO17 /

GNT5# AD24 Vss AD18 C/BE2# Vss AD11

EVss Vss VccSus3_3 Vss OC4# AD30 GNT0# Vss AD23 PAR PLOCK# AD16 REQ3# AD10

FUSBP0N USBP0P Vss Vss Vss V5REF_Sus GPIO3 /

PIRQF# GPIO4 /

PIRQG# Vcc3_3 AD22 AD21 Vss GNT3# TRDY#

GVss Vss USBP1P USBP1N Vss Vss GPIO5 /

PIRQH# GPIO2 /

PIRQE# Vss V5REF Vcc3_3 Vcc3_3 AD15 Vss

HUSBP2N USBP2P Vss Vss Vss Vcc1_5_A Vcc1_5_A

JVss Vss USBP3P USBP3N Vss Vcc1_5_A Vcc1_5_A

KUSBP4N USBP4P VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus1_05

LVccSus3_3 VccSus3_3 VccSus3_3 USBP5N USBP5P VccSus3_3 VccSus3_3 Vcc1_05 Vcc1_05 Vss Vcc1_05

MUSBP6N USBP6P Vss Vss Vss VccSus3_3 VccSus3_3 Vcc1_05 Vss Vss Vss

NVss Vss USBP7P USBP7N Vss Vss VccSus3_3 Vss Vss Vss Vss

PSPI_ARB SPI_MISO Vss Vss SPI_MOSI SPI_CS# VccSus3_3 Vcc1_05 Vss Vss Vss

RVss SPI_CLK GPIO24 GPIO14 ACZ_RST# ACZ_SYNC VccSus3_3 /

VccSusHDA* Vss Vss Vss Vss

TACZ_SDIN2 ACZ_SDIN0 ACZ_SDIN1 ACZ_SDOUT LAN_RXD2 Vss Vcc1_5_A Vcc1_05 Vss Vss Vss

UACZ_BIT_CLK GPIO34 /

AZ_DOCK_

RST#*

LAN_

RSTSYNC Vss LAN_RXD0 Vcc3_3 /

VccHDA* LAN_TXD0 Vcc1_05 Vss Vss Vss

VVccSus3_3 /

VccLAN3_3* Vss LAN_CLK LAN_RXD1 VccSus3_3 /

VccLAN3_3* LAN_TXD1 LAN_TXD2 Vcc1_05 Vcc1_05 Vss Vcc1_05

WEE_CS VccSus3_3 /

VccLAN3_3* EE_DIN INTVRMEN VccRTC Vss VccSus3_3 /

VccLAN3_3*

YEE_SHCLK EE_DOUT Vss RSMRST# INTRUDER# LAD3 VccSus1_05 /

VccLAN1_05*

AA Vss VccSus1_05 /

VccLAN1_05* RTCRST# PWROK LDRQ1# /

GPIO23 LAD0 Vcc3_3

AB RTCX1 RTCX2 LFRAME# Vss LAD1 Vss Vcc1_5_A Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss Vcc3_3 DD10 Vss

AC CLK14 Vss LDRQ0# LAD2 Vss Vcc1_5_A Vcc1_5_A Vcc1_5_A Vss Vcc1_5_A Vss DD7 DD5 DD11

AD Vss VccSATAPLL Vss Vss SA TA1RXP /

Reserved* Vcc1_5_A Vss Vss SATA3RXN

/ Reserved* Vcc1_5_A Vss DD6 Vcc3_3 DD4

AE SATA_CLKP Vss SATA0RXP Vss SA T A1 RXN /

Reserved* Vcc1_5_A SATA2RXP Vss SATA3RXP

/ Reserved* Vcc1_5_A Vss DD8 Vss DD1

AF SATA_CLKN Vss SATA0RXN Vss Vcc1_5_A Vcc1_5_A SATA2RXN Vss Vcc1_5_A Vcc1_5_A Vss DD9 DD3 DD12

AG Vss SATA0TXN Vss SATA1TXN /

Reserved* Vcc1_5_A SATA2TXN Vss SATA3TXN /

Reserved* Vcc1_5_A SATARBIASP Vss Vcc3_3 DD2 Vss

AH Vss SATA0TXP Vss SATA1TXP /

Reserved* Vcc1_5_A SATA2TXP Vss SATA3TXP /

Reserved* Vcc1_5_A SATARBIASN Vcc3_3 VSS DD13 DD14

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Intel ® ICH7 Family Datasheet 775

Ballout Definition

Figure 22-2. Desktop and Mobile Component Ballout (Topview–Rig ht Side)

15 16 17 18 19 20 21 22 23 24 25 26 27 28

AD8 AD2 AD7 AD5 SPKR GPIO10 EL_RSVD†† /

GPIO26 SYS_RST# Vss VccSus3_3 SMLINK1 LINKALERT# SUS_STAT# RI# A

C/BE0# Vcc3_3 Vss PCIRST# PME# Vss EL_ST A TE0†† /

GPIO27 SMBDATA SMBALERT# /

GPIO11 SLP_S3# SMLINK0 Vss Vcc3_3 Vss B

C/BE3# REQ1# REQ2# AD1 LAN_RST# SUSCLK TP0 /

BATLOW#* SMBCLK PWRBTN# VccSus3_3 DMI_ZCOMP PLTRST# Vss VccSus1_05 C

Vcc3_3 GNT1# GNT2# Vss VccSus3_3 GPIO25 Vss VccSus3_3 SLP_S4# Vss DMI_IRCOMP Vcc1_5_B Vcc1_5_B Vcc1_5_B D

Vss AD4 AD6 AD0 GPIO13 GPIO9 GPIO8 GPIO15 EL_ST ATE1††

/ GPIO28 Vcc1_5_B Vcc1_5_B Vcc1_5_B PETp1 PETn1 E

STOP# FRAME# Vcc1_5_A AD3 GPIO12 WAKE# TP3 SLP_S5# Vcc1_5_B Vcc1_5_B PERp1 PERn1 Vss Vss F

AD14 Vcc3_3 Vcc1_5_A Vss VccSus3_3 VccSus1_05 Vss Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp2 PETn2 G

Vcc1_5_B Vcc1_5_B Vss PERp2 PERn2 Vss Vss H

Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp3 PETn3 J

Vcc1_5_B Vcc1_5_B Vss PERp3 PERn3 Vss Vss K

Vss Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp4 PETn4 L

Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss PERp4 PERn4 Vss Vss M

Vss Vss Vss Vss Vcc1_5_B Vcc1_5_B Vss Vss Vss PETp5 /

Reserved† PETn5 /

Reserved† N

Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss PERp5 /

Reserved† PERn5 /

Reserved† Vss Vss P

Vss Vss Vss Vss Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B PETp6 /

Reserved† PETn6 /

Reserved† R

Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B PERp6 /

Reserved† PERn6 /

Reserved† Vcc1_5_B Vcc1_5_B Vcc1_5_B T

Vss Vss Vss Vcc1_05 Vcc1_5_B Vcc1_5_B Vss Vss Vss DMI0TXP DMI0TXN U

Vss Vcc1_05 Vcc1_05 Vcc1_05 Vcc1_5_B Vcc1_5_B Vss DMI0RXP DMI0RXN Vss Vss V

Vcc1_5_B Vcc1_5_B Vss Vss Vss DMI1TXP DMI1TXN W

Vcc1_5_B Vcc1_5_B Vss DMI1RXP DMI1RXN Vss Vss Y

Vcc1_5_B Vcc1_5_B Vss Vss Vss DMI2TXP DMI2TXN AA

DD0 Vss Vcc1_5_A GPIO0 /

BM_BUSY#* Vss Vcc3_3 Vss Vcc1_5_B Vcc1_5_B Vss DMI2RXP DMI2RXN Vss Vss AB

DD15 Vcc3_3 Vcc1_5_A GPIO7 GPIO33 /

AZ_DOCK_EN#* GPIO18 /

STP_PCI#* GPIO6 GPIO16 /

DPRSLPVR* Vcc1_5_B Vcc1_5_B Vcc1_5_B Vcc1_5_B DMI3TXP DMI3TXN AC

Vss DCS3# V5REF Vcc3_3 Vss GPIO38 GPIO35 /

SATACLKREQ# VRMPWRGD Vss DMI3RXP DMI3RXN Vcc1_5_B Vcc1_5_B Vcc1_5_B AD

DDREQ DCS1# DA1 Vss GPIO37 /

SATA3GP** GPIO39 Vss A20GATE V_CPU_IO Vss Vss V_CPU_IO DMI_CLKP DMI_CLKN AE

DIOR# DDACK# DA2 SATALED# GPIO21 /

SATA0GP THRM# GPIO20 /

STPCPU# INIT# SMI# TP1 /

DPRSTP#* INTR THERMTRIP# Vss Vss AF

Vcc3_3 IORDY Vss GPIO32 /

CLKRUN#* Vcc3_3 Vss INIT3_3V# IGNNE# RCIN# GPIO49/

CPUPWRGD Vss FERR# CPUSLP#**/

NC* VccDMIPLL AG

DIOW# IDEIRQ DA0 GPIO19 /

SATA1GP** GPIO36 /

SATA2GP MCH_SYNC# SERIRQ STPCLK# Vss NMI TP2 /

DPSLP#* V_CPU_IO Vss A20M# AH

15 16 17 18 19 20 21 22 23 24 25 26 27 28

776 Intel ® ICH7 Family Datasheet

Ballout Definition

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

A20GATE AE22

A20M# AH28

ACZ_BIT_CLK U1

ACZ_RST# R5

ACZ_SDIN0 T2

ACZ_SDIN1 T3

ACZ_SDIN2 T1

ACZ_SDOUT T4

ACZ_SYNC R6

AD0 E18

AD1 C18

AD2 A16

AD3 F18

AD4 E16

AD5 A18

AD6 E17

AD7 A17

AD8 A15

AD9 C14

AD10 E14

AD11 D14

AD12 B12

AD13 C13

AD14 G15

AD15 G13

AD16 E12

AD17 C11

AD18 D11

AD19 A11

AD20 A10

AD21 F11

AD22 F10

AD23 E9

AD24 D9

AD25 B9

AD26 A8

AD27 A6

AD28 C7

AD29 B6

AD30 E6

AD31 D6

C/BE0# B15

C/BE1# C12

C/BE2# D12

C/BE3# C15

CLK14 AC1

CLK48 B2

CPUSLP#** / NC* AG27

DA0 AH17

DA1 AE17

DA2 AF17

DCS1# AE16

DCS3# AD16

DD0 AB15

DD1 AE14

DD10 AB13

DD11 AC14

DD12 AF14

DD13 AH13

DD14 AH14

DD15 AC15

DD2 AG13

DD3 AF13

DD4 AD14

DD5 AC13

DD6 AD12

DD7 AC12

DD8 AE12

DD9 AF12

DDACK# AF16

DDREQ AE15

DEVSEL# A12

DIOR# AF15

DIOW# AH15

DMI_CLKN AE28

DMI_CLKP AE27

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

DMI_IRCOMP D25

DMI_ZCOMP C25

DMI0RXN V26

DMI0RXP V25

DMI0TXN U28

DMI0TXP U27

DMI1RXN Y26

DMI1RXP Y25

DMI1TXN W28

DMI1TXP W27

DMI2RXN AB26

DMI2RXP AB25

DMI2TXN AA28

DMI2TXP AA27

DMI3RXN AD25

DMI3RXP AD24

DMI3TXN AC28

DMI3TXP AC27

EE_CS W1

EE_DIN W3

EE_DOUT Y2

EE_SHCLK Y1

EL_RSVD†† /

GPIO26 A21

EL_STATE0†† /

GPIO27 B21

EL_STATE1†† /

GPIO28 E23

FERR# AG26

FRAME# F16

GNT0# E7

GNT1# D16

GNT2# D17

GNT3# F13

GNT4# / GPIO48 A14

GPIO0 /

BM_BUSY#* AB18

GPIO1 / REQ5# C8

GPIO10 A20

GPIO12 F19

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 777

Ballout Definition

GPIO13 E19

GPIO14 R4

GPIO15 E22

GPIO16 /

DPRSLPVR* AC22

GPIO17 / GNT5# D8

GPIO18 /

STP_PCI#* AC20

GPIO19 /

SATA1GP** AH18

GPIO2/ PIRQE# G8

GPIO20 / STPCPU# AF21

GPIO21 / SATA0GP AF19

GPIO24 R3

GPIO25 D20

GPIO3 / PIRQF# F7

GPIO32 /

CLKRUN#* AG18

GPIO33 /

AZ_DOCK_EN#* AC19

GPIO34 /

AZ_DOCK_RST#* U2

GPIO35 /

SATACLKREQ# AD21

GPIO36 / SATA2GP AH19

GPIO37 /

SATA3GP** AE19

GPIO38 AD20

GPIO39 AE20

GPIO4 / PIRQG# F8

GPIO49 /

CPUPWRGD AG24

GPIO5 / PIRQH# G7

GPIO6 AC21

GPIO7 AC18

GPIO8 E21

GPIO9 E20

IDEIRQ AH16

IGNNE# AG22

INIT# AF22

INIT3_3V# AG21

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

INTR AF25

INTRUDER# Y5

INTVRMEN W4

IORDY AG16

IRDY# A7

LAD0 AA6

LAD1 AB5

LAD2 AC4

LAD3 Y6

LAN_CLK V3

LAN_RST# C19

LAN_RSTSYNC U3

LAN_RXD0 U5

LAN_RXD1 V4

LAN_RXD2 T5

LAN_TXD0 U7

LAN_TXD1 V6

LAN_TXD2 V7

LDRQ0# AC3

LDRQ1# / GPIO23 AA5

LFRAME# AB3

LINKALERT# A26

MCH_SYNC# AH20

NMI AH24

OC0# D3

OC1# C4

OC2# D5

OC3# D4

OC4# E5

OC5# / GPIO29 C3

OC6# / GPIO30 A2

OC7# / GPIO31 B3

PAR E10

PCICLK A9

PCIRST# B18

PERn1 F26

PERn2 H26

PERn3 K26

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

PERn4 M26

PERn5 /

Reserved† P26

PERn6 /

Reserved† T25

PERp1 F25

PERp2 H25

PERp3 K25

PERp4 M25

PERp5 /

Reserved† P25

PERp6 /

Reserved† T24

PERR# C9

PETn1 E28

PETn2 G28

PETn3 J28

PETn4 L28

PETn5 /

Reserved† N28

PETn6 /

Reserved† R28

PETp1 E27

PETp2 G27

PETp3 J27

PETp4 L27

PETp5 /

Reserved† N27

PETp6 /

Reserved† R27

PIRQA# A3

PIRQB# B4

PIRQC# C5

PIRQD# B5

PLOCK# E11

PLTRST# C26

PME# B19

PWRBTN# C23

PWROK AA4

RCIN# AG23

REQ0# D7

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

778 Intel ® ICH7 Family Datasheet

Ballout Definition

REQ1# C16

REQ2# C17

REQ3# E13

REQ4# / GPIO22 A13

RI# A28

RSMRST# Y4

RTCRST# AA3

RTCX1 AB1

RTCX2 AB2

SATA_CLKN AF1

SATA_CLKP AE1

SATA0RXN AF3

SATA0RXP AE3

SATA0TXN AG2

SATA0TXP AH2

SATA1RXN /

Reserved* AE5

SATA1RXP /

Reserved* AD5

SATA1TXN /

Reserved* AG4

SATA1T XP /

Reserved* AH4

SATA2RXN AF7

SATA2RXP AE7

SATA2TXN AG6

SATA2TXP AH6

SATA3RXN /

Reserved* AD9

SATA3RXP /

Reserved* AE9

SATA3TXN /

Reserved* AG8

SATA3T XP /

Reserved* AH8

SATALED# AF18

SATARBIAS# AH10

SATARBIAS AG10

SERIRQ AH21

SERR# B10

SLP_S3# B24

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

SLP_S4# D23

SLP_S5# F22

SMBALERT# /

GPIO11 B23

SMBCLK C22

SMBDATA B22

SMI# AF23

SMLINK0 B25

SMLINK1 A25

SPI_ARB P1

SPI_CLK R2

SPI_CS# P6

SPI_MISO P2

SPI_MOSI P5

SPKR A19

STOP# F15

STPCLK# AH22

SUS_STAT# A27

SUSCLK C20

SYS_RST# A22

THERMTRIP# AF26

THRM# AF20

TP0 / BATLOW#* C21

TP1 / DPRSTP#* AF24

TP2 / DPSLP#* AH25

TP3 F21

TRDY# F14

USBP0N F1

USBP0P F2

USBP1N G4

USBP1P G3

USBP2N H1

USBP2P H2

USBP3N J4

USBP3P J3

USBP4N K1

USBP4P K2

USBP5N L4

USBP5P L5

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

USBP6N M1

USBP6P M2

USBP7N N4

USBP7P N3

USBRBIAS D1

USBRBIAS# D2

V_CPU_IO AE23

V_CPU_IO AE26

V_CPU_IO AH26

V5REF G10

V5REF AD17

V5REF_Sus F6

Vcc1_05 L11

Vcc1_05 L12

Vcc1_05 L14

Vcc1_05 L16

Vcc1_05 L17

Vcc1_05 L18

Vcc1_05 M11

Vcc1_05 M18

Vcc1_05 P11

Vcc1_05 P18

Vcc1_05 T11

Vcc1_05 T18

Vcc1_05 U11

Vcc1_05 U18

Vcc1_05 V11

Vcc1_05 V12

Vcc1_05 V14

Vcc1_05 V16

Vcc1_05 V17

Vcc1_05 V18

Vcc1_5_A A1

Vcc1_5_A F17

Vcc1_5_A G17

Vcc1_5_A H6

Vcc1_5_A H7

Vcc1_5_A J6

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 779

Ballout Definition

Vcc1_5_A J7

Vcc1_5_A T7

Vcc1_5_A AB7

Vcc1_5_A AB8

Vcc1_5_A AB9

Vcc1_5_A AB10

Vcc1_5_A AB17

Vcc1_5_A AC6

Vcc1_5_A AC7

Vcc1_5_A AC8

Vcc1_5_A AC10

Vcc1_5_A AC17

Vcc1_5_A AD6

Vcc1_5_A AD10

Vcc1_5_A AE6

Vcc1_5_A AE10

Vcc1_5_A AF5

Vcc1_5_A AF6

Vcc1_5_A AF9

Vcc1_5_A AF10

Vcc1_5_A AG5

Vcc1_5_A AG9

Vcc1_5_A AH5

Vcc1_5_A AH9

Vcc1_5_B D26

Vcc1_5_B D27

Vcc1_5_B D28

Vcc1_5_B E24

Vcc1_5_B E25

Vcc1_5_B E26

Vcc1_5_B F23

Vcc1_5_B F24

Vcc1_5_B G22

Vcc1_5_B G23

Vcc1_5_B H22

Vcc1_5_B H23

Vcc1_5_B J22

Vcc1_5_B J23

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vcc1_5_B K22

Vcc1_5_B K23

Vcc1_5_B L22

Vcc1_5_B L23

Vcc1_5_B M22

Vcc1_5_B M23

Vcc1_5_B N22

Vcc1_5_B N23

Vcc1_5_B P22

Vcc1_5_B P23

Vcc1_5_B R22

Vcc1_5_B R23

Vcc1_5_B R24

Vcc1_5_B R25

Vcc1_5_B R26

Vcc1_5_B T22

Vcc1_5_B T23

Vcc1_5_B T26

Vcc1_5_B T27

Vcc1_5_B T28

Vcc1_5_B U22

Vcc1_5_B U23

Vcc1_5_B V22

Vcc1_5_B V23

Vcc1_5_B W22

Vcc1_5_B W23

Vcc1_5_B Y22

Vcc1_5_B Y23

Vcc1_5_B AA22

Vcc1_5_B AA23

Vcc1_5_B AB22

Vcc1_5_B AB23

Vcc1_5_B AC23

Vcc1_5_B AC24

Vcc1_5_B AC25

Vcc1_5_B AC26

Vcc1_5_B AD26

Vcc1_5_B AD27

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vcc1_5_B AD28

Vcc3_3 A5

Vcc3_3 B7

Vcc3_3 B13

Vcc3_3 B16

Vcc3_3 B27

Vcc3_3 C10

Vcc3_3 D15

Vcc3_3 F9

Vcc3_3 G11

Vcc3_3 G12

Vcc3_3 G16

Vcc3_3 AA7

Vcc3_3 AB12

Vcc3_3 AB20

Vcc3_3 AC16

Vcc3_3 AD13

Vcc3_3 AD18

Vcc3_3 AG12

Vcc3_3 AG15

Vcc3_3 AG19

Vcc3_3 AH11

Vcc3_3 / VccHDA* U6

VccDMIPLL AG28

VccRTC W5

VccSATAPLL AD2

VccSus1_05 C28

VccSus1_05 G20

VccSus1_05 K7

VccSus1_05 /

VccLAN1_05* Y7

VccSus1_05 /

VccLAN1_05* AA2

VccSus3_3 A24

VccSus3_3 C24

VccSus3_3 D19

VccSus3_3 D22

VccSus3_3 E3

VccSus3_3 G19

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

780 Intel ® ICH7 Family Datasheet

Ballout Definition

VccSus3_3 K3

VccSus3_3 K4

VccSus3_3 K5

VccSus3_3 K6

VccSus3_3 L1

VccSus3_3 L2

VccSus3_3 L3

VccSus3_3 L6

VccSus3_3 L7

VccSus3_3 M6

VccSus3_3 M7

VccSus3_3 N7

VccSus3_3 P7

VccSus3_3 /

VccLAN3_3* V1

VccSus3_3 /

VccLAN3_3* V5

VccSus3_3 /

VccLAN3_3* W2

VccSus3_3 /

VccLAN3_3* W7

VccSus3_3 /

VccSusHDA* R7

VccUSBPLL C1

VRMPWRGD AD22

Vss A4

Vss A23

Vss B1

Vss B8

Vss B11

Vss B14

Vss B17

Vss B20

Vss B26

Vss B28

Vss C2

Vss C6

Vss C27

Vss D10

Vss D13

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vss D18

Vss D21

Vss D24

Vss E1

Vss E2

Vss E4

Vss E8

Vss E15

Vss F3

Vss F4

Vss F5

Vss F12

Vss F27

Vss F28

Vss G1

Vss G2

Vss G5

Vss G6

Vss G9

Vss G14

Vss G18

Vss G21

Vss G24

Vss G25

Vss G26

Vss H3

Vss H4

Vss H5

Vss H24

Vss H27

Vss H28

Vss J1

Vss J2

Vss J5

Vss J24

Vss J25

Vss J26

Vss K24

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vss K27

Vss K28

Vss L13

Vss L15

Vss L24

Vss L25

Vss L26

Vss M3

Vss M4

Vss M5

Vss M12

Vss M13

Vss M14

Vss M15

Vss M16

Vss M17

Vss M24

Vss M27

Vss M28

Vss N1

Vss N2

Vss N5

Vss N6

Vss N11

Vss N12

Vss N13

Vss N14

Vss N15

Vss N16

Vss N17

Vss N18

Vss N24

Vss N25

Vss N26

Vss P3

Vss P4

Vss P12

Vss P13

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 781

Ballout Definition

Vss P14

Vss P15

Vss P16

Vss P17

Vss P24

Vss P27

Vss P28

Vss R1

Vss R11

Vss R12

Vss R13

Vss R14

Vss R15

Vss R16

Vss R17

Vss R18

Vss T6

Vss T12

Vss T13

Vss T14

Vss T15

Vss T16

Vss T17

Vss U4

Vss U12

Vss U13

Vss U14

Vss U15

Vss U16

Vss U17

Vss U24

Vss U25

Vss U26

Vss V2

Vss V13

Vss V15

Vss V24

Vss V27

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vss V28

Vss W6

Vss W24

Vss W25

Vss W26

Vss Y3

Vss Y24

Vss Y27

Vss Y28

Vss AA1

Vss AA24

Vss AA25

Vss AA26

Vss AB4

Vss AB6

Vss AB11

Vss AB14

Vss AB16

Vss AB19

Vss AB21

Vss AB24

Vss AB27

Vss AB28

Vss AC2

Vss AC5

Vss AC9

Vss AC11

Vss AD1

Vss AD3

Vss AD4

Vss AD7

Vss AD8

Vss AD11

Vss AD15

Vss AD19

Vss AD23

Vss AE2

Vss AE4

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Vss AE8

Vss AE11

Vss AE13

Vss AE18

Vss AE21

Vss AE24

Vss AE25

Vss AF2

Vss AF4

Vss AF8

Vss AF11

Vss AF27

Vss AF28

Vss AG1

Vss AG3

Vss AG7

Vss AG11

Vss AG14

Vss AG17

Vss AG20

Vss AG25

Vss AH1

Vss AH3

Vss AH7

Vss AH12

Vss AH23

Vss AH27

WAKE# F20

Table 22-1. Desktop

and Mobile

Component Ballout

by Signal Name

Signal Name Ball #

Ballout Definition

782 Intel ® ICH7 Family Datasheet

22.2 Ultra Mobile Component Ballout

Figure 22-3 and Figure 22-4 show the ICH7-U ballout from the top of the package view.

Table 22-2 lists the ballout arranged by signal name.

Figure 22-3. Intel® ICH7-U Ballout (top view, left side)

1234567891011

AVSS VCC3_3 GNT5#/

GPIO17 AD22 PAR AD15 REQ5#/

GPIO1 PLOCK# TRDY# SERR# AD20 A

BPIRQG#/

GPIO4 AD23 AD29 VSS RSVD VSS VCC3_3 VSS PERR# AD18 VSS B

CPIRQF#/

GPIO3 RSVD RSVD AD31 AD30 RSVD AD24 IRDY# V5REF1 VSS VCC3_3 C

DOC3# VSS VCCSUS1_05 OC0# OC7#/

GPIO31 PIRQE#/

GPIO2 AD21 AD28 AD25 VCC3_3 AD16 D

EVSS VCCSUS3_3 CLK48 VSS VCCAUSBPLL VSS PIRQH#/

GPIO5 VSS GNT3# AD26 PCICLK E

FUSBP0P USBP0N USBRBIAS# USBRBIAS OC5#/

GPIO29 OC6#/

GPIO30 OC1# RSVD AD27 AD17 VSS F

GVSS USBP2P USBP2N VSS V5REF_SUS OC4# OC2# G

HUSBP4P USBP4N VSS USBP1P USBP1N VSS VCC1_5A VCC1_5A VSS VCC1_05 H

JVSS USBP5P USBP5N VSS USBP3N USBP3P VCC1_5A VCC1_5A VSS VCC1_05 J

KUSBP6P USBP6N VSS USBP7P USBP7N VSS VCC1_5A VSS VSS VSS K

LRSVD RSVD RSVD RSVD RSVD VCCSUS3_3 VSS VSS VSS VSS L

MRSVD ACZ_RST# GPIO14 VCCSUSHDA ACZ_SDIN0 RSVD VCCSUS3_3 VSS VSS VSS M

NRSVD ACZ_SDIN1 VSS VCCHDA VSS VCC1_5A VCCSUS3_3 VCCSUS3_3 VSS VSS N

PRSVD ACZ_SYNC RSVD ACZ_BIT_CLK ACZ_SDOUT VCC3_3 VCCSUS3_3 VCCSUS3_3 VSS VCC1_05 P

RRSVD RSVD RSVD NC VCC3_3 VSS VCCSUS3_3 VCCSUS3_3 VSS VCC1_05 R

TRSVD RSVD RSVD VSS RSVD VCCRTC RSVD T

URSVD RSVD RSVD INTRUDER# RTCX1 RTCX2 RTEST# VSS RSVD RSVD VSS U

VPWROK RSMRST# LAD0 RSVD RSVD RSVD RSVD RSVD DD5 VSS VCC3_3 V

WCLK14 VSS LAD2 RSVD RSVD RSVD RSVD VSS DD2 DD1 DD15 W

YLFRAME# LAD1 RSVD RSVD RSVD RSVD DD10 DD7 VCC3_3 DD12 DIOW# Y

AA LAD3 RSVD RSVD RSVD DD6 VSS DD9 DD13 VSS DDREQ IDEIRQ AA

AB VSS RSVD RSVD RSVD DD8 DD3 DD14 DD4 DD11 DIOR# DD0 AB

1234567891011

Intel ® ICH7 Family Datasheet 783

Ballout Definition

Figure 22-4. Intel® ICH7-U Ballout (top view, right side)

12 13 14 15 16 17 18 19 20 21 22

AAD14 VSS REQ4#/

GPIO22 GNT4#/

GPIO48 C/BE#_0 RSVD VCC3_3 AD1 AD0 SPKR VSS A

BAD12 AD11 FRAME# VSS AD6 PME# VSS RSVD GPIO12 VSS GPIO10 B

CC/BE#_2 AD13 STOP# C/BE#_3 AD5 RSVD GPIO9 RSVD VSS SUSCLK RSVD C

DAD19 VSS DEVSEL# VCC3_3 VSS AD2 BATLOW# PWRBTN# RSVD SYS_RST# GPIO13 D

EC/BE#_1 AD10 AD8 AD7 AD4 RSVD RSVD VSS SMBCLK WAKE# VSS E

FREQ#_3 AD9 VSS AD3 LAN_RST# SMBDATA GPIO8 GPIO15 SMBALERT#/

GPIO11 SLP_S3# SLP_S4# F

GPCIRST# RSVD RSVD SLP_S5# VCCSUS1_05 VSS SUS_STAT# G

HVSS VCC1_5A VCC1_5A VCCSUS3_3 RSVD VSS RSVD VSS VCC3_3 VSS H

JVSS VSS VSS VSS PLTRST# VSS RSVD RSVD VSS VSS J

KVSS VSS VCC1_05 VCC1_05 VSS VSS VSS VSS RSVD RSVD K

LVSS VSS VSS VCC1_05 VCC1_5B VCC1_5B DMI_ZCOMP DMI_IRCOMP VSS VSS L

MVSS VSS VCC1_05 VCC1_05 VCC1_5B VSS VSS VSS DMI0TXP DMI0TXN M

NVSS VSS VSS VCC1_05 VCC1_5B VSS DMI0RXP DMI0RXN VSS VSS N

PVSS VCC1_05 VSS VCC1_05 VCC1_5B VSS VSS VSS DMI1TXP DMI1TXN P

RVCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_5B VCC1_5B DMI1RXP DMI1RXN VSS VSS R

TVSS VSS VSS VSS VSS DMI_CLKP DMI_CLKN T

UVCC1_5A VCC1_5A VSS VCC3_3 RSVD RSVD VCCDMIPLL VSS STPCLK# VSS VSS U

VVSS VCC3_3 VSS DA0 BMBUSY#/

GPIO0 MCH_SYNC# VSS V_CPU_IO THERMTRIP# FERR# INTR V

WIORDY DDACK# DCS3# RSVD SERIRQ VSS V_CPU_IO A20M# DPRSTP# DPSLP# IGNNE# W

YV5REF2 DA2 CLKRUN# RSVD RCIN# VCC3_3 VSS CPUSLP# SMI# CPUPWRGD/

GPIO49 INIT# Y

AA VSS VCC3_3 VSS THRM# VSS A20GATE VSS V_CPU_IO NMI VSS V_CPU_IO AA

AB DCS1# DA1 GPIO7 RSVD RSVD STPPCI#/

GPIO18 RSVD GPIO6 STPCPU#/

GPIO20 DPRSLPVR/

GPIO16 VRMPWRGD AB

12 13 14 15 16 17 18 19 20 21 22

784 Intel ® ICH7 Family Datasheet

Ballout Definition

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

A20GATE AA17

A20M# W19

ACZ_BIT_CLK P4

ACZ_RST# M2

ACZ_SDIN0 M5

ACZ_SDIN1 N2

ACZ_SDOUT P5

ACZ_SYNC P2

AD0 A20

AD1 A19

AD2 D17

AD3 F15

AD4 E16

AD5 C16

AD6 B16

AD7 E15

AD8 E14

AD9 F13

AD10 E13

AD11 B13

AD12 B12

AD13 C13

AD14 A12

AD15 A6

AD16 D11

AD17 F10

AD18 B10

AD19 D12

AD20 A11

AD21 D7

AD22 A4

AD23 B2

AD24 C7

AD25 D9

AD26 E10

AD27 F9

AD28 D8

AD29 B3

AD30 C5

AD31 C4

BATLOW# D18

BMBUSY#/

GPIO0 V16

C/BE#_0 A16

C/BE#_1 E12

C/BE#_2 C12

C/BE#_3 C15

CLK14 W1

CLK48 E3

CLKRUN# Y14

CPUPWRGD/

GPIO49 Y21

CPUSLP# Y19

DA0 V15

DA1 AB13

DA2 Y13

DCS1# AB12

DCS3# W14

DD0 AB11

DD1 W10

DD2 W9

DD3 AB6

DD4 AB8

DD5 V9

DD6 AA5

DD7 Y8

DD8 AB5

DD9 AA7

DD10 Y7

DD11 AB9

DD12 Y10

DD13 AA8

DD14 AB7

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

DD15 W11

DDACK# W13

DDREQ AA10

DEVSEL# D14

DIOR# AB10

DIOW# Y11

DMI_CLKN T22

DMI_CLKP T21

DMI_IRCOMP L20

DMI_ZCOMP L19

DMI0RXN N20

DMI0RXP N19

DMI0TXN M22

DMI0TXP M21

DMI1RXN R20

DMI1RXP R19

DMI1TXN P22

DMI1TXP P21

DPRSLPVR/

GPIO16 AB21

DPRSTP# W20

DPSLP# W21

FERR# V21

FRAME# B14

GNT3# E9

GNT4#/ GPIO48 A15

GNT5#/ GPIO17 A3

GPIO6 AB19

GPIO7 AB14

GPIO8 F18

GPIO9 C18

GPIO10 B22

GPIO12 B20

GPIO13 D22

GPIO14 M3

GPIO15 F19

IDEIRQ AA11

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 785

Ballout Definition

IGNNE# W22

INIT# Y22

INTR V22

INTRUDER# U4

IORDY W12

IRDY# C8

LAD0 V3

LAD1 Y2

LAD2 W3

LAD3 AA1

LAN_RST# F16

LFRAME# Y1

MCH_SYNC# V17

NC R4

NMI AA20

OC0# D4

OC1# F7

OC2# G7

OC3# D1

OC4# G6

OC5#/ GPIO29 F5

OC6#/ GPIO30 F6

OC7#/ GPIO31 D5

PAR A5

PCICLK E11

PCIRST# G16

PERR# B9

PIRQE#/ GPIO2 D6

PIRQF#/ GPIO3 C1

PIRQG#/ GPIO4 B1

PIRQH#/ GPIO5 E7

PLOCK# A8

PLTRST# J17

PME# B17

PWRBTN# D19

PWROK V1

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

RCIN# Y16

REQ#_3 F12

REQ4#/ GPIO22 A14

REQ5#/ GPIO1 A7

RSMRST# V2

RSVD A17

RSVD AA2

RSVD AA3

RSVD AA4

RSVD AB15

RSVD AB16

RSVD AB18

RSVD AB2

RSVD AB3

RSVD AB4

RSVD B19

RSVD B5

RSVD C17

RSVD C19

RSVD C2

RSVD C22

RSVD C3

RSVD C6

RSVD D20

RSVD E17

RSVD E18

RSVD F8

RSVD G17

RSVD G18

RSVD H17

RSVD H19

RSVD J19

RSVD J20

RSVD K21

RSVD K22

RSVD L1

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

RSVD L2

RSVD L3

RSVD L4

RSVD L5

RSVD M1

RSVD M6

RSVD N1

RSVD P1

RSVD P3

RSVD R1

RSVD R2

RSVD R3

RSVD T1

RSVD T2

RSVD T3

RSVD T5

RSVD T7

RSVD U1

RSVD U10

RSVD U16

RSVD U17

RSVD U2

RSVD U3

RSVD U9

RSVD V4

RSVD V5

RSVD V6

RSVD V7

RSVD V8

RSVD W15

RSVD W4

RSVD W5

RSVD W6

RSVD W7

RSVD Y15

RSVD Y3

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

786 Intel ® ICH7 Family Datasheet

Ballout Definition

RSVD Y4

RSVD Y5

RSVD Y6

RTCX1 U5

RTCX2 U6

RTEST# U7

SERIRQ W16

SERR# A10

SLP_S3# F21

SLP_S4# F22

SLP_S5# G19

SMBALERT#/

GPIO11 F20

SMBCLK E20

SMBDATA F17

SMI# Y20

SPKR A21

STOP# C14

STPCLK# U20

STPCPU#/

GPIO20 AB20

STPPCI#/

GPIO18 AB17

SUS_STAT# G22

SUSCLK C21

SYS_RST# D21

THERMTRIP# V20

THRM# AA15

TRDY# A9

USBP0N F2

USBP0P F1

USBP1N H5

USBP1P H4

USBP2N G3

USBP2P G2

USBP3N J5

USBP3P J6

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

USBP4N H2

USBP4P H1

USBP5N J3

USBP5P J2

USBP6N K2

USBP6P K1

USBP7N K5

USBP7P K4

USBRBIAS F4

USBRBIAS# F3

V_CPU_IO AA19

V_CPU_IO AA22

V_CPU_IO V19

V_CPU_IO W18

V5REF_SUS G5

V5REF1 C9

V5REF2 Y12

VCC1_05 H11

VCC1_05 J11

VCC1_05 K14

VCC1_05 K15

VCC1_05 L15

VCC1_05 M14

VCC1_05 M15

VCC1_05 N15

VCC1_05 P11

VCC1_05 P13

VCC1_05 P15

VCC1_05 R11

VCC1_05 R12

VCC1_05 R13

VCC1_05 R14

VCC1_05 R15

VCC1_5A H13

VCC1_5A H14

VCC1_5A H8

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

VCC1_5A H9

VCC1_5A J8

VCC1_5A J9

VCC1_5A K8

VCC1_5A N6

VCC1_5A U12

VCC1_5A U13

VCC1_5B L17

VCC1_5B L18

VCC1_5B M17

VCC1_5B N17

VCC1_5B P17

VCC1_5B R17

VCC1_5B R18

VCC3_3 A18

VCC3_3 A2

VCC3_3 AA13

VCC3_3 B7

VCC3_3 C11

VCC3_3 D10

VCC3_3 D15

VCC3_3 H21

VCC3_3 P6

VCC3_3 R5

VCC3_3 U15

VCC3_3 V11

VCC3_3 V13

VCC3_3 Y17

VCC3_3 Y9

VCCAUSBPLL E5

VCCDMIPLL U18

VCCHDA N4

VCCRTC T6

VCCSUS1_05 D3

VCCSUS1_05 G20

VCCSUS3_3 E2

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 787

Ballout Definition

VCCSUS3_3 H15

VCCSUS3_3 L6

VCCSUS3_3 M8

VCCSUS3_3 N8

VCCSUS3_3 N9

VCCSUS3_3 P8

VCCSUS3_3 P9

VCCSUS3_3 R8

VCCSUS3_3 R9

VCCSUSHDA M4

VRMPWRGD AB22

VSS A1

VSS A13

VSS A22

VSS AA12

VSS AA14

VSS AA16

VSS AA18

VSS AA21

VSS AA6

VSS AA9

VSS AB1

VSS B11

VSS B15

VSS B18

VSS B21

VSS B4

VSS B6

VSS B8

VSS C10

VSS C20

VSS D13

VSS D16

VSS D2

VSS E1

VSS E19

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

VSS E22

VSS E4

VSS E6

VSS E8

VSS F11

VSS F14

VSS G1

VSS G21

VSS G4

VSS H10

VSS H12

VSS H18

VSS H20

VSS H22

VSS H3

VSS H6

VSS J1

VSS J10

VSS J12

VSS J13

VSS J14

VSS J15

VSS J18

VSS J21

VSS J22

VSS J4

VSS K10

VSS K11

VSS K12

VSS K13

VSS K17

VSS K18

VSS K19

VSS K20

VSS K3

VSS K6

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

VSS K9

VSS L10

VSS L11

VSS L12

VSS L13

VSS L14

VSS L21

VSS L22

VSS L8

VSS L9

VSS M10

VSS M11

VSS M12

VSS M13

VSS M18

VSS M19

VSS M20

VSS M9

VSS N10

VSS N11

VSS N12

VSS N13

VSS N14

VSS N18

VSS N21

VSS N22

VSS N3

VSS N5

VSS P10

VSS P12

VSS P14

VSS P18

VSS P19

VSS P20

VSS R10

VSS R21

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

788 Intel ® ICH7 Family Datasheet

Ballout Definition

VSS R22

VSS R6

VSS T16

VSS T17

VSS T18

VSS T19

VSS T20

VSS T4

VSS U11

VSS U14

VSS U19

VSS U21

VSS U22

VSS U8

VSS V10

VSS V12

VSS V14

VSS V18

VSS W17

VSS W2

VSS W8

VSS Y18

WAKE# E21

Table 22-2. Intel®

ICH7-U Ballout by

Signal Name

Signal Name Ball #

Intel ® ICH7 Family Datasheet 789

Electrical Characteristics

23 Electrical Characteristics

This chapter contains the DC and AC characteristics for the ICH7. AC timing diagrams

are included.

23.1 Thermal Specifications

Refer to the Intel® I/O Controller Hub (ICH7) Thermal Design Guidelines for ICH7

thermal information.

23.2 Absolute Maximum Ratings

Table 23-1. Intel® ICH7 Absolute Maximum Ratings

Parameter Maximum Limits

Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.5 V

Voltage on any 5 V Tolerant Pin with respect to Ground

(V5REF=5 V) -0.5 to V5REF + 0.5 V

1.05 V Supply Voltage with respect to VSS -0.5 to 2.1 V

1.5 V Supply Voltage with respect to VSS -0.5 to 2.1 V

3.3 V Supply Voltage with respect to VSS -0.5 to 4.6 V

5.0 V Supply Voltage with respect to VSS -0.5 to 5.5 V

V_CPU_IO Supply Voltage with respect to VSS -0.5 to 2.1 V

Electrical Characteristics

790 Intel ® ICH7 Family Datasheet

23.3 DC Characteristics

Table 23-2. DC Current Characteristics

Power Plane Maximum Power Consumption

Symbol S0 S3COLD S4/S5 G3

Vcc1_05 0.86 A NA NA NA

VccSus1_05 See Note 1NA NA NA

Vcc1_5_A1

NOTES:

1. Due to the integrated 1.05 V voltage regulator on the ICH7, VccSus1_05 is included in the

Vcc1_05 rail during the S0–S1 states and in the VccSus3_3 rail during the S3–S5 states.

1.01 A NA NA NA

Vcc1_5_B10.77 A NA NA NA

Vcc3_3 0.33 A NA NA NA

VccSus3_31,2

2. VccSus3_3 assumes that the 8 high-speed USB 2.0 devices are connected to the ICH7’s root

ports.

52 mA 30 mA 30 mA NA

VccRTC3

3. Icc (RTC) data is estimated with VccRTC at 3.0 V while the system is in a mechanical off (G3)

state at room temperature. Only the G3 state of this rail is shown to provide an estimate of

battery life.

NA NA NA 6 uA

V5REF 6 mA NA NA NA

V5REF_Sus 10 mA 10 mA 10 mA NA

V_CPU_IO 14 mA NA NA NA

VccUSBPLL 10 mA NA NA NA

VccDMIPLL 50 mA NA NA NA

VccSATAPLL 50 mA NA NA NA

Intel ® ICH7 Family Datasheet 791

Electrical Characteristics

Table 23-3. DC Current Characteristics (Mobile/Ultra Mobile Only)

Power Plane Maxi m u m Powe r Consum pt ion

Symbol S0 S3COLD S4/S5 G3

Vcc1_051,2

NOTES:

1. When the internal VccSus1_05 voltage regulator on the ICH7-M/ICH7-U is enabled,

VccSus1_05 is included in the Vcc1_05 rail during the S0 state and in the VccSus3_3 rail

during the S3 - S5 states . Th ere is a n egligible change in Vcc1_05 and VccSus3_3 maximum

power consumption when internal VccSus1_05 VR is disabled.

2. When the internal VccSus1_05 voltage regulator on the ICH7-M/ICH7-U is enabled,

VccLAN1_05 is included in the Vcc1_05 rail during the S0 state and in the VccLAN3_3 rail

during the S3 - S5 states. There is a negligible change in Vcc1_05 and VccLAN3_3 maximum

power consumption when internal VccSus1_05 VR is disabled.

0.94 ANANANA

VccSus1_053

3. Integrated VccSus1_05 VR disabled.

17 mA 17 mA 17 mA NA

VccLAN1_05330 mA 3 mA 3 mA NA

Vcc1_5_A 0.64 A NA NA NA

Vcc1_5_B 0.77 A NA NA NA

Vcc3_3 0.27 A NA NA NA

VccHDA4

4. VccHDA and VccSusHDA at 3.3 V.

56 mA NA NA NA

VccHDA5

5. VccHDA and VccSusHDA at 1.5 V.

92 mA NA NA NA

VccSus3_31,6

6. VccSus3_3 assumes that the 8 high-speed USB 2.0 devices are connected to the ICH7’s root

ports.

45 mA 21 mA 21 mA NA

VccSusHDA410 mA 2 mA 2 mA NA

VccSusHDA517 mA 2 mA 2 mA NA

VccLAN3_3240 mA 7 mA 7 mA NA

VccRTC7

7. Icc (RTC) data is estimated with VccRTC at 3.0 V while the system is in a mechanical off (G3)

state at room temperature. Only the G3 state of this rail is shown to provide an estimate of

battery life.

NA NA NA 6 uA

V5REF 6 mA NA NA NA

V5REF_Sus 10 mA 10 mA 10 mA NA

V_CPU_IO 14 mA NA NA NA

VccUSBPLL 10 mA NA NA NA

VccDMIPLL 50 mA NA NA NA

VccSATAPLL 50 mA NA NA NA

Electrical Characteristics

792 Intel ® ICH7 Family Datasheet

Table 23-4. DC Characteristic Input Signal Association (Sheet 1 of 2)

Symbol Associated Signals

VIH1/VIL1

(5V Tolerant)

PCI Signals: AD[31:0], C/BE[3:0 ]#, DEVSEL#, FRAME#, IRDY#, PAR,

PERR#, PLOCK#, REQ[3:0]#, REQ4#/GPIO22, REQ5#/GPIO1, SERR#,

STOP#, TRDY#

Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]#/GPIO[5 :2]

VIH2/VIL2

(5V Tolerant) Interrupt Signals: IDEIRQ

VIH3/VIL3

Clock Signals: CLK14, CLK48

Power Management Signals: MCH_SYNC#, THRM#, VRMPWRG D

SATA Signals:

Desktop Only: SATAGP[3:0]/GPIO[37,36,19,21], SATACLKREQ#/GPIO35

Mobile Only: SATAGP[2,0]/GPIO[36,21], SATACLKREQ#/GPIO35

AC ’97/Intel® High De f inition Audio Signals:

Mobile Only: AZ_DOCK_EN#/GPIO33

GPIO Signals:

Desktop Only: GPIO[39, 38, 33, 32, 20, 18, 16, 7, 6]

Mobile/Ultra Mobile Only: GPIO[39:37, 19, 7, 6]

Strap Signals: SPKR, SATALED# (Strap purposes only)

VIH4/VIL4

Clock Signals: PCICL K

LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LDRQ0#, LDRQ1#/

GPIO23

Power Management Signals:

Desktop Only: LAN_RST#

Mobile/Ultra Mobile Only: BM_BUSY#/GPIO0, CLKRUN#, LAN_RST#

PCI Signals: PME#

Interrupt Signals: SERIRQ

CPU Signals: A20GATE, RCIN#

USB Signals: OC[4:0]#, OC[7:5]#/GPIO[31:29]

GPIO Signals: GNT4#/GPIO48, GNT5#/GPIO17, GPIO0

SPI Signals:

Desktop and Mobile Only: SPI_CS#, SPI_MISO, SPI_ARB

VIH5/VIL5

SMBus Signals: SMB CLK, SMBDATA

System Management Signals: SMBALERT#/GPIO11

Desktop and Mobile Only: SMLINK[1:0]

VIH6/VIL6

LAN Signals: LAN_CLK, LAN_RXD[2:0]

EEPROM Signals: EE_DIN

Strap Signals: EE_CS, EE_DOUT (Strap purposes only)

VIH7/VIL7 Processor Signals: FERR#, THRMTRIP#

GPIO Signals: GPIO49/CPUPWRGD

VIMIN8/VIMAX8 PCI Express* Data RX Signals: PER[p,n][6:1] (Desktop and Mobile Onl y)

VIH9/VIL9 Real Time Clock Signals: RTCX1

VIMIN10/VIMAX10

SATA Signals:

Desktop Only: SATA[3:0]RX[P,N]

Mobile Only: SATA[2,0]RX[P,N]

Intel ® ICH7 Family Datasheet 793

Electrical Characteristics

VIH11/VIL11

AC ’97/Intel® High Definition Audio Signals: ACZ_SDIN[2:0],

Mobile Only: AZ_DOCK_RST#/GPIO34

AC ‘97 Signals: ACZ_BIT_CLK

Strap Signals: ACZ_SDOUT, ACZ_SYNC (Strap purposes only)

GPIO Signals: GPIO34 (Desktop Only)

NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode

(Mobile/Ultra Mobile Only)

VIH12/VIL12/

Vcross(abs) Clock Signals: DMI_CLKN, DMI_CLKP, SATA_CLKN, SATA_CLKP

VIH13/VIL13

Power Management Signals:

Desktop Only: PWRBTN#, RI#, SYS_RESET#, WAKE#

Mobile/Ultra Mobile Only: BATLOW#, PWRBTN#, RI#, SYS_RESET#,

WAKE#

System Management Signal: LINKALERT#

Intel® Quick Resume Technology Signals: EL_STATE[1:0]/GPIO[28:27],

EL_RSVD/GPIO26 (ICH7DH Only)

GPIO Signals: GPIO[ 28:26, 25:24, 15:12, 10:8]

Other Signals: TP0

VIH14/VIL14 Power Management Signals: PWROK, RSMRST#, RTCRST#

System Management Signals: INTRUDER#

VIH15/VIL15 Other Signals: INTV RMEN (Desktop and Mobile Only)

V+/V-/VHYS/

VTHRAVG/VRING

(5V Tolerant)

IDE Signals: DD[15:0], DDREQ, IORDY,

For Ultra DMA Mode 4 and lower these signals follow the DC characteristics

for VIH2/VIL2

VDI / VCM / VSE

(5V Tolerant) USB Signals: USBP[7:0][P,N] (Low-speed and Full-speed)

VHSSQ / VHSDSC /

VHSCM

(5V Tolerant) USB Signals: USBP[7:0][P,N] (in High-speed Mode)

VIH_HDA / VIL_HDA

(Mobile/Ultra

Mobile Only)

Intel® High Definition Audio Signals: ACZ_SDIN[2:0],

AZ_DOCK_RST#/GPIO34

NOTE: Only applies when running in Low Vo ltage Mode (1.5 V)

Table 23-4. DC Characteristic Input Signal Association (Sheet 2 of 2)

Symbol Associated Signals

Electrical Characteristics

794 Intel ® ICH7 Family Datasheet

Table 23-5. DC Input Characteristics (Sheet 1 of 2)

Symbol Parameter Min Max Unit Notes

VIL1 Input Low Voltage –0.5 0.3(Vcc3_3) V

VIH1 Input High Voltage 0.5(Vcc3_3) V5REF + 0.5 V

VIL2 Input Low Voltage -0.5 0 .8 V

VIH2 Input High Voltage 2.0 V5REF + 0.5 V

VIL3 Input Low Voltage –0.5 0.8 V

VIH3 Input High Voltage 2.0 Vcc3_3 + 0.5 V

VIL4 Input Low Voltage –0.5 0.3(Vcc3_3) V

VIH4 Input High Voltage 0.5(Vcc3_3) Vcc3_3 + 0.5 V

VIL5 Input Low Voltage –0.5 0.8 V

VIH5 Input High Voltage 2.1 VccSus3_3 + 0.5 V

VIL6 Input Low Voltage -0.5 0.3(Vcc3_3) V

VIH6 Input High Voltage 0.6(Vcc3_3) Vcc3_3 + 0.5 V

VIL7 Input Low Voltage –0.5 0.58(V_CPU_IO) V

VIH7 Input High Voltage 0.73(V_CPU_IO) V_CPU_IO + 0.5 V

VIMIN8 Minimum Input

Voltage 175 mVdiff

p-p 1

VIMAX8 Maximum Input

Voltage 1200 mVdiff

p-p 1

VIL9 Input Low Voltage –0.5 0.10 V

VIH9 Input High Voltage 0.40 1 .2 V

VIMIN10 Minimum Input

Voltage 325 mVdiff

p-p 2

VIMAX10 Maximum Input

Voltage 600 mVdiff

p-p 2

VIMIN10 Minimum Input

Voltage 275 mVdiff

p-p 3

VIMAX10 Maximum Input

Voltage 750 mVdiff

p-p 3

VIL11 Input Low Voltage –0.5 0.35(Vcc3_3) V

VIH11 Input High Voltage 0.65(Vcc3_3) Vcc3_3 + 0.5 V

VIL12 Input Low Voltage -0.150 0.150 V

VIH12 Input High Voltage 0.660 0.850 V

VIL13 Input Low Voltage –0.5 0.8 V

VIH13 Input High Voltage 2.0 VccSus3_3 + 0.5 V

VIL14 Input Low Voltage –0.5 0.78 V

VIH14 Input High Voltage 2.0 VccRTC + 0.5 V 4

VIL15 Input Low Voltage –0.5 0.65 V

VIH15 Input High Voltage 2.0 VccRTC + 0.5 V 4

Vcross(abs) Absolute Crossing

Point 0.250 0.550 V

V+ Low to high input

threshold 1.5 2.0 V 5

Intel ® ICH7 Family Datasheet 795

Electrical Characteristics

V–High to low input

threshold 1.0 1.5 V 5

VHYS

Difference between

input thresholds:

(V+current value) –

(V– current value)

320 mV 5

VTHRAVG

Average of

thresholds:

((V+current value)

+ (V– current

value))/2

1.3 1.7 V 5

VRING AC Voltage at

recipient connector –1 6 V 5,6

VDI Differential Input

Sensitivity 0.2 V 7,8

VCM

Differential

Common Mode

Range 0.8 2.5 V 8,9

VSE Single-Ended

Receiver Threshold 0.8 2.0 V 8

VHSSQ HS Squelch

Detection Threshold 100 150 mV 8

VHSDSC HS Disconnect

Detection Threshold 525 625 mV 8

VHSCM

HS Data Signaling

Common Mode

Voltage Range –50 500 mV 8

VHSSQ HS Squelch

detection threshold 100 150 mV 8

VHSDSC HS disconnect

detection threshold 525 625 mV 8

VHSCM

HS data signaling

common mode

voltage range –50 500 mV 8

VIL_HDA

(Mobile/

Ultra

Mobile

Only)

Input Low Voltage 0.4(Vcc_HDA) V

VIH_HDA

(Mobile/

Ultra

Mobile

Only)

Input High Voltage 0.6(Vcc_HDA) V

NOTES:

1. PCI Express mVdiff p-p = |PETp[x] – PETn[x]|

2. Applicable only when SATA port signaling rate is 1.5 Gb/s: SATA Vdiff, tx (VIMAX/MIN10) is measured at the

SATA connector on the transmit side (generally, the motherboard connector), where

SATA mVdiff p-p = |SATA[x]TXP/RXP – SATA[x]TXN/RXN|

Table 23-5. DC Input Characteristics (Sheet 2 of 2)

Symbol Parameter Min Max Unit Notes

Electrical Characteristics

796 Intel ® ICH7 Family Datasheet

3. Applicable only when SATA port signaling rate is 3 Gb/s: SAT A Vdiff , tx (VIMAX/MIN10) is measured at the SAT A

connector on the transmit side (generally, the motherboard connector), where

SATA mVdiff p-p = |SATA[x]TXP/RXP – SATA[x]TXN/RXN|

4. VccRT C is the voltage applied to the VccRT C well of the ICH7. When the system is in a G3 state, this is generally

supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3.

5. Applies to Ultra DMA Modes greater than Ultra DMA Mode 4

6. This is an AC Characteristic that represents transient values for these signals

7. VDI = | USBPx[P] – USBPx[N]

8. Applies to High-speed US B 2.0

9. Includes VDI range

Table 23-6. DC Characteristic Output Signal Association (Sheet 1 of 2)

Symbol Associated Signals

VOH1/VOL1 IDE Signals: DA[2:0], DCS[3,1]#, DDACK#, DD[15:0], DIOR#, DIOW#

VOH2/VOL2

Processor Signals:

Desktop Only: A20M#, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#,

STPCLK#, CPUPWRGD/G PIO49

Mobile/Ultra Mobile Only: A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#,

INTR, NMI, SMI#, STPCLK#, CPUPWRGD/GPIO49

VOH3/VOL3

PCI Signals: AD[31:0], C/BE[3:0 ]#, DEVSEL#, FRAME#, IRDY#, PAR,

PERR#, PLOCK#, SERR#, STOP#, TRDY#

AC ’97/Intel® High Definition Audio Signals: ACZ_RST#, ACZ_SDOUT,

ACZ_SYNC

Intel High Definition Audio Signals: ACZ_BIT_CLK

NOTE: See VOH_HDA/VOL_HDA for High Definition Audio Low Voltage Mode

(Mobile/Ultra Mobile Only)

VOH4/VOL4

SMBus Signals: SMBCLK1, SMBDATA1

System Management Signals: SMLINK[1:0]1

GPIO Signals: GPIO11/SMBALERT1

VOH5/VOL5

Power Management Signals:

Desktop Only: PLTRST#, SLP_S3#, SLP_S4#, SLP_S5#, SUSCLK#,

SUS_STAT

Mobile/Ultra Mobile Only: DPRSLPVR, PLTRST#, SLP_S3#, SLP_S4#,

SLP_S5#, STP_CPU#, STP_PCI#, SUSCLK#, SUS_STAT

GPIO Signals:

Desktop Only: GPIO[39, 38, 33, 32, 20, 18, 16, 7, 6], GPIO[37,36,19,21]/

SATAGP[3:0]#,

Mobile/Ultra Mobile Only: GPIO[39:37,19, 7, 6], GPIO[36,21]/

SA TAGP[2,0]#

Intel High Definition Audio Signals: AZ_DOCK_EN#/GPIO33 (Mobile

Only)

Other Signals: SPKR

SATA Signal: SATALE D#, SATA CLKREQ#/GPIO35

EEPROM Signals: EE_CS, EE_DOUT, EE_SHCLK

VOH6/VOL6 USB Signals: USBP[7:0][P,N] in Low-speed and Full-speed Modes

VOMIN7/VOMAX7 PCI Express* Data TX Signals: PET[p,n][4:1] on ICH7 and PET[p,n][6:1]

on ICH7R and ICH7DH and Mobile

VOMIN8/VOMAX8

SATA Signals:

Desktop Only: SATA[3:0]TX[P,N]

Mobile Only: SATA[2,0]TX[P,N]

Intel ® ICH7 Family Datasheet 797

Electrical Characteristics

VOH9/VOL9

LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4]

PCI Signals: PCIRST#, GNT[3:0]#, GNT4/GPIO48, GNT5/GPIO17

GPIO Signals:

Desktop Only: GPIO[34, 0], GPIO23/LDRQ1#, GPIO22/REQ4#, GPIO[5:2]/

PIRQ[H:E]#, GPIO1/REQ5#

Mobile/Ultra Mobile Only: GPIO23/LDRQ1#, GPIO22/REQ4#, GPIO[5:2]/

PIRQ[H:E]#, GPIO1/REQ5#, GPIO0/BM_BUSY#

Intel High Definition Audio Signals: AZ_DOCK_RST#/GPIO34 (Mobile

Only)

Interrupt Signals: SERIRQ

SPI Signals:

Desktop and Mobile Only: SPI_CS#, SPI_MOSI, SPI_CLK

Processor Interface Signal: INIT3_3V#

LAN Signals: LAN_RSTSYNC, LAN_TXD[2:0]

VOH10/VOL10

GPIO Signals: GPIO[28:26, 25:24, 15:12, 10:8], GPIO[31:29]/OC[7:5]#

Intel Quick Resume Technology Signals: EL_STATE[1:0]/GPIO[28:27],

EL_RSVD/GPIO26 (ICH7DH Only)

VHSOI

VHSOH

VHSOL

VCHIRPJ

VCHIRPK

USB Signals: USBP[7:0][P:N ] i n High-speed Mode

VOH_HDA/VOL_HDA

(Mobile/Ultra

Mobile Only)

Intel® High Definition Audio Signals: ACZ_RST#, ACZ_SDOUT, ACZ_SYNC

NOTE: Only applies when running in Low Vo ltage Mode (1.5 V)

NOTES:

1. These signals are open drain.

Table 23-6. DC Characteristic Output Signal Association (Sheet 2 of 2)

Symbol Associated Signals

Electrical Characteristics

798 Intel ® ICH7 Family Datasheet

Table 23-7. DC Output Characteristics

Symbol Parameter Min Max Unit IOL / IOH Notes

VOL1 Output Low Voltage 0.51 V 6 mA

VOH1 Output High Voltage Vcc3_3 – 0.51 V -6 mA

VOL2 Output Low Voltage 0.255 V 3 mA 1

VOH2 Output High Voltage V_CPU_IO –

0.3 V-3 mA

VOL3 Output Low Voltage 0.1(Vcc3_3) V 1.5 mA

VOH3 Output High Voltage 0.9(Vcc3_3) V -0.5 mA 2

VOL4 Output Low Voltage 0.4 V 4 mA

VOH4 Output High Voltage VccSus3_3 –

0.5 V-2 mA 2

VOL5 Output Low Voltage 0.4 V 6 mA

VOH5 Output High Voltage Vcc3_3 – 0.5 V -2 mA

VOL6 Output Low Voltage 0.4 V 5 mA

VOH6 Output High Voltage Vcc 3_3 – 0.5 V -2 mA

VOMIN7 Minimum Output

Voltage 800 mVdif

fp-p 3

VOMAX7 Maximum Output

Voltage 1200 mVdif

fp-p 3

VOMIN8 Minimum Output

Voltage 400 mVdif

fp-p 4

VOMAX8 Maximum Output

Voltage 600 mVdif

fp-p 4

VOMIN8 Minimum Output

Voltage 400 mVdif

fp-p 5

VOMAX8 Maximum Output

Voltage 700 mVdif

fp-p 5

VOL9 Output Low Voltage 0.1(Vcc3_3) V 1.5 mA

VOH9 Output High Voltage 0.9(Vcc3_3) V -0.5 mA 2

VOL10 Output Low Voltage 0.4 V 6 mA

VOH10 Output High Voltage VccSus3_3 –

0.5 V-0.5 mA

VHSOI HS Idle Level –10.0 10.0 mV

VHSOH HS Data Signaling High 360 440 mV

VHSOL HS Data Signaling Low –10.0 10.0 mV

VCHIRPJ Chirp J Level 700 1100 mV

VCHIRPK Chirp K Level –900 –500 mV

VOL_HDA

(Mobile/

Ultra

Mobile

Only)

Output Low Voltage 0.1(VccHDA) V 1.5 mA

VOH_HDA

(Mobile/

Ultra

Mobile

Only)

Output High Voltage 0 .9(Vcc_HDA) V -0.5 mA

NOTES:

1. Maximum Iol for CPUPWRGD is 12 mA for short durations (<500 mS per 1.5 s) and 9 mA for long durations.

2. The SERR#, PIRQ[H:A], GPIO11, SMBDA TA, SMBCLK, LINK ALER T#, and SMLINK[1: 0] signal has an o pen drain

driver and SATALED# has an open collector driver, and the VOH spec does not apply. This signal must have an

external pull-up resistor.

3. PCI Express mVdiff p-p = |PETp[x] – PETn[x]|

Intel ® ICH7 Family Datasheet 799

Electrical Characteristics

4. Applicable only when SATA port si gnaling rate is 1.5 Gb/s: SAT A Vdiff, TX (VOMAX/MIN8) is measured at the SAT A

connector on th e transmit side closest to the ICH7 (generally, the moth erboard connector), whe re SATA mV diff

p-p = |SATAxTXP – SATAxTXN|.

5. Applicable only when SATA port signaling rate is 3 Gb/s: SATA Vdiff, TX (VOMAX/MIN8) is measured at the SATA

connector on th e transmit side closest to the ICH7 (generally, the moth erboard connector), whe re SATA mV diff

p-p = |SATAxTXP – SATAxTXN|.

Table 23-8. Other DC Characteristics

Symbol Parameter Min Max Unit Notes

V5REF Intel® ICH7 Core Well

Reference Voltage 4.75 5.25 V 1

Vcc3_3 I/O Buffer Voltage 3.135 3.465 V 1

Vcc1_5_A,

Vcc1_5_B,

VccUSBPLL,

VccSATAPLL,

VccDMIPLL

Internal Logic and I/O Buffer

Voltage 1.425 1.575 V 1

V_CPU_IO Processor Interface 0.945 1.25 V 1, 2

V5REF_Sus Suspend W e ll Reference

Voltage 4.75 5.25 V 1

VccSus3_3 Suspend Well I/O Buffer

Voltage 3.135 3.465 V 1

Vcc1_05 Internal Logic Voltage 0.998 1.102 V 1

VccSus1_05 Suspend Well Logic Voltage 0.998 1.102 V 1

VccLAN3_3

(Mobile Only) LAN Controller I/O Buffer

Voltage 3.135 3.465 V

VccLAN1_05

(Mobile Only) LAN Controller Logic Voltage 0.998 1.102 V

VccSusHDA

(Mobile/Ultra

Mobile Only)

High Definition Audio

Controller Low Voltage Mode

Suspend Voltage 1.425 1.575 V Same as

VccSus3_3 if not in

low voltage mode

VccHDA

(Mobile/Ultra

Mobile Only)

High Definition Audio

Controller Low Voltage Mode

Core Voltage 1.425 1.575 V Same as Vcc3_3 if

not in low voltage

mode

VccR TC Battery Voltage 2.0 3.6 V 1

VDI Differential Input Sensitivi t y 0.2 V |(USBPx+,USBPx-

VCM Differential Common Mode

Range 0.8 2.5 V Includ es VDI

VCRS Output Signal Crossover

Voltage 1.3 2.0 V

VSE Single Ended Rcvr Threshold 0.8 2.0 V

ILI1 ATA Input Leakage Current –200 200 µA (0 V < VIN < 5 V)

ILI2 PCI_3V Hi-Z State Data Line

Leakage –10 10 µA (0 V < VIN < 3.3 V)

ILI3 PCI_5V Hi-Z State Data Line

Leakage –70 70 µA Max VIN = 2.7 V

Min VIN = 0.5 V

ILI4 Input Leakage Current – Clock

signals –100 +100 µA 3

Electrical Characteristics

800 Intel ® ICH7 Family Datasheet

CIN Input Capacitance – All Other 12 pF FC = 1 MHz

COUT Output Capacitance 12 pF FC = 1 MHz

CI/O I/O Capacitance 12 pF FC = 1 MHz

Typical Value

CLXTAL1 6 pF

CLXTAL2 6 pF

NOTES:

1. For all noise components ≤20 MHz, the sum of the DC voltage and the AC noise co mponent must be within the

specifie d DC min/max operating r ange on the ICH7 supply voltages.

2. Th e tolerances shown in Table 23-8 are inclusive of all noise from DC up to 20 MHz. In testing, the voltage

rails should be measured with a bandwidth limited oscillos cope that has a rolloff of 3 dB/decade above 20 MHz.

3. Includes CLK14, CLK48, LAN_CLK, and PCICLK.

Table 23-8. Other DC Characteristics

Symbol Parameter Min Max Unit Notes

Intel ® ICH7 Family Datasheet 801

Electrical Characteristics

23.4 AC Characteristics

Table 23-9. Clock Timings (Sheet 1 of 2)

Sym Parameter Min Max Unit Notes Figur

PCI Clock (PCICLK)

t1 Period 30 33.3 ns 23-1

t2 High Time 11 ns 23-1

t3 Low Time 11 ns 23-1

t4 Rise Time 1 4 V/ns 23-1

t5 Fall Time 1 4 V/ns 23-1

14 MHz Clock (CLK14)

t6 Period 67 70 ns 23-1

t7 High Time 20 ns 23-1

t8 Low Time 20 ns 23-1

t41 Rising Edge Rate 1.0 4.0 V/ns 1

t42 Falling Edge R ate 1.0 4.0 V/ns 1

48 MHz Clock (CLK48)

fclk48 Operating Frequency 48.00

0MHz 2

t9 Frequency Tolerance 100 ppm

t10 High Time 7 ns 23-1

t11 Low Time 7 ns 23-1

t12 Rise Time 1.2 ns 23-1

t13 Fall Time 1.2 ns 23-1

SMBus Clock (SMBCLK)

fsmb Operating Frequency 10 16 KHz

t18 High time 4.0 50 us 323-16

t19 Low time 4.7 us 23-16

t20 Rise time 1000 ns 23-16

t21 Fall time 300 ns 23-16

Electrical Characteristics

802 Intel ® ICH7 Family Datasheet

AC ’97 Clock (ACZ_BIT_CLK - AC ‘97 mode) (Desktop and Mobile Only)

fac97 Operating Frequency 12.288 MHz

t26 Input Jitter (refer to Clock Chip

Specification) —2ns

t27 High time 36 45 ns 23-1

t28 Low time 36 45 ns 23-1

t29 Rise ti me 2.0 6.0 ns 523-1

t30 Fall time 2.0 6.0 ns 523-1

ACZ_BIT_CLK (Intel®High Definition Audio Mode)

fHDA Operating Frequency 24.0 MHz

Frequency Tolerance — 100 ppm

t26a Input Jitter (refer to Clock Chip

Specification) — 300 ppm

t27a High Time (Measured at 0.75Vcc) 18.75 22.91 ns 23-1

t28a Low Time (Measured at 0.35Vcc) 18.75 22.91 ns 23-1

SATA Clock (SATA_CLKP, SATA_CLKN) /DMIClock(DMI_CLKP,DMI_CLKN)

(Desktop and Mobile Only)

t36 Period 9.997 10.053

3ns

t37 Rise time 175 700 ps

t38 Fall time 175 700 ps

Suspend Clock (SUSCLK)

fsuscl

kOperating Frequency 32 kHz 6

t39 High Time 10 — us 6

t39a Low Time 10 — us 6

NOTES:

1. CLK14 edge rates in a system as measured from 0.8 V to 2.0 V.

2. The CLK48 expects a 40/60% duty cycle.

3. The maximum high time (t18 Max) provides a simple method for devices to detect bus idle conditions.

4. The ICH7 can tolerate a maximum of 2 ns of jitter from the input BITCLK. Note that clock jitter may impact

system timing. Contact your Intel representative for further details and documentation.

5. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.

6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.

Table 23-9. Clock Timings (Sheet 2 of 2)

Sym Parameter Min Max Unit Notes Figur

Intel ® ICH7 Family Datasheet 803

Electrical Characteristics

Table 23-10. PCI Interface Timing

Sym Parameter Min Max Units Notes Figure

t40 AD[31:0] Valid Delay 2 11 ns 123-2

t41 AD[31:0] Setup Time to PCICLK Rising 7 — ns 23-3

t42 AD[31:0] Hold Time from PCICLK Rising 0 — ns 23-3

t43 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from

PCICLK Rising 211ns 123-2

t44 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output

Enable Delay from PCICLK Rising 2—ns 23-6

t45 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PERR#, PLOCK #, DEVSEL#, GNT[A:B]# Float

Delay from PCICLK Rising 228ns 23-4

t46 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, Setup Time to PCICLK

Rising 7—ns 23-3

t47 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time

from PCLKIN Rising 0—ns 23-3

t48 PCIRST# Low Pulse Width 1 — ms 23-5

t49 GNT[5:0]# Valid Delay from PCICLK Rising

NOTE: GNT[2:0]# not on Ultra Mobile. 212ns

t50 REQ[5:0]# Setup Time to PCICLK Rising

NOTE: REQ[2:0]# not on Ultra Mobile. 12 — ns

NOTES:

1. Refer to note 3 of table 4-4 in Section 4.2.2.2 and note 2 of table 4-6 in Section 4.2.3.2 of the PCI Local Bus

Specification, Revision 2.3 for measurement details.

Electrical Characteristics

804 Intel ® ICH7 Family Datasheet

Table 23-11. IDE PIO Mode Timings

Sym Parameter Mode 0

(nS) Mode 1

(nS) Mode 2

(nS) Mode 3

(nS) Mode 4

(nS) Figure

t60 Cycle Time (min) 600 383 240 180 120 23-7

t61 Addr setup to DIOW#/

DIOR# (min) 70 50 30 30 25 23-7

t62 DIRW#/DIOR# (min) 165 125 100 80 70 23-7

t62i DIOW#/DIOR# recovery

time (min) ———702523-7

t63DIOW# data setup (min)604530302023-7

t64DIOW# data hold (min)302015101023-7

t65DIOR# data setup (min)503520202023-7

t66DIOR# data hold (min)5555523-7

t66zDIOR# data tristate (max)303030303023-7

t69 DIOW#/DIOR# to address

valid hold (min) 20 15 10 10 10 23-7

t60rd Read data Valid to IORDY

active (min) 0000023-7

t60aIORDY Setup 353535353523-7

t60b IORDY Pulse Width (max) 1250 1250 1250 1250 1250 23-7

t60c IORDY assertion to release

(max) 5555523-7

Table 23-12. IDE Multiword DMA Timings

Sym Parameter Mode 0

(nS) Mode 1

(nS) Mode 2

(nS) Figure

t70 Cycle Time (min) 480 150 120 23-8

t70d DIOR#/DIOW# (min) 215 80 70 23-8

t70e DIOR# Data access (max) 150 60 50 23-8

t70f DIOR# Data hold (min) 5 5 5 23-8

t70g DIOR#/DIOW# Data setup (min) 100 30 20 23-8

t70h DIOW# Data hold (min) 20 15 10 23-8

t70i DDACK# to DIOR#/DIOW# setup (min) 0 0 0 23-8

t70j DIOR#/DIOW# to DDACK# hold (min) 20 5 5 23-8

t70kr DIOR# negated pulse width (min) 50 50 25 23-8

t70kw DIOW# negated pulse width (min) 215 50 25 23-8

t70lr DIOR# to DDREQ delay (max) 120 40 35 23-8

t70lw DIOW# to DDREQ delay (max) 40 40 35 23-8

t70m DCS1#/DCS3# valid to DIOR#/DIOW#

(min) 50 30 25 23-8

t70n DCS1#/DCS3# hold (min) 15 10 10 23-8

t70z DDACK# to tristate (max) 20 25 25 23-8

Intel ® ICH7 Family Datasheet 805

Electrical Characteristics

Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)

Sym Parameter1Mode 0

(ns) Mode 1

(ns) Mode 2

(ns) Measuring

Location Figure

Min Max Min Max Min Max

t80 Sustained Cycle Time

(T2cyctyp) 240 160 120 Sender

Connector

t81 Cycle Time (Tcyc) 112 — 73 — 54 — End

Recipient

Connector 23-10

t82 Two Cycle Time (T2cyc) 230 — 153 — 115 — Sender

Connector 23-10

t83a Data Setup Time (Tds) 15 — 10 — 7 — Recipient

Connector 23-10

t83b Recipient IC data setup time

(from data valid until STROBE

edge) (see Note 2) (Tdsic)

14.

7— 9.7 — 6.8 — Intel® ICH7

ball

t84a Data Hold Time (Tdh) 5 — 5 — 5 — Recipient

Connector 23-10

t84b

Recipient IC data hold time

(from STROBE edge until data

may become invalid) (see

Note 2) (Tdhic)

4.8 — 4.8 — 4.8 — ICH7 ball

t85a Data Valid Setup Time (Tdvs) 70 — 48 — 31 — Sender

Connector 23-10

t85b

Sender IC data valid setup

time (from data valid until

STROBE edge) (see Note 2)

(Tdvsic)

72.

9—50.

9—33.

9— ICH7 ball

t86a Data Valid Hold Time (Tdvh) 6.2 — 6.2 — 6.2 — Sender

Connector 23-10

t86b

Sender IC data valid hold time

(from STROBE edge until data

may become invalid) (see

Note 2) (Tdv hic)

9—9—9—ICH7 ball

t87 Limited Interlock Time (Tli) 0 150 0 150 0 150 See Note 2 23-12

t88 Interlock Time w/ Minimum

(Tmli) 20 — 20 — 20 — Host

Connector 23-12

t89 Envelope Time (Tenv) 20 70 20 70 20 70 Host

Connector 23-9

t90 Ready to Pause Time (Trp) 160 — 125 — 100 — Recipient

Connector 23-11

t91 DMACK setup/hold Time

(Tack) 20 — 20 — 20 — Host

Connector 23-9,

23-12

t92a CRC W or d Setup Time at Host

(Tcvs) 70 — 48 — 31 — Host

Connector

Electrical Characteristics

806 Intel ® ICH7 Family Datasheet

t92b

CRC word valid hold time at

sender (from DMACK#

negation until CRC may

become invalid) (see Note 2)

(Tcvh)

6.2 — 6.2 — 6.2 — Host

Connector

t93 STROBE output released-to-

driving to the first transition of

critical t iming (Tzfs) 0—0—0— Device

Connector 23-12

t94 Data Output Released-to-

Driving Until the First Tunisian

of Critical Timing (Tdzfs) 70 — 48 — 31 — Sender

Connector 23-9

t95 Unlimited Inter lo ck Time (Tui) 0 — 0 — 0 — Host

Connector 23-9

t96a

Maximum time allowed for

output drivers to release

(from asserted or negated)

(Taz)

—10—10—10See Note 2

t96b Minimum time for drivers to

assert or negate (from

released) (Tzad) 0—0—0— Device

Connector

t97

Ready-to-final-STROBE time

(no STROBE edges shall be

sent this long after negation

of DMARDY#) (Trfs)

—75—70—60 Sender

Connector 23-9

t98a Maximum time before

releasing IORDY (Tiordyz) —20 20 20 Device

Connector

t98b Minimum time before driving

IORDY (see Note 2) (Tziordy) 0—0—0— Device

Connector

t99

Time from STROBE edge to

negation of DMARQ or

assertion of STOP (when

sender terminates a burst)

(Tss)

50 — 50 — 50 — Sender

Connector 23-11

NOTES:

1. The specification symbols in parentheses correspond to the AT Attachment – 6 with Packet Interface

(ATA/ATAPI – 6) sp ecification na me.

2. See the A T Attac hmen t – 6 with Packet Interface (ATA/ATAPI – 6) specification for further details on

measuring these timing parameters.

Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2)

Sym Parameter1Mode 0

(ns) Mode 1

(ns) Mode 2

(ns) Measuring

Location Figure

Min Max Min Max Min Max

Intel ® ICH7 Family Datasheet 807

Electrical Characteristics

Table 23-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2)

Sym Parameter1Mode 3

(ns) Mode 4

(ns) Mode 5

(ns) Measuring

Location Figure

Min Max Min Max Min Max

t80 Sustained Cycle Time

(T2cyctyp) 90 60 40 Sender

Connector

t81 Cycle Time (Tcyc) 39 — 25 — 16.

8—End

Recipient

Connector 23-10

t82 Two Cycle Time (T2cyc) 86 — 57 — 38 — Sender

Connector 23-10

t83 Data Setup Time (Tds) 7 — 5 — 4.0 — Recipient

Connector 23-10

t83b

Recipient IC data setup time

(from data valid until

STROBE edge) (see Note 2)

(Tdsic)

6.8 — 4.8 — 2.3 — ICH7 Balls

t84 Data Hold Time (Tdh) 5 — 5 — 4.6 — Recipient

Connector 23-10

t84b

Recipient IC data hold time

(from STROBE edge until

data may become invalid)

(see Note 2) (Tdhic)

4.8 — 4.8 — 2.8 — ICH7 Balls

t85 Data Valid Setup Time

(Tdvs) 20 — 6.7 — 4.8 — Sender

Connector 23-9

23-10

t85b

Sender IC data valid setup

time (from data valid until

STROBE edge) (see Note 2)

(Tdvsic)

22.

6— 9.5 — 6.0 — ICH7 Balls

t86 Data Valid Hold Time (Tdvh) 6.2 — 6.2 — 4.8 — Sender

Connector 23-9

23-10

t86b

Sender IC data valid hold

time (from STROBE edge

until data may become

invalid)

(see Note 2) (Tdvhic)

9.0 — 9.0 — 6.0 — ICH7 Balls

t87 Limited Interlock Time (Tli) 0 100 0 100 0 75 See Note 2 23-12

t88 Interlock Time w/ Minimum

(Tmli) 20 — 20 — 20 —Host

Connector 23-12

t89 Envelope Time (Tenv) 20 55 20 55 20 50 Host

Connector 23-10

t90 Ready to Pause Time (Trp) 100 — 100 — 85 — Recipient

Connector 23-11

t91 DMACK setup/hold Time

(Tack) 20 — 20 — 20 — Host

Connector 23-12

t92a CRC Word Setup Time at

Host (Tcvs) 20 — 6.7 — 10 — Host

Connector

Electrical Characteristics

808 Intel ® ICH7 Family Datasheet

t92b

CRC Word Hold Time at

Sender

CRC word valid hold time at

sender (from DMACK#

negation until CRC may

become invalid) (see Note 2)

(Tcvh)

6.2 — 6.2 — 10.

0—Host

Connector

t93 STROBE output released-to-

driving to the first transition

of critical timing (Tzfs) 0—0—35— Device

Connector 23-12

t94

Data Output Released-to-

Driving Un til the First

Transition of Critical Timing

(Tdzfs)

20.

0—6.7—25— Sender

Connector

t95 Unlimited Interlock Time

(Tui) 0—0—0— Host

Connector

t96a

Maximum time allowed for

output drivers to release

(from asserted or negated)

(Taz)

—10—10—10See Note 2

t96b Drivers to assert or negate

(from released) (Tzad) 0—0—0— Device

Connector

t97

Ready-to-final-STROBE time

(no STROBE edges shall be

sent this long after negation

of DMARDY#) (Trfs)

—60—60—50 Sender

Connector

t98a Maximum time before

releasing IORDY (Tiordyz) —20—20—20 Device

Connector

t98b Minimum time before

driving IORDY (see Note 2)

(Tziordy) 0—0—0— Device

Connector

t99

Time from STROBE edge to

negation of DMARQ or

assertion of STOP (when

sender terminates a burst)

(Tss)

50 — 50 — 50 — Sender

Connector 23-11

NOTES:

1. The specification symbols in parentheses correspond to the AT Attachment – 6 with Packet Interface

(ATA/ATAPI – 6) specification n ame.

2. See the A T Attac hment – 6 with Pack et Interface ( ATA/ATAPI – 6) specifi cation for further details on

measuring these timing parameters.

Table 23-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (S heet 2 of 2)

Sym Parameter1Mode 3

(ns) Mode 4

(ns) Mode 5

(ns) Measuring

Location Figure

Min Max Min Max Min Max

Intel ® ICH7 Family Datasheet 809

Electrical Characteristics

Table 23-15. Universal Serial Bus Timing

Sym Parameter Min Max Units Notes Fig

Full-speed Source1

t100 USBPx+, USBPx- Driver Rise Time 4 20 ns Note 2,

CL = 50 pF 23-13

t101 USBPx+, USBPx- Driver Fall Time 4 20 ns Note 2,

CL = 50 pF 23-13

t102 Source Differential Driver Jitter

To Next Transition

For Paired Transitions –3.5

–43.5

4ns

3, 4 23-14

t103 Source SE0 interval of EOP 160 175 ns 523-15

t104 Source Jitter for Differential Transition

to SE0 Transition –25 ns 6

t105 Receiver Data Jitter Tolerance

To Next Transition

For Paired Transitions –18.5

–918.5

9ns

423-14

t106 EOP Width: Must accept as EOP 82 — ns 523-15

t107 Width of SE0 interval during differential

transition —14ns

Low-speed Source7

t108 USBPx+, USBPx – Driver Rise Time 75 300 ns Note 2, 8,

CL = 50 pF

CL = 350 pF 23-13

t109 USBPx+, USBPx – Driver Fall Time 75 300 ns Note 2, 8,

CL = 50 pF

CL = 350 pF 23-13

t110 Source Differential Driver Jitter

To Next Transition

For Paired Transitions –25

–14 25

14 ns

3, 423-14

t111 Source SE0 interval of EOP 1.25 1.50 µs 523-15

t112 Source Jitter for Differential Transition

to SE0 Transition –40 100 ns 6

t113 Receiver Data Jitter Tolerance

To Next Transition

For Paired Transitions –152

–200 152

200 ns

423-14

t114 EOP Width: Must accept as EOP 670 — ns 523-15

t115 Width of SE0 interval during differential

transition — 210 ns

NOTES:

1. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s.

2. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at

maximum.

3. Timing difference between the differential data signals.

4. Measured at crossover point of differential data signals.

5. Measured at 50% swing point of data signals.

6. Measured from last crossover point to 50% swing point of data line at leading edge of EOP.

7. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.

8. Measured from 10% to 90% of the data signal.

Electrical Characteristics

810 Intel ® ICH7 Family Datasheet

Table 23-16. SATA Interface Timings (Desktop and Mobile Only)

Sym Parameter Min Max Units Notes Figure

UI Gen I Operating Data Period 666.43 670.12 ps

UI-2 Gen II Operating Data Period (3Gb/s) 333.21 335.06 ps

t120 Rise Time 0.2 0.41 UI 1

NOTES:

1. 20% – 80% at transmitter

t121 Fall Time 0.2 0.41 UI 2

2. 80% – 20% at transmitter

t122 TX differential skew — 20 ps

t123 COMRESET 310.4 329.6 ns 3

3. As measured from 100 mV differential crosspoints of last and first edges of burst.

t124 COMWAKE transmit spacing 103.5 109.9 ns 3

t125 OOB Operating Data period 646.67 686.67 ns 4

4. Operating data period during Out-Of-Band burst transmissions.

Table 23-17. SMBus Timing

Sym Parameter Min Max Units Notes Figure

t130 Bus Tree Time Between Stop and Start

Condition 4.7 — µs 23-16

t131 Hold Time after (repeated) Start Condition.

After this period, the first clock is

generated. 4.0 — µs 23-16

t132 Repeated Start Condition Setup Time 4.7 — µs 23-16

t133 Stop Condition Setup Time 4.0 — µs 23-16

t134 Data Hold Time 0 — ns 1

NOTES:

1. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.

23-16

t135 Data Setup Time 250 — ns 23-16

t136 Device Time Out 25 35 ms 2

2. A device will timeout when any clock low exceeds this value.

t137 Cumulative Clock Low Extend Time (slave

device) —25ms3

3. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial

start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and

reset itself.

23-17

t138 Cumulativ e Clock Low Extend Time (master

device) —10ms4

4. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message

as defined from start-to-ack, ack-to-ack or ack-to-stop.

23-17

Intel ® ICH7 Family Datasheet 811

Electrical Characteristics

Table 23-18. AC ’97 / Intel® High Definition Audio Timing

Sym Parameter Min Max Units Notes Figures

t140 ACZ_SDIN[2:0] Setup to Falling Edge of

ACZ_BIT_CLK 10 — ns 123-30

t141 ACZ_SDIN[2:0] Hold from Falling Edge of

ACZ_BIT_CLK 10 — ns 123-30

t142 ACZ_SYNC, ACZ_SDOUT valid dela y from rising

edge of ACZ_BIT_CLK —15ns 123-30

t143 Time duration for which ACZ_SDOUT is valid

before ACZ_BIT_CLK edge. 7—ns 223-31

t144 Time duration for which ACZ_SDOUT is valid

after ACZ_BIT_CLK edge. 7—ns 223-31

t145 Setup time for ACZ_SDIN[2:0 ] at rising edge of

ACZ_BIT_CLK 15 — ns 223-31

t146 Hold time for ACZ_SDIN[2:0] at rising edge of

ACZ_BIT_CLK 0—ns 223-31

NOTES:

1. Audio link operating in AC ‘97 mode. (Desktop and Mobile Only)

2. Audio link operating in Intel High Definition Audio mode.

Table 23-19. LPC Timing

Sym Parameter Min Max Units Notes Figures

t150 LAD[3:0] Valid Delay from PCICLK Rising 2 11 ns 23-2

t151 LAD[3:0] Output Enable Dela y from PCICLK

Rising 2— ns 23-6

t152 LAD[3:0] Float Delay from PCICLK Rising — 28 ns 23-4

t153 LAD[3:0] Setup Time to PCICLK Rising 7 — ns 23-3

t154 LAD[3:0] Hold Time from PCICLK Rising 0 — ns 23-3

t155 LDRQ[1:0]# Setup Time to PC ICLK Rising 12 — ns 23-3

t156 LDRQ[1:0]# Hold Time from PCICLK Rising 0 — ns 23-3

t157 LFRAME# Valid Delay from PCICLK Rising 2 12 ns 23-2

Table 23-20. Miscellaneous Timings

Sym Parameter Min Max Units Notes Figures

t160 SERIRQ Setup Time to PCICLK Rising 7 — ns 23-3

t161 SERIRQ Hold Time from PCICLK Rising 0 — ns 23-3

t162 RI#, EXTSMI#, GPIO, USB Resume Pulse

Width 2 — RTCCLK 23-5

t163 SPKR Valid Delay from OSC Rising — 200 ns 23-2

t164 SERR# Active to NMI Active — 200 ns

t165 IGNNE# Inactive from FERR# Inactive — 230 ns

Electrical Characteristics

812 Intel ® ICH7 Family Datasheet

Table 23-21. SPI Timings (Desktop and Mobile Only)

Sym Parameter Min Max Units Notes Figures

t180 Serial Clock Frequency 17.3 1 8.4 MHz 1

NOTES:

1. The typical clock frequency driven by the ICH7 is 17.9 MHz.

t182 Duty cycle at the host 40 60 % 23-32

t183 Tco of SPI_MOSI with respect to serial

clock falling edge at the host -5 13 ns 23-32

t184 Setup of SPI_MISO with respect to serial

clock falling edge at the host 16 — ns 23-32

t185 Hold of SPI_MISO with respect to serial

clock falling edge at the host 0—ns 23-32

t186 Setup of SPI_CS# assertion with respect

to serial clock rising at the host. 30 — ns 23-32

t187 Hold of SPI_CS# deassertion with respect

to serial clock falling at the host. 30 — ns 23-32

Table 23-22. (Power Sequencing and Reset Signal Timings (Sheet 1 of 2)

Sym Parameter Min Max Units Notes Fig

t200 VccRTC active to RTCRST# inactive 1 8 — ms 23-18

23-19

t201 V5REF_Sus active to VccSus3_3 active 0 — ms 123-18

23-19

t202 VccSus3_3 active to VccSus1_05 active — — — 223-18

23-19

t203 VccRTC supply active to VccSus supplies

active 0—ms323-18

23-19

t204 VccSus supplies active to LAN_RST#

inactive, RSMRST# inactive

(Desktop Only) 10 — ms 23-18

23-20

t205 VccSus supplies active to RSM RST#

inactive

(Mobile/Ultra Mobile Only) 5 — ms 23-19

23-21

t206 VccLAN3_3 active to VccLAN1_05 active

(Mobile Only) ——— 423-19

t207 VccSus supplies active to VccLAN supplies

active

(Mobile Only) 0—ms523-19

t208 VccLAN supplies active to LAN_RST#

inactive

(Mobile Only) 10 — ms 23-19

t209 V5REF active to Vcc3_3 active 0 — ms 123-18

23-19

t211 Vcc1_5 active to V_CPU_IO active — — — 623-18

23-19

Intel ® ICH7 Family Datasheet 813

Electrical Characteristics

t212 VccLAN supplies ac tive to Vcc supplies

active

(Mobile Only) 0—ms523-19

t213 VccSus supplies active to Vcc supplies

active

(Desktop Only) 0—ms323-18

t214

Vcc supplies active to PWROK

NOTE: PWROK assertion indicates that

PCICLK has been stable for at

least 1 ms.

99 — ms 5, 7

23-18

23-19

23-20

23-21

23-23

23-24

23-25

23-26

t215 V_CPU_IO active to STPCLK# and

CPUSLP# inactive

(Desktop Only) —50ns 23-20

23-23

23-24

t216

Vcc active to DPR S LPVR inactive and

STPCLK#, STP_CPU#, STP_PCI#,

DPSLP#, DPRSTP# inactive

(Mobile/Ultra Mobile Only)

—50ns 23-21

23-25

23-26

t217

PWROK and VRMPWRGD active and

SYS_RESET# inactive to SUS_STAT#

inactive and Processor I/F signals latched

to strap value

32 38 RTCCLK 8, 9

23-20

23-21

23-23

23-24

23-25

23-26

t218 SUS_STAT# inactive to PLTRST# inactive 2 3 RTCCLK 9

23-20

23-21

23-23

23-24

23-25

23-26

t228 ACZ_RST# acti ve lo w pulse width 1 — us

t229 ACZ_RST# inactive to ACZ_BIT_CLK

startup delay 162.8 — ns

NOTES:

1. 5REF must be powered up be fore Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after

Vcc3_3, or before Vcc3_3 within 0.7 V.

2. The associated 3.3 V and 1.05 V supplies are assumed to power up or down ‘together’. If the integrated

VccSus1_05 voltage regulator is not used: a) VccSus3_3 must power up before VccSus1_05 or after

VccSus1_05 within 0.7 V, b) VccSus1_05 must power down before VccSus3_3 or after VccSus3_3 within 0.7 V.

3. The VccSus suppli e s must not be active while the VccRTC supply is inactive.

4. (Mobile Only) – a) VccLan3_3 must power up before VccLAN1_05 or after VccLAN1_05 within 0.7 V,

b) VccLAN1_05 must power down before VccLAN3_3 or after VccLAN3_3 within 0.7V.

5. (Mobile Only) - Vcc or VccLAN supplies must not be active while the VccS us supp lies are inactive, and the Vcc

supplies must not be active while the VccLAN supplies are inactive.

6. Vcc1_5 must power up before V_CPU_IO or after V_CPU_IO within 0.7 V, b) V_CPU_IO must power down

before Vcc1_5 or after Vcc1_5 within 0.7 V.

7. Vcc supplies refer to all “core well” supplies: Vcc3_3, Vcc1_05, Vcc1_5, V5REF, VccUSBPLL, VccDMIPLL,

VccSATAPLL , V_C PU_IO an d VccH DA (Mo bile On ly). It implies that all “suspend wells” and VccRTC are stable

too.

8. INIT# value determined by value of the CPU BIST Enable bit (Chipset Configuration Register Offset 3414h: bit

2).

9. These transitions are clocked off the internal RTC. 1 RTC clock is approximately from 28.992 µs to 32.044 µs.

Table 23-22. (Power Sequen cing and Reset Signal Timings (Sheet 2 of 2)

Sym Parameter Min Max Units Notes Fig

Electrical Characteristics

814 Intel ® ICH7 Family Datasheet

Table 23-23. Power Management Timings (Sheet 1 of 3)

Sym Parameter Min Max Units Notes Fig

t230 VccSus active to SLP_S5#, SLP_S4#,

SLP_S3#, SUS_STAT#, PLTRST# and

PCIRST#active 50 ns 23-20

23-21

t231

t232 RSMRST# inactive to SUSCLK running,

SLP_S5# inactive 110 ms 1, 2 23-20

23-21

t233 SLP_S5# inactive to SLP_S4# inac tive See Note Below 323-20

23-21

t234 SLP_S4# inactive to SLP_S3# inactive 1 2 RTCCLK 423-20

23-21

t250 Processor I/F signals latched prior to

STPCLK# active

(Mobile/Ultra Mobile Only) 0523-27

23-29

23-30

t253 DPSLP#/Ultra Mobile active to STP_CPU#

active

(Mobile On ly) 11PCICLK

623-28

23-29

t254 STP_CPU# activ e to processor clock st opped

(Mobile/Ultra Mobile Only) 0–PCICLK

6, 7 23-29

23-30

t255 STP_CPU# active to DPRSTP#, DPRSLPVR

active

(Mobile/Ultra Mobile Only) 023-29

t265

Break Event to DPRSTP#, DPRSLPVR

inactive

(C4 Exit)

(Mobile/Ultra Mobile Only)

1.5 1.8 µs 823-29

t266 DPRSLPVR, DPRSTP# inactive to STP_CPU#

inactive and CPU Vcc ramped

(Mobile/Ultra Mobile Only)

Programable.

See

D31:F0:AA,

bits 3:2

µs 23-29

t267 Break Event to STP_CPU# inactive

(C3 Exit)

(Mobile/Ultra Mobile Only) 6Note

14 PCICLK 6, 9, 10 23-28

t268 STP_CPU# inactive to processor clock

running

(Mobile/Ultra Mobile Only) 03PCICLK

6, 723-29

23-30

t269 STP_CPU# inactive to DPSLP# inactive

(Mobile/Ultra Mobile Only) 11PCICLK

6, 11 23-28

23-29

t271 S1 Wake Event to CPUSLP# inactive

(Desktop Only) 1 25 PCICLK 623-22

t273 Break Event to STPCLK# inactive

(C2 Exit)

(Mobile/Ultra Mobile Only) 0ns23-27

t274 STPCLK# inactive to processor I/F signals

unlatched

(Mobile/Ultra Mobile Only) 89PCICLK

5, 623-27

23-29

23-30

t280 STPCLK# active to DMI Message 0 PCICLK 12

23-22

23-23

23-24

23-25

23-26

Intel ® ICH7 Family Datasheet 815

Electrical Characteristics

t281 DMI Message to CPUSLP# active

(Desktop Only) 60 63 PCICLK 623-22

t283 DMI Message to SUS_STAT# active 2 RTCCLK 4

23-23

23-24

23-25

23-26

t284 SUS_STAT# active to PLTRST#, PCIRST#

active

(Desktop Only) 7 17 RTCCLK 423-23

23-24

t285 SUS_STAT# active to STP_PCI# active

(Mobile/Ultra Mobile Only) 2 10 RTCCLK 423-25

23-26

t286 STP_PCI# active to PLTRST# an d PCIRST#

active

(Mobile/Ultra Mobile Only) 5 7 RTCCLK 423-25

23-26

t287 PL TRST#, PCIRST# active to SLP_S3# active 1 2 RT CCLK 4

23-23

23-24

23-25

23-26

t288 (S3COLD Configuration Only) SLP_S3# active

to PWROK, VRMPWRGD inactive

(Mobile/Ultra Mobile Only) 0ms

13 23-25

t289 SLP_S3# active to PWROK, VRMPWRGD

inactive

(Desktop Only) 0ms

13 23-23

t290 (S3COLD Configuration Only) PWROK,

VRMPWRGD inactive to Vcc supplies inactive

(Mobile/Ultra Mobile Only) 20 ns 14, 15 23-25

t291 SLP_S3# active to SLP_S4# active 1 2 RTCCLK 4

23-23

23-24

23-25

23-26

t292 (S3HOT Configuration Only) SLP_S4# active

to VRMPWRGD and PWROK inactive 0ms

13 23-24

23-26

t293 (S3HOT Configuration On ly) PWROK,

VRMPWRGD inactive to Vcc supplies inactive 20 ns 14, 15 23-24

23-26

t294 PWROK, VRMPWRGD inactive to Vcc su pplies

inactive

(Desktop Only) 20 ns 14, 15 23-23

t295 SLP_S4# active to SLP_S5# active 1 2 RTCCLK 4, 16

23-23

23-24

23-25

23-26

t296 Wake Event to SLP_S5# inactive 1 10 RTCCLK 4

23-23

23-24

23-25

23-26

t297 SLP_S5# inactive to SLP_S4# inactive See Note Below 3

23-23

23-24

23-25

23-26

Table 23-23. Power Managemen t Timing s (Sheet 2 of 3)

Sym Parameter Min Max Units Notes Fig

Electrical Characteristics

816 Intel ® ICH7 Family Datasheet

t298 SLP_S4# inactive to SLP_S3# inactive 1 2 RTCCLK 4

23-23

23-24

23-25

23-26

t299 S4 Wa ke Event to SL P_S4# inactive (S4

Wake) See Note Below 3

23-23

23-24

23-25

23-26

t300 S3 Wa ke Event to SL P_S3# inactive (S3

Wake) 0

small

possi

ble

RTCCLK 4

23-23

23-24

23-25

23-26

t301 CPUSLP# inactive to STPCLK# inactive

(Desktop Only) 8 PCICLK 23-22

t302 SLP_S3# inactive to ICH7 check for PWROK

active 45msec

23-23

23-24

23-25

23-26

t303 SLP_S3# active to Vcc supplies inactive 5 us 15, 17

Other Timings

t310 THRMTRIP# active to SLP_S3#, SLP_S4#,

SLP_S5# active 3 PCI CLK

t311 RSMRST# rising edge transition from 20% to 80% 50 us

t312 RSMRST# falling edge transition 18

NOTES:

1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up togeth er, the delay from

RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.

2. If the AFTERG3_EN bit (GEN_PMCON_3 Configuration Register Bit 1) is set to a 1, SLP_S5# will not be de-

asserted until a wake event is detected. If the AFTERG3_EN bit is set to 0, SLP_S5# will deassert within the

specification listed in the table.

3. The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the

“SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).

4. Th ese transitions are clocked off the internal RTC. 1 RTC clock is approximately 28.992 µs to 32.044 µs.

5. Note that this does not apply for synchronous SMIs.

6. Th ese transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns .

7. This is a clock generator specification.

8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for DPRSLPVR

has been met, then this is permitted to be 0.

9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for STP_CPU#

has been met, then this is permitted to be 0.

10.This value should be at most a few clocks greater than the minimum.

11.This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).

12.The ICH7 STPCLK# as sertion will trigger the processor to send a stop gr ant acknowledge cycle. The timing for

this cycle getting to the ICH7 is dependant on the processor and the memory controller.

13.The ICH7 has no maximum timing requirement for this transition. It is up to th e system designer to determine

if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.

14.t290, t 293, and t294 apply during S0 to G3 transitions only. In additi on, the timings are not applied to V5REF.

V5REF timings are bonded by power sequencing.

15.A Vcc supply is inactive when the voltage is below the min value specified in Table 23-8.

16.If the tr ansition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together

similar to timing t287 (PCIRST# active to SLP_S3# active).

17.t303 applies during S0 to S3-S5 transitions.

18.RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.1 V.

Table 23-23. Power Management Timings (Sheet 3 of 3)

Sym Parameter Min Max Units Notes Fig

Intel ® ICH7 Family Datasheet 817

Electrical Characteristics

23.5 Timing Diagrams

Figure 23-1. Clock Timing

Figure 23-2. Valid Delay from Rising Clock Edge

Figure 23-3. Setup and Hold Times

2.0V

0.8V

Period

High Time

Low Time

Fall Tim e Rise Time

Clock 1.5V

Valid Delay

Output

Clock

VTInput

Hold T imeSet up Time

1.5V

Electrical Characteristics

818 Intel ® ICH7 Family Datasheet

Figure 23-4. Float Delay

Figure 23-5. Pulse Width

Figure 23-6. Output Enable Delay

Input VT

Output

Float

Delay

Pulse Wi dth

Clock

Output

Enable

Delay

1.5V

Intel ® ICH7 Family Datasheet 819

Electrical Characteristics

Figure 23-7. IDE PIO Mode

Figure 23-8. IDE Multiword DMA

CS0#, CS1#,

DA[2:0]

DIOR#/DIOW#

DD[15:0] Writes

DD[15:0] Reads

IORDY

t60

t61

t62 t69

t62i

t63 t64

t65 t66 t66z

t60a

t60b

t60rd

t60c

CS0#/

CS1#

DDREQ

DDACK#

DIOR#/DIOW#

DD[15:0]

Read

DD[15:0]

Write

t70m t70n

t70

t70l

t70i

t70d t70k t70j

t70e t70f t70z

t70g

t70g t70h

Electrical Characteristics

820 Intel ® ICH7 Family Datasheet

Figure 23-9. Ultra ATA Mode (Drive Initiating a Burst Read)

Figure 23-10. Ultra ATA Mode (Sustained Burst)

DMARQ

(drive) t91

t89

DMACK# (host)

STOP

(host)

DMARDY#

(host)

STROBE

(drive)

DD[15:0]

DA[2:0], CS[1:0]

t96

t98

t94 t95

t85 t86

t97

t99b

STROBE @ sender

t81

Data @ sender

t86

t85

t86

t85

t81

t82

t86

STROBE @ receiver

Data @ receiver

t84

t83

t84

t83

t84

t99e t99e t99e

t99d t99d

t99g t99g t99g

t99f t99f

Intel ® ICH7 Family Datasheet 821

Electrical Characteristics

Figure 23-11. Ultra ATA Mode (Pausing a DMA Burst)

Figure 23-12. Ultra ATA Mode (Terminating a DMA Burst)

t90

STROBE

DATA

TOP (ho st)

DMARDY#

t99

t88

STOP

(host)

Strobe

(host)

DMARDY#

(drive)

DATA

(host)

DMACK#

(host)

t91

t87

DMARQ

(drive)

CRC

t99c

t87

t99a

t91

t92 t93

Electrical Characteristics

822 Intel ® ICH7 Family Datasheet

Figure 23-13. USB Rise and Fall Times

Figure 23-14. USB Jitter

Figure 23-15. USB EOP Width

Differential

Data Lines

90%

10% 10%

90%

tRtF

Rise Time Fall Time

Low-speed: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF

Full-speed: 4 to 20 ns at CL = 50 pF

High-speed: 0.8 to 1.2 ns at CL = 10 pF

Paired

Transitions

Consecutive

Transitions

Crossover

Points

T period

Differential

Data Lines

Jitter

Differential

Data Li ne s

EOP

Width

Data

Crossover

Level

Tperiod

Intel ® ICH7 Family Datasheet 823

Electrical Characteristics

Figure 23-16. SMBus Transaction

Figure 23-17. SMBus Timeout

t130

SMBCLK

SMBDATA

t131

t19

t134

t20 t21

t135 t132 t18 t13

Start Stop

t137

CLK

ack

CLK

ack

t138 t138

SMBCLK

SMBDATA

Electrical Characteristics

824 Intel ® ICH7 Family Datasheet

NOTES:

1. Other power includes VccUSBPLL, VccDMIPLL, and VccSATAPLL. All of these power signals

must independently meet the timings shown in the figure. There are no timing

interdependencies betw een Vcc1_05 and these other power signals. There are also n o

timing interdependencies for these power signals, including Vcc1_05, to Vcc3_3 and

Vcc1_5_A/Vcc1_5_B. However, If Vcc3_3 (core well buffer) is powered before Vcc1_05

(core well lo gic), co re well si gnal states are indeterminate, undefined, and may glitch prior

to PWROK assertion. Refer to Section 3.3 and Section 3.4 for a list of signals that will be

determinate before PWROK.

2. PRWOK must not glitch, even if RSMRST# is low.

Figure 23-18. Power Sequencing and Reset Signal Timings (Desktop Only)

VccRTC

V_CPU_IO

VccSus3_3

RTCRST#

LAN_RST#,

RSMRST#

t200

t201

ICH

Dkt

V5REF_Sus

V5REF

PWROK

Vcc3_3

VccSus1_05 t203 t204

t209

t211

t214

t202

t213

Vcc1_5_A,

Vcc1_5_B

Vcc1_05

and other

power1

Intel ® ICH7 Family Datasheet 825

Electrical Characteristics

NOTES:

1. Other power includes VccUSBPLL, VccDMIPLL, and VccSATAP LL. All of these power signals

must independently meet the timings shown in the figure. There are no timing

interdependencies between Vcc1_05 and these other power signals. There are also no

timing interdependencies for these power sign als, including Vcc1_05, to Vcc3_3 and

Vcc1_5_A/Vcc1_5_B. However, If Vcc3_3 (core well buffer) is powered before Vcc1_05

(core well logic) , core well signal states are indeterminate, undefined, and may glitch prior

to PWROK assertion. Refer to Section 3.3 and Section 3.4 for a list of signals that will be

determinate before PWROK.

Figure 23-19. Power Sequencing and Re set Signal Timings (Mobile/Ultra Mobile Only)

VccRTC

V_CPU_IO

VccSus3_3

RTCRST#

RSMRST#

t200

t201

V5REF_Sus

V5REF

PWROK

Vcc3_3

VccSus1_05 t203

t202

t209

t212

t214

LAN_RST#

VccLAN1_05

VccLAN3_3

t207 t208

t205

t211

t206

Vcc1_05

and other

power1

Vcc1_5_A,

Vcc1_5_B

Electrical Characteristics

826 Intel ® ICH7 Family Datasheet

NOTES:

1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

Figure 23-20. G3 (Mechanical Off) to S0 Timings (Desktop Only)

VccSus1_05

RunningSUSCLK

SLP_S3#

Vcc1

PWROK

VRMPWRGD

SUS_STAT#

PLTRST#

Pr oc ess or I/F

signals

STPCLK#,

CPUSLP#

DMI message

RSMRST#

LAN_RST# t204

t214

t217

t218

t230

t231

t215 ( f rom V _CPU_IO)

G3 S3 S0 S0 state

ICH7_G3_to_S0_DT.vsd

G3 S 5

System

State S4

SLP_S4#

SLP_S5# t232

t233 t234

VccSus3_3

St rap Values N orm al Operation

t202

Intel ® ICH7 Family Datasheet 827

Electrical Characteristics

NOTES:

1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

Figure 23-21. G3 (Mech anical Off) to S0 Timings (Mobile/Ultra Mobile Only)

SLP_S3#

Vcc1,

VccLAN

PWRO K,

LAN_RST#

SUS_STAT#

PLTRST#

Processor I/F

Signals

STPCLK#, STP_CPU#,

STP_PCI#, DPSLP#,

DPRSTP#

DMI message

System

State

Running

Strap Values Normal

Operation

t205

t217

t218

t230

t231

t216

S3 S0 S0 stateG 3 S5 S4

t232

t233 t234

t214

M a in B attery

Removed (G3)

VccSus1_05

SUSCLK

RSMRST#

SLP_S4#

SLP_S5#

ICH

Mbil

VccSus3_3 t202

VRMPWRGD t217

Figure 23-22. S0 to S1 to S0 Timing (Desktop Only)

t280

t281 t271

t301

S0 S0 S1 S1 S 1 S 0 S0

STATE

STPCLK#

DMI Me ssage

CPUSLP#

Wake Event

Electrical Characteristics

828 Intel ® ICH7 Family Datasheet

NOTES:

1. Vcc includes Vcc1_5_A, Vcc 1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

2. t294 is appl icable when the system transitions from S0 to G3 only.

Figure 23-23. S0 to S5 to S0 Timings, S3COLD (Desktop Only)

STPCLK#

DMI Message

SUS_STAT#

PLTRST#

SLP_S3#

(S3COLD Config)

SLP_S5#

Wake Event

PWROK

Vcc1

S0 S0 S3 S3 S5 S0

t283

t284

t287

t289

t294

t214

t217

t218

t215 (from

V_CPU_IO)

t280

ICH7_S0_S5_S0_DT_S3COLD.vsd

SLP_S4#

t291

t295 t297

t298

S4 S4 S3 S3/S4 /S5 S0

t296

t300

t299

VRMPWRGD

Intel ® ICH7 Family Datasheet 829

Electrical Characteristics

NOTES:

1. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

2. t293 is applicable when the system transitions from S0 to G3 only.

Figure 23-24. S0 to S5 to S0 Timings, S3HOT (Desktop Only)

STPCLK#

DMI Message

SUS_STAT#

PLTRST#

SLP_S3#

(S3HOT Config)

SLP_S5#

Wake Event

PWROK

Vcc1

S0 S0 S3 S3 S5 S0

t283

t284

t287

t292

t293

t214

t217

t218

t215 (f rom V _CPU_IO)t280

ICH7_S0_S5_S0_DT_S3HOT.vsd

SLP_S4#

t291

t295 t297

t298

S4 S4 S3 S3/S4/S5 S0

t296

t300

t299

t302

VRMPWRGD

Electrical Characteristics

830 Intel ® ICH7 Family Datasheet

NOTES:

1. t290 is applicable when the system transitions from S0 to G3 only.

2. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

Figure 23-25. S0 to S5 to S0 Timings, S3COLD (Mobile/Ultra Mobile Only)

STP_CPU#,

DPSLP#,

DPRSTP#

PLTRST#

PCIRST#

SLP_S3#

(S3COLD

Board Config)

SLP_S5#

Wake Event

PWROK

Vcc

S0 S0 S 3 S3 S5 S3/S4/S5 S 0 S0

t295

t288

t290

t296

t214

t217

t218

STP_PCI#

STPCLK#

DMI Message

DPRSLPVR

t280

t283

t285

t287

t286

SUS_STAT#

SLP_S4#

t291 t297

t300

t298

t216

t299

t302

Intel ® ICH7 Family Datasheet 831

Electrical Characteristics

NOTES:

1. t293 is applic able when the system transitions from S0 to G3 only.

2. Vcc includes Vcc1_5_A, Vcc1_5_B, Vcc3_3, Vcc1_05, VccUSBPLL, VccDMIPLL,

VccSATAPLL, and V5REF.

Figure 23-26. S0 to S5 to S0 Timings, S3HOT (Mobile/Ultra Mobile Only)

STP_CPU#,

DPSLP#,

DPRSTP#

PLTRST#

PCIRST#

SLP_S3#

(S3HOT

Board Config)

SLP_S5#

Wake E vent

VRMPWRGD

Vcc

S0 S0 S3 S3 S5 S 3 /S 4 / S 5 S 0 S0

t295

t292

t293

t296

t217

t218

STP_PCI#

STPCLK#

DM I Message

DPRSLPVR

t280

t283

t285

t287

t286

SUS_STAT#

SLP_S4#

t291 t297

t300

t298

t216

t299

t302

Figure 23-27. C0 to C2 to C0 Timings (Mobile/Ultra Mobile Only)

Unlatched Latched Unlatched

CPU I/F

Signals

STPCLK#

Break

Event t250 t273 t274

Electrical Characteristics

832 Intel ® ICH7 Family Datasheet

Figure 23-28. C0 to C3 to C0 Timings (Mobile/Ultra Mobile Only)

Figure 23-29. C0 to C4 to C0 Timings (Mobile/Ultra Mobile Only)

Unlatched Latched

CPU I/F

Signals

STPCLK#

C0_C3_Timing

Break

Event

Bus Master

STP_CPU#

t250

t253

t268

t269

t274

Active Idle

DPSLP#

Unlatched

CPU Clocks Running Running

Stopped

t267

t254

Unlatched

CPU I/F

Signals

STPCLK#

C0_C4_Timing

Break Event

Bus Master

STP_CPU#

t250

t253

t266

t269

t274

DPRSTP#

DPSLP#

Active Idle

DPRSLPVR

Unlatched

CPU Clocks Running Running

t254

t255

CPU Vcc

t265

Stopped t268

Latched

Intel ® ICH7 Family Datasheet 833

Electrical Characteristics

Figure 23-30. AC ’97 Data Input and Output Timings (Desktop and Mobile Only)

Figure 23-31. Intel® High Definition Audio Input and Output Tim in gs

VOH

VOL

ACZ_SDOUT

ACZ_SDIN[2:0]

ACZ_SYNC

ACZ_BIT_CLK VIH VIL

t142

t141

t140

ACZ_SDOUT

ACZ_SDIN[2:0]

ACZ_BIT_CLK

t143 t143

t144 t144

t145 t146

Electrical Characteristics

834 Intel ® ICH7 Family Datasheet

Figure 23-32. SPI Timings (Desktop and Mobile Only)

t182

SPI_CLK

SPI_MOSI

SPI_MISO

t184

t183

t185

SPI_CS#

t186 t187

Intel ® ICH7 Family Datasheet 835

Package Information

24 Package Information

24.1 Desktop and Mobile Package Information

The ICH7 package information is shown in Figure 24-1, Figure 24-2, and Figure 24-3.

Note: All dimensions, unless otherwise specified, are in millimeters

Figure 24-1. Intel® ICH7 Package (Top View)

TOP VIEW

PIN #1 IDENTIFIER

0.127 A//

A0.127

4 PLACES

-A-

-B-

22.10 REF

Package Information

836 Intel ® ICH7 Family Datasheet

Figure 24-2. Intel® ICH7 Package (Bottom View)

BOTTO M VIEW

20.50

0.70 CORNER

PIN #1

12 11 10 954867

2021 13

16 14

2324

2526

22 213

10 9

12 54

876

21 20 13

16 15 14

1718

28 23

24252627

1.10 REF

0.78 REF

Figure 24-3. Intel® ICH7 Package (Side View)

SIDE VIEW

-C-

C//

0.20

0.15

SEATING PLANE

Intel ® ICH7 Family Datasheet 837

Package Information

24.2 Ultra Mobile Package Information

Figure 24-4 is the Intel ICH7-U package drawing.

Figure 24-4. Intel ICH7-U Package Drawin g

Package Information

838 Intel ® ICH7 Family Datasheet

Intel ® ICH7 Family Datasheet 839

Testability (Desktop and Mobile Only)

25 Testability (Desktop and Mobile

Only)

The ICH7 supports XOR Chain test mode. This non-functional test mode is a dedicated

test mode when the chip is not operating in its normal manner. The XOR Chain Mode is

entered as indicated in Figure 25-1.

Figure 25-1. XOR Chain Test Mode Selection, Entry and Testing

REQ# Settings XOR Chain

REQ[4:1]# = 0000 XOR 1

REQ[4:1]# = 0001 XOR 2

REQ[4:1]# = 0010 XOR 3

REQ[4:1]# = 0011 XOR 4

REQ[4:1]# = 0100 XOR 5

REQ[4:1]# = 0111 ALL-Z

PCICLK

RSMRST# /

LAN_RST#

RTCRST#

PWROK

Chain Select (1-5)

REQ[4:1]#

ACZ_SDOUT /

EE_DOUT

XOR Chain Test Mode Selection, Entr y and Testing

Notes: RSMRST#, PWROK, RTCRST#, LAN_RST# must be held high during test mode and output testing.

PCICLK & DM I_CLK should be approximately 1 M Hz w hile running/toggling

TP3 / GPIO25

DMI_CLK

5ms 10ms Run 120 ms Run 2 ms

DMI_ CLK p = ‘0 ’

DMI_ CLK n = ‘1 ’ Toggle

Held Low

XOR Output Enabled

For chains 4 and 5, all PETx[n] signals (of that chain) must be driven during testing.

Testability (Desktop and Mobile Only)

840 Intel ® ICH7 Family Datasheet

XOR Chain Testability Algorithm Example

XOR chain testing allows motherboard manufacturers to check component connectivity

(e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in

Table 25-1.

In this example, Vector 1 applies all 0s to the chain inputs. The outputs being non-

inverting will consistently produce a 1 at the XOR output on a good board. One short to

VCC (or open floating to VCC) will result in a 0 at the chain output, signaling a defect.

Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even

number of input signals in the chain), will consistently produce a 1 at the XOR chain

output on a good board. One short to VSS (or open floating to VS S) will result in a 0 at

the chain output, signaling a defect. It is important to note that the number of inputs

pulled to 1 will affect the expected chain output value. If the number of chain inputs

pulled to 1 is even, then expect 1 at the output. If the number of chain inputs pulled to

1 is odd, expect 0 at the output.

Continuing with the example in Table 25-1, as the input pins are driv en to 1 across the

chain in sequence, the XOR Output will toggle between 0 and 1. Any break in the

toggling sequence (e.g., “1011”) will identify the location of the short or open.

Figure 25-2. Example XOR Chain Circuitry

Input

Pin 2

Vcc

Input

Pin 1 Input

Pin 3 Input

Pin 4 Input

Pin 5 Input

Pin 6

XOR

Chain

Output

Table 25-1. XOR Test Pattern Example

Vector Input

Pin 1 Input

Pin 2 Input

Pin 3 Input

Pin 4 Input

Pin 5 Input

Pin 6 XOR

Output

10000001

21000000

31100001

41110000

51111001

61111100

71111111

Intel ® ICH7 Family Datasheet 841

Testability (Desktop and Mobile Only)

25.1 XOR Chain Tables

Table 25-2. XOR Chain 1 (REQ[4:1]# = 0000)

Pin Name Ball # Notes Pin Name Ball # Notes

ACZ_SYNC R6 Top of XOR

Chain AD16 E12 30th signal in

XOR

ACZ_SDOUT T4 GNT3# F13

ACZ_BIT_CLK U1 TRDY# F14

GPIO0

(Desktop Only) /

BM_BUSY#

(Mobile On ly)

AB18 AD18 D11

GPIO16

(Desktop Only) /

DPRSLPVR

(Mobile On ly)

AC22 AD26 A8

AD0 E18 GPIO1/REQ5# C8

AD3 F18 AD24 D9

AD1 C18 AD15 G13

AD5 A18 PAR E10

REQ[2]# C17 AD22 F10

GNT[2]# D17 AD28 C7

AD6 E17 GPIO17/GNT5# D8

AD2 A16 PIRQD# B5

REQ[1]# C16 GNT0# E7

GNT[1]# D16 REQ[0]# D7

C/BE0# B15 PIRQB# B4

AD4 E16 GPIO4/PIRQG# F8

GNT[4]#/GPIO48 A14 PIRQC# C5

FRAME# F16 PIRQA# A3

AD9 C14 GPIO2/PIRQE# G8

STOP# F15 AD30 E6

REQ[4]#/GPIO22 A13 GPIO3/PIRQF# F7

AD13 C13 GPIO5/PIRQH# G7

AD11 D14 ACZ_SDIN2 T1

AD10 E14 ACZ_SDIN0 T2

C/BE1# C12 ACZ_SDIN1 T3

REQ3# E13 ACZ_RST# R5

AD20 A10

SERR# B10

TP0

(Desktop O nly) /

BATLOW#

(Mobile On ly)

C21 XOR C hain 1

OUTPUT

Testability (Desktop and Mobile Only)

842 Intel ® ICH7 Family Datasheet

Table 25-3. XOR Chain 2 (REQ[4:1]# = 0001)

Pin Name Ball # Notes Pin Name Ball # Notes

AD7 A17 Top of XOR

Chain SATA0RXP AE3 27th signal in

XOR

AD8 A15 2nd signal in

XOR SATA0RXN AF3

C/BE3# C15 SATA0TXN AG2

DEVSEL# A12 SATA0TXP AH2

AD14 G15

SATA1RXP

(Desktop Only)

Reserved

(Mobile Only)

AD5

AD12 B12

SATA1RXN

(Desktop Only)

Reserved

(Mobile Only)

AE5

AD19 A11

SATA1TXN

(Desktop Only)

Reserved

(Mobile Only)

AG4

C/BE2# D12

SATA1TXP

(Desktop Only)

Reserved

(Mobile Only)

AH4

PCICLK A9 SATARBIAS AG10

AD17 C11 SATARBIAS# AH10

AD25 B9 GPIO7 AC18

PLOCK# E11 GPIO33/

AZ_DOCK_EN#

(Mobile Only) AC19

PERR# C9

GPIO32/

(Desktop Only) /

CLKRUN# (Mobile

Only)

AG18

IRDY# A7 GPIO21/SATA0GP AF19

AD21 F11 MCH_SYNC# AH20

AD27 A6 THRM# AF20

AD23 E9 GPIO39 AE20

AD29 B6 GPIO38 AD20

AD31 D6 GPIO6 AC21

GPIO34/

AZ_DOCK_RST#

(Mobile Only) U2 GPIO35/

SATACLKREQ# AD21

LFRAME# AB3 PLTRST# C26

LAD3 Y6 RI# A28

LAD0 AA6 TP3 F21

LAD1 AB5 PWRBTN# C23

Intel ® ICH7 Family Datasheet 843

Testability (Desktop and Mobile Only)

LAD2 AC4 GPIO8 E21

LDRQ0# AC3 TP0/BATLOW# C21

EL_RSVD

(Digital Home

Only) /

GPIO26

A21

GPIO2/PIRQE# G8 XOR Ch ain 2

OUTPUT

Table 25-4. XOR Chain 3 (REQ[4:1]# = 0010)

Pin Name Ball # Notes Pin Name Ball # Notes

INTVRMEN W4 Top of XOR

Chain DCS3# AD16 26th signal in

XOR

INTRUDER# Y5 2nd signal in

XOR DA0 AH17

DD6 AD12 DA2 AF17

DD10 AB13 DA1 AE17

DD8 AE12 GPIO19/SATA1GP AH18

DD7 AC12 INIT3_3V# AG21

DD9 AF12

GPIO18

(Desktop O nly) /

STP_PCI#

(Mobile On ly)

AC20

DD3 AF13

GPIO20

(Desktop O nly) /

STP_CPU#

(Mobile On ly)

AF21

DD2 AG13 VRMPWRGD AD22

DD5 AC13 RCIN# AG23

DD13 AH13 A20GATE AE22

DD14 AH14 INIT# AF22

DD4 AD14 NMI AH24

DD11 AC14 GPIO49/

CPUPRWRGD AG24

DD1 AE14

TP1

(Desktop O nly) /

DPRSTP# (Mobile

Only)

AF24

DD12 AF14

TP2

(Desktop O nly) /

DPSLP#

(Mobile On ly)

AH25

DIOR# AF15 INTR AF25

DDREQ AE15 THRMTRIP# AF26

Table 25-3. XOR Chain 2 (REQ[4:1]# = 0001) (Continued)

Pin Name Ball # Notes Pin Name Ball # Notes

Testability (Desktop and Mobile Only)

844 Intel ® ICH7 Family Datasheet

DD15 AC15 CPUSLP# AG27

DIOW# AH15 STPCLK# AH22

DD0 AB15 A20M# AH28

IDEIRQ AH16 SPKR A19

IORDY AG16 OC4# E5

DDACK# AF16 SPI_MISO P2

SPI_ARB P1

SPI_MOSI P5

SPI_CS# P6

SPI_CLK R2

DCS1# AE16 RI# A28 XOR Chain 3

OUTPUT

Table 25-5. XOR Chain 4-1 (REQ[4:1]# = 0011)

Pin Name Ball # Notes Pin Name Ball # Notes

DMI3RXP AD24 Top of XOR

Chain SMLINK0 B25 23nd signal in

XOR

DMI3RXN AD25 2nd signal in

XOR SMLINK1 A25

DMI3TXP AC27

EL_STATE1

(Digital Home

Only) /

GPIO28

E23

DMI3TXN AC28 SLP_S3# B24

DMI2RXP AB25 SLP_S4# D23

DMI2RXN AB26 SLP_S5# F22

DMI2TXP AA27 GPIO15 E22

DMI2TXN AA28 SMBALERT#/

GPIO11 B23

PERp6 /

Reserved

(intel® ICH7 Base) T24

Must be driven

for all skus

including ICH7

Base

SMBCLK C22

PERn6 /

Reserved

(intel® ICH7 Base) T25

Must be driven

for all skus

including ICH7

Base

GPIO25 D20

PETp6 /

Reserved

(intel® ICH7 Base) R27

Must be driven

for all skus

including ICH7

Base

WAKE# F20

Table 25-4. XOR Chain 3 (REQ[4:1]# = 0010) (Continued)

Pin Name Ball # Notes Pin Name Ball # Notes

Intel ® ICH7 Family Datasheet 845

Testability (Desktop and Mobile Only)

PETn6 /

Reserved

(intel® ICH7 Base) R28

Must be driven

for all s kus

including ICH7

Base

GPIO9 E20

PERp4 M25 SMBDATA B22

PERn4 M26 GPIO13 E19

PETp4 L27 SYS_RST# A22

PETn4 L28 SUSCLK C20

PERp3 K25

EL_STATE0

(Digital Home

Only) /

GPIO27

B21

PERn3 K26 GPIO12 F19

PETp3 J27 GPIO10 A20

PETn3 J28 PME# B19

LINKALERT# A26 PCIRST# B18

SUS_STAT# A27 GPIO8 E21 XOR Chain 4-1

OUTPUT

Table 25-6. XOR Chain 4-2 (REQ[4:1]# = 0011)

Pin Name Ball # Notes Pin Name Ball # Notes

OC6#/GPIO30 A2 Top of XOR

Chain LAN_CLK V3 30th signal in

XOR

OC7#/GPIO31 B3 2nd signal in

XOR LAN_RXD0 U5

OC2# D5 LAN_TXD0 U7

OC1# C4 LAN_RXD1 V4

OC3# D4 EE_SHCLK Y1

OC0# D3 EE_DIN W3

OC5#/GPIO29 C3 LAN_TXD2 V7

CLK48 B2 LAN_TXD1 V6

USBP0N F1 EE_DOUT Y2

USBP0P F2 CLK14 AC1

USBP1N G4 LDRQ1#/GPIO23 AA5

USBP1P G3 SATA2RXP AE7

USBP2N H1 SATA2RXN AF7

USBP2P H2 SATA2TXN AG6

USBP3N J4 SATA2/TXP AH6

USBP3P J3

SATA3RXP

(Desktop Only)

Reserved

(Mobile On ly)

AE9

Table 25-5. XOR Chain 4-1 (REQ[4:1]# = 0011) (Continued)

Pin Name Ball # Notes Pin Name Ball # Notes

Testability (Desktop and Mobile Only)

846 Intel ® ICH7 Family Datasheet

2 2 §

USBP4N K1

SATA3RXN

(Desktop Only)

Reserved

(Mobile Only)

AD9

USBP4P K2

SATA3TXN

(Desktop Only)

Reserved

(Mobile Only)

AG8

USBP5N L4

SATA3TXP

(Desktop Only)

Reserved

(Mobile Only)

AH8

USBP5P L5 SATALED# AF18

USBP6N M1 GPIO37/SATA3GP AE19

USBP6P M2 GPIO36/SATA2GP AH19

USBP7N N4 SERIRQ AH21

USBP7P N3 SMI# AF23

GPIO24 R3 IGNNE# AG22

GPIO14 R4 FERR# AG26

LAN_RSTSYNC U3

LAN_RXD2 T5

EE_CS W1 PLTRST# C26 XOR Chain 4-2

OUTPUT

Table 25-7. XOR Chain 5 (REQ[4:1]# = 0100)

Pin Name Ball # Notes Pin Name Ball # Notes

DMI1RXP Y25 Top of XOR

Chain

PETn5 /

Reserved

(intel® ICH7

Base)

N28

Must be driven

for all skus

including ICH7

Base

DMI1RXN Y26 2nd signal in

XOR PERp2 H25

DMI1TXP W27 PERn2 H26

DMI1TXN W28 PETp2 G27

DMI0RXP V25 PETn2 G28

DMI0RXN V26 PERp1 F25

DMI0TXP U27 PERn1 F26

DMI0TXN U28 PETp1 E27

Table 25-6. XOR Chain 4-2 (REQ[4:1]# = 0011) (Continued)

Pin Name Ball # Notes Pin Name Ball # Notes

Intel ® ICH7 Family Datasheet 847

Testability (Desktop and Mobile Only)

§ §

PERp5 /

Reserved

(intel® ICH7 Base) P25

Must be driven

for all s kus

including ICH7

Base

PETn1 E28

PERn5 /

Reserved

(intel® ICH7 Base) P26

Must be driven

for all s kus

including ICH7

Base

PETp5 /

Reserved

(intel® ICH7 Base) N27

Must be driven

for all s kus

including ICH7

Baes

GPIO2/PIRQE# G8 XOR Chain 5

OUTPUT

Table 25-7. XOR Chain 5 (REQ[4:1]# = 0100) (Continued)

Pin Name Ball # Notes Pin Name Ball # Notes

Testability (Desktop and Mobile Only)

848 Intel ® ICH7 Family Datasheet