General Description
The MAX7034 fully integrated low-power CMOS super-
heterodyne receiver is ideal for receiving amplitude-
shift-keyed (ASK) data in the 300MHz to 450MHz
frequency range (including the popular 315MHz and
433.92MHz frequencies). The receiver has an RF sensi-
tivity of -114dBm. With few external components and a
low-current power-down mode, it is ideal for cost-sensi-
tive and power-sensitive applications typical in the
automotive and consumer markets. The MAX7034 con-
sists of a low-noise amplifier (LNA), a fully differential
image-rejection mixer, an on-chip phase-locked loop
(PLL) with integrated voltage-controlled oscillator
(VCO), a 10.7MHz IF limiting amplifier stage with
received-signal-strength indicator (RSSI), and analog
baseband data-recovery circuitry.
The MAX7034 is available in a 28-pin (9.7mm x 4.4mm)
TSSOP package and is specified over the automotive
(-40°C to +125°C) temperature range.
Features
♦Optimized for 315MHz or 433.92MHz Band
♦Operates from Single +5.0V Supply
♦Selectable Image-Rejection Center Frequency
♦Selectable x64 or x32 fLO/fXTAL Ratio
♦Low (< 6.7mA) Operating Supply Current
♦< 3.0µA Low-Current Power-Down Mode for
Efficient Power Cycling
♦250µs Startup Time
♦Built-In 44dB RF Image Rejection
♦Excellent Receive Sensitivity Over Temperature
♦-40°C to +125°C Operation
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XTAL2
SHDN
PDOUT
DATAOUT
DSP
EN_REG
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
DVDD
DGND
MIXOUT
IRSEL
AGND
MIXIN2
MIXIN1
AVDD
LNAOUT
AGND
LNASRC
LNAIN
AVDD
VDD5
XTAL1
TSSOP
TOP VIEW
MAX7034
+
Pin Configuration
Ordering Information
Applications
19-3109; Rev 3; 6/12
1
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
/V denotes an automotive qualified part.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Typical Application Circuit appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX7034AUI/V+T -40°C to +125°C 28 TSSOP
Automotive Remote
Keyless Entry
Security Systems
Garage Door Openers
Home Automation
Remote Controls
Local Telemetry
Wireless Sensors
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
2
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, VDD5 = +4.5V to +5.5V, no RF signal applied. TA= -40°C to +125°C, unless otherwise noted. Typical val-
ues are at VDD5 = +5.0V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD5 to AGND.......................................................-0.3V to +6.0V
AVDD to AGND .....................................................-0.3V to +4.0V
DVDD to DGND .....................................................-0.3V to +4.0V
AGND to DGND.....................................................-0.1V to +0.1V
IRSEL, DATAOUT, XTALSEL,
SHDN, EN_REG to AGND ....................-0.3V to (VDD5 + 0.3V)
All Other Pins to AGND ..........................-0.3V to (VDVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VDD5 +5.0V nominal supply voltage 4.5 5.0 5.5 V
fRF = 315MHz 6.7 8.2
Supply Current IDD VSHDN = VDD5 fRF = 434MHz 7.2 8.7 mA
Shutdown Supply Current ISHDN VSHDN = 0V 3 8 μA
Input-Voltage Low VIL 0.4 V
EN_REG, SHDN VDD5 -
0.4
Input-Voltage High VIH
XTALSEL V
D V DD
-
0.4
V
Input Logic Current High IIH 15 μA
fRF = 434MHz, VIRSEL = V
D V DD V
D V DD
-
0.4
fRF = 375MHz, VIRSEL = V
D V DD
/2 1.1 V
D V DD
-
1.5
Image-Reject Select Voltage
(Note 2)
fRF = 315MHz, VIRSEL = 0V 0.4
V
DATAOUT Output-Voltage Low VOL ISINK = 10μA 0.125 V
DATAOUT Output-Voltage High VOH ISOURCE = 10μA V
D D 5
-
0.125 V
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
3
AC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA= -40°C to +125°C,
unless otherwise noted. Typical values are at VDD5 = +5.0V and TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Startup Time tON
Time for valid signal detection after VSHDN
= VDD5. Does not include baseband filter
settling.
250 μs
Receiver Input Frequency Range fRF 300 450 MHz
Maximum Receiver Input Level 0 dBm
+25°C, 315MHz -114
Sensitivity at TA = +25oC (Note 3) +25°C, 434MHz -113 dBm
+125°C, 315MHz -113
Sensitivity at TA = +125°C
(Note 3) +125°C, 434MHz -110 dBm
Manchester coded 33
Maximum Data Rate NRZ coded 66 kbps
LNA/MIXER
LNA/Mixer Voltage Gain (Note 4) 330Ω IF filter load 45 dB
LNA/Mixer Input-Referred 1dB
Compression Point -50 dBm
Mixer Output Impedance ZOUT_MIX 330 Ω
fRF = 434MHz, VIRSEL = VDVDD 42
fRF = 375MHz, VIRSEL = VDVDD/2 44
Mixer Image Rejection
fRF = 315MHz, VIRSEL = 0V 44
dB
INTERMEDIATE FREQUENCY (IF)
Input Impedance ZIN_IF 330 Ω
Operating Frequency fIF Bandpass response 10.7 MHz
3dB Bandwidth 10 MHz
RSSI Linearity ±0.5 dB
RSSI Dynamic Range 80 dB
PRFIN < -120dBm 1.15
RSSI Level PRFIN > -40dBm 2.2 V
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
4
Note 1: 100% tested at TA= +125°C. Guaranteed by design and characterization over entire temperature range.
Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass
to AGND with a 1nF capacitor in a noisy environment.
Note 3: Peak power level. BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz.
Note 4: The voltage conversion gain is measured with the LNA input matching inductor and the LNA/Mixer resonator in place, and
does not include the IF filter insertion loss.
Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for
XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDVDD.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DATA FILTER
Maximum Bandwidth 50 kHz
DATA SLICER
Comparator Bandwidth 100 kHz
Output High Voltage VVDD5 V
Output Low Voltage 0V
CRYSTAL OSCILLATOR
VXTALSEL = 0V 6.6128
fRF = 433.92MHz VXTALSEL = VDVDD 13.2256
VXTALSEL = 0V 4.7547
Crystal Frequency (Note 5) fXTAL
fRF = 315MHz VXTALSEL = VDVDD 9.5094
MHz
Crystal Tolerance 50 ppm
Input Capacitance From each pin to ground 6.2 pF
Maximum Load Capacitance CLOAD 10 pF
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA= -40°C to +125°C,
unless otherwise noted. Typical values are at VDD5 = +5.0V and TA= +25°C.) (Note 1)
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
5
Typical Operating Characteristics
(
Typical Application Circuit
, VDD5 = +5.0V, fRF = 433.92MHz, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX7034 toc01
4.5 4.7 4.9 5.1 5.3 5.5
6.6
7.0
6.8
7.2
7.4
7.6
7.8
+105°C+125°C
+85°C
+25°C-40°C
SUPPLY CURRENT vs. RF FREQUENCY
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
MAX7034 toc02
250 300 350 400 450 500
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
+105°C
+125°C
+85°C
+25°C
-40°C
BIT-ERROR RATE
vs. PEAK RF INPUT POWER
PEAK RF INPUT POWER (dBm)
BIT-ERROR RATE (%)
MAX7034 toc03
-130 -125 -120 -115 -110
0.01
0.10
1.00
10.00
100.00
315MHz
433.92MHz
SENSITIVITY vs. TEMPERATURE
TEMPERATURE (°C)
SENSITIVITY (dBm)
MAX7034 toc04
-40 -15 10 35 60 85 110
-120
-118
-116
-114
-112
-110
-108
-106
-104
-102
433.92MHz
315MHz
RSSI vs. RF INPUT POWER
RF INPUT POWER (dBm)
RSSI (V)
MAX7034 toc05
-140 -120 -100 -80 -60 -40 -20 0
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
IF BANDWIDTH = 280kHz
RSSI AND DELTA vs. IF INPUT POWER
IF INPUT POWER (dBm)
RSSI (V)
DELTA
MAX7034 toc06
-25
-20
-15
-10
-5
0
5
10
15
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 10
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
RSSI
DELTA
LNA/MIXER VOLTAGE GAIN
vs. IF FREQUENCY
IF FREQUENCY (MHz)
LNA/MIXER VOLTAGE GAIN (dB)
MAX7034 toc07
0 5 10 15 20 25 30
-5
5
15
25
35
45
55
65
UPPER SIDEBAND
LOWER SIDEBAND
49.7dB
IMAGE
REJECTION
IMAGE REJECTION vs. RF FREQUENCY
RF FREQUENCY (MHz)
IMAGE REJECTION (dB)
MAX7034 toc08
280 300 320 340 360 380 400 420 440 460 480
0
10
20
30
40
50
60
fRF = 315MHz
fRF = 433.92MHz
IMAGE REJECTION vs. TEMPERATURE
TEMPERATURE (°C)
IMAGE REJECTION (dB)
MAX7034 toc09
-40 -15 10 35 60 85 110
40
42
44
46
48
50
52
433.92MHz
315MHz
Pin Description
PIN NAME FUNCTION
1 XTAL1 Crystal Input 1
2, 7 AVDD
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.4V low-
dropout regulator, and should be bypassed to AGND with a 0.1μF capacitor as close as possible to
the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a
0.01μF capacitor as close as possible to the pin (see the Voltage Regulator section and the Typical
Application Circuit).
3 LNAIN Low-Noise Amplifier Input. See the Low-Noise Amplifier section.
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc13
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 315MHz
PHASE NOISE
vs. OFFSET FREQUENCY
MAX7033 toc14
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k100
-120
-100
-80
-60
-40
-20
0
-140
10 10M
fRF = 433.92MHz
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VDD5 = +5.0V, fRF = 433.92MHz, TA= +25°C, unless otherwise noted.)
NORMALIZED IF GAIN
vs. IF FREQUENCY
MAX7034 toc10
IF FREQUENCY (MHz)
NORMALIZED IF GAIN (dB)
10
-25
-20
-15
-10
-5
0
5
-30
1 100
S11 MAGNITUDE PLOT OF RFIN
vs. FREQUENCY
MAX7034 toc11
FREQUENCY (MHz)
S11 MAGNITUDE (dB)
470440380 410260 290 320 350230
-40
-30
-20
-10
0
10
20
30
40
50
-50
200 500
315MHz
-24.1dB
S11 SMITH CHART PLOT OF RFIN
MAX7034 toc12
500MHz
200MHz
WITH INPUT
MATCHING
315MHz
6
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Pin Description (continued)
PIN NAME FUNCTION
4 LNASRC Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. See the Low-Noise Amplifier section.
5, 10 AGND Analog Ground
6 LNAOUT Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise
Amplifier section.
8 MIXIN1 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See
the Typical Application Circuit.
9 MIXIN2 2nd Differential Mixer Input. Connect to VDD3 side of the LC tank filter through a 100pF capacitor. See
the Typical Application Circuit.
11 IRSEL
Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at
434MHz. See the Mixer section.
12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 DGND Digital Ground
14 DVDD Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF
capacitor as close as possible to the pin (see the Typical Application Circuit).
15 EN_REG Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device
operation between +3.0V and +3.6V. See the Voltage Regulator section.
16 XTALSEL Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high
to select fLO/fXTAL ratio of 32.
17 IFIN1 1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
18 IFIN2 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close as possible to the pin.
19 DFO Data Filter Output
20 DSN Negative Data Slicer Input
21 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 DSP Positive Data Slicer Input
24 VDD5
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For
+5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.4V output appears at
AVDD pin 2. (see the Voltage Regulator section and the Typical Application Circuit).
25 DATAOUT Digital Baseband Data Output
26 PDOUT Peak-Detector Output
27 SHDN Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a
100kΩ resistor.
28 XTAL2 C r ystal Inp ut 2. C an al so b e d r i ven w i th an exter nal r efer ence osci l l ator . S ee the C r ystal O sci l l ator secti on.
7
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
8
Functional Diagram
LNAOUT MIXIN1 MIXIN2
0˚
90˚
IFIN1MIXOUT IFIN2
RSSI
RDF2
100kΩ
RDF1
100kΩ
DIVIDE
BY 64 VCO
LOOP
FILTER
PHASE
DETECTOR
CRYSTAL
DRIVER
POWER-
DOWN
IF LIMITING
AMPS
7
LNASRC
DATA
SLICER
DATA
FILTER
Q∑
I
IMAGE
REJECTION
3.4V REG
24
2
IRSEL
13
5, 10
AVDD
VDD5
AVDD
DVDD
DGND
AGND
LNAIN 3
XTALSEL
16
XTAL1
1
XTAL2
28
SHDN
27
DATAOUT
25
DSN
20
DSP
23
DFO
19
PDOUT
26
OPP
21
DFFB
22
4 15 6 8 9 11 12 17 18
EN_REG
÷2
÷1
MAX7034
LNA
14
Detailed Description
The MAX7034 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates can be as high as 33kbps Manchester
(66kbps NRZ).
The MAX7034 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
Voltage Regulator
For operation with a single +4.5V to +5.5V supply voltage,
connect VDD5 and the EN_REG pin to the supply voltage.
An on-chip voltage regulator drives one of the AVDD pins
(pin 2) to approximately +3.4V. For proper operation,
DVDD and both AVDD pins must be connected together.
For operation with a single +3.0V to +3.6V supply voltage,
connect both the AVDD pins, DVDD, and VDD5 to the
supply voltage and connect the EN_REG pin to ground
(which disables the internal voltage regulator). If the
MAX7034 is powered from +3.0V to +3.6V, the perfor-
mance is limited to the -40°C to +105°C range.
In either supply voltage mode, bypass VDD5, DVDD, and
the pin 7 AVDD pin to AGND with 0.01μF capacitors, and
the pin 2 AVDD to AGND with a 0.1μF capacitor, all
placed as close as possible to the pins.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical printed-circuit board (PCB)
trace antenna. A nominal value for this inductor with a
50Ωinput impedance is 15nH, but is affected by the
PCB trace.
The LC tank filter connected to LNAOUT comprises L1
and C9 (see the
Typical Application Circuit
). Select L1
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where:
LTOTAL = L1 + LPARASITICS.
CTOTAL = C9 + CPARASITICS.
fLC
RF
TOTAL TOTAL
=×
1
2π
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
9
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, etc. These parasitics at high frequen-
cies cannot be ignored, and can have a dramatic effect
on the tank filter center frequency. The total parasitic
capacitance is generally between 4pF and 6pF.
Mixer
A unique feature of the MAX7034 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applica-
tions. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., fLO = fRF -
fIF). The image-rejection circuit then combines these
signals to achieve 44dB of image rejection. Low-side
injection is required due to the on-chip image-rejection
architecture. The IF output is driven by a source follow-
er biased to create a driving-point impedance of 330Ω;
this provides a good match to the off-chip 330Ωceram-
ic IF filter.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When VIRSEL
= 0V, the image rejection is tuned to 315MHz. VIRSEL =
VDVDD/2 tunes the image rejection to 375MHz, and
VIRSEL = VDVDD tunes the image rejection to 434MHz.
The IRSEL pin is internally set to VDVDD/2 (image rejec-
tion at 375MHz) when it is left unconnected, thereby
eliminating the need for an external VDVDD/2 voltage.
Phase-Locked Loop
The PLL block contains a phase detector, charge
pump, integrated loop filter, VCO, asynchronous 64x
clock divider, and crystal oscillator driver. Besides the
crystal, this PLL does not require any external compo-
nents. The VCO generates a low-side LO. The relation-
ship between the RF, IF, and crystal frequencies is
given by:
where:
M = 1 (VXTALSEL = VDVDD) or 2 (VXTALSEL = 0V)
To allow the smallest possible IF bandwidth (for best sen-
sitivity), minimize the tolerance of the reference crystal.
Intermediate Frequency and RSSI
The IF section presents a differential 330Ωload to pro-
vide matching for the off-chip ceramic filter. The six
internal AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass-
filter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
The RSSI circuit demodulates the IF by producing a DC
output proportional to the log of the IF signal level, with
a slope of approximately 14.2mV/dB.
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7034 is designed to
present a capacitance of approximately 3pF between
the XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its intended operating frequency,
introducing an error in the reference frequency.
Crystals designed to operate with higher differential
load capacitance always pull the reference frequency
higher. For example, a 4.7547MHz crystal designed to
operate with a 10pF load capacitance oscillates at
4.7563MHz with the MAX7034, causing the receiver to
be tuned to 315.1MHz rather than 315.0MHz, an error
of about 100kHz, or 320ppm. It is very important to
use a crystal with a load capacitance that is equal to
the capacitance of the MAX7034 crystal oscillator
plus PCB parasitics.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
fP is the amount the crystal frequency pulled in ppm.
CMis the motional capacitance of the crystal.
CCASE is the case capacitance.
CSPEC is the specified load capacitance.
CLOAD is the actual load capacitance.
When the crystal is loaded as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero.
fC
CCCC
PM
CASE LOAD CASE SPEC
=++
⎛
⎝
⎜⎞
⎠
⎟×
2
11
106
-
fff
M
XTAL RF IF
=×
-
32
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the exter-
nal oscillator to XTAL2 with a 1000pF capacitor. Drive
XTAL2 with a signal level of approximately 500mVP-P.
AC-couple XTAL1 to ground with a 1000pF capacitor.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the com-
bination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capaci-
tors changes the corner frequency to optimize for differ-
ent data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C7 and C6, use the following equations, along
with the coefficients in Table 1:
where fCis the desired 3dB corner frequency.
For example, to choose a Butterworth filter response
with a corner frequency of 5kHz:
Choosing standard capacitor values changes C7 to
470pF and C6 to 220pF, as shown in the
Typical
Application Circuit
.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. One input is supplied by the data
filter output. Both comparator inputs are accessible off-
chip to allow for different methods of generating the
slicing threshold, which is applied to the second com-
parator input.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capaci-
tor (C8) from DSN to DGND (Figure 2). This configura-
tion averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The values of R1 and C8
affect how fast the threshold tracks to the analog ampli-
tude. Be sure to keep the corner frequency of the RC
circuit much lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a cod-
ing scheme, such as Manchester coding, which has an
equal number of zeros and ones, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, add hysteresis to
the data slicer as shown in Figure 3.
CkkHz
pF
C
71 000
1 414 100 3 14 5 450
.
..
=
()( )()()
≈
Ω
66 1 414
4 100 3 14 5 225
.
.
=
()( )( )( )
≈
kkHz
pF
Ω
Cb
ak f
Ca
kf
C
C
7100
64 100
=
()()
()
=
()()
()
π
π
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
10
RSSI
RDF1
100kΩ
RDF2
100kΩ
C7
19
DFO
21
OPP
22
DFFB
C6
MAX7034
FILTER TYPE a b
Butterworth (Q = 0.707) 1.414 1.000
Bessel (Q = 0.577) 1.3617 0.618
Figure 1. Sallen-Key Lowpass Data Filter
Table 1. Coefficents to Calculate C7 and C6
Peak Detector
The peak-detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor pro-
vides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data-filter output voltage. For faster data slicer
response, use the circuit shown in Figure 4. For more
details on hysteresis and peak-detector applications,
refer to Maxim Application Note 3671,
Data Slicing
Techniques for UHF ASK Receivers
.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep them
as short as possible to minimize losses and radiation.
At high frequencies, trace lengths that are on the order
of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1 inch of a PCB trace adds about
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5 inch trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply pins.
Control Interface Considerations
When operating the MAX7034 with a +4.5V to +5.5V
supply voltage, the SHDN pin can be driven by a
microcontroller with either +3.0V or +5V interface logic
levels. When operating the MAX7034 with a +3.0V to
+3.6V supply, only +3.0V logic from the microcontroller
is allowed.
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
11
DATA
SLICER
R1
25
DATAOUT
20
DSN
19
DFO
23
DSP
C8
MAX7034
DATA
SLICER
R3
R2
R*
R1
25
DATAOUT
*OPTIONAL
23
DSP
19
DFO
20
DSN
C8
MAX7034
Figure 3. Generating Data Slicer Hysteresis
DATA
SLICER
25kΩ
25
DATAOUT
20
DSN
19
DFO
26
PDOUT
23
DSP
MAX7034
47nF
Figure 4. Using PDOUT for Faster Startup
Figure 2. Generating Data Slicer Threshold
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
12
Typical Application Circuit
XTAL1
R2
R3
TO/FROM µP
POWER-DOWN
DATA OUT
AVDD
LNAIN
LNASRC
AGND
AVDD
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
DVDD
Y1
IF FILTER
COMPONENT VALUES
IN TABLE 2 ***SEE THE
MIXER
SECTION. *SEE THE
PHASE-LOCKED
LOOP
SECTION. **SEE THE
VOLTAGE
REGULATOR
SECTION.
GND
IN OUT
*
**
*** C5
C10
C9
C4
C3
C2
C1
C11 C12
C15
C7
R1
C13
RF INPUT
L3
L2
L1
VDD3
VDD3
IF VDD IS
3.0V TO 3.6V
4.5V TO 5.5V
CREATED BY LDO,
AVAILABLE AT AVDD
(PIN 2)
CONNECTED TO VDD
CONNECTED TO VDD GROUNDED
THEN VDD3 IS AND EN_REG IS
X1
(SEE TABLE)
VDD
VDD
C14
C6 C8
EN_REG
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
DATAOUT
PDOUT
SHDN
XTAL2 28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD5
LNAOUT
MAX7034
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
13
Chip Information
PROCESS: CMOS
COMPONENT VALUE FOR
fRF = 433MHz
VALUE FOR
fRF = 315MHz DESCRIPTION
C1 100pF 100pF 5%
C2 Open Open ±0.1pF
C3 100pF 100pF 5%
C4 100pF 100pF 5%
C5 1500pF 1500pF 10%
C6 220pF 220pF 5%
C7 470pF 470pF 5%
C8 0.47μF 0.47μF 20%
C9 220pF 220pF 10%
C10 0.01μF 0.01μF 20%
C11 0.1μF 0.1μF 20%
C12 100pF 100pF 5%
C13 100pF 100pF 5%
C14 0.01μF 0.01μF 20%
C15 0.01μF 0.01μF 20%
L1 56nH 120nH 5% or better**
L2 15nH 15nH 5% or better**
L3 27nH 51nH 5% or better**
R1 5.1k5.1k5%
R2 Open Open —
R3 00—
X1 (÷64) 6.6128MHz* 4.7547MHz* NDK or Suntsu
X1 (÷32) 13.2256MHz* 9.5094MHz* NDK or Suntsu
Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata
Table 2. Component Values for Typical Application Circuit
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
*
Crystal frequencies shown are for
÷
64 (VXTALSEL = 0V) and
÷
32 (VXTALSEL = VDD).
**
Wire wound recommended.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TSSOP U28+1 21-0066 90-0171
MAX7034
315MHz/434MHz ASK Superheterodyne
Receiver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
14
____________________Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/08 Initial release —
1 3/09 Added /V designation to part number. 1
2 5/11
Updated Pin Description,Functional Diagram,Voltage Regulator section, Typical
Application Circuit, and Package Information; added Control Interface Considerations
section
7, 8, 11, 12, 13
3 6/12
Updated capacitors in Data Filter section; updated Table 1 to reflect correct
capacitor; updated Figures 1, 2, 3; updated Table 2 component values and wire
wound recommendation
10, 11, 13
