1. General description
The 74AUP1T58 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XOR, inverter and buffer. All input s can be connected to
VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T58 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the outpu t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2. Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceed s 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 1.5 A (maximum)
Latch-up pe rform a nc e exceeds 100 mA per JESD 78B C lass II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides par tial power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
74AUP1T58
Low-power configurable gate with voltage-level translator
Rev. 5 — 15 August 2012 Product data sheet
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 2 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature rang e Name Description Version
74AUP1T58GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP1T58GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74AUP1T58GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74AUP1T58GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74AUP1T58GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74AUP1T58GW a8
74AUP1T58GM a8
74AUP1T58GF a8
74AUP1T58GN a8
74AUP1T58GS a8
Fig 1. Logic symbol
Y
C
B
A
6
1
3
4
001aab687
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 3 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
Fig 2. Pin configuration SOT363 Fig 3. Pin configuration SOT886 Fig 4. Pin configuration SOT891 ,
SOT1115 and SOT1202
74AUP1T58
BC
GND
AY
001aah836
1
2
3
6
V
CC
5
4
74AUP1T58
GND
001aah837
B
A
VCC
C
Y
Transparent top view
2
3
1
5
4
6
74AUP1T58
GND
001aah838
B
A
VCC
C
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
B 1 data input
GND 2 ground (0 V)
A 3 data input
Y 4 data output
VCC 5 supply voltage
C 6 data input
Table 4. Function table[1]
Input Output
C B A Y
LLLL
LLHH
LHLL
LHHH
HLLH
HLHH
HHLL
HHHL
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Product data sheet Rev. 5 — 15 August 2012 4 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5. Function selec tion t a ble
Logic function Figure
2-input NAND see Figure 5
2-input NAND with both inputs inverted see Figure 8
2-input AND with inverted input see Figure 6 and 7
2-input NOR with inverted input see Figure 6 and 7
2-input OR see Figure 8
2-input OR with both inputs inverted see Figure 5
2-input XOR see Figure 9
Buffer see Figure 10
Inverter see Figure 11
Fig 5. 2-input NAND gate or 2-input OR gate with
both inputs inverted Fig 6. 2-input AND gate with input B inverted or
2-input NOR ga te with inverted C input
001aab688
BB6
YC1
52
43Y
Y
C
B
C
V
CC
001aab689
BB6
YC1
52
43Y
Y
C
B
C
VCC
Fig 7. 2-input AND gate with input C inverted or
2-input NOR gate with inverted A input Fig 8. 2-input OR gate or 2-input NAND gate with
both inputs inverted
001aab690
A
A
6
YC1
52
43Y
Y
C
A
C
V
CC
001aab691
A
6C1
52
43Y
VCC
AY
C
Y
A
C
Fig 9. 2-input XOR gate Fig 10. Buffer
001aab692
B6C1
52
43Y
VCC
Y
B
C
001aab693
A
A
6
Y
1
52
43Y
VCC
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 5 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Fig 11. Inverter
001aab694
BB6
Y
1
52
43Y
VCC
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +4.6 V
IOK output clamping current VO<0V 50 - mA
VOoutput voltage Active mode and Power-down mode [1] 0.5 +4.6 V
IOoutput current VO=0 VtoV
CC -20 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[2] - 250 mW
Table 7. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 2.3 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 6 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
10. Static characteristics
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VT+ positive-going threshold
voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V
VCC = 3.0 V to 3.6 V 0.75 - 1.16 V
VTnegative-going threshold
voltage VCC = 2.3 V to 2.7 V 0.35 - 0.60 V
VCC = 3.0 V to 3.6 V 0.50 - 0.85 V
VHhysteresis voltage (VH = VT+ VT)
VCC = 2.3 V to 2.7 V 0.23 - 0.60 V
VCC = 3.0 V to 3.6 V 0.25 - 0.56 V
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V VCC 0.1 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V - - 0.10 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.1 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.2 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V --1.2A
CIinput capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.8-pF
COoutput capacitance VO = GND; VCC = 0 V - 1.7 - pF
Tamb = 40 C to +85 C
VT+ positive-going threshold
voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V
VCC = 3.0 V to 3.6 V 0.75 - 1.19 V
VTnegative-going threshold
voltage VCC = 2.3 V to 2.7 V 0.35 - 0.60 V
VCC = 3.0 V to 3.6 V 0.50 - 0.85 V
VHhysteresis voltage (VH = VT+ VT)
VCC = 2.3 V to 2.7 V 0.10 - 0.60 V
VCC = 3.0 V to 3.6 V 0.15 - 0.56 V
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 7 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V VCC 0.1 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V - - 0.1 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.5 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V --1.5A
ICC additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A [1] --4A
VCC = 3.0 V to 3.6 V; IO = 0 A [2] --12A
Tamb = 40 C to +125 C
VT+ positive-going threshold
voltage VCC = 2.3 V to 2.7 V 0.60 - 1.10 V
VCC = 3.0 V to 3.6 V 0.75 - 1.19 V
VTnegative-going threshold
voltage VCC = 2.3 V to 2.7 V 0.33 - 0.64 V
VCC = 3.0 V to 3.6 V 0.46 - 0.85 V
VHhysteresis voltage (VH = VT+ VT)
VCC = 2.3 V to 2.7 V 0.10 - 0.60 V
VCC = 3.0 V to 3.6 V 0.15 - 0.56 V
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V VCC 0.11 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V - - 0.11 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 8 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
[1] One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2] One input at 0.45 V or 1.2 V, other input at VCC or GND.
11. Dynamic characteristics
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.75 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V --3.5A
ICC additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A [1] --7A
VCC = 3.0 V to 3.6 V; IO = 0 A [2] --22A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 2.1 3.6 5.6 0.5 6.8 7.5 ns
CL = 10 pF 2.6 4 .1 6 .2 1.0 7.9 8.7 ns
CL = 15 pF 3.0 4 .6 6 .8 1.0 8.7 9.6 ns
CL = 30 pF 4.0 5 .8 8 .1 1.5 10.8 11 .9 ns
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 1.7 3.4 5.5 0.5 6.0 6.6 ns
CL = 10 pF 2.2 4 .0 6 .2 1.0 7.1 7.9 ns
CL = 15 pF 2.6 4 .5 6 .8 1.0 7.9 8.7 ns
CL = 30 pF 3.5 5 .6 8 .1 1.5 10.0 11 .0 ns
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 1.4 3.2 5.1 0.5 5.5 6.1 ns
CL = 10 pF 1.9 3 .7 5 .8 1.0 6.5 7.2 ns
CL = 15 pF 2.2 4 .2 6 .3 1.0 7.4 8.2 ns
CL = 30 pF 3.2 5.4 7.7 1.5 9.5 10.5 ns
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 2.0 2.9 4.0 0.5 8.0 8.8 ns
CL = 10 pF 2.4 3 .5 4 .7 1.0 8.5 9.4 ns
CL = 15 pF 2.8 3.9 5.3 1.0 9.1 10.1 ns
CL = 30 pF 3.6 5.1 6.7 1.5 9.8 10.8 ns
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 9 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 1.6 2.8 4.4 0.5 5.3 5.9 ns
CL = 10 pF 2.1 3 .4 5 .1 1.0 6.1 6.8 ns
CL = 15 pF 2.4 3 .9 5 .6 1.0 6.8 7.5 ns
CL = 30 pF 3.4 5 .0 7 .0 1.5 8.5 9.4 ns
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
tpd propagation delay A, B, C to Y; see Figure 12 [2]
CL = 5 pF 1.3 2.8 4.4 0.5 4.7 5.2 ns
CL = 10 pF 1.7 3 .3 5 .1 1.0 5.7 6.3 ns
CL = 15 pF 2.1 3 .8 5 .7 1.0 6.2 6.9 ns
CL = 30 pF 3.1 4 .9 7 .0 1.5 7.8 8.6 ns
Tamb = 25 C
CPD power dissipation
capacitance fi = 1 MHz; VI= GND to VCC [3]
VCC = 2.3 V to 2.7 V - 3.6 - - - - pF
VCC = 3.0 V to 3.6 V - 4.3 - - - - pF
Table 9. Dynamic characteristics …continu ed
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ[1] Max Min Max
(85 C) Max
(125 C)
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 10 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
12. Waveforms
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Inp ut A, B and C to output Y propagation delay times
Y output
A, B, C input
Y output
GND
VI
VOH
VOH
VOL
VOL
VMVM
VMVM
VMVM
tPLH
tPLH
tPHL
tPHL
001aab593
Table 10. Measurement points
Supply voltage Output Input
VCC VMVMVItr = tf
2.3 V to 3.6 V 0.5 VCC 0.5 VI1.65 V to 3.6 V 3.0 ns
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 11 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
001aac521
DUT
RT
VIVO
V
EXT
V
CC
RL
5 kΩ
CL
G
Table 11. Test data
Supply voltage Load VEXT
VCC CLRL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
2.3 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 Mopen GND 2 VCC
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Product data sheet Rev. 5 — 15 August 2012 12 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
13. Package outline
Fig 14. Package outline SOT363 (SC-88)
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Product data sheet Rev. 5 — 15 August 2012 13 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 15. Package outline SOT886 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1b
0.25
0.20
0.17
DEee
1
0.5
LL
1
terminal 1
index area
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 14 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 16. Package outline SOT891 (XSON6)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT891
SOT891
05-04-06
07-05-15
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm 0.20
0.12 1.05
0.95 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.350.55
A
max
0.5 0.04
1
6
2
5
3
4
A
6×
(1)
4×
(1)
Note
1. Can be visible in some manufacturing processes.
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 15 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 17. Package outline SOT1 115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 16 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
Fig 18. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 17 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
14. Abbreviations
15. Revision history
Table 12. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP1T58 v.5 20120815 Product data sheet - 74AUP1T58 v.4
Modifications: •Package outline drawing of SOT886 (Figure 15) modified.
74AUP1T58 v.4 20111128 Product data sheet - 74AUP1T58 v.3
74AUP1T58 v.3 20101018 Product data sheet - 74AUP1T58 v.2
74AUP1T58 v.2 20090929 Product data sheet - 74AUP1T58 v.1
74AUP1T58 v.1 20080306 Product data sheet - -
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 18 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specif ication for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 19 of 20
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims result ing from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AUP1T58
Low-power configurable gate with voltage-level translator
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 August 2012
Document identifier : 7 4AU P1 T 58
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
17 Contact information. . . . . . . . . . . . . . . . . . . . . 19
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20