1024-bits Serial Electrically Erasable PROM AM93LC46
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A2 Oct 20, 2003
1/11
ATC
Features
•State-of-the-art architecture
- Non-volatile data storage
- Operating voltage Vcc: 2.7~ 5.5V
- Full TTL compatible inputs and outputs
- Auto increment read for efficient data dump
• Hardware and software write protection
- Defaults to write-disabled state at power up
- Software instructions for write-enable/disable
- Vcc level verification before self-timed
programming cycle.
• Advanced low voltage CMOS EEPROM
technology
• Versatile, easy-to-use interface
- Self-timed programming cycle
- Automatic erase-before-write
- Programming status Indicator
- Word and chip erasable
- Stop SK anytime for power savings
• Durability and reliability
- 40 year data retention
- Minimum of 1M write cycles
- Unlimited read cycles
- ESD protection
Connection Diagram
1
2
3
4
8
7
6
5
VCC
GND
NC
CS
SK
PDIP-8L / SOP-8L
DO
DI
1
2
3
4
8
7
6
5
VCC GND
NC
CS
SK
Rotated SOP-8L
DO
DI
NC
NC
General Description
The AM93LC46 is a 1024-bit, non-volatile, serial
EEPROM. It is manufactured by using ATC's
advanced CMOS EEPROM technology. The
AM93LC46 provides efficient non-volatile read/write
memory arranged as 64 registers of 16 bits each.
Seven 9-bit instructions control the operation of the
device, which includes read, write, and write
enable/disable functions. The data out pin (DO)
indicates the status of the device during the
self-timed non-volatile programming cycle.
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the WRITE ENABLE state and proper Vcc
operation range is the WRITE instruction accepted
and thus to protect against inadvertent writes. Data is
written in 16 bits per write instruction into the
selected register. If Chip Select (CS) is brought HIGH
after initiation of the write cycle, the Data Output (DO)
pin will indicate the READY/BUSY status of the chip.
The AM93LC46 is available in space-saving 8-lead
PDIP, 8-lead SOP and rotated 8-lead SOP package.
Pin Assignments
Name Description
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
NC No Connection
Ordering Information
Type Package
46:1K
Temp. grade
AM 93 LC 46 XXX X
Packing
Blank : Tube
A : Taping
Operating Voltage
LC : 2.7~5.5V, CMOS Blank: C70~C0
oo
+
I : C85~C40
oo
+-
V: C125~C40
oo
+-
S : SOP-8L
GS: SOP-8L, G type
N : PDIP-8L
TS: TSSOP-8L
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
2/11
ATC
Block Diagrams
INSTRUCTION
REGISTER
(9 BITS)
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
DATA
REGISTER
(16 BITS)
ADDRESS
REGISTER
V
CC
RANGE
DETECTOR
WRITE
ENABLE
DUMMY
BIT
R/W AMPS
1 OF 64
DECODER
HIGH
VOLTAGE
GENERATOR
EEPROM
ARRAY
(64X16)
DI
CS
SK
DO
Absolute Maximum Ratings
Characteristics Symbol Values Unit
Storage Temperature TS -65 to + 125 °C
Voltage with Respect to Ground -0.3 to + 6.5 V
NOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias Values Unit
AM93LC46 0 to + 70 °C
AM93LC46I -40 to + 85 °C
AM93LC46V -40 to +125 °C
DC Electrical Characteristics (Vcc =2.7~5.5V, Ta = 25oC , unless otherwise noted)
Parameter Symbol Conditions Min Max Units
Operating current** ICC CS=VIH, SK=1MHz CMOS input levels 3 mA
Standby current ISB CS=DI=SK=0V 10 µA
Input leakage IIL V
IN = 0V to VCC(CS,SK,DI) -1 1 µA
Output leakage IOL V
OUT = 0V to VCC, CS=0V -1 1 µA
VCC = 3V + 10% -0.1 0.15 VCC
Input low voltage** VIL VCC = 5V + 10% -0.1 0.8 V
VCC = 3V + 10% 0.8 VCC V
CC +0.2
Input high voltage** VIH VCC = 5V + 10% 2 VCC +0.2 V
Output low voltage VOL1 I
OL = 2.1mA TTL, VCC=5V + 10% 0.4 V
Output high voltage VOH1 I
OH = -400uA TTL, VCC=5V + 10% 2.4 V
Output low voltage IOL = 10uA CMOS 0.2 V
Output high voltage VOL2 IOH = -10uA CMOS VCC -0.2 V
Note **: ICC , VIL min and VIH max are for reference only and are not tested
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
3/11
ATC
AC Electrical Characteristics (Vcc = 2.7V ~ 5.5V, Ta = 25oC , unless otherwise noted)
Parameter Symbol Conditions Min Max Units
SK Clock Frequency FSK 0 1 MHz
SK High Time TSKH 250 ns
SK Low Time TSKL 250 ns
Minimum CS Low Time TCS 250 ns
CS Setup Time TCSS Relative to SK 50 ns
DI Setup Time TDIS Relative to SK 100 ns
CS Hold Time TcSH Relative to SK 0 ns
DI Hold Time TDIH Relative to SK 100 ns
Output Delay to "1" TpD1 AC Test 500 ns
Output Delay to "0" TpD0 AC Test 500 ns
CS to Status Valid TSV AC Test CL = 100pF 500 ns
CS to DO in 3-state TdF CS = VIL 100 ns
Write Cycle Time TwP 10 ms
5V, 25ºC, Page Mode Endurance** 1M Write cycles
Note** : The parameter is characterized and isn’t 100% tested.
FIGURE 1. AC TEST CONDITIONS
632 ohm
DO
1.247V
(1 TTL Gate Load)
100PF
Instruction Set
Instruction Start Bit OP Code Address Input Data
READ 1 10 (A5 - A0)
WEN (Write Enable) 1 00 11XXXX
WRITE 1 01 (A5 - A0) D15-D0*
WRALL (Write All Registers) 1 00 01XXXX D15-D0*
WDS (Write Disable) 1 00 00XXXX
ERASE 1 11 (A5 - A0)
ERAL (Erase All Registers) 1 00 10XXXX
Note* : If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word)
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
4/11
ATC
Pin Capacitance ** (Ta=25°C , f=1MHz )
Symbol Parameter Max Units
COUT Output capacitance 5 pF
CIN Input capacitance 5 pF
Note ** :The parameter is characterized and isn’t 100% tested.
Functional Descriptions
Applications
The AM93LC46 is ideal for high volume applications
requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package.
Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings
such as LAN cards, monitors and MODEM.
Endurance and Data Retention
The AM93LC46 is designed for applications
requiring up to 1000K programming cycles (WRITE,
WRALL, EARSE and ERALL). It provides 40 years
of secure data retention without power after the
execution of 1000K programming cycles.
Device Operation
The AM93LC46 is controlled by seven 9-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (6 bits), and data, if appropriate.
The clock signal (SK) may be halted at any time and
the AM93LC46 will remain in its last state. This
allows full static flexibility and maximum power
conservation.
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into a
16-bit serial shift register. (Please note that one
logical "0" bit precedes the actual 16-bit output data
string.) The output on DO changes during the rising
edge transitions of SK. (Shown in Figure 3)
Auto Increment Read Operations
Sequential read is possible, since the AM93LC46
has been designed to output a continuous stream of
memory content in response to a single read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 16 bits of the addressed
word have been clocked out, the data in
consecutively higher address locations ( the address
"000000" is assumed as the higher address of
"111111") is output. The address will wrap around
continuously with CS high until the chip select (CS)
control pin is brought low. This allows for single
instruction data dumps to be executed with a
minimum of firmware overhead.
Write Enable (WEN)
Before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done, the WRITE
ENABLE (WEN) instruction must be executed first.
When Vcc is applied, this device powers up in the
WRITE DISABLE state. The device then remains in
a WRITE DISABLE state until a WEN instruction is
executed. Thereafter the device remains enabled
until a WDS instruction is executed or until Vcc is
removed. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 4.)
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all
programming capabilities. This protects the entire
part against accidental modification of data until a
WEN instruction is executed. (When Vcc is applied,
this part powers up in the WRITE DISABLE state.)
To protect data, a WDS instruction should be
executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 5.)
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev.A2 Oct 20, 2003
5/11
ATC
Functional Descriptions (Continued)
Write (WRITE)
The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data
bit has been applied to DI, and before the next rising
edge of SK, CS must be brought LOW. The falling
edge of CS initiates the self-timed programming
cycle.
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6.)
Note: The combination of CS HIGH, DI HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
Before a WRITE instruction can be executed, the
device must be in the WRITE ENABLE (WEN) state.
Write All (WRALL)
The Write All (WRALL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRALL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7.)
As with the WRITE instruction, if CS is brought
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7.)
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to indicate
the READ/BUSY status of the chip. To explain this,
a logical "0" indicates the programming is still in
progress while a logical "1" indicates the erase cycle
is complete and the part is ready for another
instruction. (Shown in Figure 8.)
Erase All (ERALL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (Shown in
Figure 9.)
Security Consideration
To protect the entire part against accidental
modification of data, each programming instruction
(WRITE, WRALL, ERASE, and ERALL) must satisfy
two conditions before user initiate self-timed
programming cycle (the falling edge of CS). One is
that the AM93LC46 is at WEN status. The other is
that Vcc value must exceed a lock-out value which
can be adjusted by ANALOG TECHNOLOGY INC.
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
6/11
ATC
Timing Diagram (1)
FIGURE 2. SYNCHRONOUS DATA TIMING
T
t
SKH
t
SKL
t
CSH
t
CSS
CS
SK
DI
DO(READ)
DO(WRITE)
(WRALL)
(ERASE)
(ERALL)
t
SV
STATUS VALID
t
DF
t
DF
t
PD1
t
PDO
t
DIS
t
DIH
FIGURE 3. DATA READ CYCLE TIMING
CS
SK
+
AOA5
0
11
DI
D15 DO
O
DO
TRI-STATE
+For all instructions, SK cycles before start bit don't care.
*Address Pointer Cycle to the Next Register.
*
t
CS
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
7/11
ATC
Timing Diagram (2)
DO = TRI-STATE
**A3~A0 don't care.
FIGURE 4. WRITE ENABLE(WEN) CYCLE TIMING
t
CS
CS
SK
DI 1 10 01 X- - - - - - - - - - - X
**
FIGURE 5. WRITE DISABLE(WDS) CYCLE TIMING
DO = TRI-STATE
**A3~A0 don't care.
CS
t
CS
SK
DI 10 000
X- - - - -- - - - X
**
FIGURE 6. WRITE(WRITE) CYCLE TIMING
t
CS
CS
DO
TRI-STATE
t
SV
t
DF
BUSY
READY
t
WP
SK
DI
101A5 AO D15 DO
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
8/11
ATC
Timing Diagram (3)
t
CS
CS
SK
BUSY READY
DO
TRI-STATE
t
SV
t
WP
**A3~A0 don't care.
FIGURE 7. WRITE ALL(WRALL) CYCLE TIMING
DI
100 0 1D15 DOX- - - - - - - - - - - -X
**
FIGURE 8. ERASE(ERASE) CYCLE TIMING
SK
DI
DO
TRI-STATE
111 A5 AO
t
SV
BUSY READY
t
WP
t
DF
t
CS
CS
FIGURE 9. ERASE ALL(ERALL) CYCLE TIMING
t
CS
CS
SK
DO
TRI-STATE
t
SV
t
DF
t
WP
BUSY READY
**A3~A0 don't care.
DI 100 1 X- - - - - - - - - X
0
**
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
9/11
ATC
Package Diagrams
(1) Plastic Dual-in-line Package: PDIP-8L
E1
D
7(4X)
AL
A2A1
B2
B1
B
e
S
15 (4X)
E
C
eB
E-PIN O0.118 inch
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
Dimensions in millimeters Dimensions in inches
Symbol Min. Nom. Max. Min. Nom. Max.
A - - 5.33 - - 0.210
A1 0.38 - - 0.015 - -
A2 3.1 3.30 3.5 0.122 0.130 0.138
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.4 1.52 1.65 0.055 0.060 0.065
B2 0.81 0.99 1.14 0.032 0.039 0.045
C 0.20 0.25 0.36 0.008 0.010 0.014
D 9.02 9.27 9.53 0.355 0.365 0.375
E 7.62 7.94 8.26 0.300 0.313 0.325
E1 6.15 6.35 6.55 0.242 0.250 0.258
e - 2.54 - - 0.100 -
L 2.92 3.3 3.81 0.115 0.130 0.150
eB 8.38 8.89 9.40 0.330 0.350 0.370
S 0.71 0.84 0.97 0.028 0.033 0.038
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
10/11
ATC
(2) JEDEC Small Outline Package: SOP-8L
VIEW "A"
L
H
E
C
VIEW "A"
A
A2
A1
B
e
D
7(4X) 0.015x45 7(4X)
y
Dimensions In Millimeters Dimensions In Inches
Symbol Min. Nom. Max. Min. Nom. Max.
A 1.40 1.60 1.75 0.055 0.063 0.069
A1 0.10 - 0.25 0.040 - 0.100
A2 1.30 1.45 1.50 0.051 0.057 0.059
B 0.33 0.41 0.51 0.013 0.016 0.020
C 0.19 0.20 0.25 0.0075 0.008 0.010
D 4.80 5.05 5.30 0.189 0.199 0.209
E 3.70 3.90 4.10 0.146 0.154 0.161
e - 1.27 - - 0.050 -
H 5.79 5.99 6.20 0.228 0.236 0.244
L 0.38 0.71 1.27 0.015 0.028 0.050
y - - 0.10 - - 0.004
θ 0O - 8O 0
O - 8O
1024-bits Serial Electrically Erasable PROM AM93LC46
Anachip Corp.
www.anachip.com.tw Rev. A2 Oct 20, 2003
11/11
ATC
(3)Package Type: TSSOP-8L
A
E
E1
b
y
e
C
DETAIL A
DETAIL A
L 1
L
E1 L1
A2
A1
D
PIN 1 INDICATOR
ψ
0.70 mm
SURFACE POLISHED
Dimensions In Millimeters Dimensions In Inches
Symbol Min. Nom. Max. Min. Nom. Max.
A 1.05 1.10 1.20 0.041 0.043 0.047
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 - 1.00 1.05 - 0.039 0.041
b 0.20 0.25 0.28 0.008 0.01 0.011
C - 0.13 - - 0.005 -
D 2.90 3.05 3.10 0.114 0.12 0.122
E 6.20 6.40 6.60 0.244 0.252 0.26
E1 4.30 4.40 4.50 0.169 0.173 0.177
e - 0.65 - - 0.026 -
L 0.50 0.60 0.70 0.02 0.024 0.028
L1 0.90 1.00 1.10 0.035 0.039 0.043
y - - 0.10 - - 0.004
θ 0O 4
O 8
O 0
O 4
O 8
O
Marking Information
Top view
Part Number (X:ID Code)
Blank : PDIP-8L & SOP-8L (Commercial)
I : PDIP-8L & SOP-8L (Industrial)
V : PDIP-8L & SOP-8L (Automotive)
G : Rotated SOP-8L (Commercial)
B : Rotated SOP-8L (Industrial)
D : Rotated SOP-8L (Automotive)
ATC
93LC46X
YYWW X
Logo
Date & ID Code
YY : Year
WW : Week
X: Internal
