PTN3300BHF,518 - NXP Semiconductors / Philips Semiconductors

1. General description

The PTN3300B is a high-speed level shifter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI and HDMI compliant open-drain

current-steering differential output signals, up to 2.25 Gbit/s per lane. Each of these lanes

provides a level-shifting differential buffer to translate from low-swing AC-coupled

differential signaling on the source side, to TMDS-type DC-coupled differential

current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the

PTN3300B provides a single-ended active buffer for voltage translation of the HPD signal

from 5 V on the sink side to 3.3 V on the source side and provides a channel for level

shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V

source side and 5 V sink side. The DDC channel is implemented using pass gate

technology allowing level shifting as well as disablement (isolation between source and

sink) of the clock and data lines.

The low-swing AC-coupled differential input signals to the PTN3300B typically come from

a display source with multi-mode I/O, which supports multiple display standards, e.g.,

DisplayPort, HDMI and DVI. While the input differential signals are conﬁgured to carry DVI

or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0

or HDMI v1.3a speciﬁcation. By using PTN3300B, chip set vendors are able to implement

such reconﬁgurable I/Os on multi-mode display source devices, allowing the support of

multiple display standards while keeping the number of chip set I/O pins low. See

Figure 1.

The PTN3300B main high-speed differential lanes feature low-swing self-biasing

differential inputs which are compliant to the electrical speciﬁcations of

DisplayPort

Standard v1.1

and/or

PCI Express Standard v1.1

, and open-drain current-steering

differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical speciﬁcations. The

PTN3300B also supports power-saving modes in order to minimize current consumption

when no display is active or connected.

The PTN3300B supports level translation functions and features supporting both DVI and

HDMI. A derivative, PTN3300A, is available that is identical to the PTN3300B except that

the HPD_SOURCE_N output is the inverting function of input HPD_SINK, level shifted to

1.1 V. For a fully-featured HDMI/DVI level shifter function that supports active buffering of

the DDC lines and HDMI dongle detect, the PTN3301 should be used.

PTN3300B is powered from a single 3.3 V power supply consuming a small amount of

power (120 mW typical) and is offered in two different 48-terminal HWQFN packages, one

laminate based (no terminals visible from edge of the package), and one leadframe-based

(terminals visible from edge of the package).

PTN3300B

DVI and HDMI level shifter

Rev. 01 — 8 July 2008 Product data sheet

Product data sheet Rev. 01 — 8 July 2008 2 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

002aad681

OUT_D1−

OUT_D1+

IN_D1−

IN_D1+

HPD_SOURCE HPD_SINK

SCL_SINK

SDA_SINK

DDC_EN

(0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3300B

OE_N

DVI CONNECTOR

5 V

0 V to 5 V0 V to 3.3 V

3.3 V

AC-coupled

differential pair

clock

CLOCK LANE

DATA LANE

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

TMDS

clock

pattern

MULTI-MODE DISPLAY SOURCE

TMDS

coded

data

TMDS

coded

data

TMDS

coded

data

PCIe PHY ELECTRICAL

CONFIGURATION

DDC I/O

(I2C-bus)

PCIe

output buffer

reconfigurable I/Os

PCIe

output buffer

PCIe

output buffer

PCIe

output buffer

Product data sheet Rev. 01 — 8 July 2008 3 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

2. Features

2.1 High-speed TMDS level shifting

nConverts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI

compliant open-drain current-steering differential output signals

nTMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)

nIntegrated 50 Ω termination resistors for self-biasing differential inputs

nBack-current safe outputs to disallow current when device power is off and monitor is

nDisable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

nIntegrated DDC level shifting (3.3 V source to 5 V sink side)

n0 Hz to 400 kHz clock frequency

nBack-power safe to disallow backdrive current when power is off or when DDC is not

enabled

2.3 HPD level shifting

nHPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or

from 5 V on the sink side to 3.3 V on the source side

nIntegrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

2.4 General

nPower supply 3.3 V ±10 %

nESD resilience to 3.5 kV HBM, 1 kV CDM

nPower-saving modes by source side disablement (using output enable) as well as

sink side detection (using HPD)

nBack-current-safe design on all sink side terminals

nTransparent operation: no re-timing or software conﬁguration required

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

PTN3300BHF HWQFN48R plastic thermal enhanced very very thin quad ﬂat package; no leads;

48 terminals; resin based; body 7 ×7×0.7 mm SOT1031-2

PTN3300BHF2 HWQFN48 plastic thermal enhanced very very thin quad ﬂat package; no leads;

48 terminals; body 7 ×7×0.65 mm SOT1074-1

Product data sheet Rev. 01 — 8 July 2008 4 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

4. Functional diagram

Fig 2. Functional diagram of PTN3300B

002aad682

OUT_D1−

OUT_D1+

input bias

50 Ω50 Ω

IN_D1−

IN_D1+

HPD level shifter

HPD_SOURCE

(0 V to 3.3 V) HPD_SINK

(0 V to 5 V)

200 kΩ

SCL_SINK

SDA_SINK

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3300B

OE_N

enable

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

enable

DDC level shifter

Product data sheet Rev. 01 — 8 July 2008 5 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

5. Pinning information

5.1 Pinning

HWQFN48R package supply ground is connected to both GND pins and exposed center pad.

GND pins must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 3. Pin conﬁguration for HWQFN48R

OUT_D4+

OUT_D4−

VDD

OUT_D3+

OUT_D3−

GND

OUT_D2+

OUT_D2−

VDD

OUT_D1+

OUT_D1−

GND

VDD

GND

n.c.

SCL_SOURCE

SDA_SOURCE

HPD_SOURCE

REXT

GND

n.c.

VDD

GND

IN_D4+

IN_D4−

VDD

IN_D3+

IN_D3−

GND

IN_D2+

IN_D2−

VDD

IN_D1+

IN_D1−

GND

002aad683

OE_N

VDD

GND

SCL_SINK

SDA_SINK

HPD_SINK

GND

DDC_EN

VDD

n.c.

GND

PTN3300BHF

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

136

terminal 1

index area

Transparent top view

Product data sheet Rev. 01 — 8 July 2008 6 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

5.2 Pin description

HWQFN48 package supply ground is connected to both GND pins and exposed center pad. GND

pins must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 4. Pin conﬁguration for HWQFN48

OUT_D4+

OUT_D4−

VDD

OUT_D3+

OUT_D3−

GND

OUT_D2+

OUT_D2−

VDD

OUT_D1+

OUT_D1−

GND

VDD

GND

n.c.

SCL_SOURCE

SDA_SOURCE

HPD_SOURCE

REXT

GND

n.c.

VDD

GND

OE_N

VDD

GND

SCL_SINK

SDA_SINK

HPD_SINK

GND

DDC_EN

VDD

n.c.

GND

IN_D4+

IN_D4−

VDD

IN_D3+

IN_D3−

GND

IN_D2+

IN_D2−

VDD

IN_D1+

IN_D1−

GND

002aad684

Transparent top view

PTN3300BHF2

terminal 1

index area

Table 2. Pin description

Symbol Pin Type Description

OE_N, IN_Dx and OUT_Dx signals

OE_N 25 3.3 V low-voltage

CMOS

single-ended input

Output Enable and power saving function for high-speed differential level

shifter path.

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero output current

When OE_N = LOW:

IN_Dx termination = 50 Ω

OUT_Dx outputs = active

IN_D4+ 48 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D4+ makes a differential pair with IN_D4−. The input to this

pin must be AC coupled externally.

IN_D4−47 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D4−makes a differential pair with IN_D4+. The input to this

pin must be AC coupled externally.

IN_D3+ 45 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D3+ makes a differential pair with IN_D3−. The input to this

pin must be AC coupled externally.

Product data sheet Rev. 01 — 8 July 2008 7 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

IN_D3−44 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D3−makes a differential pair with IN_D3+. The input to this

pin must be AC coupled externally.

IN_D2+ 42 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D2+ makes a differential pair with IN_D2−. The input to this

pin must be AC coupled externally.

IN_D2−41 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D2−makes a differential pair with IN_D2+. The input to this

pin must be AC coupled externally.

IN_D1+ 39 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D1+ makes a differential pair with IN_D1−. The input to this

pin must be AC coupled externally.

IN_D1−38 Self-biasing

differential input Low-swing differential input from display source with PCI Express electrical

signalling. IN_D1−makes a differential pair with IN_D1+. The input to this

pin must be AC coupled externally.

OUT_D4+ 13 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D4+ makes a differential pair

with OUT_D4−. OUT_D4+ is in phase with IN_D4+.

OUT_D4−14 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D4− makes a differential pair

with OUT_D4+. OUT_D4− is in phase with IN_D4−.

OUT_D3+ 16 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D3+ makes a differential pair

with OUT_D3−. OUT_D3+ is in phase with IN_D3+.

OUT_D3−17 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D3− makes a differential pair

with OUT_D3+. OUT_D3− is in phase with IN_D3−.

OUT_D2+ 19 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D2+ makes a differential pair

with OUT_D2−. OUT_D2+ is in phase with IN_D2+.

OUT_D2−20 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D2− makes a differential pair

with OUT_D2+. OUT_D2− is in phase with IN_D2−.

OUT_D1+ 22 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D1+ makes a differential pair

with OUT_D1−. OUT_D1+ is in phase with IN_D1+.

OUT_D1−23 TMDS differential

output DVI or HDMI compliant TMDS output. OUT_D1− makes a differential pair

with OUT_D1+. OUT_D1− is in phase with IN_D1−.

HPD and DDC signals

HPD_SINK 30 5 V CMOS

single-ended input 0 V to 5 V (nominal) input signal. This signal comes from the DVI or HDMI

sink. A HIGH value indicates that the DVI or HDMI sink is connected; a

LOW value indicates that the sink is disconnected. HPD_SINK is pulled

down by an integrated 200 kΩpull-down resistor. A LOW input level on this

pin will automatically put the PTN3300B in Standby mode for lowest power

consumption.

HPD_SOURCE 7 3.3 V CMOS

single-ended output 0 V to 3.3 V (nominal) output signal. This is the level-shifted, non-inverted

version of the HPD_SINK signal.

SCL_SOURCE 9 single-ended 3.3 V

DDC I/O pass gate 3.3 V source side DDC clock I/O. Pulled up by external termination to 3.3 V.

SDA_SOURCE 8 single-ended 3.3 V

DDC I/O pass gate 3.3 V source side DDC data I/O. Pulled up by external termination to 3.3 V.

SCL_SINK 28 single-ended 5 V

DDC I/O pass gate 5 V sink side DDC clock I/O. Pulled up by external termination to 5 V.

SDA_SINK 29 single-ended 5 V

DDC I/O pass gate 5 V sink side DDC data I/O. Pulled up by external termination to 5 V.

Table 2. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 01 — 8 July 2008 8 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

[1] HWQFN48R and HWQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be

connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed

pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the

board, thermal vias need to be incorporated in the PCB in the thermal pad region.

DDC_EN 32 3.3 V CMOS input Enables or disables the DDC level shifter path.

When DDC_EN = LOW, DDC level shifter is disabled.

When DDC_EN = HIGH, DDC level shifter are enabled.

Note that HPD_SINK needs to be HIGH for the DDC channel to be enabled.

Supply and ground

VDD 2, 11,

15, 21,

26, 33,

40, 46

3.3 V DC supply Supply voltage; 3.3 V ±10 %.

GND[1] 1, 5,

12, 18,

24, 27,

31, 36,

37, 43

ground Supply ground. All ground pins must be connected to ground for proper

operation.

Feature control signals

REXT 6 analog I/O Current sense port used to provide an accurate current reference for the

differential outputs OUT_Dx. For best output voltage swing accuracy, use of

a 10 kΩ resistor (1 % tolerance) from this terminal to GND is

recommended. May also be left open-circuit or tied to either VDD or GND.

See Section 6.2 for details.

Miscellaneous

n.c. 3, 4,

10, 34,

no connection to

the die Not connected. May be left open-circuit or tied to GND or VDD either directly

or via a resistor.

Table 2. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 01 — 8 July 2008 9 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

6. Functional description

Refer to Figure 2 “Functional diagram of PTN3300B”.

The PTN3300B level shifts four lanes of low-swing AC-coupled differential input signals to

DVI or HDMI compliant open-drain current-steering differential output signals, up to

2.25 Gbit/s per lane. It has integrated 50 Ω termination resistors for AC-coupled

differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs

and outputs, thereby minimizing power consumption. The TMDS outputs are back-power

safe to disallow current ﬂow from a powered sink while the PTN3300B is unpowered.

The PTN3300B's DDC level-shifter allows 3.3 V source side termination and 5 V sink side

termination. The PTN3300B offers the back-power safe feature to disallow backdrive

current from the DDC clock and data lines when power is off or when DDC is not enabled.

An enable signal DDC_EN enables the level shifter block.

The PTN3300B also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side. PTN3300B also

automatically goes into low power mode when the sink is not connected (HPD_SINK is

LOW).

The PTN3300B does not re-time any data. It contains no state machines. No inputs or

outputs of the device are latched or clocked. Because the PTN3300B acts as a

transparent level shifter, no reset is required.

6.1 Flexible and power-efﬁcient enable and disable features

PTN3300B offers different ways to enable or disable functionality, using the Output Enable

(OE_N), Hot Plug Detect (HPD_SINK) and DDC Enable (DDC_EN) inputs. Whenever the

PTN3300B is disabled using HPD_SINK or OE_N, the device will be in Standby mode and

power consumption will be minimal; otherwise the PTN3300B will be in Active mode and

power consumption will be nominal. These three inputs each affect the operation of

PTN3300B differently: OE_N affects only the TMDS channels, DDC_EN affects only the

DDC channel, and HPD_SINK affects both TMDS and DDC channels. The following

sections and truth table describe their detailed operation.

6.1.1 Hot plug detect with power-saving feature

The HPD channel of PTN3300B in fact has a dual function: as a level-shifting buffer to

pass the HPD logic signal from the display sink device (via input HPD_SINK) on to the

display source device (via output HPD_SOURCE), as well as a detection input for

determining when the PTN3300B will go into Standby mode to save power consumption.

The PTN3300B will automatically disable both the TMDS and DDC channels when the

HPD input indicates that no display is connected (indicated by HPD_SINK = LOW), upon

which power consumption is minimized. The power-down behavior in HPD power-saving

mode is identical to the active disablement using both the OE_N input and the DDC_EN

input.

The logic state of the HPD_SOURCE output always follows the logic state of the

HPD_SINK input, regardless of whether the device is in Active or Standby mode.

Product data sheet Rev. 01 — 8 July 2008 10 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

6.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional provided that HPD_SINK input is HIGH. Input termination resistors are enabled

and the internal bias circuits are turned on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Internal bias circuits for the differential inputs and

outputs are turned off. Power consumption is minimized.

Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE

output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS

channel.

6.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change

state during an I2C-bus operation. Note that disabling DDC_EN during a bus operation will

hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I2C-bus

operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2C-bus

speciﬁcation).

6.1.4 Enable/disable truth table

[1] A LOW level on input HPD_SINK disables both the TMDS and DDC channels.

[2] A HIGH level on input OE_N disables only the TMDS channels.

[3] A LOW level on input DDC_EN disables only the DDC channel.

[4] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[5] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[6] The HPD_SOURCE output logic state follows the HPD_SINK input logic state regardless of Active or Standby mode.

Table 3. HPD_SINK, OE_N and DDC_EN enabling and power saving functions truth table

Inputs Channels Mode

HPD_SINK

[1] OE_N

[2] DDC_EN

[3] IN_Dx OUT_Dx[4] DDC[5] HPD_SOURCE

[6]

LOW X X high-impedance high-impedance;

zero output current high-impedance LOW Standby

HIGH LOW LOW 50 Ω termination

to VRX(bias)

enabled high-impedance HIGH Active

HIGH LOW HIGH 50 Ω termination

to VRX(bias)

enabled enabled HIGH Active

HIGH HIGH LOW high-impedance high-impedance;

zero output current high-impedance HIGH Standby

HIGH HIGH HIGH high-impedance high-impedance;

zero output current enabled HIGH Standby

with DDC

channel

enabled

Product data sheet Rev. 01 — 8 July 2008 11 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

6.2 Analog current reference

The REXT pin (pin 6) is an analog current sense port used to provide an accurate current

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use

of a 10 kΩ resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 kΩ±1 % resistor is not used, this pin can be left open-circuit, or

connected to GND or VDD, either directly (0 Ω) or using pull-up or pull-down resistors of

value less than 10 kΩ. In any of these cases, the output will function normally but at

reduced accuracy over voltage and temperature of the following parameters: output levels

(VOL), differential output voltage swing, and rise and fall time accuracy.

6.3 Backdrive current protection

The PTN3300B is designed for backdrive prevention on all sink side terminals. This

supports user scenarios where the display is connected and powered, but the PTN3300B

is unpowered. In these cases, the PTN3300B will sink no more than a negligible amount

of leakage current, and will block the display (sink) termination network from driving the

power supply of the PTN3300B or that of the inactive DVI or HDMI source.

Product data sheet Rev. 01 — 8 July 2008 12 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

7. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

8. Recommended operating conditions

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 6.2.

8.1 Current consumption

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.3 +4.6 V

VIinput voltage 3.3 V CMOS inputs −0.3 VDD + 0.5 V

5.0 V CMOS inputs −0.3 6.0 V

Tstg storage temperature −65 +150 °C

Vesd electrostatic discharge

voltage HBM [1] - 4000 V

CDM [2] - 1000 V

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VIinput voltage 3.3 V CMOS inputs 0 - 3.6 V

5.0 V CMOS inputs 0 - 5.5 V

VI(AV) average input voltage DC value at IN_Dx+,

IN_Dx− inputs [1] -0-V

Rref(ext) external reference

resistance connected between pin

REXT (pin 6) and GND;

±1%

[2] -10-kΩ

Tamb ambient temperature operating in free air −40 - +85 °C

Table 6. Current consumption

Symbol Parameter Conditions Min Typ Max Unit

IDD supply current OE_N = 0 and HPD_SINK = 1;

Active mode 10 35 50 mA

OE_N = 1 or HPD_SINK = 0;

Standby mode 0250µA

Product data sheet Rev. 01 — 8 July 2008 13 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

9. Characteristics

9.1 Differential inputs

[1] UI (unit interval) = tbit (bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.25 Gbit/s per lane. Nominal UI at

2.25 Gbit/s = 444 ps. 400 ps = 444 ps −10 %.

[3] VRX_DIFFp-p = 2 ×|VRX_D+ −VRX_D−|. Applies to IN_Dx signals.

[4] Vi(cm)M(AC) = |VRX_D+ +V

RX_D−|/2−VRX(cm).

VRX(cm) = DC (average) of |VRX_D+ +V

RX_D−|/2.

[5] Intended to limit power-up stress on source side PCIe output buffers.

[6] Differential inputs will switch to a high-impedance state when OE_N is LOW.

Table 7. Differential input characteristics for IN_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

UI unit interval[1] [2] 400 - 4000 ps

VRX_DIFFp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 V

TRX_EYE receiver eye time minimum eye width at

IN_Dx input pair 0.8 - - UI

Vi(cm)M(AC) peak common-mode input voltage (AC) includes all frequencies

above 30 kHz [4] - - 100 mV

ZRX_DC DC input impedance 40 50 60 Ω

VRX(bias) bias receiver voltage voltage at IN_Dx when

IN_Dx = open circuit [5] 1.0 1.2 1.4 V

ZI(se) single-ended input impedance inputs are in

high-impedance state [6] 100 - - kΩ

Product data sheet Rev. 01 — 8 July 2008 14 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

9.2 Differential outputs

The level shifter’s differential outputs are designed to meet DVI version 1.0 and

HDMI version 1.3a speciﬁcations.

[1] VTT is the DC termination voltage in the DVI sink. VTT is nominally 3.3 V. Termination resistance is nominally 50 Ω.

[2] The open-drain output pulls down from VTT.

[3] Swing down from TMDS termination voltage (3.3 V ±10 %).

[4] Maximum rise/fall time at 2.25 Gbit/s = 444 ps. 400 ps = 444 ps −15 %.

[5] This differential skew budget is in addition to the skew presented between IN_Dx+ and IN_Dx− paired input pins.

[6] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[7] Jitter budget for differential signals as they pass through the level shifter. 7.4 ps = 0.02 UI at 1.65 Gbit/s.

Table 8. Differential output characteristics for OUT_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

VOH(se) single-ended HIGH-level

output voltage [1] VTT −0.01 VTT VTT + 0.01 V

VOL(se) single-ended LOW-level

output voltage [2] VTT −0.60 VTT −0.50 VTT −0.40 V

∆VO(se) single-ended output

voltage variation logic 1 and logic 0 state applied

respectively to differential inputs

IN_Dx; Rref(ext) connected.

See Table 5

[3] 450 500 600 mV

IOZ off-state output current single-ended - - 10 µA

trrise time 20 % to 80 % [4] 75 - 180 ps

tffall time 80 % to 20 % [4] 75 - 180 ps

tsk skew time intrapair [5] - - 10 ps

interpair [6] - - 250 ps

tjit jitter time jitter contribution [7] - - 7.4 ps

Product data sheet Rev. 01 — 8 July 2008 15 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

9.3 HPD_SINK input, HPD_SOURCE output

[1] Low-speed input changes state on cable plug/unplug.

[2] Measured with HPD_SINK at VIH maximum and VIL minimum.

[3] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[4] Time required to transition from VOH to VOL or from VOL to VOH.

[5] Guarantees HPD_SINK is LOW when no display is plugged in.

9.4 OE_N and DDC_EN inputs

[1] Measured with input at VIH maximum and VIL minimum.

9.5 DDC characteristics

Table 9. HPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage HPD_SINK [1] 2.0 5.0 5.3 V

VIL LOW-level input voltage HPD_SINK 0 - 0.8 V

ILI input leakage current HPD_SINK [2] --10µA

VOH HIGH-level output voltage HPD_SOURCE 2.5 - VDD V

VOL LOW-level output voltage HPD_SOURCE 0 - 0.2 V

tPD propagation delay from HPD_SINK to HPD_SOURCE;

50 % to 50 %; CL=10pF [3] - - 200 ns

tttransition time HPD_SOURCE rise/fall;10 % to90 %;

CL=10pF [4] 1 - 20 ns

Rpd pull-down resistance HPD_SINK input pull-down resistor [5] 100 200 300 kΩ

Table 10. OE_N and DDC_EN input characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

ILI input leakage current OE_N pin [1] --10µA

Table 11. DDC characteristics

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency SCL_SOURCE, SDA_SOURCE,

SCL_SINK, SDA_SINK - - 400 kHz

ON state (DDC_EN = HIGH and HPD_SINK = HIGH)

RON ON resistance pass gate in ON state; IO=15mA;

VO= 0.4 V -730Ω

VO(sw) switch output voltage SOURCE side; VI= 3.3 V; IO=−100 µA 1.8 2.1 2.4 V

SINK side; VI= 5.0 V; IO=−100 µA 1.8 2.1 2.4 V

Cio input/output capacitance VI= 3.3 V; IO=−100 µA-510pF

OFF state (DDC_EN = LOW)

ILI input leakage current SOURCE side; 0 V < VI< 3.3 V −1- +1µA

SINK side; 0 V < VI< 5.0 V −1- +1µA

Cio input/output capacitance VI= 3.3 V; IO=−100 µA - 15pF

Product data sheet Rev. 01 — 8 July 2008 16 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

10. Package outline

Fig 5. Package outline SOT1031-2 (HWQFN48R)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT1031-2 - - -

- - -

SOT1031-2

08-03-06

08-03-26

UNIT

mm max

nom

min

0.80

0.70

0.65

0.27

0.25

0.23

5.35

5.25

5.15

7.1

7.0

6.9

5.35

5.25

5.15 0.5 5.5 0.42

0.40

0.38 0.1

DIMENSIONS (mm are the original dimensions)

HWQFN48R: plastic thermal enhanced very very thin quad flat package; no leads

48 terminals; resin based; body 7 x 7 x 0.7 mm

b D

7.1

7.0

6.9

DhE Ehe e1

5.5

e2L L1

0.10

0.05

0.00

v w

0.05

0.1

0 2.5 5 mm

scale

detail X

terminal 1

index area

terminal 1

index area

1/2 e

AC B

vMCw M

13 24

48 37

Product data sheet Rev. 01 — 8 July 2008 17 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

Fig 6. Package outline SOT1074-1 (HWQFN48)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT1074-1 - - -

- - -

SOT1074-1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

UNIT

mm max

nom

min

0.80

0.65

0.60

0.05

0.02

0.00 0.2 7.1

7.0

6.9

5.40

5.25

5.10

7.1

7.0

6.9 0.5 5.5 0.5

0.4

0.3 0.1

A(1)

DIMENSIONS (mm are the original dimensions)

HWQFN48: plastic thermal enhanced very very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.65 mm

0 2.5 5 mm

scale

A1b

0.30

0.21

0.18

c D(1) DhE(1) Eh

5.40

5.25

5.10

e e1e2

5.5

L v

0.1

0.05

B A

terminal 1

index area

detail X

AA1

1/2 e

AC B

vMCw M

terminal 1

index area

48 37

2413

08-03-06

08-03-14

Product data sheet Rev. 01 — 8 July 2008 18 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

11. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

11.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

11.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

11.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 01 — 8 July 2008 19 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

11.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 7) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 7.

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 01 — 8 July 2008 20 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

12. Abbreviations

MSL: Moisture Sensitivity Level

Fig 7. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 14. Abbreviations

Acronym Description

CDM Charged-Device Model

CEC Consumer Electronics Control

DDC Data Display Channel

DVI Digital Visual Interface

EMI ElectroMagnetic Interference

ESD ElectroStatic Discharge

HBM Human Body Model

HDMI High-Deﬁnition Multimedia Interface

HPD Hot Plug Detect

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

NMOS Negative-channel Metal-Oxide Semiconductor

TMDS Transition Minimized Differential Signaling

VESA Video Electronics Standards Association

Product data sheet Rev. 01 — 8 July 2008 21 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

13. Revision history

Table 15. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PTN3300B_1 20080708 Product data sheet - -

Product data sheet Rev. 01 — 8 July 2008 22 of 23

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PTN3300B

DVI and HDMI level shifter

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 July 2008

Document identifier: PTN3300B_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3

2.2 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

2.4 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . . 9

6.1 Flexible and power-efﬁcient enable and

disable features. . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1.1 Hot plug detect with power-saving feature . . . . 9

6.1.2 Output Enable function (OE_N) . . . . . . . . . . . 10

6.1.3 DDC channel enable function (DDC_EN). . . . 10

6.1.4 Enable/disable truth table. . . . . . . . . . . . . . . . 10

6.2 Analog current reference . . . . . . . . . . . . . . . . 11

6.3 Backdrive current protection. . . . . . . . . . . . . . 11

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

8 Recommended operating conditions. . . . . . . 12

8.1 Current consumption . . . . . . . . . . . . . . . . . . . 12

9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 13

9.1 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 13

9.2 Differential outputs . . . . . . . . . . . . . . . . . . . . . 14

9.3 HPD_SINK input, HPD_SOURCE output. . . . 15

9.4 OE_N and DDC_EN inputs. . . . . . . . . . . . . . . 15

9.5 DDC characteristics . . . . . . . . . . . . . . . . . . . . 15

10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Soldering of SMD packages . . . . . . . . . . . . . . 18

11.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18

11.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 18

11.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18

11.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 19

12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

14.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15 Contact information. . . . . . . . . . . . . . . . . . . . . 22

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23