Intel® 840 Chipset: 82840 Memory Controller
Hub (MCH)
Datasheet
September 2000
Document Number: 298020-002
R
2 Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel a ssumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in
medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82840 MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations
of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced M anageability Alliance and a trademark of IBM
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
*Third-party brands and names are the property of their respective owners.
Copyright © Intel Corporation 2000
82840 MCH
R
Datasheet 3
Contents
1. Overview.....................................................................................................................................13
1.1. Intel® 840 Chipset System Architecture.........................................................................13
1.2. 82840 MCH Overview....................................................................................................16
1.3. Terminology ...................................................................................................................18
2. Signal Description.......................................................................................................................21
2.1. Host Interface Signals....................................................................................................22
2.2. Direct Rambus* Interface A ...........................................................................................24
2.3. Direct Rambus* Interface B ...........................................................................................25
2.4. Hub Interface A Signals .................................................................................................26
2.5. Hub interface B Signals..................................................................................................26
2.6. AGP Interface Signals....................................................................................................26
2.6.1. AGP Addressing Signals...................................................................................26
2.6.2. AGP Flow Control Signals.................................................................................27
2.6.3. AGP Status Signals...........................................................................................28
2.6.4. AGP Clocking Signals—Strobes .......................................................................28
2.6.5. AGP FRAME# Signals.......................................................................................29
2.7. Clocks, Reset, and Miscellaneous.................................................................................31
2.8. Voltage References, PLL Power....................................................................................32
2.9. Strap Signals..................................................................................................................33
3. Register Description ...................................................................................................................35
3.1. Register Nomenclature and Access Attributes ..............................................................35
3.2. PCI Configuration Space Access...................................................................................36
3.3. I/O Mapped Registers....................................................................................................39
3.3.1. CONF_ADDRConfiguration Address Register ..............................................39
3.3.2. CONF_DATA—Configuration Data Register.....................................................40
3.4. Host-Hub interface A Bridge/DRAM Controller Device Registers (Device 0) ................41
3.4.1. VID—Vendor Identification Register (Device 0)................................................44
3.4.2. DID—Device Identification Register (Device 0).................................................44
3.4.3. PCICMD—PCI Command Register (Device 0).................................................45
3.4.4. PCISTS—PCI Status Register (Device 0).........................................................46
3.4.5. RID—Revision Identification Register (Device 0)..............................................47
3.4.6. SUBC—Sub-Class Code Register (Device 0)...................................................47
3.4.7. BCC—Base Class Code Register (Device 0)....................................................47
3.4.8. MLT—Master Latency Timer Register (Device 0).............................................48
3.4.9. HDR—Header Type Register (Device 0) ..........................................................48
3.4.10. —Aperture Base Configuration Register (Device 0)..........................................48
3.4.11. SVID—Subsystem Vendor ID (Device 0)..........................................................50
3.4.12. SID—Subsystem ID (Device 0).........................................................................50
3.4.13. CAPPTR—Capabilities Pointer (Device 0)........................................................50
3.4.14. GAR[15:0]—RDRAM Group Architecture Register (Device 0)..........................51
3.4.15. MCHCFG—MCH Configuration Register (Device 0).........................................52
3.4.16. FDHC—Fixed DRAM Hole Control Register (Device 0)....................................53
3.4.17. PAM0–PAM6—Programmable Attribute Map Registers (Device 0) ................54
3.4.18. GBA0–GBA15—RDRAM Group Boundary Address Register (Device 0)........57
3.4.19. RDPS—RDRAM Pool Sizing Register (Device 0).............................................58
4 Datasheet
3.4.20. DRD—RDRAM Device Register Data Register (Device 0) ..............................59
3.4.21. RICM—RDRAM Initialization Control Management Register (Device 0)..........59
3.4.22. MCH Expansion RAC A/B Configuration Registers..........................................61
3.4.23. SMRAM—System Management RAM Control Register (Device 0) ................61
3.4.24. ESMRAMC—Extended System Management RAM Control Register
(Device 0) ..........................................................................................................62
3.4.25. ACAPID—AGP Capability Identifier Register (Device 0)..................................63
3.4.26. AGPSTAT—AGP Status Register (Device 0)...................................................64
3.4.27. AGPCMD—AGP Command Register (Device 0) .............................................65
3.4.28. AGPCTRL—AGP Control Register (Device 0).................................................66
3.4.29. APSIZE—Aperture Size (Device 0) ..................................................................66
3.4.30. ATTBASE Aperture Translation Table Base Register (Device 0)................67
3.4.31. AMTT—AGP Interface Multi-Transaction Timer Register (Device 0)..............67
3.4.32. LPTT—Low Priority Transaction Timer Register (Device 0).............................68
3.4.33. RDTR—RDRAM Timing Register (Device 0) ...................................................69
3.4.34. RDCR—RDRAM Refresh Control Register (Device 0).....................................70
3.4.35. TOM—Top of Low Memory Register (Device 0)...............................................71
3.4.36. ERRSTS—Error Status Register (Device 0).....................................................71
3.4.37. ERRCMD—Error Command Register (Device 0).............................................73
3.4.38. SMICMD—SMI Command Register (Device 0)................................................75
3.4.39. SCICMD—SCI Command Register (Device 0).................................................77
3.4.40. SKPD—Scratchpad Data (Device 0) ................................................................78
3.4.41. HERRCTL_STS—Host Error Control/Status Register (Device 0)....................79
3.4.42. DERRCTL_STS—DRAM Error Control/Status Register (Device 0)................80
3.4.43. EAP—Error Address Pointer Register (Device 0).............................................80
3.4.44. AGPBCTRL—AGP Buffer Strength Control Register.......................................81
3.4.45. AGPAPPEND—AGP Append Disable Register................................................81
3.4.46. GTLNCLAMP—GTL N Clamp Disable Register...............................................81
3.5. AGP Bridge Registers (Device 1)..................................................................................82
3.5.1. VID1—Vendor Identification Register (Device 1)..............................................83
3.5.2. DID1—Device Identification Register (Device 1)..............................................83
3.5.3. PCICMD1—PCI-PCI Command Register (Device 1) .......................................84
3.5.4. PCISTS1—PCI-PCI Status Register (Device 1)...............................................85
3.5.5. RID1—Revision Identification Register (Device 1) ...........................................85
3.5.6. SUBC1—Sub-Class Code Register (Device 1) ................................................86
3.5.7. BCC1—Base Class Code Register (Device 1).................................................86
3.5.8. MLT1—Master Latency Timer Register (Device 1) ..........................................86
3.5.9. HDR1—Header Type Register (Device 1)........................................................86
3.5.10. PBUSN1—Primary Bus Number Register (Device 1).......................................87
3.5.11. SBUSN1—Secondary Bus Number Register (Device 1)..................................87
3.5.12. SUBUSN1—Subordinate Bus Number Register (Device 1).............................87
3.5.13. SMLT1—Secondary Master Latency Timer Register (Device 1)......................88
3.5.14. IOBASE1—I/O Base Address Register (Device 1)...........................................88
3.5.15. IOLIMIT1—I/O Limit Address Register (Device 1)............................................89
3.5.16. SSTS1—Secondary PCI-PCI Status Register (Device 1).................................89
3.5.17. MBASE1—Memory Base Address Register (Device 1)....................................90
3.5.18. MLIMIT1—Memory Limit Address Register (Device 1) ....................................91
3.5.19. PMBASE1—Prefetchable Memory Base Address Register (Device 1)............91
3.5.20. PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1).............92
3.5.21. BCTRL1—PCI-PCI Bridge Control Register (Device 1) ...................................92
3.5.22. ERRCMD1—Error Command Register (Device 1)...........................................94
82840 MCH
R
Datasheet 5
3.6. Hub interface B Bridge Registers (Device 2) .................................................................95
3.6.1. VID2—Vendor Identification Register (Device 2)..............................................96
3.6.2. DID2—Device Identification Register (Device 2)...............................................96
3.6.3. PCICMD2—PCI-PCI Command Register (Device 2)........................................97
3.6.4. PCISTS2—PCI-PCI Status Register (Device 2)................................................98
3.6.5. RID2—Revision Identification Register (Device 2)............................................98
3.6.6. SUBC2—Sub-Class Code Register (Device 2).................................................99
3.6.7. BCC2—Base Class Code Register (Device 2)..................................................99
3.6.8. MLT2—Master Latency Timer Register (Device 2)...........................................99
3.6.9. HDR2—Header Type Register (Device 2) ........................................................99
3.6.10. PBUSN2—Primary Bus Number Register (Device 2).....................................100
3.6.11. SBUSN2—Secondary Bus Number Register (Device 2) ................................100
3.6.12. SUBUSN2—Subordinate Bus Number Register (Device 2)............................100
3.6.13. SMLT2—Secondary Master Latency Timer Register (Device 2) ....................100
3.6.14. IOBASE2—I/O Base Address Register (Device 2) .........................................101
3.6.15. IOLIMIT2—I/O Limit Address Register (Device 2)..........................................101
3.6.16. SSTS2—Secondary PCI-PCI Status Register (Device 2)...............................102
3.6.17. MBASE2—Memory Base Address Register (Device 2)..................................103
3.6.18. MLIMIT2—Memory Limit Address Register (Device 2)...................................103
3.6.19. PMBASE2—Prefetchable Memory Base Address Register (Device 2) ..........104
3.6.20. PMLIMIT2—Prefetchable Memory Limit Address Register (Device 2) ...........104
3.6.21. BCTRL2—PCI-PCI Bridge Control Register (Device 2)..................................105
3.6.22. ERRCMD2—Error Command Register (Device 2) .........................................106
4. System Address Map................................................................................................................107
4.1. Memory Address Ranges.............................................................................................107
4.1.1. DOS Compatibility Area...................................................................................108
4.1.2. Extended Memory Area...................................................................................110
4.1.3. AGP Memory Address Ranges.......................................................................112
4.1.4. AGP DRAM Graphics Aperture.......................................................................113
4.1.5. System Management Mode (SMM) Memory Range.......................................113
4.1.5.1. SMM Space Definition.......................................................................114
4.1.5.2. SMM Space Restrictions...................................................................114
4.1.6. Memory Shadowing.........................................................................................115
4.1.7. I/O Address Space..........................................................................................115
4.1.7.1. AGP I/O Address Mapping................................................................115
4.1.8. MCH Decode Rules and Cross-Bridge Address Mapping...............................116
4.1.8.1. The Hub interface A Decode Rules...................................................116
4.1.8.2. The Hub interface B Decode Rules...................................................116
4.1.8.3. AGP Interface Decode Rules............................................................117
4.1.8.4. Legacy VGA Ranges.........................................................................118
6 Datasheet
5. Functional Description..............................................................................................................119
5.1. Host Interface..............................................................................................................119
5.1.1. Frame Buffer Memory Support.......................................................................125
5.2. AGP Interface..............................................................................................................125
5.2.1. AGP Target Operations ..................................................................................125
5.2.2. AGP Transaction Ordering .............................................................................127
5.2.3. AGP Electricals...............................................................................................127
5.2.4. The Differences Between AGP FRAME# and PCI-66 Devices ......................127
5.2.5. 4x AGP Protocol .............................................................................................127
5.2.6. Fast Writes......................................................................................................128
5.2.7. AGP Universal Connector...............................................................................128
5.2.8. AGP FRAME# Transactions on AGP .............................................................128
5.2.8.1. MCH Initiator and Target Operations................................................129
5.2.8.2. MCH Retry/Disconnect Conditions ...................................................131
5.2.8.3. Delayed Transaction.........................................................................131
5.3. RDRAM Interface ........................................................................................................132
5.3.1. RDRAM Organization and Configuration........................................................134
5.3.1.1. Rules for Populating RDRAM Devices .............................................135
5.3.1.2. RDRAM CMOS Signals Description and Usage...............................136
5.3.1.3. Direct RDRAM Core Refresh............................................................138
5.3.1.4. Direct RDRAM Current Calibration...................................................138
5.3.2. Direct RDRAM Command Encoding...............................................................138
5.3.2.1. Row Packet (ROWA/ROWR)...........................................................139
5.3.2.2. Column Packet (COLC/COLX).........................................................141
5.3.2.3. Data Packet......................................................................................142
5.3.3. Direct RDRAM Register Programming...........................................................143
5.3.4. Direct RDRAM Operating States ....................................................................143
5.3.5. RDRAM Power Management..........................................................................144
5.3.6. Data Integrity...................................................................................................145
5.3.7. RDRAM Array Thermal Management.............................................................145
5.4. System Reset ..............................................................................................................146
6. Ballout and Package Information.............................................................................................147
6.1. MCH Ball List...............................................................................................................147
6.2. Package Information....................................................................................................154
6.2.1. 82840 RSL Nomalized Trace Length Data.....................................................156
6.3. Initialization Sequence.................................................................................................160
6.4. XOR Chains.................................................................................................................161
82840 MCH
R
Datasheet 7
Figures
Figure 1. Intel 840 Chipset System Block Diagram ................................................................14
Figure 2. PAM Registers...........................................................................................................55
Figure 3. System Address Map ..............................................................................................107
Figure 4. Detailed DOS Compatible Area Address Map.........................................................110
Figure 5. Detailed Extended Memory Range Address Map ...................................................110
Figure 6. Single Channel-pair Mode.......................................................................................132
Figure 7. Multiple Channel-pair Mode.....................................................................................133
Figure 8. RDRAM Devices Sideband CMOS Signal Configuration on
Rambus* Channel A................................................................................................136
Figure 9. MRH-R Sideband CMOS Signal Configuration on Rambus* Channel A.................137
Figure 10. 82840 MCH Reset.................................................................................................146
Figure 11. MCH Ballout (Top View, Left Side)........................................................................148
Figure 12. MCH Ballout (Top View, Right Side) .....................................................................149
Figure 13. 82840 MCH BGA Package Dimensions (Top and Side Views) ............................154
Figure 14. 82840 MCH BGA Package Dimensions (Bottom View)........................................155
Figure 15. XOR-Tree Chain....................................................................................................159
Figure 16. XOR Chain Test Mode Initialization.......................................................................160
8 Datasheet
Tables
Table 1. Maximum Memory Vs DRAM Densities.....................................................................17
Table 2. MCH Configuration Space (Device 0)........................................................................41
Table 3. Attribute Bit Assignment.............................................................................................54
Table 4. PAM Registers and Associated Memory Segments ..................................................55
Table 5. MCH Configuration Space (Device 1)........................................................................82
Table 6. MCH Configuration Space (Device 2)........................................................................95
Table 7. Memory Segments and their Attributes....................................................................108
Table 8. P6 Bus Transactions Supported by the MCH ..........................................................119
Table 9. Ty pes of Responses Supported by the MCH...........................................................121
Table 10. Types of Special Cycles Supported by the MCH ...................................................124
Table 11. AGP Commands Supported by the MCH When Acting as an AGP Target...........126
Table 12. Fast Write Register Programming .........................................................................128
Table 13. PCI Commands Supported by the MCH When Acting as A FRAME# Target .......129
Table 14. Maximum Memory Supported For Various Configurations....................................133
Table 15. Direct RDRAM Device Configurations ...................................................................134
Table 16. RDRAM Device Grouping ......................................................................................135
Table 17. Sideband CMOS Signal Description ......................................................................137
Table 18. CMD Signal Value Decode.....................................................................................137
Table 19. ROWA Packet for Activating (sensing) a Row (i.e., AV = 1)..................................139
Table 20. ROWR Packet for other operations (i.e., AV = 0)..................................................139
Table 21. COLC Packet.........................................................................................................141
Table 22. COLC Packet Field Encodings...............................................................................141
Table 23. COLX Packet (M = 0).............................................................................................142
Table 24. COLM Packet and COLX Packet Field Encodings ................................................142
Table 25. Data Packet............................................................................................................142
Table 26. DRAM Operating States.........................................................................................143
Table 27. RDRAM Power Management States......................................................................144
Table 28. MCH Alphabetical Ballout List................................................................................150
Table 29. Package Dimensions .............................................................................................155
Table 30. XOR Chain #0 Connections...................................................................................161
Table 31. XOR Chain #1 Connections...................................................................................161
Table 32. XOR Chain #2 Connections...................................................................................162
Table 33. XOR Chain #3 Connections...................................................................................162
Table 34. XOR Chain #4 Connections...................................................................................163
Table 35. XOR Chain #5 Connections...................................................................................164
Table 36. XOR Chain #6 Connections...................................................................................164
82840 MCH
R
Datasheet 9
Revision History
Rev. Draft/Changes Date
-001 • Initial Rel ease October 1999
-002 • Minor edits throughout for c l ari ty.
• Removed ref erences to MRH-S and S DRAM
• Removed ref erences to us i ng two MRH-Rs per channel.
September 2000
10 Datasheet
This page is left intentionally blank.
82840 MCH
R
Datasheet 11
Intel® 82840 MCH
Product Features
!
Processor/Host Bus Support
Supports up to two Pentium II processors
or Pentium III processors at 100 MHz or
133 MHz system bus frequency
Supports full symmetric multiprocessor
(SMP) protocol
Supports 32- or 36-bit host bus addressing
Supports 8 deep In-Order Queue
ECC protection on FSB data signals
IERR and BERR signals ge ne rate SCI/ SERR
Parity protection on address/response signals
!
Memory Controller—Direct Rambus* Support
Direct support for dual Direct Rambus*
Channels operating in lock-step: Supports
300 MHz, 400 MHz
Supports 64Mb, 128Mb, 256Mb RDRAM
devices
Maximum memory arra y si ze up to 1 GB
using 64Mb, 2 GB using 128Mb, 4 GB using
256Mb
Supports up to 64 Direct Rambus* devices
without using MRH-Rs
Supports up to four Rambus* channels using
two external Memory Repeater Hubs for
RDRAM devices (MRH-R)
!
Po wer Manage ment
SMRAM space remapping to
A0000h–BFFFFh (128 KB)
Supports extended SMRAM space above
256 MB, additional 128 KB / 256 KB /
512 KB / 1 MB TSEG from Top of
Memory, cacheable (cacheability controlled
by processor)
Suspend to RAM support
!
Memory Controller—Configurable Optional
ECC Oper a tion
ECC with single bit Error Correction and
multiple bit Erro r Detection
Single bit errors corrected and written back
to memory (scrubbing)
!
Accelerated Graphics Port (AGP) Interface
Supports a single AGP device (either via a
connector or on the motherboard)
Supports AGP 2.0 including 4x AGP data
transfers and 2x/4x Fast Write protocol
AGP Universal Connector support via dual
mode buffers to allow AGP 2.0 3.3V or 1.5V
signaling
!
Hub interface A to ICH—High speed
interconnect between MCH and ICH
(266 MB/sec)
!
Hub interface B to P 64H—High speed
interconnect between MCH and P64H
(533 MB/sec)
!
Arbitration
Distributed arbitration model for optimum
concurrency support
Concurrent operations of host, hub interface,
AGP, and memory buses supported via
dedicated arbitration and data buffering logic
!
Process/Package
544 mBGA
The Intel 82840 Memory Controller Hub may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available
on request.
12 Datasheet
Simplified Block Diagram
MCH_blk.vs
d
HA[35:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
AP[1:0]#
BERR#
BREQ0#
DBSY#
DEP[7:0]#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
IERR#
RP#
RSP#
RS[2:0]#
CPURST#
System Bus
Interface
AGP
Interface
Clocks,
Reset, and
Test
CPUCLK
CLK66
RCLKOUT[A:B]
HCLKOUT[A:B]
RSTIN#
TEST#
OVERT#
Voltage
References,
Power,
Ground
GTLREF[A:B]
AGPRCOMP
CHA_REF[1:0]
CHB_REF[1:0]
AGPREF
HLAREF
HLBREF
VDDQ
VCC1_8
VTT
VSS
PIPE#
SBA[7:0]
ST[2:0]
RBF#
WBF#
AD_STB0, AD_STB0#
AD_STB1, AD_STB1#
SB_STB, SB_STB#
G_AD[31:0]
G_C/BE[3:0]#
G_FRAME#
G_TRDY#
G_IRDY#
G_REQ#
G_DEVSEL#
G_GNT#
G_PAR
G_STOP#
G_SERR#
HLA[11:0]
HLA_STB, HLA_STB#
HLAZCOMP
Hub
Interface
A
HLB[19:0]
HLB_STB[1:0], HLB_STB[1
HLBRCOMP
Hub
Interface
B
CHA_DQA[8:0]
CHA_DQB[8:0]
CHA_RQ[7:5] or CHA_ROW[2:0]
CHA_RQ[4:0] or CHA_COL[4:0]
CHA_CTM, CHA_CTM#
CHA_CFM, CHA_CFM#
CHA_CMD
CHA_SCK
CHA_SIO
CHA_EXP[1:0]
System
Memory
Direct
Rambus
Interface
A
CHB_DQA[8:0]
CHB_DQB[8:0]
CHB_RQ[7:5] or CHB_ROW[2:0]
CHB_RQ[4:0] or CHB_COL[4:0]
CHB_CTM, CHB_CTM#
CHB_CFM, CHB_CFM#
CHB_CMD
CHB_SCK
CHB_SIO
CHB_EXP[1:0]
System
Memory
Direct
Rambus
Interface
B
82840 MCH
R
Datasheet 13
1. Overview
The Intel® 840 chipset is a high-bandwidth chipset designed for workstation and server platforms based
on Intel Pentium II processor / Intel Pentium III processor architectures. The chipset contains two
main components and additional optional components that provide expansion capability. The 82840
Memory Controller Hub (MCH) provides the system bus interface, memory controller, AGP interface,
hub interface for I/O, and hub interface for PCI bus expansion. This document describes the 82840
Memory Controller Hub (MCH). Section 1.1, Intel® 840 Chipset System Architecture, provides an
overview of each of the components of the Intel® 840 chipset.
1.1. Intel® 840 Chipset System Architecture
The Intel® 840 chipset is optimized for the Intel Pentium II processor and Intel Pentium III processor
architectures. The Intel® 840 chipset allows flexibility for dual and multi-processor configurations with
100 MHz and 133 MHz system buses. T he Intel® 840 chipset consists of 2 main components: 82840
Memory Controller Hub (MCH), and 82801AA I/O Controller Hub (ICH).
Architectural expansion is provided with the memory expansion card and PCI 64-bit Hub. The 82803AA
Memory Repeater Hub (MRH-R) provides memory expansion capabilities for RDRAM channels. The
82806AA PCI 64 Hub (P64H) provides PCI bridging functions between the hub interface and PCI Bus.
The Intel® 840 chipset components are interconnected via an interface called “hub interface”. The hub
interface provides efficient communication between the chipset components.
Additional hardware platform features, supported by Intel® 840 chipset, include AGP 4X, RDRAM,
Ultra DMA/66, Low Pin Count interface (LPC), and Universal Serial Bus (USB). The Intel® 840 chipset
architecture removes the requirement for the ISA expansion bus that was traditionally integrated into the
I/O subsystem of PCIsets/AGPsets. This eliminates many conflicts experienced when installing legacy
ISA hardware and drivers.
The Intel® 840 chipset is also ACPI compliant and supports Full-on, Stop Grant, Suspend to RAM,
Suspend to Disk, and Soft-off power manage ment st ates. Through the use of an appropriate LAN device,
Intel® 840 chipset also supports wake-on-LAN* for remote administration and troubleshooting.
14 Datasheet
Figure 1. Intel
840 Chipset System Block Diagram
Main Memory
(2 GB Max.)
sys_blk
82840 Memory
Controller Hub
(MCH)
AGP 4X
Graphics
Controller
Hub
Interface A
AGP 2.0
Processor Processor
82806AA
PCI 64 Hub
(P64H)
Six 33 MHz
PCI Slots
Or
Two 66 MHz
PCI Slots
82801AA
I/O Controller
Hub (ICH)
FWH Flash
BIOS
GPIO
2 USB Ports
4 IDE Drives
AC'97 Codec(s)
(optional) AC'97 2.1
33 MHz
PCI Bus
PCI
Slots
PCI
Agent
LPC I/F
Super I/O
RDRAM
RDRAM
Channel A
Channel B
Memory Interface
(300 MHz, 400 MHz)
Hub
Interface B
RDRAM
82803AA
(MRH-R) RDRAM
RDRAM
82803AA
(MRH-R) RDRAM
Channel A
Channel B
Memory Expansion Card
Shaded blocks are
Intel
®
840 Chipset components
82801AA I/O Controller Hub (ICH)
The ICH is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI
Bus and integrates many of the functions needed in today’s PC platforms. The MCH and ICH
communicate over a dedicated hub interface. Functions and capabilities include:
• PCI Rev 2.2 compliant with support for 33 MHz PCI operations
• Supports up to 6 Req/Gnt pairs (PCI Slots)
• Power Management Logic Support
• Enhanced DMA Controller, Interrupt Controller and Timer Functions
• Integrated IDE controller; Ultra ATA/66
• USB host interface with support for 2 USB ports
• System Management Bus (SMBus) compatible with most I2C devices
• AC’97 2.1 Compliant Link for Audio and Telephony CODECs
• Low Pin Count (LPC) interface
• FWH Flash BIOS interface support
• Alert on LAN*
82840 MCH
R
Datasheet 15
82806AA PCI 64 Hub (P64H)
The PCI-64 Hub(P64H) is a peripheral chip that performs PCI bridging functions between the hub
interface and the PCI Bus and is used as an integral part of the Intel 840 chipset. The P64H has a 16-bit
primary hub interface to the Memory Controller Hub (MCH) and a secondary 64-bit PCI Bus interface.
The 64-bit interfaces inter-operates transparently with either 64-bit or 32-bit devices. The P64H is fully
compliant with the PCI Local Bus Specification, Revision 2.2. The P64H functi ons include:
• PCI Hot Plug controller
• Integrated PCI low skew clock driver
• I/O APIC
82803AA Memory Repeater Hub (MRH-R)
The MRH-R supports multiple RDRAM channels from an “expansion channel.” Expansion channel is
the interconnect between the MCH and the MRH-R. Each MRH-R can support up to 2 “stick” channels.
The MRH-R acts as a pass-through logic with fixed delay for read and write accesses from expansion
channels to RDRAM channels. The MRH-R features include:
• Maximu m of 1 GB memo ry per ch an nel
• Nap Entry/Exit, Power down Exit, Refresh and Precharge on a channel upon request from memory
controller
• Core logic gating to minimize power consumption
• Clock genera t ion for Direct Rambus* Cloc k Generator (DRCG)
• Integrated SMBus controller to read/write data from/to SPD EEP ROM on the RIMMs
16 Datasheet
1.2. 82840 MCH Overview
The 82840 Memory Hub (MCH) component provides the processor interface, DRAM interface, and
AGP interface in a 82840 workstation or server platform. It supports dual channels of Direct Rambus
DRAM operating in lock-step. It also supports 4x AGP data transfers and 2x/4x AGP Fast Writes. The
MCH contains advanced power management logic. The Intel 840 chipset platform uses the dedicated I/O
Controller Hub (ICH) designed for use with the MCH to provide the features required by a workstation
or a server platform. In addition, the 82840 MCH implements a second 16 bit/66 MHz port that may be
used to connect an advanced 64 bit PCI interface (P64H). Communication with ICH and P64H is
accomplished via a high speed interface called “hub interface”.
The 82840 MCH contains the following functionality:
• Supports up to two processor configurations at 100 MHz or 133 MHz
• GTL+ host bus supporting 32 or 36-bit host addressing
• Dual Direct Rambus channels supported for 300 MHz or 400 MHz operation
• 4 GB support for RDRAM devices
• AGP interface with 4x SBA/Data Transfer and 2x/4x Fast Write capability
• 8 bit, 66 MHz hub interface A to ICH
• 16 bit, 66 MHz hub interface B to P64H
• Fully optimized data p a ths and buffering
• Distr ibuted arbitr ation for highl y concurrent o peration
Host Interface
The 82840 MCH supports up to two processors at FSB frequencies of 100/133 MHz using AGTL+
signaling. In a dual-processor system one of the two processor agent IDs must be assigned to ID0. The
82840 MCH supports either 32 or 36-bit host addresses, allowing the processor to access the entire 4 GB
of the MCH’s memory address space. The MCH has an 8-deep In-Order Queue to support up to eight
outstanding pipelined address requests on the host bus. Host-initiated I/O cycles are positively decoded
to AGP, hub interface B, or MCH configuration space and subtractively decoded to hub interface A.
Host-initiated memory cycles are positively decoded to AGP, hub interface B, or DRAM, and are again
subtractively decoded to hub interface A. AGP semantic memory accesses initiated from AGP to DRAM
are not snooped on the host bus. Memory accesses initiated from AGP using PCI semantics and from
either hub interface to DRAM will be snooped on the FSB. Memory accesses whose addresses lie within
the AGP aperture are translated using the AGP address translation table, regardless of the originating
interface.
The MCH provides optional host bus error checking for data, address, request and response signals.
Single bit errors (correctable) are always corrected if it is enabled and can be configured to generate hub
interface SMI or SCI cycles to ICH on the host data bus. Multiple bit errors (uncorrectable) can be
configured to generate a BERR# condition on the host bus. The MCH can be configured to generate hub
interface SERR or SCI cycles to ICH for BE RR# or IERR# error conditio ns. T he MCH can also generate
the hub interface SERR cycle to ICH for the host address parity or the request parity conditio ns. T he
MCH also supports response parity RSP# for the response signals RS[2:0]#.
82840 MCH
R
Datasheet 17
DRAM Interf ace
The MCH directly supports dual channels of Direct Rambus* memory operating in lock-step using
Rambus* Signaling Level (RSL) technology. Only 300 MHz and 400 MHz Direct Rambus* devices are
supported in any of 64, 128 or 256Mb technology. The 64 and 128 MBit RDRAMs use page sizes of
1 KB, while 256Mb devices target 1 KB or 2 KB pages. A maximum of 64 Rambus* devices
(64Mb technology implies 512 MB maximum in 16 MB increments, 256Mb technology implies 2 GB
maximum in 64 MB increments) are supported on the paired channels without external logic. The MCH
also supports a single external Rambus* channel repeater per connected channel. Each repeater adds a
single additional branch to the main channel, which yields a total of four Rambus* channels. The
following table shows the maximum DRAM array size and the minimum increment size for the various
DRAM densities supported.
Table 1. Maximum Memory Vs DRAM Densities
Directly Supported Supported via Repeater(s) RDRAM
Technology Increments Maximum Increments Maximum
64Mb 16 MB 512 MB 16 MB 1 GB
128Mb 32 MB 1 GB 32 MB 2 GB
256Mb 64 MB 2 GB 64 MB 4 GB
The 82840 MCH provides optional ECC error checking for DRAM data integrity. During DRAM writes,
ECC is generated on a QWord (64 bit) basis. Partial QWord writes require a read-modify-write cycle
when ECC is enabled. During DRAM reads, the MCH supports detection of single-bit and multiple-bit
errors, and correct single bit errors, when correction is enabled. The MCH scrubs single bit errors by
writing the corrected value back into DRAM for all reads, when hardware scrubbing is enabled (except
for those launched to satisfy an AGP aperture translation). ECC can only be enabled when all RDRAM
devices populated in a system support the extra two data bits used to store the ECC code.
The 82840 MCH provides a maximum DRAM address decode space of 4 GB. The MCH does not remap
APIC memory space in hardware. It is the BIOS or system designers respo nsibility to limit DRAM
configuration so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated.
AGP Interface
A single AGP device or connector (not both) is supported by the MCH AGP interface. The AGP buffers
operate in one of two selectable modes to support the AGP Universal Connector:
• 3.3V drive, not 5 volt safe: This mode is compliant to the AGP 1 . 0 specification
• 1.5V drive, not 3.3 volt safe: This mode is compliant with the AGP 2.0 specication
The following table shows the AGP data rate and the signaling levels supported by the MCH.
Signaling Level Data Rate
1.5V 3.3V
1x AGP * Yes Yes
2x AGP Yes Yes
4x AGP Yes No
* Note AGP FRAME # d ata rate and signaling level is the same as 1X AGP.
18 Datasheet
The AGP interface supports 4x AGP signaling and 4x Fast Writes. AGP semantic (PIPE# or SBA[7:0])
cycles to DRAM are not snooped on the host bus. AGP FRAME# cycles to DRAM are snooped on the
host bus. The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously.
Either the PIPE# or the SB A[7:0] mechanism must be selected during system initialization. High priority
accesses are supported. Only memory writes from either hub interface A or hub interface B to AGP are
allowed. No transactions from AGP to the hub interface are allowed.
MCH Clocki ng
The MCH has two clock input pins: CPUCLK for the host clock and CLK66 for the AGP clock. Clock
Synthesizer chip(s) are responsible for generating the Host clocks, AGP clocks, PCI clocks, and
Rambus* clocks. These clocks must be synchronous to each other.
The MCH host interface runs at 100 MHz or 133 MHz. The supported speed bins for Direct RDRAM
devices are 300 MHz and 400 MHz. T he AGP interface runs at a constant 66 MHz. The hub interface
interfaces run at the same base frequency as the AGP interface.
1.3. Terminology
Term Description
MCH The 82840 Memory Controller Hub component that contains the processor
interface, DRAM controller, PCI-64 bridge and AGP interface. It
communicates with the 82840 I/O controller hub (ICH) and the 64 bit PCI bus
hub (P64H) over a private interconnect called “hub interface”.
ICH The 82801AA IO Controller Hub component that contains the primary PCI
interface, LPC interface, USB, ATA-66, and other IO functions. The ICH
communicates with the MCH over a private interconnect called hub interface.
P64H The 82806AA Bus Controller Hub component that contains a 64-bit, 66 MHz
PCI interface.
Host This term is used synonymously with processor.
Core The internal base logic in the MCH.
Hub Interface The private interconnect that ties the MCH to the ICH and/or P64H. In this
document hub interface cycles originating from or destined for the primary PCI
interface on the ICH are generally referred to as hub interface A cycles. Cycles
originating from or destined for any target on the secondary hub interfaces are
described as hub interface B cycles.
Accelerated Graphics
Port (AGP) The AGP interface in the MCH. The MCH supports a subset of 3.3V, 66 MHz
components, 3.3V 66/133 MHz AGP 2.0 compliant components, and the new
1.5V 66/266 MHz components. PIPE# and SBA addressing cycles and their
associated data phases are generally referred to as AGP transactions.
RSL Rambus* Signaling Level is the name of the signa ling technology used by
Rambus*.
82840 MCH
R
Datasheet 19
Term Description
Single Channel-pair
Mode In this mode, the 82840 MCH is configured to directly support RDRAM
devices on its dual Rambus* channel. There is no MRH-R used on the memory
subsystem.
Multiple Channel-pair
Mode In this mode, the 82840 MCH is configured to use MRH-R on the memory
subsystem. Each Rambus* channel of the MRH-R on the MCH Direct Rambus*
Interface A matches with one Rambus* channel of the MRH-R on the Direct
Rambus* Interface B.
Single Device-pair In the single channel-pair mode, the 82840 MCH is configured to directly
support RDRAM devices on its dual Rambus* channel. Each RDRAM deivce
of the MCH Direct Rambus* Interface A matches with one RDRAM device of
the Direct Rambus* Interface B. There is no MRH-R used on the memory
subsystem.
Multiple Device-pair In the multiple channel-pair mode, the 82840 MCH is configured to use
MRH-R on the memory subsystem. Each RDRAM deivce on Direct Rambus*
Interface A matches with one RDRAM device on the Direct Rambus* Interface
B.
20 Datasheet
This page is left intentionally blank.
82840 MCH
R
Datasheet 21
2. Signal Description
This section provides a detailed descriptio n of MCH signals. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
The following notations are used to describe the signal type:
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
s/t/s Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.
as/t/s Active Sustained Tristate. This applies to some of the hub interface signals. T his pin is weakly
driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal:
GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details.
AGP AGP interface signals. These signals can be programmed to be compatible with AGP 2.0 3.3v
or 1.5v Signaling Environment DC and AC Specifications. In 3.3v mode the buffers are not 5v
tolerant. In 1.5v mode the buffers are not 3.3v tolerant.
CMOS CMOS buffers.
RSL Rambus* Signaling Level interface signal.
22 Datasheet
2.1. Host Interface Signals
Name Type Description
ADS# I/O
GTL+ Address Strobe: The PROCES SOR bus owner assert s ADS# to i ndi cate the fi rst of
two cycles of a request phas e.
AP[1:0]# I/O
GTL+ Address Parity: A P[1:0]# provi de parity over the addres s signals. AP1# covers
HA[35:24]#; AP0 # covers HA[23:3]#. These signals mus t be valid for t wo clo cks
beginning when ADS# is asserted.
BERR# I/O
GTL+ Bus Error: The BERR# signal is asserted t o i ndi cate an unrecoverable error without
a bus protoc ol vi ol ation.
BNR# I/O
GTL+ Block Next Request: Used to block t he current request bus owner from issuing a
new requests. Thi s signal is used to dynamical l y c ontrol the PROCE S SOR bus
pipeline depth.
BREQ0# O
GTL+ Symmetric Agent Bus Request: Ass e rt ed by the MCH when CPURST# is as serted
to confi gure the sym metric bus agents. The BREQ0# is negat ed 2 host cl ocks after
CPURST# is negated.
BPRI# O
GTL+ Priority Agent Bus Request: The MCH is the only P ri ori ty Agent on the
PROCESS OR bus. It asserts this s i gnal to obtain the ownership of the address bus.
This si gnal has priority over s ymmetric bus requests and causes t he current
symmetric owner to stop is suing new transact i ons unless t he HLOCK# signal was
asserted.
CPURST# O
GTL+ CPU Reset. The CPURS T # pi n i s an output from the MCH. The MCH asserts
CPURST# while RSTI N# (P CIRST# from ICH) is asserted f o r approxim ately 1 m s
after RSTIN# is deasserted. The CP URS T # al l ows t he processors to begin execution
in a known state.
DBSY# I/O
GTL+ Data Bus Busy: Us ed by the data bus owner to hold t he data bus for t ransfers
requiring m ore than one cycle.
DEFER# O
GTL+ Defer: MCH generates a def erred response as defined by the rules of the MCH’s
dynamic defer polic y. The MCH also uses the DEFER# s i gnal t o i ndi cate a processor
retry respons e.
DEP[7:0]# I/O
GTL+ Host ECC: The DE P [7:0]# s i gnal s are driven during the Data P hase by the agent
responsibl e for driving HD[63: 0] #. The DEP[7:0]# si gnal s provide ECC protection for
the signal s on the data bus .
DRDY# I/O
GTL+ Data Ready: Asserted f or each cycle that data is transf erred.
HA[35:3]# I/O
GTL+ Host Address Bus: HA[35:3]# connec t to the proc essor address bus. During
process or cycles, HA[35:3]# are inputs . The MCH drives HA[35:3]# duri ng snoop
cycles on behal f of hub interface and AGP FRA ME # i ni t i ators. Not e that the addres s
is invert ed on the process or bus.
HD[63:0]# I/O
GTL+ Host Data: These signals are c onnected to t he processor dat a bus. Note that the
data signal s are inverted on the processor bus.
HIT# I/O
GTL+ Hit: Indicates that a c aching agent is retaining an unmodified vers i on of the
requested li ne. HIT# is also driven in conjunc tion with HITM# by the target to extend
the snoop window.
HITM# I/O
GTL+ Hit Mod ified: Indicates that a c aching agent holds a modified version of the
requested line and that this agent assumes res ponsibility for providing the line. A l so,
driven in conjunc tion with HIT# to extend the snoop window.
82840 MCH
R
Datasheet 23
Name Type Description
HLOCK# I
GTL+ Host Lock: All processor bus cycles sampl ed with t he asserti on of HLOCK# and
ADS#, unt i l the negation of HLOCK # must be atomi c (i.e., no hub i nterface or A GP
snoopable access to DRAM is all owed when HLOCK# is as serted by the proc essor).
HREQ[4:0]# I/O
GTL+ Host Request Command: Asserted during both clocks of request phase. In the fi rst
clock, HREQ[ 4:0]# define the transac tion type to a level of detail t hat is suffici ent to
begin a snoop request. In the second cl ock, t he signals carry additional i nformat i on t o
define the c omplet e t ransaction type. The transactions supported by the MCH Host
Bridge are defined i n the Functional Description Chapt er.
HTRDY# O
GTL+ Host Target Ready: HTRDY# indicates that t he target of t he processor t ransaction i s
able to enter t he data transf er phase.
IERR# I
CMOS Internal Error: A proces sor assert s IERR# when it det ects an internal error unrelated
to bus operati on.
RP# I/O
GTL+ Request Parity: RP# Provides pari ty protect i on over ADS# and HREQ[ 4:0]#. RP #
must be valid for two clocks beginning when ADS# is assert ed.
RS[2:0]# O
GTL+ Response Signals: Indicates type of response acc ordi ng to the foll owing the t abl e:
RS[2:0] Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Fai l ure (not driven by MCH)
101 No data response
110 Impli cit Wri t eback
111 Normal data response
RSP# O
GTL+ Response Parity: RS P# is always driven by t he 82840 MCH and must be valid on all
clocks. Response parity is correct if t here are an even number of low si gnal s in the
set c onsisti ng of the RS[2 : 0]# signals and the RSP# signal.
The following is the list of processor bus interface signals that are NOT supported by MCH.
Signal Function Not Support By MCH
AERR# Address P arity Error Error Phase response t o pari ty error
BINIT# Bus Ini tializati on S i gnal Rest of the host bus state machines without full MCH reset
24 Datasheet
2.2. Direct Rambus* Interface A
Signal Type Description
CHA_DQA[8:0] I/O
RSL Rambus Data Byte A (CHA): Bi-direc tional 9-bit data bus A on the Rambus*
interfac e A. Data s i gnal s used for read and write operati ons on Rambus* channel
“A”.
CHA_DQB[8:0] I/O
RSL Rambus Data Byte B (CHA): Bi-directional 9-bit data bus B on the Rambus*
interfac e A. Data s i gnal s used for read and write operati ons on Rambus* channel
“A”.
CHA_RQ[7:5]/
CHA_ROW [2:0]
O
RSL Row Access Control (CHA): Three request pac kage pins containing cont rol and
address informat i on for row accesses. Note t hat RQ_A[7:5] can also be named as
ROW_A[2: 0] signals.
CHA_RQ[4:0]/
CHA_COL[4:0]
O
RSL Column Access Control (CHA): Five request package pins containi ng control
and address informat i on for column accesses. Note that RQ_A[4:0] c an al so be
named as COL_A [4:0] s i gnal s.
CHA_CTM I
RSL Clock To Master (CHA): One of the two differential transmi t clock signals us ed
for RDRAM operations on Rambus * channel “A”. It is an i nput to the MCH and is
generated from an external clock synthes i zer.
CHA_CTM# I
RSL Clock To Master Com p liment (CHA): One of the two diff erent i al transm i t clock
signals used for RDRAM operations on Rambus* channel “A”. It is an i nput to the
MCH and is generated from an external clock synt hesizer.
CHA_CFM O
RSL Clock From Master (CHA): One of t he two differential receive cloc k signals used
for RDRAM operations on Rambus * channel “A”. It is an output from the MCH.
CHA_CFM# O
RSL Clock From Master Compli ment(CHA): One of the two differenti al receive cloc k
signals used for RDRAM operations on Rambus* channel “A”. It is an output from
the MCH.
CHA_EXP[1:0] O
RSL Expansion (CHA): These signals are used to comm uni cate to an external
Rambus * repeat er on Rambus* channel “A”. The repeat er i ncreases t he
maxim um memory size supported by the MCH.
CHA_CMD O
CMOS
Comma n d (CHA): Command output t o the Rambus * devi ces used f or power
mode c ont rol , configuri ng the SIO daisy chain, and f raming SI O operations.
CHA_SCK O
CMOS Serial Clock (CHA): This signal provides cloc king for regis ter acces ses and
selects Ram bus* channel “A” devi ces for power management.
CHA_SIO I/O
CMOS Serial Input/Output (A): Bi-di rectional serial data s i gnal used for devic e
initial i zat i on, register operations, power m ode control, and devi ce reset.
82840 MCH
R
Datasheet 25
2.3. Direct Rambus* Interface B
Signal Nam e Type Description
CHB_DQA[8:0] I/O
RSL Rambus Data Byte A (CHB): Bi-directional 9-bit data bus A on the Rambus*
interfac e B. Data s i gnal s used for read and write operati ons on Rambus * channel
“A”.
CHB_DQB[8:0] I/O
RSL Rambus Data Byte B (CHB): Bi-direct i onal 9-bi t data bus B on the Rambus *
interfac e B. Data s i gnal s used for read and write operati ons on Rambus * channel
“A”.
CHB_RQ[7:50]/
CHB_ROW [2:0]
O
RSL Row Access ControlRequest Control (CHB): Three request pac kage pins
containi ng control and address information for row accesses . Note that
CHB_RQ[7:5] can also be named as CHB_ROW[2:0] signals.
CHB_RQ[4:0]/
CHB_COL[4:0]
O
RSL Column Access Control (CHB): Five request package pins containing c ontrol
and address informat i on for column accesses. Note that CHB _RQ[ 4:0] can also
be named as CHB _COL[4:0] s i gnal s.
CHB_CTM I
RSL Clock To M aster (CHB): One of the t wo differential t ransmit clock signals used
for RDRAM operations on Rambus * channel “B”. CHB _ CTM is an i nput to the
MCH and is generated from an external clock synthesizer.
CHB_CTM# I
RSL Clock To Master Com p liment (CHB): One of the two differenti al transm i t clock
signals used for RDRAM operations on Rambus* channel “B”. CHB_CTM# is an
input to t he MCH and is generated from an external clock synthesizer.
CHB_CFM O
RSL Clock From Master (CHB): One of the two differenti al receive cloc k signals used
for RDRAM operations on Rambus * channel “B”. CHB _ CFM is an output from the
MCH.
CHB_CFM# O
RSL Clock From Master Compli ment (CHB): One of t he two differential receive cloc k
signals used for RDRAM operations on Rambus* channel “B”. CHB_CFM# is an
output from the MCH.
CHB_EXP[1:0] O
RSL Expansion (CHB): These signals are used to communi cate to an external
Rambus * repeat er on Rambus* channel “B”. The repeat er i ncreases t he
maxim um memory size supported by the MCH.
CHB_CMD O
CMOS Comma n d (CHB): Command output to the Ram bus* devices used for power
mode c ont rol , configuri ng the SIO daisy chain, and f raming SI O operations.
CHB_SCK O
CMOS Serial Clock (CHB): This signal provides clocki ng for register accesses and
selects Ram bus* channel “B” devi ces for power management.
CHB_SIO I/O
CMOS Serial Input/Output (CHB): Serial Input/Output A: Bi-directional serial data
signal us ed for device ini t i al i zation, regis ter operations, power mode control , and
device reset.
26 Datasheet
2.4. Hub Interface A Signals
Name Type Description
HLA_STB I/O
CMOS Hub interface A Strobe. One of two differenti al strobe si gnal s used to transmi t or
receive packet data over hub interface A .
HLA_STB# I/O
CMOS Hub interface A Strobe Compliment. One of two differenti al strobe signal s used
to transmit or receive packet data over hub interface A.
HLA[11:0] I/O
CMOS Hub interface A Signals: Signal s used for t he hub i nterface.
HLAZCOMP I/O
CMOS Impedance Compensation for hub interface A: Thi s signal is used to cali brat e
the hub interf ace A I/ O buffers. Thi s signal pi n must be connected t o a P CB trace
representative of the hub int erf ace A data s i gnal traces but sufficiently long t o
present a long shelf before signal reflection occurs. The hub interface A buf fers
are calibrat ed based on the m easured shelf vol tage.
2.5. Hub interface B Signals
Name Type Description
HLB_STB[1:0] I/O
CMOS
Hub interface B Strobe: One of two differenti al strobe si gnal s used to t rans mit
or receive packet data over hub interface B .
HLB_STB[1:0]# I/O
CMOS
Hub interface B Strobe Compliment: One of two differenti al strobe signal s
used to t rans mit or receive packet data over hub interface B.
HLB[19:0] I/O
CMOS
Hub interface B Signal s: Signals used for t he hub i nt erface.
HLBRCOMP I/O
CMOS
Resistor Compensation for hub i n terface B: HLBRCOMP is used to cali brate
the hub interf ace B I/O buffers. Thi s signal pin must be connected t o an external
resistor to ground with the value Z0/ 2. Z0 i s the PCB trace impedance used on
the hub interf ace B.
2.6. AGP Interface Signals
For more details on the operation of these signals, refer to the AGP Interface Specification , Revision 2.0.
2.6.1. AGP Addressing Signals
There are two mechanisms the AGP master can use to enqueue AGP requests: PIPE# and SBA (side-
band addressing). Upon initialization, one of the methods is chosen. The master may not switch methods
without a full reset of the system. When PIPE# is used to enqueue addresses, the master is not allowed to
queue addresses using the SBA bus. For example, during configuration time, if the master indicates that
it can use either mechanism, the configuration software will indicate which mechanism the master will
use. Once this choice has been made, the master continues to use the mechanism selected until the system
is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism
but rather a static decision when the device is first being configured after reset.
82840 MCH
R
Datasheet 27
Name Type Description
PIPE# I
AGP
Pipeline:
PIPE# Operation: This si gnal i s assert ed by the AGP master to indicat e a f ul l -width
adress is to be enqueued on by the t arget using the A D bus. One address i s placed in
the AGP request queue on each rising clock edge while PIP E# is as serted.
SBA Operation: This signal is not used if SBA (Si de B and Addressing) i s selec t ed.
FRAME# Operation: This signal is not used during AGP FRAME# operation.
SBA[7:0] I
AGP
Side-band Addressing:
PIPE# Operation: These signal s are not used during PIPE# operat i on.
SBA Operation: These signals (t he SBA, or side-band address i ng, bus) are used by
the AGP mast er (graphi cs component) t o pl ace addresses i nto the AGP request
queue. The SBA bus and AD bus operate i ndependently. That is, trans action can
proceed on the SBA bus and the AD bus simultaneously.
FRAME# Operation: These s i gnal s are not used during AGP FRAME# operati on.
2.6.2. AGP Flow Control Si gnal s
Name Type Description
RBF# I
AGP
Receive Buffer Full:
PIPE# and SBA Operation: Read buffer full i ndi cates if the m aster is ready t o accept
previously reques t ed l ow priorit y read dat a. When RBF# is assert ed, the MCH is not
allowed to initi at e the return low priority read data. Thus, t he MCH can finish ret urni ng
the data for the request c urrently being serviced; however, it c an not begin returning
data for the next reques t. RBF# is onl y sampl ed at the beginning of a cycle.
If the AGP m aster is al ways ready t o accept ret urn read data, it i s not required to
impl ement thi s signal.
FRAME# Operation: This signal is not used during AGP FRAME# operation.
WBF# I
AGP
Write-Buffer Full:
PIPE# and SBA Operation: W ri te bufff er full indic ates if t he master is ready to accept
Fast Wri te data from the MCH. When WBF# is asserted, t he MCH is not allowed to
drive Fast Wri te data to the AGP m aster. WB F # i s only sampled at the begi nni ng of a
cycle.
If the AGP m aster is al ways ready t o accept f ast write data, i t is not requi red to
impl ement thi s signal.
FRAME# Operation: This signal is not used during AGP FRAME# operation.
28 Datasheet
2.6.3. AGP Status Signals
Name Type Description
ST[2:0] O
AGP
Status Bus:
PIPE# and SBA Operation: These signals provi de i nformat i on from t he arbi ter to a AGP
Master on what it may do. ST [ 2 : 0] only have meani ng to the m aster when its GNT# i s
assert ed. When GNT# is deasserted, these signals have no meaning and must be
ignored. Refer t o the AGP I nterface Specificaiton, revi sion 2.0 for further explanation of t he
ST[2: 0] values and thei r meanings.
FRAME# Operation: These s i gnal s are not used during FRAME# based operation; except
that a ‘111’ i ndi cates t hat the m aster m ay begi n a FRAME# transac tion.
An external 8.2 KΩ pull up to Vddq is requi red on each ST[2: 0] signal, except S T 0. An
external 1 KΩ pulldown is needed on ST 0 f o r enabl i ng Host Bus ECC generation.
2.6.4. AGP Clocking Signals—Strobes
Name Type Description
AD_STB0 I/O
s/t/s
AGP
AD Bus Strobe-0:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this s i gnal provi des timing for the A D[15:0] and
C/BE[1:0]# signals. The agent that is providing t he dat a will drive this s i gnal.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the AD[15:0] and C/B E [1:0]# s i gnal s.
AD_STB0# I/O
s/t/s
AGP
AD Bus Strobe-0 Co mpliment:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this si gnal i s not used.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the AD[15: 0] and C/BE[1:0]# s i gnal s. The agent t hat is
providing the data will drive this signal.
AD_STB1 I/O
s/t/s
AGP
AD Bus Strobe-1:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this s i gnal provi des timing for the A D[31:16] and
C/BE[3:2]# signals. The agent that is providing t he dat a will drive this s i gnal.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the AD[31: 16] and C/BE[3:2]# s i gnal s. The agent t hat
is providing the data will drive this signal.
AD_STB1# I/O
s/t/s
AGP
AD Bus Strobe-1 Co mpliment:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this si gnal i s not used.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the AD[16: 31] and C/BE[2:3]# s i gnal s. The agent t hat
is providing the data will drive this signal.
82840 MCH
R
Datasheet 29
Name Type Description
SB_STB I
AGP
SBA Bus Strobe:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this s i gnal provi des timing for the SBA bus
signals. The agent that is driving the S BA bus will drive this signal.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the SBA bus signals. The agent t hat i s driving the
SBA bus will drive this signal.
SB_STB# I
AGP
SBA Bus Strobe Compliment:
1X Operation: This signal i s not used during 1X operation.
2X Operation: During 2X operation, this si gnal i s not used.
4X Operation: During 4X operation, this is one-half of a di f ferential s trobe pair that
provides ti ming inf ormation for the SBA bus signals. The agent t hat i s driving the
SBA bus will drive this signal.
2.6.5. AGP FRAME# Signals
For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate
similar to their semantics in the PCI 2.1 specification. The exact role of all AGP FRAME# signals are
defined below.
Name Type Description
G_FRAME# I/O
s/t/s
AGP
FRAME:
PIPE# and SBA Operation: Not used by AGP SBA and PIPE#, but used during AGP
FRAME# .
Fast Write Operation: G_FRAME# is used to fram e transact i ons as an output f rom
the MCH during Fast Writes.
FRAME# Operation: G_FRAME# is an output when the MCH acts as an initiator on
the AGP Interfac e. G_FRAME# is asserted by t he MCH to i ndi cate the beginni ng and
duration of an ac cess. G_FRAME# is an input when the MCH act s as a FRAME#
based AGP t arget. As a FRA ME# based AGP t arget, the MCH latches the
C/BE[ 3 : 0]# and the AD[31:0] signal s on the first clock edge on which it samples
FRAME# active.
G_IRDY# I/O
s/t/s
AGP
Initiator Ready:
PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and
PIPE #, but used during the data phase of P IPE# and SB A transac tions.
FRAME# Operation: G_IRDY# i s an output when MCH acts as a FRAME# based
AGP initiator and an input when the MCH acts as a FRAME# bas ed AGP target. The
assertion of G_IRDY# indicates the current FRAME# based AGP bus initiator's ability
to complete t he current data phas e of the transac tion.
Fast Write Operation: G_IRDY # i ndi cates t he AGP compliant mast er i s ready to
provide all write data f or the current t ransaction. Once G_IRDY # i s assert ed for a
write operation, t he mast er i s not allowed to ins ert wait states . The mas ter is never
allowed to insert a wait state during t he i ni tial data t ransfer (32 bytes ) of a write
transac tion. However, it may ins ert wait stat es after eac h 32 byte block i s transf erred.
30 Datasheet
Name Type Description
G_TRDY# I/O
s/t/s
AGP
Target Ready:
PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and
PIPE #, but used during the data phase of P IPE# and SB A transac tions.
FRAME# Operation: G_TRDY# is an input when the MCH acts as an AGP ini t i ator
and an output when the MCH acts as a FRAME# based A GP target. The as sertion of
G_TRDY# indicates the target’s ability to com plet e the current data phase of the
transaction.
Fast Write Operation: G_TRDY# indi cates t he AGP compliant target is ready to
receive write data f or t he entire transaction (when the trans fer size is l e ss than or
equal to 32 bytes) or is ready to transfer t he i ni tial or subs equent block (32 bytes) of
data when the transf er size is great er than 32 bytes. The target is al l owed to insert
wait states after eac h bl ock (32 bytes) is transferred on write trans actions.
G_STOP# I/O
s/t/s
AGP
Stop:
PIPE# and SBA Operation: This signal i s not used during P IPE# or SB A operation.
FRAME# Operation: STOP # i s an input when the MCH acts as a FRAME# based
AGP ini t i ator and an output when the MCH acts as a FRAME# bas ed AGP target .
STOP# is used for disconnect, retry, and abort sequences on the AGP interface.
G_DEVSEL# I/O
s/t/s
AGP
Device Select:
PIPE# and SBA Operation: This signal i s not used during P IPE# or SB A operation.
FRAME# Operation: DEVSEL#, when assert ed, indicat es that a FRA ME# based
AGP target device has decoded its addres s as the t arget of the c urrent acces s. The
MCH asserts DEVSEL# based on the DRAM addres s range being acc essed by a PCI
initiator. As an input it i ndi cates whether any devic e on the bus has been s el ected.
Fast Write Operation: G_DEV S EL# is used when the t ransaction cannot complete
during the bloc k data trans f er
G_REQ# I
AGP
Request:
SBA Operation: This s i gnal is not used during PIPE# or SBA operation.
PIPE# and FRAME# Operation: REQ#, when ass erted, indic ates that a FRA ME# or
PIPE # based AGP master i s requesting use of the A GP interface. This signal is an
input int o the MCH.
G_GNT# O
AGP
Grant:
SBA, PIPE# and FRAME# Operation: GNT# along with the inf ormation on t he
ST[2:0] signals (status bus) indicates how the AGP interface will be used next. Refer
to the AGP Interfac e S pecific ai ton, revis i on 2. 0 for further explanation of the ST[ 2:0]
values and thei r meanings.
G_AD[31:0] I/O
AGP
Address/Data Bus:
PIPE# and FRAME# Operation: AD[ 31:0] are used t o t ransfer both addres s and
data information on t he AGP inteface.
SBA Operation: AD[ 31:0] are used t o t ransfer data on t he AGP interf ace.
82840 MCH
R
Datasheet 31
Name Type Description
G_C/BE[3:0]# I/O
AGP
Command/Byte Enable:
FRAME# Operation: During the address phase of a transact i on, C/BE[3:0]# def i ne
the bus c omm and. During the data phase, C/BE[3:0]# are used as byte enabl es. The
byte enables determine which byte lanes ca rry meaningful dat a. The commands
issued on the C/BEx# signal s during FRAME# based AGP are the s ame C/BEx#
com mand desc ri bed i n the PCI 2.1 specifi cation.
PIPE# Operati on: When an address i s enqueued using PIPE#, the C/BEx# signal s
carry comm and i nformat i on. Refer to t he A G P 2.0 Interf ace Speci f i cation Revision
2.0 for the definition of these c omm ands. The command encoding used during P IPE#
based AGP i s Different than t he command encoding used during FRAME# based
AGP c yc l es (or standard P CI cycles on a PCI bus).
SBA Operation: These signals are not used during SBA operation.
G_PAR I/O
AGP
Parity:
FRAME# Operation: G_PAR i s driven by the MCH when it acts as a FRAME# bas ed
AGP initiator during addres s and data phases for a write cycl e, and during the
address phas e for a read cycle. PAR is driven by the MCH when it acts as a
FRAME# based AGP target during each data phase of a FRA ME# based AGP
memory read cycl e. Even parity is generated across AD[31:0] and C/B E [3:0]#.
SBA and PIPE# Operati on: This si gnal i s not used during S BA and PIP E#
operation.
G_SERR# I
AGP
System Error: G_SERR# c an be pul sed to report a s ys tem error c ondi tion. Upon
sam pl i ng G_SERR# act i ve, the MCH can generate a hub int erf ace SERR c ycle to the
ICH.
NOTES:
1. PCIRST# from t he I CH i s connect ed to RSTIN# and is used to res et AGP int erface logic within the MCH. The
AGP agent will also use P CI RS T# provided by the I CH as an input to reset its internal logic.
2. The LOCK# Signal i s NOT supported on t he A G P i nterface, even f or FRAME based AGP operat i ons.
3. The PERR# Signal i s NOT supported on t he A G P i nterface.
2.7. Clocks, Reset, and Miscellaneous
Name Type Description
CPUCLK I
CMOS Host Clock In: CPUCLK rec ei ves a buffered host clock f rom the external c l ock
synthesi zer. Thi s cloc k is us ed by al l of the MCH logic that is in t he Host cl ock
domain.
Note that the clock synthes i zer drives this signal to 2. 5V.
CLK66 I
CMOS 66MHz Clock In: . CLK66 receives a buffered clock from the cl ock synt hesizer
that is synchronously deri ved f rom the hos t clock . Thi s cloc k is used by al l of the
MCH logic that i s in the AGP clock domai n.
Note that the clock synthes i zer drives this signal to 3. 3V, and this input is 3.3V
tolerant.
RCLKOUT[A,B] O
CMOS Rambus Clo ck Ou t: RCLKOUT[A ,B] provide di vi ded down versions of the
Rambus * clock as feedback to the Ram bus* clock synthes i zers for phase
alignment.
Note that this pin will only be driven to 1.8V.
HCLKOUT[A,B] O
CMOS Host Clock Out: HCLK OUT[A,B] provide divided down versions of the host clock
as feedbac k to the Rambus* cl ock synt hesizers for phas e al i gnment.
Note that this pin will only be driven to 1.8V.
32 Datasheet
Name Type Description
RSTIN# I
CMOS Reset In: When as serted, RS TI N# asynchronousl y res ets the MCH logic . This
signal is connect ed to the PCIRS T # output of t he I CH. All AG P output and bi-
directional si gnals will also tri-s tate compliant to PCI Rev 2.0 and 2.1
specificati ons.
Note that this input needs to be 3.3V t ol erant.
TEST# I
CMOS Test Input: This pin is us ed for manuf acturing and board level test purpos es.
OVERT# I
CMOS Overtemperature condition: An active low input s i gnal generated by external
hardware to indicated the overtem perature conditi on i n the memory subs ystem.
2.8. Voltage References, PLL Power
Signal Nam e Description
GTLREF[A:B] GTL Reference: Reference voltage input for the Host GTL i nterface.
AGPRCOMP AGP RCOM P : AGPRCOMP i s used to cali brate AGP GTL I/O buffers. This si gnal must be
connect ed t o a PCB trace representative of the AGP bus dat a signal trac es but suf ficient l y
long to present a l ong shelf before signal reflection oc curs. The AG P buffers are c al i brated
based on the measured shel f voltage.
CHA_REF[1:0] Rambus Channel A Reference: Reference voltage input for the Ram bus* Channel A RSL
interface.
CHB_REF[1:0] Rambus Channel B Reference: Reference voltage input for the Ram bus* Channel B RSL
interface.
AGPREF AGP Reference: Referenc e vol tage input for t he AGP interface.
HLAREF hub interface A Reference: Ref e rerence voltage input f or the hub interface.
HLBREF hub interface B Reference: Ref ererence voltage input for the hub int erface.
VCC1_8 1.8V Power Supply: The 1.8v power input pin
VDDQ AGP I/O Power Supply: The power supply input for t he AGP I/ O supply.
VTT AGTL+ 1.5V Volatage: The GTL+ bus 1.5v termination vol t age i nputs.
VSS Ground:
82840 MCH
R
Datasheet 33
2.9. Strap Signals
This section provides the strap options invoked by various MCH signal pins.
Name Definition
HLA10 Host Bus Frequency: This signal i s latched on t he ri sing edge of RSTIN#. It i ndi cates what the
host FSB frequency is to select the correct internal frequency ratios. Thi s value can be read from
the MCHCFG register. There is no int ernal pul l up or pul l down resistor.
HLA10 Host Bus Frequency
0 100 MHz
1 133 MHz
HA7# CP U Bus I n -Order Queue Depth: The value on HA7# is sampled by all host bus agents (i ncluding
the MCH) on the risi ng edge of CPURST#. It’s l atched value determines t he maximum IOQ depth
mode s upported on the host bus. If HA7# is sampled low the IOQ dept h on the bus is one. If HA7#
is sampled high, t he IOQ depth on the bus i s the m axim um of eight. When the I OQ depth on the
bus is set to 8, t he MCH does not lim i t the num ber of queued transac t i ons, si nce it supports an
IOQ depth of 8.
The MCH does not drive HA7# during CPURST#. If an IOQ depth of 1 i s desired, HA 7# needs to
be driven low during CPURST# by external logic.
ST0 Host Bus ECC Generation: ST0 is lat ched on the risi ng edge of RSTIN#. It is used to enable the
data ECC protection coveri ng HD[63:0]#. Thi s value can be read from the HE RRCTL regi ster.
There is no int ernal pul l up or pul l down resistor.
To strap for Host Bus ECC enabled, a 1 KΩ pul l down should be connected t o S T 0. ST0 shoul d
have a 8.2 KΩ external pullup resistor to Vddq to disable the Hot B us ECC generation.
ST0 ECC Generation on DEP[7:0]#
0 Enable (external 1 K Ω pul l down)
1 Disabl e (external 8.2 KΩ pullup))
34 Datasheet
This page is left intentionally blank.
82840 MCH
R
Datasheet 35
3. Register Description
This chapter describes the MCH PCI configuration registers. A detailed bit description is provided. The
MCH contains two sets of software accessible registers, accessed via the Host I/O address space:
• Control registers I/O mapped into the host I/O space, which control access to PCI and AGP
configuration space (see section entitled I/O Mapped Registers)
• Internal configuration registers residing within the MCH are partitioned into two logical device
register sets (“logical” since they reside within a single physical device). The first register set is
dedicated to Ho st-Hub interface Bridge/DRAM Controller functionality (controls PCI_A i.e.
DRAM configuration, other chip-set operating parameters and optional features). The second
register block is dedicated to Host-AGP B ridge functions (controls AGP interface configurations
and operating parameters).
The MCH supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.
The MCH internal registers (both I/O Mapped and Configuration registers) are accessible by the host.
The registers can be accessed as Byte, Word (16-bit), or DW ord (32-bit) quantities, with the exception of
CONF_ADDR which can only be accessed as a Dword. All multi-byte numeric fields use "little-endian"
ordering (i.e., lower addresses contain the least significant parts of the field).
3.1. Register Nomenclature and Access Attributes
Symbol Description
RO Read Only. If a register is read only, writes to this register have no effect.
R/W Read/Write. A register with this attribute can be read and written
R/W/L Read/Write/Lock. A register with this attribute can be read, written, and Lock.
R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a
write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
R/WO Read/Write Once. A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only.
L Lock. A register bit with this attribute beco mes Read Only after a lock bit is set.
Reserved
Bits Software must deal correctly with fields that are reserved. On reads, software must use
appropr iate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, software must ensure that the values of reserved bit p ositions
are preserved. That is, the values of reserved bit positions must first be read, merged
with the new values for other bit positions and then written back. Note that software does
not need to perform read, merge, write operation for the configuration address register.
36 Datasheet
Symbol Description
Reserved
Registers In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-hub interface A Bridge/DRAM Controller, Host-AGP
Bridge and Host-Hub interface B Bridge entities that are marked “Reserved”. When a
“Reserved” register location is read, a random value can be returned. (“Reserved”
registers can be 8-, 16-, or 32-bit in size). Registers that are marked “Reserved” must
not be mod ified by system software. Writes to “Reserved ” registers may cause system
failure.
Default
Value
Upon
Reset
Upon a Full Reset, the MCH sets all of its internal configuration registers to
predetermined default states. Upo n a P artial Reset some of the MCH configuration
register bits associated with DRAM configuration are not reset. These register bits are
identified in the bit descriptions below. Some register values at reset are determined by
external strapping options. The default state represents the minimum functionality
feature set required to successfully bring up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization software
(usually BIOS) to p r operly determine the DRAM configurations, operating parameters
and optional system features that are applicable, and to program the MCH registers
accordingly.
3.2. PCI Configuration Space Access
The MCH and the ICH are physically connected by hub interface A. From a configuration standpoint,
hub interface A is logically PCI bus #0. As a result, all devices internal to the MCH and ICH appear to
be on PCI bus #0. The system’s primary PCI expansion bus is physically attached to the ICH and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and,
therefore, has a programmable PCI Bus number.
Note: The primary PCI bus is referred to as PCI_A in this document and is not PCI bus #0 from a configuration
standpoint. The secondary hub interface port appears to system software to be a real PCI bus behind a
PCI-to-PCI bridge resident as device 2 on PCI bus #0.
The MCH contains three PCI devices within a single physical component. The configuration registers for
devices 0, 1, and 2 are mapped as devices residing on PCI bus #0.
• Device 0: Host-hub interfa ce A Bridge/DRAM Controller. Logically this appears as a PCI
device residing on PCI bus #0. Physically Device 0 contains the standard PCI registers, DRAM
registers, the Graphics Aperture controller, and other MCH specific registers.
• Device 1: Host-AGP Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge residing on
PCI bus #0. Physically Device 1 contains the standard PCI-to-PCI bridge registers and the standard
AGP configura t ion registers (including the AGP I/O and memory address mapping).
• Device 2 Host - hub int erface B Bridg e . Logically this bridge appears to be a PCI-to-PCI br idge
device residing on PCI bus #0. Physically, device 2 contains the standard PCI-to-PCI registers.
Note: A physical PCI bus #0 does not exist. The hub interface and the internal devices in the MCH and ICH
logically constitute PCI Bus #0 to configuration software.
82840 MCH
R
Datasheet 37
PCI Bus Configurat i on Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions, with each function containing up to 256 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported
by a mapping mechanism implemented within the MCH. The PCI specification defines two mechanisms
to access configuration space, Mechanism #1 and Mechanism #2. The MCH supports only
Mechanism #1.
The configuration access mechanism makes use of the CONF_ADDR Register and CONF_DATA
Register. T o reference a configuration register a DWord I/O write cycle is used to place a value into
CONF_ADDR that specifies:
• The PCI bus
• The device on that bus
• The function within the device
• A specific configuration register of the device function being accessed.
CONF_ADDR[31] must be 1 to enable a configuration cycle. CONF_DATA then becomes a window
into the four bytes of configuration space specified by the contents of CONF_ADDR. Any read or write
to CONF_DATA will result in the MCH translating the CONF_ADDR into the appropriate configuration
cycle.
The MCH is responsible for translating and routing the processor I/O accesses to the CONF_ADDR and
CONF_DATA registers to internal MCH configuration registers, the hub interfaces or AGP.
Routing Confi gurat ion Accesses to Primary PCI (PCI_A), or AGP
The MCH supports three bus interfaces: hub interface A, hub interface B, and AGP. PCI configuration
cycles are selectively routed to one of these interfaces. The MCH is responsible for routing PCI
configuration cycles to the proper interface. PCI configuration cycles to ICH internal devices and PCI_A
(including downstream devices) are routed to the ICH via the hub interface A. AGP configuration cycles
are routed to AGP. PCI configuration cycles to P64H are routed to hub interface B. The AGP interface is
treated as a separate PCI bus from the configuration point of view. Routing of configuration accesses to
both hub interface B and AGP is controlled via the standard PCI-PCI bridge mechanism using
information contained within the Primary Bus Number, the Secondary Bus Number, and the Subordinate
Bus Number registers of the Host-AGP internal “virtual” PCI-PCI bridge device.
38 Datasheet
Logical PCI Bus #0 Conf iguration Mechani sm
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONF_ADDR
register. If the Bus Number field of CONF_ADDR is 0 the configuration cycle is targeting a PCI Bus #0
device.
• The Host-hub interface A Brid ge/DRAM Controller entity within the MCH is hardwired as
Device 0 on PCI Bus #0.
• The Host-AGP Bridge entity within the MCH is hardwired as Device 1 on PCI Bus #0.
• The Host-hub interface B bridge entity within the MCH is hardwired as Device 2 on P CI B us #0 .
Configuration cycles to the MCH internal devices are confined to the MCH and not sent over the hub
interface. Accesses to devices #3 to #31 will be forwarded over the hub interface A.
Primary PCI (PCI_A) and Downstream Conf i gurat i on Mechanism
If the Bus Number in the CONF_ADDR is non-zero, and is less than the value programmed into both of
the MCH’s device 1 and device 2 Secondary Bus Number register or greater than the value programmed
into the Subordinate Bus Number Register, the MCH will generate a Type 1 configuration cycle over hub
interface A. The ICH compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle is meant for
Primary PCI (PCI_A), or a downstream PCI bus.
AGP Bus Configurat ion Mechanism
From the chipset configuration perspective, AGP is seen as another PCI bus interface residing on a
Secondary Bus side of the “virtual” PCI-PCI bridge referred to as the MCH Host-AGP bridge. On the
Primary bus side, the “virtual” PCI-PCI bridge is attached to PCI Bus #0. Therefore the Primary Bus
Number register is hardwired to “0”. The “virtual” PCI-PCI bridge entity converts Type #1 P CI Bus
Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP interface.
Type 1 configuration cycles on PCI Bus #0 that have a BUS NUMBER that matches the Secondary Bus
Number of the MCH Host-AGP bridge will be translated into Type 0 configuration cycles on the AGP
interface.
if the Bus Number is non-zero, greater than the value programmed into the Secondary Bus Number
register, and less than or equal to the value programmed into the Subordinate Bus Number register, the
MCH will generate a Type 1 PCI configuration cycle on AGP.
82840 MCH
R
Datasheet 39
3.3. I/O Mapped Registers
The MCH contains a set of registers that reside in the host I/O address space − the Confi guration Addr ess
(CONF _ADDR) Register and the Configura t ion Data (CONF_DATA) Register. The Configurat i on
Address Register enables/disables the configuration space and determines what portion of configuration
space is visible through the Configuration Data window.
3.3.1. CONF_ADDR
Configuration Address Register
I/O Address: 0CF8h Accessed as a DWord
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
CONF_ADDR is a 32 bit register accessed only when referenced as a DWord. A Byte or Word reference
will "pass through" the Configuration Add ress Register and the hub interface onto the PCI0 bus as an I/O
cycle. The CONF_ADDR register contains the Bus Number, Device Number, Function Number, and
Register Number for which a subsequent configuration access is intended.
Bit Descriptions
31 Configuration Enable (CFGE): This bi t controls access to PCI s pace.
1 = Enable.
0 = Disable.
30:24 Reserved (These bits are read only and have a value of 0).
23:16 Bus Num b er: When the B us Number is programmed to 00h, the target of t he PCI confi guration cycl e
is a hub int erface agent (MCH, I CH, etc. ).
The configuration cycle i s forwarded to hub interf ace A if t he Bus Num ber i s programmed to 00h and
the MCH is not the target (t he devi ce number i s ≥ 3).
If the Bus Num ber i s non-zero and matches t he val ue programmed into the S econdary Bus Number
Register of Device 1, a Type 0 PCI configuration cycl e will be generated on AGP .
If the Bus Num ber i s non-zero, greater t han the value in the S econdary Bus Number register of
Device 1, and l ess than or equal to the value programmed i nto the Subordinat e Bus Num ber Regi ster
of Device 1, a Type 1 P CI c onfiguration cycl e will be generated on AGP .
If the Bus Num ber i s non-zero and matches t he val ue programmed into the S econdary Bus Number
Register of Device 2, a Type 0 PCI c onf iguration cycle will be generated on hub interf ace B.
If the Bus Num ber i s non-zero, greater t han the value in the S econdary Bus Number register of
Device 2, and l ess than or equal to the value programmed i nto the Subordinat e Bus Num ber Regi ster
of Device 2, a Type 1 P CI configuration cyc l e will be generated on hub interface B.
If the Bus Number is non-zero and does not fall withi n the ranges enum erated by Device 1 and Device
2’s Secondary Bus Number or Subordinat e B us Number Regi ster, a hub interface A Conf i guration
Cycle is generated.
40 Datasheet
Bit Descriptions
15:11 Device Numb er: This f i el d selects one agent on the PCI bus selected by the B us Number. When the
Bus Number field i s “00”, the MCH decodes the Devic e Number fiel d. The MCH is always Devic e
Number 0 f or the Host-hub interface A bri dge entity, Devi ce Number 1 f o r t he Host-AGP entity, and
Device Number 2 for the Hos t-hub interface B entity. Therefore, when the B us Number =0 and t he
Device Number=0, 1, or 2 t he i nternal MCH devices are select ed. Note that A D11, AD12, and AD13
mus t not be connec ted to any other PCI_A bus device as IDSEL signals.
If the Bus Num ber is non-zero and m atches t he val ue programmed into the S econdary Bus Number
Register, a Type 0 P CI configuration cycle will be generated on AGP. The MCH decodes the Device
Number f i el d [ 15:11] and ass erts the appropriate GAD signal as an IDSEL. For PCI-to-P CI Bridge
translat i on, one of 16 IDSE Ls are generated. When bit [15] = 0, bi ts [14: 11] are decoded to as sert a
single A D[ 31:16] IDSEL. GAD16 is assert ed to access Device 0, GAD17 for Device 1, and so f orth up
to Device 16 which asserts AD31. Al l devi ce numbers hi gher than 16 cause a type 0 configurat i on
acces s with no IDSE L asserted, which results i n a Mas ter Abort reported i n the MCH’s “virtual ” PCI-
PCI bridge registers.
For Bus Numbers resul ting in hub interface A or hub interface B configurati on cycles, the MCH
propagates t he Devi ce Number f i el d as A[15: 11].
10:8 Function Number: This field is mapped to GA D[ 10:8] during AGP Configurati on cycles and A [10:8]
during hub interface A or hub interface B c onf i guration cycl es. This al l ows t he configurati on regi sters
of a particular funct ion in a mul ti-funct i on device to be ac cessed. The MCH ignores configurati on
cycles to it’s two internal devices if the functi on number is not equal to 0.
7:2 Register Number: Thi s field selects one register withi n a particular B us, Device, and Function as
specified by the other f i el ds in the Confi guration Address Register. This fi el d i s mapped t o GAD[7:2]
during AGP Conf i guration cycl es and A[7: 2] duri ng hub i nterface A or hub i nterface B Conf i guration
cycles.
1:0 Reserved.
3.3.2. CONF_DATA—Configuration Data Register
I/O Address: 0CFCh
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
CONF_DATA is a 32 bit read/write window into configuration space. The portion of configuration space
that is referenced by CONF_DATA is determined by the contents of CONF_ADDR.
Bit Descriptions
31:0 Configuration Data Window (CDW): If bit 31 of CONF_ADDR is 1, any I/O acc e ss to t he
CONF_DATA register will be mapped to conf iguration space us ing the contents of CONF_ADDR.
82840 MCH
R
Datasheet 41
3.4. Host-Hub interface A Bridge/DRAM Controller Device
Registers (Device 0)
An “s” in the Default Value field means that the power-up default value for that bit is determined by a
strap.
Table 2. MCH Configuration Space (Device 0)
Address
Offset Symbol Register Name Default Access
00–01h VID Vendor Identification 8086h RO
02–03h DID Device Identification 1A21h RO
04–05h PCICMD PCI Command 0006h R/W
06–07h PCISTS PCI Status 0090h/0080h RO, R/WC
08h RID Revision Identification 00h RO
0Ah SUBC Sub-Class Code 00h RO
0Bh BCC Base Class Code 06h RO
0Dh MLT Master Latency Timer 00h R/W
0Eh HDR Header Type 00h R/W
10–13h APBA SE Aperture Base Conf i gurat i on 00000008h R/W
2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2E–2Fh SID Subsystem Identification 0000h R/WO
34h CAPPTR Capabilities Pointer A0h / 00h RO
40–4Fh GAR[0:15] RDRAM Group Archit ecture Regis t er [15:0] 80h R/W
50–51h MCHCFG MCH Configuration 00ss00000000
0s00b R/WO,R/W
52–57h — Reserved — —
58h FDHC Fixed DRAM Hole Control 00h R/W
59–5Fh PAM[0:6] Programm abl e Attribut e Map [0:6] 00h R/W
60–61h GBA0 RDRAM Group Boundary Address 0 0001h R/W
62–63h GBA1 RDRAM Group Boundary Address 1 0001h R/W
64–65h GBA2 RDRAM Group Boundary Address 2 0001h R/W
66–67h GBA3 RDRAM Group Boundary Address 3 0001h R/W
68–69h GBA4 RDRAM Group Boundary Address 4 0001h R/W
6A–6Bh GBA5 RDRAM Group Boundary A ddress 5 0001h R/W
6C-6Dh GB A6 RDRAM Group Boundary A ddress 6 0001h R/W
6E–6Fh GBA7 RDRA M Group Boundary Address 7 0001h R/W
70–71h GBA8 RDRAM Group Boundary Address 8 0001h R/W
72–73h GBA9 RDRAM Group Boundary Address 9 0001h R/W
42 Datasheet
Address
Offset Symbol Register Name Default Access
74–75h GBA10 RDRAM Group Boundary Address A 0001h R/W
76–77h GBA11 RDRAM Group Boundary Address B 0001h R/W
78–79h GBA12 RDRAM Group Boundary Addres s C 0001h R/W
7A–7Bh GBA13 RDRA M Group Boundary Address D 0001h R/ W
7C–7Dh GBA14 RDRAM Group B oundary A ddress E 0001h R/W
7E–7Fh GBA15 RDRAM Group Boundary Addres s F 0001h R/W
80–87h — Reserved — —
88h RDPS RDRAM Pool S i zing Register 10h R/W
89–8Fh — Reserved — —
90–93h DRD RDRAM Device Register Data 0000h R/W
94–97h
94–96h
RICM or
—
RDRAM Initi al i zat i on Control Management
Reserved
0000_0000h
—
R/W
—
98–9Ch — Reserved — —
9Dh SMRAM Sys t em Management RAM Control 02h R/W
9Eh ESMRAMC Extended System Management RAM Control 38h R/W
9Fh — Reserved — —
A0–A3h ACAPID AGP Capability Identifier 00200002h
/00000000h RO
A4–A7h AGPSTAT AGP Status Register 1F000217h RO
A8–ABh AGPCMD AGP Command Register 00000000h RW
AC–AFh — Reserved — —
B0–B3h AGPCTRL AGP Control Register 00000000h R/W
B4h APSIZE Aperture Size 00h R/W
B5–B7h — Reserved — —
B8–BBh ATTB A SE A pert ure Translation Table 00000000h R/W
BCh AMTT AGP MTT Control Regi s ter 00h R/W
BDh LPTT AGP Low Priority Transac t i on Ti mer Reg. 00h R/W
BEh RDT RDRAM Timing 00h R/W
BFh DRAMRC RDRAM Refresh Cont rol 00h R/W
C0–C3h — Reserved — —
C4–C5h TOM Top of Low Memory 0000h R/W
C6–C7h — Reserved 0000h —
C8–C9h ERRSTS Error Status Regi ster 0000h R/WC
CA–CBh ERRCMD Error Com mand Register 0000h R/W
CC–CDh SMICMD SMI Command Register 0000h R/W
CE–CFh SCICMD SCI Command Register 0000h R/W
82840 MCH
R
Datasheet 43
Address
Offset Symbol Register Name Default Access
D0–DDh — Reserved — —
DE–DFh SKPD Scratchpad Data 0000h R/W
E0–E1h HERRCTL_STS Host Error Control /Status 0000h R/W, R/WC
E2–E3h DERRCTL_STS DRAM ERROR Control/S t atus 0000h R/W,R/WC
E4–E7h EAP Error Address Pointer 0000h R/W
E8–EBh A GPBCTRL AGP Buffer Strength Control 0000h R/W
EC–F5h — Reserved — —
F6 A G P APPEND A G P Append Disable 00h R/W
F7 GTLNCLAMP GTL N Clamp Di sable 00h R/W
F8–FFh — Reserved — —
44 Datasheet
3.4.1. VID—Vendor Identi fi cation Register (Device 0)
Address Offset: 00–01h
Default Value: 8086h
Attribute: Read Only
Size: 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the
Device Identification Register uniquely identify any PCI device. Writes to this register have no effect.
Bit Description
15:0 Vendor Identification Number. This i s a 16-bit value as signed to Intel. Int el VID = 8086h.
3.4.2. DID—Device Identification Register (Device 0)
Address Offset: 02–03h
Default Value: 1A21h
Attribute: Read Only
Size: 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Writes to this register have no effect.
Bit Description
15:0 Device Id enti fication Number. Thi s is a 16 bit value assi gned to the MCH Host-hub interface A
Bridge/DRA M Control l er Function #0.
DID = 1A21h for the MCH device 0.
82840 MCH
R
Datasheet 45
3.4.3. PCICMD—PCI Command Register (Device 0)
Address Offset: 04–05h
Default: 0006h
Access: Read/Write, Read Only
Size 16 bits
Since MCH Device 0 does not physically reside on PCI0 many of the bits are not implemented. Writes to
Not Implemented bits have no affect.
Bit Descriptions
15:10 Reserved.
9 Fast Back-to-Back—RO: (Not Implemented). Hardwired to 0. This bit controls whether or not t he
mas ter can do fas t back-t o-back writes. Since Device 0 is strict l y a t arget, this bit is not impl emented.
8 SERR Enable (SERRE)—R/W: Thi s bit is a gl obal enabl e bi t for Device 0 SERR m essaging. The
MCH does not have an SERR# signal. The MCH comm uni cates the SERR# condi tion by sending a
SERR message to the ICH.
1 = Enable. The MCH is enabl ed t o generate SERR messages over the hub interface for s pecific
Device 0 error condi tions t hat are i ndi vi dual ly enabled in the ERRCMD regis ter. The error st atus is
reported in the ERRSTS and PCISTS registers.
0 = The SERR message i s not generated by the MCH f or Devi ce 0.
NOTE: This bit only controls SERR m essage for t he Devi ce 0. Devic es 1 and 2 have their own
SERRE bi ts to c ontrol error reporting f or error conditions occurring on their respec tive devices .
7 Address/Data Stepping—RO: (Not Implemented). Hardwired to 0. Addres s/data s t eppi ng i s not
impl emented in the MCH.
6 Parity Error E n abl e (P ERRE)—R/W:
1 = Detect i on of a parity error by the MCH on the hub i nterface A results in an SERR message bei ng
sent t o t he ICH, if the SERRE bi t (bit 9 of this regis ter) is also set.
0 = Parity errors detected on hub interface A by t he MCH do not result in an S E RR message.
5 VGA Palette Snoop—RO: (Not Implemented). Hardwired to 0.
4 Memory Write and In val idate Enable(MW IE)—RO: (Not Implemented). Hardwired to 0.
3 Special Cycle Enable(SCE)—RO: (Not Implemented). Hardwired to 0.
2 Bus Master En abl e (BME) —RO: (Not Implemented). Hardwired to 1. The MCH is always enabled
as a m aster on hub interface A.
1 Memo ry Access Enable (MAE) —RO: (Not Implemented). Hardwired to 1. The MCH always all ows
access to main memory.
0 I/O Access Enable (IOAE)—RO: (Not Implemented). Hardwired to a 0.
46 Datasheet
3.4.4. PCISTS—PCI Status Register (Device 0)
Address Offset: 06–07h
Default Value: 0090h
Access: Read Only, Read/Write Clear
Size: 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s on the hub
interface. Bits 15:12 are read/write clear. All other bits are Read Only. Since the MCH Device 0 is the
Host-to-hub interface A bridge, many of the bits are not implemented.
Bit Descriptions
15 Detected Parity Error (DPE)—R/WC:
1 = The MCH detects a pari ty error on the hub interface A.
0 = Software clear this bit by writi ng a 1 t o i t.
14 Signaled System Error (SSE)—R/WC:
1 = The MCH Device 0 generates a S ERR mes sage over the hub interface A f or any enabl ed
Device 0 error condition. Devi ce 0 error condit i ons are enabled in the P CICMD and ERRCMD
registers. Device 0 error flags are read/reset from the PCISTS or ERRSTS regi sters.
0 = Software clears this bi t by writing a 1 to it .
13 Received Master Abort Status (RMAS)—R/WC:
1 = This bit i s set when the MCH generates a request over the hub interface A and receives a Mast er
Abort completi on packet.
0 = Software clears this bi t by writing a 1 to it .
12 Received Target Abort Status (RTAS)—R/WC:
1 = The MCH generates a request over the hub interface A and receives a Target Abort completi on
packet.
0 = Software clears this bi t by writing a 1 to it .
11 Signaled Target Abort Status (STAS)—RO: (Not Implemented). Hardwired to a 0. The MCH does
not generate a Target Abort completion packet over t he hub i nterface A .
10:9 DEVSEL# Timing (DEVT)—RO: (Not Implemented). Hardwired to a 00. The Hub Interfac e does not
use DEVSEL# protoc ol .
8 Data Parity Detected (DPD)—RO: (Not Implemented). Hardwired to 0.
7 Fast Back-to-Back (FB2B)—RO: (Not Implemented). Hardwired to 1.
6:5 Reserved.
4 Capability List (CLIST)—RO:
1 = Indicates to t he configurati on software that t hi s device/function i mplements a l i st of new
capabilities. A list of new capabilities is acces s ed via register CAPP TR at configuration address
offs et 34h. Register CAPPTR contains an offset pointing to the start addres s within confi guration
space of this device where the AGP Capabilit y s tandard register resi des.
3:0 Reserved.
82840 MCH
R
Datasheet 47
3.4.5. RID—Revision Identification Register (Device 0)
Address Offset: 08h
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the revision number of the MCH Device 0. These bits are read only and writes to
this register have no effect.
Bit Description
7:0 Revisi on I d entification Number. This is an 8-bit value t hat indicat es the revisi on i dentific ation number
for the MCH Devic e 0.
For the A-0 St eppi ng, this val ue i s 00h.
3.4.6. SUBC—Sub-Class Code Register (Device 0)
Address Offset: 0Ah
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the MCH Device 0. This code is 00h indicating a Host
Bridge device. The register is read only.
Bit Description
7:0 Sub-Cl ass Code (SUBC). This i s an 8-bit value t hat indicat es the cat egory of Bridge for the MCH.
00h = Host Bri dge.
3.4.7. BCC—Base Class Code Register (Device 0)
Address Offset: 0Bh
Default Value: 06h
Access: Read Only
Size: 8 bits
This register contains the Base Class Code of the MCH Device 0.
Bit Description
7:0 Base Class Code (BASEC): This i s an 8-bit value t hat indicat es the Bas e Cl ass Code for t he MCH.
06h = Bridge device.
48 Datasheet
3.4.8. MLT—Master Latency Timer Register (Device 0)
Address Offset: 0Dh
Default Value: 00h
Access: Read Only
Size: 8 bits
The hub interface does not use a Master Latency Timer. Therefore, this register is not implemented.
Bit Description
7:0 These bit s are hardwired to 0. Writ es have no effec t .
3.4.9. HDR—Header Type Register (Device 0)
Offset: 0Eh
Default: 00h
Access: Read Only
Size: 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit Descriptions
7:0 This read onl y f i el d al ways ret urns 0 when read and writes have no affec t .
3.4.10. APBASE—Aperture Base Configuration Register (Device 0)
Offset: 10–13h
Default: 00000008h
Access: Read/Write, Read Only
Size: 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration register
such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or
behave as hardwired to 0). To allow for flexibility (of the aperture), an additional register called APSIZE
is used as a “back-end” register to control which bits of the APBASE will behave as hardwired to 0. This
register is programmed by the MCH specific BIOS code that runs before any of the generic configuration
software is run.
Note: Bit 9 of the MCHCFG register is used to prevent accesses to the aperture range before this register is
initialized by the configuration software and the approp r iate translation table structure has been
established in the main memory.
82840 MCH
R
Datasheet 49
Bit Description
31:28 Upper Programmable Base Address bits—R/W: These bits are used to locate the range size
selected via bits 27:4 of this register. Default = 0000
27:22 Lower “Hardw i r ed” /Programmable Base Address bits: These bits behave as a “hardwired” or as a
programmable depending on the contents of the APSIZE regist er as defined below:
27 26 25 24 23 22 Aperture Size
r/w r/w r/w r/w r/w r/w 4 MB
r/w r/w r/w r/w r/w 0 8 MB
r/w r/w r/w r/w 0 0 16 MB
r/w r/w r/w 0 0 0 32 MB
r/w r/w 0 0 0 0 64 MB
r/w 0 0 0 0 0 128 MB
0 0 0 0 0 0 256 MB
Bits 27:22 are controll ed by bi ts 5:0 of the APSIZE regis ter in the fol l owing manner:
If bit APSIZE[5]=0, APBASE[ 27] =0; if APSI ZE[ 5]=1, APBASE[ 27] =r/ w (read/write). The same applies
correspondingl y to other bits.
Default for APSIZE[5:0] =000000b f orc ing def ault APBASE[27:22] =000000b (i.e. , all bits respond as
“hardwired” to 0). This provides a default to the m aximum apert ure size of 256 MB. The MCH specific
BIOS i s responsib l e f or a select i ng small er size (if requi red) bef ore PCI conf i gurat i on software runs and
establi shes the s ys tem addres s map.
21:4 Hardwired to 0s. This forces minimum aperture size sel ected by thi s register to be 4 MB.
3 Prefetchable—RO: Hardwired to 1.
1 = Prefetchable (i.e. , there are no side effects on reads, t he devi ce returns al l byt es on reads
regardless of the byte enables, and the MCH may merge proc essor writes i nto this range without
causing errors).
2:1 Type—RO: Hardwired to 00. These bit s determ i ne addressing type.
00 = Address range defined by the upper bit s of this register can be locat ed anywhere in the 32-bit
address s pace.
0 Memory Space Indicator—RO: Hardwired to 0.
0 = Memory range (Apert ure range i s a memory range).
50 Datasheet
3.4.11. SVID—Subsystem Vendor I D (Device 0)
Offset: 2C–2Dh
Default: 0000h
Access: Read/Write Once
Size: 16 bits
This value is used to identify the vendor of the subsystem.
Bit Description
15:0 Subsystem Vendor ID—R/WO: The defaul t value is 00h. Thi s field s houl d be programm ed duri ng boot -
up. After this field is writt en once, it becomes read only.
3.4.12. SID—Subsystem ID (Device 0)
Offset: 2E–2Fh
Default: 0000h
Access: Read/Write Once
Size: 16 bits
This value is used to identify a particular subsystem.
Bit Description
15:0 Subsystem ID—R/W O: The def aul t value is 00h. Thi s field s houl d be programm ed duri ng boot-up. After
this field is written once, it becom es read only.
3.4.13. CAPPTR—Capabilities Pointer (Device 0)
Offset: 34h
Default: A0h
Access: Read Only
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location where the AGP standard registers are
located.
Bit Description
7:0 Start of AGP Standard Register Block: Thi s field is a pointer to the start of AGP s tandard register
block.
A0h = Start of AGP standard register block.
82840 MCH
R
Datasheet 51
3.4.14. GAR[15:0]—RDRAM Group Archi tecture Register (Devi ce 0)
Address Offset: 40–4Fh
Default Value: 80h
Access: Read/Write
Size: 8 bits/register
This 8-bit register defines the page size, the #of banks, and DRAM technology of each device group in
the RDRAM channel. T here are 16 GAR registers (GAR0 – GAR15). In single channel-pair operation,
only the first eight are used to describe the 32 device-pairs, where each register describes a group of 4
RDRAM device pairs. In multiple channel-pair mode, all 16 registers are used to describe memory
device-pair groups. Since there can be four times as many devices in this mode and the number of
descriptive registers is only doubled, each register describes twice as many register-pairs (8 device-
pairs/group).
Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. This
is done for improve SMM security.
Bit Description
7:6 Device Page S ize (DPS). This fi el d defines the page size of the each device in the corresponding
group.
00 = Reserved
01 = Reserved
10 = 1 KB
11 = 2 KBs
5 Reserved
4 Device Banks (DB): Thi s field def i nes # of bank arc hi tecture in each device in t he group.
0 = 16 dependent Banks
1 = 32 dependent Banks arranged in two groups of 16 dependent banks (i.e., 2x16)
3 Reserved
2:1 Device DRAM Technology (DDT): This field def i nes the DRAM tec hnol ogy of eachdevice i n the group.
00 = 64/72Mbit
01 = 128/144Mbit
10 = 256/288Mbit
11 = Reserved
0 Reserved.
52 Datasheet
3.4.15. MCHCFG—MCH Configuration Regi ster (Device 0)
Offset: 50–51h
Default: 00s0_0000_ 0000-_0s00b
Access: Read/Write Once, Read/Write, Read Only
Size: 16 bits
Bit Description
15:14 Reserved
13: Host Frequency—RO: These bits are used to determ i ne t he host frequenc y. These bits are set by an
external strapping opt i on at reset and are Read Only.
0 = 100 MHz
1 = 133 MHz
12 Reserved
11 Direct Rambus Frequency—R/W: These bit s are written by the BIOS after pol l i ng t he Rambus* Di rect
RDRAMs and findi ng the least common denom i nat or speed.
0 = 300 MHz
1 = 400 MHz
10 Reserved
9 Aperture Access Global Enable—R/W: This bit is used to prevent ac cess to the aperture from any
port (host , PCI0 or AGP) before the aperture range is establi shed by the conf i guration software and
appropriate trans l ation table in the main DRAM has been initi al i zed. Default is 0. This bit must be set
after s ys tem is fully c onfigured for aperture access es.
1 = Enable
0 = Disable
8:7 DRAM Data Integrity M o d e (DDIM)—R/ W: These bits selec t one of 3 DRAM data integrity modes.
00 = Non-ECC (B yte-Wise writes supported, RDRAM device only) (Default)
01 = Reserved
10 = ECC Mode (Generation and Error Checking/Correction)
11 = ECC Mode with hardware scrubbing enabled. Sam e as DDIM=10, plus corrected dat a written to
DRAM.
6 ECC Diagnostic Mode Enable (EDME)—R/W:
1 = Enable. MCH enters ECC Diagnosti c test mode. On all subsequent write c ycles to main memory,
the MCH will write all zeroes to the ECC field. This allows straightforward creation of both single bit
and multiple bit errors.
0 = Disable. Normal operati ng mode (default).
82840 MCH
R
Datasheet 53
Bit Description
5 MDA Present (MDAP)—R/ W: This bit works with t he VGA Enable bi t i n the BCTRL regist er of device
1and 2 to control the routing of host init i ated transac t i ons targeting MDA compat i bl e I/O and m emory
address ranges . This bit should not be set when the VGA Enable bi t is not set in eit her devi ce 1 or 2. If
the VGA enabl e bi t is set, then ac cesses to IO address range x3BCh–x3BFh are forwarded to the hub
interface A. MDA resources are defined as the foll owing:
Memory: 0B0000h–0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not us ed i n decode)
Any I/O ref erence that i ncludes the I/O loc at i ons listed above, or their al i ases, are f orwarded to t he hub
interface A, even if the reference includes I/O locati ons not listed above.
Refer to the System Addres s Map Chapter for further information.
4 Reserved.
3 AGP I/ O Buffer Mode—RO: The MCH has an internal circuit that detects the voltage level on the
AGPI/O buffer V ddq rai l .
0 = AGP Vddq i s 1.5V.
1 = AGP Vddq i s 3.3V.
2 In-Order Queue Depth (IOQD)—RO: This bit reflects the value sampled on HA7# on the deassert i on
of the CPURST#. It i ndi cates the depth of the host bus i n-order queue (i .e., level of host bus
pipelining). I f IOQD is set to 1 (HA 7# sampled 1; i.e., undriven on the host bus), the dept h of the host
bus in-order queue is configured to the maxim um allowed by the host bus protoc ol (i .e., 8). If the I OQD
bit is set to 0 (HA7# i s sampled asserted; i.e., 0), the depth of the hos t bus in-order queue is set to 1
(i.e., no pi pel i ni ng support on the hos t bus).
Note that HA7# is not dri ven by the MCH during CPURST#. If an IOQ s i ze of 1 is des i red, HA7# m ust
be driven low during CPURST# by an external s ource.
1:0 Reserved.
3.4.16. FDHC—Fixed DRAM Hole Control Register (Device 0)
Address Offset: 58h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This 8-bit register controls a fixed DRAM hole: 15–16 MB.
Bit Description
7 Hole Enable (HEN): This field enables a memory hole in DRAM spac e. Host c ycles matching an
enabled hole are pass ed on to ICH through the hub i nterface. The hub i nterface c ycles matching an
enabled hole will be ignored by the MCH. Note that a selected hole is not re-mapped.
1 = Enable. 15 MB – 16 MB (1MB)
0 = Disable
6:0 Reserved.
54 Datasheet
3.4.17. PAM0–PAM6—Programmable Attribute Map Registers
(Device 0)
Address Offset: 59–5Fh (PAM0–PAM6)
Default Value: 00h
Attribute: Read/Write
Size: 8 bits
The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in
the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to
support these features. Cacheability of these areas is controlled via the MT RR registers in the processor.
Two bits are used to specify memory attributes for each memory segment. These bits apply to host
initiator only access to the PAM areas. The 82840 MCH will respond to a “Master Abort” for any AGP,
PCI, or hub interface A/B initiated accesses to the P AM areas. These attributes are:
RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment are
claimed by the MCH and directed to main memory. Conversely, when RE = 0, the host read
accesses are directed to PCI0.
WE Write Enable. When WE = 1, the host write accesses to the corresponding memory segment
are claimed by the MCH and directed to main memory. Conversely, when WE = 0, the host
write accesses are directed to PCI0.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions; typically, 16 KBs in size. Each of these regions has a 4-bit
field. The four bits that control each region have the same encoding and are defined in Table 3.
Table 3. Attribute Bit Assignment
Bits [7, 3]
Reserved Bits [6, 2]
Reserved Bits [5, 1]
WE Bits [4, 0]
RE Description
x x 0 0
Disabled. DRA M is di sabled and all ac cesses are
directed t o the hub interface A. The MCH does not
respond as a P CI target for any read or write ac cess
to this area.
X x 0 1
Read Only. Reads are forwarded to DRAM and
writes are forwarded to the hub interface A for
term i nat i on. This write protects t he corresponding
memory segment. The MCH will respond as an AGP
or the hub interf ace A target for read acces ses but
not for any write ac cesses.
X x 1 0
Write Only. Writ es are forwarded to DRAM and
reads are forwarded to the hub interface f or
termination. The MCH will respond as an AGP or hub
interface A target for write accesses but not for any
read acces ses.
X x 1 1
Read/Write. This i s the norm al operat i ng mode of
main mem ory. Both read and write c yc l es from the
host are c l ai med by the MCH and forwarded to
DRAM. The MCH will respond as an AGP or the hub
interface A target for both read and write acc esses.
82840 MCH
R
Datasheet 55
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization
process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is
shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the
attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read
of that address. This read is forwarded to the expansion bus. The host then does a write of the same
address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory
area are set to read only so that all writes are forwarded to the expansion bus. Table 4 and Figure 4 shows
the PAM registers and the associated attribute bits.
Figure 2. PAM Registers
pam
REWERE R RWERR
76543210
PAM6
PAM5
PAM4
PAM3
PAM2
PAM1
PAM0
Read Enable
(
R/
1=Enable
0=Disable
Write Enable (R/W)
1=Enable
0=Disable
Reserved
Reserved
Read Enable (R/W)
1=Enable
0=Disable
Write Enable (R/W)
1=Enable
0=Disable
Reserved
Reserved
5Fh
5Eh
5Dh
5Ch
5Bh
5Ah
59h
Offset
Table 4. PAM Registers and A ssociated Memory Segments
PAM Reg Attribute Bits Memory Segment Comments Offset
PAM0[3:0] Reserved 59h
PAM0[7:4] R R WE RE 0F0000h–0FFFFFh BIOS Area 59h
PAM1[3:0] R R W E RE 0C0000h–0C3FFFh ISA A dd-on BIOS 5Ah
PAM1[7:4] R R W E RE 0C4000h–0C7FFFh ISA A dd-on BIOS 5Ah
PAM2[3:0] R R W E RE 0C8000h–0CBFFFh ISA Add-on BIOS 5B h
PAM2[7:4] R R WE RE 0CC000h–0CFFFFh I S A Add-on BIOS 5Bh
PAM3[3:0] R R W E RE 0D0000h–0D3FFFh ISA A dd-on BIOS 5Ch
PAM3[7:4] R R W E RE 0D4000h–0D7FFFh ISA A dd-on BIOS 5Ch
PAM4[3:0] R R W E RE 0D8000h–0DBFFFh ISA Add-on BIOS 5Dh
PAM4[7:4] R R WE RE 0DC000h–0DFFFFh I S A Add-on BIOS 5Dh
PAM5[3:0] R R WE RE 0E0000h–0E3FFFh BIOS Extension 5Eh
PAM5[7:4] R R WE RE 0E4000h–0E7FFFh BIOS Extension 5Eh
PAM6[3:0] R R WE RE 0E8000h–0EBFFFh BIOS Extension 5Fh
PAM6[7:4] R R WE RE 0EC000h–0EFFFFh BIOS Extension 5Fh
For details on overall system address mapping scheme, see The System Address Map Chapter.
56 Datasheet
DOS Application Area (00000h–9FFFh)
The DOS area is 640 KB and it is divided into two parts. The 512 KB area at 0 to 7FFFFh is always
mapped to the main memory controlled by the MCH, while the 128 KB address range from 080000 to
09FFFFh can be mapped to PCI0 o r to main DRAM. By default this range is mapped to main memory
and can be declared as a main memory hole (accesses forwarded to PCI0) via MCH FDHC configuration
register.
Video Buffer Area (A0000h–BFFFFh)
This 128 KB area is not controlled by attribute bits. The host -initiated cycles in this region are always
forwarded to either PCI0 or AGP unless this range is accessed in SMM mode. Routing of accesses is
controlled by the Legacy VGA control mechanism of the “virtual” PCI-PCI bridge device in the MCH.
This area can be programmed as SMM area via the SMRAM register. When used as a SMM space, this
range can not be accessed from the hub interface nor AGP.
Expansion Area (C0000h–DFFFFh)
This 128 KB area is divided into eight 16 KB segments that can be assigned with different attributes via
PAM control register.
Extended System BIOS Area (E0000h–EFFFFh)
This 64 KB area is d ivided into four 16 KB segments which can be assigned with different attributes via
PAM control register.
System BIOS Ar ea ( F0000h–FFFFFh)
This area is a single 64 KB segment which can be assigned with different attributes via PAM control
register.
82840 MCH
R
Datasheet 57
3.4.18. GBA0–GBA15—RDRAM Group Boundary Address Register
(Device 0)
Address Offset: 60–7Fh (GBA0–GBA15)
Default: 01h
Access: Read/Write
Size 16 bits/register
Note: This register is locked and becomes Read Only when the D_CLK bit in the SMRAM register is set. T his
is done to improve SMM security.
The RDRAM device-pairs are logically arranged into groups. T here are eight groups when the MCH is
configured for single channel-pair mode operation; there are four groups for multiple channel-pair mode
operation. Each group requires a separate GBA register. The GBA registers define group ID and the
upper and lower addresses for each group in a channel-pair. Contents of bits 0:9 of this register represent
the boundary addresses in 16 MB granularity.
For example, a value of 01h indicates that the programmed group applies to memory below 16 MB. Only
the first eight GBA registers are used in single channel-pair mode. All 16 GBA registers are used in
multiple channel-pair mode. Note that GBA15 must always contain the group boundary addr ess that
points to the top of memory, whether the MCH is being used in single channel-pair mode or multiple
channel-pair mode.
60–61h GBA0 = Total memory in group0 (in 16 MBs)
62–63h GBA1 = Total memory in group0 + group1 (in 16 MBs)
64–65h GBA2 = Total memory in group0 + group1 + group2 (in 16 MBs)
66–67h GBA3 = Total memory in group0 + group1 + group2 + group3 (in 16 MBs)
....
7E–7Fh GBA15 = Total memory in group0 + group1 + group2 + … + group15 (in 16 MBs)
Bit Description
15 Reserved.
14:13 Channel ID (CHID): Reflects t he ID of the Rambus* channel described by thi s GBA entry. This fi el d i s
only used when MRH-R is present .
12:10 Group ID (GID): This 3-bit val ue i s used to i dentify a logical group of Direct RDRAM devic es. This
value and appropriate addres s bits are used to generate t he devi ce RDRAM_D device ID. Note that al l
device-pairs popul ated in a group must be of t he same mem ory technology.
9:0 Group Boundary Address (GBA): This 10-bit value is com pared agai nst address l i nes A[33: 24] to
determ i ne t he upper address limit of a particul ar group of devices
(i.e., GBA mi nus previous GBA = group size).
58 Datasheet
3.4.19. RDPS—RDRAM Pool Siz ing Register (Devi ce 0)
Address Offset: 88h
Default Value: 10h
Access: Read/Write
Size: 8 bits
Bit Description
7 Pool Lock (LOCK):
1 = Contents of the RDPS regi ster becomes RE A D Onl y.
0 = Contents of the RDPS regi ster becomes READ/WRITE .
6 Reserved
5 Reinitialize RDRAM Pools (POOLINIT):
1 = RDRAM pools are reinit i al i zed t o the default val ue contained in t hi s register.
0 = As long as this bit i s 0, the ot her fields in this register m ay be modifi ed without changing the
behavior of the pool s. This bi t is set to 0 aft er the RDRAM devices are i ni tialized with the new pool
sett i ngs and the MCH is operated i n t he new pool s et tings.
Note that the external therm al sensor trip conditions (i .e., a rising edge on OVERT# or RDRA M devices
report an overtemperature condi tion) do not have any eff ect on thi s bit, even t hough they do cause new
pool values t o be l oaded.
4 Pool C Operating Mode (PCS) :
1 = All devices found neit her i n pool A nor in pool B are as sumed t o be i n nap mode.
0 = All devices in pool C are as sumed t o be i n standby m ode.
3:2 Pool A Capacity (PAC): This fiel d def i nes the maximum number of RDRAM devices that can reside in
Pool A at a t i me.
00 = 1
01 = 2
10 = 4
11 = 8
1:0 Pool B Capacity (PBC): This fi el d defines the maximum number of RDRAM devices t hat can resi de i n
Pool B at a t i me.
00 = 1
01 = 4
10 = 8
11 = 16
82840 MCH
R
Datasheet 59
3.4.20. DRD—RDRAM Device Register Data Register (Device 0)
Address Offset: 90–93h
Default Value: 0000h
Access: Read/Write
Size: 32 bits
Bit Description
31:0 Regi ster Data (RD): Bits 31:0 cont ai n the 32 bits of data to be written to a RDRAM regist er or t he data
read from a RDRA M register as a res ul t of IOP execut i on. Data is val i d when the I IO bit of the RICM
register has transitioned from 1 to 0. B i t s 31:16 apply to Direct Rambus* int erface A and bits 15:0 apply
to Direct Rambus * i nterface B.
3.4.21. RICM—RDRAM Initialization Control Management Register
(Device 0)
Address Offset: 94–97h
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
Bit Description
31 Reserved
30 Rambus* Interface B Sti ck Channesl Swap:
1 = Swap. The two stic k channels of each MRH-R are swapped on the Rambus* interface B.
0 = Not Swapped.
29:28 Time To P ow erUp (TPU): This field def i nes the tot al powerdown exit tim e f or RDRAM devices and
corresponds to the RDRAM device (PDNA+t PDNB) timing.
00 = 42.0 us
01 = 34.5 us
10 = 27.0 us
11 = 19.5 us
27 Initialization Complete (IC):
1 = BIOS sets t hi s bit to 1 after the ini tializati on of the RDRAM m emory array is compl ete.
26:25 Reserved
24 MRH-R P resent (MRHRP):
1 = Set by software when it detects the presenc e of Memory Repeater Hub f or Rambus* Component in
the system.
23 Initiate Initialization Operation (IIO): The sof tware must check t o see if thi s bit is 0 before writing to
this bit. The operations which specif y regis t er data read from t he Direct RDRAM will have the data valid
in DRD regist er when this bit is cleared to 0.
1 = Execution of t he i ntializati on operat i on specifi ed by IOP st arts.
0 = After the execution is completed, the MCH clears this bi t to 0.
22 Reserved
60 Datasheet
Bit Description
21:20 Channel ID (CID): This fiel d specif i es the channel address for which t he i ni t i al i zat i on or the channel
reset operat i on i s initial ed.
19 Broadcast Address (BA):
1 = Initiali zat i on operation (IOP) i s broadcast to all devices. When t hi s bit is set to 1, the DSA fi el d i s
don’t care.
18:10 Devi ce Register Address (DRA): This field s pecifies the register address for t he regi ster read and
write operations.
9:5 Seri al Device/Channel Address (SDCA): Thi s 5 bits f i el d specif i es the serial devi ce ID of the Di rect
RDRAM to which the intialization operation is t argeted for the next SI O command to be s ent by MCH.
4:0 Initialization Opcode (IOP): This field specif i es the initi al i zat i on operartion to be done on Direc t
RDRAM device.
00000 = RDRAM Register Read
00001 = RDRAM Register Write
00010 = RDRAM Set Res et
00011 = Reserved
00100 = RDRAM Set Fast Clock Mode
00101 = RDRAM Temperat ure Cal i brat e Enable
00110 = RDRAM Temperat ure Cal i brat e
00111 = Reserved
01000 = Redirect Next SI O
01001 = MRH-R “Stick Channel” SIO Reset
01010 = Reserved
01011 = RDRAM Clear Reset
01100 = Reserved
01101 = Write SPD Register
01110 = Read SPD Regis t er
01111 = Reserved
10000 = RDRAM Current Calibrat i on
10001 = RDRAM SIO Reset
10010 = RDRAM Powerdown Exit
10011 = RDRAM Powerdown Entry
10100 = RDRAM Nap Entry
10101 = RDRAM Nap Exit
10110 = RDRAM Refresh
10111 = RDRAM Precharge
11000 = Manual Current Calibration of MCH RAC
11001 = MCH RAC load RAC A c onfiguration register
11010 = MCH RAC load RAC B c onfiguration register
11011 = Initi al i ze MCH RAC
11100 = MCH RAC Current Calibrat i on
11101 = MCH RAC Thermal Cal i bration
11110 = Reserved
11111 = PowerUp All Sequence
82840 MCH
R
Datasheet 61
3.4.22. MCH Expansion RAC A/B Configur ation Registers
Address Offset Not Applicable (see description below)
Default: 0000_0000h
Access: Not Applicable (see description below)
Size: 32 bits
To enable the E-clamp of MCH RAC A, first write a 32-bit value into the DRD register (offset 90–93h).
Then, issue an Initialization Opcode (IOP=11001b) through the RICM/S ICM re gister (offset 94–97h).
Repeat the same procedure above for enabling the E-clamp on MCH RAC B (IOP=11010b). The default
state of the E-Clamps are disabled after power on.
Bit Description
31:26 Reserved
25:24 Early Clamp Enable:
00 = Disabled
11 = Enabled
01 or 10 = Reserved
23:0 Reserved
3.4.23. SMRAM —System Management RAM Control Register
(Device 0)
Address Offset: 9Dh
Default Value: 02h
Access: Read/Write, Read Only
Size: 8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated.
The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit
must be reset b e fore the LOCK bit is set.
Bit Description
7 Reserved
6 SMM Space Open (D_OP E N): When D_OPE N=1 and D_LCK =0, the SMM space DRAM is m ade
visible even when SMM decode is not active. This is i ntended to help BI OS initial i ze S MM spac e.
Software should ensure that D_OP E N=1 and D_CLS = 1 are not set at t he same t i me. When D_LCK is
set t o a 1, D_OPEN is reset to 0 and bec omes read onl y.
5 SMM Space Cl osed (D_CLS): When D_CLS = 1 SMM space DRAM is not acces sible to dat a
references, even if SMM decode is act i ve. Code references may still access SMM spac e DRA M. This
will allow SMM software to referenc e "t hrough" S MM spac e t o updat e the display even when SMM is
mapped over t he V GA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at t he
same time.
4 SMM Space Locked (D_LCK): When D_LCK is set to 1, then D_OPEN is reset to 0 and D_LCK ,
D_OPEN, C_B A SE_SEG, H_SMRAM_EN, TSE G_SZ and TSEG_EN become “Read Only”. D_LCK can
be set t o 1 vi a a normal configuration s pace write but can only be cleared by a Full Res et. The
com bi nation of D_LCK and D_OP E N provi de convenience with s ecurity. BIOS can us e the D_OPEN
funct i on t o i ni tialize SMM spac e and t hen use D_LCK to "l ock down" SMM space in the future s o t hat no
applicat i on software (or BIOS i tself) can violate t he i ntegrity of SMM space, even if the program has
knowledge of the D_OPE N function.
62 Datasheet
Bit Description
3 Global SMRAM Enable (G_SMRAME): I f set to a 1, then Compat i bl e SMRAM functions is enabled,
providing 128 KB of DRAM accessible at the A0000h address while i n S MM (ADS # with S MM decode).
To enable Extended SMRAM function this bi t has be set to 1. Refer to the Sy stem Address Map
Chapter for more details. Once D_LCK i s set, this bit becom es read only.
1 = Enable
0 = Disable
2:0 Compatible SMM Space Base Segm ent (C_BASE_SEG)—RO: This field indi cates t he location of
SMM space. " SMM DRAM" is not remapped. It i s simply "made visibl e" i f the conditions are right to
acces s SMM space, otherwise the acc e ss is forwarded to the hub interf ace. C_BAS E_SEG is hardwired
to 010 to indicat e that the MCH supports the SMM space at A 0000h-BFFFFh.
3.4.24. ESMRAM C—Extended System Management RAM Control
Register (Device 0)
Address Offset: 9Eh
Default Value: 38h
Access: Read/Write/Lock
Size: 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memo ry provides a write-back cacheable SMRAM memo ry space that is above
1 MB.
Bit Description
7 H_SM RAM_EN (H_SMRAM E): Control s the SMM memory space locati on (i .e., above 1 MB or below
1 MB). When G_SMRAME is 1 and H_SMRAME is set t o 1, the high SMRAM m emory space is
enabled. SMRAM acces ses from 0FFEA0000h to 0FFE BFFFFh are remapped to DRAM address
000A0000h to 000BFFFFh. Once D_LCK is s et , this bit becomes read only.
6 E_SMRAM _ERR (E_SMERR): Thi s bit is set when the host access es the defined mem ory ranges in
Extended SMRAM (High Memory and T-segment) while not i n SMM space and with the D-OPE N bit = 0.
It is s of t ware’s responsibility to clear this bit . Software must write a 1 to this bit t o clear it
5 SM RAM_Cache (SM _CACHE): Hardwired to 1.
4 SM RAM_L1_EN (SM_L1): Hardwired to 1.
3 SM RAM_L2_EN (SM_L2): Hardwired to 1.
2:1 TSEG_SZ[1-0] (T_SZ): Sel ects t he size of the TS EG memory block, if enabl ed. Thi s memory is t aken
from the top of DRAM s pace (i.e., TOM - TSEG_SZ), which is no longer claimed by the memory
controll er (i f TSEG_EN is set, al l accesses to t hi s space are s ent to the hub int erface). This field
decodes as follows:
00 = (TOM-128K) to TOM
01 = (TOM-256K) to TOM
10 = (TOM-512K) to TOM
11 = (TOM-1M) to TOM
Once D_LCK is set, this bit becomes read only.
0 TSEG Enable (TSEG_EN): Enabling of SMRAM memory (TS EG, 128 KB, 256 KB, 512 K B or 1 MB of
additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and
TSEG_EN = 1, the TSEG is enabled to appear in t he appropriate physical address space. Once D_LCK
is set, this bit bec omes read only. TSEG_EN can only be 1 when G_SMRAME is 1.
82840 MCH
R
Datasheet 63
3.4.25. ACAPID—AGP Capability Identifier Register (Device 0)
Address Offset: A0–A3h
Default Value: 00200002h / 00000000h
Access: Read Only
Size: 32 bits
This register provides standard identifier for AGP capability.
Bit Description
31:24 Reserved
23:20 Major AGP Revision Num b er: These bits provide a m aj or revi sion number of AGP s pecific ation to
which this version of MCH conf orms.
0010 = Rev 2.x.
19:16 Minor AGP Revision Number: These bits provi de a minor revis i on number of A GP specification that
this version of the MCH c onforms . This number is hardwired to value of “0000” (i.e., im pl yi ng Rev x.0).
Together with m aj or revi sion number this fi el d i dentifies MCH as an AGP RE V 2.0 com p l i ant devi ce.
0000 = Rev x.0
15:8 Next Capability Pointer: AGP capability is the firs t and the last capability described via the capabilit y
pointer mechanism. Hardwired to 0s .
0000_0000 = End of the c apabilit y link ed list
7:0 AGP Capability ID: This fi el d i dentifies t he l i nked list i tem as containing A GP registers.
0000_0010 = Assi gned by the PCI SI G.
64 Datasheet
3.4.26. AGPSTAT—AGP Status Register (Device 0)
Address Offset: A4–A7h
Default Value: 1F000217h
Access: Read Only
Size: 32 bits
This register reports AGP device capability/status.
Bit Description
31:24 Maximu m Requests (RQ): Hardwired to 1Fh. This field c ont ai ns the m aximum number of AGP
com mand request s the MCH is c onf i gured to manage. The l ower 6 bits of this field ref l ect the value
programmed in AGP CTRL[ 12:10]. Only discrete values of 32, 16, 8, 4 , 2 and 1 can be s el ected via
AGPCTRL. Upper bi t s are hardwired to 0s.
1Fh = A maximum of 32 outstanding A G P command requests can be handled by t he MCH
23:10 Reserved
9 Sideband Addressing (SBA): Hardwired to 1.
1 = MCh supports s i de band addressing.
8:6 Reserved
5 4 GB M aximum Address Space (4GB): Hardwired to 0.
0 = MCH does not support addres ses greater t han 4 gi gabytes.
4 Fast Writes (FW): Hardwired to 1.
1 = MCH supports Fas t Writes from the host to t he A G P mast er.
3 Reserved
2:0 RATE: After reset, the MCH reports its data transfer rate capabilit y. B i t 0 identifies if A GP device
supports 1x data transfer m ode, bit 1 ident i f i es if AG P devi ce supports 2x data t rans fer mode, bi t 2
identif i es if AGP devi ce supports 4x data transfer mode. Note that the s el ected data t ransfer m ode
apply to both A D bus and SBA bus. It al so applies to Fast Writes, i f they are enabled.
111 = 1x, 2x, and 4x data t ransfer m odes supported
82840 MCH
R
Datasheet 65
3.4.27. AGPCMD—AGP Command Register (Device 0)
Address Offset: A8–ABh
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
This register provides control of the AGP operational parameters.
Bit Description
31:10 Reserved.
9 Side Band Addressing Enable (SBA_EN):
1 = Enable. S i de band addressing mechanism is enabled.
0 = Disable
8 AGP Enable: When this bi t is set to 0, t he MCH ignores al l A G P operations, i ncluding the sync cycl e.
Any AGP operations received while this bit is set to 1 will be serviced, even if this bit is reset t o 0. I f this
bit trans i tions from a 1 to a 0 on a c l ock edge in the middle of an SBA comm and bei ng del i vered i n 1X
mode, the com mand will be issued. When this bit is set to 1, t he MCH res ponds to AGP operat ions
delivered via PI P E# or to operations delivered via SB A, if the AGP Si de Band Address i ng Enable bit is
also set to 1.
1 = Enable
0 = Disable
7:6 Reserved.
5 4 GB M aximum Address Space (4GB): Hardwired to 0.
0 = The MCH, as an AG P target, does not support addressing greater than 4 GB s.
4 Fast Writes Enabl e (FW_EN):
1 = The MCH uses the Fast Write protocol f or Memory Write transact i ons from the MCH to the AGP
mas ter. Fast Writes oc cur at the data transfer rat e selected by the data rate bits (2:0) in this
register.
0 = When thi s bit is 0 (or when the data rate bits are set to 1x mode), the Memory Write transactions
from t he MCH t o t he AGP m aster use standard PCI protocol.
3 Reserved.
2:0 Data Rate: The settings of thes e bi ts determines t he A G P data transf er rate. One (and only one) bit i n
this f i el d must be set to indi cate the des i red dat a transfer rat e. Bit 0: 1X, Bit 1: 2X, Bit 2: 4x. The same
bit must be set on both master and target. Conf iguration software will update this fi eld by s et t ing only
one bit that corresponds to the capability of t he A G P master (after that capability has been verified by
acces sing the same func tional regis t er withi n the AGP masters configuration spac e. ) Note that t hi s field
applies t o A D and S BA buses . It als o appl i es to Fast Writes, i f they are enabled.
001 = 1x
010 = 2x
100 = 4x
All other combi nat i ons are illegal.
66 Datasheet
3.4.28. AGPCTRL—AGP Control Register (Device 0)
Address Offset: B0–B3h
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
This register provides for additional control of the AGP interface.
Bit Description
15:8 Reserved
7 GTLB Enable (and GTLB Flush Control)—R/W:
1 = Enable. Normal operations of the Graphics Transl at i on Lookaside Buffer.
0 = Disable (default). GTLB is fl ushed by clearing t he val i d bi ts ass ociated with each entry.
6:0 Reserved.
3.4.29. APSIZE—Aperture Size (Device 0)
Address Offset: B4h
Default Value: 00h
Access: Read/Write
Size: 8 bits
APSIZE determines the effective size of the Graphics Aperture used for a particular MCH configuration.
This register can be updated by the MCH specific BIOS configuration sequence before the PCI standard
bus enumeration sequence takes place. If the register is not updated, the default value selects an aperture
of maximum size (i.e., 256 MB). The size of the table that corresponds to a 256 MB aperture is not
practical for most applications; therefore, these bits must be programmed to a smaller practical value that
forces adequate address range to be requested via the APBASE register from the PCI configuration
software.
Bit Description
7:6 Reserved
5:0 Graphics Aperture Size (APSIZE)—R/W : Each bit in APS IZE[5:0] operates on s i milarly ordered bi ts in
APBA SE[27:22] of the Aperture Base c onfiguration register. When a particular bit of this field is 0, it
forces t he similarly ordered bit in APBASE[ 27:22] to behave as “hardwired” to 0. When a parti c ular bit of
this f i el d i s set t o 1, it allows t he corresponding bit of the APB ASE[27:22] to be read/ write ac cessi bl e.
Only the foll owing combinations are allowed:
5 4 3 2 1 0 Aperture Size
1 1 1 1 1 1 4 MB
1 1 1 1 1 0 8 MB
1 1 1 1 0 0 16 MB
1 1 1 0 0 0 32 MB
1 1 0 0 0 0 64 MB
1 0 0 0 0 0 128 MB
0 0 0 0 0 0 256 MB
Default for APSIZE[5:0] =000000b f orc es default APBASE[27:22] =000000b (i.e., all bits respond as
“hardwired” to 0). This provi des maxim um aperture s i ze of 256 MB. As anot her exam pl e, programming
APSI ZE[5:0]=111000b hardwires APBAS E [24:22]=000b while enabling A PBASE [27:25] as read/write
programmable.
82840 MCH
R
Datasheet 67
3.4.30. ATTBASE
Aperture Translation Table Base Register
(Device 0)
Address Offset: B8–BBh
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base located in the
main DRAM. This value is used by the MCH Graphics Aperture address translation logic (including the
GTLB logic) to obtain the appropriate address translation entry required during the translation of the
aperture address into a corresponding physical DRAM address. The AT TBASE register may be
dynamically changed.
Note: T he address provided via ATTB ASE is 4 KB aligned.
Bit Description
31:12 Address Translati on Table Base Po i n ter: Thi s field c ontains a point er to the base of t he translati on
table used to map memory space addresses in t he apert ure range to addresses in mai n memory.
11:0 Reserved
3.4.31. AMTT—AGP Interface Multi-Transaction Timer Register
(Device 0)
Address Offset: BCh
Default Value: 00h
Access: Read/Write
Size: 8 bits
AMTT is an 8-bit register that controls the amount of time that the MCH arbiter allows an AGP master to
perform multiple back-to-back transactions. The MCH AMTT mechanism is used to optimize the
performance of the AGP master (using PCI protocol) that performs multiple back-to-back transactions to
fragmented memory ranges (and as a consequence it can not use long burst transfers). The AMTT
mechanism applies to the host-AGP transactions as well and it guarantees to the processor a fair share of
the AGP interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current agent (either AGP master or Host bridge) after which the AGP
arbiter will grant the bus to another agent. The default value of 00h disables this function. The AMTT
value can be programmed with 8 clock granularity. For example, if the AMTT is programmed to 18h, the
selected value corresponds to the time period of 24 AGP (66 MHz) clocks.
Bit Description
7:3 Multi-Transaction Timer Count Value: The value programmed in this field represents t he guarant eed
time slic e (measured i n ei ght 66 MHz clock granul ari ty) allott ed t o t he current agent (either AGP master
or MCH) after which the AGP arbit er will grant the bus to another agent.
2:0 Reserved.
68 Datasheet
3.4.32. LPTT—Low Priority Transaction Timer Register (Device 0)
Address Offset: BDh
Default Value: 00h
Access: Read/Write
Size: 8 bits
LPTT is an 8-bit register similar in a function to AMT T. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# o r SB
mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not
necessarily app ly to a single transaction but it can span over multiple lo w-priority transactions of the
same type. After this time expires, the AGP arbiter may grant the bus to another agent, if there is a
pending request. The LPTT does not apply in the case of high-priority request where ownership is
transferred directly to high-priority requesting queue. The default value of 00h disables this function. The
LPTT value can be programmed with 8 clock granularity. For example, if the LPTT is programmed to
10h, the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
Bit Description
7:3 Low P ri o ri ty Transaction Timer Count V al u e: The number of clocks programmed in these bits
represents the guaranteed time sli ce (measured in eight 66 MHz cl ock granularit y) al l otted to t he
current low priorit y A GP transac tion data transfer st at e.
2:0 Reserved.
82840 MCH
R
Datasheet 69
3.4.33. RDTR—RDRAM Timing Register (Device 0)
Address Offset: BEh
Default Value: 00h
Access: Read/Write
Size: 8 bits
RDTR defines the timing parameters for all devices in the Direct RDRAM channel. BIOS programs this
register with the “least common denominator” values after reading configuration registers of each device
in the Direct RDRAM channel. This register applies to the entire DRAM array.
Bit Description
7:6 Row to Co lumn Delay (tRCD): This field def i nes the m i ni mum i nterval between opening a row and
column operation on that row in units of Di rect Ram bus* clocks (RCLKs).
00 = Reserved
01 = 7
10 = 9
11 = Reserved
5:0 RDRAM Total CAS Access Delay (tRDRAM): Thi s field defi nes the m i ni mum round trip propagation
time of the RDRA M channel i n units of RDRA M c l ocks (RCLKs). This value includes the CAS access
time, the c hannel del ay tim e, or any MRH delay time.
tRDRAM = tCAC + tRDLY
• tRDRAM has a minimum val ue of 8 RCLKs si nce the support ed RDRA M t CA C = 8 RCLKs.
• The maxim um value of t RDRAM is 12 RCLKs i n single channel-pai r mode.
• The maxim um value of tRDRAM is 24 RCLKs in mul tiple channel -pai r mode..
• tRDLY is the total channel delay time and shoul d i nclude the channel del ay tim e of the RDRAM device
in the MCH RDRAM interf ace, the MRH-R propagation delay time, and the c hannel del ay time of the
RDRAM device in the MRH-R RDRAM interface.
The following table shows the valid tRCD and tCAC combinations for 300 MHz and 400 MHz.
RDRAM F r eq u en c y (RCLK) tRCD i n RCL Ks tCAC in RCLKs
400 MHz 9 8
400 MHz 7 8
300 MHz 7 8
70 Datasheet
3.4.34. RDCR—RDRAM Refresh Control Regi ster (Device 0)
Address Offset: BFh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register is loaded by configuration software with the refresh timings when the Direct RDRAM
Devices or the MRH-R Present bit is set in the RICM register (device 0, o ffset 94h, bit 24) for all
RDRAM channels present in the system. The value placed into this register should represent the least
commo n denominator of all of the devices on the specified channel pair. The MCH starts the refresh
cycles after bit 27 (offset 94–97h), Initialization Complete bit, is programmed by BIOS.
Bit Description
7:6 DRAM Refresh Rate for RDRAM Ch an n e l Pair #3 (DRR3): The DRAM refresh rate is adjusted
according to the frequenc y select ed by t hi s field. Note that refresh is al so disabled via this f i el d, and that
disabling refresh results in the eventual loss of DRAM data. Thi s field i s programmed by BIOS after
collec ting confi guration information from all Di rect RDRAM devic es in the channel and determini ng the
least common denomi nator value for refresh.
00 = Refresh Disabled
01 = 1.95 us
10 = 3.9 us
11 = 7.8 us
5:4 DRAM Refresh Rate RDRAM Ch an n el Pair #2 (DRR2): The DRAM refresh rat e i s adjusted according
to the frequency selec ted by this field. Not e that refres h i s also disabled via this field, and that disabl i ng
refresh res ul t s in the eventual l oss of DRA M data. This fi el d i s programmed by BIOS after c ol l ecting
configuration information f rom all Direct RDRAM devic es in the channel and determi ni ng t he l east
com mon denom i nator value for refresh.
00 = Refresh Disabled
01 = 1.95 us
10 = 3.9 us
11 = 7.8 us
3:2 DRAM Refresh Rate RDRAM Ch an n el Pair #1 (DRR1): The DRAM refresh rat e i s adjusted according
to the frequency selec ted by this field. Not e that refres h i s also disabled via this field, and that disabl i ng
refresh res ul t s in the eventual l oss of DRA M data. This fi el d i s programmed by BIOS after c ol l ecting
configuration information f rom all Direct RDRAM devic es in the channel and determi ni ng t he l east
com mon denom i nator value for refresh.
00 = Refresh Disabled
01 = 1.95 us
10 = 3.9 us
11 = 7.8 us
1:0 DRAM Refresh Rate RDRAM channel pair #0 (DRR0): The DRAM refresh rat e i s adjust ed according
to the frequency selec ted by this field. Not e that refres h i s also disabled via this field, and that disabl i ng
refresh res ul t s in the eventual l oss of DRA M data. This fi el d i s programmed by BIOS after c ol l ecting
config i nformat i on from all Di rect RDRAM devic es in the channel and determini ng the least common
denominator value for refresh.
00 = Refresh Disabled
01 = 1.95 us
10 = 3.9 us
11 = 7.8 us
82840 MCH
R
Datasheet 71
3.4.35. TOM — Top of Low Memor y Register (Device 0)
Address Offset: C4–C5h
Default Value: 00h
Access: Read/Write
Size: 16 bits
A memory hole is present under normal operating conditions from TOM up to the 4 GB address where
TOM is the Top Of Lower Memory register. This hole is used to access devices present behind hub
interfaces A and B, the AGP bus, the memory-mapped APIC register, and the boot BIOS area just below
4 GB. T hus, the hole range subtracts from the overall available RDRAM memory and will effectively
break the main memory into two contiguous areas: one below TOM and one above 4 GB, if available
RDRAM exceeds 4 GB. If the total amount of main memory is less than 4 GB, the addresses (i.e., not
their ‘values’) indicated by the TOM and GBA15 (or TOM and SRBA7) registers will be identical.
Bit Description
15:0 Top of Low Memory (TOM): This regis ter contains the address that corres ponds to bits 31:16 of t he
maxim um DRAM m emory address that lies bel ow 4 GB. Configuration s oftware should set this value t o
either the maximum amount of memory in the system or to the minimum address allocated for PCI
memory or the graphic s aperture, whichever i s smaller.
3.4.36. ERRSTS—Error Status Register (Device 0)
Address Offset: C8–C9h
Default Value: 0000h
Access: Read/Write Clear
Size: 16 bits
This register is used to report various error conditions via the hub interface messages to ICH. An SERR,
SMI, or SCI error message may be generated via the hub interface A on a zero to one transition of any of
these flags, when enabled in the PCICMD/E RRCMD, SMICMD, or SCICM D registers respectively.
Bit Description
15 FSB Parity Error (FSBPAR):
1 = The MCH detected an uncorrectable pari ty error on either the address or request signals of the
front si de bus.
0 = Soft ware m ust write a 1 to cl ear this bit .
14 SERR Request from AGP Port (AGPERR):
1 = AGP i nterface has received an SERR reques t from the Device 1 Vi rt ual Bridge. The S E RR
requests i nclude the AG P pari ty error, AGP forwarding SERR# error, and AGP receiving t argeted
abort error. If the appropriate bi t is set in the ERRCMD regis ter, this request is forwarded down hub
interface A to t he ICH.
0 = Software must write a 1 to clear this bit.
13 SERR Request from Hub interface B (HLBE RR):
1 = Hub i nterface B has received an SE RR request from the Devic e 2 V i rtual Bridge. The S ERR
requests i nclude the hub int erface B parity error and forwarding SERR# error. If the appropriate bit
is set in the ERRCMD register, thi s request i s forwarded down hub interface A to the ICH.
0 = Soft ware m ust write a 1 to cl ear this bit .
72 Datasheet
Bit Description
12 Host Uncorrectable Error (FSBBIERR):
1 = MCH detect ed t he asserti on of ei ther the BE RR# signal or the I E RR# signal on the processor bus .
An SERR or SCI hub int erface A message will be generated to ICH, if the appropriate bit is
enabled in the E RRCMD or SCI CMD regis ter.
0 = Soft ware m ust write a 1 to cl ear this bit .
11 Host Correctable Error (HCE RR):
1 = MCH detected a correctable data error on the host bus. An SCI or SMI hub interface A message
will be generated to ICH, if the appropriate bit is enabled in the S CI CMD or SMICMD register.
0 = Soft ware m ust write a 1 to cl ear this bit .
10 Exte rna l The rma l Trip (ETST):
1 = MCH detected a ri sing edge on the OVERT# or the RDRAM devices report an overtemperature
conditi ons. The OVERT# s houl d be used to receive an interrupt from an external therm al sensor
when the sensor has been t ripped. An SERR, S CI or S MI hub interface A mess age will be
generated to ICH, if the appropri ate bit is enabl ed i n the ERRCMD, SCICMD or SMICMD regis ter.
0 = Soft ware m ust write a 1 to cl ear this bit .
9 LOCK to non-DRAM M emory Flag (LCKF)—R/WC:
1 = When thi s bit is set it i ndi cates t hat a host ini tiated LOCK cycle target i ng non-DRAM memory
space oc curred.
0 = Software must write a 1 t o clear this bi t.
8 SERR on Hub interface B Target Abort (TAHLB):
1 = MCH detected that an MCH originated hub interface B cycle is t erminated with a Target Abort. An
SERR, S CI or S MI hub interface A mess age will be generated to I CH, if the appropriate bit is
enabled in the E RRCMD, S CICMD or SMICMD register.
0 = Soft ware m ust write a 1 to cl ear this bit .
7 Unimplemented Hub interface B Speci al Cycle (UNSCB):
1 = MCH initiat ed a hub i nterface B request that was t erminated with a Uni mplemented Spec i al Cycle
com plet i on packet. An SERR, S CI or S MI hub interface A mess age will be generated to the ICH, if
the appropriate bi t is enabled in the ERRCMD, SCI CMD or SMICMD regis ter.
0 = Soft ware m ust write a 1 to cl ear this bit .
6 SERR on hub interface A Target Abort (TAHLA):
1 = MCH detected that an MCH originated hub interface A cycl e i s term i nated with a Target Abort. An
SERR, S CI or S MI hub interface A mess age will be generated to t he ICH, if the appropriat e bit is
enabled in the E RRCMD, S CICMD or SMICMD register.
0 = Soft ware m ust write a 1 to cl ear this bit .
5 Unimplemented Hub interface A Special Cycle (UNS CA):
1 = MCH initiat ed a hub i nterface A request that was t erminated with a Uni mplemented Spec i al Cycle
com plet i on packet. An SERR, S CI or S MI hub interface A mess age will be generated to the ICH, if
the appropriate bi t is enabled in the ERRCMD, SCI CMD or SMICMD regis ter.
0 = Soft ware m ust write a 1 to cl ear this bit .
4 AGP Access Outside of Graphics Aperture Flag (OOGF):
1 = Indic ates that an A G P access occurred t o an address that i s outside of the graphics aperture
range. An SE RR, SCI or SMI hub int erf ace A m essage will be generated to the I CH, if the
appropriate bit i s enabled in the E RRCMD, SCICMD or SMICMD register.
0 = Soft ware m ust write a 1 to cl ear this bit .
82840 MCH
R
Datasheet 73
Bit Description
3 Invali d AGP Access Fl ag (IAAF):
1 = An AGP access was attempted outsi de of the graphics aperture and either to the 640 KB – 1 MB
range or above the top of memory. An SERR, S CI or SMI hub interfac e A mess age will be
generated to the ICH, if the appropriate bit i s enabled in the E RRCMD, SCICMD or SMICMD
register.
0 = Soft ware m ust write a 1 to cl ear this bit .
2 Invalid Graphics Aperture Translation Table Entry (ITTEF):
1 = An invalid translation t abl e ent ry was ret urned i n response to an A G P access to the graphics
aperture. An S E RR, SCI or SMI hub int erface A message will be generated to the ICH, if the
appropriate bit i s enabled in the E RRCMD, SCICMD or SMICMD register.
0 = Soft ware m ust write a 1 to cl ear this bit .
1 Multiple-bit DRAM ECC Error Flag (DMERR):
1 = A memory read dat a t ransfer had an uncorrectable multiple-bi t error. When thi s bit is set, t he
address t hat caused the error and t he syndrome are logged i n the EAP regi ster. Onc e this bit i s
set, the EAP f i eld in t he Error Address Point er Regist er and t he DECCSYN field in t he DRAM Error
Control/S tatus Register are locked until t he processor clears th i s bit by writing a 1. Software uses
bits [1:0] to detect whether the l ogged error address is f or Single or Multipl e-bi t error.
0 = Once software compl etes the error proc essing, a val ue of 1 i s written to t hi s bit to clear the value
(back t o 0) and unl ock the error loggi ng mechanism.
0 Single-bit DRAM ECC Error Flag (DSERR):
1 = A memory read dat a transfer had a s i ngl e-bi t correct abl e error and the correct ed data was sent for
the acc ess. When this bit i s set, the address t hat caused t he error and the syndrome are l ogged i n
the EAP regi ster. Onc e this bit is set, the EAP fiel d i n the Error Address Pointer Regi ster Register
and the DECCSYN field in the DRAM Error Control/Stat us Register are l ocked to prevent further
single bit error updates unt i l the process or clears t hi s bit by writing a 1. A multi pl e bi t error that
occurs after this bit is set will overwrite the EAP field with the multiple bit error addres s; the DCERR
or DUCERR bits in the Dram Error Control/Status Register will also be set.
0 = Soft ware m ust write a 1 to c l ear t hi s bit and unloc k the error logging mechanism.
3.4.37. ERRCMD—Error Command Register (Device 0)
Address Offset: CA–CBh
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register enables various errors to generate a SERR message via the hub interface A. Since the MCH
does not have an SERR# signal, SERR messages are passed from the MCH to the ICH over the hub
interface.
Note: The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command
register.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and
SCI error messages are disabled for that same erro r co nditio n.
74 Datasheet
Bit Description
15 SERR on Host Bus Error Enable (HBSERR):
1 = Enable. Generati on of the hub interf ace A SE RR mess age i s enabled for the pari t y errors on the
address or reques t signals of the front side bus.
0 = Di sable
14 AGP SERR Enable (AGPSERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled for the AGP parity error,
SERR# or target abort if t he appropri a t e bi t is enabled i n th device 1 regis ter.
0 = Di sable. AG P SERR events are i gnored.
13 SERR Request from Hub i n terface B (HLBS ERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled for the receipt of an
SERR request from the hub interface B.
0 = Disable
12 SERR on Host Uncorrectable Error (HUCSERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when the MCH detects
the BERR# or the IERR# error c ondi t i on on the front s i de bus.
0 = Di sable
11 Reserved
10 SERR on External Thermal Sensor Trip (THERM_SERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when the MCH has
detect ed a ri sing edge on the OVE RT# or t he RDRAM devices report an overtemperat ure
conditions.
0 = Di sable.
9 Reserved
8 SERR on Target Abort on Hub interface B E xception (TAHLB_SE RR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an MCH originated
hub interface B cycl e i s com pl eted with "Target A bort" status.
0 = Disable
7 SERR on Hub interface B Unimpl emented Special Cycle (UNSCB_SERR):
1 = Enable. When t hi s bit is set, t he generation of the hub interface A S ERR mes sage is enabled when
an MCH initiated hub i nterface B request is terminated with a Unim pl emented Special Cycl e
com pl et i on packet.
0 = Di sable
6 SERR on Target Abort on Hub interface A Exception (TAHLA_SERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an MCH originated
hub interface A cycl e i s com pl eted with "Target A bort" status.
0 = Di sable
5 SERR on Hub interface A Unimpl emented Special Cycle (UNSCA_SERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an MCH initiated
Hub interface A request i s term i nated with a Unimpl emented S pecial Cycle compl etion pack et .
0 = Di sable
82840 MCH
R
Datasheet 75
Bit Description
4 SERR on AGP Access Outsid e of Graphi cs Aperture (OOGF_SERR)
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an AGP access
occurs to an address out side of the graphi cs aperture.
0 = Di sable
3 SE RR on I n val id AGP Access (IAAF_SERR)
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an AGP access
occurs to an address out side of the graphi cs aperture and either to the 640 K B – 1 MB range or
above the top of memory.
0 = Di sable
2 SERR on I n val i d Translati on Table E ntry (ITTEF_S E RR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when an invalid
translat ion table entry was returned i n response to an A G P access to the graphics aperture.
0 = Di sable
1 SERR Multiple-Bit DRAM ECC Error (DMERR_SERR):
1 = Enable. The generati on of the hub interface A SERR mess age i s enabled when the MCH DRAM
controll er detects a multi pl e-bi t error. For sys t ems not supporting ECC, this bi t must be disabl ed.
0 = Di sable
0 SERR on Single-bit ECC Error (DSERR):
1 = Enable. When t hi s bit is set, t he generation of the hub interface A S ERR mes sage is enabled when
the MCH DRAM controll er detects a single bit error. For systems not supporting ECC, this bi t must
be disabled.
0 = Di sable
3.4.38. SMICM D—SMI Command Register (Device 0)
Address Offset: CC–CDh
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register enables various errors to generate a SMI message via the hub interface A.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SMI error message is enabled for an error condition, SERR and
SCI error messages are disabled for that same erro r co nditio n.
Bit Description
15:12 Reserved
11 SMI on Host Correctabl e E rror (HCS MI):
1 = Enable. When t hi s bit is set, t he generat i on of the hub interface A SMI message is enabled when
the MCH has detec ted a correct abl e single-bit dat a error on the host bus .
0 = Di sable. This bit m ust be set to a 0 if the systems does not i mplement the dat a correction on the
host bus .
76 Datasheet
Bit Description
10 SMI on External Thermal Sensor Trip (THERM_SMI):
1 = When this bit is s et , the generation of the hub interface A SMI message i s enabled when the MCH
has detec ted a rising edge on t he OV ERT# or the RDRAM devices report an overtemperature
conditions.
0 = Di sable
9 Reserved
8 SMI on Target Abort on Hub interface B E xception (TAHLB_SMI):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an MCH originated
hub interface B cycl e i s com pl eted with "Target A bort" status.
0 = Di sable.
7 SMI on Hub interface B Unim pl emented Special Cycle (UNSCB_SMI ):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an MCH initiated hub
interface B request i s terminated with a Unimplem ented Special Cycle completion packet.
0 = Di sable.
6 SMI on Target Abort on Hub interface A Exception (TAHLA_SM I):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an MCH originated
hub interface A cycl e i s com pl eted with "Target A bort" status.
0 = Di sable
5 SMI on Hub interface A Unim pl emented Special Cycle (UNSCA_SMI):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an MCH initiated Hub
interface A request i s terminated with a Unimplem ented Special Cycle completion packet.
0 = Di sable
4 SMI on AGP Access Outsid e of Graphi cs Aperture (OOGF_SMI):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an AGP access
occurs to an address out side of the graphi cs aperture.
0 = Di sable.
3 SMI on Invali d AGP Access (I AAF_SMI):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when an AGP access
occurs to an address out side of the graphi cs aperture and either to the 640 K B – 1 MB range or
above the top of memory.
0 = Di sable.
2 SMI on I n val id Translation Table Entry (ITTEF_SMI):
1 = Enable. When t hi s bit is set, t he generation of the hub interface A S MI mess age i s enabled when
an invalid translation t abl e entry was returned in respons e to an AGP ac cess t o the graphics
aperture.
0 = Di sable.
1 SMI on Multiple-Bit DRAM ECC Error (DMERR_SMI):
1 = Enable. The generati on of the hub interface A SMI message i s enabled when the MCH DRAM
controller detects a multiple-bit error.
0 = Di sable. For s ys tems not supporting ECC this bi t mus t be disabled.
0 SMI on Single-bit ECC Error (DSERR_SMI):
1 = Tthe generation of the hub interfac e A SMI m essage is enabl ed when the MCH DRAM control l er
detect s a single bit error.
0 = Di sable. For system s that do not support ECC, this bit must be disabled.
82840 MCH
R
Datasheet 77
3.4.39. SCICMD—SCI Command Register (Device 0)
Address Offset: CE–CFh
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register enables various errors to generate a SCI message via the hub interface A.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and
SMI error messages are disabled for that same error condition.
Bit Description
15:13 Reserved
12 SCI on Host Uncorrectable Error (HUCS CI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when the MCH detects the
BERR# or the IERR# error condition on the front side bus.
0 = Di sable.
11 SCI on Host Correctable Error (HCS CI):
1 = Enable. The generation of the hub interface A SCI mes sage is enabled when the MCH has
detected a correctabl e single-bit data error on the host bus.
0 = Di sable. This bi t mus t be set t o a 0 i f the syst ems does not i mplement the dat a correction on the
host bus .
10 SCI on External Thermal Sensor Trip (THERM_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when the MCH has
detect ed a ri sing edge on the OVE RT# or t he RDRAM devices report an overtemperat ure
conditions.
0 = Di sable.
9 SCI on LOCK to non-DRAM M emory Flag (LCKF_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when a host initi ated LOCK
cycle t a rget i ng non-DRAM memory space has occurred.
0 = Di sable. If this bi t is s et to “0”, then t he report i ng of this condition i s disabled.
8 SCI on Target Abort on Hub interface B E xcepti on (TAHLB_SCI ):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an MCH originated
hub interface B cycl e i s com pl eted with "Target A bort" status.
0 = Di sable.
7 SCI on Hub interface B Unimpl emented Special Cycle (UNSCB_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an MCH initiated hub
interface B request i s terminated with a Unimplem ented Special Cycle completion packet.
0 = Di sable.
6 SCI on Target Abort on Hub interface A Exception (TAHLA_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an MCH originated
hub interface A cycl e i s com pl eted with "Target A bort" status.
0 = Di sable.
5 SCI on Hub interface A Unimpl emented Special Cycle (UNSCA_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an MCH initiated Hub
interface A request i s terminated with a Unimplem ented Special Cycle completion packet.
0 = Di sable.
78 Datasheet
Bit Description
4 SCI on AGP Access Outsid e of Graphi cs Aperture (OOGF_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an AGP acc es s
occurs to an address out side of the graphi cs aperture.
0 = Di sable.
3 SCI on Invalid AGP Access (IAAF_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an AGP acc es s
occurs to an address out side of the graphi cs aperture and either to the 640 K B – 1 MB range or
above the top of memory.
0 = Di sable.
2 SCI on I nvalid Translation Table Entry (ITTEF_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when an invalid transl ation
table entry was returned i n response to an AG P access to the graphics aperture.
0 = Disable.
1 SCI on Multiple-Bit DRAM ECC Error (DMERR_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when the MCH DRAM
controll er detects a multi pl e-bi t error.
0 = Di sable. For system s not support i ng E CC, this bi t must be di sabled.
0 SCI on Single-bit ECC Error (DSERR_SCI):
1 = Enable. The generati on of the hub interface A SCI mess age i s enabled when the MCH DRAM
controll er detects a single bit error.
0 = Di sable. For s ys tems that do not s upport ECC, this bit must be disabled.
3.4.40. SKPD—Scratchpad Data (Device 0)
Address Offset: DE–DFh
Default Value: 0000h
Access: Read/Write
Size: 16 bits
Bit Description
15:0 Scratchpad [15:0]: Thes e bi ts are si mply R/W storage bits that have no ef fect on t he MCH
functionality.
82840 MCH
R
Datasheet 79
3.4.41. HERRCTL_STS—Host Error Control/Status Register (Device 0)
Address Offset: E0–E1h
Default Value: 0000h
Access: Read/Write, Read/Write Clear
Size: 16 bits
This register enables and reflects the status of various errors checking functions which the MCH supports
on the front side bus.
Bit Description
15 Detected BERR (DBERR)—R/W C:
1 = MCH detected a BE RR# error c ondi tion on the host bus.
0 = Software mus t write a 1 to this field to c l ear i t.
14 Detected IERR (DIERR)—R/WC:
1 = MCH detected an IE RR# error condition on t he host bus.
0 = Software mus t write a 1 to this field to c l ear i t.
13:12 Reserved
11 Host Bus BERR# and IERR# Enab le (BIERRE N)—R/W :
1 = Enable. The detection of ei t her a BERR or an IERR signal on the hos t bus is enabl ed. The type of
mes sage sent is control l ed by the ERRCMD, SCICMD, and S MICMD regis ters.
0 = Di sable.
10 Host Bus M u l tiple Bit Error (HUCERR)—R/WC:
1 = MCH detected an uncorrectable error on the host bus.
0 = Software mus t write a 1 to this bi t to clear i t.
9 Host Bus BERR# Enabl e (HUCBERR)—R/W:
1 = Enable. Generati on of the host bus BERR signal when the MCH detec ts an uncorrec table error on
the host bus data pins i s enabled.
0 = Di sable.
8 Host Bus ECC Generation Strapping Status (HECCSS)—RO: This bit reflects t he status of the MCH
strapping option of enabling t he error correcti ng codes generation for host bus transact i ons.
1 = Enable (via st rappi ng option)
0 = Di sable (via strapping option)
7:0 Host Bus ECC Syndr o me (HECCSYN)—RO: After a host bus ECC error, hardware loads this field
with a syndrome that desc ri bes the set of bits found to be in error. Not e that this field is lock ed from the
time that it i s loaded to the tim e when it is read by software. If the f i rst error was a single bi t, correc table
error, then a subsequent mult iple bit error will overwrite this f i eld. In all other cas es, an error which
occurs af ter the first error and before the register has been read by s of tware will escape recording.
80 Datasheet
3.4.42. DERRCTL_STS—DRAM Error Control/Status Register
(Device 0)
Address Offset: E2–E3h
Default Value: 0000h
Access: Read Only, Read/Write Clear
Size: 16 bits
This register enables and reflects the status of various errors checking functions which the MCH supports
on the DRAM interface.
Bit Description
15:12 Reserved
11 DRAM Correctabl e E CC E rror (DCERR)—R/WC:
1 = MCH detected a correctable error on the DRA M I nt erface.
0 = It is cleared by writing 1 to it or when an uncorrectable error is detect ed on the bus.
10 DRAM Multi p le Bit Error (DUCERR)—R/WC:
1 = MCH detected an uncorrectable error on the DRA M interface.
0 = It is cleared by writing 1 to it.
9:8 Reserved
7:0 DRAM ECC Syndrom e (DECCSYN)—RO: After a DRAM ECC error, hardware loads t his fiel d with a
syndrome that desc ri bes the set of bits found to be in error. Not e that this field is lock ed from t he t i me
that it i s loaded up to the time when it i s read by soft ware. I f the first error was a single bi t, correc table
error, then a subsequent mult iple bit error will overwrite this f i eld. In all other cas es, an error which
occurs af ter the first error and before the register has been read by software will escape recording.
3.4.43. EAP—Error Address Pointer Register (Device 0)
Address Offset: E4–E7h
Default Value: 0000h
Access: Read Only
Size: 32 bits
This register stores the DRAM address when an ECC error occurs.
Bit Description
31:11 E rror Address Pointer (EAP)—RO: Thi s field is used to store the 4 KB block of main mem ory where
an error (single bit or multi-bit error) has occurred. Not e that the value of this bi t field repres ents the
address of the first single or the f i rst m ul tiple bit error occurrence after the error fl ag bi ts in the ERRSTS
register have been cleared by s oftware. A mult iple bit error will overwrite a si ngle bit error.
Once the error f l ag bi t s are set as a result of an error, this bi t field is lock ed and doesn't c hange as a
result of a new error.
10:1 Reserved
0 Error Address Segment (EAS )—RO: This bit indicat es whether the reported error was found on
Rambus * channel 0 or on channel 1.
1 = Channel 1
0 = Channel 0
82840 MCH
R
Datasheet 81
3.4.44. AGPBCTRL—AGP Buffer Strength Control Register
Address Offset: E8–EBh
Default Value: 0000h
Access: Read/Write
Size: 32 bits
This register controls the 3.3V AGP buffer strength. The prop er setting is documented in the Intel
840
BIOS Specification Update.
Bit Description
31:24 AGP Buffer Strength Control 1:
23:16 AGP Buffer Strength Control 2:.
15:0 Reserved
3.4.45. AGPAPPEND—AGP Append Disable Register
Address Offset: F6h
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register controls the AGP interface.
Bit Description
7:6 Reserved
5 AGP Append Disable:
1 = Disable CP U-t o-AGP Writ e A ppendi ng
0 = Enable (default).
4:0 Reserved
3.4.46. GTLNCLAMP—GTL N Clamp Disable Register
Address Offset: F7h
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7 Reserved
6:5 GTL N-Clamp Disable Register:
10 = Disable.
4:0 Reserved
82 Datasheet
3.5. AGP Bridge Registers (Device 1)
Table 5 summarizes the MCH configuration space for Device 1.
Table 5. MCH Configuration Space (Device 1)
Address
Offset Symbol Register Name Default
Value Access
00–01h VID1 Vendor Identification 8086h RO
02–03h DID1 Device Identification 1A23h RO
04–05h PCICMD1 PCI Command Register 0000h R/W
06–07h PCISTS 1 P CI S tatus Register 0020h RO, R/WC
08 RID1 Revision Identification 00h RO
09 Reserved 00h
0Ah SUBC1 Sub-Class Code 04h RO
0Bh B CC1 Base Class Code 06h RO
0Ch Reserved 00h
0Dh MLT1 Master Latency Timer 00h R/W
0Eh HDR1 Header Type 01h RO
0F–17h Reserved 00h
18h PBUSN1 Primary Bus Number 00h RO
19h SBUSN1 Secondary B us Number F0h R/W
1Ah SUBUSN1 Subordinate Bus Number 00h R/W
1Bh SMLT1 Secondary Bus Master Latency Timer 00h R/W
1Ch I OBASE1 I/O Base Addres s Regis ter 00h R/ W
1Dh IOLIMIT1 I/O Limi t Address Regi ster 00h R/W
1E–1Fh SSTS1 S e condary Status Regist er 02A0h RO, R/WC
20–21h MBAS E1 Memory Bas e A ddress Regist er FFF0h R/W
22–23h MLIMIT1 Mem ory Li mit Address Regi ster 0000h R/W
24–25h PMBA S E1 Prefetchable Memory Base Address Reg. FFF0h R/W
26–27h PMLIMIT1 Prefetchable Memory Limit Address Reg. 0000h R/W
28–3Dh Reserved
3Eh BCTRL1 Bridge Control Regist er 00h R/W
3Fh Reserved
40h ERRCMD1 Error Command 00h R/W
41–FFh Reserved
82840 MCH
R
Datasheet 83
3.5.1. VID1—Vendor Identi fi cation Register (Device 1)
Address Offset: 00–01h
Default Value: 8086h
Attribute: Read Only
Size: 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the
Device Identification Register uniquely identify any PCI device. Writes to this register have no effect.
Bit Description
15:0 Vendor Identification Number: This i s a 16-bit value as signed to Intel. Intel VID = 8086h.
3.5.2. DID1—Device Identification Register (Device 1)
Address Offset: 02–03h
Default Value: 1A23h
Attribute: Read Only
Size: 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Writes to this register have no effect.
Bit Description
15:0 Device Identification Numb er: This is a 16 bit value assigned to the MCH Device 1.
The MCH Device 1 DID = 1A23h.
84 Datasheet
3.5.3. PCICMD1—PCI-PCI Command Register (Device 1)
Address Offset: 04–05h
Default: 0000h
Access: Read Only, Read/Write
Size 16 bits
Bit Descriptions
15:10 Reserved
9 Fast Back-to-Back—RO: (Not Appli cabl e). Hardwired to 0.
8 SERR M essage Enable (SE RRE 1)—R/ W. This bit i s a global enable bit for Device 1 SERR
mes saging. The MCH does not have an SERR# signal . The MCH c omm uni cates t he S ERR# conditi on
by sending an SE RR message to the I CH.
1 = Enable. The MCH is enabl ed t o generate SERR messages over the hub interf ace for specific
Device 1 error condi tions that are individuall y enabled i n the BCTRL regist er. The error stat us is
reported in the P CI S TS1 register.
0 = Disable. The SERR message is not generated by the MCH for Device 1.
NOTE: This bit only c ontrols SERR mes saging for the Devi ce 1. Devic e 0 has its own SERRE bit to
control error reporting for error condi tions oc curring on Device 0.
7 Address/Data Stepping—RO: (Not appl i cable). Hardwired to 0.
6 Parity Error E nable (PERRE1)— RO: PERR# is not supported on AGP . Hardwired to 0.
5 Reserved
4 Memory Write and Invalidate Enabl e—RO: (Not Implem ented). Hardwired to 0.
3 Special Cycle Enable—RO: (Not I m plemented). Hardwired to 0.
2 Bus Master En abl e (BME1)— R/W:
1 = Enable. AGP Master initiated FRAME# cyc l es will be accepted by the MCH, if they hit a valid
address dec ode range.
0 = Disable (default). A GP Master initiated FRA ME# c yc les will be ignored by the MCH resulting in a
Master Abort .
Note that inc oming configuration cycles still need t o be ac cepted regardless of the setting of this Bus
Master Enable bi t . This bit has no affec t on AGP Mast er ori gi nat ed SBA or PI PE# cycl es.
1 Memo ry Access Enable (MAE1)—R/W:
1 = Enable. This bit must be 1 t o enabl e the Memory and Pref et chable m emory address ranges
defined in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
0 = Disable. All of Device 1’s memory space is di sabled.
0 I/O Access Enable (IOAE1)— R/W: Thi s bit m ust be set to1 to enable the I /O address range def i ned
in the IOBASE1, and I OLI MIT1 regis ters. When s et to 0 all of Device 1’s I/ O s pace is disabled.
82840 MCH
R
Datasheet 85
3.5.4. PCISTS1—PCI-PCI Status Register (Device 1)
Address Offset: 06–07h
Default Value: 0000h
Access: Read Only, Read/Write Clear
Size: 16 bits
PCISTS1 is a 1 6 -bit status register that reports the occurrence of error conditions associated with the
primary side of the “virtual” PCI-PCI bridge in the MCH. Since this device does not physically reside on
PCI_A, it reports the optimum operating conditions so that it does not restrict the capability of PCI_A.
Bit Descriptions
15 Detected Parity Error (DPE1)—RO: (Not Applicable). Hardwired to 0.
14 Signaled System Error (SSE1)—R/WC:
1 = MCH Device 1 generates an S ERR mes sage over the hub int erface A f or any enabl ed Devi ce 1
error conditi on. Device 1 error condi tions are enabled i n t he PCICMD1 and BCTRL1 regist ers.
Device 1 error fl ags are read/reset from t he SSTS1 register.
0 = Software clears this bi t by writing a 1 to it .
13 Received Master Abort Status (RMAS1)— RO: (Not Applicable). Hardwired to 0.
12 Received Target Abort Status (RTAS1) —RO: (Not Applicable). Hardwired to 0.
11 Signaled Target Abort Status (STAS1) (RO): (Not Applicable). Hardwired to 0.
10:9 DEVSEL# Timing (DEVT1): This bit field is hardwired to “00b” to indicat e that the Device 1 uses t he
fastest possible decode.
8 Data Parity Detected (DPD1)—RO: Parity is not support ed on AGP port. Hardwired to 0.
7 Fast Back-to-Back (FB2B1)—RO: AGP port always supports fast back to bac k transac tions.
Hardwired to 1.
6 Reserved.
5 33/66 MHz Capability—RO: AGP port is 66 MHz capabl e. Hardwired to 1.
4:0 Reserved.
3.5.5. RID1—Revision Identification Register (Device 1)
Address Offset: 08h
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the revision number of the MCH device 1. These bits are read only and writes to
this register have no effect. For the A-0 Stepp ing, this value is 00h.
Bit Description
7:0 Revisi on I d enti fication Number: Thi s is an 8-bit value that indi cates t he revi sion identificati on number
for the MCH Devic e 1.
86 Datasheet
3.5.6. SUBC1—Sub-Class Code Register (Device 1)
Address Offset: 0Ah
Default Value: 04h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the MCH device 1.
Bit Description
7:0 Su b -Class Code (SUBC1): This is an 8-bit value t hat indicates the cat egory of Bridge for t he MCH.
04h = PCI-to-P CI Bridge.
3.5.7. BCC1—Base Class Code Register (Device 1)
Address Offset: 0Bh
Default Value: 06h
Access: Read Only
Size: 8 bits
This register contains the Base Class Code of the MCH device 1.
Bit Description
7:0 Base Class Code (BASEC): This i s an 8-bit value t hat indicat es the Bas e Cl ass Code for t he MCH
device 1.
06h = Bridge device.
3.5.8. MLT1—Master Latency Timer Register (Device 1)
Address Offset: 0Dh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This functionality is not applicab le. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-PCI bridge configuration software from getting “confused” .
Bit Description
7:3 Not applicable but s upport read/write operations. (Reads return previously written data. )
2:0 Reserved.
3.5.9. HDR1—Header Type Register (Device 1)
Offset: 0Eh
Default: 01h
Access: Read Only
Size: 8 bits
This register identifies the header layout of the configuration space.
Bit Descriptions
7:0 Header Type: Hardwired to 01h.
82840 MCH
R
Datasheet 87
3.5.10. PBUSN1—Primary Bus Number Register (Device 1)
Offset: 18h
Default: 00h
Access: Read Only
Size: 8 bits
This register identifies that “virtual” PCI-PCI bridge is connected to bus #0.
Bit Descriptions
7:0 Pri mary Bus Number: Hardwired to 00h.
3.5.11. SBUSN1—Secondary Bus Number Register (Device 1)
Offset: 19h
Default: 00h
Access: Read /Write
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI bridge
(i.e., to AGP). This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to AGP.
Bit Descriptions
7:0 Secondary Bus Number: Programmable. Def aul t=00h.
3.5.12. SUBUSN1—Subordi nate Bus Number Register (Device 1)
Offset: 1Ah
Default: 00h
Access: Read /Write
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP. This number is
programmed by the PCI confi guration software to a llow mapping of co nfi guration cycles to AGP.
Bit Descriptions
7:0 Subordinate Bus Number: Programmabl e. Default = 0.
88 Datasheet
3.5.13. SMLT1—Secondary Master Latency Ti mer Register (Device 1)
Address Offset: 1Bh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register controls the bus tenure of the MCH on AGP. SMLT1 controls the amount of time the MCH,
as a AGP/PCI bus master, can burst data on the AGP Bus. The Count Value is an 8 bit quantity;
however, MLT[2:0] are reserved and assumed to be 0 when determining the Count Value. The SMLT1 is
used to guarantee to the AGP master a minimum amount of the system resources. When the MCH begins
the first AGP FRAME# cycle after being granted the bus, the counter is loaded and enabled to count
from the assertion of FRAME#. If the count expires while the MCH’s grant is removed (due to AGP
master request), the MCH loses the use of the bus, and the AGP master agent may be granted the bus. If
the MCH’s bus grant is not removed, the MCH continues to own the AGP bus, regardless of the SMLT1
expiration or idle condition. Note that the MCH must always properly terminate an AGP transaction,
with FRAME# negation prior to the final data transfer.
The number of clocks programmed in the SMLT1 represents the guaranteed time slice (measured in
66 MHz AGP clocks) allotted to the MCH, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT1 is
programmed to 18h, then the value is 24 AGP clocks. The default value of 00h disables this function.
When the SMLT1 is disabled, the burst time for the MCH is unlimited (i.e., the MCH can burst forever).
Bit Description
7:3 Secondary M LT Counter Value: Default =0 (i .e., SMLT1 disabled)
2:0 Reserved.
3.5.14. IOBASE1—I/O Base Address Register (Device 1)
Address Offset: 1Ch
Default Value: F0h
Access: Read/Write
Size: 8 bits
This register control the host to AGP I/O access routing based on the following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
treated as 0. T hus, the bottom of the defined I/O add r ess range will be aligned to a 4 KB boundary.
Note: BI OS must not set this register to 00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to AGP.
Bit Description
7:4 I/ O Address Base: Corresponds to A[15:12] of the I/O addres s. Default=F0h
3:0 Reserved.
82840 MCH
R
Datasheet 89
3.5.15. IOLIMIT1—I/O Limit Address Register (Device 1)
Address Offset: 1Dh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register controls the host to AGP I/O access routing based on the following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O ad dress range will be at the top of a 4 KB aligned
address block.
Bit Description
7:4 I/ O Address Limit: Corresponds to A[15:12] of t he I /O address. Default=0
3:0 Reserved. (Onl y 16 bit address i ng supported.)
3.5.16. SSTS1—Secondary PCI-PCI Status Register (Device 1)
Address Offset: 1E–1Fh
Default Value: 02A0h
Access: Read Only, Read/Write Clear
Size: 16 bits
SSTS is a 16 -bit status register that reports the occurrence of error conditions associated with the
secondary side (i.e., AGP side ) of the “virtual” PCI-PCI bridge in the MCH.
Bit Descriptions
15 Detected Parity Error (DPE1)—R/W C:
1 = MCH detected a parity error in the address or data phase of AGP bus t ransactions.
0 = Software sets DPE1 to 0 by writing a 1 to this bit.
Note that the funct i on of this bi t is not affect ed by the PERRE1 bi t. Also note that P ERR# is not
impl emented in the MCH.
14 Received System Error (SSE1)—R/WC:
1 = MCH generates an SERR message for any enabled error condi tion under device 1. Device 1 error
conditi ons are enabled in the BCTRL1 regi ster.
0 = Software clears SSE1 to 0 by writing a 1 to this bit.
13 Received Master Abort Status (RMAS1)—R/WC:
1 = MCH terminates a Host -to-AGP with an unexpected master abort.
0 = Software reset s this bi t to 0 by writing a 1 to it.
12 Received Target Abort Status (RTAS1)—R/WC:
1 = MCH-initiated t ransaction on AGP is terminated with a target abort.
0 = Software reset s RTAS1 to 0 by writing a 1 to it.
90 Datasheet
Bit Descriptions
11 Signaled Target Abort Status (STAS1)—RO: MCH does not generate target abort on AGP .
Hardwired to a 0.
10:9 DEVSEL# Timing (DEVT1)—RO: This 2-bit field indicates the tim ing of the DEVSEL# signal when the
MCH responds as a t arget on AGP, and i s hardwired to the value 01b (medium) to indicat e the time
when a valid DEVSE L# can be sam pl ed by the initiator of the P CI cycle.
8 Data P arity Detected (DPD1)—RO: (Not I mplemented): Hardwired to 0. MCH does not impl ement
G_PERR# function. However, data parity errors are still detected and reported via t he hub interface A
(if enabled by SERRE1 bit of the PCICMD1 regist er and bi t 0 of the B CTRL register).
7 Fast Back-to-Back (FB2B1)—RO: MCH, as a target, support s fast back-to-bac k transac tions on AG P .
Hardwired to 1.
6 Reserved
5 33/66 MHz Capable (CAP66)—RO: A GP bus is capable of 66 MHz operation. Hardwired to 1.
4:0 Reserved.
3.5.17. MBASE1—Memory Base Address Register (Device 1)
Address Offset: 20–21h
Default Value: FFF0h
Access: Read/Write
Size: 16 bits
This register controls the host to AGP non-prefetchable memory access routing based on the following
formula:
MEMORY_BASE1 ≤ address ≤ MEMORY_LIMIT1
The upper 12 bits of this register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1 MB boundary.
Bit Description
15: 4 M emory Address Base 1 (M EM_BASE1): Corresponds t o A[31:20] of the m emory address .
3:0 Reserved.
82840 MCH
R
Datasheet 91
3.5.18. MLIMIT1—Memory Limit Address Register (Device 1)
Address Offset: 22–23h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register controls the host to AGP non-prefetchable memory access routing based on the following
formula:
MEMORY_BASE1 ≤ address ≤ MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to b e FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1 MB aligned memory block.
Bit Description
15: 4 M em o ry Address Limit 1(MEM_LIM IT1): Corresponds t o A[31:20] of the m emory address. Default=0
3:0 Reserved.
Note: Memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable AGP
address ranges (typically, where control/status memory-mapped I/O data structures of the graphics
controller will reside) and P M BASE 1and PMLIMIT1 are used to map prefetchable address ranges
(typically, graphics local memory). This segregation allows application of USWC space attribute to be
performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP
memory access performance.
3.5.19. PMBASE1—Prefetchable M emory Base Address Register
(Device 1)
Address Offset: 24–25h
Default Value: FFF0h
Access: Read/Write
Size: 16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE1 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1 MB boundary.
Bit Description
15: 4 Prefetchabl e Memory Address Base 1(PMEM _BASE1): Corresponds to A[31:20] of t he mem ory
address.
3:0 Reserved.
92 Datasheet
3.5.20. PMLIM I T1—Prefetchable Memory Limit Address Register
(Device 1)
Address Offset: 26–27h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register controls the host to AGP prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE1 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to b e FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1 MB aligned memory block.
Note: A prefetchable memory range is supported to allow segregation by the configuration software between
the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e.,
prefetchable) from the processor perspective.
Bit Description
15: 4 Prefetchabl e Memory Address Limi t 1(P MEM_LIMIT1): Corresponds t o A[31:20] of the memory
address. Default=0
3:0 Reserved.
3.5.21. BCTRL1—PCI-PCI Bridge Control Register (Device 1)
Address Offset: 3Eh
Default: 00h
Access: Read Only, Read/Write
Size 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary interface (i.e., AGP) as well as some bits that
affect the overall behavior of the “virtual” PCI-PCI bridge embedded within MCH (e.g., VGA
compatible address ranges mapping).
82840 MCH
R
Datasheet 93
Bit Descriptions
7 Fast Back to Back Enable—RO: Since there i s only one target al l owed on AGP this bit i s
meaningles s .Hardwired to 0. The MCH will not generate FB2B cycl es in 1x mode, but will generate
FB2B cyc l es in 2x and 4x Fast Write modes.
6 Secondary Bus Reset—RO: MCH does not support generation of reset via this bit on the AGP.
Hardwired to 0.
Note that t he onl y way to perf o rm a hard reset of the AGP i s via the system reset eit her i ni tiated by
soft ware or hardware via ICH.
5 Master Abort Mode—RO: Hardwired to 0. This means when act i ng as a mas t er on AGP the MCH will
discard data on writes and return all 1s during reads when a Master Abort occurs.
4 Reserved
3 VGA Enable (VGAEN1)—R/W: Controls the routing of host, hub interface A, and hub interface B
initiated transac tions targeting VGA compat i bl e I/O and m emory address ranges.
1 = Enable. MCH forwards t he following host access e s to the AG P :
• mem ory ac cesses in t he range 0A0000h–0BFFFFh
• I/O address es where A[9:0] are in the ranges 3B0h–3BBh and 3C0h–3DFh
(inclus i ve of ISA address aliases; A [15:10] are not decoded)
When enabled, f orwarding of t hese accesses issued by the hos t is independent of the I/ O address
and memory address ranges defined by the previ ously defined bas e and l i mit regi sters. Forwarding
of these accesses is al so independent of t he settings of bit 2 (ISA Enabl e) of this regi ster, if this bi t
is 1.
0 = Disable. V G A compatible m emory and I/ O range accesses are not f orwarded to AGP; rather, t hey
are mapped t o pri mary PCI unl ess they are mapped to A GP via I/O and mem ory range regi sters
defined above (IOBASE1, IOLIMIT1, MBASE1, MLIMIT1, PMBASE1, PMLIMIT1)
Refer to the System Addres s Map Chapter for further information.
2 ISA Enable —R/W: Modifies the response by the MCH to an I/O ac cess i ssued by the host that
targets I SA I/O addresses. Thi s applies onl y t o I/O address es that are enabled by the IOBA S E and
IOLIMIT regis ters.
1 = MCH will not forward to AGP any I/O trans actions addressing the last 768 bytes in each 1 KB
block, even if the addresses are within the range defined by the I O B ASE and IOLIMIT registers.
Inst ead of goi ng to AGP t hese cycles are forwarded to PCI0 where they can be subtractively or
positi vel y claim ed by the ISA bridge.
0 = Disable (def aul t ). All addres ses defined by the IOBASE and IOLIMIT for host I /O transac t i ons are
mapped t o A GP.
1 SERR# En ab le (SERRE )—R/W : This bi t controls t he forwarding of SERR# on the secondary inte rf ace
to the primary inte rf ace.
1= Enable SE RRE . MCH generates SE RR mess ages to hub int erf ace A when the SERR# pin on AGP
bus is asserted and when the messages are enabled by the SE RRE 1 bi t in the PCI CMD1 register.
0 = Disable.
0 Parity Error Response En abl e—R/ W: Controls MCH’s response to dat a phase parity errors on A G P .
Note that G_PERR# is not impl emented by t he MCH.
1 = Address and data parity errors on AGP are reported via S ERR# mechanism, if enabl ed by
SERRE1 and SERRE.
0 = Address and dat a parity errors on AG P are not reported via the MCH SERR# signal. Other types of
error conditions can still be s ignaled vi a S E RR# independent of this bit’ s state.
94 Datasheet
3.5.22. ERRCMD1—Error Command Register (Device 1)
Address Offset: 40h
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7:1 Reserved
0 SERR on Receiving Target Abort (S ERTA):
1 = MCH generates an SERR mes sage over hub interface A upon receivi ng a t arget abort on AGP .
0 = MCH does not as sert an SERR mess age upon receipt of a target abort on AG P . SERR messagi ng
for Device 1 i s globally enabled in the PCICMD1 register.
82840 MCH
R
Datasheet 95
3.6. Hub interface B Bridge Registers (Device 2)
Table 6 summarizes the MCH configuration space for device 2.
Table 6. MCH Configuration Space (Device 2)
Address
Offset Symbol Register Name Default Access
00–01h VID2 Vendor Identi ficati on 8086h RO
02–03h DID2 Device Identification 1A24h RO
04–05h PCICMD2 PCI Command Register 0000h R/W
06–07h PCIS TS2 PCI Status Register 0020h RO, R/WC
08 RID2 Revision Identification 00h RO
09 Reserved 00h
0Ah SUBC2 Sub-Class Code 04h RO
0Bh BCC2 Base Class Code 06h RO
0Ch Reserved 00h
0Dh MLT2 Master Latency Timer 00h R/W
0Eh HDR2 Header Type 01h RO
0F–17h Reserved 00h
18h PBUSN2 Primary Bus Number 00h RO
19h SBUSN2 Secondary B us Number 00h R/W
1Ah SUBUSN2 Subordinate Bus Number 00h R/W
1Bh SMLT2 Secondary Bus Master Latency Timer 00h R/ W
1Ch IOBASE2 I/O Base Address Register F0h R/W
1Dh I O LI MI T2 I/O Limit Address Register 00h R/W
1E–1Fh SSTS2 S econdary Status Register 02A0h RO, R/WC
20–21h MBASE2 Memory Base Address Regis t er FFF0h R/ W
22–23h MLIMIT2 Memory Limit Address Regis ter 0000h R/ W
24–25h PMBASE2 Prefetc hable Memory Base Addres s Reg. FFF0h R/W
26–27h PMLIMIT2 P refetchable Memory Lim i t Address Reg. 0000h R/W
28–3Dh Reserved
3Eh BCTRL2 Bridge Control Register 00h R/W
3Fh Reserved
40h ERRCMD2 Error Command 00h R/W
41–FFh Reserved
96 Datasheet
3.6.1. VID2—Vendor Identi fi cation Register (Device 2)
Address Offset: 00–01h
Default Value: 8086h
Attribute: Read Only
Size: 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the
Device Identification Register uniquely identify any PCI device. Writes to this register have no effect.
Bit Description
15:0 Vendor Identification Number: This i s a 16-bit value as signed to Intel. Intel VID = 8086h.
3.6.2. DID2—Device Identification Register (Device 2)
Address Offset: 02–03h
Default Value: 1A24h
Attribute: Read Only
Size: 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Writes to this register have no effect.
Bit Description
15:0 Device Identification Numb er: This is a 16 bit value assigned to the MCH Device 2.
The MCH Device 2 DID = 1A24h.
82840 MCH
R
Datasheet 97
3.6.3. PCICMD2—PCI-PCI Command Register (Device 2)
Address Offset: 04–05h
Default: 0000h
Access: Read Only, Read/Write
Size 16 bits
Bit Descriptions
15:10 Reserved.
9 Fast Back-to-Back—RO: (Not applicable). Hardwired to 0.
8 SERR M essage Enable (SE RRE 2)—R/ W: This bit is a global enabl e bi t for Devic e 2 S ERR
mes saging. The MCH does not have an SERR# signal . The MCH c omm uni cates t he S ERR# conditi on
by sending an SE RR message to the I CH.
1 = Enable. MCH is enabl ed to generate SERR mess ages over the hub interface A f or specifi c
Device 2 error condi tions that are individuall y enabled i n the BCTRL2 regist er. The error stat us is
reported in the P CI S TS2 register.
0 = SERR message i s not generated by t he MCH for Devi ce 2.
NOTE: This bit only c ontrols SERR mes saging for the Devi ce 2. Devic e 0 has its own SERRE bit to
control error reporting for error condi tions oc curring on Device 0.
7 Address/Data Stepping—RO: (Not appl i cable). Hardwired to 0.
6 Parity Error E nable (PERRE2)—R/W: (Not applicable). S upported as a read/write bit to avoid is sues
with standard PCI-PCI Bridge configurati on software.
5 Reserved.
4 Memory Write and In val idate Enable—R/ W: (Not applicable). S upported as a read/write bit to avoid
issues with standard P CI -P CI Bridge configuration s of tware.
3 Special Cycle Enable—R/W: (Not appl icable). S upported as a read/write bit to avoid is sues with
standard PCI-PCI Bridge configurati on software.
2 Bus Master En abl e (BME2)—R/W:
1 = Enable. Device#2 (virtual P 2P bridge) operates as a master on the primary interface on behalf of a
mas ter on the sec ondary i nterface f or mem ory or I/O trans action.
0 = Disable. Devi ce 2 disables response t o al l memory or I/O transacti ons on the sec ondary i nterface.
1 Memo ry Access Enabl e (MAE2)—R/W: (Not appl icable). Support ed as a read/write bit to avoid
issues with standard P CI -P CI Bridge configuration s of tware.
0 I/O Access Enable (IOAE2)—R/W: (Not appl icable). S upport ed as a read/write bit to avoid iss ues
with standard PCI-PCI Bridge configurati on software.
98 Datasheet
3.6.4. PCISTS2—PCI-PCI Status Register (Device 2)
Address Offset: 06–07h
Default Value: 00A0h
Access: Read Only, Read/Write Clear
Size: 16 bits
PCISTS2 reports the occurrence of error conditions associated with the primary side of the “virtual” PCI-
PCI bridge in the MCH. Since this device does not physically reside on PCI_A, it reports the optimum
operating conditions so that it does not restrict the capability of PCI_A.
Bit Descriptions
15 Detected Parity Error (DPE2)—RO: (Not Applicable). Hardwired to 0.
14 Signaled System Error (SSE2)—R/WC:
1 = MCH Device 2 generates an S ERR message over the hub interface A for any enabled Device 2
error conditi on. Device 2 error condi tions are enabled i n t he PCICMD2 and BCTRL2 regist ers.
Device 2 error fl ags are read/reset f rom the S S TS2 register.
0 = Software clears this bi t by writing a 1 to it .
13 Received Master Abort Status (RMAS2)—RO: (Not Applicable). Hardwired to 0.
12 Received Target Abort Status (RTAS2)—RO: (Not Applicable). Hardwired to 0.
11 Signaled Target Abort Status (STAS2)—RO: (Not Applicable). Hardwired to 0.
10:9 DEVSEL# Timing (DEVT2)—RO: Device 2 uses the fastes t possi bl e decode. Hardwired to 00.
8 Data P arity Detected (DPD2)—RO: (Not Applicable). Hardwired to 0.
7 Fast Back-to-Back (FB2B2)—RO: Fast back-to-bac k writes are always support ed. Hardwired to 1.
6 Reserved.
5 33/66 MHz Capability—RO: Capable of 66 MHz operation. Hardwired to 1.
4:0 Reserved.
3.6.5. RID2—Revision Identification Register (Device 2)
Address Offset: 08h
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the revision number of the MCH Device 2. These bits are read only and writes to
this register have no effect.
Bit Description
7:0 Revisi on I d entification Number: This is an 8-bit value t hat indicat es the revisi on i dentific ation
number f or the MCH Device 2.
A-0 Stepping = 00h.
82840 MCH
R
Datasheet 99
3.6.6. SUBC2—Sub-Class Code Register (Device 2)
Address Offset: 0Ah
Default Value: 04h
Access: Read Only
Size: 8 bits
This register contains the Sub-Class Code for the MCH Device 2.
Bit Description
7:0 Sub-Cl ass Code (SUBC2): This is an 8-bit val ue that indic ates the c a t egory of Bridge for the MCH.
04h = PCI-PCI Bridge.
3.6.7. BCC2—Base Class Code Register (Device 2)
Address Offset: 0Bh
Default Value: 06h
Access: Read Only
Size: 8 bits
This register contains the Base Class Code of the MCH Device 2.
Bit Description
7:0 Base Class Code (BASEC2): This i s an 8-bit value t hat indicates the B ase Class Code for the MCH
Device 2.
06h = Bridge device.
3.6.8. MLT2—Master Latency Timer Register (Device 2)
Address Offset: 0Dh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This functionality is not applicab le. It is described here since these bits should be implemented as a
read/write to prevent issues with standard PCI-PCI bridge configuration software.
Bit Description
7:3 M LT Count Value: Not appli cable but support read/write operations . (Reads return previously written
data.)
2:0 Reserved.
3.6.9. HDR2—Header Type Register (Device 2)
Offset: 0Eh
Default: 01h
Access: Read Only
Size: 8 bits
This register identifies the header layout of the configuration space.
Bit Descriptions
7:0 Header Type: This read only field always returns 01h when read. Writ es have no effec t.
100 Datasheet
3.6.10. PBUSN2—Primary Bus Number Register (Device 2)
Offset: 18h
Default: 00h
Access: Read Only
Size: 8 bits
This register identifies that “virtual” PCI-PCI bridge is connected to bus #0.
Bit Descriptions
7:0 Pri mary Bus Number: Hardwired to 0.
3.6.11. SBUSN2—Secondary Bus Number Register (Device 2)
Offset: 19h
Default: 00h
Access: Read /Write
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI bridge
(the hub interface B connection). This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to a second bridge device connected to hub interface B.
Bit Descriptions
7:0 Secondary Bus Number: P rogramm abl e. Default=00h.
3.6.12. SUBUSN2—Subordi nate Bus Number Register (Device 2)
Offset: 1Ah
Default: 00h
Access: Read /Write
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below the secondary hub
interface. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to devices subordinate to the secondary hub interface port.
Bit Descriptions
7:0 Subordinate Bus Number: Programmabl e Def aul t = 0.
3.6.13. SMLT2—Secondary Master Latency Ti mer Register (Device 2)
Address Offset: 1Bh
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7:3 Secondary M L T counter value (SMLT): Default=0 (S MLT dis abl ed)
2:0 Reserved.
82840 MCH
R
Datasheet 101
3.6.14. IOBASE2—I/O Base Address Register (Device 2)
Address Offset: 1Ch
Default Value: F0h
Access: Read/Write
Size: 8 bits
This register controls the host to hub interface B I/O access routing based on the following formula:
IO_BASE2 ≤ address ≤ IO_LIMIT2
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
treated as 0. T hus, the bottom of the defined I/O add r ess range will be aligned to a 4 KB boundary.
Bit Description
7:4 I/ O Address Base 2: Corresponds t o A [15:12] of t he I/O addresses pass ed by the device 2 bridge to
hub interfac e B. Default = Fh
3:0 Reserved.
3.6.15. IOLIMIT2—I/O Limit Address Register (Device 2)
Address Offset: 1Dh
Default Value: 00h
Access: Read/Write
Size: 8 bits
This register controls the host to hub interface B I/O access routing based on the following formula:
IO_BASE2 ≤ address ≤ IO_LIMIT2
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O ad dress range will be at the top of a 4 KB aligned
address block.
Bit Description
7:4 I/ O Address Limit: Corresponds to A[15:12] of t he I/O address l i mit of Device 2. Default=0
3:0 Reserved. (Onl y 16 bit address i ng supported.)
102 Datasheet
3.6.16. SSTS2—Secondary PCI-PCI Status Register (Device 2)
Address Offset: 1E–1Fh
Default Value: 02A0h
Access: Read Only, Read/Write Clear
Size: 16 bits
SSTS2 reports the occurrence of error conditions associated with secondary side (i.e., hub interface B
side ) of the “virtual” PCI-PCI bridge embedded within MCH.
Bit Descriptions
15 Detected Parity Error (DPE2)—R/WC: This bit is s et to a 1 to indicate MCH’s det ection of a pari t y
error in the address or data phase of hub i nterface B bus transac tions. S oftware clear this bit by writing
a 1 to this bi t.
Note that the funct i on of this bi t is not affect ed by the PERRE2 bi t. Also note that P ERR# is not
impl emented in the MCH.
14 Received System Error (SSE2)—R/WC:
1 = MCH received an SERR mess age across t he hub i nterface B .
0 = Software clears this bi t by writing a 1 to thi s bit.
13 Received Master Abort Status (RMAS2)—R/WC:
1 = MCH terminates a Host -to-hub interface B with an unexpected m aster abort.
0 = Software clears this bi t to 0 by writing a 1 to i t .
12 Received Target Abort Status (RTAS2)—R/WC:
1 = MCH-initiated transact i on on hub i nterface B i s terminated with a target abort.
0 = Software clear this bit by writi ng a 1 t o i t.
11 Signaled Target Abort Status (STAS2)—RO: (Not Applicable). Hardwired to 0.
10:9 DEVSEL# Timing (DEVT2)—RO: This 2-bit field indicates the tim ing of the DEVSEL# signal when the
MCH responds as a t arget on hub interface B, and is hard-wired to the value 01b (medium) to indicat e
the time when a valid DEVSEL# can be sampled by the initiat or of t he PCI c yc l e.
01 = Medium
8 Data Parity Detected (DPD2)—RO: (Not Applic abl e). Hardwired to 0.
7 Fast Back-to-Back (FB2B2)—RO: MCH as a target supports f ast back -to-back t ransacti ons on hub
interface B. Hardwired to 1.
6 Reserved
5 33/66MHz Capabl e (CAP66)—RO: Hub interface B is capable of 66 MHz operation.
Hardwired to 1.
4:0 Reserved.
82840 MCH
R
Datasheet 103
3.6.17. MBASE2—Memory Base Address Register (Device 2)
Address Offset: 20–21h
Default Value: FFF0h
Access: Read/Write
Size: 16 bits
This register controls the host to hub interface B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE2 ≤ address ≤ MEMORY_LIMIT2
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1 MB boundary.
Bit Description
15: 4 M emory Address Base 2 (M EM_BASE2): Corresponds t o A[31:20] of the lower limi t memory address
that will be passed by the Device 2 to hub interfac e B.
3:0 Reserved.
3.6.18. MLIMIT2—Memory Limit Address Register (Device 2)
Address Offset: 22–23h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register controls the host to hub interface B non-prefetchable memory access routing based on the
following formula:
MEMORY_BASE2 ≤ address ≤ MEMORY_LIMIT2
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to b e FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1MB aligned memory block.
Bit Description
15: 4 M em o ry Address Limit 2(MEM_LIM IT2): Bits 15:4 correspond to A[31:20] of the upper li mit mem ory
address that will be passed by the Device 2 t o hub int erface B. Default=0
3:0 Reserved.
Note: Memory range covered by MBASE2 and MLIMIT2 registers are used to map non-prefetchable hub
interface B address ranges (typically, where control/status memory-mapped I/O data structures of the
graphics controller will reside) and PMBASE2 and PMLIMIT2 are used to map prefetchable address
ranges (typ ically, graphics local memory). This segregation allows application of USWC space attribute
to be performed in a true plug-and-play manner to the prefetchable address range for improved host-hub
interface B memory access performance.
104 Datasheet
3.6.19. PMBASE2—Prefetchable M emory Base Address Register
(Device 2)
Address Offset: 24–25h
Default Value: FFF0h
Access: Read/Write
Size: 16 bits
This register controls the host to hub interface B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE2 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT2
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1 MB boundary.
Bit Description
15: 4 Prefetchabl e Memory Address Base 2(PMEM _BASE2): Bits 15:4 c orrespond to A[31:20] of t he
memory address .
3:0 Reserved.
3.6.20. PMLIM I T2—Prefetchable Memory Limit Address Register
(Device 2)
Address Offset: 26–27h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register controls the host to hub interface B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE2 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT2
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The lower 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode, address bits
A[19:0] are assumed to b e FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1 MB aligned memory block.
Bit Description
15: 4 Prefetchabl e Memory Address Limi t 2(P MEM_LIMIT2): Bits 15:4 corres pond to A[31:20] of the
memory address . Default=0
3:0 Reserved.
Note that prefetchable memory range is supported to allow segregation by the configuration software
between the memory ranges that must be defined as UC and the ones that can be designated as a USWC
(i.e. prefetchable) from the processor perspective.
82840 MCH
R
Datasheet 105
3.6.21. BCTRL2—PCI-PCI Bridge Control Register (Device 2)
Address Offset: 3Eh
Default: 00h
Access: Read/Write
Size 8 bits
This register provides extensions to the PCICMD2 register that are specific to PCI-PCI bridges. The
BCTRL2 provides add itional control for the secondary interface (i.e., hub interface B) as well as some
bits that affect the overall behavior of the “virtual” PCI-PCI bridge in the MCH (e.g., VGA compatible
address ranges mapping).
Bit Descriptions
7 Fast Back to Back Enable—RO: The MCH does not generate fast back-to-bac k cycles as a m a ster
on hub interfac e B. This bi t is hardwired to 0.
6 Secondary Bus Reset—RO: MCH does not support generation of reset via this bit on the hub
interfac e B. This bi t is hardwired to 0.
5 Master Abort Mode—RO: Hardwired to 0. As a m aster on hub interface B the MCH will discard data
on writes and return all 1s during reads when a Master Abort occurs.
4 Reserved
3 VGA2 Enable (VGAEN2)—R/W: Cont rol s the routing of host ini tiated transactions targeting VGA
com patible I/ O and memory address ranges .
1 = Enable. The MCH will forward the following host accesses to the hub interface B:
• mem ory ac cesses in t he range 0A0000h–0BFFFFh
• I/O address es where A[9:0] are in the ranges 3B0h–3BBh and 3C0h–3DFh
(inclus i ve of ISA address aliases: A [15:10] are not decoded)
When enabled, f orwarding of t hese accesses i ssued by the proc essor is i ndependent of the I /O
address and memory address ranges defined by the previous l y def ined base and limit registers.
Forwarding of these accesses is als o i ndependent of the s ettings of bit 2 (IS A Enable) of t hi s
register, if thi s bit is 1.
0 = Disable (def aul t ). VGA c ompatibl e mem ory and I/O range acc esses are not forwarded to hub
interface B; rat her, they are subtractively mapped to primary PCI unless they are mapped to hub
interface B via I/ O and mem ory range regi sters def i ned above (IOBASE2, IOLI MIT2, MBASE2,
MLIMIT2, PMBASE2, PMLIMIT2)
Refer to the System Addres s Map Chapter for further information.
2 ISA Enable—R/W: This bi t modifies the response by the MCH to an I /O acces s iss ued by the
process or that target ISA I/O addresses . This appli es only to I/ O addresses t hat are enabled by the
IOBAS E and IOLIMIT regis ters.
1 = Enable. MCH will not forward to hub interface B any I/O trans actions addressing the last 768 bytes
in each 1 KB bl ock, even if the address es are within the range defi ned by t he IOBASE and IOLIMIT
registers. Ins t ead of going to hub int erface B, t hese cycles are forwarded to hub interf ace A where
they can be s ubtractivel y or positively claimed by the IS A bri dge.
0 = Disable (def aul t ). All addres ses defined by the IOBASE and IOLIMIT for processor I/O transactions
will be mapped to hub interfac e B.
1 SERR# Enable (SERRE1)—R/W: This bit enables or dis abl es forwarding of SERR messages from
hub interface B to hub int erface A, where they c an be converted into i nterrupts t hat are eventually
delivered to the processor.
1 = Enable.
0 = Disable.
106 Datasheet
Bit Descriptions
0 Parity Error Response En abl e—R/ W: Thi s bit c ont rols MCH’s res ponse to data phas e pari ty errors
on hub interface B.
1 = Address and dat a parity errors on hub interface B are report ed vi a SERR# m echanism, if enabl ed
by SERRE2 and SERREN.
0 = address and dat a pari ty errors on hub interface B are not reported via the MCH SERR# signal.
Other types of error conditions c an still be signaled via S ERR# independent of this bit’s st ate.
3.6.22. ERRCMD2—Error Command Register (Device 2)
Address Offset: 40h
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7:1 Reserved
0 SERR on Receiving Target Abort (S ERTA):
1 = MCH generates an SERR mes sage over hub interface A upon receivi ng a t arget abort on hub
interface B.
0 = MCH does not as sert an SERR mess age upon receipt of a target abort on hub interface B . SERR
mes saging for Devic e 2 i s globally enabled in the PCICMD2 regist er.
82840 MCH
R
Datasheet 107
4. System Address Map
A system based on the 82840 chipset supports 4 GB of addressable memory space and 64 KB+3 of
addressable I/O space. The I/O and memory spaces are divided by system configuration software into
regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O
regions are used solely to control the operation of devices in the system.
The Pentium II and Pentium III processor families support addressing of memory ranges larger than
4 GB. The 82840 MCH claims any access that maps neither to an expansion bus nor to system memory
(including accesses over 4 GB) by terminating the transaction without forwarding it to hub interface A,
hub interface B, or AGP. When the MCH receives a write request whose address targets an invalid space,
the data is ignored. For reads, the MCH responds by returning all 0s on the requesting interface.
4.1. Memory Address Ranges
The system memory map is broken into three categories:
• Extended M e mory Rang e ( 1 MB to 4 GB ) - The extended memory range (1 MB to 4 GB)
contains a 32 bit memory space. This memory space is used for mapping PCI, AGP, APIC,
SMRAM, and BIOS memory spaces.
• DOS Compatible Area (below 1 M B) - The DOS Compatibility Area is a DOS legacy space. It is
used for BIOS and legacy devices on the LPC interface.
Figure 3. System Address Map
DOS legacy
Address
Range
PCI Memory
Address Range
Top of Low Memory
Main Memory
Address Range
4 GB
1 MB
Hublink_B AGP Graphics
Aperture
Independently Programmable Non-
Overlapping Windows
mem_map_1
108 Datasheet
4.1.1. DOS Compatibility Area
This area is divided into the following address regions:
• 0–640 KB DOS Area
• 640–768 KB Video Buffer Area
• 768–896 KB in 16 KB sections (total of 8 sections) - Expansion Area
• 896 -960 KB in 16 KB sections (total of 4 sections) - Extended System BIOS Area
• 960 KB - 1 MB Memory (BIOS Area) - System BIOS Area
There are sixteen memory segments in the compatibility area. Thirteen of the memory ranges can be
enabled or disabled independently for both read and write cycles.
Table 7. Memory Segments and their Attributes
Memory Segments Attributes Comments
000000h–09FFFFh Fixed (Always mapped to main DRAM) 0 to 640 KB (DOS Region)
0A0000h–0BFFFFh Mapped to the hub interface or A G P
(Configurable as S MM space) Video Buf fer (physic al DRAM
configurabl e as SMM space)
0C0000h–0C3FFFh WE RE Add-on BIOS
0C4000h–0C7FFFh WE RE Add-on BIOS
0C8000h–0CBFFFh WE RE Add-on BIOS
0CC000h–0CFFFFh WE RE Add-on BIOS
0D0000h–0D3FFFh WE RE Add-on BIOS
0D4000h–0D7FFFh WE RE Add-on BIOS
0D8000h–0DBFFFh WE RE Add-on BIOS
0DC000h–0DFFFFh WE RE Add-on BIOS
0E0000h–0E3FFFh WE RE BIOS Extension
0E4000h–0E7FFFh WE RE BIOS Extension
0E8000h–0EBFFFh WE RE BIOS Extension
0EC000h–0EFFFFh WE RE BIOS Extension
0F0000h–0FFFFFh WE RE BIOS Area
DOS Area (00000h–9FFFFh)
The DOS area is 640 KB in size and is always mapped to the main memory controlled by the MCH.
Video Buffer Area (A0000h–BFFFFh)
The 128 KB graphics adapter memory region is normally mapped to a legacy video device on the
primary PCI bus (PCI_A) behind the hub interface (typically, a VGA controller). This region is also the
default region for SMM space.
82840 MCH
R
Datasheet 109
Accesses to this range can be directed to AGP b y setting the VGAEN bit in the BCTRL1 (PCI-PCI
Bridge Control) register in Device 1. In addition, accesses to this range can be directed to the hub
interface B by setting the VGAEN bit in the BCTRL2 (PCI-PCI Bridge Control) register in Device 2.
The control is applied for accesses initiated from any of the system interfaces (i.e., processor bus , hub
interface A/PCI, hub interface B, and AGP). Note that no AGP – Hub Interface accesses are supported.
The SMRAM Control register controls how SMM accesses to this space are treated.
Compatible SM RAM Address Range ( A0000h–BFFFFh)
When compatible SMM space is enabled, SMM mode processor accesses to this range are routed to
physical DRAM at this address. Non-SMM-mode processor accesses to this range are considered to be to
the Video Buffer Area as described above. Originated cycles from AGP or the hub interface to enabled
SMM space are not allowed and are considered to be to the Video Buffer Area.
Monochrome Adapter (M DA) Range (B0000h–B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system.
Since the monochrome adapter may be on the hub interface A bus, the MCH must decode cycles in the
MDA range and forward them to hub interface A. This capability is controlled by the MDAP bit in
device 0 configuration space register at offset BEh). In addition to the memory range B0000h–B7FFFh,
the MCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah, and 3BFh and forwards them to the hub
interface A bus.
ISA Expansion Area (C0000h–DFFFFh)
This 128 KB ISA Expansion region is divided into eight 16 KB segments. Each segment can be assigned
one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are
mapped through the MCH and are subtractively decoded to the ISA space. Memory that is disabled is not
remapped.
Extended System BIOS Area (E0000h–EFFFFh)
This 64 KB area is divided into four 16 KB segments. Each segment can be assigned independent read
and write attributes so it can be mapped either to main DRAM or to the hub interface. Typically, this area
is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere.
System BIOS Ar ea ( F0000h–FFFFFh)
This area is a single 64 KB segment. This segment can be assigned read and write attributes. It is by
default (after reset) Read/Write disabled and cycles are forwarded to the hub interface. By manipulating
the Read/Write attributes, the MCH can “shadow” BIOS into the main DRAM. When disabled, this
segment is not remapped.
110 Datasheet
Figure 4. Detailed DOS Compatible Area Address Map
mem_map_DOS-area
Upper, Lower,
Expansion Card BIOS
and Buffer Area
1MB
640 KB
768 KB0C0000h
0A0000h
Controlled by
PAM[6:0].
Monchrome Display
Adapter Space
Standard PCI/ISA
Video Memory
(SMM Memory)
0B8000h
0B0000h
736 KB
704 KB
Controlled by
VGA Enable and
MDA enable.
= DRAM
= Optionally DRAM
= Optionally AGP
4.1.2. Extended Memory Area
This memory area contains the main DRAM address range. It is divided into regions as shown in
Figure 5.
Figure 5. Detailed Extended Memory Range Address Map
mem_map_Extend-mem
1_0000_0000 (4GB)
FEF0_0000
FEE0_0000
FED0_0000
Top of Low Memory (TOM)
FEC0_0000
FEC8_0000
FF00_0000
100A_0000
100C_0000
00F0_0000 (15 MB)
0100_0000 (16 MB)
0010_0000 (1MB)
TEM - TSEG
Local APIC Space
Hublink_B I/O APIC
Space
Hublink_A I/O APIC
Space
High BIOS, optional
extended SMRAM
Extended SMRAM
(translated to < 1MB)
Extended SMRAM
Space
Region allowed for AGP/PCI, Aperture,
and Hublink_B windows
DRAM Region
Optional DRAM Region
Hublink_A (always)
ISA Hole
Hublink_A (always)
DRAM Region
DRAM Region
Optional DRAM Region
82840 MCH
R
Datasheet 111
ISA Hole Memory Space (0_00F0_0000 to 0_00FF_FFFF)
Thi s memor y hol e is opened through t he FDHC register (devi ce 0, offset 58h) . When i t is enabled,
accesses to this region are forward to hub interface A.
Extended SMRAM Address Range
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG (0_FFEA_0000 to 0_FFEB_FFFF)
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h–000BFFFFh. Non-SMM-
mode processor accesses to enabled HSEG are considered invalid and remapped to address 0h (byte
enables are deasserted for the writes). T he exception to this rule are Non-SMM-mode write back cycles
that are remapped to SMM space to maintain cache coherency. Originated cycle from AGP or the hub
interface to enabled SMM space are not allowed. Physical DRAM behind the HSEG transaction address
is not remapped and is not accessible.
TSEG (TOM to TO M - TSEG)
TSEG can be up to 1 MB in size and is at the top of memory. SMM-mode processor accesses to enabled
TSEG access the physical DRAM at the same address. Non-SMM-mode processor accesses to enabled
TSEG are considered invalid. The exception to this rule are Non-SMM-mode write back cycles that are
directed to the physical SMM space to maintain cache coherency. Originated cycle from AGP or the hub
interface to enabled SMM space are not allowed.
APIC Configurat i on Space ( FEC0_0000h–FECF_FFFFh,
FEE0_0000h–FEEF_FFFFh)
This range is reserved for APIC configuration space which includes the default I/O APIC configuration
space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh. The 82840 MCH
only decodes the FEC0_0000h to FECF_FFFFh range and forwards them to hub interface A or hub
interface B.
Host accesses to the Local APIC configuration space do not result in external bus activity since the Local
APIC configuration space is internal to the host. However, a MTRR must be programmed to make the
Local APIC range uncacheable (UC). The Local APIC base address in each host should be relocated to
the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64 KB
for the Local and I/O APICs.
A fixed address decode region has been allocated for I/O APIC. The FEC0_0000 to FEC7_FFFFh
address range is forwarded to hub interface A. The FEC8_0000 to FECF_FFFFh address range is
forwarded to hub interface B. If hub interface B is not enabled, the cycle is forwarded to hub interface A.
The 82840 MCH does not support I/O APIC on AGP. If an access is attempted to an IOAPIC region
from an IO agent, the hub interfaces will terminate reads with a master-abort completion status. Writes
will simply be ignored.
112 Datasheet
AGP Memory and Prefetchable Memory
Plug-and-play software configures the AGP memory window to provide enough memor y space. Accesses
whose addresses fall within this window are decoded and forwarded to AGP for completion. Note that
these registers (MBASE1, MLIMIT1, MBASE1,PMLIMIT1) must be programmed with values that
place the AGP memory space window between the value in the TOM register and 4 GB. In addition,
neither region should overlap with any other fixed or relocatable area of memory.
Hub interface B Memory and Prefetchable Memory
Plug-and-play software configures the hub interface B memory window in orde r to provide enough
memo ry space for the devices behind this PCI-to-PCI bridge. Accesses whose addresses fall within this
window are decoded and forwarded to hub interface B for completion. Note that these registers
(MBASE2, MLIMIT2, PMBASE2, PMLIMIT2) must be programmed with values that place the hub
interface B memory space window between the value in the TOM register and 4 GB. In addition, neither
region should overlap with any other fixed or relocatable area of memory.
Hub interface A Subtractive Decode
All accesses that fall between the value programmed into the TOM register and 4 GB are subtractively
decoded and forwarded to hub interface A, if they do not decode to a space that corresponds to another
device.
4.1.3. AGP Memory Address Ranges
The MCH can be programmed to direct memo ry accesses to the AGP bus interface when addresses are
within either of two ranges specified via registers in MCH Device 1 configuration space. The first range
is controlled via the Memory Base Register (MBASE1) and Memory Limit Register (MLIMIT1)
registers. T he second range is controlled via the Prefetchable Memory Base (PMB ASE1) and
Prefetchable Memory Limit (PMLIMIT1) registers.
The MCH positively decodes memory accesses to AGP memory address space as de fined by the
following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of memory claimed by the AGP device.
Note that the MCH Device 1 memory range registers described above are used to allocate memory
address space for any devices sitting on AGP bus that require such a window.
82840 MCH
R
Datasheet 113
4.1.4. AGP DRAM Graphics Aperture
Memory-mapped, graphics data structures can reside in a Graphics Aperture to mai n D RAM me mory.
This aperture is an address range defined by the APBASE and APSIZE configuration registers of the
MCH device 0. The APBASE register follows the standard base address register template as defined by
the PCI 2.1 specificatio n. The size of the range claimed by the APBASE is programmed via “back-end”
register APSIZE (programmed by the chip-set specific BIOS before plug-and-play session is performed).
APSIZE allows BIOS to pre-configure the aperture size to be either 4 MB, 8 MB,16 MB, 32 MB,
64 MB, 128 MB or 256 MB. By programming APSIZE to specific size, the corresponding lower bits of
APBASE are forced to “0” (behave as hardwired). T he APSIZE default value forces an aperture size of
256 MB. The aperture address range is naturally aligned.
Accesses within the aperture range are forwarded to the main DRAM subsystem. The MCH translates the
originally issued add r esses via a translation table maintained in main memory. The aperture range should
be programmed as non-cacheable in the processor caches.
Note: Plug-and-play software configuration model does not allow overlap of different address ranges.
Therefore, the AGP Graphics Aperture and AGP Memory Address Range are independent address
ranges that may be adjacent, but cannot overlap one another.
4.1.5. System Management M ode (SMM) M emory Range
The MCH supports the use of main memory as System Management RAM (SMRAM) enabling the use
of System Management Mode. The MCH supports two SMRAM options: Compatible SMRAM
(C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM (SMRAM) space
provides a memory area that is available for the SMI handlers and code and data storage. This memory
resource is normally hidden from the system operating system so that the processor has immediate access
to this memory space upon entry to SMM. The MCH provides three SMRAM options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM.
• Optional larger write-back cacheable T_SEG area from 128 KB to 1 MB in size above 1 MB that is
reserved from the highest area in system DRAM memory. The above 1 MB solutions require
changes to compatible SMRAM handlers code to properly execute above 1 MB.
Note: Masters from the hub interface and AGP are not allowed to access the SMM space.
114 Datasheet
4.1.5.1. SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed SMM
space is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM
space is defined as the range of physical DRAM memory locations containing the SMM code. SMM
space can be accessed at one of three transaction address ranges: Compatible, High and TSEG. The
Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and DRAM SMM
space is a different address range. Note that the High DRAM space is the same as the Compatible
Transaction Address space. Therefore the table below describes three unique address ranges:
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
These abbreviations are used later in the table describing SMM Space Tr ansaction Handling.
SMM Space E nabled Transaction Address Space (Adr) DRAM Space (DRAM )
Compatible (C) A 0000h–B FFFFh A0000h–BFFFFh
High (H) 0FFEA0000h–0FFEBFFFFh A0000h–BFFFFh
TSEG (T) (TOM - TSEG_SZ) to TOM (TOM-TSEG_SZ) to TOM
Note: High SMM is different than in previous chipsets. In previous chipsets the High segment was the 384 KB
region from A0000h–FFFFFh. However, C0000h–FFFFFh is removed in the MCH.
Note: TSEG SMM is different than in previous chipsets. In previous chipsets the TSEG address space was
offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just under the TOM. In
the MCH the TSEG region is not offset by 256 MB and it is not remapped.
4.1.5.2. SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and may
cause the system to hang up:
• The Compatible SMM space must not be setup as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to system
DRAM, the AGP aperture range, or to any “PCI” devices (including hub interface and AGP
devices). This is a BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must n ot be reported to the operating system
as available DRAM. This is a BIOS responsibility.
• Any addre ss transla ted through the AGP Aperture G TLB must not target DRAM from
000A0000h–000FFFFFh.
82840 MCH
R
Datasheet 115
4.1.6. Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into MCH
DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out of main DRAM.
ROM is used as a read-only during the copy process while DRAM at the same time is designated write-
only. After copying, the DRAM is designated read-only so that ROM is shadowed. Host bus transactions
are routed accordingly.
4.1.7. I/O Address Space
The 82840 MCH does not support the existence of any other I/O devices besides itself on the processor
bus. The MCH generates either hub interface A/PCI, hub interface B, or AGP bus cycles for all
processor I/O accesses. The MCH contains two internal registers in the processor I/O space—
Configur ation Address Register (CONF_ADDR) and Configuratio n Data Re gi ster (C ONF_DATA).
These locations are used to implement configuration space access mechanism as described in the
Configuration Register Chapter.
The processor allows 64K+3 bytes to be addressed within the I/O space. The MCH propagates the
processor I/O ad dress without any translation on to the destination bus and therefore, provides
addressability for 64K+3 byte locations. Note that the upper 3 locations can be accessed only during I/O
address wrap-around when processor bus A16# address signal is asserted. A16# is asserted on the
processor bus when an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16#
is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to either
the hub interface A/PCI bus or to hub interface B unless they fall within the AGP I/O address range as
defined by the mechanisms explained b elow. The MCH will not post I/O write cycles to IDE.
The MCH never responds to I/O cycles initiated on AGP or either Hub interface.
4.1.7.1. AGP I/O Address Mapping
The MCH can be programmed to direct non-memory (I/O) accesses to the AGP bus interface or to the
hub interface B when processor-initiated I/O cycle addresses are within the AGP I/O address range or the
hub interface B I/O address range. The AGP I/O range and the hub interface B I/O range are controlled
via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in MCH Device 1 and
Device 2 configuration space, respectively.
The MCH positively decodes I/O accesses to AGP and hub interface B I/O address spaces as d e fined by
the following equations:
AGP I/O
Device 1 I/O_Base_Address ≤ CPU I/O Cycle Address ≤ Device 1 I/O_Limit_Address
Hub interface B I/O
Device 2 I/O_Base_Address ≤ CPU I/O Cycle Address ≤ Device 2 I/O_Limit_Address
The effective sizes of the ranges are programmed by the plug-and-play configuration software and
depend on the size of I/O space claimed by the AGP and hub interface B devices.
116 Datasheet
4.1.8. MCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the four interfaces (i.e.,
Host bus, the hub interface A, hub interface B or AGP).
4.1.8.1. The Hub interface A Decode Rules
The MCH accepts accesses from the hub interface A to the following address ranges:
• All memory read and write accesses to Main DRAM (except SMM space).
• All memory write accesses from the hub interface A to AGP memory range defined by MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1.
• All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
• Memory writes to VGA range on AGP, if enabled.
All memory reads from the hub interface A that are targeted > 4 GB memory range will be terminated
with Master Abort completion, and all memory writes (>4 GB) from the hub interface A will b e ignored.
4.1.8.2. The Hub interface B Decode Rules
The MCH accepts accesses from hub interface B to the following address ranges:
• All memory read and write accesses to Main DRAM (except SMM space).
• All memory write accesses from the hub interface to AGP memory range defined by MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1.
• All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
• Memory writes to VGA range on AGP, if enabled.
Memory accesses from the hub interface B that fall elsewhere within the memory range and I/O cycles
will not be accepted. They are terminated with Master Abort completion.
82840 MCH
R
Datasheet 117
4.1.8.3. AGP Interface Decode Rules
Cycles Initiate d Usi ng AGP FRAM E# Prot ocol
The MCH does not support any AGP FRAME# access targeting hub interface A. The MCH claims AGP-
initiated memory read/write transactions decoded to the main DRAM range or the Graphics Aperture
range. All other memory read/write requests will be master-aborted by the AGP initiator as a
consequence of the MCH not responding to a transaction.
Under certain conditions, the MCH restricts access to the DOS Compatibility ranges governed by the
PAM registers b y distinguishing access type and d estination bus. The MCH does NOT accept AGP
FRAME# write transactions to the compatibility ranges if the PAM designates DRAM as writable. If
accesses to a range are not write enabled by the PAM, the MCH does not respond and the cycle results in
a master-abort. The MCH accepts AGP FRAME# read transactions to the compatibility ranges if the
PAM designates DRAM as readable. If accesses to a range are not read enabled by the PAM, the MCH
does not respond and the cycle results in a master-abort.
If an agent on AGP issues an I/O, PCI Configuration, or PCI Special Cycle transaction, the MCH will not
respond and cycle results in a master-abort.
Cycles Initiate d Usi ng AGP PIPE# or SB Protocol
All cycles must reference main memory, main DRAM address range (including PAM), or Graphics
Aperture range (also physically mapped within DRAM but using different address range). AGP accesses
to SMM space are not allowed. AGP-initiated cycles that target DRAM are not snooped on the host bus,
even if they fall outside of the AGP aperture range.
If a cycle is outside of main memory range, the cycle terminates as follows:
• Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error bit in
ERRSTS register in device 0
• Writes: Te rminated internally without affecting any buffers or main memory
AGP Accesses to MCH t hat Cross Device Boundaries
For AGP FRAME# accesses, when an AGP master gets disconnected, it will resume at the new address;
this allows the cycle to be routed to or claimed by the new target. Therefore, accesses should be
disconnected by the target on potential device boundaries. The MCH disconnects AGP FRAME#
transactions on 4 KB boundaries.
AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. Read accesses crossing a
device boundary returns invalid data when the access crosses out of DRAM. Write accesses crossing out
of DRAM are discarded. The IAAF Error bit is set.
118 Datasheet
4.1.8.4. Legacy VGA Ranges
The legacy VGA memory range A0000h–BFFFFh is mapped either to hub interface A, hub interface B,
or AGP. This behavior is configured by the pro gramming of the VGA Enable bits in the BCTRL
configuration registers in MCH Device 1 and Device 2 configuration spaces, as well as the MDAP bit in
the MCHCONF configuration register in Device 0 configuration space. The same registers control
mapping of VGA I/O address ranges. VGA I/O range is defined as addresses where A[9:0] are in the
ranges 3B0h–3BBh and 3C0h–3DFh (inclusive of ISA address aliases: A[15:10] are not decoded). The
function and interaction of these three bits is described b elow:
VGA Enable: Controls the routing of processor-initiated transactions targeting VGA compatible I/O and
memo ry address ranges. When one of these bits is set , the MCH forwards the following processor
accesses (VGA references) to either AGP or hub interface B:
• memo ry accesses in the range 0A0000h to 0BFFFFh
• I/O addresses where A[9:0] are in the ranges 3B0h–3BBh and 3C0h–3DFh
(inclusive of ISA address aliases - A[15:10] are not decoded)
MDA references are defined as the following:
• Memory: 0B0000h–0B7FFFh
• I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
MDA-only references are defined as the following:
• I/O 3BFh and its aliases.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN1
(Device 1) VGAEN2
(Device 2) MDAP Behavior
0 0 0 All ref erences to MDA and V GA go to hub interf ace A
0 0 1 Ill egal combination: Do Not Use
0 1 0 All ref erences to V GA go to hub interface B. Addresses 3B4h, 3B5h,
3B8h, 3B9h, 3BAh and thei r ai l ases are both MDA and VG A
references , and they go to hub interface B . MDA-only references go to
hub interface A.
0 1 1 VGA ref erences go to hub i nterface B . MDA-onl y references go t o hub
interface A
1 0 0 All ref erences to V GA go to AGP A ddresses 3B 4h, 3B5h, 3B8h,
3B9h, 3BA h and their ailas es are both MDA and VGA references, and
they go to AG P . MDA-only references go to hub int erface B
1 0 1 VGA ref erences go to A G P . MDA-only references go to hub interface
A
1 1 0 Ill egal combination: Do Not Use
1 1 1 Ill egal combination: Do Not Use
82840 MCH
R
Datasheet 119
5. Functional Description
5.1. Host Interface
The 82840 MCH is optimized to support the Pentium II processor or Pentium III pro cessor with the
bus clock frequencies of 133 MHz or 100 MHz. The MCH supports up to two processors at FSB
frequencies of 100/133 MHz using AGTL+ signaling. Note that one of the two processors’ agent ID
needs to be assigned as “ID# 0” in the system. It supports either 32- or 36-bit host addresses, allowing
the processor to access the entire 4 GB of the MCH’s memory address space. The MCH has an 8-deep
In-Order Queue to support up to eight outstanding pipelined address requests on the host bus. Host-
initiated I/O cycles are positively decoded to AGP/P CI, hub interface B, or MCH configuration space
and subtractively decode d to hub interface A. Host initiated memory cycles are positively decoded to
AGP/PCI, hub interface B, or DRAM and are again subtractively decoded to hub interface A. AGP
semantic memory accesses initiated from AGP to DRAM are not snooped on the host bus. Memory
accesses initiated from AGP using PCI semantics and from either hub interfaces to DRAM will be
snooped on the host bus. Memo ry accesses whose addresses lie within the AGP aperture are translated
using the AGP address translation table, regardless of the originating interface.
The MCH recognizes and supports a large subset of the transaction types that are defined for the
Pentium II processor bus interface. However, each of these transaction types has a multitude of
response types, some of which are not supported by the MCH. All transactions are processed in the order
that they are received on the host bus. A summary of transactions supported by the MCH is given in the
following table.
Table 8. P6 Bus Transactions Supported by the MCH
Transaction REQa[4:0]# REQb[4:0]# MCH Support
Deferred Reply 0 0 0 0 0 X X X X X The MCH initi ates a deferred repl y f or a
previously deferred transact i on.
Reserved 0 0 0 0 1 X X X X X Reserved
Interrupt Acknowledge 0 1 0 0 0 0 0 0 0 0 Interrupt ack nowledge cyc l es are forwarded to
the hub interf ace A or hub interface B A single
byte of data i s returned on HD[7:0]#.
Special Transactions 0 1 0 0 0 0 0 0 0 1 See s eparate table in Special Cycl es sect i on.
Reserved 0 1 0 0 0 0 0 0 1 x Reserved
Reserved 0 1 0 0 0 0 0 1 x x Res erved
Branch Trace Mes sage 0 1 0 0 1 0 0 0 0 0 The MCH terminat es a branch trac e mess age
without latc hi ng data.
Reserved 0 1 0 0 1 0 0 0 0 1 Reserved
Reserved 0 1 0 0 1 0 0 0 1 x Reserved
Reserved 0 1 0 0 1 0 0 1 x x Res erved
120 Datasheet
Transaction REQa[4:0]# REQb[4:0]# MCH Support
I/O Read 1 0 0 0 0 0 0 x LEN# I/ O read cycles are forwarded to the hub
interfac e A, hub interf ace B, or A GP . I/O c yc l es
to the MCH configuration space will not be
forwarded to AGP or t he hub i nterfaces .
I/O Wri t e 1 0 0 0 1 0 0 x LEN# I /O write cycles are forwarded to the hub
interfac e A, hub interf ace B or AGP . I/O c yc l es
to the MCH conf i guration space are not
forwarded to AGP or t he hub i nterface.
Reserved 1 1 0 0 x 0 0 x x x Reserved
Memory Read and
Invalidate 0 0 0 1 0 0 0 x LEN# Hos t-initiated memory read and invalidate
cycles are forwarded to DRAM. The MCH
initiat es an MRI (LEN=0) cycl e to snoop a hub
interface A, hub int erface B or A GP initiated
write cycle to DRAM.
Reserved 0 0 0 1 1 0 0 x LEN# Reserved
Memory Code Read 0 0 1 0 0 0 0 x LEN# Memory code read cycles are forwarded to
DRAM, hub interface A, hub i nterface B or
AGP.
Memory Data Read 0 0 1 1 0 0 0 x LEN# Host-Ini t i ated memory read cyc l es are
forwarded to DRAM, the hub in t erface A, hub
interface B or AGP. The MCH initiates a
memory read cycl e to snoop a hub interface A,
hub interface B or AGP i ni tiated read cyc l e to
DRAM.
Memory Write (no retry) 0 0 1 0 1 0 0 x LEN# This memory write is a writebac k cycle and
cannot be retri ed. The MCH forwards the write
to DRAM.
Memory Write (can be
retried) 0 0 1 1 1 0 0 x LEN# The st andard mem ory write cycle is forwarded
to DRAM, hub interface A , hub i nterface B , or
AGP.
NOTES:
1. For Memory cycles, REQa[4:3]# = ASZ#.
2. REQb[4:3]# = DSZ#. For the P entium® P ro processor, DSZ# = 00 (64 bit data bus size).
3. LEN# = data transfer length as follows:
LEN# Data length
00 <= 8 bytes (BE[ 7: 0]# speci fy granularity)
01 Length = 16 bytes BE[7:0]# all active
10 Length = 32 bytes BE[7:0]# all active
11 Reserved
82840 MCH
R
Datasheet 121
Table 9. Types of Responses Supported by the MCH
RS2# RS1# RS0# Description MCH Support
0 0 0 Idle
0 0 1 Retry
Response This response is generat ed i f an acces s is to a resource
that c annot be accessed by the proces sor at this time and
the logic must avoi d deadl ock. I CH di rected reads and
writes, DRAM locked reads, AGP reads and writes can be
retried.
0 1 0 Deferred
Response This response can be ret urned for all trans actions that can
be executed ‘out of order.’ Host Memory Reads I/O Reads,
Interrupt Acknowledge and I/O Writes c yc l es to the hub
interface A, hub int erface B and AG P can be deferred.
0 1 1 Reserved Reserved
1 0 0 Hard Failure Not supported.
1 0 1 No Data
Response This i s for trans actions where the dat a has already been
transferred or for transac tions where no data is transferred.
Writes and zero l ength reads recei ve t hi s response.
1 1 0 Implicit
Writeback This res ponse is given f or t hose transactions where the
initial t ransactions snoop hit s on a modified cache l i ne.
1 1 1 Normal Data
Response This response is f or transact i ons where data accompanies
the respons e phase. Reads rec ei ve t hi s response.
Host Addresses Above 4 GB
Host memory writes to address space above 4 GB are discarded without affecting the system state. Host
memo ry reads to address space above 4 GB are immediately terminated and return with a fixed value.
Host Bus Cycles
The following transaction descriptions illustrate the various operations in their most straightforward
representation.
Partial Reads
Partial Read transactions include I/O reads and memory read operations of less than or equal to eight
bytes ( four consecutive bytes for I/O) within an aligned 8 byte span. The byte enable signals, BE[7 :0 ]#,
select which bytes in the span to read.
Part-Line Read and Wri t e Transacti ons
The MCH does not support partial-line (i.e., 16-byte) transactions.
Cache Line Reads
A read of a full cache line (as indicated by the LEN[1:0]=10 during request phase) requires 32 bytes of
data to be transferred. This translates into four data transfer cycles for a given request. Since the MCH is
the only response agent in the system, it is always selected as the target and will determine whether the
address is directed to DRAM, the hub interface A, the hub interface B, or AGP and provide the
corresponding command and control to comp lete the transaction.
122 Datasheet
Partial Writes
Partial Write transactions include: I/O and memory wr ite o perations of eight bytes or less (maximum of
four bytes for I/O) within an aligned 8 byte span. The byte enable signals, BE[7:0]#, select which bytes
in the span to write. I/O writes crossing a 4 byte boundary are broken into two separate transactions by
the processor.
Cache Line Writes
A write of a full cache line requires 32 bytes of data to be transferred; this translates into four data
transfer cycles for a given request.
Memory-Read-and-Invalidate (length > 0)
A Memory-Read-and-Invalidate (MRI) transaction is functionally equivalent to a cache line read. The
purpose of having this special transaction is to support write allocation (write miss case) of cache lines in
the processors. When a processor issues an MRI, the cache line is read as in a normal cache line read
operation; however, all other caching agents must invalidate this line if they have it in a shared or
exclusive state. If a caching agent has this line in the Modified State, it must be written back to memory
and invalidated and it is . The MCH captures the write-back data. It is illegal for a bus agent to assert
HIT# o n this transaction.
Memory-Read-and-Invalidate (length = 0)
A Memory Read and Invalidate transaction of length zero (MRI0) does not have an associated Data
Response. Executing the transaction informs other agents in the system that the agent issuing this request
requires exclusive ownership of a cache line that maybe in the Shared State (write hit to a shared line).
Agents with this cache line invalidate the line. If this line is in the modified state, an implicit write-back
cycle is generated and the MCH captures the data.
Memory Read (length = 0)
A Memory Read of length zero, MR(0) does not have an associated Data Response. This transaction is
used by the MCH to snoop for the hub interface to DRAM and AGP FRAME# snoopable DRAM read
accesses. The MCH snoop request policy is identical for the hub interface and AGP FRAME# memory
read transactions. Note that the MCH will do multiple snoop ahead cycles for a hub interface burst reads
greater than 32 bytes and for AGP FRAME# master burst read (i.e., memory read multiple) to DRAM.
The MCH performs single MR(0) cycles for the hub interface reads less than or equal to 32 bytes and for
AGP FRAME# master standard read or read line directed to DRAM.
The MCH generates length=0 Memory Read cycles for the hub interface and AGP FRAME# memory
read cycles to DRAM.
Cache Coherency Cycl es
The MCH generates an implicit writeback response during host bus read and wr ite transactions when a
processor asserts HITM# during the snoop phase. The host-initiated write case can have two data
transfers, the requesting agents data followed by the snooping agents writeback data.
The MCH performs a memory read and invalidate cycle of length 0 (MRI[0]) on the host bus when a hub
interface or AGP FRAME# snoopable DRAM read or write cycle occurs.
82840 MCH
R
Datasheet 123
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259-
compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction,
except that the address bus does not contain a valid address.
Interrupt Acknowledge cycles are always directed to the hub interface A (never to AGP).
Locked Cycles
The MCH supports resource locking due to the assertion of the LOCK# line on the host bus as follows:
• Host<->DRAM Locked Cycles. The MCH supports host to DRAM locked cycles. The P6 bus
protoco l ensures that the host bus will execute any other transactions until the locked cycle is
complete. The MCH arbiter may grant another hub interface A, hub interface B, or AGP device;
however, any cycles to DRAM requiring cache coherency will b e b lo cked.
• Host<-> ICH Locked Cycles. Any host to the ICH locked transaction will initiate a locked sequence
to the hub interface A. The P6 bus implements a bus lock mechanism that ensures that no change of
bus ownership can occur from the time one agent has established a locked transaction (i.e., the
initial read cycle of a locked transaction has completed) until the locked transaction is completed.
Note that for host transactions to hub interface A, a “LOCK” special cycle is issued to establish the
lock prior to the initial read and a “UNLOCK” special cycle is issued to the hub interface A after the
host lock transaction is completed.
Any concurrent cycle that requires snooping on the host bus is not processed while a LOCK
transaction is occurring on the host bus.
Locked cycles from hub interface A to DRAM are not supported.
• Host<->AGP Locked Cycles. Any Host-AGP lock cycle result in a un-predictable system behavior.
• Host<->P64H Locked Cycles. The MCH does not support a Master Abort on the second read of a
split lock from the host.
Branch Trace Cycles
An agent issues a Branch Tr ace Cycle for taken branches if execution tracing is enabled. Address
Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear address of the
instruction causing the branch and D[31:0]# carries the target linear address. The MCH responds and
retires this transaction but does not latch the value on the data lines or provide any additional support for
this type o f cycle.
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. In the first address phase
Aa[35:3]# is undefined and can be driven to any value. In the second address phase, Ab[15:8]# defines
the type of Special Cycle issued by the processor. All Host initiated Special Cycles are routed to the hub
interface A.
A special Cycle is “posted” into the MCH and the FSB transaction is terminated immediately after the
cycle has been broadcast. It does not wait for the cycle to propagate or terminate on the hub interface
interface.
124 Datasheet
Table 1 0 specifies the cycle type and definition as well as the action taken by the MCH when a special
cycle is identified. Note that none of the host bus special cycles are propagated to either the AGP
interface or the hub interface B.
Table 10. Types of S pecial Cycles Supported by the MCH
BE[7:0]# Special Cycle Type Action Taken
0000 0000 NOP This transact i on has no side-eff ects.
0000 0001 Shutdown This transaction i s iss ued when an agent detects a s evere
soft ware error that prevents furt her processi ng. Thi s cycle i s
claimed by the MCH and propogated as a Shutdown special
cycle over t he hub i nterface A . Thi s cycle i s retired on the host
bus after the associated special cyc l e request is successfull y
broadcast over the hub interface.
0000 0010 Flush This trans action is i ssued when an agent has invali dated its
internal c aches without writing bac k any modi f i ed l i nes. The
MCH claim s this cycle and si mply reti res it.
0000 0011 Hal t This transact ion i s iss ued when an agent executes a HLT
instruction and st ops program executi on. This cycle is c l ai med
by the MCH and propagated over the hub interface A as a Halt
special cycle. This cycle i s retired on the host bus af t er the
assoc i ated speci al cycle request i s successf ul l y broadcast over
the hub interf ace.
0000 0100 Sync This t ransaction i s iss ued when an agent has written back all
modified lines and has invalidated i ts internal caches. The MCH
claims thi s cycle and simpl y retires it .
0000 0101 Fl ush Ack nowledge This transac tion is issued when an agent has completed a
cache s ync and flush operat i on i n response to an earl i er
FLUSH# signal assertion. The MCH claim s this cycle and reti res
it.
0000 0110 Stop Grant Acknowledge This transact i on is iss ued when an agent enters Stop Grant
mode. Thi s cycle i s claimed by the MCH and propagated over
the hub interf ace A as a Stop Grant spec i al cycle. Thi s cycle is
retired on the hos t bus aft er the assoc i ated speci al cycle request
is successfully broadc ast over the hub interface.
0000 0111 SMI A cknowledge This t ransaction i s firs t i ssued when an agent enters the System
Management Mode (SMM). Ab[ 7 ] # i s also s et at this entry point.
All s ubsequent transactions from t he host with Ab[7]# set are
treated by the MCH as accesses to t he S MM space. No
corresponding cycle is propagated to the hub int erface. To exit
the Syst em Management Mode the host issues anot her one of
these c yc l es with the Ab[7]# bit deasserted. The SMM spac e
acces s is c l osed by the MCH at thi s point.
all others Reserved
82840 MCH
R
Datasheet 125
5.1.1. Frame Buffer Memory Support
To allow for high speed write capability for graphics, the Pentium II processor introduced WC (Write-
combined memory type). USWC is uncacheable, speculative, write-combining. The USWC memory type
provides a write -combining buffer ing mechanism for write o peratio ns. A high percent age of graphi cs
transactions are writes to the memory-mapped graphics region, normally known as the linear frame
buffer. Reads and writes to USWC are non-cached and are not allowed to have side effects.
In the case of graphics, current 32-bit drivers (without modifications) would use a Partial W r ite p r otocol
to update the frame buffer. The highest performance write transaction on the host bus is the Line Write.
By combining several back-to-back Pa rtial write transactions (internal to the pro cesso r) into a Line write
transaction on the processor bus, the performance of frame buffer accesses would be greatly improved.
Writes to USWC memory can be buffered and combined in the processor's write-combining buffers
(WCB). The WCB is flushed after executing a serializing, locked, I/O instruction, or the WCB is full (32
bytes). To extend this capability to the current drivers, it is necessary to set up the linear frame buffer
address range to be USWC memory type. T his can be done by programming the MTRR registers in the
processor.
Note that the application of USWC memory attribute is not limited only to the frame buffer support and
that the MCH implements write combining for any host to the hub interface or host to AGP posted write.
5.2. AGP Interface
The MCH support 3.3V AGP 1x/2x, and 1.5V AGP 1x/2x/4x devices. T o support these modes of
operation, the AGP signal buffers are designed with two modes of operation:
• 3.3V drive/receive (not 5 volt tolerant)
• 1.5V drive/receive (not 3.3 volt tolerant).
The MCH supports 2x/4x clocking transfers for read and write data, and for sideband addressing. It will
also support 2x and 4x clocking for Fast Writes initiated from the MCH (on behalf of the processor).
AGP PIPE# or SBA[7:0] transactions to DRAM are not snooped and are, therefore, not coherent with the
processor caches. AGP FRAME# transactions to DRAM are snooped. AGP PIPE# and SBA[7:0]
accesses to and from the hub interface A or hub interface B are not supported. AGP FRAME# access
from an AGP master to the hub interface are also not supported. Only the AGP FRAME memory writes
from the hub interface are supported.
5.2.1. AGP Target Operations
As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH supports
AGP cycles targeting interface to main memory only. The MCH supports interleaved AGP PIPE# and
AGP FRAME#, or AGP SBA[7 :0] an d AGP FRAME# t ran sactions.
126 Datasheet
Table 11. AGP Commands Supported by the MCH When Acting as an AGP Target
MCH Host Bridge AGP Com mand C/BE[3:0]#
Encoding Cycle Destination Response as PCIx Target
Read 0000 Main Mem o ry Low Priority Read
0000 The Hub interface Complete with random data
Hi-Priority Read 0001 Main Memory High Priori t y Read
0000 The Hub interface Complete with random data
Reserved 0010 N/A No Response
Reserved 0011 N/A No Response
Write 0100 Main Memory Low Priority Write
0100 The Hub interface Cycl e goes to DRAM with BE s inacti ve
Hi-Priority Write 0101 Main Memory Hi gh Priority Write
0101 The Hub interface Cyc l e goes to DRAM with BEs inact i ve -
does not go to t he hub i nterface
Reserved 0110 N/A No Response
Reserved 0111 N/A No Response
Long Read 1000 Main Mem o ry Low Priority Read
The Hub i nterface Complete loc al l y with random data - does
not go to the hub i nterface
Hi-Priority Long Read 1001 Main Memory High Priority Read
The Hub i nterface Complete with random data
Flush 1010 MCH Complete with QW of Random Dat a
Reserved 1011 N/A No Response
Fence 1100 MCH No Respons e - Fl ag i nserted in MCH
request queue
Reserved 1101 N/A No Response
Reserved 1110 N/A No Response
Reserved 1111 N/A No Response
NOTES: N/ A refers t o a function that is not applicable
As a target of an AGP cycle, the MCH supports all the transactions that directly forward main memo ry
and these are summarized in the table above. T he MCH supports both normal and high priority read and
write requests. The MCH does not support AGP cycles to either hub interfaces. PIPE# and SBA cycles
do not require coherency management and all AGP initiator accesses to main memory using AGP PIPE #
or SBA protocol are treated as non-snoopable cycles. These accesses are directed either to the AGP
aperture in main memory or to the un-translated main memory outside of the graphics aperture The
memory space covered by the aperture should be programmed as either uncacheable (UC) memory or
write combining (WC) in the Intel® Pentium® Pro processor’s MTRRs.
82840 MCH
R
Datasheet 127
5.2.2. AGP Transaction Ordering
The MCH observes transaction ordering rules as defined by the AGP Interface S p ecification,
Revision 2.0.
5.2.3. AGP Electricals
The 4x data transfers use 1.5V signaling levels as described in the AGP 2.0 Specification. The MCH
supports 1x/2x data transfers using either the 3.3V or 1.5V signaling levels. The mechanism to select the
data transfer mode is orthogonal to the mechanism to select the signaling level. The following table
shows the data rates and signaling levels supported by the MCH.
Signaling Level Data Rate
1.5V 3.3V
1x AGP* yes Yes
2x AGP Yes Yes
4x AGP Yes No
* Note that AGP FRAME# data rate and signaling level is the same as 1x AGP.
5.2.4. The Differences Between AGP FRAM E# and PCI-66 Devices
• MCH supports only one AGP FRAME# device.
• The AGP FRAME# device must meet the AGP 2.0 electrical specification.
• LOCK# signal is not present for AGP FRAME#. Neither inbound or outbound locks are supported.
• SERR# signal is present for AGP FRAME#.
• PERR# signal is not present for AGP FRAME#.
• 16 clock Subsequent Data Latency timer (instead of 8) for AGP FRAME# devices.
Note PCI-66 devices are not supported on the AGP interface unless they comply with the AGP 2.0
Specification.
5.2.5. 4x AGP Protocol
In addition to the 1x and 2x AGP protocol, the MCH supports 4x AGP read and write data transfers, and
4x sideband address generation. The 4x operation is compliant with AGP 2.0 specification.
The MCH indicates that it supports 4x data transfers through RATE[2] (bi t 2) of the AGP Stat us
Register. When DATA_RATE[2] (bit 2) of the AGP Command Register is 1 during system initialization,
the MCH performs AGP read and write data transactions using 4x protocol. This bit is not dynamic.
Once this bit is set during initialization, the data transfer rate may not change.
The 4x data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4x data
transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred on every
66 MHz clock edge. The minimum throttleable block size remains four 66 MHz clocks which means
64 bytes of data is transferred per block. Three additional signal pins are required to implement the 4x
data transfer protocol. T hese signal pins are complimentary data transfer strobes for the AD bus (2) and
the SBA bus (1).
128 Datasheet
5.2.6. Fast Writes
The MCH supports 2x and 4x Fast Writes from the MCH to the graphics controller on AGP. Fast Write
operation is compliant with Fast Writes as currently described in AGP 2.0.
The MCH indicates that it supports Fast Writes through bit 4 (F W) of t he AGP Stat us Register. When
FW_ENABLE (bit 4 ) of the AGP Command Register is 1, the MCH uses Fast Write protocol to transfer
memory write data to the AGP master. Memory writes originating from the host(s) or from the hub
interface use the Fast Write protocol, when it is enabled. The data rate used to perform the Fast Writes is
dependent on which bit is set in DATA_RATE[2:0] (bits 2:0) of the AGP Command Register. If
DATA_RATE[2]=1, the data transfers occur using 4x strobing. If DATA_RATE[1]=1, the data transfers
occur using 2x strobing. If DATA_RATE[0] =1, Fast Writes are disabled and occur using standard PCI
protoco l. No te that only one of the three DATA_RATE bits may be set by initialization software. This is
summarized in the following table.
Table 12. Fast Write Register Programming
FW_ENABLE DATA_RATE[2] DATA_RATE[1] DATA_RATE[0] MCH =>AGP Master
Write Protocol
0 x x x 1x
1 0 0 1 1x
1 0 1 0 2x Strobing
1 1 0 0 4x Strobing
5.2.7. AGP Universal Connector
The MCH supports the AGP Universal Connector that allows either a 1.5V or a 3.3V AGP add-in card to
be supported by the system.
5.2.8. AGP FRAME# Transactions on AGP
The MCH accepts and generates AGP FRAME# transactions on the AGP bus. The MCH guarantees that
AGP FRAME# accesses to DRAM are kept coherent with the processor caches by generating snoops to
the host bus. LOCK#, SERR#, and PERR# signals are not supported.
82840 MCH
R
Datasheet 129
5.2.8.1. MCH Initiator and Target Operations
Table 13 summarizes MCH target operation for AGP FRAME# initiators. These cycles target only to
main memory.
Table 13. PCI Commands Supported by the MCH When Acting as A FRAME# Target
MCH PCI Command C/BE [3:0]#
Encoding Cycle Desti n ati on Response as A FRAM E#
Target
Interrupt Acknowledge 0000 N/A No Response
Special Cycle 0001 N/A No Response
I/O Read 0010 N/A No Response
I/O Write 0011 N/A No Response
Reserved 0100 N/A No Response
Reserved 0101 N/A No Response
Memory Read 0110 Main Memory Read
0110 The Hub i nterface No Response
Memory Wri te 0111 Main Memory Post s Data
0111 The Hub i nterface No Response
Reserved 1000 N/A No Response
Reserved 1001 N/A No Response
Configurati on Read 1010 N/A No Response
Configurati on Write 1011 N/A No Response
Memory Read Multi pl e 1100 Main Memory Read
1100 The Hub int erf ace A/B No Respons e
Dual Address Cycle 1101 N/A No Response
Memory Read Line 1110 Main Memory Read
1110 The Hub int erf ace A/B No Respons e
Memory Write and Invalidate 1111 Main Memory Post s Data
1111 The Hub int erf ace A/B Posts Data
NOTES: N/ A refers t o a function that is not applicable
130 Datasheet
MCH as Target of AGP FRAME# Cycle (Supported Transactions)
• Memory Read, Memory Read Line, and Memory Read Multiple. These commands are
supported identically by the MCH. The MCH does not support reads of the hub interface bus from
AGP.
• Memory Write and Memory Write and Invalidate. These commands are aliased and processed
identically.
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not supported by
MCH as a target and result in master abort.
• Exclusive Access. The MCH does not support PCI locked cycles as a target.
• Fast Back-to-Back Transactions. The MCH, as a target, supports fast back-to-back cycles from an
AGP FRAME# initiator.
MCH as Init iator of AGP FRAME# Cycle (Supported Transactions)
• Memory Read and Memory Read Line. The MCH supports reads from host to AGP. The MCH
does not support reads from either hub interfaces to AGP.
• Memory Read Multiple. T his command is not supported by the MCH as an AGP FRAME#
initiator.
• Memory Write. The MCH initiates AGP FRAME# cycles on behalf of the host or the hub
interface. The MCH does not issue Memory Write and Invalidate as an initiator. MCH does not
support write merging or write collapsing. The MCH allows non-snoopable write transactions from
the hub interface to the AGP bus.
• I/O Read and Write. I/O read and write from the host are sent to the AGP bus. I/O base and limit
address r ange for AGP bus a re programmed in AGP FRAME# configurat i on regi sters. All other
accesses that do not correspond to this programmed address range are forwarded to the hub
interface A.
• Exclusive Access. The MCH will not issue a locked cycle on the AGP b us on behalf of either the
host or the hub interface. The hub interface and host locked transactions to AGP are initiated as
unlocked transactions by the MCH on the AGP bus.
• Configurat ion Read and Write. Host Configuration cycles to AGP are forwarded as Type 1
Configur ation Cycles.
• Fast Back-to-Back Transactions. The MCH, as an initiator, does not perform fast back-to-back
cycles.
82840 MCH
R
Datasheet 131
5.2.8.2. MCH Retry/Disconnect Conditions
The MCH generates retry/disconnect according to the AGP Specification rules when being accessed as a
target from the AGP FRAME# device.
5.2.8.3. Delayed Transaction
When a AGP FRAME#-to-DRAM read cycle is retried by the MCH, the cycle is processed internally as
a Delayed Transaction.
The MCH supports the Delayed Transaction mechanism on the AGP target interface for the transactions
issued using AGP FRAME# proto col. This mechanism is co mpatible with the PCI 2.1 Specification. The
process of latching all information required to complete the transaction, terminating with Retry, and
completing the request without hold ing the master in wait-states is called a Delayed Transaction. The
MCH latches the Address and Command when establishing a Delayed Transaction. The MCH generates
a Delayed Transaction on AGP only for AGP FRAME# to DRAM read accesses. The MCH does not
allow more than one Delayed Transaction access from AGP at any time.
132 Datasheet
5.3. RDRAM Interface
The 82840 MCH directly supports Dual channels(interfaces) of Rambus* Direct memory operating in
lock-step using RSL technology. The MCH support two different operation modes:
• Single Channel-pair Mode. T he MCH is configured to directly support RDRAM devices on its
dual Rambus* interfaces. There is no MRH-R used on the memory subsystem. A maximum of
64 RDRAM devices are supported on the paired channels without external logic.
• Multiple Channel-pa ir Mode. The MCH is configured to use MRH-R on the memory subsystem.
Each Rambus* channel of the MRH-R on the MCH Direct Rambus* Interface A is paired with one
Rambus* channel of the MRH-R on the Direct Rambus* Interface B. The MCH supports one
MRH-R per interface and each MRH-R can support up to 2 RDRAM channels. Therefore, up to 4
RDRAM channels are supported by the MCH with a total of 2 MRH-Rs (1 MRH-R per interface).
The interface between the MCH and Direct RDRAM devices is referred to either as a “channel" or as an
“expansion channel.” The channel interface consists of 33 signals including clocks (30 are RSL signals
and 3 are CMOS signals). When MRH-R is used for channel expansion, there are two additional RSL
signals per channel.
Figure 6 shows the interconnections between MCH and its dual Direct RDRAM channels configured in
single channel-pair mode.
Figure 6. Si ngle Channel-pair Mode
82840 MCH
Channel A
RDRAM
CFM, CFM#
RQ[7:0]
DQ[15:0], DQP[1:0]
SFM, STM, SCFM
CTM, CTM#
Terminator
CFM, CFM#
RQ[7:0]
DQ[15:0], DQP[1:0]
SFM, STM, SCFM
Gen
Clock
Channel B
RDRAM
CFM, CFM#
RQ[7:0]
DQ[15:0], DQP[1:0]
SFM, STM, SCFM
CTM, CTM#
Terminator
CFM, CFM#
RQ[7:0]
DQ[15:0], DQP[1:0]
SFM, STM, SCFM
Gen
Clock
single_pr-ch
82840 MCH
R
Datasheet 133
Figure 7 shows the interconnections between MCH and its dual Direct RDRAM channels configured at
multiple channel-pair mode .
Figure 7. Multiple Channel-pair Mode
multi_pr-ch
Terminator
Rambus Expansion
Channel B
MRH-R
82840
MCH
Up to 32 RDRAM
Devices
Terminator
Rambus Expansion
Channel A
MRH-R
The maximum system memory supported by MCH depends on the Direct RDRAM device technology
(Table 14).
Table 14. Maximum Memory Supported For Various Configur ations
Directly Supported Supported via MRH-R(s) RDRAM
Increments Maximum Increments Maximum
64Mb 16 MB 512 MB 16 MB 1 GB
128Mb 32 MB 1 GB 32 MB 2 GB
256Mb 6 4MB 2 GB 64 MB 4 GB
The row, column, and bank address bits required for the Direct RDRAM device depends on the number
of banks and page size of device. Table 15 shows the different combinations supported by the MCH.
134 Datasheet
Table 15. Direct RDRAM Device Configurations
CF# Device
Tech Device
Capacity
in MB
# of Banks
(D= dependent) Page
Size # of Bank
Address
Bits
# of Row
Address
Bits
# of
Column
Address
Bits
1 64Mbit 8 16 (D) 1 KB 4 9 6
2 128Mbit 16 2x16 (D) 1 KB 5 9 6
3 32 2x16 (D) 1 KB 5 10 6
4
256Mbit
32 2x16 (D) 2 KB 4 10 7
A brief overview of the registers that configure the Direct RDRAM interface is provided below:
• Group Boundary Address Register (GBA). GB A registers define the upper and lower addresses
for a group of Direct RDRAM device pairs in a channel-pair. Each group requires a separate GBA
register. Each group consists of 4 device-pairs in single channel mode and 8 device-pairs in multiple
channel mode. The MCH contains 16 GBA registers.
• Group Architecture Register (GAR). GAR registers specify the architecture features of each
group of device pairs in a channel pair. The architecture features specified are bank type and device
core technology. Each GAR represents a group consisting of 4 device-pairs in single channel mode
and 8 device-pairs in multiple channel mode. There is a 1:1 correspondence between GBA and
GAR registers.
• RDRAM Timing Register (RDTR). The DTR defines the timing parameters for all devices in all
channels. The BIOS programs this register with “least common denominator” values after reading
configuration registers of each device in the channels.
• RDRAM Poo l Sizing Register (RPMR). T his register provides bits to program the number of
RDRAM device-pair in one of three RDRAM power management states.
• RDRAM Initia liza tion Control Register (RICM). This register provides bits to pro gram MCH to
do initialization activities on Direct RDRAM devices.
5.3.1. RDRAM Organization and Configuration
The MCH supports 16/18-bit Direct RDRAM configurations. The MCH supports a maximum of
64 RDRAM devices (32 devices per channel) on its dual Direct RDRAM channels. Direct RDRAM
channel can be populated with a mix of 64Mbit, 128Mbit, and 256Mbit Direct RDRAM devices.
82840 MCH
R
Datasheet 135
5.3.1.1. Rules for Populating RDRAM Devices
MCH Rambus* channels can be implemented such that it is fully or partially loaded with RDRAM
devices; however, they must be populated in either single-device pair or multiple-device pair.
• Single Device-pair. The 82840 MCH is configured to directly support RDRAM devices on its dual
Rambus* channel. Each RDRAM device of the MCH Direct Rambus* Interface A is paired with
one RDRAM device of the Direct Rambus* Interface B. There is no MRH-R used on the memory
subsystem.
• Multiple Device-pair. The 82840 MCH is configured to use MRH-R on the memory subsystem.
Each RDRAM deivce on Direct Ramb us* Interface A is paired with one RDRAM device on the
Direct Rambus* Interface B.
From the MCH point-of-view, all device-pairs in the channels are grouped into logical groups. System
initialization software partitions the RDRAMs into groups of four device-pairs in single channel mode
operation and into groups of eight device-pairs in multiple channel mode operation. As a result, there can
be a maximum of 8 groups per channel-pair in single channel-pair operation and a maximum of 4 groups
per channel pair in multiple channel-pair mode. All device-pairs populated in a group must be of the
same architecture. That is, all device-pairs in a group must be the same core technology, and have the
same number of banks. Following are the rules for populating the groups:
• A group can be partially populated.
• There is no requirement that group members have to be populated in contiguous physical slots.
• There can be a maximum of 8 groups in single channel-pair mode or 4 groups per channel in
multiple channel-pair mode. A member that does not belong to any of the groups in the channel will
not be recognized.
The following table provides the device IDs for members in all groups.
Table 16. RDRAM Device Grouping
Single Channel Mode Multiple Channel M ode
Device-Pair I Ds for
Group Members Group Name Device Pair IDs for Group
Members Group Name
0, 1, 2, 3 Group#0 0, 1, 2, 3, 4, 5, 6, 7, Ch#0 Pair, Group#0
4, 5, 6, 7 Group#1 8, 9, 10, 11, 12, 13, 14, 15 Ch#0 Pair, Group#1
8, 9, 10, 11 Group#2 16, 17, 18, 19, 20, 21, 22, 23 Ch#0 Pai r, Group#2
12, 13, 14, 15 Group#3 24, 25, 26, 27, 28, 28, 30, 31 Ch#0 Pai r, Group#3
16, 17, 18, 19 Group#4 0, 1, 2, 3, 4, 5, 6, 7, Ch#1 Pai r, Group#0
20, 21, 22, 23 Group#5 8, 9, 10, 11, 12, 13, 14, 15 Ch#1 Pair, Group#1
24, 25, 26, 27 Group#6 16, 17, 18, 19, 20, 21, 22, 23 Ch#1 Pai r, Group#2
28, 29, 30, 31 Group#7 24, 25, 26, 27, 28, 28, 30, 31 Ch#1 Pai r, Group#3
0, 1, 2, 3, 4, 5, 6, 7, Ch#2 Pair, Group#0
8, 9, 10, 11, 12, 13, 14, 15 Ch#2 P ai r, Group#1
16, 17, 18, 19, 20, 21, 22, 23 Ch#2 Pair, Group#2
24, 25, 26, 27, 28, 28, 30, 31 Ch#2 Pair, Group#3
136 Datasheet
Single Channel Mode M ultiple Channel Mode
Device-Pair IDs for
Group Members Group Name Device Pair IDs for Group
Members Group Name
0, 1, 2, 3, 4, 5, 6, 7, Ch#3 Pair, Group#0
8, 9, 10, 11, 12, 13, 14, 15 Ch#3 P ai r, Group#1
16, 17, 18, 19, 20, 21, 22, 23 Ch#3 Pair, Group#2
24, 25, 26, 27, 28, 28, 30, 31 Ch#3 Pair, Group#3
NOTES:
1. All RSL signals must be terminated at the f ar end from t he MCH.
2. The default device ID for an RDRA M devic e after power up is 1Fh.
5.3.1.2. RDRAM CMOS Signal Description and Usage
There are 3 CMOS signal pins per channel on the MCH to support Direct RDRAM device configuration,
SIO reset, register accesses, and Nap and PowerDown exits. These signals are SCK, CMD and SIO.
They are used to perform the following operations:
• SIO pin initialization
• SIO operations (includes register accesses and device reset)
• Device selection for Nap and PowerDown exits
Figure 8. RDRAM Devices Sideband CMOS Signal Configuration on Rambus* Channel A
rdram_cmos
SIO SIO1
SIO0
SIO0
SCK
CMD
SCK
CMD
82840
MCH
Rambus channel
A
Note: MCH supports Dual Rambus Direct Channels.
RDRAM
RDRAM
RDRAM
RDRAM
82840 MCH
R
Datasheet 137
Figure 9. MRH-R Sideband CMOS Signal Configuration on Rambus* Channel A
rdram_cmos_mrh-r
SIO
SIO0
SCK
CMD
SCK
CMD
82840
MCH
Rambus channel
A
MRH-R
Table 17. Sideband CMOS Signal Description
Signal Description
SCK Serial Clock: This signal serves as the c l ock for S I O and CMD s i gnal s. SCK i s a cloc k source us ed
for reading from and writing to c ontrol regist er.
• For SIO operati ons and pin initi al i zat ion, SCK ≤ 1 MHz
• For power mode operations, SCK ≤ 100 MHz
CMD Command: CMD is a control si gnal used for power mode transitions , SIO pin configurati on duri ng
initial i zat i on, and framing of SIO operati ons. CMD is ac tive high. This signal is sampled at both
edges of SCK and is a level sensit i ve s i gnal .
SIO Serial In Out: This bi-directi onal signal is dai sy chained through al l Di rect RDRAM (SI O0 to SIO1)
devices i n a channel. This pi n carries data used for SI O operat i ons that include register acces ses,
device reset, and device ID initial i zat i on. SIO is al so used for power m ode control. S IO is an active
low signal and is sam pled on the falling edge of SCK.
Table 18. CMD Signal Value Decode
SIO = 0, CMD Sample Value
on 4 SCK Edges SIO = 1, CMD Sample Val u e
on 4 SCK Edges
Cycle 0 Cycle 1
Command
Cycle 0 Cycle 1
Command
0 1 x x Nap Exit 0 1 x x Power-down Exit
1 0 x x Reserved 1 0 x x Reserved
0 0 x x No-op 0 0 x x No-op
1 1 1 1 SIO Request Frame 1 1 1 1 SIO Request
Frame
1 1 0 0 SIO Reset 1 1 0 0 SIO Reset
1 1 1 0 Reserved 1 1 1 0 Reserved
1 1 0 1 Reserved 1 1 0 1 Reserved
138 Datasheet
SIO Pin Initialization
SIO0 and SIO1 pins on Direct RDRAM devices are bi-directional; their direction needs to b e initialized.
The “SIO Reset” initializes SIO0 and SIO1 pins on all Direct RDRAMs as daisy chain configuration and
is performed with SCK and CMD. Once the SIO daisy chain is fully configured, SIO operations can
occur. Note “SIO Reset” does NOT reset the entire device. For a complete description of operation and
associated timing diagram, refer to Direct RDRAM data sheet from Rambus*.
SIO Operations
SIO operations are also known as Direct RDRAM initialization operations. These operations include
Direct RDRAM register accesses and device reset, and are performed using the SCK, CMD, SIO0, and
SIO1 CMOS pins. For a complete description of operation and associated timing diagram, refer to the
Direct RDRAM data sheet from Rambus*.
Nap and PowerDown Exits
The Nap and Power Down exits are performed using CMD, SIO and SCK signals. For a complete
description and timing diagrams associated with Nap and PowerDown exits, refer to Direct RDRAM
data sheet from Rambus*.
5.3.1.3. Direct RDRAM Core Refresh
All rows in an Direct RDRAM device must be refreshed within 32 ms. The refresh rate depends on the
device size and page size of a device. MCH supports two core refresh mechanisms: Active refresh and
self refresh.
• Active Refresh. Refresh and precharge after refresh commands are issued from the primary control
packet. These commands provide refresh support in Standby/Active modes.
• Self Refresh. Internal timebase and row/bank address counters in the core provide allow for a self
refresh in PowerDown modes without controller support.
5.3.1. 4. Direct RDRAM Current Calibration
All Direct RDRAM devices must be current calibrated once every 100 ms. T here are RSL commands to
perform this function. The MCH schedules periodic current calibration activity such that every device in
the channel is current calibrated at least once every 100 ms.
5.3.2. Direct RDRAM Command Encoding
The operations on a Direct RDRAM channel are performed using control packets. There are two types of
command packets—row(ROWA/ROWR) packet and column (COLC/COLM/COLX) packet. Each
command packet requires 4 Direct RDRAM clock duration and packet data is transferred on both
(leading and falling) edges of the clock. A Row packet contains 24 bits and column packet contains 40
bits.
82840 MCH
R
Datasheet 139
5.3.2.1. Row Packet (ROWA/ROWR)
The row packet is defined using three RSL signals RQ[7:5]/ROW[2:0]. The row packet is generally the
first control packet issued to a device. Major characteristics of a row packet are:
• The only way to activate (sense) a row within a bank
• Independent of Direct RDRAM’s active/standby state
• A non-broadcast row package causes an addressed Direct RDRAM to move to active state
The packet definition of row packet is provided in the following table.
Table 19. ROWA Packet for Activating (sensing) a Row (i.e., AV = 1)
Row # Cycle 0 Cycl e 1 Cycle 2 Cycle 3
ROW2 DR4T DR[2] BR[0] BR[3] R[10] R[8] R[5] R[2]
ROW1 DR4F D[R1] BR[1] BR[4] R[9] R[7] R[4] R[1]
ROW0 DR[3] DR[0] BR[2] REV AV = 1 R[6] R[3] R[0]
Table 20. ROWR Packet for other operations (i.e., AV = 0)
Row # Cycl e 0 Cycle 1 Cycle 2 Cycle 3
ROW2 DR4T DR[2] BR[0] BR[3] ROP[10] ROP[8] ROP[5] ROP[2]
ROW1 DR4F DR[1] BR[1] BR[4] ROP[9] ROP[7] ROP[4] ROP[1]
ROW0 DR[3] DR[0] BR[2] REV AV = 0 ROP[6] ROP[3] ROP[0]
DR4T DR4F Device ID
0 0 No row packet
0 1 DR[3:0], DR[4] = 0
1 0 DR[3:0], DR[4] = 1
1 1 Broadcast
DR[4] – DR[0] Device address
BR[5] – BR[0] Bank Address
R[10] – R[0] Row address
AV Select between ROWA and ROWR, Active Row
ROP[10] – ROP[0] Opcode for Primary Control Packet
REV Reserved
140 Datasheet
Opcode bits AV
10 9 8 7 6 5 4 3 2: 0
Operation
Description
1 x x x x x x x x xxx Activate Row
0 1 1 0 0 0 0 0 0 000 Precharge
0 1 1 0 0 0 0 0 1 000 Precharge & Relax
0 0 0 0 1 1 0 0 0 000 Refresh
0 1 0 1 0 1 0 0 0 000 Precharge
Postrefresh
0 0 0 0 0 0 1 0 0 000 Nap
0 0 0 0 0 0 1 1 0 000 Conditional Nap
0 0 0 0 0 0 0 1 0 000 Power Down
0 0 0 0 0 0 0 0 1 000 Relax
0 0 0 0 0 0 0 0 0 010 Temp Calibration
Enable
0 0 0 0 0 0 0 0 0 001 Temp Calibration
0 0 0 0 0 0 0 0 0 000 No-op
Legend: x = Controller drives 0 or 1
0 = Controller drives 0
1 = Controller drives 1
82840 MCH
R
Datasheet 141
5.3.2.2. Column Packet (COLC/COLX)
The column packet is defined using five of the RSL signals RQ[4:0]/COL[4:0]. Major characteristics of
column are:
• the only way to dispatch column operation for read or write
• requires the target Direct RDRAM to be in active state
Note: When an Direct RDRAM is in active state, it can receive both row and column packets. When a Direct
RDRAM is in Standby state, it can only receive a row packet. Thus, before sending a column packet,
make sure the addressed Direct RDRAM is in active state.
The packet definition of column packet is provided belo w.
Table 21. COLC Packet
Col # Cycle 0 Cycle 1 Cycle 2 Cycle 3
COL4 DC[4] S = 1 C[6] C[4]
COL3 DC[3] C[5] C[3]
COL2 DC[2] COP[1] REV BC[2] C[2]
COL1 DC[1] COP[0] BC[4] BC[1] C[1]
COL0 DC[0] COP[2] COP[3] BC[3] BC[0] C[0]
DC[4:0] Device ID for Column Operation
S Start bit, for framing
M Mask bit. Asserted indicates mask format for packet
COP[3:0] Column Operation Code
C[6:0] Address for Column operation
BC[4:0] Bank Address for Column operation
REV Reserved
Table 22. COLC Packet Field Encodings
S COP[3] COP[2] COP[1] COP[0] Command Operation
0 x x x x No operation
1 x 0 0 0 NOCOP. Retire write buffer of this device
1 x 0 0 1 Write
1 x 0 1 1 Read
NOTES: A l l other com bination are reserved
142 Datasheet
Table 23. COLX Packet (M = 0)
Cycle 0 Cycle 1 Cycle 2 Cycle 3
COL4 DX[4] XOP[4] REV BX[1]
COL3 M = 0 DX[3] XOP[3] BX[4] BX[0]
COL2 DX[2] XOP[2] BX[3]
COL1 DX[1] XOP[1] BX[2]
COL0 DX[0] XOP[0]
DX[4:0] Device ID for Extra operation
BX[4:0] Bank Address for Extra operation
MA[7:0] Byte Mask (low order)
MB[7:0] Byte Mask (high order)
XOP[4:0] Opcode for Extra Operation
REV Reserved
Table 24. COLM Packet and COLX Packet Field Encodings
M XOP Bits Operation Description
4 3 2 1 0
1 x x x x x Non existent Xop
0 0 0 0 0 0 NoXop
0 1 0 0 0 0 Reserved
0 0 1 0 0 0 Calibrate Current
0 0 1 1 0 0 Calibrate Current & Sample
0 0 0 0 0 1 Reserved
Legend: x = Controller drives 0 or 1
0 = Controller drives 0
1 = Controller drives 1
5.3.2.3. Data Packet
Table 25. Data Packet
Cycle 0 Cycle 1 Cycle 2 Cycle 3
DQA[8:0] DA0[8:0] DA1[8:0] DA2[8:0] DA3[8:0] DA4[8:0] DA5[8:0] DA6[8:0] DA7[8:0]
DQB[8:0] DB0[8:0] DB1[8:0] DB2[8:0] DB3[8:0] DB4[8:0] DB5[8:0] DB6[8:0] DB7[8:0]
82840 MCH
R
Datasheet 143
5.3.3. Direct RDRAM Register Pr ogramming
Software can read and write Direct RDRAM device registers by programming the RDRAM Initialization
Control Management (RICM) Register in the MCH. The register data returned by the device will be
available in the Device Register Data (DRD) Register.
5.3.4. Direct RDRAM Operating States
The Direct RDRAM devices support different operating and idle states to minimize the power
consumption and thermal overload. Table 26 provides an overview of the different operating/power
states supported by Direct RDRAMs.
Table 26. DRAM Operating States
Direct RDRAM
State Functionality Refresh
Scheme RDRAM
Clock State
Inactive S tates
PowerDown No operation allowed except refresh. Direct RDRAM
awaits CMOS signal s to exit PowerDown state Sel f Refresh stopped
Nap No operation al l owed except refresh. Direct RDRAM
awaits Nap exit command t o exit Nap Active Refresh stopped
Active States
Standby Device Ready t o receive row packet . with fast clock Active Ref resh ful l speed
Act i ve Device ready to rec ei ve any control packet Active Ref resh ful l speed
Act i ve-Read Device ready to receive any control packet.
Transm i t ting data on channel Active Refresh full s peed
Act i ve-Write Device ready to recei ve any control packet.
Receiving data from c hannel Active Refresh full speed
Active-Read/Write st at e
A Direct RDRAM device is in active-Read/Write state when it is transferring data. This state lasts as
long as the data transfer is occurring. Once the data transfer is done, the Direct RDRAM transitions into
Active or Standby state based on the column command last executed.
Active State
A Direct RDRAM enters into active state immediately after the data transfer from/to that device is done
and the last COLC command that caused the data transfer does not have its RC bit set to 1. When a
device is in Active state, it can accept both row and column packets.
Standby State
A Direct RDRAM enters into Standby state either from Active-Read/Write or Active state. Transition
from Active-Read/Write to Standby happens if the last column executed has its RC bit set to 1.
Transition from Active to Standby happens if COLC or row specifies an operation with Relax. When a
144 Datasheet
device is in Standby mode, it can accept only row packets. Once a device receives any row packet, it
transitions into active state and then can accept a column packet.
Nap State
A Direct RDRAM enters into Nap state when it receives a row packet that specified an operation with
Nap. No operations except refresh is allowed during Nap state.
PowerDown State
A Direct RDRAM enters into PowerDown state when it receives a row packet which specified an
operation with PowerDown. No operations, except Self-refresh, are allowed during PowerDown state.
RDRAM Operating Pools
To minimize the operating power, the RDRAM devices are grouped into two operating pools called Pool
“A” and Pool “B”.
Pool “A” and Pool “B” Operat i on
In the “pool” mode, two queues are used inside the MCH: pool “A” contains references to device pairs
that are currently in the active mode while pool “B” contains references to device pairs that are in the
standby mode. All devices that are found in neither pool are either napping or standby. Pool “A” may
hold between 1 and 8 device pairs, while pool “B” may be configured to contain between 1 and 16
device pairs.
5.3.5. RDRAM Power Management
82840 MCH systems support ACPI based power management. The MCH puts all RDRAM devices into
PowerDown (PD) state during S3 power management states. To enter the PowerDown state all RDRAM
devices in the channel must be in active or standby state. The MCH then sends a broadcast PowerDown
command to that channel.
During PowerDown state, RDRAM devices are put into Self Refresh mode so that external (active)
refreshes are not required. During the powerdown state, the clocks to RDRAM are shut off. Exiting the
powerdown and Nap states are done t hrough CMO S signals. Table 27 shows the actions taken by MCH
during different processor and System power states.
Table 27. RDRAM Power Management States
Processor
State System
State State of
RDRAMs in
Pool “A”
State of
RDRAMs in
Pool “B”
State of
RDRAMs in
Pool “C”
Refresh
Scheme RDRA M
Clock
State
C0, C1, C2
(processor in
working stat e)
S0 Active-
Read/Write,
Active
Standby Nap or
Standby Active Running
(processor in
inacti ve state) S1,
S3( STR) No devices
in Pool “A” No devi ces in
Pool “B” Powerdown Self Stopped
82840 MCH
R
Datasheet 145
5.3.6. Data Integrity
The MCH supports an Error Correcting Code (or Error Checking and Correcting) on the main memory
interface. The MCH can optionally be configured to generate the ECC code for writes to memory and
check the code for reads from memory. The MCH generates an 8-bit code word for each 64-bit QWord
of memory. Since the code word covers a full QWord, writes of less than a QWord require a read-merge-
write operation. Consider a DWord write to memory. In this case, when in ECC mode, the MCH will
read the QWord where the addressed DWord will be written, merge in the new DWord, generate a code
covering the new QWord and finally write the entire QWord and code back to memory. Any correctable
(single) errors detected during the initial QWord read are corrected before merging the new DWord.
Error scrubbing is supported by the MCH. When enabled, this feature not only corrects single bit error
data being returned to the requesting agent but also writes the corrected value back to the DRAM array.
Single-bit and multiple-bit errors set separate flags in the ERRSTS register. Single-bit errors and
mutiple-bit errors can be independently enabled to generate hub interface SERR, SMI, or SCI special
cycles to the ICH. The address and syndrome of the first single bit error are latched in the EAP and
DERRCT L registers. Subsequent single bit errors do not ove rwrite the EAP and DERRCTL r egisters
unless the single-bit error status bit is cleared. A multiple-bit error overwrites the EAP and DERRCTL
registers. Sub sequent multiple-bit errors do not overwrite the EAP and DERRCTL registers, unless the
multiple-bit error status bit is cleared.
5.3.7. RDRAM Array Thermal Management
The RDRAM thermal and power management functions of the 82840 MCH have been optimized for
workstation and server system designs. It is assumed that proper system design will always provide and
ensure adequate cooling in a 82840 chipset based system. The failsafe mechanism that protects the
devices in the event of a catastrophic failure requires an external thermal sensor. When the thermal
sensor is activated, the MCH immediately exits the “all devices on” mode and reverts the pool mode that
has been programmed by system software.
In a 82840-based system, RDRAM operates in one of three modes: active, standby, or nap. The number
of devices allowed in each state at any given time is dictated by the heat dissipation budget specified by
the system designer. From 1 to 8 device-pairs may be in pool “A” and are configured to operate in the
active mode. In addition, from 1 to 16 device-pairs may be in pool “B” and are configured to operate in
the standby mode. The rest of the device-pairs are in pool “C” and may be configured to operate in
either nap mode or standby mode. Regardless of how many devices are configured into pool “A” and
pool “B” or whether the pool “C” devices are in napping or standby mode, the system designer is
responsible for providing adequate cooling for the number of RDRAM devices in the system.
After BIOS loads the system’s “target” values into the DPS register and initializes the pools, it should
load a “safer” set of values into the DPS register without setting the POOLINIT field. The POOLINIT
bit instructs the MCH to transition to the new pool sizes. There are two other conditions that cause the
82840 MCH to resize and initialize the pools:
• The transition of the OVERT# pin from electrical 1 to electrical 0
• The detection of an overtemperature condition on any RDRAM device
The OVERT# method is intended to allow system designers to use external thermal sensors to monitors
the system temp erature and assert OVERT# when system temperature exceeds system specifications.
When the 82840 MCH detects a falling edge on the OVERT# signal, it reinitializes and resizes the pools
with whatever values are in the DPS register. Also, the RDRAM devices report overtemperature
146 Datasheet
conditions back to the MCH via a special bit asserted during their current calibration operations. When
the MCH detects an overtemperature condition in any of the memory devices, the RDRAM pools are
reinitialized with “safer” values. Finally, the MCH ma y be configured to send an SERR, SCI, or SMI hub
interface message to ICH. The software may take action to cool the system o r to log the condition.
5.4. System Reset
The reset scheme for 82840 MCH is shown in Figure 10. After PWROK is asserted to indicate the
system power is stable, RSTIN# is generated by ICH and is used as an input to reset the MCH. The MCH
always asserts CPURST #, if RST IN# is asser t e d. The assertio n of CPURST# resets the processors, a s
well as ITP. CPURST# is deassert e d synchronous to the host bus clock.
Figure 10. 82840 MCH Reset
reset_overview
ITP
MCH CPURST#
RSTIN#
ICH PCIRST#
INIT#
PWROK
PWRGOOD
ITP_RST#
INIT#
Processor
RESET#PWRGOOD
NOTES: The di agram does not represent all the details f or schematics connect i on.
148 Datasheet
Figure 11. MCH Ballout (Top View, Left Side)
1 2 3 4 5 6 7 8 9 10 11 12 13
A AGPRCOMP AGPREF GAD8 VCC1_8 CLK66 GFRAME# GAD17 GC/BE3# GAD25 GAD30 SBA4 SBA2 RBF#
B GAD3 GAD7 GC/BE0# GAD12 VSS GDEVSEL# VSS GAD21 GAD24 VSS SBA5 VSS PIPE#
C GAD2 GAD6 VDDQ VSS GPAR GTRDY# GAD18 VDDQ ADSTB1 GAD29 SBSTB# SBA3 VDDQ
D GAD1 VSS ADSTB0 GAD11 G/CBE1# GSTOP# GC/BE2# GAD22 ADSTB1# GAD28 SBA6 SBSTB WBF#
E GAD0 GAD5 ADSTB0# GAD10 GAD15 VSS GAD16 GAD19 VSS GAD27 SBA7 VSS SBA0
F VSS GAD4 VSS GAD9 GAD14 GSERR# GIRDY# GAD20 GAD23 GAD26 GAD31 VDDQ SBA1
G CHA_DQA8 VSS CHA_DQA7 VSS GAD13 VDDQ VDDQ VDDQ VDDQ Vcc1_8
H CHA_DQA6 VSS CHA_DQA5 VSS VSS VDDQ Vcc1_8
J CHA_DQA2 CHA_DQA4 CHA_DQA3 VSS VSS VCC1_8 VCC1_8
K CHA_DQA0 VSS CHA_DQA1 VSS VSS VCC1_8 VCC1_8
L CHA_CFM CHA_CFM# VSS VSS VSS VCC1_8 VCC1_8 VCC1_8 VSS
M CHA_CTM# CHA_CTM VSS VSS VSS VCC1_8 VCC1_8 VSS VSS
N CHA_RQ6 VSS CHA_RQ7 VSS VSS CHA_REF0 VSS VSS VSS
P CHA_RQ5 CHA_EXP1 CHA_EXP0 VSS VSS CHA_REF1 VSS VSS VSS
R CHA_RQ4 VSS CHA_RQ3 VSS VSS Vcc1_8 VCC1_8 VSS VSS
T CHA_RQ2 CHA_RQ1 CHA_RQ0 VSS VSS VCC1_8 VCC1_8 VCC1_8 VSS
U CHA_DQB1 VSS CHA_DQB0 VSS VSS VCC1_8 VCC1_8
V CHA_DQB3 CHA_DQB6 CHA_DQB2 VSS VSS VCC1_8 VCC1_8
W CHA_DQB5 VSS CHA_DQB4 VSS VSS NC VCC1_8
Y CHA_DQB7 VSS CHA_DQB8 VSS VSS Vcc1_8 Vcc1_8 VCC1_8 VCC1_8 VCC1_8
AA VSS VSS VSS CMDA SCKA OVERT# Vcc1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 CHB_REF0
AB RCLKOUTA SIOA DCLKOUTA HLAPD0 VSS RSTIN# VSS VSS VSS VSS VSS VSS VSS
AC HLAPD3 VSS HLA11 HLAPD2 HLAPD1 TEST# VSS VSS VSS VSS VSS VSS VSS
AD HLA8 HLASTB# HLASTB VSS DCLKOUTB VSS CHB_DQA7 CHB_DQA5 CHB_DQA3 CHB_DQA1 VSS VSS CHB_RQ7
AE HLAPD6 VSS HLA10 HLAPD4 HLA9 VSS VSS VSS CHB_DQA4 VSS CHB_CFM# CHB_CTM VSS
AF HLAPD7 HLAPD5 HLAREF HLAZCOMP RCLKOUTB VSS CHB_DQA8 CHB_DQA6 CHB_DQA2 CHB_DQA0 CHB_CFM CHB_CTM# CHB_RQ6
1 2 3 4 5 6 7 8 9 10 11 12 13
82840 MCH
R
Datasheet 149
Figure 12. MCH Ballout (Top View, Right Side)
14 15 16 17 18 19 20 21 22 23 24 25 26
GREQ# HLBSTB0# HLBSTB0 HLB17 HLBPD9 HLBRCOMP IERR# GTLREFA VCC1_8 VSS DEP2# DEP4# DEP0# A
GGNT# VSS HLBPD4 VSS HLBPD10 VSS HLBREF DEP1# HCLKIN DEP3# DEP7# VSS DEP5#
B
ST0 HLBPD1 HLBPD5 HLB19 HLBPD11 HLBPD13 DEP6# HD61# VSS HD62# HD58# HD63# HD55#
C
ST1 HLBPD2 HLBPD6 HLB16 HLBSTB1# HLBPD14 HD60# HD53# HD57# HD56# HD50# HD54# HD46#
D
ST2 VSS HLBPD7 VSS HLBSTB1 VSS HD49# VSS HD51# HD59# HD48# VSS HD42#
E
HLBPD0 HLBPD3 HLB18 HLBPD8 HLBPD12 HLBPD15 HD45# HD39# HD52# VSS HD41# HD47# HD43#
F
Vcc1_8 Vcc1_8 Vcc1_8 VSS HD37# HD33# HD44# HD36# HD40# HD35#
G
VTT HD31# VSS HD34# HD38# VSS HD30#
H
VTT HD27# HD24# HD32# HD28# HD29# HD23#
J
VTT HD21# HD16# HD26# HD25# HD22# HD13#
K
VSS VCC1_8 VCC1_8 HD11# VSS HD19# HD18# VSS HD10#
L
VSS VSS VCC1_8 HD14# HD9# HD20# HD17# HD15# HD8#
M
VSS VSS VSS HD5# HD3# HD12# HD7# HD6# HD1#
N
VSS VSS VSS BERR# VSS HD4# HD2# VSS HA33#
P
VSS VSS VCC1_8 HA34# HA30# HD0# CPURST# HA35# HA32#
R
VSS VCC1_8 VCC1_8 HA31# HA27# HA22# HA29# HA26# HA24#
T
VTT HA23# VSS HA19# HA28# VSS HA20#
U
VTT HA18# HA16# HA13# HA21# HA25# HA15#
V
VTT HA14# HA10# HA5# HA17# HA11# HA12#
W
VCC1_8 VCC1_8 VCC1_8 VSS HA9# VSS HA4# HA8# VSS HA7#
Y
CHB_REF1 Vcc1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 BNR# BPRI# HA3# HA6# HREQ0# HTRDY#
AA
VSS VSS VSS VSS VSS VSS VSS SCKB DEFER# HREQ1# HREQ4# HLOCK# HREQ2#
AB
VSS VSS VSS VSS VSS VSS VSS CMDB VSS HREQ3# DRDY# VSS HITM#
AC
CHB_EXP0 CHB_RQ3 CHB_RQ0 CHB_DQB0 CHB_DQB2 CHB_DQB4 CHB_DQB8 VSS DBSY# RS0# HIT# RS2# RP# AD
CHB_EXP1 VSS CHB_RQ1 VSS CHB_DQB6 VSS VSS VSS SIOB VSS RSP# VSS ADS#
AE
CHB_RQ5 CHB_RQ4 CHB_RQ2 CHB_DQB1 CHB_DQB3 CHB_DQB5 CHB_DQB7 VSS GTLREFB RS1# BREQ0# AP0# AP1# AF
14 15 16 17 18 19 20 21 22 23 24 25 26
150 Datasheet
Table 28. MCH Alphabetical Ballout List
Signal Ball #
ADS# AE26
ADSTB0 D3
ADSTB0# E3
ADSTB1 C9
ADSTB1# D9
AGPRCOMP A1
AGPREF A2
AP0# AF25
AP1# AF26
BERR# P21
BNR# AA21
BPRI# AA22
BREQ0# AF24
CHA_CFM L1
CHA_CFM# L2
CHA_CTM M2
CHA_CTM# M1
CHA_DQA0 K1
CHA_DQA1 K3
CHA_DQA2 J1
CHA_DQA3 J3
CHA_DQA4 J2
CHA_DQA5 H3
CHA_DQA6 H1
CHA_DQA7 G3
CHA_DQA8 G1
CHA_DQB0 U3
CHA_DQB1 U1
CHA_DQB2 V3
CHA_DQB3 V1
CHA_DQB4 W3
CHA_DQB5 W1
CHA_DQB6 V2
CHA_DQB7 Y1
CHA_DQB8 Y3
Signal Ball #
CHA_EXP0 P3
CHA_EXP1 P2
CHA_REF0 N6
CHA_REF1 P6
CHA_RQ0 T3
CHA_RQ1 T2
CHA_RQ2 T1
CHA_RQ3 R3
CHA_RQ4 R1
CHA_RQ5 P1
CHA_RQ6 N1
CHA_RQ7 N3
CHB_CFM AF11
CHB_CFM# AE11
CHB_CTM AE12
CHB_CTM# AF12
CHB_DQA0 AF10
CHB_DQA1 AD10
CHB_DQA2 AF9
CHB_DQA3 AD9
CHB_DQA4 AE9
CHB_DQA5 AD8
CHB_DQA6 AF8
CHB_DQA7 AD7
CHB_DQA8 AF7
CHB_DQB0 AD17
CHB_DQB1 AF17
CHB_DQB2 AD18
CHB_DQB3 AF18
CHB_DQB4 AD19
CHB_DQB5 AF19
CHB_DQB6 AE18
CHB_DQB7 AF20
CHB_DQB8 AD20
CHB_EXP0 AD14
Signal Ball #
CHB_EXP1 AE14
CHB_REF0 AA13
CHB_REF1 AA14
CHB_RQ0 AD16
CHB_RQ1 AE16
CHB_RQ2 AF16
CHB_RQ3 AD15
CHB_RQ4 AF15
CHB_RQ5 AF14
CHB_RQ6 AF13
CHB_RQ7 AD13
CLK66 A5
CMDA AA4
CMDB AC21
CPURST# R24
DBSY# AD22
DCLKOUTA AB3
DCLKOUTB AD5
DEFER# AB22
DEP0# A26
DEP1# B21
DEP2# A24
DEP3# B23
DEP4# A25
DEP5# B26
DEP6# C20
DEP7# B24
DRDY# AC24
G/CBE1# D5
GAD0 E1
GAD1 D1
GAD2 C1
GAD3 B1
GAD4 F2
GAD5 E2
Signal Ball #
GAD6 C2
GAD7 B2
GAD8 A3
GAD9 F4
GAD10 E4
GAD11 D4
GAD12 B4
GAD13 G5
GAD14 F5
GAD15 E5
GAD16 E7
GAD17 A7
GAD18 C7
GAD19 E8
GAD20 F8
GAD21 B8
GAD22 D8
GAD23 F9
GAD24 B9
GAD25 A9
GAD26 F10
GAD27 E10
GAD28 D10
GAD29 C10
GAD30 A10
GAD31 F11
GC/BE0# B3
GC/BE2# D7
GC/BE3# A8
GDEVSEL# B6
GFRAME# A6
GGNT# B14
GIRDY# F7
GPAR C5
GREQ# A14
82840 MCH
R
Datasheet 151
Signal Ball #
GSERR# F6
GSTOP# D6
GTLREFA A21
GTLREFB AF22
GTRDY# C6
HA3# AA23
HA4# Y23
HA5# W23
HA6# AA24
HA7# Y26
HA8# Y24
HA9# Y21
HA10# W22
HA11# W25
HA12# W26
HA13# V23
HA14# W21
HA15# V26
HA16# V22
HA17# W24
HA18# V21
HA19# U23
HA20# U26
HA21# V24
HA22# T23
HA23# U21
HA24# T26
HA25# V25
HA26# T25
HA27# T22
HA28# U24
HA29# T24
HA30# R22
HA31# T21
HA32# R26
HA33# P26
Signal Ball #
HA34# R21
HA35# R25
HCLKIN B22
HD00# R23
HD1# N26
HD2# P24
HD3# N22
HD4# P23
HD5# N21
HD6# N25
HD7# N24
HD8# M26
HD9# M22
HD10# L26
HD11# L21
HD12# N23
HD13# K26
HD14# M21
HD15# M25
HD16# K22
HD17# M24
HD18# L24
HD19# L23
HD20# M23
HD21# K21
HD22# K25
HD23# J26
HD24# J22
HD25# K24
HD26# K23
HD27# J21
HD28# J24
HD29# J25
HD30# H26
HD31# H21
HD32# J23
Signal Ball #
HD33# G22
HD34# H23
HD35# G26
HD36# G24
HD37# G21
HD38# H24
HD39# F21
HD40# G25
HD41# F24
HD42# E26
HD43# F26
HD44# G23
HD45# F20
HD46# D26
HD47# F25
HD48# E24
HD49# E20
HD50# D24
HD51# E22
HD52# F22
HD53# D21
HD54# D25
HD55# C26
HD56# D23
HD57# D22
HD58# C24
HD59# E23
HD60# D20
HD61# C21
HD62# C23
HD63# C25
HIT# AD24
HITM# AC26
HLA8 AD1
HLA9 AE5
HLA10 AE3
Signal Ball #
HLA11 AC3
HLAPD0 AB4
HLAPD1 AC5
HLAPD2 AC4
HLAPD3 AC1
HLAPD4 AE4
HLAPD5 AF2
HLAPD6 AE1
HLAPD7 AF1
HLAREF AF3
HLASTB AD3
HLASTB# AD2
HLAZCOMP AF4
HLB16 D17
HLB17 A17
HLB18 F16
HLB19 C17
HLBPD0 F14
HLBPD1 C15
HLBPD2 D15
HLBPD3 F15
HLBPD4 B16
HLBPD5 C16
HLBPD6 D16
HLBPD7 E16
HLBPD8 F17
HLBPD9 A18
HLBPD10 B18
HLBPD11 C18
HLBPD12 F18
HLBPD13 C19
HLBPD14 D19
HLBPD15 F19
HLBRCOMP A19
HLBREF B20
HLBSTB0 A16
152 Datasheet
Signal Ball #
HLBSTB0# A15
HLBSTB1 E18
HLBSTB1# D18
HLOCK# AB25
HREQ0# AA25
HREQ1# AB23
HREQ2# AB26
HREQ3# AC23
HREQ4# AB24
HTRDY# AA26
IERR# A20
NC W6
OVERT# AA6
PIPE# B13
RBF# A13
RCLKOUTA AB1
RCLKOUTB AF5
RP# AD26
RS0# AD23
RS1# AF23
RS2# AD25
RSP# AE24
RSTIN# AB6
SBA0 E13
SBA1 F13
SBA2 A12
SBA3 C12
SBA4 A11
SBA5 B11
SBA6 D11
SBA7 E11
SBSTB D12
SBSTB# C11
SCKA AA5
SCKB AB21
SIOA AB2
Signal Ball #
SIOB AE22
ST0 C14
ST1 D14
ST2 E14
TEST# AC6
VCC1_8 W7
VCC1_8 Y8
VCC1_8 Y19
VCC1_8 AA8
VCC1_8 AA19
VCC1_8 AA20
VCC1_8 G10
VCC1_8 G17
VCC1_8 G18
VCC1_8 G19
VCC1_8 H7
VCC1_8 L11
VCC1_8 L12
VCC1_8 L15
VCC1_8 L16
VCC1_8 M11
VCC1_8 M16
VCC1_8 R6
VCC1_8 R11
VCC1_8 R16
VCC1_8 T11
VCC1_8 T12
VCC1_8 T15
VCC1_8 T16
VCC1_8 Y6
VCC1_8 Y7
VCC1_8 AA7
VCC1_8 AA15
VCC1_8 A4
VCC1_8 A22
VCC1_8 J6
Signal Ball #
VCC1_8 J7
VCC1_8 K6
VCC1_8 K7
VCC1_8 L6
VCC1_8 M6
VCC1_8 T6
VCC1_8 U6
VCC1_8 U7
VCC1_8 V6
VCC1_8 V7
VCC1_8 Y9
VCC1_8 Y10
VCC1_8 Y17
VCC1_8 Y18
VCC1_8 AA9
VCC1_8 AA10
VCC1_8 AA11
VCC1_8 AA12
VCC1_8 AA16
VCC1_8 AA17
VCC1_8 AA18
VDDQ C3
VDDQ C8
VDDQ C13
VDDQ F12
VDDQ G6
VDDQ G7
VDDQ G8
VDDQ G9
VDDQ H6
VSS A23
VSS B5
VSS B7
VSS B10
VSS B12
VSS B15
Signal Ball #
VSS B17
VSS B19
VSS B25
VSS C4
VSS C22
VSS D2
VSS E6
VSS E9
VSS E12
VSS E15
VSS E17
VSS E19
VSS E21
VSS E25
VSS F1
VSS F3
VSS F23
VSS G2
VSS G4
VSS G20
VSS H2
VSS H4
VSS H5
VSS H22
VSS H25
VSS J4
VSS J5
VSS K2
VSS K4
VSS K5
VSS L3
VSS L4
VSS L5
VSS L13
VSS L14
VSS L22
82840 MCH
R
Datasheet 153
Signal Ball #
VSS L25
VSS M3
VSS M4
VSS M5
VSS M12
VSS M13
VSS M14
VSS M15
VSS N2
VSS N4
VSS N5
VSS N11
VSS N12
VSS N13
VSS N14
VSS N15
VSS N16
VSS P4
VSS P5
VSS P11
VSS P12
VSS P13
VSS P14
VSS P15
VSS P16
VSS P22
VSS P25
VSS R2
VSS R4
VSS R5
VSS R12
VSS R13
VSS R14
VSS R15
VSS T4
VSS T5
Signal Ball #
VSS T13
VSS T14
VSS U2
VSS U4
VSS U5
VSS U22
VSS U25
VSS V4
VSS V5
VSS W2
VSS W4
VSS W5
VSS Y2
VSS Y4
VSS Y5
VSS Y20
VSS Y22
VSS Y25
VSS AA1
VSS AA2
VSS AA3
VSS AB5
VSS AB7
VSS AB8
VSS AB9
VSS AB10
VSS AB11
VSS AB12
VSS AB13
VSS AB14
VSS AB15
VSS AB16
VSS AB17
VSS AB18
VSS AB19
VSS AB20
Signal Ball #
VSS AC2
VSS AC7
VSS AC8
VSS AC9
VSS AC10
VSS AC11
VSS AC12
VSS AC13
VSS AC14
VSS AC15
VSS AC16
VSS AC17
VSS AC18
VSS AC19
VSS AC20
VSS AC22
VSS AC25
VSS AD4
VSS AD6
VSS AD11
VSS AD12
VSS AD21
VSS AE2
VSS AE6
VSS AE7
VSS AE8
VSS AE10
VSS AE13
VSS AE15
VSS AE17
VSS AE19
VSS AE20
VSS AE21
VSS AE23
VSS AE25
VSS AF6
Signal Ball #
VSS AF21
VTT H20
VTT J20
VTT K20
VTT U20
VTT V20
VTT W20
WBF# D13
154 Datasheet
6.2. Package Information
This specification outlines the mechanical dimensions for the 82840 MCH. The package is a 544 ball
grid array (BGA).
Figure 13. 82840 MCH BGA Package Dimensions (Top and Side Views)
Pin A1 I.D.
Pin A1 corner
D
D1
EE1
Top View
AA2
A1
c
Side View
pkgbga_top&side.vsd
Seating Plane
-C-
45° Chamfer
(4 places)
30°
82840 MCH
R
Datasheet 155
Figure 14. 82840 MCH BGA Package Dimensions (Bottom View)
pkgbga_544
Pin A1 corner
e
544 BGA
Bottom View
210162022 35791113151719 1
21
23 4618 81214
A
B
C
D
E
F
G
H
J
K
L
P
R
T
U
V
Y
AB
AA
AC
N
W
M
j
le
b
24
25
26
AD
AE
AF
Table 29. Package Dimensions
Symbol Min Nominal Max Units Note
A 2.17 2.38 2.59 mm
A1 0.50 0.60 0.70 mm
A2 1.12 1.17 1.22 mm
D 34.80 35.00 35.20 mm
D1 29.75 30.00 30.25 mm
E 34.80 35.00 35.20 mm
E1 29.75 30.00 30.25 mm
e 1.27 (solder bal l pi tch) m m
I 1.63 REF. mm
J 1.63 REF. mm
M 26 x 26 Matrix mm
b2 0.60 0.75 0.90 mm
c 0.55 0.61 0.67 mm
NOTES:
1. All dimensions and tolerances conform to ANS I Y14.5-1982
2. Dimension is measured at maximum solder bal l di ameter parall el to prim ary dat um (-C-)
3. Prim ary Datum (-C-) and seating plane are def i ned by t he spherical crowns of the sol der bal l s.
156 Datasheet
6.2.1. 82840 RSL Nomalized Trace Length Data
Expansion Channel A
∆
∆∆
∆LPKG Normalized to CHA_DQA8
Expansion Channel B
∆
∆∆
∆LPKG Normalized to CHB_DQB7
Signal Ball
∆
∆∆
∆LPKG (mils) Signal Ball ∆
∆∆
∆LPKG (mils)
CHA_CFM L1 102.756 CHB_CFM AF11 103.543
CHA_ CFM# L2 118.897 CHB _ CFM# AE11 110.630
CHA_CTM M2 130.315 CHB_CTM AE12 109.842
CHA_CTM# M1 117.716 CHB_CTM# AF12 110.236
CHA_DQA0 K1 93.701 CHB_DQA0 AF10 101.968
CHA_ DQA1 K3 162.204 CHB_ DQA1 AD10 150. 393
CHA_ DQA2 J1 40.551 CHB_ DQA 2 AF9 81.102
CHA_ DQA3 J3 137.008 CHB_ DQA3 AD9 137.401
CHA_ DQA4 J2 87.795 CHB_ DQA 4 AE9 115.354
CHA_ DQA5 H3 115.748 CHB_ DQA5 A D8 120.079
CHA_ DQA6 H1 61.811 CHB_ DQA6 AF8 48.425
CHA_ DQA7 G3 99.212 CHB_ DQA7 AD7 109.055
CHA_DQA8 G1 0.000 CHB_DQA8 AF7 29.921
CHA_DQB0 U3 143.307 CHB_DQB0 AD17 130.708
CHA_ DQB1 U1 122.441 CHB_ DQB1 AF17 72.441
CHA_ DQB2 V3 164.173 CHB_ DQB2 AD18 120. 079
CHA_ DQB3 V1 111.417 CHB_ DQB3 AF 18 69.291
CHA_ DQB4 W3 151. 181 CHB _ DQB 4 AD19 142.126
CHA_ DQB5 W1 68.504 CHB_ DQB5 AF 19 34.252
CHA_ DQB6 V2 106.693 CHB_ DQB6 A E18 111.417
CHA_ DQB7 Y1 40.157 CHB_ DQB7 AF20 0.000
CHA_ DQB8 Y3 134.252 CHB_ DQB8 AD20 70.472
CHA_EXP0 P3 192.519 CHB_EXP0 AD14 160.236
CHA_EXP1 P2 129.921 CHB_EXP1 AE14 161.811
CHA_RQ0 T3 185.433 CHB_RQ0 AD16 152.362
CHA_ RQ1 T2 131. 496 CHB_ RQ1 AE16 93.307
CHA_ RQ2 T1 126. 378 CHB_ RQ2 A F 16 98.425
CHA_ RQ3 R3 189.370 CHB_ RQ3 AD15 157.480
CHA_ RQ4 R1 85.039 CHB_ RQ4 A F 15 106.693
CHA_ RQ5 P1 78.740 CHB_ RQ5 A F 14 101.968
CHA_ RQ6 N1 124.409 CHB_ RQ6 AF13 112.205
CHA_ RQ7 N3 175.984 CHB_ RQ7 AD13 161.811
82840 MCH
R
Datasheet 157
These lengths must be considered when matching trace lengths as described in the Intel ® 840 Chipset
Design Guide . Note that these lengths are normalized to 0 with the longest trace on the package. They do
not represent the actual lengths from pad to ball. The following formula is used to determine ∆LPCB
∆LPCB = (∆Lpkg*Vpkg) / VPCB
Where:
∆LPCB is the nominal ∆ PCB trace length to be added on the PCB
∆LPkg is the nominal ∆ package trace length.
Vpkg is the package trace velocity, and the nominal value is 180 ps/in
VPCB is the PCB trace velocity
The dat a given can be renormalized to start routi ng from a differe nt ball. If a different RSL signa l (other
than longest trace) is used for nominalization, simply use the following equation:
New ∆Lpkg' = ∆Lpkg - ∆LRSL
For example: For the MCH, if MCH CHA_CFM trace length is used for nominalization, then:
Signal ∆
∆∆
∆LPKG (mils) New ∆
∆∆
∆LPKG (mils)
CHA_CFM 102.756 0.000
CHA_CFM# 118.897 16.142
CHA_CTM 130.315 27.559
: : :
: : :
CHA_RQ6 124.409 21.653
CHA_RQ7 175.984 73.228
158 Datasheet
This page is intentionally left blank.
82840 MCH
R
Datasheet 159
7. Testability
In the MCH, the testability for Automated Test Equipment (ATE) board level testing has been changed
from traditional NAND chain to the new XOR chain. An XOR-Tree is a chain of XOR gates, each with
one Input pin connected to it as shown in Figure 15. The first XOR gate should have one pin connected
to VCC1_8.
Figure 15. XOR-Tree Chain
Input
XOR
Out
xor.vsd
Input Input Input Input
VCC1_8
The algorithm used for in-circuit test is as follows:
• Drive “0” onto all Input pins. This, along with the first XOR gate having one input connected to
VCC1_8 and the Outputs being non-inverting, consistently produces a “1” at “XOR out”, regardless
of how many XOR gates are in the chain.
• Drive each Input pin one at a time, first to a “1” and then back to a “0”. This causes “XOR out” first
to produce a “0” and then a “1”.
• The Output pins can now be checked by driving a “0” onto the Pin of the XOR gate that has its
second input to the XOR gate connected to GND and then back to a “1”. The Output pins will go to
a “0” and then back to a “1”.
The above algorithm is for all pins properly soldered to the board under test and no pins connected to a
power plane. If there is an even number of total signal pins connected to a power plane or unsoldered and
floating to a “1” logic level, then the following would happen:
• Drive “0” onto all other Input and Bi-directional pins. “XOR out” would start out at a “1” level
instead of a “0”.
• Drive each Input or Bi-directional pin, one at a time, first to a “1” and then back to a “0.” This
causes “XOR out” first to produce a “0” and then a “1”.
A flexible test model used for in-circuit test will need to determine if “XOR out” initially is a “0” or “1”
level. One at a time, each Input or Bi-directional pin is driven to “1” and then back to a “0.” T he “XOR
out” will first toggle to the opposite state that was initially determined and then toggle back to the
initially determined state. Any unsoldered pin will cause “XOR out” not to toggle.
160 Datasheet
7.1. Initialization Sequence
Two pins are used to enter the XOR chain test mode as shown in the Figure 16.
XOR Chain Test Mode Enter ing Rules:
• TEST # should be driven “Low” for exactly 7 clocks after “RSTIN#” goes “High” (inactive).
• Once TEST # is driven “Low” for exactly 7 clocks and then “High”, it will “LOCK” in the XOR
chain test mode.
• TEST # should never be driven in the “Low” state other than driven “Low” for 7 clocks to enter the
XOR chain test mode. If TE ST# goes “Low” for a moment because of a glitch, the MCH needs to
be “reset” for going to normal operation or entering the XOR chain test mode again.
Figure 16. XOR Chain Test Mode Initialization
CLK66
RSTIN#
any number of
clocks between
16 and 64
1234 657
TEST#
minimum
10 clocks Exactly 7
clocks
"Lock" in the
XOR Chain
Test Mode
To Enter The XOR Chain Test Mode, Drive TEST# LOW for
EXACTLY 7 CLK66 Clocks After RSTIN# Is High (inactive).
test_init
82840 MCH
R
Datasheet 161
7.2. XOR Chains
Table 30. XOR Chain #0 Connections
Name Ball Chain
Element # Note
GC/BE1# D5 1 Input
GSERR# F6 2
GAD_15 E5 3
GC/BE0# B3 4
GAD_11 D4 5
GAD_14 F5 6
GAD_7 B2 7
GAD_10 E4 8
GAD_13 G5 9
GAD_6 C2 10
ADSTB0 D3 11
GAD_2 C1 12
GAD_5 E2 13
GAD_1 D1 14
GAD_4 F2 15
GAD_0 E1 16
GAD_9 F4 17
GAD_8 A3 18
GAD_12 B4 19
GAD_3 B1 20
CHA_SIO AB2 21
CHA_CMD AA4 22
CHA_SCK AA5 23
HCLKOUTA AB3 24
RCLKOUTA AB1 25
HLA11 AC3 26
HLA8 AD1 27
HLA3 AC1 28
HLA0 AB4 29
HLA6 AE1 30
HLA2 AC4 31
HLASTB AD3 32
HLASTB# AD2 33
HLA7 AF1 34
HLA1 AC5 35
HLA5 AF2 36
Table 30. XOR Chain #0 Connections
Name Ball Chain
Element # Note
HLA4 AE4 37
HLA10 AE3 38
HLAZCOMP AF4 39
HLA9 AE5 40
TEST# AC6 41
OVERT# AA6 42
HCLKOUTB AD5 43
RCLKOUTB AF5 44 Output
Table 31. XOR Chain #1 Connections
Name Ball Chain
Element # Note
ADSTB0# E3 1 Input
CHB_SCK AB21 2
CHB_CMD AC21 3
CHB_SIO AE22 4
RS1# AF23 5
DBSY# AD22 6
BREQ0# AF24 7
RSP# AE24 8
AP0# AF25 9
RS0# AD23 10
RP# AD26 11
ADS# AE26 12
HIT# AD24 13
HREQ3# AC23 14
RS2# AD25 15
DRDY# AC24 16
DEFER# AB22 17
HITM# AC26 18
HREQ1# AB23 19
BNR# AA21 20
HREQ4# AB24 21
BPRI# AA22 22
AP1# AF26 23 Output
162 Datasheet
Table 32. XOR Chain #2 Connections
Name Ball Chain
Element # Note
HA3# AA23 1 Input
HLOCK# AB25 2
HA6# AA24 3
HREQ2# AB26 4
HA4# Y23 5
HREQ0# AA25 6
HA8# Y24 7
HTRDY# AA26 8
HA5# W23 9
HA17# W24 10
HA11# W25 11
HA7# Y26 12
HA13# V23 13
HA21# V24 14
HA12# W26 15
HA9# Y21 16
HA14# W21 17
HA25# V25 18
HA19# U23 19
HA10# W22 20
HA15# V26 21
HA18# V21 22
HA28# U24 23
HA20# U26 24
HA22# T23 25
HA16# V22 26
HA26# T25 27
HA29# T24 28
HA24# T26 29
HD0# R23 30
HD2# P24 31
CPURST# R24 32
HA23# U21 33
HA35# R25 34
HA32# R26 35
HA31# T21 36
HA33# P26 37
HD4# P23 38
HD1# N26 39
Table 32. XOR Chain #2 Connections
Name Ball Chain
Element # Note
HA27# T22 40
HD6# N25 41
HD7# N24 42
HD12# N23 43
HA34# R21 44
HA30# R22 45
HD8# M26 46
HD19# L23 47
HD15# M25 48
HD17# M24 49
BERR# P21 50
HD10# L26 51
HD20# M23 52
HD3# N22 53
HD13# K26 54
HD18# L24 55
HD5# N21 56
HD22# K25 57
HD23# J26 58
SBSTB D12 59
ADSTB1 C9 60 Output
Table 33. XOR Chain #3 Connections
Name Ball Chain
Element # Note
HD25# K24 1 Input
HD9# M22 2
HD29# J25 3
HD30# H26 4
HD14# M21 5
HD26# K23 6
HD28# J24 7
HD11# L21 8
HD35# G26 9
HD40# G25 10
HD43# F26 11
HD47# F25 12
HD16# K22 13
HD21# K21 14
82840 MCH
R
Datasheet 163
Table 33. XOR Chain #3 Connections
Name Ball Chain
Element # Note
HD41# F24 15
HD32# J23 16
HD24# J22 17
HD27# J21 18
HD38# H24 19
HD36# G24 20
HD42# E26 21
HD34# H23 22
HD46# D26 23
HD54# D25 24
HD31# H21 25
HD48# E24 26
HD50# D24 27
HD44# G23 28
HD55# C26 29
HD59# E23 30
HD56# D23 31
HD63# C25 32
HD33# G22 33
HD37# G21 34
HD58# C24 35
DEP5# B26 36
HD52# F22 37
HD62# C23 38
HD51# E22 39
DEP7# B24 40
DEP0# A26 41
DEP4# A25 42
DEP2# A24 43
HD39# F21 44
HD57# D22 45
DEP3# B23 46
HD45# F20 47
HD53# D21 48
HD61# C21 49
HD49# E20 50
DEP1# B21 51
HD60# D20 52
DEP6# C20 53
IERR# A20 54 Output
Table 34. XOR Chain #4 Connections
Name Ball Chain
Element # Note
HLBZCOMP A19 1 Input
HLB15 F19 2
HLB14 D19 3
HLB13 C19 4
HLB12 F18 5
HLBSTB1 E18 6
HLBSTB1# D18 7
HLB11 C18 8
HLB10 B18 9
HLB9 A18 10
HLB8 F17 11
HLB16 D17 12
HLB19 C17 13
HLB17 A17 14
HLB18 F16 15
HLB7 E16 16
HLB6 D16 17
HLB5 C16 18
HLB4 B16 19
HLBSTB0 A16 20
HLBSTB0# A15 21
HLB3 F15 22
HLB2 D15 23
HLB1 C15 24
HLB0 F14 25
GREQ# A14 26
GGNT# B14 27
ST_0 C14 28
ST_1 D14 29
ST_2 E14 30
RBF# A13 31
PIPE# B13 32
WBF# D13 33
SBSTB# C11 34
GAD_30 A10 35
GAD_25 A9 36
GAD_29 C10 37
GAD_24 B9 38
GC/BE3# A8 39
164 Datasheet
Table 34. XOR Chain #4 Connections
Name Ball Chain
Element # Note
GAD_28 D10 40
GAD_21 B8 41
GAD_31 F11 42
GAD_27 E10 43
ADSTB1# D9 44
GAD_17 A7 45
GAD_26 F10 46
GAD_22 D8 47
GAD_18 C7 48
GC/BE2# D7 49
GAD_19 E8 50
GAD_23 F9 51
GAD_16 E7 52
GAD_20 F8 53
GFRAME# A6 54
GDEVSEL# B6 55
GPAR C5 56
GTRDY# C6 57
GSTOP# D6 58
GIRDY# F7 59 Output
Table 35. XOR Chain #5 Connections
Name Ball Chain
Element # Note
CHA_DQA8 G1 1 Input
CHA_DQA7 G3 2
CHA_DQA6 H1 3
CHA_DQA5 H3 4
CHA_DQA4 J2 5
CHA_DQA3 J3 6
CHA_DQA2 J1 7
CHA_DQA1 K3 8
CHA_DQA0 K1 9
CHA_CFM L1 10
CHA_CFM# L2 11
CHA_EXP0 P3 12
CHA_EXP1 P2 13
CHA_RQ7 N3 14
CHA_RQ6 N1 15
Table 35. XOR Chain #5 Connections
Name Ball Chain
Element # Note
CHA_RQ5 P1 16
CHA_RQ4 R1 17
CHA_RQ3 R3 18
CHA_RQ2 T1 19
CHA_RQ1 T2 20
CHA_RQ0 T3 21
CHA_DQB0 U3 22
CHA_DQB1 U1 23
CHA_DQB2 V3 24
CHA_DQB3 V1 25
CHA_DQB4 W3 26
CHA_DQB5 W1 27
CHA_DQB6 V2 28
CHA_DQB7 Y1 29
CHA_DQB8 Y3 30
SBA_5 B11 31 Output
Table 36. XOR Chain #6 Connections
Name Ball Chain
Element # Note
CHB_DQA8 AF7 1 Input
CHB_DQA7 AD7 2
CHB_DQA6 AF8 3
CHB_DQA5 AD8 4
CHB_DQA4 AE9 5
CHB_DQA3 AD9 6
CHB_DQA2 AF9 7
CHB_DQA1 AD10 8
CHB_DQA0 AF10 9
CHB_CFM AF11 10
CHB_CFM# AE11 11
CHB_EXP0 AD14 12
CHB_EXP1 AE14 13
CHB_RQ7 AD13 14
CHB_RQ6 AF13 15
CHB_RQ5 AF14 16
CHB_RQ4 AF15 17
CHB_RQ3 AD15 18
CHB_RQ2 AF16 19
82840 MCH
R
Datasheet 165
Table 36. XOR Chain #6 Connections
Name Ball Chain
Element # Note
CHB_RQ1 AE16 20
CHB_RQ0 AD16 21
CHB_DQB0 AD17 22
CHB_DQB1 AF17 23
CHB_DQB2 AD18 24
CHB_DQB3 AF18 25
CHB_DQB4 AD19 26
CHB_DQB5 AF19 27
CHB_DQB6 AE18 28
CHB_DQB7 AF20 29
CHB_DQB8 AD20 30
SBA_7 E11 31 Output
Intel around the world
United States and Canada
Intel Corporation
Robert Noyce Building
2200 Mission College Boulevard
P.O. Box 58119
Santa Clara, CA 95052-8119
USA
Phone: (800) 628-8686
Europe
Intel Corporation (U.K.) Ltd.
Pipers Way
Swindon
Wiltshire SN3 1RJ
UK
Phone:
England (44) 1793 403 000
Germany (49) 89 99143 0
France (33) 1 4571 7171
Italy (39) 2 575 441
Israel (972) 2 589 7111
Netherlands (31) 10 286 6111
Sweden (46) 8 705 5600
Asia Pacific
Intel Semiconductor Ltd.
32/F Two Pacific Place
88 Queensway, Central
Hong Kong, SAR
Phone: (852) 2844 4555
Japan
Intel Kabushiki Kaisha
P.O. Box 115 Tsukuba-gakuen
5-6 Tokoda i , T sukuba-shi
Ibaraki-ken 305
Japan
Phone: (81) 298 47 8522
South America
Intel Semicondutores do Brazil
Rua Florida 1703-2 and CJ22
CEP 04565-001 Sao Paulo-SP
Brazil
Phone: (55) 11 5505 2296
For More Information
To learn more about Intel Corporation, visit our site
o n the Worl d Wide Web at www.intel.com
R
