CD74HC4046AM96E4 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS204J

Features

• Operating Frequency Range

- Up to 18MHz (Typ) at VCC = 5V

- Minimum Center Frequency of 12MHz at VCC = 4.5V

• Choice of Three Phase Comparators

- EXCLUSIVE-OR

- Edge-Triggered JK Flip-Flop

- Edge-Triggered RS Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

• Minimal Frequency Drift

• Operating P o wer Supply Voltage Range

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤ 1µA at VOL, VOH

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

Description

The ’HC4046A and ’HCT4046A are high-speed silicon-gate

CMOS devices that are pin compatible with the CD4046B of

the “4000B” series. They are specified in compliance with

JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop

circuits that contain a linear voltage-controlled oscillator

(VCO) and three different phase comparators (PC1, PC2 and

PC3). A signal input and a comparator input are common to

each comparator.

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to small

voltage signals. A self-bias input circuit keeps small voltage

signals within the linear region of the input amplifiers. With a

passive low-pass filter, the 4046A forms a second-order loop

PLL. The excellent VCO linearity is achieved by the use of

linear op-amp techniques.

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC4046AF3A -55 to 125 16 Ld CERDIP

CD54HCT4046AF3A -55 to 125 16 Ld CERDIP

CD74HC4046AE -55 to 125 16 Ld PDIP

CD74HC4046AM -55 to 125 16 Ld SOIC

CD74HC4046AMT -55 to 125 16 Ld SOIC

CD74HC4046AM96 -55 to 125 16 Ld SOIC

CD74HC4046ANSR -55 to 125 16 Ld SOP

CD74HC4046APWR -55 to 125 16 Ld TSSOP

CD74HC4046APWT -55 to 125 16 Ld TSSOP

CD74HCT4046AE -55 to 125 16 Ld PDIP

CD74HCT4046AM -55 to 125 16 Ld SOIC

CD74HCT4046AMT -55 to 125 16 Ld SOIC

CD74HCT4046AM96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

February 1998 - Revised December 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4046A, CD74HC4046A,

CD54HCT4046A, CD74HCT4046A

High-Speed CMOS Logic

Phase-Locked Loop with VCO

[ /Title

(CD74

HC404

6A,

CD74

HCT40

46A)

/Sub-

ject

(High-

Speed

CMOS

Pinout CD54HC4046A, CD54HCT4046A (CERDIP)

CD74HC4046A (PDIP, SOIC, SOP, TSSOP)

CD74HCT4046A (PDIP, SOIC)

TOP VIEW

Functional Diagram

PCPOUT

PC1OUT

COMPIN

VCOOUT

INH

C1A

GND

C1B

VCC

SIGIN

PC2OUT

DEMOUT

VCOIN

PC3OUT

4VCO

OUT

DEM

OUT

VCO

INH

2PC1

OUT

PC3

OUT

PC2

OUT

PCP

OUT

COMP

SIG

VCO

Pin Descriptions

PIN NUMBER SYMBOL NAME AND FUNCTION

1 PCPOUT Phase Comparator Pulse Output

2 PC1OUT Phase Comparator 1 Output

3 COMPIN Comparator Input

4 VCOOUT VCO Output

5 INH Inhibit Input

6C1

ACapacitor C1 Connection A

7C1

BCapacitor C1 Connection B

8 GND Ground (0V)

9 VCOIN VCO Input

10 DEMOUT Demodulator Output

11 R1Resistor R1 Connection

12 R2Resistor R2 Connection

13 PC2OUT Phase Comparator 2 Output

14 SIGIN Signal Input

15 PC3OUT Phase Comparator 3 Output

16 VCC Positive Supply Voltage

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

General Description

VCO

The VCO requires one external capacitor C1 (between C1A

and C1B) and one external resistor R1 (between R1and

GND) or two external resistors R1 and R2 (between R1and

GND, and R2and GND). Resistor R1 and capacitor C1

determine the frequency range of the VCO. Resistor R2

enables the VCO to have a frequency offset if required. See

logic diagram, Figure 1.

The high input impedance of the VCO simpliﬁes the design

of low-pass ﬁlters by giving the designer a wide choice of

resistor/capacitor ranges. In order not to load the low-pass

ﬁlter, a demodulator output of the VCO input voltage is

provided at pin 10 (DEMOUT). In contrast to conventional

techniques where the DEMOUT voltage is one threshold

voltage lower than the VCO input voltage, here the DEMOUT

voltage equals that of the VCO input. If DEMOUT is used, a

load resistor (RS) should be connected from DEMOUT to

GND; if unused, DEMOUT should be left open. The VCO

output (VCOOUT) can be connected directly to the

comparator input (COMPIN), or connected via a frequency-

divider. The VCO output signal has a speciﬁed duty factor of

50%. A LOW level at the inhibit input (INH) enables the VCO

and demodulator, while a HIGH level turns both off to

minimize standby power consumption.

Phase Comparators

The signal input (SIGIN) can be directly coupled to the self-

biasing ampliﬁer at pin 14, provided that the signal swing is

between the standard HC family input logic levels.

Capacitive coupling is required for signals with smaller

swings.

Phase Comparator 1 (PC1)

This is an Exclusive-OR network. The signal and comparator

input frequencies (fi) must have a 50% duty factor to obtain

the maximum locking range. The transfer characteristic of

PC1, assuming ripple (fr = 2fi) is suppressed, is:

VDEMOUT =(V

CC/π)(φSIGIN -φCOMPIN) where VDEMOUT

is the demodulator output at pin 10; VDEMOUT =V

PC1OUT

(via low-pass ﬁlter).

The average output voltage from PC1, fed to the VCO input

via the low-pass ﬁlter and seen at the demodulator output at

pin 10 (V

DEMOUT

), is the resultant of the phase differences

of signals (SIG

) and the comparator input (COMP

)as

shown in Figure 2. The average of V

DEM

is equal to 1/2

when there is no signal or noise at SIG

, and with this

input the VCO oscillates at the center frequency (f

Typical waveforms for the PC1 loop locked at f

are shown

in Figure 3.

FIGURE 1. LOGIC DIAGRAM

DEMOUT

PC2OUT 13

GND

VCC

PCPOUT

PC3OUT

PC1OUT

DOWN

VCC

INH

VCOIN

VCO

VCOOUT

COMPIN

SIGIN

C1B

C1A

VREF

674314

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

The frequency capture range (2fC) is deﬁned as the

frequency range of input signals on which the PLL will lock if

it was initially out-of-lock. The frequency lock range (2fL)is

deﬁned as the frequency range of input signals on which the

loop will stay locked if it was initially in lock. The capture

range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass ﬁlter

characteristics and can be made as large as the lock range.

This conﬁguration retains lock behavior even with very noisy

input signals. Typical of this type of phase comparator is that

it can lock to input frequencies close to the harmonics of the

VCO center frequency.

Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency

detector. When the PLL is using this comparator, the loop

is controlled by positive signal transitions and the duty

factors of SIG

and COMP

are not important. PC2

comprises two D-type ﬂip-ﬂops, control-gating and a three-

state output stage. The circuit functions as an up-down

counter (Figure 1) where SIG

causes an up-count and

COMP

a down-count. The transfer function of PC2,

assuming ripple (f

= f

) is suppressed, is:

VDEMOUT =(V

CC/4π)(φSIGIN -φCOMPIN) where

VDEMOUT is the demodulator output at pin 10;

VDEMOUT =V

PC2OUT (via low-pass ﬁlter).

The average output voltage from PC2, fed to the VCO via the

low-pass ﬁlter and seen at the demodulator output at pin 10

(VDEMOUT), is the resultant of the phase differences of

SIGIN and COMPIN as shown in Figure 4. Typical waveforms

for the PC2 loop locked at fo are shown in Figure 5.

When the frequencies of SIGIN and COMPIN are equal but

the phase of SIGIN leads that of COMPIN, the p-type output

driver at PC2OUT is held “ON” for a time corresponding to

the phase difference (φDEMOUT). When the phase of SIGIN

lags that of COMPIN, the n-type driver is held “ON”.

When the frequency of SIG

is higher than that of

COMP

, the p-type output driver is held “ON” for most of

the input signal cycle time, and for the remainder of the

cycle both n- and p-type drivers are “OFF” (three-state). If

the SIG

frequency is lower than the COMP

frequency,

then it is the n-type driver that is held “ON” for most of the

cycle. Subsequently, the voltage at the capacitor (C2) of

the low-pass ﬁlter connected to PC2

OUT

varies until the

signal and comparator inputs are equal in both phase and

FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN -

φCOMPIN); φDEMOUT =(φSIGIN - φCOMPIN)

VCC

VDEMOUT (AV)

1/2 VCC

0o90oφDEMOUT 180o

FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 1, LOOP LOCKED AT fo

SIGIN

COMPIN

VCOOUT

PC1OUT

VCOIN

VCC

GND

FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

VDEMOUT = VPC2OUT

= (VCC/4π) (φSIGIN - φCOMPIN);

φDEMOUT =(φSIGIN - φCOMPIN)

VCC

VDEMOUT (AV)

1/2 VCC

-360o0oφDEMOUT 360o

FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 2, LOOP LOCKED AT fo

SIGIN

COMPIN

VCOOUT

PC2OUT

VCOIN

VCC

GND

PCPOUT

HIGH IMPEDANCE OFF - STATE

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

frequency. At this stable point the voltage on C2 remains

constant as the PC2 output is in three-state and the VCO

input at pin 9 is a high impedance. Also in this condition,

the signal at the phase comparator pulse output (PCP

OUT

)

is a HIGH level and so can be used for indicating a locked

condition.

Thus, for PC2, no phase difference exists between SIGIN

and COMPIN over the full frequency range of the VCO.

Moreover, the power dissipation due to the low-pass ﬁlter is

reduced because both p- and n-type drivers are “OFF” for

most of the signal input cycle. It should be noted that the

PLL lock range for this type of phase comparator is equal to

the capture range and is independent of the low-pass ﬁlter.

With no signal present at SIGIN, the VCO adjusts, via PC2,

to its lowest frequency.

Phase Comparator 3 (PC3)

This is a positive edge-triggered sequential phase

detector using an RS-type flip-flop. When the PLL is using

this comparator, the loop is controlled by positive signal

transitions and the duty factors of SIGIN and COMPIN are

not important. The transfer characteristic of PC3,

assuming ripple (fr = fi) is suppressed, is:

VDEMOUT =(V

CC/2p) (fSIGIN - fCOMPIN) where

VDEMOUT is the demodulator output at pin 10; VDEMOUT

= VPC3OUT (via low-pass filter).

The average output from PC3, fed to the VCO via the low-

pass filter and seen at the demodulator at pin 10

(VDEMOUT), is the resultant of the phase differences of

SIGIN and COMPIN as shown in Figure 6. Typical

waveforms for the PC3 loop locked at foare shown in

Figure 7.

The phase-to-output response characteristic of PC3

(Figure 6) differs from that of PC2 in that the phase angle

between SIGIN and COMPIN varies between 0oand 360o

and is 180oat the center frequency. Also PC3 gives a

greater voltage swing than PC2 for input phase differences

but as aconsequence the ripple content of the VCO input

signal is higher. With no signal present at SIGIN, the VCO

adjusts, via PC3, to its highest frequency.

The only difference between the HC and HCT versions is the

input level speciﬁcation of the INH input. This input disables

the VCO section. The comparator’s sections are identical, so

that there is no difference in the SIGIN (pin 14) or COMPIN

(pin 3) inputs between the HC and the HCT versions.

FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT

VOLTAGE vs INPUT PHASE DIFFERENCE:

VDEMOUT = VPC3OUT

= (VCC/2π) (φSIGIN - φCOMPIN);

φDEMOUT = (φSIGIN - φCOMPIN)

VCC

VDEMOUT (AV)

1/2 VCC

0o180oφDEMOUT 360o

FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE

COMPARATOR 3, LOOP LOCKED AT fo

SIGIN

COMPIN

VCOOUT

PC3OUT

VCOIN VCC

GND

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Package Thermal Impedance, θJA (see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

VCO SECTION

INH High Level Input

Voltage VIH - - 3 2.1 - - 2.1 - 2.1 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

INH Low Level Input

Voltage VIL - - 3 - - 0.9 - 0.9 - 0.9 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

VCOOUT High Level

Output Voltage

CMOS Loads

VOH VIH or VIL -0.02 3 2.9 - - 2.9 - 2.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

VCOOUT High Level

Output Voltage

TTL Loads

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VCOOUT Low Level

Output Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

VCOOUT Low Level

Output Voltage

TTL Loads

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

C1A, C1B Low Level

Output Voltage

(Test Purposes Only)

VOL VIL or VIH 4 4.5 - - 0.40 - 0.47 - 0.54 V

5.2 6 - - 0.40 - 0.47 - 0.54 V

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046ACD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

INH VCOIN Input

Leakage Current IIVCC or

GND -6--±0.1 - ±1-±1µA

R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ

R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ

C1 Capacitance

Range ---3--No

Limit ----pF

4.5 - - - - - - pF

6-- ----pF

VCOIN Operating

Voltage Range - Over the range

specified for R1 for

LinearitySeeFigure

10, and 34 - 37

(Note 3)

3 1.1 - 1.9 - - - - V

4.5 1.1 - 3.2 - - - - V

6 1.1 - 4.6 - - - - V

PHASE COMPARATOR SECTION

SIGIN, COMPIN

DC Coupled

High-Level Input

Voltage

VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

SIGIN, COMPIN

DC Coupled

Low-Level Input

Voltage

VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

PCPOUT, PCn OUT

High-Level Output

Voltage

CMOS Loads

VOH VIL or VIH -0.02 2 1.9 - - 1.9 - 1.9 - V

4.5 4.4 - - 4.4 - 4.4 - V

6 5.9 - - 5.9 - 5.9 - V

PCPOUT, PCn OUT

High-Level Output

Voltage

TTL Loads

VOH VIL or VIH -4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

PCPOUT, PCn OUT

Low-Level Output

Voltage

CMOS Loads

VOL VIL or VIH 0.02 2 - - 0.1 - 0.1 - 0.1 V

4.5 - - 0.1 - 0.1 - 0.1 V

6 - - 0.1 - 0.1 - 0.1 V

PCPOUT, PCn OUT

Low-Level Output

Voltage

TTL Loads

VOL VIL or VIH 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

SIGIN, COMPIN Input

Leakage Current IIVCC or

GND -2--±3-±4-±5µA

3--±7-±9-±11 µA

4.5 - - ±18 - ±23 - ±29 µA

6--±30 - ±38 - ±45 µA

PC2OUT Three-State

Off-State Current IOZ VIL or VIH -6--±0.5 - ±5-±10 µA

SIGIN, COMPIN Input

Resistance RIVI at Self-Bias

Operation Point:

∆VI = 0.5V,

See Figure 10

3 - 800 - - - - - kΩ

4.5 - 250 - - - - - kΩ

6 - 150 - - - - - kΩ

DEMODULATOR SECTION

Resistor Range RSat RS > 300kΩ

Leakage Current

Can Influence

VDEMOUT

3 50 - 300 - - - - kΩ

4.5 50 - 300 - - - - kΩ

6 50 - 300 - - - - kΩ

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

OffsetVoltageVCOIN

to VDEM VOFF VI = VVCO IN =

Values Taken Ov er

RS Range

See Figure 23

3-±30 - - - - - mV

4.5 - ±20 - - - - - mV

6-±10 - - - - - mV

Dynamic Output

Resistance at

DEMOUT

RDVDEMOUT =3-25-----Ω

4.5 - 25 - - - - - Ω

6 - 25 - - - - - Ω

Quiescent Device

Current ICC Pins 3, 5 and 14

at VCC Pin 9 at

GND, I1 at Pins 3

and 14 to be

excluded

6 - - 8 - 80 - 160 µA

HCT TYPES

VCO SECTION

INH High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

INH Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

VCOOUT High Level

Output Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

VCOOUT High Level

Output Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

VCOOUT Low Level

Output Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCOOUT Low Level

Output Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

C1A, C1B Low Level

Output Voltage

(Test Purposes Only)

VOL VIH or VIL 4 4.5 - - 0.40 - 0.47 - 0.54 V

INH VCOIN Input

Leakage Current IIAny Voltage

Between VCC and

GND

5.5 - ±0.1 - ±1-±1µA

R1 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ

R2 Range (Note 2) - - - 4.5 3 - 300 - - - - kΩ

C1 Capacitance

Range - - - 4.5 0 - No

Limit ----pF

VCOIN Operating

Voltage Range - Over the range

specified for R1 for

LinearitySeeFigure

10, and 34 - 37

(Note 3)

4.5 1.1 - 3.2 - - - - V

PHASE COMPARATOR SECTION

SIGIN, COMPIN

DC Coupled

High-Level Input

Voltage

VIH - - 4.5 to

5.5 2--2 - 2 - V

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

SIGIN, COMPIN

DC Coupled

Low-Level Input

Voltage

VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

PCPOUT, PCn OUT

High-Level Output

Voltage

CMOS Loads

VOH VIL or VIH - 4.5 4.4 - - 4.4 - 4.4 - V

PCPOUT, PCn OUT

High-Level Output

Voltage

TTL Loads

VOH VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V

PCPOUT, PCn OUT

Low-Level Output

Voltage

CMOS Loads

VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V

PCPOUT, PCn OUT

Low-Level Output

Voltage

TTL Loads

VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V

SIGIN, COMPIN Input

Leakage Current IIAny

Voltage

Between

VCC and

GND

- 5.5 - - ±30 ±38 ±45 µA

PC2OUT Three-State

Off-State Current IOZ VIL or VIH - 5.5 - - ±0.5 ±5- -±10 µA

SIGIN, COMPIN Input

Resistance RIVI at Self-Bias

Operation Point:

∆VI = 0.5V,

See Figure 10

4.5 - 250 - - - - - kΩ

DEMODULATOR SECTION

Resistor Range RSat RS > 300kΩ

Leakage Current

Can Influence

VDEM OUT

4.5 5 - 300 - - - - kΩ

OffsetVoltageVCOIN

to VDEM VOFF VI = VVCO IN =

Values taken ov er

RS Range

See Figure 23

4.5 - ±20 - - - - - mV

Dynamic Output

Resistance at

DEMOUT

RDVDEM OUT = 4.5 - 25 - - - - - Ω

Quiescent Device

Current ICC VCC or

GND - 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC

(Note 4) VCC

-2.1

Excluding

Pin 5

- 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTES:

2. The value for R1 and R2 in parallel should exceed 2.7kΩ.

3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

HCT Input Loading Table

INPUT UNIT LOADS

INH 1

NOTE: Unit load is ∆ICC limit speciﬁc in DC Electrical Speciﬁcations

Table, e.g., 360µA max. at 25oC.

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

PHASE COMPARATOR SECTION

Propagation Delay tPLH, tPHL

SIGIN, COMPIN to PCIOUT 2 - - 200 - 250 - 300 ns

4.5 - - 40 - 50 - 60 ns

6 - - 34 - 43 - 51 ns

SIGIN, COMPIN to PCPOUT 2 - - 300 - 375 - 450 ns

4.5 - - 60 - 75 - 90 ns

6 - - 51 - 64 - 77 ns

SIGIN, COMPIN to PC3OUT 2 - - 245 - 305 - 307 ns

4.5 - - 49 - 61 - 74 ns

6 - - 42 - 52 - 63 ns

Output Transition Time tTHL, tTLH 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Output Enable Time, SIGIN,

COMPIN to PC2OUT tPZH, tPZL 2 - - 265 - 330 - 400 ns

4.5 - - 53 - 66 - 80 ns

6 - - 45 - 56 - 68 ns

Output Disable Time, SIGIN,

COMPIN to PC2OUT tPHZ, tPLZ 2 - - 315 - 395 - 475 ns

4.5 - - 63 - 79 - 95 ns

6 - - 54 - 67 - 81 ns

AC Coupled Input Sensitivity

(P-P) at SIGIN or COMPIN VI(P-P) 3 - 11 - - - - - mV

4.5 - 15 - - - - - mV

6 - 33 - - - - - mV

VCO SECTION

Frequency Stability with

Temperature Change ∆f

∆TR1 = 100kΩ,

R2 = ∞3 - 0.11 - - - - - %/oC

4.5 - 0.11 - - - - - %/oC

6 - 0.11 - - - - - %/oC

Maximum Frequency fMAX C1 = 50pF

R1 = 3.5kΩ

R2 = ∞

3 - 24 - - - - - MHz

4.5 - 24 - - - - - MHz

6 - 24 - - - - - MHz

C1 = 0pF

R1 = 9.1kΩ

R2 = ∞

3 - 38 - - - - - MHz

4.5 - 38 - - - - - MHz

6 - 38 - - - - - MHz

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

Center Frequency C1 = 40pF

R1 = 3kΩ

R2 = ∞

VCOIN =

VCC/2

3 7 10 - - - - - MHz

4.5 12 17 - - - - - MHz

6 14 21 - - - - - MHz

Frequency Linearity ∆fVCO R1 = 100kΩ

R2 = ∞

C1 = 100pF

3 - 0.4 - - - - - %

4.5 - 0.4 - - - - - %

6 - 0.4 - - - - - %

Offset Frequency R2 = 220kΩ

C1 = 1nF 3 - 400 - - - - - kHz

4.5 - 400 - - - - - kHz

6 - 400 - - - - - kHz

DEMODULATOR SECTION

VOUT VS fIN R1 = 100kΩ

R2 = ∞

C1 = 100pF

RS = 10kΩ

R3 = 100kΩ

C2 = 100pF

3 - - - - - - - mV/kHz

4.5 - 330 - - - - - mV/kHz

6 - - - - - - - mV/kHz

HCT TYPES

PHASE COMPARATOR SECTION

Propagation Delay tPHL, tPLH

SIGIN, COMPIN to PCIOUT CL = 50pF 4.5 - - 45 - 56 - 68 ns

SIGIN, COMPIN to PCPOUT tPHL, tPLH CL = 50pF 4.5 - - 68 - 85 - 102 ns

SIGIN, COMPIN to PC3OUT tPHL, tPLH CL = 50pF 4.5 - - 58 - 73 - 87 ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns

Output Enable Time, SIGIN,

COMPIN to PC2OUT tPZH, tPZL CL = 50pF 4.5 - - 60 - 75 - 90 pF

Output Disable Time, SIGIN,

COMPIN to PCZOUT tPHZ, tPLZ CL = 50pF 4.5 - - 68 - 85 - 102 pF

AC Coupled Input Sensitivity

(P-P) at SIGIN or COMPIVI(P-P) 4.5 - 15 - - - - - mV

VCO SECTION

Frequency Stability with

Temperature Change ∆f

∆TR1 = 100kΩ,

R2 = ∞4.5 - 0.11 - - - - - %/oC

Maximum Frequency fMAX C1 = 50pF

R1 = 3.5kΩ

R2 = ∞

4.5 - 24 - - - - - MHz

C1 = 0pF

R1 = 9.1kΩ

R2 = ∞

4.5 - 38 - - - - - MHz

Center Frequency C1 = 40pF

R1 = 3kΩ

R2 = ∞

VCOIN =

VCC/2

4.5 12 17 - - - - - MHz

Frequency Linearity ∆fVCO R1 = 100kΩ

R2 = ∞

C1 = 100pF

4.5 - 0.4 - - - - - %

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

Offset Frequency R2 = 220kΩ

C1 = 1nF 4.5 - 400 - - - - - kHz

DEMODULATOR SECTION

VOUT VS fIN R1 = 100kΩ

R2 = ∞

C1 = 100pF

RS = 10kΩ

R3 = 100kΩ

C2 = 100pF

4.5 - 330 - - - - - mV/kHz

Switching Speciﬁcations CL = 50pF, Input tr, tf= 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC-40oC TO

85oC-55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 8. INPUT TO OUTPUT PROPAGATION DELAYS AND

OUTPUT TRANSITION TIMES FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR

PC2OUT

tPHL tPHL

tTLH

SIGIN COMPIN

INPUTS

PCPOUT PC1OUT

PC3OUT OUTPUTS

SIGIN

tPZH

90%

INPUTS

COMPIN

INPUTS

PC2OUT

OUTPUT

tPZL tPZL

10%

Typical Performance Curves

FIGURE 10. TYPICAL INPUT RESISTANCE CURVE AT SIGIN,

COMPIN

∆VI

SELF-BIAS OPERATING POINT

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 11. HC4046A TYPICAL CENTER FREQUENCY vs R1,

C1 (VCC = 4.5V) FIGURE 12. HC4046A TYPICAL CENTER FREQUENCY vs R1,

C1 (VCC = 6V)

FIGURE 13. HC4046A TYPICAL CENTER FREQUENCY vs R1,

C1 (VCC = 3V, R2 = OPEN) FIGURE 14. HCT4046A TYPICAL CENTER FREQUENCY vs R1,

C1 (VCC = 4.5V)

FIGURE 15. HCT4046A TYPICAL CENTER FREQUENCY vs R1,

C1 (VCC = 5.5V) FIGURE 16. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 1.5MΩ, C1 = 50pF)

Typical Performance Curves (Continued)

108

107

106

105

104

103

102

1110102103104105106

CAPACITANCE, C1 (pF)

CENTER FREQUENCY (Hz)

VCOIN = 0.5 VCC

VCC = 4.5V

R1 = 2.2K

R1 = 22K

R1 = 220K

R1 = 2.2M

R1 = 11M

108

107

106

105

104

103

102

1110102103104105106

CAPACITANCE, C1 (pF)

CENTER FREQUENCY (Hz)

VCOIN = 0.5 VCC

VCC = 6.0V

R1 =3K

R1 = 30K

R1 =330K

R1 = 3M

R1 = 15M

108

107

106

105

104

103

102

1110102103104105106

CAPACITANCE, C1 (pF)

CENTER FREQUENCY (Hz)

VCOIN = 0.5 VCC

VCC = 3.0V

R2 = OPEN

R1 = 1.5K

R1 = 15K

R1 = 150K

R1 = 1.5M

R1 = 7.5M

108

107

106

105

104

103

102

1110102103104105106

CAPACITANCE, C1 (pF)

CENTER FREQUENCY (Hz)

VCOIN = 0.5 VCC

VCC = 4.5V

R1 = 2.2K

R1 = 22K

R1 = 220K

R1 = 2.2M

R1 = 11M

108

107

106

105

104

103

102

1110102103104105106

CAPACITANCE, C1 (pF)

CENTER FREQUENCY (Hz)

VCOIN = 0.5 VCC

VCC = 5.5V

R1 = 3K

R1 = 30K

R1 = 300K

R1 = 3M

R1 = 15M

140

120

100

20 01 2 3 456

VCOIN (V)

VCO FREQUENCY (kHz)

C1 = 50pF

R1 = 1.5M

VCC = 3V

VCC = 4.5V

VCC = 6V

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 17. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 1.5MΩ, C1 = 0.1µF) FIGURE 18. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 150kΩ, C1 = 0.1µF)

FIGURE 19. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 5.6kΩ, C1 = 0.1µF) FIGURE 20. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 150kΩ, C1 = 50pF)

FIGURE 21. HC4046A TYPICAL VCO FREQUENCY vs VCOIN

(R1 = 5.6kΩ, C1 = 50pF) FIGURE 22. HC4046A TYPICAL CHANGE IN VCO FREQUENCY

vs AMBIENT TEMPERATURE AS A FUNCTION OF

R1 (VCC = 3V)

Typical Performance Curves (Continued)

10 01 2 3 45 6

VCOIN (V)

VCO FREQUENCY (Hz)

C1 = 0.1µF

R1 = 1.5M

VCC = 3V

VCC = 4.5V

VCC = 6V

800

600

500

400

300

200

100 01 2 3 45 6

VCOIN (V)

VCO FREQUENCY (Hz)

C1 = 0.1µF

R1 = 150K

VCC = 3V

VCC = 4.5V

VCC = 6V

700

201 2 3 45 6

VCOIN (V)

VCO FREQUENCY (kHz)

C1 = 0.1µF

R1 = 5.6k

VCC = 3V

VCC = 4.5V

VCC = 6V

1400

1000

800

600

400

200 01 2 3 45 6

VCOIN (V)

VCO FREQUENCY (kHz)

C1 = 50pF

R1 = 150K

VCC = 3V

VCC = 4.5V

VCC = 6V

1200

401 2 3 45 6

VCOIN (V)

VCO FREQUENCY (MHz)

C1 = 50pF

R1 = 5.6K

VCC = 3V

VCC = 4.5V

VCC = 6V

24 R1 = 1.5M

R1 = 150K

R1 = 3K

R1 = 1.5K

VCOIN = 0.5 VCC

C1 = 50pF, VCC = 3V

R2 = OPEN

-4

VCO FREQUENCY CHANGE, ∆f (%)

-75 -50 -25 0 25 50 75

AMBIENT TEMPERATURE, TA (oC)

100 125 150

-8

-12

-16

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 23. HC4046A TYPICAL CHANGE IN VCO FREQUENCY

vs AMBIENT TEMPERATURE AS A FUNCTION OF

R1 (VCC = 4.5V)

FIGURE 24. HC4046A TYPICAL CHANGE IN VCO FREQUENCY

vs AMBIENT TEMPERATURE AS A FUNCTION OF

R1 (VCC = 6V)

FIGURE 25. HCT4046A TYPICAL CHANGE IN VCO

FREQUENCY vs AMBIENT TEMPERATURE AS A

FUNCTION OF R1

FIGURE 26. HC4046A TYPICAL CHANGE IN VCO FREQUENCY

vs AMBIENT TEMPERATURE AS A FUNCTION OF

R1 (VCC = 4.5V)

Typical Performance Curves (Continued)

R1 = 2.2M

R1 = 220K

R1 = 2.2K

VCOIN = 0.5 VCC

C1 = 50pF, VCC = 4.5V

R2 = OPEN

VCO FREQUENCY CHANGE, ∆f (%)

-75 -50 -25 0 25 50 75

AMBIENT TEMPERATURE, TA (oC)

100 125 150

-4

-8

-12

R1 = 3M

R1 = 300K

R1 = 3K

VCOIN = 0.5 VCC

C1 = 50pF, VCC = 6.0V

R2 = OPEN

VCO FREQUENCY CHANGE, ∆f (%)

-75 -50 -25 0 25 50 75

AMBIENT TEMPERATURE, TA (oC)

100 125 150

-4

-8

-12

R1 = 3M

R1 = 300K

R1 = 3K

VCOIN = 0.5 VCC

C1 = 50pF, VCC = 5.5V

R2 = OPEN

VCO FREQUENCY CHANGE, ∆f (%)

-75 -50 -25 0 25 50 75

AMBIENT TEMPERATURE, TA (oC)

100 125 150

-4

-8

-12

R1 = 2.2M

R1 = 220K

R1 = 2.2K

VCOIN = 0.5 VCC

C1 = 50pF, VCC = 4.5V

R2 = OPEN

VCO FREQUENCY CHANGE, ∆f (%)

-75 -50 -25 0 25 50 75

AMBIENT TEMPERATURE, TA (oC)

100 125 150

-4

-8

-12

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 27. HC4046A OFFSET FREQUENCY vs R2, C1

(VCC = 4.5V) FIGURE 28. HC4046A OFFSET FREQUENCY vs R2, C1

(VCC = 3V)

FIGURE 29. HCT4046A OFFSET FREQUENCY vs R2, C1

(VCC = 4.5V) FIGURE 30. HC4046A AND HCT4046A OFFSET FREQUENCY

vs R2, C1 (VCC = 6V, VCC = 5.5V)

FIGURE 31. HC4046A fMIN/fMAX vs R2/R1 (VCC = 3V, 4.5V, 6V) FIGURE 32. HCT4046A fMAX/fMIN vs R2/R1 (VCC = 4.5V TO 5.5V)

Typical Performance Curves (Continued)

R2 = 2.2K

R2 = 22K

R2 = 220K

VCOIN = 0.5 VCC

VCC = 4.5V

110

102103104105106

CAPACITANCE, C1 (pF)

108

107

106

105

104

103

102

OFFSET FREQUENCY (Hz)

R2 = 2.2M

R2 = 11M VCOIN = 0.5 VCC

VCC = 3V

110

102103104105106

CAPACITANCE, C1 (pF)

108

107

106

105

104

103

102

OFFSET FREQUENCY (Hz)

R2 = 1.5K

R2 = 15K

R2 = 150K

R2 = 1.5M

R2 = 7.5M

VCOIN = 0.5 VCC

VCC = 4.5V

110

102103104105106

CAPACITANCE, C1 (pF)

108

107

106

105

104

103

102

OFFSET FREQUENCY (Hz)

R2 = 2.2K

R2 = 22K

R2 = 220K

R2 = 2.2M

R2 = 11M

110

102103104105106

CAPACITANCE, C1 (pF)

108

107

106

105

104

103

102

OFFSET FREQUENCY (Hz)

R2 = 3K

R2 = 30K

R2 = 300K

R2 = 3M

R2 = 15M

VCOIN = 0.5 VCC

HC VCC = 6V

HCT VCC = 5.5V

PIN 9 = 0.95 VCC FOR fMAX

PIN 9 = 0V FOR fMIN

VCC = 3V, 4.5V, 6V

102

fMAX/fMIN

010-2 10-1 1

R2/R1 102

PIN 9 = 0.95 VCC FOR fMAX

PIN 9 = 0V FOR fMIN

VCC = 4.5V TO 5.5V

102

fMAX/fMIN

010-2 10-1 1

R2/R1 102

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 33. DEFINITION OF VCO FREQUENCY LINEARITY FIGURE 34. HC4046A VCO LINEARITY vs R1 (VCC = 4.5V)

FIGURE 35. HC4046A VCO LINEARITY vs R1 (VCC = 3V) FIGURE 36. HC4046A VCO LINEARITY vs R1 (VCC = 6V)

FIGURE 37. HCT4046A VCO LINEARITY vs R1 (VCC = 4.5V,

VCC = 5.5V) FIGURE 38. HC4046A DEMODULATOR POWER DISSIPATION

vs RS (TYP) (VCC = 3V, 4.5V, 6V)

Typical Performance Curves (Continued)

∆V

1/2VCC VVCOIN

MIN MAX

∆V

∆V = 0.5V OVER THE VCC RANGE

FOR VCO LINEARITY

f’o = f1 + f2

LINEARITY = f’o - fo

f’ox 100%

1K 10K 100K 1M 10M

R1 (OHMS)

-2

-4

-6

-8

LINEARITY (%)

VCOIN = 2.25V ±1V

C1 = 50pF

VCC = 4.5V

R2 = OPEN

VCOIN = 2.25V ±0.45V

1K 10K 100K 1M 10M

R1 (OHMS)

-2

-4

-6

-8

LINEARITY (%)

VCOIN = 1.50V ±0.4V

C1 = 50pF

VCC = 3V

R2 = OPEN

VCOIN = 1.50V ±0.3V

1K 10K 100K 1M 10M

R1 (OHMS)

-2

-4

-6

-8

LINEARITY (%)

VCOIN = 3V ±1.5V

C1 = 50pF

VCC = 6V

R2 = OPEN

VCOIN = 3V ±0.6V

1K 10K 100K 1M 10M

R1 (OHMS)

-2

-4

-6

-8

LINEARITY (%)

VCC = 5.5V,

C1 = 50pF

R2 = OPEN

VCC = 4.5V,

VCOIN = 2.75V ±1.3V

VCOIN = 2.25V ±1.0V

VCC = 5.5V,

VCC = 4.5V,

VCOIN = 2.75V ±0.55V

VCOIN = 2.25V ±0.45V

VCOIN = 0.5 VCC

1K 10K 100K 1M

RS (OHMS)

104

103

102

VCC = 3V VCC = 4.5V

VCC = 6V

DEMODULATOR POWER DISSIPATION, PD (µW)

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

FIGURE 39. HCT4046A DEMODULATOR POWER DISSIPATION

vs RS (TYP) (VCC = 3V, 4.5V, 6V) FIGURE 40. HC4046A VCO POWER DISSIPATION vs R1

(C1 = 50pF, 1µF)

FIGURE 41. HCT4046A VCO POWER DISSIPATION vs R2

(C1 = 50pF, 1µF) FIGURE 42. HCT4046A VCO POWER DISSIPATION vs R1

(C1 = 50pF, 1µF)

FIGURE 43. HC4046A VCO POWER DISSIPATION vs R2 (C1 = 50pF, 1µF)

Typical Performance Curves (Continued)

VCOIN = 0.5 VCC

1K 10K 100K 1M

RS (OHMS)

104

103

102

VCC = 3V VCC = 4.5V

VCC = 6V

R1 = R2 = OPEN

DEMODULATOR POWER DISSIPATION, PD (µW)

VCOIN = 0.5VCC

1K 10K 100K 1M

R1 (OHMS)

106

105

104

103

102

R2 = RS = OPEN

CL = 50pF VCC = 6V

C1 = 50pF

VCC = 3V

C1 = 1µF

VCO POWER DISSIPATION, PD (µW)

VCC = 6V

C1 = 1µF

VCC = 3V

C1 = 50pF VCC = 4.5V

C1 = 1µF

VCC = 4.5V

C1 = 50pF

VCOIN = 0V (AT fMIN)

1K 10K 100K 1M

R2 (OHMS)

106

105

104

103

102

R1 = RS = OPEN

CL = 50pF

VCC = 6V

C1 = 50pF

VCC = 4.5V

C1 = 1µF

VCO POWER DISSIPATION, PD (µW)

VCC = 4.5V

C1 = 50pF

VCC = 6V

C1 = 1µF

VCOIN = 0.5V

1K 10K 100K 1M

R1 (OHMS)

106

105

104

103

102

R2 = RS = OPEN

VCC = 5.5V

C1 = 50pF

VCC = 5.5V

C1 = 1µF

VCO POWER DISSIPATION, PD (µW)

VCC = 4.5V

C1 = 50pF

VCC = 4.5V

C1 = 1µF

VCOIN = 0V (AT fMIN)

1K 10K 100K 1M

R2 (OHMS)

106

105

104

103

102

R1 = RS = OPEN

CL = 50pF

VCC = 6V

C1 = 50pF

VCC = 3V

C1 = 1µF

VCO POWER DISSIPATION, PD (µW)

VCC = 4.5V

C1 = 1µF

VCC = 4.5V

C1 = 50pF

VCC = 6V

C1 = 1µF

VCC = 3V

C1 = 50pF

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

Application Information

This information is a guide for the approximation of values of

external components to be used with the ’HC4046A and

’HCT4046A in a phase-lock-loop system.

References should be made to Figures 11 through 15 and

Figures 27 through 32 as indicated in the table.

Values of the selected components should be within the

following ranges:

HC/HCT4046A CPD

CHIP SECTION HC HCT UNIT

Comparator 1 48 50 pF

Comparators 2 and 3 39 48 pF

VCO 61 53 pF R1 Between 3kΩ and 300kΩ

R2 Between 3kΩ and 300kΩ

R1 + R2 Parallel Value > 2.7kΩ

C1 Greater Than 40pF

SUBJECT PHASE

COMPARATOR DESIGN CONSIDERATIONS

VCO Frequency

Without Extra Offset PC1, PC2 or PC3 VCO Frequency Characteristic

With R2 = ∞ and R1 within the range 3kΩ < R1 < 300kΩ, the characteristics of the VCO

operation will be as shown in Figures 11 - 15. (Due to R1, C1 time constant a small offset

remains when R2 = ∞.)

PC1 Selection of R1 and C1

Given fo, determine the values of R1 and C1 using Figures 11 - 15

PC2 or PC3 Given fMAX calculate foas fMAX/2 and determine the values of R1 and C1 using Figures 11 -

15. To obtain 2fL:2f

L≈1.2 (VCC - 1.8V)/(R1C1) where valid range of VCOIN is 1.1V < VCOIN

< VCC - 0.9V

VCO Frequency with

Extra Offset PC1, PC2 or PC3 VCO Frequency Characteristic

With R1 and R2 within the ranges 3kΩ< R1 < 300kΩ,3kΩ, < R2 < 300kΩ, the characteristics

of the VCO operation will be as shown in Figures 27 - 32.

PC1, PC2 or PC3 Selection of R1, R2 and C1

Given fo and fL, offset frequency, fMIN, may be calculated from fMIN ≈ fo - 1.6 fL.

Obtain the values of C1 and R2 by using Figures 27 - 30.

Calculate the values of R1 from Figures 31 - 32.

FIGURE 44. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT

OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE

fMAX

fVCO

fMIN MIN 1/2 VCC VVCOIN MAX

2fL

FIGURE 45. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:

fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE

fMAX

fVCO

fMIN

MIN 1/2 VCC VVCOIN MAX

2fL

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

PLL Conditions with

No Signal at the

SIGIN Input

PC1 VCO adjusts to fo with φDEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2)

PC2 VCO adjusts to fMIN with φDEMOUT = -360o and VVCOIN = 0V (see Figure 4)

PC3 VCO adjusts to fMAX with φDEMOUT = 360o and VVCOIN = VCC (see Figure 6)

PLL Frequency

Capture Range PC1, PC2 or PC3 Loop Filter Component Selection

PLL Locks on

Harmonics at Center

Frequency

PC1 or PC3 Yes

PC2 No

Noise Rejection at

Signal Input PC1 High

PC2 or PC3 Low

AC Ripple Content

when PLL is Locked PC1 fr = 2fi, large ripple content at φDEMOUT = 90o

PC2 fr = fi, small ripple content at φDEMOUT = 0o

PC3 fr = fSIGIN, large ripple content at φDEMOUT = 180o

SUBJECT PHASE

COMPARATOR DESIGN CONSIDERATIONS

small capture range (2fc) is obtained if τ > 2fc≈ 1/π (2πfL/τ.)1/2

FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET

(A) τ = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM

INPUT OUTPUT

|F(jω)|

-1/τ

FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET

(A) τ1 = R3 x C2; (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM

|F(jω)|

-1/τ2

INPUT OUTPUT

τ2 = R4 x C2;

τ3 = (R3 + R4) x C2

-1/τ3

1/τ31/τ2

R4 m = R4

R3 + R4

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-8875701EA ACTIVE CDIP J 16 1 TBD Call TI Call TI

5962-8960901EA ACTIVE CDIP J 16 1 TBD Call TI Call TI

CD54HC4046AF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD54HC4046AF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD54HCT4046AF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD74HC4046AE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC4046AEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC4046AM ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AM96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AME4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AMT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046ANSR ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046APWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

CD74HC4046APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046APWT ACTIVE TSSOP PW 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC4046APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT4046AEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT4046AM ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AM96 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AME4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AMT ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT4046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 5-Sep-2011

Addendum-Page 3

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC4046A, CD54HCT4046A, CD74HC4046A, CD74HCT4046A :

•Catalog: CD74HC4046A, CD74HCT4046A

•Military: CD54HC4046A, CD54HCT4046A

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC4046AM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74HC4046ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD74HC4046APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HC4046APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HCT4046AM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC4046AM96 SOIC D 16 2500 333.2 345.9 28.6

CD74HC4046ANSR SO NS 16 2000 367.0 367.0 38.0

CD74HC4046APWR TSSOP PW 16 2000 367.0 367.0 35.0

CD74HC4046APWT TSSOP PW 16 250 367.0 367.0 35.0

CD74HCT4046AM96 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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