LM21215AMHE-1/NOPB - NATIONAL SEMICONDUCTOR

PGOOD

VIN

LM21215A-1

VOUT

AGND

COMP

PVIN

SYNC

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11Å16

8,9,10

5,6,7

SS/TRK

CSS

CIN COUT

17 PGOOD

optional

0 3 6 9 12 15

100

EFFICIENCY (%)

OUTPUT CURRENT (A)

VIN = 3.3V

VIN = 4.0V

VIN = 5.0V

VIN = 5.5V

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM21215A

SNOSB87D –MARCH 2011–REVISED MAY 2019

LM21215A 2.95-V to 5.5-V,15-A, Voltage-Mode Synchronous Buck Converter

With Frequency Synchronization

1 Features

1• High-Efficiency Synchronous DC/DC Converter

– Input Voltage Range of 2.95 V to 5.5 V

– Adjustable Output Voltage From 0.6 V to VIN

– Output Current as High as 15 A

• Frequency Synchronization 300 kHz to 1.5 MHz

• Integrated 7-mΩPMOS Buck Switch Supports

100% Duty Cycle for Low Dropout Voltage

• Integrated 4.3-mΩNMOS Synchronous Rectifier

Eliminates Schottky Diode

• Accurate ±1% Internal Voltage Reference

• Automatic Diode Emulation Mode for Improved

Efficiency at Light Loads

• Monotonic Pre-Biased Startup

• Internal 0.5-ms or Externally Adjustable Soft Start

• Output Voltage Tracking Capability

• Ultra-Fast Line and Load Transient Response

– Voltage-Mode PWM Control

– Wide-Bandwidth Voltage Loop Error Amplifier

• Precision Enable with Hysteresis

• Integrated OVP, UVP, OCP, and UVLO

• Open-Drain Power Good Indicator

• Thermal Shutdown Protection With Hysteresis

• Thermally-Enhanced HTSSOP-20 Package

• Create a custom design using the LM21215A with

the WEBENCH®Power Designer

2 Applications

• Telecommunications Infrastructure

• DSP and FPGA Core Voltage Supplies

• High Efficiency POL Conversion

• Embedded Computing, Servers and Storage

Efficiency at 2.5 V, 500 kHz

3 Description

The LM21215A is a synchronous buck DC-DC

converter that delivers up to 15 A of output current at

output voltages as low as 0.6 V. Operating over an

input voltage range of 2.95 V to 5.5 V with ultra-high

efficiency, the LM21215A suits a wide variety of low

voltage systems. The voltage-mode control loop with

high gain-bandwidth error amplifier provides high

noise immunity, narrow duty cycle capability and is

easily compensated for stable operation with any type

of output capacitor, providing maximum flexibility and

ease of use.

The LM21215A features internal overvoltage

protection (OVP) and cycle-by-cycle overcurrent

protection (OCP) for increased system reliability. A

precision enable pin and integrated UVLO allow turn-

on of the device to be tightly controlled and

sequenced. Startup inrush currents are limited by an

internally-fixed or externally-adjustable soft-start

circuit. An integrated open-drain PGOOD indicator

provides fault reporting and supply sequencing.

Other features include auxiliary voltage rail tracking,

monotonic startup into pre-biased loads, and

switching frequency synchronization to an external

clock signal between 300 kHz and 1.5 MHz for beat-

frequency sensitive and multi-regulator applications.

The LM21215A is offered in a thermally-enhanced

20-pin HTSSOP package with an exposed pad that is

soldered to the PCB to achieve a very low junction-to-

board thermal impedance.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM21215A HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 15

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ............................................... 17

9 Power Supply Recommendations...................... 28

10 Layout................................................................... 29

10.1 Layout Guidelines ................................................. 29

10.2 Layout Example .................................................... 31

11 Device and Documentation Support................. 32

11.1 Device Support .................................................... 32

11.2 Documentation Support ........................................ 32

11.3 Community Resources.......................................... 33

11.4 Trademarks........................................................... 33

11.5 Electrostatic Discharge Caution............................ 33

11.6 Glossary................................................................ 33

12 Mechanical, Packaging, and Orderable

Information........................................................... 33

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (January 2016) to Revision D Page

• Editorial changes only, no technical revisions; add links for WEBENCH .............................................................................. 1

Changes from Revision B (March 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 27

SYNC

SS/TRK

AVIN

PVIN

PGND SW

AGND

COMP

PGOOD

PGND

11 SW

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(1) P = Power, G = Ground, I = Input, O = Output.

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP With Exposed Thermal Pad

Top View

Pin Functions

PIN TYPE(1) DESCRIPTION

NO. NAME

1 SYNC I Frequency synchronization input pin. Applying a clock signal to this pin forces the device to switch

at the clock frequency. If left unconnected, the frequency defaults to 500 kHz.

2 SS/TRK I Soft-start control pin. An internal 2-µA current source charges an external capacitor connected

between this pin and AGND to set the output voltage ramp rate during startup. This pin can also be

used to configure the tracking feature.

3 EN I Active high precision enable input. If not used, the EN pin can be left open, which will go high due to

an internal pullup current source.

4 AVIN P Analog input voltage supply that generates the internal bias. Connect PVIN to AVIN through a low

pass RC filter to minimize the influence of input rail ripple and noise on the analog control circuitry.

5–7 PVIN P Input voltage to the power switches inside the device. Connect these pins together at the device.

Locate a low ESR input capacitance as close as possible to these pins.

8–10 PGND G Power ground pins for the internal power switches.

11–16 SW P Switch node pins. Tie these pins together locally and connect to the filter inductor.

17 PGOOD O Open-drain power good indicator.

18 COMP O Compensation pin is connected to the output of the voltage loop error amplifier.

19 FB I Feedback pin is connected to the inverting input of the voltage loop error amplifier.

20 AGND G Quiet analog ground for the internal reference and bias circuitry.

EP Exposed

Pad PExposed metal pad on the underside of the package with an electrical and thermal connection to

PGND. Connect this pad to the PC board ground plane to improve thermal dissipation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) The PVIN prin can tolerate transient voltages up to 6.5 V for a duration of up to 6 ns. These transients can occur during normal

operation of the device.

(4) The SW pin can tolerate transient voltages up to 9 V for a duration of 6 ns and –1 V for a duration of 4 ns. These transients can occur

during normal operation of the device.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

PVIN(3) to GND, AVIN to GND −0.3 6 V

SW(4) to GND −0.3 VPVIN + 0.3 V

EN, FB, COMP, PGOOD, SS/TRK to GND −0.3 VPVIN + 0.3 V

Storage temperature, Tstg −65 150 ºC

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Input voltages PVIN, AVIN to GND 2.95 5.5 V

Output current, IOUT −0.3 15 A

Junction temperature, TJ−40 125 ºC

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1) LM21215A

UNITPWP (HTSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance 30.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 12.9 °C/W

RθJB Junction-to-board thermal resistance 0.3 °C/W

ψJT Junction-to-top characterization parameter 0.3 °C/W

ψJB Junction-to-board characterization parameter 2.3 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 0 °C/W

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6.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VPVIN = VAVIN= 5 V, TJ= 25°C. Minimum and maximum limits are

specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C

and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM

VFB Feedback voltage VIN = 2.95 V to 5.5 V TJ= –40°C to 125°C –1% 1% V

TJ= 25°C 0.6

ΔVOUT/ΔIOUT Load regulation 0.02% VOUT/A

ΔVOUT/ΔVIN Line regulation 0.1% VOUT/V

RDSON-HS High-side switch on-resistance ISW = 12 A TJ= –40°C to 125°C 9 mΩ

TJ= 25°C 7

RDSON-LS Low-side switch on-resistance ISW = 12 A TJ= –40°C to 125°C 6 mΩ

TJ= 25°C 4.3

ICLR HS rising switch current limit TJ= –40°C to 125°C 17.3 22.8 A

TJ= 25°C 20

ICLF LS falling switch current limit 14 A

VZX Zero-cross voltage –8 3 12 mV

IQOperating quiescent current TJ= –40°C to 125°C 3 mA

TJ= 25°C 1.5

ISD Shutdown quiescent current VEN = 0 V TJ= –40°C to 125°C 70 µA

TJ= 25°C 50

VUVLO AVIN undervoltage lockout AVIN rising TJ= –40°C to 125°C 2.45 2.95 V

TJ= 25°C 2.70

VUVLOHYS AVIN undervoltage lockout hysteresis TJ= –40°C to 125°C 140 280 mV

TJ= 25°C 200

VTRACKOS SS/TRACK accuracy (VSS/TRK – VFB) 0 < VSS/TRK < 0.55 V TJ= –40°C to 125°C –10 20 mV

TJ= 25°C 6

ISS Soft-start pin source current TJ= –40°C to 125°C 1.3 2.5 µA

TJ= 25°C 1.9

tINTSS Internal soft-start ramp to Vref SS/TRK open TJ= –40°C to 125°C 350 675 µs

TJ= 25°C 500

tRESETSS Device reset to soft-start ramp TJ= –40°C to 125°C 50 200 µs

TJ= 25°C 110

OSCILLATOR

fSYNCR SYNC frequency range TJ= –40°C to 125°C 300 1500 kHz

fDEFAULT Default (no SYNC signal) frequency TJ= –40°C to 125°C 475 525 kHz

TJ= 25°C 500

tSY_SW Time from VSYNC falling to VSW rising 200 ns

tSY_MIN Minimum SYNC pulse width, high or

low 100 ns

tHSBLANK HS OCP blanking time Rising edge of SW to ICLR comparison 55 ns

tLSBLANK LS OCP blanking time Falling edge of SW to ICLF comparison 400 ns

tZXBLANK Zero cross blanking time Falling edge of SW to VZX comparison 120 ns

tMINON Minimum HS on-time 140 ns

ΔVRAMP PWM ramp peak-peak voltage 0.8 V

ERROR AMPLIFIER

VOL Error amplifier open-loop gain ICOMP = –65 µA to 1 mA 95 dB

GBW Error amplifier gain-bandwidth 11 MHz

IFB Feedback pin bias current VFB = 0.6 V 1 nA

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Electrical Characteristics (continued)

Unless otherwise stated, the following conditions apply: VPVIN = VAVIN= 5 V, TJ= 25°C. Minimum and maximum limits are

specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C

and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ICOMPSRC COMP output source current 1 mA

ICOMPSINK COMP output sink current 65 µA

POWER GOOD

VOVP Overvoltage protection rising

threshold VFB rising TJ= –40°C to 125°C 105% 120% VFB

TJ= 25°C 112.5%

VOVPHYS Overvoltage protection hysteresis VFB falling 2% VFB

VUVP Undervoltage protection rising

threshold VFB rising TJ= –40°C to 125°C 82% 97% VFB

TJ= 25°C 90%

VUVPHYS Undervoltage protection hysteresis VFB falling 2.5% VFB

tPGDGL PGOOD deglitch low Time to PGOOD falling after OVP/UVP event 15 µs

tPGDGH PGOOD deglitch high Minimum low pulse 12 µs

RPGOOD PGOOD pulldown resistance TJ= –40°C to 125°C 10 40 Ω

TJ= 25°C 20

IPGOODLEAK PGOOD leakage current VPGOOD = 5 V 1 nA

LOGIC

VIHSYNC SYNC pin logic high 2 V

VILSYNC SYNC pin logic low 0.8 V

VIHENR EN pin rising threshold VEN Rising TJ= –40°C to 125°C 1.2 1.45 V

TJ= 25°C 1.35

VENHYS EN pin hysteresis TJ= –40°C to 125°C 50 180 mV

TJ= 25°C 110

IEN EN pin pullup current VEN = 0 V 2 µA

THERMAL SHUTDOWN

TTSD Thermal shutdown 165 °C

TTSD-HYS Thermal shutdown hysteresis 10 °C

3.0 3.5 4.0 4.5 5.0 5.5

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

ûOUTPUT VOLTAGE (%)

INPUT VOLTAGE (V)

IOUT = 0A

IOUT = 12A

3.0 3.5 4.0 4.5 5.0 5.5

1.0

1.1

1.2

1.3

1.4

1.5

IPVIN+ IAVIN(mA)

INPUT VOLTAGE (V)

0 3 6 9 12 15

100

EFFICIENCY (%)

OUTPUT CURRENT (A)

VIN = 3.3V

VIN = 4.0V

VIN = 5.0V

VIN = 5.5V

0 3 6 9 12 15

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

ûOUTPUT VOLTAGE (%)

OUTPUT CURRENT (A)

VIN = 3.3V

VIN = 5.0V

0 3 6 9 12 15

100

EFFICIENCY (%)

OUTPUT CURRENT (A)

FSW = 500 kHz

FSW = 750 kHz

FSW = 1 MHz

0 3 6 9 12 15

100

EFFICIENCY (%)

OUTPUT CURRENT (A)

VOUT = 1.2V

VOUT = 3.3V

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6.6 Typical Characteristics

Unless otherwise specified: VIN = 5 V, VOUT = 1.2 V, LF= 0.56 µH (1.8 mΩRDCR), CSS = 33 nF, fSW = 500 kHz, TA= 25°C for

efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 1. Efficiency Figure 2. Efficiency

Figure 3. Efficiency (VOUT = 2.5 V, FSW= 500 kHz, Inductor

P/N SER2010-601MLD) Figure 4. Load Regulation

Figure 5. Line Regulation Figure 6. Non-Switching IQ(TOTAL) vs VIN

-40 -20 0 20 40 60 80 100 120

0.50

0.52

0.54

0.57

0.58

0.60

0.62

0.64

0.66

0.68

VOVP,VUVP(V)

JUNCTION TEMPERATURE (°C)

VUVP

VOVP

0.70

-40 -20 020 40 60 80 100 120

SHUTDOWN CURRENT I ( A)

SD μ

JUNCTION TEMPERATURE (°C)

-40 -20 0 20 40 60 80 100 120

1.28

1.29

1.30

1.31

1.32

1.33

1.34

1.35

1.36

1.37

104

112

120

128

136

144

152

160

VIHENR(V)

JUNCTION TEMPERATURE (°C)

VENHYS(V)

VIHENR

VENHYS

1.38

-40 -20 0 20 40 60 80 100 120

2.60

2.62

2.64

2.66

2.68

2.70

2.72

2.74

2.76

2.78

2.80

150

165

180

195

210

225

240

255

270

285

300

VUVLO(V)

JUNCTION TEMPERATURE (°C)

VUVLOHYS(mV)

VUVLO

VUVLOHYS

-40 -20 0 20 40 60 80 100 120

0.90

0.93

0.96

0.99

1.02

1.05

1.08

1.11

1.14

1.17

1.20

0.100

0.108

0.116

0.124

0.132

0.140

0.148

0.156

0.164

0.172

0.180

IAVIN(mA)

JUNCTION TEMPERATURE (°C)

IPVIN(mA)

IAVIN

IPVIN

140

-40 -20 0 20 40 60 80 100 120

0.598

0.599

0.600

0.601

0.602

VFB(V)

JUNCTION TEMPERATURE (°C)

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Typical Characteristics (continued)

Unless otherwise specified: VIN = 5 V, VOUT = 1.2 V, LF= 0.56 µH (1.8 mΩRDCR), CSS = 33 nF, fSW = 500 kHz, TA= 25°C for

efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 7. Non-Switching IAVIN and IPVIN vs Temperature Figure 8. Feedback (FB) Voltage vs Temperature

Figure 9. Enable Threshold and Hysteresis vs Temperature Figure 10. UVLO Threshold and Hysteresis vs Temperature

Figure 11. Enable Low Current vs Temperature Figure 12. OVP/UVP Threshold vs Temperature

VOUT (200 mV/Div)

VSYNC (2V/Div)

VSWITCH (2V/Div)

VOUT (50 mV/Div)

IOUT (5A/Div)

-40 -20 0 20 40 60 80 100 120

18.7

18.8

18.9

19.0

19.1

19.2

19.3

19.4

19.5

19.6

CURRENT LIMIT ICLR(A)

AMBIENT TEMPERATURE (°C)

JUNCTION TEMPERATURE (°C)

CURRENT LIMIT ICLR (A)

VSWITCH (2V/Div)

VSYNC (2V/Div)

VOUT (200 mV/Div)

-40 -20 0 20 40 60 80 100 120

120

124

128

132

136

140

144

148

152

156

160

MINIMUM ON-TIME (nS)

JUNCTION TEMPERATURE (°C)

-40 -20 0 20 40 60 80 100 120

RDSON(m)

JUNCTION TEMPERATURE (°C)

LOW SIDE

HIGH SIDE

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Typical Characteristics (continued)

Unless otherwise specified: VIN = 5 V, VOUT = 1.2 V, LF= 0.56 µH (1.8 mΩRDCR), CSS = 33 nF, fSW = 500 kHz, TA= 25°C for

efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 13. Minimum On-Time vs Temperature Figure 14. MOSFET On-State Resistance vs Temperature

Figure 15. Peak Current Limit vs Temperature Figure 16. SYNC Signal Removed, 4 µs/Div

Figure 17. SYNC Signal Acquired, 10 µs/div Figure 18. Load Transient Response, 100 µs/Div

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VTRACK (500 mV/Div)

IOUT (10A/Div)

VSW (2V/Div)

VOUT (1V/Div)

IL (10A/Div)

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VENABLE (5V/Div)

IOUT (10A/Div)

VOUT (500 mV/Div)

VPGOOD (5V/Div)

VENABLE (5V/Div)

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Typical Characteristics (continued)

Unless otherwise specified: VIN = 5 V, VOUT = 1.2 V, LF= 0.56 µH (1.8 mΩRDCR), CSS = 33 nF, fSW = 500 kHz, TA= 25°C for

efficiency curves, loop gain plots and waveforms, and TJ= 25°C for all others.

Figure 19. Startup with Prebiased Output, 2 ms/Div Figure 20. Startup with SS/TRK Open Circuit, 200 µs/Div

Figure 21. Startup with Tracking Signal Applied, 200 ms/Div Figure 22. Output Overcurrent Condition, 10 µs/Div

Control

Logic

Thermal

Shutdown

OSC RAMP

INT

VREF

0.6V +

AVIN

SYNC

SS/TRK

COMP

AGND

PGND

PGOOD

PVIN

PWM

Comparator

UVLO

Precision

Enable

UVP

ILIMIT Low

ILIMIT High

Zero-cross

OVP

PowerBAD

PWM

0.675V

0.54V

PLL

AVIN

PVIN

2.7V

1.35V

0.6V

1.9A+

Driver

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7 Detailed Description

7.1 Overview

The LM21215A synchronous buck regulator features all of the functions necessary to implement an efficient low-

voltage converter using a minimum number of external components. This easy-to-use regulator features two

integrated power MOSFET switches and is capable of supplying up to 15 A of continuous output current.

Synchronous rectification yields high efficiency for low output voltage and high load current applications, whereas

discontinuous conduction mode (DCM) with diode emulation mode (DEM) enables high-efficiency conversion

with light load current conditions.

The regulator utilizes voltage-mode control with trailing-edge PWM modulation to optimize stability and transient

response over the entire input voltage range. The device operates at high switching frequency, allowing the use

of a small inductor yet still achieving high efficiency. The precision internal voltage reference allows output

voltages as low as 0.6 V. Fault protection features include peak and valley current limiting, thermal shutdown,

overvoltage protection, and undervoltage lockout. The device is available in the HTSSOP-20 package featuring

an exposed pad to aid thermal dissipation. The LM21215A is ideal for numerous applications to efficiently step-

down from a 5-V or 3.3-V bus.

7.2 Functional Block Diagram

VOUT

VEN

Voltage

Time

VPGOOD

Soft-Start Time, tSS

VUVP

90% VOUT

Enable Delay,

tRESETSS

SS SS

SS t I

C0.6V

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7.3 Feature Description

7.3.1 Precision Enable

The EN pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a

precision analog input that enables the device when the voltage exceeds 1.35 V (typical). The EN pin has 110

mV of hysteresis and disables the output when the Enable voltage falls below 1.24 V (typical). If the EN pin is not

used, it can be left open as it is pulled high by an internal 2-µA current source. Since the EN pin has a precise

turn-on threshold, it can be used along with an external resistor divider network from VIN to configure the device

to turn on at a precise input voltage.

7.3.2 Input Voltage UVLO

The LM21215A has a built-in undervoltage lockout protection circuit that prevents the device from switching until

the input voltage reaches 2.7 V (typical). The UVLO threshold has 200 mV of hysteresis that prevents the device

from responding to power-on glitches during startup. As mentioned above, adjust the turn-on threshold of the

supply by using the precision enable pin and a resistor divider network connected to VIN. Please refer to

Figure 30 of the Detailed Design Procedure section for more detail.

7.3.3 Soft-Start Capability

When EN exceeds 1.35 V and AVIN is above its UVLO threshold of 2.7 V, the LM21215A begins charging the

output linearly to the voltage setpoint dictated by the feedback resistor network. The LM21215A employs a user-

adjustable soft-start circuit to set the output voltage ramp time during startup. A capacitor from SS/TRK to GND

sets the required soft-start time. Once the enable voltage exceeds 1.35 V, an internal 1.9-µA current source

begins to charge the soft-start capacitor. This allows the user to limit inrush currents due to a high output

capacitance and avoid an overcurrent condition. Adding a soft-start capacitor also reduces the stress on the input

rail. Use Equation 1 to calculate the soft-start capacitance.

where

• ISS is nominally 1.9 µA

• tSS is the desired startup time (1)

If VIN is higher than the UVLO level and Enable is toggled high, the soft-start sequence begins. There is a small

delay between enable transitioning high and the beginning of the soft-start sequence. This delay allows the

LM21215A to initialize its internal circuitry. Once the output has charged to 90% of the nominal output voltage,

the PGOOD flag transitions high. This behavior is illustrated in Figure 23.

Figure 23. Soft-Start Timing

Vss

VFB

VEN

VPGOOD

VSW

OVP UVP PRE-BIASED

STARTUP

DISABLE

Vovp

Vuvp

tPGDGL

0.6V

tRESETSS

tPGDGH

VOVPHYS

VUVPHYS

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Feature Description (continued)

As shown above, the soft-start capacitance is set by the nominal feedback voltage level 0.6 V, the soft-start

charging current ISS, and the desired soft-start time. If a soft-start capacitor is not installed, the LM21215A

defaults to a soft-start time of 500 µs. The LM21215A cannot startup faster than 500 µs. When Enable is cycled

or the device enters UVLO, the soft-start capacitor is discharged to reset the startup process. This also occurs

when the device enters short circuit mode following an overcurrent event.

7.3.4 PGOOD Indicator

The PGOOD flag provides the user with a way to monitor the status of the LM21215A. In order to use the

PGOOD function, the application must provide a pullup resistor to a desired DC voltage, for example VIN.

PGOOD responds to a fault condition by pulling PGOOD low with the open-drain output. PGOOD pulls low on

the following conditions: 1) VFB moves above or below the VOVP or VUVP, respectively; 2) The EN voltage is

brought below the Enable turn-off threshold; 3) A pre-biased output condition exists (VFB > VSS/TRK). PGOOD has

12 μs and 15 μs of built-in deglitch time for rising and falling edges, respectively.

Figure 24 shows the conditions that cause PGOOD to respond.

Figure 24. PGOOD Indicator Operation

7.3.5 Frequency Synchronization

The SYNC pin allows the LM21215A to be synchronized to an external clock frequency. When a clock signal

within the allowable frequency range of 300 kHz to 1.5 MHz is present on SYNC, an internal PLL synchronizes

the turn-on of the high-side MOSFET (SW voltage rising) to the negative edge of the clock signal, as seen in

Figure 25.

The clock signal can be present on the SYNC pin before the device is powered on without loading of the clock

signal. Alternatively, if a clock signal is not present while the device is powered up, the default switching

frequency is 500 kHz. Once the clock signal is available, the device synchronizes to the clock frequency. The

time required to achieve synchronization depends on the clock frequency.

SHORT CIRCUIT

ICLF

ICLR

VSS

VFB

VOUT

VSW

CURRENT LIMIT SHORT CIRCUIT

REMOVED

100 mV

VIN

Time

VSW

Time

VSYNC

tSY_SW

VIH_SYNC

VIL_SYNC

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Feature Description (continued)

Figure 25. Frequency Synchronization

7.3.6 Current Limit

The LM21215A has overcurrent protection to avoid excessive current levels through the power MOSFETs and

inductor. A current limit condition exists when the high-side MOSFET's current exceeds the rising current limit

level, ICLR. The control circuitry responds to this event by turning off the high-side MOSFET and turning on the

low-side MOSFET. This forces a negative voltage on the inductor, thereby causing the inductor current to

decrease. The high-side MOSFET does not conduct again until the lower current limit level, ICLF, is sensed on

the low-side MOSFET. At this point, the LM21215A resumes normal switching.

A current limit condition causes the internal soft-start voltage to ramp downward. After the internal soft-start

ramps below the feedback (FB) voltage, nominally 0.6 V, FB begins to ramp downward, as well. This voltage

foldback limits the power consumption in the device during a sustained overload. After the current limit condition

is cleared, the internal soft-start voltage ramps up again. Figure 26 describes current limit behavior including VSS,

VFB, VOUT and VSW waveforms.

Figure 26. Current Limit Conditions

 

OUT

BOUNDARY F SW

V 1 D

I2 2 L F

˜ 

˜ ˜

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Feature Description (continued)

7.3.7 Short Circuit Protection

In an event that the output is shorted with a low impedance to ground, the LM21215A limits the current into the

short by resetting the device. A short circuit condition is sensed as a current limit condition coinciding with a

voltage on the FB pin that is lower than 100 mV. When this condition occurs, the device begins its reset

sequence, turning off both power MOSFETs and discharging the soft-start capacitor after tRESETSS (nominally 110

µs). The device then attempts to restart. If the short circuit condition still exists, it resets again, repeating until the

short circuit condition is cleared. The reset prevents excessive power MOSFET dissipation and limits thermal

stress during a short circuit fault condition.

7.4 Device Functional Modes

7.4.1 Light-Load Operation

The LM21215A maintains high efficiency when operating at light loads. Whenever the load current is reduced to

a level less than half the peak-to-peak inductor ripple current, the device enters discontinuous conduction mode

(DCM) and prevents negative inductor current. The low-side MOSFET then operates in diode emulation mode

(DEM), conducting only positive inductor current. Calculate the critical conduction boundary using Equation 2.

(2)

Several diagrams are shown in Figure 27 illustrating continuous conduction mode (CCM), discontinuous

conduction mode (DCM), and the boundary condition.

When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at SW

as a result of the LC tank circuit formed by the filter inductor and the parasitic capacitance at the SW node. At

very light loads, usually below 500 mA, several pulses may be skipped in between switching cycles, effectively

reducing the switching frequency and further improving light-load efficiency.

7.4.2 Overvoltage and Undervoltage Handling

The LM21215A has built-in undervoltage protection (UVP) and overvoltage protection (OVP) using FB voltage

comparators to control the power MOSFETs. The rising OVP threshold is typically set at 112.5% of the nominal

voltage setpoint. Whenever excursions occur in the output voltage above the OVP threshold, the device

terminates the present on-pulse, turns on the low-side MOSFET, and pulls PGOOD low. The low-side MOSFET

remains on until either the FB voltage falls back into regulation or the inductor current zero-cross is detected. If

the output reaches the falling UVP threshold, typically 90% of the nominal setpoint, the device continues

switching and PGOOD is asserted and pulls low. As detailed in the PGOOD Indicator section, PGOOD has 15 μs

of built-in deglitch time in response to a UVP or OVP condition to avoid false tripping during transient glitches.

7.4.3 Thermal Shutdown

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum

junction temperature is exceeded. When activated, typically at 165°C, the LM21215A tri-states the power

MOSFETs and resets soft start. After the junction temperature cools to approximately 155°C, the device starts up

using the normal startup routine.

Discontinuous Conduction Mode (DCM)

IPEAK

Discontinuous Conduction Mode (DCM)

DCM±CCM Boundary

Continuous Conduction Mode (CCM)

SW Node Voltage, vSW(t) SW Node Voltage, vSW(t)Inductor Current, iL(t)Inductor Current, iL(t)Inductor Current, iL(t)

VIN

IOUT2

IOUT1

VIN

IOUT3

'IL

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Device Functional Modes (continued)

Figure 27. LM21215A Modes of Operation

PGOOD

VIN

LM21215A-1

VOUT

AGND

COMP

PVIN

SYNC

CIN3

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11Å16

8,9,10

5,6,7

SS/TRK

CSS

CIN2

CIN1

VIN

RPGOOD

CO1 CO2 CO3

OPEN PGOOD

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM21215A is a synchronous buck DC/DC converter with a maximum output current of 15 A. The following

design procedure assists with component selection for the LM21215A. Alternately, the WEBENCH® Design Tool

is available to generate a complete design. With access to a comprehensive component database, this tool uses

an iterative design procedure to create an optimized design, allowing the user to experiment with various design

options. As well as numerous LM21215 reference designs populated in the TI Designs reference design library,

the LM21215A Quickstart Design Calculator is also available as a free download.

8.2 Typical Applications

8.2.1 Typical Application 1

The schematic diagram of a 15-A regulator is given in Figure 28. The target full-load efficiency in this example is

89% at an output voltage of 1.2 V and nominal input voltage of 5 V. The free-running switching frequency (with

the SYNC pin open circuit) is 500 kHz. In terms of control loop performance, the target loop crossover frequency

is 100 kHz with a phase margin in excess of 50°.

Figure 28. Typical Application Schematic 1

8.2.1.1 Design Requirements

An example of the step-by-step procedure to generate power stage and compensation component values using

the typical application setup of Figure 28) is given in Table 1. The relevant design specifications are given in

Table 1. Here, fcrossover is the desired loop crossover frequency, which generally is less than one-fifth of the

switching frequency, and ΔVOUT(pk-pk) is the peak-to-peak output voltage ripple.

FB1

OUT FB2

V 0.6V 1 R

§ ·

˜ 

¨ ¸

RFB1

RFB2

VOUT

LM21215A-1

0.6V

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Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

VIN 5 V

VOUT 1.2 V

IOUT 15 A

FSW 500 kHz

fcrossover 100 kHz

ΔVOUT(pk-pk) 10 mV

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM21215A device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Output Voltage Setpoint

The first step in designing an LM21215A application is to configure the output voltage setpoint by using a voltage

divider between VOUT and AGND, with the middle node connected to FB. When operating under steady state

conditions, the LM21215A regulates VOUT such that the FB voltage is driven to 0.6 V.

Figure 29. Setting the Output Voltage by Feedback Resistor Divider

A good starting point for the lower feedback resistor, RFB2, is 10 kΩ. Calculate RFB1 using Equation 3.

(3)

EN1 EN2 EN EN2

V 1.35V

R R 1.35V I R



 ˜

AVIN

REN1 LM21215A-1

Input Power

Supply

REN2

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8.2.1.2.3 Precision Enable

The Enable (EN) pin of the LM21215A allows the output to be toggled on and off. This pin is a precision analog

input. When the voltage exceeds 1.35 V, the converter begins to regulate the output voltage as long as AVIN has

exceeded the UVLO threshold voltage of 2.7 V. There is an internal pullup current source of 2 µA connected to

EN. If enable is not used, the device turns on automatically. Also, if EN is not toggled directly, the device can be

set to turn on at a certain input voltage higher than the internal UVLO rising threshold. This is achieved with an

external resistor divider from AVIN to EN and EN to AGND as shown in Figure 30.

Figure 30. Input Voltage Turn-on Setpoint Configured by Enable Resistor Divider

The resistances of REN1 and REN2 are chosen to allow EN to reach its rising threshold voltage at the desired the

input supply voltage. With the enable current source included, use Equation 4 to solve for REN1.

where

• REN1 is the resistor from VIN to EN

• REN2 is the resistor from EN to AGND

• IEN is the internal enable pullup current (2 µA)

• 1.35 V is the precision enable rising threshold voltage (4)

Typical values for REN2 range from 10 kΩto 100 kΩ.

8.2.1.2.4 Filter Inductor Selection

The filter inductor, designated LF, chosen for the application influences the ripple current and the efficiency of the

converter. The first selection criteria is to define the buck converter inductor ripple current ΔIL, typically selected

between 20% to 40% of the maximum output current. Figure 31 shows the ripple current in a conventional buck

converter operating in continuous conduction mode. Larger ripple current results in a lower inductance, which

leads to lower inductor DC resistance (DCR) and improved efficiency. However, larger ripple current causes the

LM21215A to operate in DCM at a higher average output current.

OUT L ESR SW OUT

V I R 8 F C

§ ·

' '  ¨ ¸

˜ ˜

L(max)

L(max) OUT(max) I

I I 2



 

OUT

FL SW

V 1 D

LI F

˜ 

' ˜

VIN

IL AVG = IOUT 'IL

Time

VSW

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Figure 31. Switch (SW) Voltage and Inductor Current Waveforms

Once the ripple current has been determined, calculate the appropriate inductance using Equation 5.

(5)

A 0.56-µH inductor with 1.8-mΩDCR meets the application requirements here. The peak inductor current at full

load corresponds to the maximum output current plus the ripple current, as shown by Equation 6.

(6)

Choose an inductor with a saturation current rating at maximum operating temperature that is higher than the

overcurrent protection limit. In general, lower inductance is desirable in switching converters because it equates

to faster transient response, lower inductor DCR, and reduced size for more compact designs. However, too low

of an inductance implies large inductor ripple current such that the overcurrent protection circuit is falsely

triggered at the full load. Larger inductor ripple current also implies higher output voltage ripple.

8.2.1.2.5 Output Capacitor Selection

The output capacitor, designated COUT, filters the inductor ripple current and provides a source of charge for

transient load conditions. A wide range of output capacitors may be used with the LM21215A that provide various

advantages. The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical

trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and

noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for

transient loading conditions.

When selecting an output capacitor, the two performance characteristics to consider are the output voltage ripple

and load transient response. Approximate the output voltage ripple by using Equation 7.

where

•ΔVOUT is the peak-to-peak output voltage ripple

• RESR is the effective series resistance (ESR) of the output capacitor

• FSW is the switching frequency

• COUT is the effective output capacitance (7)

 

OUT IN OUT

RMS CIN OUT IN

V V V

I I V



˜ 

 

F OUT STEP

DROOP OUT STEP ESR OUT IN OUT

L I

V I R C V V



˜ '

' ˜  ˜ 

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The amount of output voltage ripple is application specific. A general recommendation is to keep the output ripple

less than 1% of the rated output voltage. Keep in mind that ceramic capacitors are sometimes preferred because

they have very low ESR. However, depending on package and voltage rating of the capacitor, the effective in-

circuit capacitance can drop significantly with applied voltage. The output capacitor selection also affects the

output voltage droop during a load transient. The peak deviation of the output voltage during a load transient is

dependent on many factors. An approximation of the transient dip ignoring loop bandwidth is obtained using

Equation 8:

where

• COUT is the minimum required output capacitance

• LFis the filter inductance

• VDROOP is the output voltage deviation ignoring loop bandwidth considerations

•ΔIOUT-STEP is the load step change

• RESR is the output capacitor ESR

• VIN is the input voltage

• VOUT is the output voltage setpoint (8)

Three 100-µF, 6.3-V ceramic capacitors with X5R dielectric and 1210 footprint are selected here based on a

review of the capacitor's tolerance and voltage coefficient to meet output ripple specification.

8.2.1.2.6 Input Capacitor Selection

High quality input capacitors are necessary to limit the input voltage ripple while supplying switching-frequency

AC current to the buck power stage. It is generally recommended to use X5R or X7R dielectric ceramic

capacitors, thus providing low impedance and high RMS current rating over a wide temperature range. To

minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the

PVIN and PGND pins. A good approximation for the required ripple current rating is given by Equation 9.

(9)

The highest input capacitor RMS current occurs at 50% duty cycle, at which point the RMS ripple current rating

should be greater than half the output current. Place low ESR ceramic capacitors in parallel with higher value

bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input

parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and

one or two 22-μF 10-V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor

based on its ripple current rating and operating temperature.

When operating at low input voltages (3.3 V or lower), additional capacitance may be necessary to avoid

triggering an undervoltage condition during an output current transient. This depends on the impedance between

the input voltage supply and the LM21215A, as well as the magnitude and slew rate of the load transient.

The AVIN pin requires a 1-µF ceramic capacitor to AGND and a 1-Ωresistor to PVIN. This RC network filters

inherent noise on PVIN from the sensitive analog circuitry connected to AVIN.

8.2.1.2.7 Control Loop Compensation

This section walks through the various steps in obtaining the open-loop transfer function. There are three main

blocks of a voltage-mode buck converter that the power supply designer must consider when designing the

control system: the power stage, the PWM modulator, and the compensated error amplifier. The control loop

architecture of a voltage-mode buck converter is provided in Figure 32.

ESR OUT ESR

f2 C R

˜ S ˜ ˜

LC O ESR

F OUT O DCR

1 1

f2R R

L C R R

˜ S § ·



˜ ˜¨ ¸



PWM RAMP

VIN

COUT

RFB1

RFB2

CC2

CC1 RC1

VOUT

CC3

RC2

COMP

Driver

PWM

Error Amplifier and Compensation

PWM Modulator

SW RESR

Power Stage

0.6V

RDCR

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Figure 32. Voltage-mode Buck Converter Architecture

The power stage consists of the filter inductor (LF) with DCR (DC resistance RDCR), output capacitor (COUT) with

ESR (effective series resistance RESR), and load resistance (RO). The LM21215A incorporates a high-bandwidth

error amplifier between the FB and COMP pins to achieve high loop bandwidth. The error amplifier (EA)

constantly regulates FB to 0.6 V. The compensation component network around the error amplifier establish

system stability. The modulator creates the duty cycle command by comparing the error amplifier output with an

internally-generated PWM ramp set at the switching frequency.

There are three transfer functions that are taken into consideration when obtaining the total open-loop transfer

function; COMP-to-duty cycle (modulator), duty cycle-to-VOUT (power stage), and VOUT-to-COMP (compensator).

If ΔVRAMP is the peak-to-peak ramp voltage (nominally 0.8 V), the COMP-to-duty cycle transfer function is simply

the PWM modulator gain given by Equation 10.

(10)

The duty cycle-to-output transfer function includes the filter inductor, output capacitor, and output load resistance.

The inductor and capacitor create a pair of complex poles at the LC tank frequency expressed by Equation 11.

(11)

In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a

frequency described by Equation 12.

(12)

 

C mid

P1 P2

2 f s

1 1

s 2 f

G s K s s

1 1

2 f 2 f

§ ·

˜ S ˜

§ ·

 ˜ 

¨ ¸

¨ ¸ ˜ S˜

§ · § ·

 ˜ 

¨ ¸ ¨ ¸

˜ S ˜ ˜ S ˜

100 1k 10k 100k 1M 10M

-80

-60

-40

-20

-360

-320

-280

-240

-200

-160

-120

-80

-40

GAIN (dB)

FREQUENCY (HZ)

PHASE (°)

GAIN

PHASE

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A Bode plot showing the –40dB/decade power stage response is shown in Figure 33

Figure 33. Power Stage Bode Plot

The complex poles created by the filter inductor and output capacitor cause a 180° phase lag. The phase is

boosted back up to –90° by the output capacitor ESR zero. The compensator must provide sufficient phase

boost to stabilize the loop response. The type-III compensation network shown around the error amplifier in

Figure 32 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct

frequencies stabilizes the closed loop response. The compensator transfer function is given by Equation 13.

where

• Kmid is the mid-band gain, RC1/RFB1 (13)

The pole located at the origin gives high open-loop gain at DC, translating into improved load regulation

accuracy. This pole occurs at a very low frequency due to the finite gain of the error amplifier; however, its

location is approximated at DC for the purposes of compensation. The other two poles and two zeros are located

accordingly to stabilize the voltage-mode loop depending on the power stage complex poles and their quality

factor, Q. Figure 34 illustrates a typical type-III compensator transfer function.

crossover RAMP

C1 FB1

LC IN

fV100kHz 0.8V

R R 10k 9.2k

f V 17.4kHz 5V

˜ ˜ ˜ ˜ : :

 

Z1 C1 C1

Z2 LC C1 FB1 C3

P1 ESR C2 C3

SW C1 C2

P2 C1 C1 C2

f2 2 R C

f f 2 R R C

f f 2 R C

F C C

f2 2 R C C

˜ S ˜ ˜

˜ S ˜  ˜

˜ S ˜ ˜



˜ S ˜ ˜ ˜

100 1k 10k 100k 1M 10M

-20

100

-180

-135

-90

-45

GAIN (dB)

FREQUENCY (Hz)

PHASE (°)

GAIN

PHASE

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Figure 34. Type-III Compensation Network Bode Plot

As seen in Figure 34, the two compensator zeros located at (fLC/2, fLC) provide a phase boost. This mitigates the

effect of the phase loss from the output filter. The compensation network also adds two poles to the system. One

pole is located at the output capacitor ESR zero (fESR) and the other pole is at half the switching frequency

(FSW/2) to roll off the high frequency response.

The dependency of the pole and zero locations on the compensation components is described as follows:

The output capacitance, COUT, depends on capacitor chemistry and bias voltage. For multi-layer ceramic

capacitors (MLCC), the total capacitance degrades as the DC bias voltage is increased. To accurately calculate

and optimize the compensation network, it is advisable to determine the effective capacitance of the output

capacitors when biased at the output voltage.

The example given here is the total output capacitance using three MLCC output capacitors biased at 1.2 V, as

seen in the typical application schematic of Figure 28. 50% capacitance derating is assumed.

NOTE

It is more conservative, from a stability standpoint, to err on the side of a lower output

capacitance in the compensation calculations rather than a higher, as this will result in a

lower bandwidth but increased phase margin.

First, choose a resistance for RFB1, a typical value being 10 kΩ. From this, calculate the resistance of RC1 using

Equation 14 to set the mid-band gain such that the desired crossover frequency is achieved.

(14)

10 100 1k 10k 100k 1M

-50

100

150

200

-40

-20

100

120

140

160

GAIN (dB)

FREQUENCY (Hz)

PHASE MARGIN (°)

GAIN

PHASE

C3 ESR C2

C 898pF

2 f R

˜ S ˜ ˜

C2 ESR

C2 ESR LC

R f

R 166

f f



C2 SW C1 C1

C 71pF

F R C 1

S ˜ ˜ ˜ 

C1 LC C1

C 1.99nF

f R

S ˜ ˜

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Next, calculate the capacitance of CC1 by placing a zero at half of the LC double pole frequency (fLC):

(15)

Now calculate CC2 to place a pole at half of the switching frequency and RC2 to place the second zero at the LC

double pole frequency:

(16)

(17)

Last, derive capacitance of CC3 to place a pole at the same frequency as the output capacitor ESR zero:

(18)

An illustration of the total loop response is seen in Figure 35.

Figure 35. Loop Response

It is important to verify the stability either by observing the load transient response or by using a network

analyzer. A phase margin between 45° and 70° is usually desired for voltage-mode converter circuits. Excessive

phase margin causes slow system response to load transients whereas low phase margin leads to an oscillatory

load transient response. If the peak deviation of the load transient response is larger than required, increasing

fcrossover and recalculating the compensation components may help but usually at the expense of phase margin.

VSYNC (1V/Div)

VSWITCH (2V/Div)

100 1k 10k 100k 1M

-20

-80

-40

120

160

GAIN (dB)

FREQUENCY (Hz)

PHASE MARGIN (°)

GAIN

PHASE MARGIN

0 2 4 6 8 10 12

EFFICIENCY (%)

OUTPUT CURRENT (A)

500kHz

1MHz

1.5MHz

VOUT (10 mV/Div)

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Table 2. Bill of Materials (VIN = 3.3 V to 5.5 V, VOUT = 1.2 V, IOUT = 15 A, fSW = 500 kHz)

REF DES DESCRIPTION VENDOR PART NUMBER QUANTITY

CFCAP, CERM, 1 µF, 10 V, ±10%, X7R, 0603 MuRata GRM188R71A105KA61D 1

CIN1, CIN2, CIN3,

CO1, CO2, CO3 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1206 MuRata GRM31CR60J107ME39L 6

CC1 CAP, CERM, 1800 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H182J 1

CC2 CAP, CERM, 68 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1

CC3 CAP, CERM, 820 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H821J 1

CSS CAP, CERM, 0.033 µF, 16 V, ±10%, X7R, 0603 MuRata GRM188R71C333KA01D 1

LFInductor, Powdered Iron, 560 nH, 27.5A, 1.8 mΩ, SMD Vishay Dale IHLP4040DZERR56M01 1

RFRES, 1 Ω, 5%, 0.1 W, 0603 Vishay Dale CRCW06031R00JNEA 1

RC1 RES, 9.31 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW06039K31FKEA 1

RC2 RES, 165 Ω, 1%, 0.1 W, 0603 Vishay Dale CRCW0603165RFKEA 1

RFB1, RFB2, RPGOOD RES, 10 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW060310K0FKEA 3

U1LM21215A Synchronous Buck Regulator TI LM21215AMH-1/NOPB 1

8.2.1.3 Application Curves

For additional details on the wavefroms shown in this section, please refer to application note AN-2131

LM21215A Evaluation Board,SNVA477.

Figure 36. Efficiency vs Load Current, VOUT = 1.2 V Figure 37. Output Ripple Voltage Waveform (1 µs/Div)

Figure 38. SW and SYNC Voltage Waveforms (1 µs/Div) Figure 39. Bode Plot

PGOOD

VIN

LM21215A-1

VOUT

AGND

COMP

PVIN

SYNC

RC1

CC1

CC2

CC3

RFB1

RFB2

RC2

PGND

AVIN

11Å16

8,9,10

5,6,7

SS/TRK

CSS

CIN1

CO1 CO2

REN1

REN2

1 MHz

VIN

RPGOOD

PGOOD

LM21215A

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SNOSB87D –MARCH 2011–REVISED MAY 2019

Product Folder Links: LM21215A

8.2.2 Typical Application 2

The schematic diagram of a DC/DC regulator with 8-A output current is given by Figure 40.

Figure 40. Typical Application Schematic 2

8.2.2.1 Design Requirements

Output voltage setpoint is 0.9 V and the input voltage ranges from 4 V to 5.5 V. The switching frequency is set by

means of an external synchronization signal at 1 MHz. The output voltage soft-start time is 10 ms.

8.2.2.2 Detailed Design Procedure

Follow the detailed design procedure in Typical Application 1. The relevant power stage and small-signal

components are listed in Table 3.

Table 3. Bill of Materials (VIN =4Vto5.5V,VOUT = 0.9 V, IOUT =8A,FSW = 1 MHz)

REF DES DESCRIPTION VENDOR PART NUMBER QUANTITY

CFCAP, CERM, 1 µF, 10 V, ±10%, X7R, 0603 MuRata GRM188R71A105KA61D 1

CIN1, CO1, CO2 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1206 MuRata GRM31CR60J107ME39L 3

CC1 CAP, CERM, 1800 pF, 50 V, ±5%, C0G/NP0, 0603 MuRata GRM1885C1H182JA01D 1

CC2 CAP, CERM, 68 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1

CC3 CAP, CERM, 470 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H471J 1

CSS CAP, CERM, 0.033 µF, 16 V, ±10%, X7R, 0603 MuRata GRM188R71C333KA01D 1

LFInductor, Shielded Core, 240 nH, 20 A, 1 mΩ, SMD Würth 744314024 1

RFRES, 1 Ω, 5%, 0.1 W, 0603 Vishay Dale CRCW06031R00JNEA 1

RC1 RES, 4.87 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW06034K87FKEA 1

RC2 RES, 210 Ω, 1%, 0.1 W, 0603 Vishay Dale CRCW0603210RFKEA 1

REN1, RFB1, RPGOOD RES, 10 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW060310K0FKEA 3

REN2 RES, 19.6 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW060319K6FKEA 1

RFB2 RES, 20 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW060320K0FKEA 1

U1LM21215A Synchronous Buck Regulator TI LM21215AMH-1/NOPB 1

K˜

OUTOUT

IN VIV

LM21215A

SNOSB87D –MARCH 2011–REVISED MAY 2019

www.ti.com

Product Folder Links: LM21215A

9 Power Supply Recommendations

The LM21215A converter is designed to operate from an input voltage supply range between 2.95 V and 5.5 V.

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and

Recommended Operating Conditions tables. In addition, the input supply must be capable of delivering the

required input current to the fully-loaded regulator. Estimate the average input current with Equation 19, where η

is the efficiency:

(19)

If the converter is connected to an input supply through long wires or PCB traces with large impedance, special

care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may

have an adverse affect on converter operation. The parasitic inductance in combination with the low ESR

ceramic input capacitors form an under-damped resonant circuit. This circuit can cause overvoltage transients at

PVIN each time the input supply is cycled on and off. The parasitic resistance causes the PVIN voltage to dip

during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false

UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the

input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The

moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage

overshoots. A capacitance in the range of 20 µF to 100 µF is usually sufficient to provide input damping and

helps to hold the input voltage steady during large load transients.

An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as

well as some of the effects mentioned above. The user guide Simple Success with Conducted EMI for DC-DC

Converters,SNVA489, provides helpful suggestions when designing an input filter for any switching regulator.

LM21215A

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SNOSB87D –MARCH 2011–REVISED MAY 2019

Product Folder Links: LM21215A

10 Layout

10.1 Layout Guidelines

PC board layout is an important and critical part of any DC-DC converter design. The performance of any

switching converter depends as much upon the layout of the PCB as the component selection. Poor layout

disrupts the performance of a switching converter and surrounding circuitry by contributing to EMI, ground

bounce, conduction loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter,

possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or

voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade

the power-supply performance.

The following guidelines serve to help users to design a PCB with the best power conversion performance,

thermal performance, and minimized generation of unwanted EMI.

1. Locate the input capacitors as close as possible to the PVIN and PGND pins, and place the inductor as close

as possible to the SW pins and output capacitors. As described further in the Compact PCB Layout for EMI

Reduction section, this placement is to minimize the area of switching current loops and reduce the resistive

loss of the high current path. Ideally, use a ground plane on the top layer that connects the PGND pins, the

exposed pad of the device, and the return terminals of the input and output capacitors in a small area near

pins 10 and 11 of the device. For more details, refer to the board layout detailed in application note AN-2131

LM21215A Evaluation Board,SNVA477.

2. Minimize the copper area of the switch node. Route the six SW pins on a single top-layer plane to the

inductor terminal using a wide trace to minimize conduction loss. The inductor can be placed on the bottom

side of the PCB relative to the LM21215A, but take care to avoid any coupling of the inductor's magnetic field

to sensitive feedback or compensation traces.

3. Use a solid ground plane on layer two of the PCB, particularly underneath the LM21215A and power stage

components. This plane functions as a noise shield and also as a heat dissipation path.

4. Make input and output power bus connections as wide and short as possible to reduce voltage drops on the

input and output of the converter and to improve efficiency. Use copper planes on top to connect the multiple

PVIN pins and PGND pins together.

5. Provide enough PCB area for proper heat-sinking. As stated in the Thermal Design section, use enough

copper area to ensure a low RθJA commensurate with the maximum load current and ambient temperature.

Make the top and bottom PCB layers with two ounce copper thickness and no less than one ounce. Use an

array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the

PCB has multiple copper layers as recommended, connect these thermal vias to the inner layer heat-

spreading ground planes.

6. Route the sense trace from the VOUT point of regulation to the feedback resistors away from the SW pins

and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important

when high resistances are used to set the output voltage. Routing the feedback trace on a different layer

than the inductor and SW node trace is recommended such that a ground plane exists between the sense

trace and inductor or SW node polygon to provide further cancellation of EMI on the feedback trace.

7. If voltage accuracy at the load is important, ensure that the feedback voltage sense is made directly at the

load terminals. Doing so corrects for voltage drops in the PCB planes and traces and provides optimal output

voltage setpoint accuracy and load regulation. Place the feedback resistor divider closer to the FB node,

rather than close to the load, because the FB node is the input to the error amplifier and is thus noise

sensitive. COMP is a also noise-sensitive node and the compensation components must be located as close

as possible to the device.

8. Place the AVIN bypass capacitor and the soft-start capacitor close to their respective pins.

9. See Related Documentation for additional important guidelines.

 

OUTJA

OUT V1

1R TT

I˜

K



PVIN

VOUT

GND

LM21215A-1

Low-side

NMOS

gate driver

High-side

PMOS

gate driver

CIN

COUT

PGND

High

di/dt

loop

VIN

LM21215A

SNOSB87D –MARCH 2011–REVISED MAY 2019

www.ti.com

Product Folder Links: LM21215A

Layout Guidelines (continued)

10.1.1 Compact PCB Layout for EMI Reduction

Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

reducing radiated EMI is to identify the pulsing current path and minimize the area of that path. The main

switching loop of the LM21215A power stage is denoted by #1 in Figure 41. The topological architecture of a

buck converter means that particularly high di/dt current flows in loop #1, and it becomes mandatory to reduce

the parasitic inductance of this loop by minimizing its effective loop area. For loop #2 however, the di/dt through

inductor LFand capacitor COUT is naturally limited by the inductor. Keeping the area of loop #2 small is not nearly

as important as that of loop #1. Also important are the gate drive loops of the low-side and high-side MOSFETs,

which are inherently tight by virtue of the integrated power MOSFETs and gate drivers of the LM21215A

Figure 41. LM21215A Power Stage Circuit Switching Loops

High-frequency ceramic bypass capacitors at the input side provide the primary path for the high di/dt

components of the pulsing current. Placing ceramic bypass capacitors as close as possible to the PVIN and

PGND pins is the key to EMI reduction. Keep the SW trace connecting to the inductor as short as possible, and

just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours

(shapes) for current conduction path to minimize parasitic resistance. Place the output capacitors close to the

VOUT side of the inductor and route the return using GND plane copper back to the PGND pins and the exposed

pad of the LM21215A.

10.1.2 Thermal Design

As with any power conversion device, the LM21215A dissipates internal power while operating. The effect of this

power dissipation is to raise the internal junction temperature of the LM21215A above ambient. The junction

temperature (TJ) is a function of the ambient temperature (TA), the power dissipation and the effective thermal

resistance of the device and PCB combination (RθJA). The maximum operating junction temperature for the

LM21215A is 125°C, thus establishing a limit on the maximum device power dissipation and therefore the load

current at high ambient temperatures. Equation 20 shows the relationships between these parameters.

(20)

LM21215A-1 EVALUATION MODULE

LM21215A

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Product Folder Links: LM21215A

Layout Guidelines (continued)

High ambient temperatures and large values of RθJA reduce the maximum available output current. If the junction

temperature exceeds 165°C, the LM21215A cycles in and out of thermal shutdown. Thermal shutdown may be a

sign of inadequate heat-sinking or excessive power dissipation. Improve PCB heat-sinking by using more thermal

vias, a larger board, or more heat-spreading layers within that board.

As stated in application note Semiconductor and IC Package Thermal Metrics,SPRA953, the values given in the

Thermal Information table are not always valid for design purposes to estimate the thermal performance of the

application. The values reported in the Thermal Information table are measured under a specific set of conditions

that are seldom obtained in an actual application. The effective RθJA is a critical parameter and depends on many

factors (such as power dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias

under the package, air flow, and adjacent component placement). The LM21215A uses an advanced flip-chip-on-

lead (FCOL) package and its exposed pad has a direct electrical and thermal connection to PGND. This pad

must be soldered directly to the PCB copper ground plane to provide an effective heat-sink and proper electrical

connection. Use the documents listed in Related Documentation as a guide for optimized thermal PCB design

and estimating RθJA for a given application environment.

10.1.3 Ground Plane Design

As mentioned previously, using one of the middle layers as a solid ground plane is recommended. A ground

plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control

circuitry. Connect the AGND and PGND pins to the ground plane using an array of vias under the exposed pad.

The PGND pins are connected to the source of the integrated low-side power MOSFET. Connect these pins

directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching

frequency and can bounce because of load current variations. The PGND trace, as well as PVIN and SW traces,

must be constrained to one side of the ground plane. The other side of the ground plane contains much less

noise and is ideal for sensitive routes.

10.2 Layout Example

Figure 42. Layout Example Showing Top Layer Copper and Silkscreen

LM21215A

SNOSB87D –MARCH 2011–REVISED MAY 2019

www.ti.com

Product Folder Links: LM21215A

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

For the LM21215A Quickstart Design Tool,gotohttp://www.ti.com/product/LM21215A/toolssoftware#devtools.

For the PowerLab™, go to http://www.ti.com/powerlab.

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM21215A device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

•AN-2131 LM21215A Evaluation Board,SNVA477

•AN-2130 LM21215 Evaluation Board,SNVA476

•AN-2107 LM21212-1 Evaluation Board,SNVA467

•AN-2140 LM21212-2 Evaluation Board,SNVA480

•AN-2162: Simple Success with Conducted EMI from DC-DC Converters,SNVA489

•6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current,

SNVS822

•AN-1149 Layout Guidelines for Switching Power Supplies,SNVA021

•AN-1229 Simple Switcher PCB Layout Guidelines,SNVA054

•Constructing Your Power Supply – Layout Considerations,SLUP230

•Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x,SNVA721

•AN-2020 Thermal Design By Insight, Not Hindsight,SNVA419

•AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages,SNVA183

•SPRA953B Semiconductor and IC Package Thermal Metrics,SPRA953

•SNVA719 Thermal Design made Simple with LM43603 and LM43602,SNVA719

•SLMA002 PowerPAD™ Thermally Enhanced Package,SLMA002

•SLMA004 PowerPAD Made Easy,SLMA004

•SBVA025 Using New Thermal Metrics,SBVA025

LM21215A

www.ti.com

SNOSB87D –MARCH 2011–REVISED MAY 2019

Product Folder Links: LM21215A

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM21215AMH-1/NOPB ACTIVE HTSSOP PWP 20 73 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215

AMH-1

LM21215AMHE-1/NOPB ACTIVE HTSSOP PWP 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215

AMH-1

LM21215AMHX-1/NOPB ACTIVE HTSSOP PWP 20 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LM21215

AMH-1

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM21215AMHE-1/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

LM21215AMHX-1/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM21215AMHE-1/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0

LM21215AMHX-1/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2019

Pack Materials-Page 2

MECHANICAL DATA

PWP0020AA

www.ti.com

MYB20XX (REV E)

4214875/A 02/2013

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

C. Reference JEDEC Registration MO-153, Variation ACT.

NOTES:

IMPORTANT NOTICE AND DISCLAIMER

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