Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
1
About M32C/83 Group
The M32C/83 group of single-chip microcomputers are built using a high-performance silicon gate CMOS
process uses a M32C/80 Series CPU core and are packaged in a 144-pin and 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 16M bytes of address space, they are capable of executing instructions at high speed.
They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,
industrial equipment, and other high-speed processing applications.
Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Index
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error.
Specifications in this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
About M32C/83 Group ..........................................1
Central Processing Unit (CPU) ...........................20
Reset...................................................................24
SFR.....................................................................37
Software Reset ...................................................48
Processor Mode..................................................48
Bus Settings........................................................52
Bus Control .........................................................55
System Clock ......................................................65
Power Saving......................................................76
Protection............................................................81
Interrupt Outline ..................................................83
______
INT Interrupts ...................................................... 98
______
NMI Interrupt .......................................................99
Key Input Interrupt ..............................................99
Address Match Interrupt....................................100
Intelligent I/O and CAN Interrupt.......................101
Precautions for Interrupts..................................104
W atchdog Timer ................................................106
DMAC ...............................................................109
DMAC II ............................................................121
Timer .................................................................129
T imer A..............................................................131
Timer B..............................................................147
Three-phase motor control timers’ functions.....155
Serial I/O ...........................................................168
CAN Module......................................................198
Intelligent I/O.....................................................235
Base timer (group 0 to 3) ..................................240
Time measurement (group 0 and 1)..................247
WG function (group 0 to 3)................................252
Serial I/O (group 0 to 2) ....................................264
A-D Converter ...................................................281
D-A Converter ...................................................296
CRC Calculation Circuit ....................................298
X-Y Converter ................................................... 300
DRAM Controller...............................................303
Programmable I/O Ports ...................................310
VDC ..................................................................334
Usage Precaution .............................................335
Electrical characteristics ...................................344
Outline Performance .........................................381
Flash Memory ...................................................383
CPU Rewrite Mode ...........................................384
Outline Performance of CPU Rewrite Mode .....384
Inhibit Rewriting Flash Memory Version............397
Parallel I/O Mode ..............................................399
Standard serial I/O mode ..................................400
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
2
Performance Outline
Table 1.1.1 and 1.1.2 are performance outline of M32C/83 group.
Table 1.1.1. Performance outline of M32C/83 group (144-pin version) (1/2)
Item Performance
CPU Number of basic instructions 108 instructions
Shortest instruction execution time 33 ns(f(XIN)=30MHz)
Operation mode Single-chip, memory expansion and microprocessor modes
Memory space 16 M bytes
Memory capacity See ROM/RAM expansion figure.
Peripheral function
I/O port 123 pins (P0 to P15 except P85)
Input port 1 pin (P85)
Multifunction timer Output 16 bits x 5 (TA0, TA1, TA2, TA3, TA4)
Input 16 bits x 6 (TB0, TB1, TB2, TB3, TB4, TB5)
Intelligent I/O 4 groups
Time measurement 8 channels (group 0) + 4 channels (group 1)
Waveform generation
4 channels (group 0) + 8 channels X 3 (group 1, 2 and 3)
Bit-modulation PWM 8 channels X 2 (group 2 and 3)
Real time port 8 channels X 2 (group 2 and 3)
Communication function • Clock synchronous serial I/O, UART (group 0 and 1)
• HDLC data process (group 0 and 1)
• Clock synchronous variable length serial I/O (group 2)
• IE bus (Note 1) (group 2)
Serial I/O 5 channels (UART0 to UART4)
IE Bus (Note 1, 3), I2C Bus (Note 2, 3)
CAN module 1 channel, 2.0B specification
A-D converter 10-bit A-D x 2 circuits, standard 18 inputs, max 34 inputs
D-A converter 8-bit D-A x 2 circuits
DMAC 4 channels
DMAC II Start by all variable vector interrupt factor
Immediate transfer, operation transfer and chain transfer function
DRAM controller CAS before RAS refresh, self-refresh, EDO, FP
CRC calculation circuit CRC-CCITT
X-Y converter 16 bits X 16 bits
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 42 internal and 8 external sources, 5 software sources, interrupt
priority level 7 levels
Clock generating circuit 3 built-in clock generation circuits
• Main/sub-clock generating circuit :built-in feedback resistance, and
external ceramic or quartz oscillator
• Ring oscillator for detecting main clock oscillation stop
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
3
Table 1.1.1. Performance outline of M32C/83 group (144-pin version) (2/2)
Electric characteristics
Supply voltage
4.2 to 5.5V (f(X
IN
)=30MHz without wait), 3.0 to 3.6V (f(X
IN
)=20MHz without wait)
Power consumption 26mA (f(XIN)=20MHz without software wait,Vcc=5V)
38mA (f(XIN)=30MHz without software wait,Vcc=5V)
I/O characteristics I/O withstand voltage :5V
I/O current :5mA
Operating ambient temperature –40 to 85oC
Device configuration CMOS high performance silicon gate
Package 144-pin plastic mold QFP
Note 1 :IE Bus is a trademark of NEC corporation.
Note 2 :I2C Bus is a registered trademark of Philips.
Note 3 :This function is executed by using software and hardware.
Table 1.1.2. Performance outline of M32C/83 group (100-pin version) (1/2)
Item Performance
CPU Number of basic instructions 108 instructions
Shortest instruction execution time 33 ns (f(XIN)=30MHz)
Operation mode Single-chip, memory expansion and microprocessor modes
Memory space 16 M bytes
Memory capacity See ROM/RAM expansion figure.
Peripheral function
I/O port 87 pins (P0 to P10 except P85)
Input port 1 pin (P85)
Multifunction timer Output 16 bits x 5 (TA0, TA1, TA2, TA3, TA4)
Input 16 bits x 6 (TB0, TB1, TB2, TB3, TB4, TB5)
Intelligent I/O 4 groups
Time measurement 3 channels (group 0) + 2 channels (group 1)
Waveform generation 2 channels X 2 (group 0 and 3) + 3 channels X 2 (group 1 and 2)
Bit-modulation PWM 3 channels (group 2)
+ 2 channels (group 3)
Real time port 3 channels (group 2)
+ 2 channels (group 3)
Communication function • Clock synchronous serial I/O, UART (group 0 and 1)
• HDLC data process (group 0 and 1)
• Clock synchronous variable length serial I/O (group 2)
• IE bus (Note 1) (group 2)
Serial I/O 5 channels (UART0 to UART4)
IE Bus (Note 1, 3), I2C Bus (Note 2, 3)
CAN module 1 channel, 2.0B specification
A-D converter 10 bits A-Dx 2 circuits, standard 10 inputs, max 26 inputs
D-A converter 8 bits D-A x 2 circuits
DMAC 4 channels
DMAC II Start by all variable vector interrupt factor
Immediate transfer, operation function and chain transfer function
DRAM controller CAS before RAS refresh, self-refresh, EDO, FP
CRC calculation circuit CRC-CCITT
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
4
Table 1.1.2. Performance outline of M32C/83 group (100-pin version) (2/2)
X-Y converter 16 bits X 16 bits
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 42 internal and 8 external sources, 5 software sources, interrupt priority
level 7 levels
Clock generating circuit 3 built-in clock generation circuits
• Main/sub-clock generating circuit :built-in feedback resistance, and
external ceramic or quartz oscillator
• Ring oscillator for detecting main clock oscillation stop
Electric characteristics
Supply voltage
4.2 to 5.5V (f(X
IN
)=30MHz without wait), 3.0 to 3.6V (f(X
IN
)=20MHz without wait)
Power consumption 26mA (f(XIN)=20MHz without software wait,Vcc=5V)
38mA (f(XIN)=30MHz without software wait,Vcc=5V)
I/O characteristics I/O withstand voltage :5V
I/O current :5mA
Operating ambient temperature –40 to 85oC
Device configuration CMOS high performance silicon gate
Package 100-pin plastic mold QFP
Note 1 :IE Bus is a trademark of NEC corporation.
Note 2 :I2C Bus is a registered trademark of Philips.
Note 3 :This function is executed by using software and hardware.
Mitsubishi plans to release the following products in the M32C/83 group:
(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and flash memory version)
100P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)
144P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)
RAM size
(byte) M30835FJGP
M30835MJGP
31K M30833FJGP
M30833MJGP
M30833FJFP
M30833MJFP
20K
10K 128K 192K 256K 512K ROM size
(byte)
Figure 1.1.1. ROM expansion
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
5
The M32C/83 group products currently supported are listed in Table 1.1.3.
Table 1.1.3. M32C/83 group As of Nov. 2001
Type No ROM capacity RAM capacity Package type Remarks
M30835MJGP *** 144P6Q-A
M30833MJGP *** 100P6Q-A Mask ROM version
M30833MJFP *** 100P6S-A
512K 31K
M30835FJGP ** 144P6Q-A
M30833FJGP ** 100P6Q-A Flash memory version
M30833FJFP ** 100P6S-A
** :Under development
*** :Under planning
Figure 1.1.2. Type No., memory size, and package
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM capacity:
J : 512K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Type No. M 3 0 8 3 5 F J – (X X X ) G P
M32C/83 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
6
Pin Configuration and Pin Description
Figure 1.1.3 to 1.1.5 show the pin configurations (top view), Table 1.1.3 list pin names, and Table 1.1.4 list
pin description.
Figure 1.1.3. 144-pin version pin configuration (top view)
SRxD4 / SDA4 / TxD4 / ANEX1 / P9
6
CLK4 / ANEX0 / P9
5
SS4 / RTS4 / CTS4 / TB4
IN
/ DA1 / P9
4
SS3 / RTS3 / CTS3 / TB3
IN
/ DA0 / P9
3
IE
OUT
/ OUTC2
0
/ SRxD3 / SDA3 / TxD3 / TB2
IN
/ P9
2
IE
IN
/ STxD3 / SCL3 / RxD3 / TB1
IN
/ P9
1
CLK3 / TB0
IN
/ P9
0
P14
6
P14
5
P14
4
OUTC1
7
/ INPC1
7
/ P14
3
OUTC1
6
/ INPC1
6
/ P14
2
OUTC1
5
/ P14
1
OUTC1
4
/ P14
0
BYTE
CNVss
V
CONT
/ X
CIN
/ P8
7
X
COUT
/ P8
6
RESET
X
OUT
Vss
X
IN
Vcc
NMI / P8
5
INT2 / P8
4
CAN
IN
/ INT1 / P8
3
CAN
OUT
/ OUTC3
2
/ INT0 / P8
2
OUTC3
0
/ U / TA4
IN
/ P8
1
BE0
IN
/ ISRxD0 / INPC0
2
/ U / TA4
OUT
/ P8
0
CAN
IN
/ ISCLK0 / OUTC0
1
/ INPC0
1
/ TA3
IN
/ P7
7
CAN
OUT
/ BE0
OUT
/ ISTxD0 / OUTC0
0
/ INPC0
0
/ TA3
OUT
/ P7
6
BE1
IN
/ ISRxD1 / OUTC1
2
/ INPC1
2
/ W / TA2
IN
/ P7
5
ISCLK1 / OUTC1
1
/ INPC1
1
/ W / TA2
OUT
/ P7
4
BE1
OUT
/ ISTxD1 / OUTC1
0
/ SS2 / RTS2 / CTS2 / V / TA1
IN
/ P7
3
CLK2 / V / TA1
OUT
/ P7
2
IE
IN
/ ISRxD2 / OUTC2
2
/ STxD2 / SCL2 / RxD2 / TA0
IN
/ TB5
IN
/ P7
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
50
49
48
47
46
45
44
43
42
41
40
39
38
37
56
55
54
53
52
51
62
61
60
59
58
57
68
67
66
65
64
63
72
71
70
69
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
131
132
133
134
135
136
137
138
139
140
141
142
143
144
125
126
127
128
129
130
119
120
121
122
123
124
113
114
115
116
117
118
109
110
111
112
M32C/83 (144P6Q-A)
P1
1
/ D
9
P1
2
/ D
10
P1
3
/ D
11
P1
4
/ D
12
P1
5
/ D
13
/ INT3
P1
6
/ D
14
/ INT4
P1
7
/ D
15
/ INT5
P2
0
/ A
0
( / D
0
) / AN2
0
P2
1
/ A
1
( / D
1
) / AN2
1
P2
2
/ A
2
( / D
2
) / AN2
2
P2
3
/ A
3
( / D
3
) / AN2
3
P2
4
/ A
4
( / D
4
) / AN2
4
P2
5
/ A
5
( / D
5
) / AN2
5
P2
6
/ A
6
( / D
6
) / AN2
6
P2
7
/ A
7
( / D
7
) / AN2
7
Vss
P3
0
/ A
8
( MA
0
) ( / D
8
)
Vcc
P12
0
/ OUTC3
0
P12
1
/ OUTC3
1
P12
2
/ OUTC3
2
P12
3
/ OUTC3
3
P12
4
/ OUTC3
4
P3
1
/ A
9
( MA
1
) ( / D
9
)
P3
2
/ A
10
( MA
2
) ( / D
10
)
P3
3
/ A
11
( MA
3
) ( / D
11
)
P3
4
/ A
12
( MA
4
) ( / D
12
)
P3
5
/ A
13
( MA
5
) ( / D
13
)
P3
6
/ A
14
( MA
6
) ( / D
14
)
P3
7
/ A
15
( MA
7
) ( / D
15
)
P4
0
/ A
16
( MA
8
)
P4
1
/ A
17
( MA
9
)
Vss
P4
2
/ A
18
( MA
10
)
Vcc
P4
3
/ A
19
( MA
11
)
D
8
/ P1
0
AN0
7
/ D
7
/ P0
7
AN0
6
/ D
6
/ P0
6
AN0
5
/ D
5
/ P0
5
AN0
4
/ D
4
/ P0
4
P11
4
OUTC1
3
/ P11
3
BE1
IN
/ ISRxD
1
/ OUTC1
2
/ INPC1
2
/ P11
2
ISCLK1 / OUTC1
1
/ INPC1
1
/ P11
1
BE1
OUT
/ ISTxD1 / OUTC1
0
/ P11
0
AN0
3
/ D
3
/ P0
3
AN0
2
/ D
2
/ P0
2
AN0
1
/ D
1
/ P0
1
AN0
0
/ D
0
/ P0
0
INPC0
7
/ AN15
7
/ P15
7
INPC0
6
/ AN15
6
/ P15
6
OUTC0
5
/ INPC0
5
/ AN15
5
/ P15
5
OUTC0
4
/ INPC0
4
/ AN15
4
/ P15
4
INPC0
3
/ AN15
3
/ P15
3
BE0
IN
/ ISRxD0 / INPC0
2
/ AN15
2
/ P15
2
ISCLK0 / OUTC0
1
/ INPC0
1
/ AN15
1
/ P15
1
Vss
BE0
OUT
/ ISTxD0 / OUTC0
0
/ INPC0
0
/ AN15
0
/ P15
0
Vcc
KI
3
/ AN
7
/ P10
7
KI
2
/ AN
6
/ P10
6
KI
1
/ AN
5
/ P10
5
KI
0
/ AN
4
/ P10
4
AN
3
/ P10
3
AN
2
/ P10
2
AN
1
/ P10
1
AVss
AN
0
/ P10
0
V
REF
AVcc
STxD4 / SCL4 / RxD4 / AD
TRG
/ P9
7
P4
4
/ CS3 / A
20
(MA
12
)
P4
5
/ CS2 / A
21
P4
6
/ CS1 / A
22
P4
7
/ CS0 / A
23
P12
5
/ OUTC3
5
P12
6
/ OUTC3
6
P12
7
/ OUTC3
7
P5
0
/ WRL / WR / CASL
P5
1
/ WRH / BHE / CASH
P5
2
/ RD / DW
P5
3
/ CLK
OUT
/ BCLK / ALE
P13
0
/ OUTC2
4
P13
1
/ OUTC2
5
Vcc
P13
2
/ OUTC2
6
Vss
P13
3
/ OUTC2
3
P5
4
/ HLDA / ALE
P5
5
/ HOLD
P5
6
/ ALE / RAS
P5
7
/ RDY
P13
4
/ OUTC2
0
/ ISTxD2 / IE
OUT
P13
5
/ OUTC2
2
/ ISRxD2 / IE
IN
P13
6
/ OUTC2
1
/ ISCLK2
P13
7
/ OUTC2
7
P6
0
/ CTS0 / RTS0 / SS0
P6
1
/ CLK0
P6
2
/ RxD0 / SCL0 / STxD0
P6
3
/ TxD0 / SDA0 / SRxD0
P6
4
/ CTS1 / RTS1 / SS1 / OUTC2
1
/ ISCLK2
P6
5
/ CLK1
Vss
P6
6
/ RxD1 / SCL1 / STxD1
Vcc
P6
7
/ TxD1 / SDA1 / SRxD1
P7
0
/ TA0
OUT
/ TxD2 / SDA2 / SRxD2
/ OUTC2
0
/ ISTxD2 / IE
OUT
Note: P7
0
and P7
1
are N-channel open drain output.
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
7
Table 1.1.4. 144-pin version pin description (1/3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Control
BYTE
CNV
SS
X
CIN
/V
CONT
X
COUT
RESET
X
OUT
V
SS
X
IN
V
CC
V
CC
V
SS
Port
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
P14
6
P14
5
P14
4
P14
3
P14
2
P14
1
P14
0
P8
7
P8
6
P8
5
P8
4
P8
3
P8
2
P8
1
P8
0
P7
7
P7
6
P7
5
P7
4
P7
3
P7
2
P7
1
P7
0
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
P13
7
NMI
INT2
INT1
INT0
Timer
TB4
IN
TB3
IN
TB2
IN
TB1
IN
TB0
IN
TA4
IN
/U
TA4
OUT
/U
TA3
IN
TA3
OUT
TA2
IN
/W
TA2
OUT
/W
TA1
IN
/V
TA1
OUT
/V
TB5IN/TA0IN
TA0
OUT
UART/CAN
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
CAN
IN
CAN
OUT
CAN
IN
CAN
OUT
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
OUTC2
0
/IE
OUT
IE
IN
INPC1
7
/OUTC1
7
INPC1
6
/OUTC1
6
OUTC1
5
OUTC1
4
OUTC3
2
OUTC3
0
INPC0
2
/ISRxD0/BE0
IN
INPC0
1
/OUTC0
1
/ISCLK0
INPC0
0
/OUTC0
0
/ISTxD0/BE0
OUT
INPC1
2
/OUTC1
2
/ISRxD1/BE1
IN
INPC1
1
/OUTC1
1
/ISCLK1
OUTC1
0
/ISTxD1/BE1
OUT
OUTC2
2
/ISRxD2/IE
IN
OUTC2
0
/ISTxD2/IE
OUT
OUTC2
1
/ISCLK2
OUTC2
7
ANEX1
ANEX0
DA1
DA0
Intelligent I/O Bus controlAnalog
Interrupt
Pin
No
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
8
Table 1.1.5. 144-pin version pin description (2/3)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Control
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
Port
P13
6
P13
5
P13
4
P5
7
P5
6
P5
5
P5
4
P13
3
P13
2
P13
1
P13
0
P5
3
P5
2
P5
1
P5
0
P12
7
P12
6
P12
5
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P12
4
P12
3
P12
2
P12
1
P12
0
P3
0
P2
7
P2
6
P2
5
Timer UART/CAN
OUTC2
1
/ISCLK2
OUTC2
2
/ISRxD2/IE
IN
OUTC2
0
/ISTxD2/IE
OUT
OUTC2
3
OUTC2
6
OUTC2
5
OUTC2
4
OUTC3
7
OUTC3
6
OUTC3
5
OUTC3
4
OUTC3
3
OUTC3
2
OUTC3
1
OUTC3
0
AN3
7
AN3
6
AN3
5
RDY
ALE/RAS
HOLD
HLDA/ALE
CLK
OUT
/BCLK/ALE
RD/DW
WRH/BHE/CASH
WRL/WR/CASL
CS0/A
23
CS1/A
22
CS2/A
21
CS3/A
20
(MA
12
)
A
19
(MA
11
)
A
18
(MA
10
)
A
17
(MA
9
)
A
16
(MA
8
)
A
15
(MA
7
)(/D
15
)
A
14
(MA
6
)(/D
14
)
A
13
(MA
5
)(/D
13
)
A
12
(MA
4
)(/D
12
)
A
11
(MA
3
)(/D
11
)
A
10
(MA
2
)(/D
10
)
A
9
(MA
1
)(/D
9
)
A
8
(MA
0
)(/D
8
)
A
7
(/D
7
)
A
6
(/D
6
)
A
5
(/D
5
)
Intelligent I/O Bus controlAnalog
Interrupt
Pin
No
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
9
Table 1.1.6. 144-pin version pin description (3/3)
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Control
V
SS
V
CC
AV
SS
V
REF
AV
CC
Port
P2
4
P2
3
P2
2
P2
1
P2
0
P1
7
P1
6
P1
5
P1
4
P1
3
P1
2
P1
1
P1
0
P0
7
P0
6
P0
5
P0
4
P11
4
P11
3
P11
2
P11
1
P11
0
P0
3
P0
2
P0
1
P0
0
P15
7
P15
6
P15
5
P15
4
P15
3
P15
2
P15
1
P15
0
P10
7
P10
6
P10
5
P10
4
P10
3
P10
2
P10
1
P10
0
P9
7
INT5
INT4
INT3
KI
3
KI
2
KI
1
KI
0
Timer UART/CAN
RxD4/SCL4/STxD4
AN2
4
AN2
3
AN2
2
AN2
1
AN2
0
AN0
7
AN0
6
AN0
5
AN0
4
AN0
3
AN0
2
AN0
1
AN0
0
AN15
7
AN15
6
AN15
5
AN15
4
AN15
3
AN15
2
AN15
1
AN15
0
AN
7
AN
6
AN
5
AN
4
AN
3
AN
2
AN
1
AN
0
AD
TRG
A
4
(/D
4
)
A
3
(/D
3
)
A
2
(/D
2
)
A
1
(/D
1
)
A
0
(/D
0
)
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Bus control
AnalogInterrupt
Pin
No Intelligent I/O
OUTC1
3
INPC1
2
/OUTC1
2
/ISRxD1/BE1
IN
INPC1
1
/OUTC1
1
/ISCLK1
OUTC1
0
/ISTxD1/BE1
OUT
INPC0
7
INPC0
6
INPC0
5
/OUTC0
5
INPC0
4
/OUTC0
4
INPC0
3
INPC0
2
/ISRxD0/BE0
IN
INPC0
1
/OUTC0
1
/ISCLK0
INPC0
0
/OUTC0
0
/ISTxD0/BE0
OUT
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
10
Figure 1.1.4. 100-pin version pin configuration (top view)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / OUTC32 / INT0 / P82
OUTC30 / U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70
P44 / CS3 / A20 (MA12)
P45 / CS2 / A21
P46 / CS1 / A22
P47 / CS0 / A23
P50 / WRL / WR / CASL
P51 / WRH / BHE / CASH
P52 / RD / DW
P53 / CLKOUT / BCLK / ALE
P54 / HLDA / ALE
P55 / HOLD
P56 / ALE / RAS
P57 / RDY
P60 / CTS0 / RTS0 / SS0
P61 / CLK0
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
P65 / CLK1
P66 / RxD1 / SCL1 / STxD1
P67 / TxD1 / SDA1 / SRxD1
P10 / D8
P11 / D9
P12 / D10
P13 / D11
P14 / D12
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27
Vss
P30 / A8 ( MA0 ) ( / D8 )
Vcc
P31 / A9 ( MA1 ) ( / D9 )
P32 / A10 ( MA2 ) ( / D10 )
P33 / A11 ( MA3 ) ( / D11 )
P34 / A12 ( MA4 ) ( / D12 )
P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
P42 / A18 ( MA10 )
P43 / A19 ( MA11 )
D7 / AN07 / P07
D6 / AN06 / P06
D5 / AN05 / P05
D4 / AN04 / P04
D3 / AN03 / P03
D2 / AN02 / P02
D1 / AN01 / P01
D0 / AN00 / P00
KI3 / AN7 / P107
KI2 / AN6 / P106
KI1 / AN5 / P105
KI0 / AN4 / P104
AN3 / P103
AN2 / P102
AN1 / P101
AVss
AN0 / P100
VREF
AVcc
RxD4 / ADTRG / P97
STxD4 / SCL4 /
M32C/83 (100P6S-A)
Note: P70 and P71 are N-channel open drain output.
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
11
Figure 1.1.5. 100-pin version pin configuration (top view)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
30
29
28
27
26
76
77
78
79
80
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SS4 / RTS4 / CTS4 / TB4
IN
/ DA1 / P9
4
SS3 / RTS3 / CTS3 / TB3
IN
/ DA0 / P9
3
IE
OUT
/ OUTC2
0
/ SRxD3 / SDA3 / TxD3 / TB2
IN
/ P9
2
IE
IN
/ STxD3 / SCL3 / RxD3 / TB1
IN
/ P9
1
CLK3 / TB0
IN
/ P9
0
BYTE
CNVss
V
CONT
/ X
CIN
/ P8
7
X
COUT
/ P8
6
RESET
X
OUT
Vss
X
IN
Vcc
NMI / P8
5
INT2 / P8
4
CAN
IN
/ INT1 / P8
3
CAN
OUT
/ OUTC3
2
/ INT0 / P8
2
OUTC3
0
/ U / TA4
IN
/ P8
1
BE0
IN
/ ISRxD0 /INPC0
2
/ U / TA4
OUT
/ P8
0
CAN
IN
/ ISCLK0 / OUTC0
1
/ INPC0
1
/ TA3
IN
/ P7
7
CAN
OUT
/ BE0
OUT
/ ISTxD0 / OUTC0
0
/ INPC0
0
/ TA3
OUT
/ P7
6
BE1
IN
/ ISRxD1 / OUTC1
2
/ INPC1
2
/ W / TA2
IN
/ P7
5
ISCLK1 / OUTC1
1
/ INPC1
1
/ W / TA2
OUT
/ P7
4
BE1
OUT
/ ISTxD1 / OUTC1
0
/ SS2 / RTS2 / CTS2 / V / TA1
IN
/ P7
3
P4
2
/ A
18
( MA
10
)
P4
3
/ A
19
( MA
11
)
P4
4
/ CS3 / A
20
(MA
12
)
P4
5
/ CS2 / A
21
P4
6
/ CS1 / A
22
P4
7
/ CS0 / A
23
P5
0
/ WRL / WR / CASL
P5
1
/ WRH / BHE / CASH
P5
2
/ RD / DW
P5
3
/ CLK
OUT
/ BCLK / ALE
P5
4
/ HLDA / ALE
P5
5
/ HOLD
P5
6
/ ALE / RAS
P5
7
/ RDY
P6
0
/ CTS0 / RTS0 / SS0
P6
1
/ CLK0
P6
2
/ RxD0 / SCL0 / STxD0
P6
3
/ TxD0 / SDA0 / SRxD0
P6
4
/ CTS1 / RTS1 / SS1 / OUTC2
1
/ ISCLK2
P6
5
/ CLK1
P6
6
/ RxD1 / SCL1 / STxD1
P6
7
/ TxD1 / SDA1 / SRxD1
P7
0
/ TA0
OUT
/ TxD2 / SDA2 / SRxD2 / OUTC2
0
P7
1
/ TA0
IN
/ TB5
IN
/ RxD2 / SCL2
/ STxD2 / OUTC2
2
P7
2
/ TA1
OUT
/ V / CLK2
P1
3
/ D
11
P1
4
/ D
12
P1
5
/ D
13
/ INT3
P1
6
/ D
14
/ INT4
P1
7
/ D
15
/ INT5
P2
0
/ A
0
( / D
0
) / AN2
0
P2
1
/ A
1
( / D
1
) / AN2
1
P2
2
/ A
2
( / D
2
) / AN2
2
P2
3
/ A
3
( / D
3
) / AN2
3
P2
4
/ A
4
( / D
4
) / AN2
4
P2
5
/ A
5
( / D
5
) / AN2
5
P2
6
/ A
6
( / D
6
) / AN2
6
P2
7
/ A
7
( / D
7
) / AN2
7
Vss
P3
0
/ A
8
( MA
0
) ( / D
8
)
Vcc
P3
1
/ A
9
( MA
1
) ( / D
9
)
P3
2
/ A
10
( MA
2
) ( / D
10
)
P3
3
/ A
11
( MA
3
) ( / D
11
)
P3
4
/ A
12
( MA
4
) ( / D
12
)
P3
5
/ A
13
( MA
5
) ( / D
13
)
P3
6
/ A
14
( MA
6
) ( / D
14
)
P3
7
/ A
15
( MA
7
) ( / D
15
)
P4
0
/ A
16
( MA
8
)
P4
1
/ A
17
( MA
9
)
D
10
/ P1
2
D
9
/ P1
1
D
8
/ P1
0
D
7
/ AN0
7
/ P0
7
D
6
/ AN0
6
/ P0
6
D
5
/ AN0
5
/ P0
5
D
4
/ AN0
4
/ P0
4
D
3
/ AN0
3
/ P0
3
D
2
/ AN0
2
/ P0
2
D
1
/ AN0
1
/ P0
1
D
0
/ AN0
0
/ P0
0
KI
3
/ AN3
7
/ P10
7
KI
2
/ AN3
6
/ P10
6
KI
1
/ AN3
5
/ P10
5
KI
0
/ AN3
4
/ P10
4
AN3
3
/ P10
3
AN3
2
/ P10
2
AN3
1
/ P10
1
AVss
AN3
0
/ P10
0
V
REF
AVcc
STxD4 / SCL4 / RxD4 / AD
TRG
/ P9
7
SRxD4 / SDA4 / TxD4 / ANEX1 / P9
6
CLK4 / ANEX0 / P9
5
/ ISRxD2 / IE
IN
/ ISTxD2 / IE
OUT
M32C/83 (100P6Q-A)
Note: P7
0
and P7
1
are N-channel open drain output.
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
12
Table 1.1.7. 100-pin version pin description (1/2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE
CNV
SS
XCIN/VCONT
X
COUT
RESET
X
OUT
V
SS
X
IN
V
CC
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
P8
7
P8
6
P8
5
P8
4
P8
3
P8
2
P8
1
P8
0
P7
7
P7
6
P7
5
P7
4
P7
3
P7
2
P7
1
P7
0
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
P4
7
P4
6
P4
5
P4
4
NMI
INT2
INT1
INT0
TB4
IN
TB3
IN
TB2
IN
TB1
IN
TB0
IN
TA4
IN
/U
TA4
OUT
/U
TA3
IN
TA3
OUT
TA2
IN
/W
TA2
OUT
/W
TA1
IN
/V
TA1
OUT
/V
TB5
IN
/TA0
IN
TA0
OUT
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
CAN
IN
CAN
OUT
CAN
IN
CAN
OUT
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
OUTC2
0
/IE
OUT
IE
IN
OUTC3
2
OUTC3
0
INPC0
2
/ISRxD0/BE0
IN
INPC0
1
/OUTC0
1
/ISCLK0
INPC0
0
/OUTC0
0
/ISTxD0/BE0
OUT
INPC1
2
/OUTC1
2
/ISRxD1/BE1
IN
INPC1
1
/OUTC1
1
/ISCLK1
OUTC1
0
/ISTxD1/BE1
OUT
OUTC2
2
/ISRxD2/IE
IN
OUTC2
0
/ISTxD2/IE
OUT
OUTC2
1
/ISCLK2
ANEX1
ANEX0
DA1
DA0
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RDY
ALE/RAS
HOLD
HLDA/ALE
CLKOUT/BCLK/ALE
RD/DW
WRH/BHE/CASH
WRL/WR/CASL
CS0/A
23
CS1/A
22
CS2/A
21
CS3/A
20
(MA
12
)
Package
Pin No
FP GP Control Port Timer UART/CAN Intelligent I/O Bus controlAnalogInterrupt
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
13
Table 1.1.8. 100-pin version pin description (2/2)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Control
VCC
VSS
AVSS
VREF
AVCC
Port
P43
P42
P41
P40
P37
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
P107
P106
P105
P104
P103
P102
P101
P100
P97
Timer UART/CAN
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN07
AN06
AN05
AN04
AN03
AN02
AN01
AN00
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
ADTRG
A19(MA11)
A18(MA10)
A17(MA9)
A16(MA8)
A15(MA7)(/D15)
A14(MA6)(/D14)
A13(MA5)(/D13)
A12(MA4)(/D12)
A11(MA3)(/D11)
A10(MA2)(/D10)
A9(MA1)(/D9)
A8(MA0)(/D8)
A7(/D7)
A6(/D6)
A5(/D5)
A4(/D4)
A3(/D3)
A2(/D2)
A1(/D1)
A0(/D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Intelligent I/O Bus controlAnalogInterrupt
INT5
INT4
INT3
KI3
KI2
KI1
KI0
RxD4/SCL4/STxD4
FP GP
Package
pin No
Under
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
14
Table 1.1.9. Pin description (1/4)
Function
I/O port
I/O port
I/O port
I/O port
Description
An 8-bit CMOS I/O port.
It has an input/output port direction register that allows the
user to set each pin for input or output individually.
The user can specify in units of four bits via software whether
or not they are tied to a pull-up resistor.
When set as a separate bus, these pins input and output 8
low-order data bits.
This is an 8-bit I/O port equivalent to P0.
When set as a separate bus, these pins input and output 8
high-order data bits.
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits.
If a multiplexed bus is set, these pins input and output data and
output 8 low-order address bits separated in time by
multiplexing.
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits.
If the external bus is set as a 16-bit wide multiplexed bus,
these pins output 8 middle-order address bits, and input and
output 8 middle-order data separated in time by multiplexing.
I/O
I/O
I/O
I/O
I/O type
I/O
O
I/O
I/O
O
I/O
P00 to P07
D0 to D7
P10 to P17
D8 to D15
P20 to P27
A0 to A7
A0/D0 to
A7/D7
P30 to P37
A8 to A15
A8/D8 to
A15/D15
Pin name
MA0 to MA7 If accessing to DRAM area, these pins output row address
and column address separated in time by multiplexing.
O
P0
P1
P2
P3
Port
Data bus
Data bus
Address bus
Address bus/data bus
Address bus
Address bus/data bus
P15 to P17 function as external interrupt pins.
External interrupt input
port I
INT3 to INT5
Address bus
I/O port This is an 8-bit I/O port equivalent to P0.
I/O
O
O
P40 to P47
A16 to A22
A23
Chip select
MA8 to MA12 O
P4
Address bus
Address bus
CS0 to CS3P40 to P47 are chip select output pins to specify access area.
These pins output 8 high-order address bits.
Highest address bit (A23) outputs inversely.
If accessing to DRAM area, these pins output row address and
column address separated in time by multiplexing.
P00 to P07 are analog input ports for the A-D converter.IAN00 to AN07
Analog input port
P20 to P27 are analog input ports for the A-D converter.IAN20 to AN27
Analog input port
VCC
VSS
CNVSS
XIN
XOUT
BYTE
AVCC
AVSS
VREF
4.2 to 5.5 V or 3.0V to 3.6V.
0 V.
Connect it to VSS : Single-chip or memory expansion mode
Connect it to VCC : Microprocessor mode
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the XIN and
the XOUT pins. To use an externally derived clock, input it to
the XIN pin and leave the XOUT pin open.
Selects the width of the data bus for external memory.
Connect it to VSS : A 16-bit width
Connect it to VCC : An 8-bit width
Connect this pin to VCC.
Connect this pin to VSS.
This pin is a reference voltage input for the A-D converter.
I
I
I
O
I
I
Power supply
input
CPU mode switch
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Reference
voltage input
RESET
I
I
I
I
Under
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
15
Table 1.1.10. Pin description (2/4)
Function
I/O port
Bus control
UART port
Timer A port
Description
I/O
O
I/O
I/O
I/O type
I/O
O
I
I/O
I/O
I
I/O
O
I
P5
0
to P5
7
CLK
OUT
OUTC/ISCLK
TA
OUT
TA
IN
TB
IN
INPC/OUTC
ISCLK/ISTxD/
ISRxD
IE
OUT
/IE
IN
BE
OUT
/BE
IN
CAN
Pin name
V, V
W, W O
P5
P6
P7
Port
Clock output
I/O port
Intelligent I/O port
I/O port
Timer B port
Three phase motor
control output port
Bus control for DRAM
P6
0
to P6
7
P7
0
to P7
7
This is an 8-bit I/O port equivalent to P0.
P6
0
to P6
3
are I/O ports for UART0.
P6
4
to P6
7
are I/O ports for UART1.
This is an 8-bit I/O port equivalent to P0.
However, P7
0
and P7
1
are N-channel open drain outputs.
WRL / WR,
WRH / BHE,
RD
ALE,
RDY
Output WRL, WRH and RD, or WR, BHE and RD bus control
signals.
WRL, WRH, and RD selected
In 16-bit data bus, data is written to even addresses when the
WRL signal is “L”.
Data is written to odd addresses when the WRH signal is “L”.
Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”.
Data is read when RD is “L”.
Odd addresses are accessed when BHE is “L”. Even
addresses are accessed when BHE is “H”.
Use WR, BHE, and RD when all external memory is an 8-bit
data bus.
Output operation clock for CPU.
While the input level at the HOLD pin is “L”, the microcomputer
is placed in the hold state.
While in the hold state, HLDA outputs a “L” level.
ALE is used to latch the address.
While the input level of the RDY pin is “L”, the microcomputer
is in the ready state.
DW,
CASL,
CASH,
RAS
When DW signal is “L”, write to DRAM.
Timing signal when latching to line address of even address.
Timing signal when latching to line address of odd address.
Timing signal when latching to row address.
P5
3
in this port outputs a divide-by-8 or divide-by-32 clock of
X
IN
or a clock of the same frequency as X
CIN
.
BCLK,
HOLD,
HLDA
O
O
O
I
O
I
O
O
O
O
O
This is an 8-bit I/O port equivalent to P0.
I/O
ISCLK is a clock I/O port for intelligent I/O communication.
OUTC is an output port for waveform generation function.
P7
0
to P7
7
are I/O ports for timers A0–A3.
P7
1
is an input port for timer B5.
P7
2
and P7
3
are V phase outputs.
P7
4
and P7
5
are W phase outputs.
P7
0
to P7
3
are I/O ports for UART2.
INPC is an input port for time measurement function.
OUTC is an output port for waveform generation function.
ISCLK is a clock I/O port for intelligent I/O communication.
ISTxD/IE
OUT
/BE
OUT
is transmit data output port for intelligent
I/O communication.
ISRxD/IE
IN
/BE
IN
is receive data input port for intelligent I/O
communication.
P7
6
and P7
7
are I/O ports for CAN communication function.
CTS/RTS/SS
CLK
RxD/SCL/STxD
TxD/SDA/SRxD
UART port CTS/RTS/SS
CLK
RxD/SCL/STxD
TxD/SDA/SRxD
Intelligent I/O port
CAN
OUT
CAN
IN
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
16
Table 1.1.11. Pin description (3/4)
Function
I/O port
UART port
Description
I/O
O
I/O
I
I/O type
P8
0
-P8
4
, P8
6
, P8
7
INPC/ISRxD/BE
IN
Pin name
P8
P9
Port
I/O port
Intelligent I/O port
P9
0
to P9
7
This is a 7-bit I/O port equivalent to P0.
P9
0
to P9
3
are I/O ports for UART3.
P9
4
to P9
7
are I/O ports for UART4.
I
This is an 8-bit I/O port equivalent to P0.
I/O
INPC is an input port for time measurement function.
ISRxD/BE
IN
is receive data input port for intelligent I/O
communication.
CTS/RTS/SS
CLK
RxD/SCL/STxD
TxD/SDA/SRxD
Timer A port
Three phase motor
control output port
P8
0
to P8
1
are I/O ports for timer A4.
P8
0
and P8
1
are U phase output ports.
O
I
TA4
OUT
TA4
IN
External interrupt input
port P8
2
to P8
4
are external interrupt input ports.
IINT
0
to INT
2
Input port P8
5
/NMI Input port and input ports for NMI interrupt.
I
TB0
IN
to TB4
IN
Timer B port P9
0
to P9
4
are input port for timer B4.
O
DA0, DA1
D-A output port P9
3
and P9
4
are D-A output ports.
I
I
ANEX1, ANEX2
AD
TRG
A-D related port P9
5
to P9
6
are expanded input port for A-D converter.
P9
7
is A-D trigger input port.
Intelligent I/O port OUTC is an output port for waveform generation function.
IE
OUT
is transmit data output port for intelligent I/O
communication.
IE
IN
is receive data input port for intelligent I/O
communication.
OUTC/IE
OUT
IE
IN
Key input interrupt port I
I/O
I
KI
0
to KI
3
AN
0
to AN
7
P10 I/O port
Analog input port
P10
0
to P10
7
This is an 8-bit I/O port equivalent to P0.
P10
4
to P10
7
are key input interrupt ports.
P10
0
to P10
7
are analog input ports for A-D convertor.
The protect register prevents a false write to P9 direction register and function select register A3.
U, U
I/O
I
I/O
I/O
I/O
X
CIN
X
COUT
P8
6
and P8
7
function as I/O ports for the sub clock
generating circuit by software. Connect a crystal between
the X
CIN
and the X
COUT
pins.
I
O
Sub clock input
Sub clock output
V
COUT
When using PLL frequency synthesizer, connect P8
7
to a
low-pass filter. To stabilize PLL frequency, connect P8
6
to
Vss.
O
Low-pass filter connect
pin for PLL frequency
synthesizer
Under
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
17
Table 1.1.12. Pin description (4/4)
Function DescriptionI/O type
INPC/OUTC
ISCLK/ISTxD/
ISRxD
BEOUT/BEIN
Pin namePort
Intelligent I/O port I/O
INPC/OUTC
ISCLK
ISTxD/ISRxD
BEOUT/BEIN
P11 I/O port P110 to P114This is an 5-bit I/O port equivalent to P0.
INPC is an input port for time measurement function.
OUTC is an output port for waveform generation function.
ISCLK is a clock I/O port for intelligent I/O communication.
ISTxD/BEOUT is transmit data output port for intelligent I/O
communication.
ISRxD/BEIN is receive data input port for intelligent I/O
communication.
Intelligent I/O port O
I/O
OUTC
P12 I/O port P120 to P127This is an 8-bit I/O port equivalent to P0.
OUTC is an output port for waveform generation function.
Intelligent I/O port I/O
I/O
OUTC
ISCLK/ISTxD/
ISRxD
IEOUT/IEIN
P13 I/O port P130 to P137This is an 8-bit I/O port equivalent to P0.
OUTC is an output port for waveform generation function.
ISCLK is a clock I/O port for intelligent I/O communication.
ISTxD/IEOUT is transmit data output port for intelligent I/O
communication.
ISRxD/IEIN is receive data input port for intelligent I/O
communication.
Intelligent I/O port I/O
I/O
INPC/OUTC
P14 I/O port P140 to P146This is a 7-bit I/O port equivalent to P0.
INPC is an input port for time measurement function.
OUTC is an output port for waveform generation function.
Intelligent I/O port I/O
I/O
P15 I/O port P150 to P157This is an 8-bit I/O port equivalent to P0.
INPC is an input port for time measurement function.
OUTC is an output port for waveform generation function.
ISCLK is a clock I/O port for intelligent I/O communication.
ISTxD/BEOUT is transmit data output port for intelligent I/O
communication.
ISRxD/BEIN is receive data input port for intelligent I/O
communication.
I
AN150 to AN157
Analog input port P150 to P157 are analog input ports for A-D convertor.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note :Port P11 to P15 exist in 144-pin version.
(Note)
(Note)
(Note)
(Note)
(Note)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
18
Block Diagram
The M32C/83 group includes the following devices in a single-chip. ROM and RAM for code instructions
and data, storage, CPU for executing operation and peripheral functions such as timer, serial I/O, D-A
converter, DMAC, CRC operation circuit, A-D converter, DRAM controller, intelligent I/O and I/O ports.
Figure 1.1.6 is a block diagram of the M32C/83 group (144-pin version).
Figure 1.1.6. Block diagram of the M32C/83 group (144-pin version)
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7
Port P15 Port P14 Port P13 Port P12 Port P11 Port P10 Port P9 Port P8
P8
5
Timer (16 bits)
Input (6)
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Output (5)
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Three-phase control
circuit
Watchdog timer (15 bits)
Intelligent I/O
Group 0
Group 1
Group 2
Group 3
D-A converter
(8-bit X 2 circuit)
A-D converter
(10-bit X 2 circuits)
UART/Clock synchronous
SI/O
(8-bit X 5 channels)
X-Y converter
(16-bit X 16-bit)
CRC arithmetic circuit
(CCITT)
System clock generator
XIN - XOUT
XCIN - XCOUT
Ring oscillator
Memory (Note)
ROM
RAM
Internal peripheral functions
M32C/80 series CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
FLG
INTB
ISP
USP
PCSVF
SVP
VCT
DMA
controller
DMA II
controller
DRAM
controller
Multiplier
I/O ports
88888888
8788588 7
CAN communication
function
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
19
Memory
Figure 1.2.1 is a memory map of the M32C/83 group. The address space extends 16 Mbytes from address
00000016 to FFFFFF16. From FFFFFF16 down is ROM. For example, in the M30835FJGP, there are 512K
bytes of internal ROM from F8000016 to FFFFFF16. The vector table for fixed interrupts such as the reset
_______
and NMI are mapped to FFFFDC16 to FFFFFF16. The starting address of the interrupt routine is stored
here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 00040016 up is RAM. For example, in the M30835FJGP, 31 Kbytes of internal RAM are mapped to
the space from 00040016 to 007FFF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped from 00000016 to 0003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area
that is not occupied is reserved and cannot be used for any other purpose.
The special page vector table is mapped from FFFE0016 to FFFFDB16. If the starting addresses of subrou-
tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc-
tions can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used.
Figure 1.2.1. Memory map
000000
16
YYYYYY
16
FFFFFF
16
000400
16
008000
16
XXXXXX
16
F00000
16
AAAAA
A
AAA
A
A
AAA
A
AAAAA
External area
Internal ROM
area
Internal RAM
area
Internal reserved
area (Note 1)
Internal reserved
area (Note 2)
FFFE00
16
FFFFDC
16
FFFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer
Reset
Special page
vector table
NMI
SFR area
Address
XXXXX
16
F80000
16
007FFF
16
M30835F/MJ
Type No. Address
YYYYY
16
M30833F/MJ
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
20
Central Processing Unit (CPU)
The CPU has a total of 28 registers shown in Figure 1.3.1. Eight of these registers (R0, R1, R2, R3, A0, A1,
SB and FB) come in two sets; therefore, these have two register banks.
Figure 1.3.1. Central processing unit register
b23
b7 b0
Flag register
Address register (Note)
Static base register (Note)
Frame base register (Note)
User stack pointer
Interrupt stack pointer
Interrupt table register
Flag save register
PC save register
Vector register
DMA mode register
DMA transfer count register
DMA transfer count reload register
DMA memory address register
DMA SFR address register
DMA memory address reload register
b15 b0
b15 b0
b23
b15
b23
Data register (Note)
FLG
R0H
R1H
R2
R3
A0
A1
SB
FB
USP
ISP
INTB
PC
SVF
VCT
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
SVP
DMAC related register
Program counter
R2
R3
High-speed interrupt register
General register
b31
R0L
R1L
Note: These registers have two register banks.
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
21
Processor Mode
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can function as 32-bit data
registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also function as address register, indirect addressing and address register
relative addressing.
(3) Static base register (SB)
Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.
(4) Frame base register (FB)
Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.
(5) Program counter (PC)
Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.
(6) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.
(7) User stack pointer (USP), interrupt stack pointer (ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
The desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This
flag is located at bit 7 in the flag register (FLG).
To execute efficienly set USP and ISP to an even number.
(8) Save flag register (SVF)
This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.
(9) Save PC register (SVP)
This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is
generated.
This register consist of 24 bits and is used to indicate a jump address when a high-speed interrupt is
generated.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
22
Processor Mode
(10) Vector register (VCT)
This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is
generated.
(11) DMA mode registers (DMD0/DMD1)
These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA.
(12) DMA transfer count registers (DCT0/DCT1)
These registers consist of 16 bits and are used to set the number of DMA transfers performed.
(13) DMA transfer count reload registers (DRC0/DRC1)
These registers consist of 16 bits and are used to reload the DMA transfer count registers.
(14) DMA memory address registers (DMA0/DMA1)
These registers consist of 24 bits and are used to set a memory address at the source or destination of
DMA transfer.
(15) DMA SFR address registers (DSA0/DSA1)
These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA
transfer.
(16) DMA memory address reload registers (DRA0/DRA1)
These registers consist of 24 bits and are used to reload the DMA memory address registers.
(17) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.3.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
23
Processor Mode
Processor Mode
• Bit 4: Register bank select flag (B)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Numbers. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
AA
AA
AA
AA
AA
AA
A
A
AAAAAAA
AAAAAAA
AA
AA
AA
AA
A
A
AA
AA
AA
AA
CDZSBOIU
IPL
b0b15
Figure 1.3.2. Flag register (FLG)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
24
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is enabled by holding the
reset pin Low (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to High while
main clock is stable, the reset status is cancelled and program execution resumes from the address in the
reset vector table.
Since the value of RAM is indeterminate when power is applied, the initial values must be set. Also, if a
reset signal is input during write to RAM, the access to the RAM will be interrupted. Consequently, the value
of the RAM being written may change to an unintended value due to the interruption.
Figure 1.4.1 shows the example reset circuit. Figure 1.4.2 shows the reset sequence.
____________
Table 1.4.1 shows the status of other pins while the RESET pin level is Low. Figures 1.4.3 and 1.4.4 show
the internal status of the microcomputer immediately after the reset is cancelled.
RESET VCC
0.8V
RESET
VCC
0V
0V
5V
5V
4.2V
Example when VCC = 5V
.
Figure 1.4.1. Example reset circuit
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
25
BCLK
X
IN
RESET
RD
WR
CS0
RD
WR
CS0
Address
Address
Address
Microprocessor
mode BYTE = “H”
Microprocessor
mode BYTE = “L”
Content of reset vector
Single chip
mode
BCLK 24cycles
FFFFC
16
FFFFD
16
FFFFE
16
Content of reset vector
FFFFE
16
Content of reset vector
FFFFE
16
FFFFC
16
More than 20 cycles are needed
FFFFC
16
Figure 1.4.2. Reset sequence
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
26
Status
CNV
SS
= V
CC
CNV
SS
= V
SS
BYTE = V
SS
BYTE = V
CC
Pin name
P0
P1
P2, P3, P4
P5
0
P5
1
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (undefined)
BCLK output
RAS output
WR output (“H” level output)
RD output (“H” level output)
RDY input (floating)
Input port (floating)
BHE output (undefined)
HLDA output (The output value depends on the input to the
HOLD pin)
HOLD input (floating)
Input port (floating)P6 to P15
(Note)
____________
Table 1.4.1. Pin status when RESET pin level is “L”
Note :Port P11 to P15 exists in 144-pin version.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
27
(006B
16
)
(006C
16
)
(006D
16
)
(006E
16
)
(006F
16
)
(0070
16
)
(0071
16
)
(0072
16
)
(0073
16
)
(0074
16
)
(0075
16
)
(0076
16
)
(0077
16
)
(0078
16
)
(0079
16
)
(007A
16
)
(007B
16
)
(007C
16
)
(007D
16
)
(007E
16
)
(007F
16
)
(0081
16
)
(0086
16
)
(0088
16
)
(0089
16
)
(008A
16
)
(008B
16
)
(008C
16
)
(008D
16
)
(008E
16
)
(008F
16
)
(0090
16
)
(0091
16
)
(0004
16
)
(0005
16
)
(0006
16
)
(0007
16
)
(0008
16
)
(0009
16
)
(000A
16
)
(000B
16
)
(000C
16
)
(000D
16
)
(000E
16
)
(000F
16
)
(0010
16
)
(0011
16
)
(0012
16
)
(0014
16
)
(0015
16
)
(0016
16
)
(0017
16
)
(0018
16
)
(0019
16
)
(001A
16
)
(001B
16
)
(001C
16
)
(001D
16
)
(001E
16
)
(001F
16
)
(0040
16
)
(0041
16
)
(0057
16
)
(0068
16
)
(0069
16
)
(006A
16
)
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
Wait control register
Address match interrupt control register
Protect register
External data bus width control register
Main clock divided register
Oscillation stop detect register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
Address match interrupt register 1
VDC control register for PLL
Address match interrupt register 2
VDD control register 1
Address match interrupt register 3
VDD control register 1
DRAM control register
DRAM refresh interval set register
Flash memory control register 0
DMA0 interrupt control register
Timer B5 interrupt control register
DMA2 interrupt control register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
80
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
??
16
U AR T2 receiv e /A CK interrupt control register
Timer A0 interrupt control register
U ART3 receive/ACK interrupt control register
Timer A2 interrupt control register
U AR T4 receiv e/A CK interrupt control register
Timer A4 interrupt control register
U AR T0 receiv e/A CK interrupt control register
A-D0 interrupt control register
U AR T1 receiv e/A CK interrupt control register
Intelligent I/O interrupt control register 0
Timer B1 interrupt control register
Intelligent I/O interrupt control register 2
Timer B3 interrupt control register
Intelligent I/O interrupt control register 4
INT5 interrupt control register
Intelligent I/O interrupt control register 6
INT3 interrupt control register
Intelligent I/O interrupt control register 8
INT1 interrupt control register
A-D1 interrupt control register
DMA1 interrupt control register
U AR T2 transmit /NA CK interrupt control register
DMA3 interrupt control register
U ART3 transmit /NA CK interrupt control register
Timer A1 interrupt control register
U AR T4 transmit /NA CK interrupt control register
Timer A3 interrupt control register
UART2
bus collision detection interrupt
control register
U AR T0 transmit /NA CK interrupt control register
20
16
FF
16
XXXX0000
X00000XX
0000X000
XXXX0000
XXXXX000
XXX01000
??
16
000?????
00
16
00
16
00
16
?XXX????
XXXXXX01
XXXX?000
XX000001
XXXX?000
XXXX?000
UART0/UART3
bus collision detection interrupt
control register
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XX00?000
XX00?000
XX00?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
UART1/UART4 bus collision detection
interrupt control register
XXXX?000
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the V
CC
level is applied to the CNV
SS
pin, it is 03
16
at a reset.
Note 2: When the BYTE pin is "L", bit 3 is "1". When the BYTE pin is "H", bit 3 is "0".
(Note 1)
(Note 2)
00
16
00
16
XXXX?000
Intelligent I/O interrupt control register 10/
CAN interrupt 1 control register
Intelligent I/O interrupt control register 11/
CAN interrupt 2 control register
Figure 1.4.3. Device's internal status after a reset is cleared (1/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
28
(00B716)
(00B816)
(00B916)
(00BA16)
(00BB16)
(00C016)
(00C116)
(00C216)
(00C316)
(00C416)
(00C516)
(00C616)
(00C716)
(00C816)
(00C916)
(00CA16)
(00CB16)
(00CC16)
(00CD16)
(00CE16)
(00CF16)
(00D016)
(00D116)
(00D416)
(00D516)
(00D816)
(00D916)
(00DA16)
(00DB16)
(00DC16)
(00DD16)
(00DE16)
(00DF16)
(009216)
(009316)
(009416)
(009516)
(009616)
(009716)
(009816)
(009916)
(009A16)
(009B16)
(009C16)
(009D16)
(009E16)
(009F16)
(00A016)
(00A116)
(00A216)
(00A316)
(00A416)
(00A516)
(00A616)
(00A716)
(00A816)
(00A916)
(00AA16)
(00AB16)
(00B016)
(00B116)
(00B216)
(00B316)
(00B416)
(00B516)
(00B616)
UART1 transmit/NACK interrupt control register
Key input interrupt control register
Timer B0 interrupt control register
Intelligent I/O interrupt control register 1
Timer B2 interrupt control register
Intelligent I/O interrupt control register 3
Timer B4 interrupt control register
Intelligent I/O interrupt control register 5
INT4 interrupt control register
Intelligent I/O interrupt control register 7
INT2 interrupt control register
INT0 interrupt control register
Exit priority register
Interrupt request register 0
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Interrupt request register 4
Interrupt request register 5
Interrupt request register 6
Interrupt request register 7
Interrupt request register 8
Interrupt request register 9
Interrupt request register 10
Interrupt request register 11
Interrupt enable register 0
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt enable register 4
Interrupt enable register 5
Interrupt enable register 6
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
(73)
(74)
(75)
(76)
(77)
(78)
(79)
(80)
(81)
(82)
(83)
(84)
(85)
(86)
(87)
(88)
(89)
(90)
(91)
(92)
(93)
(94)
(95)
(96)
(97)
(98)
(99)
(100)
(101)
(102)
(103)
(104)
(105)
(106)
(107)
(108)
(109)
(110)
(111)
(112)
(113)
(114)
(115)
(116)
Interrupt enable register 7
Interrupt enable register 8
Interrupt enable register 9
Interrupt enable register 10
Interrupt enable register 11
Group 0 time measurement/waveform
generate register 0
Group 0 time measurement/waveform
generate register 1
Group 0 time measurement/waveform
generate register 2
Group 0 time measurement/waveform
generate register 3
Group 0 time measurement/waveform
generate register 4
Group 0 time measurement/waveform
generate register 5
Group 0 time measurement/waveform
generate register 6
Group 0 time measurement/waveform
generate register 7
Group 0 wav ef orm generate control register 0
Group 0 wav ef orm generate control register 1
Group 0 wav ef orm generate control register 4
Group 0 wav ef orm generate control register 5
Group 0 time measurement control register 0
Group 0 time measurement control register 1
Group 0 time measurement control register 2
Group 0 time measurement control register 3
Group 0 time measurement control register 4
Group 0 time measurement control register 5
Group 0 time measurement control register 6
Group 0 time measurement control register 7
XXXX?000
XXXX?000
XX00?000
XX00?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XX00?000
XX0X0000
0X00X000
0XX00000
00X00000
0XXX0000
0XXX0000
0XX00000
0X00X000
0X00X000
0X00X000
0016
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
0016
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
XX00X00X
XX00000X
00X0000X
XXX0000X
00X0000X
XX00X00X
XX00X0XX
XXX0000X
0XX0000X
0XX0000X
0XX0000X
0XX0000X
XX00X000
XX00X000
XX00X0X0
XX000000
00X00000
XXX00000
XXX00000
Intelligent I/O interrupt control register 9/
CAN interrupt 0 control register
Figure 1.4.3. Device's internal status after a reset is cleared (2/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
29
(010416)
(010516)
(010616)
(010716)
(010816)
(010916)
(010A16)
(010B16)
(010C16)
(010D16)
(010E16)
(010F16)
(011016)
(011116)
(011216)
(011316)
(011416)
(011516)
(011616)
(011716)
(011916)
(011A16)
(011E16)
(011F16)
(012016)
(012116)
(012216)
(012316)
(00E016)
(00E116)
(00E216)
(00E316)
(00E416)
(00E516)
(00E616)
(00E716)
(00E816)
(00E916)
(00EA16)
(00EC16)
(00ED16)
(00EE16)
(00EF16)
(00F016)
(00F116)
(00F216)
(00F316)
(00F416)
(00F516)
(00F816)
(00F916)
(00FA16)
(00FB16)
(00FC16)
(00FD16)
(00FE16)
(00FF16)
(010016)
(010116)
(010216)
(010316)
Group 0 base timer register
Group 0 base timer control register 0
Group 0 base timer control register 1
Group 0 time measurement prescaler register 6
Group 0 time measurement prescaler register 7
Group 0 function enable register
Group 0 function select register
Group 0 SI/O receive buffer register
Group 0 transmit buffer/receive data register
Group 0 receive input register
Group 0 SI/O communication mode register
Group 0 transmit output register
Group 0 SI/O communication control register
Group 0 data compare register 0
Group 0 data compare register 1
Group 0 data compare register 2
Group 0 data compare register 3
Group 0 data mask register 0
Group 0 data mask register 1
Group 0 receive CRC code register
Group 0 transmit CRC code register
Group 0 SI/O expansion mode register
Group 0 SI/O expansion receiv e control register
Group 0 SI/O special communication
interrupt detect register
Group 0 SI/O expansion transmit
control register
Group 1 time measurement/waveform
generate register 0
Group 1 time measurement/waveform
generate register 1
(117)
(118)
(119)
(120)
(121)
(122)
(123)
(124)
(125)
(126)
(127)
(128)
(129)
(130)
(131)
(132)
(133)
(134)
(135)
(136)
(137)
(138)
(139)
(140)
(141)
(142)
(143)
(144)
(145)
(146)
(147)
(148)
(149)
(150)
(151)
(152)
(153)
(154)
(155)
(156)
(157)
(158)
(159)
(160)
(161)
(162)
(163)
(164)
Group 1 time measurement/waveform
generate register 2
Group 1 time measurement/waveform
generate register 3
Group 1 time measurement/waveform
generate register 4
Group 1 time measurement/waveform
generate register 5
Group 1 time measurement/waveform
generate register 6
Group 1 time measurement/waveform
generate register 7
Group 1 wav eform generate control register 0
Group 1 wav eform generate control register 1
Group 1 wav eform generate control register 2
Group 1 wav eform generate control register 3
Group 1 wav eform generate control register 4
Group 1 wav eform generate control register 5
Group 1 wav eform generate control register 6
Group 1 wav eform generate control register 7
Group 1 time measurement control register 1
Group 1 time measurement control register 2
Group 1 time measurement control register 6
Group 1 time measurement control register 7
Group 1 base timer register
Group 1 base timer control register 0
Group 1 base timer control register 1
X000XXXX
0000X011
000000XX
00000XXX
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0016
0016
0016
0016
0016
0016
0016
??16
??16
0016
0016
0016
0016
0016
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
??16
0016
0016
??16
??16
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Figure 1.4.3. Device's internal status after a reset is cleared (3/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
30
(0148
16
)
(0149
16
)
(014A
16
)
(014B
16
)
(014C
16
)
(014D
16
)
(014E
16
)
(014F
16
)
(0150
16
)
(0151
16
)
(0152
16
)
(0153
16
)
(0154
16
)
(0155
16
)
(0156
16
)
(0157
16
)
(0160
16
)
(0161
16
)
(0162
16
)
(0163
16
)
(0164
16
)
(0166
16
)
(0167
16
)
(016A
16
)
(016B
16
)
(016C
16
)
(016D
16
)
(016E
16
)
(016F
16
)
(0170
16
)
(0171
16
)
(0172
16
)
(0124
16
)
(0125
16
)
(0126
16
)
(0127
16
)
(0128
16
)
(0129
16
)
(012A
16
)
(012C
16
)
(012D
16
)
(012E
16
)
(012F
16
)
(0130
16
)
(0131
16
)
(0132
16
)
(0133
16
)
(0134
16
)
(0135
16
)
(0138
16
)
(0139
16
)
(013A
16
)
(013B
16
)
(013C
16
)
(013D
16
)
(013E
16
)
(013F
16
)
(0140
16
)
(0141
16
)
(0142
16
)
(0143
16
)
(0144
16
)
(0145
16
)
(0146
16
)
(0147
16
)
Group 1 time measurement prescaler register 6
Group 1 time measurement prescaler register 7
Group 1 function enable register
Group 1 function select register
Group 1 SI/O receive buffer register
Group 1 transmit buffer/receive data register
Group 1 receive input register
Group 1 SI/O communication mode register
Group 1 transmit output register
Group 1 SI/O communication control register
Group 1 data compare register 0
Group 1 data compare register 1
Group 1 data compare register 2
Group 1 data compare register 3
Group 1 data mask register 0
Group 1 data mask register 1
Group 1 receive CRC code register
Group 1 transmit CRC code register
Group 1 SI/O expansion mode register
Group 1 SI/O expansion receiv e control register
Group 1 SI/O special communication
interrupt detect register
Group 1 SI/O expansion tr ansmit control register
Group 2 waveform generate register 0
Group 2 waveform generate register 1
Group 2 waveform generate register 2
Group 2 waveform generate register 3
(165)
(166)
(167)
(168)
(169)
(170)
(171)
(172)
(173)
(174)
(175)
(176)
(177)
(178)
(179)
(180)
(181)
(182)
(183)
(184)
(185)
(186)
(187)
(188)
(189)
(190)
(191)
(192)
(193)
(194)
(195)
(196)
(197)
(198)
(199)
(200)
(201)
(202)
(203)
(204)
(205)
(206)
(207)
(208)
(209)
(210)
(211)
(212)
(213)
(214)
Group 2 waveform generate register 4
Group 2 waveform generate register 5
Group 2 waveform generate register 6
Group 2 waveform generate register 7
Group 2 waveform generate control register 0
Group 2 waveform generate control register 1
Group 2 waveform generate control register 2
Group 2 waveform generate control register 3
Group 2 waveform generate control register 4
Group 2 waveform generate control register 5
Group 2 waveform generate control register 6
Group 2 waveform generate control register 7
Group 2 base timer register
Group 2 base timer control register 0
Group 2 base timer control register 1
Base timer start register
Group 2 function enable register
Group 2 RTP output buffer register
Group 2 SI/O communication mode register
Group 2 SI/O communication control register
Group 2 SI/O transmit buffer register
Group 2 SI/O receive buffer register
Group 2 IEBus address register
Group 2 IEBus control register
X000XXXX
0000X011
00XXX000
0000X110
???XX???
XXX?XXXX
XXXX????
XXXX0000
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
??
16
??
16
00
16
00
16
00
16
00
16
??
16
??
16
??
16
00
16
00
16
??
16
??
16
??
16
00
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
00
16
00
16
00
16
00
16
??
16
??
16
00
16
00
16
00XXX000
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
000000XX
00000XXX
Figure 1.4.3. Device's internal status after a reset is cleared (4/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
31
(019816)
(019916)
(019A16)
(019B16)
(019C16)
(019D16)
(019E16)
(019F
16
)
(01A016)
(01A116)
(01A216)
(01A316)
(01A616)
(01A716)
(01AB16)
(01AC16)
(01AD16)
(01AE16)
(01AF16)
(01B016)
(01B116)
(01B216)
(01B316)
(01B416)
(01B516)
(01B616)
(01B716)
(01B816)
(01B916)
(01BA16)
(01BB16)
(01BC16)
(01BD16)
(017316)
(017416)
(017816)
(017A16)
(017B16)
(017C16)
(017D16)
(017E16)
(017F16)
(018016)
(018116)
(018216)
(018316)
(018416)
(018516)
(018616)
(018716)
(018816)
(018916)
(018A16)
(018B16)
(018C16)
(018D16)
(018E16)
(018F16)
(019016)
(019116)
(019216)
(019316)
(019416)
(019516)
(019616)
(019716)
Input function select register
Group 3 SI/O communication mode register
Group 3 SI/O communication control register
Group 3 SI/O transmit buffer register
Group 3 SI/O receive buffer register
Group 3 waveform generate register 0
Group 3 waveform generate register 1
Group 3 waveform generate register 2
Group 3 waveform generate register 3
Group 3 waveform generate register 4
Group 3 waveform generate register 5
Group 3 waveform generate register 6
Group 3 waveform generate register 7
Group 3 waveform generate control register 0
Group 3 waveform generate control register 1
Group 3 waveform generate control register 2
Group 3 waveform generate control register 3
Group 3 waveform generate control register 4
Group 3 waveform generate control register 5
Group 3 waveform generate control register 6
Group 3 waveform generate control register 7
(215)
(216)
(217)
(218)
(219)
(220)
(221)
(222)
(223)
(224)
(225)
(226)
(227)
(228)
(229)
(230)
(231)
(232)
(233)
(234)
(235)
(236)
(237)
(238)
(239)
(240)
(241)
(242)
(243)
(244)
(245)
(246)
(247)
(248)
(249)
(250)
(251)
(252)
(253)
(254)
(255)
(256)
(257)
Group 3 waveform generate mask register 4
Group 3 waveform generate mask register 5
Group 3 waveform generate mask register 6
Group 3 waveform generate mask register
7
Group 3 base timer register
Group 3 base timer control register 0
Group 3 base timer control register 1
Group 3 function enable register
Group 3 RTP output
buffer
register
Group 3 high-speed HDLC
communication
control register 1
Group 3 high-speed HDLC
communication
control register
Group 3 high-speed HDLC
communication
register
Group 3 high-speed HDLC transmit counter
Group 3 high-speed HDLC data
compare register 0
Group 3 high-speed HDLC data
mask register 0
Group 3 high-speed HDLC data
compare register 1
Group 3 high-speed HDLC data
mask register 1
Group 3 high-speed HDLC data
compare register 2
Group 3 high-speed HDLC data
mask register 2
Group 3 high-speed HDLC data
compare register 3
XXX00000
XXX00000
00?0X??0
00XX0000
0XX0X000
Group 2 IEBus transmit interrupt
cause detect register
Group 2 IEBus receive interrupt
cause detect register
0016
0016
0016
0016
0016
0016
??16
??16
0016
0016
0016
0016
??16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
??16
??16
??16
??16
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
00XXXXX0
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
Figure 1.4.3. Device's internal status after a reset is cleared (5/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
32
(01EC
16
)
(01ED
16
)
(01EE
16
)
(01EF
16
)
(01F0
16
)
(01F1
16
)
(01F2
16
)
(01F3
16
)
(01F4
16
)
(01F5
16
)
(01F6
16
)
(01F7
16
)
(01F8
16
)
(01F9
16
)
(01FA
16
)
(01FB
16
)
(01FC
16
)
(01FD
16
)
(01FE
16
)
(01FF
16
)
(0200
16
)
(0201
16
)
(0202
16
)
(0203
16
)
(0204
16
)
(0205
16
)
(0206
16
)
(0207
16
)
(0208
16
)
(0209
16
)
(020A
16
)
(020B
16
)
(01BE
16
)
(01BF
16
)
(01C0
16
)
(01C1
16
)
(01C2
16
)
(01C3
16
)
(01C4
16
)
(01C5
16
)
(01C6
16
)
(01C7
16
)
(01C8
16
)
(01C9
16
)
(01CA
16
)
(01CB
16
)
(01CC
16
)
(01CD
16
)
(01CE
16
)
(01CF
16
)
(01D4
16
)
(01D6
16
)
(01D7
16
)
(01E0
16
)
(01E1
16
)
(01E2
16
)
(01E3
16
)
(01E4
16
)
(01E5
16
)
(01E6
16
)
(01E7
16
)
(01E8
16
)
(01E9
16
)
(01EA
16
)
(01EB
16
)
Group 3
high-speed HDLC data
mask register 3
A-D1 register 0
A-D1 register 1
A-D1 register 2
A-D1 register 3
A-D1 register 4
A-D1 register 5
A-D1 register 6
A-D1 register 7
A-D1 control register 2
A-D1 control register 0
A-D1 control register 1
CAN0 message slot buffer 0 standard ID 0
CAN0 message slot buffer 0 standard ID 1
CAN0 message slot buffer 0 extended ID 0
CAN0 message slot buffer 0 extended ID 1
CAN0 message slot buffer 0 extended ID 2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
(258)
(259)
(260)
(261)
(262)
(263)
(264)
(265)
(266)
(267)
(268)
(269)
(270)
(271)
(272)
(273)
(274)
(275)
(276)
(277)
(278)
(279)
(280)
(281)
(282)
(283)
(284)
(285)
(286)
(287)
(288)
(289)
(290)
(291)
(292)
(293)
(294)
(295)
(296)
(297)
(298)
(299)
(300)
(301)
(302)
(303)
(304)
(305)
(306)
(307)
(308)
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp high
CAN0 message slot buffer 0 time stamp low
CAN1 message slot buffer 0 standard ID 0
CAN1 message slot buffer 0 standard ID 1
CAN1 message slot buffer 0 extended ID 0
CAN1 message slot buffer 0 extended ID 1
CAN1 message slot buffer 0 extended ID 2
CAN1 message slot buff er 0 data length code
CAN1 message slot buffer 0 data 0
CAN1 message slot buffer 0 data 1
CAN1 message slot buffer 0 data 2
CAN1 message slot buffer 0 data 3
CAN1 message slot buffer 0 data 4
CAN1 message slot buffer 0 data 5
CAN1 message slot buffer 0 data 6
CAN1 message slot buffer 0 data 7
CAN1 message slot buffer 0 time stamp high
CAN1 message slot buffer 0 time stamp low
CAN0 control register
0
CAN0 status register
CAN0 expansion ID register
CAN0 configuration register
CAN0 time stamp register
CAN0 transmit error count register
CAN0 receive error count register
XXXX0000
0000XXXX
X00XX000
XX000000
X0000X01
XX010X01
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
00
16
??
16
??
16
00
16
??
16
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 0242
16
) to 1 after reset.
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
XXX?????
XX??????
XXXX????
XX??????
XXXX????
XXX?????
XX??????
XXXX????
XX??????
XXXX????
Figure 1.4.3. Device's internal status after a reset is cleared (6/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
33
(02C016)
(02C116)
(02C216)
(02C316)
(02C416)
(02C516)
(02C616)
(02C716)
(02C816)
(02C9
16
)
(02CA16)
(02CB16)
(02CC16)
(02CD16)
(02CE16)
(02CF16)
(02D016)
(02D116)
(02D216)
(02D316)
(02D416)
(02D516)
(02D616)
(02D716)
(02D816)
(02D916)
(02DA16)
(02DB16)
(02DC16)
(02DD16)
(02DE16)
(02DF16)
(02E016)
(020C16)
(020D16)
(021016)
(021116)
(021416)
(021516)
(021716)
(022816)
(022916)
(022A16)
(022B16)
(022C16)
(023016)
(023116)
(023216)
(023316)
(023416)
(023516)
(023616)
(023716)
(023816)
(023916)
(023A16)
(023B16)
(023C16)
(023D16)
(023E16)
(023F16)
(024016)
(024116)
(024216)
(024416)
(024516)
CAN0 slot interrupt status register
CAN0 slot interrupt mask register
CAN0 error interrupt mask register
CAN0 error interrupt status register
CAN0 baud rate prescaler
CAN0 global mask register standard ID0
CAN0 global mask register standard ID1
CAN0 global mask register extended ID0
CAN0 global mask register extended ID1
CAN0 global mask register extended ID2
CAN0 message slot 5 control register
CAN0 message slot 6 control register
CAN0 message slot 7 control register
CAN0 message slot 13 control register
CAN0 message slot 14 control register
CAN0 message slot 15 control register
CAN0 slot buffer select register
CAN0 control register 1
CAN0 sleep control register
CAN0 acceptance filter support register
(309)
(310)
(311)
(312)
(313)
(314)
(315)
(316)
(317)
(318)
(319)
(320)
(321)
(322)
(323)
(324)
(325)
(326)
(327)
(328)
(329)
(330)
(331)
(332)
(333)
(334)
(335)
(336)
(337)
(338)
(339)
(340)
(341)
(342)
(343)
(344)
(345)
(346)
(347)
(348)
(349)
(350)
(351)
(352)
(353)
(354)
(355)
X0 register/Y0 register
X1 register/Y1 register
X2 register/Y2 register
X3 register/Y3 register
X4 register/Y4 register
X5 register/Y5 register
X6 register/Y6 register
X7 register/Y7 register
X8 register/Y8 register
X9 register/Y9 register
X10 register/Y10 register
X11 register/Y11 register
X12 register/Y12 register
X13 register/Y13 register
X14 register/Y14 register
X15 register/Y15 register
XY control register
XXXXX000
XXXXX000
XXXXXXX0
XXXXXX00
CAN0 message slot 0 control register /
CAN0 local mask register A standard ID0
CAN0 message slot 8 control register /
CAN0 local mask register B standard ID0
CAN0 message slot 9 control register /
CAN0 local mask register B standard ID1
CAN0 message slot 10 control register /
CAN0 local mask register B extended ID0
CAN0 message slot 11 control register /
CAN0 local mask register B extended ID1
CAN0 message slot 12 control register /
CAN0 local mask register B extended ID2
CAN0 message slot 1 control register /
CAN0 local mask register A standard ID1
CAN0 message slot 3 control register /
CAN0 local mask register A extended ID1
CAN0 message slot 2 control register /
CAN0 local mask register A extended ID0
CAN0 message slot 4 control register /
CAN0 local mask register A extended ID2
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0116
0016
0116
0016
0016
XX0000XX
??16
??16
??16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
XXX00000
XX000000
XXX00000
XX000000
0016
XXX00000
XX000000
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit (bit 0 at address 024216) to 1 after reset.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Figure 1.4.3. Device's internal status after a reset is cleared (7/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
34
(030A16)
(030B16)
(030C16)
(030D16)
(031016)
(031116)
(031216)
(031316)
(031416)
(0315
16
)
(031B16)
(031C16)
(031D16)
(031F16)
(032416)
(032516)
(032616)
(032716)
(032816)
(032916)
(032A16)
(032B16)
(032C16)
(032D16)
(032E16)
(032F16)
(033416)
(033516)
(033616)
(033716)
(033816)
(033916)
(02E416)
(02E516)
(02E616)
(02E716)
(02E816)
(02E916)
(02EA16)
(02EB16)
(02EC16)
(02ED16)
(02EE16)
(02EF16)
(02F416)
(02F516)
(02F616)
(02F716)
(02F816)
(02F916)
(02FA16)
(02FB16)
(02FC16)
(02FD16)
(02FE16)
(02FF16)
(030016)
(030216)
(030316)
(030416)
(030516)
(030616)
(030716)
(030816)
(030916)
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART1 transmit-receive mode register
UART1 bit rate generator
UART1 transmit buffer register
UART1 transmit-receive control register 0
UART1 transmit-receive control register 1
UART1 receive buffer register
UART4 special mode register 4
UART4 special mode register 3
UART4 special mode register 2
UART4 special mode register
UART4 transmit-receive mode register
UART4 bit rate generator
UART4 transmit buffer register
UART4 transmit-receive control register 0
UART4 transmit-receive control register 1
UART4 receive buffer register
Timer B3,B4,B5 count start flag
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
Three-phase PWM control register 0
Three-phase PWM control register 1
(356)
(357)
(358)
(359)
(360)
(361)
(362)
(363)
(364)
(365)
(366)
(367)
(368)
(369)
(370)
(371)
(372)
(373)
(374)
(375)
(376)
(377)
(378)
(379)
(380)
(381)
(382)
(383)
(384)
(385)
(386)
(387)
(388)
(389)
(390)
(391)
(392)
(393)
(394)
(395)
(396)
(397)
(398)
(399)
(400)
(401)
(402)
(403)
(404)
(405)
(406)
(407)
(408)
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
Timer B2 interrupt occurrence
frequency set counter
Timer B3 register
Timer B4 register
Timer B5 register
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
External interrupt cause select register
UART3 special mode register 4
UART3 special mode register 3
UART3 special mode register 2
UART3 special mode register
UART3 transmit-receive mode register
UART3 bit rate generator
UART3 transmit buffer register
UART3 transmit-receive control register 0
UART3 transmit-receive control register 1
UART3 receive buffer register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit-receive mode register
UART2 bit rate generator
XXXXXXX?
XXXXXXX?
XX000000
XX000000
XXXX????
00?X0000
?????XX?
?????XX?
000XXXXX
00?X0000
00?00000
XXXXXXX?
?????XX?
0816
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
0016
??16
??16
0216
??16
0016
0016
0016
0016
0016
??16
0016
0016
0016
??16
0816
??16
0216
??16
0016
0016
0016
??16
??16
0816
0216
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Figure 1.4.3. Device's internal status after a reset is cleared (8/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
35
(035C
16
)
(035D
16
)
(035E
16
)
(035F
16
)
(0364
16
)
(0365
16
)
(0366
16
)
(0367
16
)
(0368
16
)
(0369
16
)
(036A
16
)
(036B
16
)
(036C
16
)
(036D
16
)
(036E
16
)
(036F
16
)
(0376
16
)
(0378
16
)
(0379
16
)
(037A
16
)
(037B
16
)
(037C
16
)
(037D
16
)
(037E
16
)
(0380
16
)
(0381
16
)
(0382
16
)
(0383
16
)
(0384
16
)
(0385
16
)
(0386
16
)
(0387
16
)
(033A
16
)
(033B
16
)
(033C
16
)
(033D
16
)
(033E
16
)
(033F
16
)
(0340
16
)
(0341
16
)
(0342
16
)
(0343
16
)
(0344
16
)
(0346
16
)
(0347
16
)
(0348
16
)
(0349
16
)
(034A
16
)
(034B
16
)
(034C
16
)
(034D
16
)
(034E
16
)
(034F
16
)
(0350
16
)
(0351
16
)
(0352
16
)
(0353
16
)
(0354
16
)
(0355
16
)
(0356
16
)
(0357
16
)
(0358
16
)
(0359
16
)
(035A
16
)
(035B
16
)
UART2 transmit buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
(409)
(410)
(411)
(412)
(413)
(414)
(415)
(416)
(417)
(418)
(419)
(420)
(421)
(422)
(423)
(424)
(425)
(426)
(427)
(428)
(429)
(430)
(431)
(432)
(433)
(434)
(435)
(436)
(437)
(438)
(439)
(440)
(441)
(442)
(443)
(444)
(445)
(446)
(447)
(448)
(449)
(450)
(451)
(452)
(453)
(454)
(455)
(456)
Timer B1 mode register
Timer B2 mode register
Timer B2 special mode register
Count source prescaler register
UART0 pecial mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
PLL control register 0
DMA0 cause select register
DMA1 cause select register
DMA2 cause select register
DMA3 cause select register
CRC data register
CRC input register
A-D0 register 0
A-D0 register 1
A-D0 register 2
A-D0 register 3
0XXXXXXX
XXXXXXX?
?????XX?
00?X0000
00?X0000
0XXX0000
XXXXXXX0
00000X00
00000X00
00000X00
00000X00
00000X00
00?00000
XXXXXXX?
?????XX?
00110100
0X000000
0X000000
0X000000
0X000000
??
16
??
16
00
16
00
16
00
16
00
16
00
16
??
16
??
16
02
16
08
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
02
16
??
16
00
16
00
16
00
16
00
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
08
16
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM are undefined when the microcomputer is reset. The initial values must therefore be set.
Figure 1.4.3. Device's internal status after a reset is cleared (9/10)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
36
(03C5
16
)
(03C6
16
)
(03C7
16
)
(03C8
16
)
(03C9
16
)
(03CA
16
)
(03CB
16
)
(03CC
16
)
(03CD
16
)
(03CE
16
)
(03CF
16
)
(03D0
16
)
(03D1
16
)
(03D2
16
)
(03D3
16
)
(03DA
16
)
(03DB
16
)
(03DC
16
)
(03E0
16
)
(03E1
16
)
(03E2
16
)
(03E3
16
)
(03E4
16
)
(03E5
16
)
(03E6
16
)
(03E7
16
)
(03E8
16
)
(03E9
16
)
(03EA
16
)
(03EB
16
)
(03F0
16
)
(03F1
16
)
(03FF
16
)
(0388
16
)
(0389
16
)
(038A
16
)
(038B
16
)
(038C
16
)
(038D
16
)
(038E
16
)
(038F
16
)
(0394
16
)
(0396
16
)
(0397
16
)
(0398
16
)
(039A
16
)
(039C
16
)
(03A0
16
)
(03A1
16
)
(03AF
16
)
(03B0
16
)
(03B1
16
)
(03B2
16
)
(03B3
16
)
(03B4
16
)
(03B5
16
)
(03B6
16
)
(03B7
16
)
(03B9
16
)
(03BC
16
)
(03BD
16
)
(03C0
16
)
(03C1
16
)
(03C2
16
)
(03C3
16
)
(03C4
16
)
A-D0 register 4
A-D0 register 5
A-D0 register 6
A-D0 register 7
A-D0 control register 2
A-D0 control register 0
A-D0 control register 1
D-A register 0
D-A register 1
D-A control register
Function select register A8
Function select register A9
Function select register C
Function select register A0
Function select register A1
Function select register B0
Function select register B1
Function select register A2
Function select register A3
Function select register B2
Function select register B3
Function select register A5
Function select register A6
Function select register A7
Port P6
Port P7
Port P6 direction register
Port P7 direction register
Port P8
(457)
(458)
(459)
(460)
(461)
(462)
(463)
(464)
(465)
(466)
(467)
(468)
(469)
(470)
(471)
(472)
(473)
(474)
(475)
(476)
(477)
(478)
(479)
(480)
(481)
(482)
(483)
(484)
(485)
(486)
(487)
(488)
(489)
(490)
(491)
(492)
(493)
(494)
(495)
(496)
(497)
(498)
(499)
(500)
(501)
(502)
(503)
(504)
(505)
(506)
(507)
(508)
(509)
(510)
(511)
(512)
(513)
(514)
(515)
(516)
(517)
(518)
Port P9
Port P8 direction register
Port P9 direction register
Port P10
Port P11
Port P10 direction register
Port P11 direction register
Port P12
Port P13
Port P12 direction register
Port P13 direction register
Port P14
Port P15
Port P14 direction register
Port P15 direction register
Pull-up control register 2
Pull-up control register 3
Pull-up control register 4
Port P0
Port P1
Port P0 direction register
Port P1 direction register
Port P2
Port P3
Port P2 direction register
Port P3 direction register
Port P4
Port P5
Port P4 direction register
Port P5 direction register
Pull-up control register 0
Pull-up control register 1
Port control register
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note :This register exists in 144-pin version.
X0000000
XXXXXX00
XXXX0000
00X00000
XXXXX000
00X00000
XXX?????
XXX00000
XXXXX000
XXXX0000
X???????
X0000000
XXXX0000
XXXX0000
XXXXXXX0
??
16
00
16
??
16
??
16
00
16
??
16
??
16
00
16
00
16
??
16
00
16
00
16
00
16
??
16
??
16
00
16
??
16
00
16
00
16
??
16
??
16
00
16
00
16
00
16
??
16
??
16
??
16
??
16
??
16
??
16
??
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
??
16
??
16
00
16
00
16
??
16
??
16
??
16
??
16
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note) 00
16
00
16
00
16
00
16
00
16
Figure 1.4.3. Device's internal status after a reset is cleared (10/10)
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
37
SFR
Address Register
000016
000116
000216
000316
000416 Processor mode register 0 PM0
000516 Processor mode register 1 PM1
000616 System clock control register 0 CM0
000716 System clock control register 1 CM1
000816 Wait control register WCR
000916 Address match interrupt control register AIER
000A16 Protect register PRCR
000B16 External data bus width control register DS
000C16 Main clock divided register MCD
000D16 Oscillation stop detect register CM2
000E16 Watchdog timer start register WDTS
000F16 Watchdog timer control register WDC
001016
001116 Address match interrupt register 0 RMAD0
001216
001316
001416
001516 Address match interrupt register 1 RAMD1
001616
001716 VDC control register for PLL PLV
001816
001916 Address match interrupt register 2 RAMD2
001A16
001B16 VDC control register 1 VDC1 *
001C16
001D16 Address match interrupt register 3 RAMD3
001E16
001F16 VDC control register 0 VDC0 *
002016
002116 Emulator interrupt vector table register EIAD0 *
002216
002316 Emulator interrupt detect register EITD *
002416 Emulator protect register EPRR *
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
Address Register
003016 ROM area set register ROA *
003116 Debug moritor area set register DBA *
003216 Expansion area set register 0 EXA0 *
003316 Expansion area set register 1 EXA1 *
003416 Expansion area set register 2 EXA2 *
003516 Expansion area set register 3 EXA3 *
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016 DRAM control register DRAMCONT
004116 DRAM refresh interval set register REFCNT
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516 Flash memory control register 2 FMR2 *
005616 Flash memory control register 1 FMR1 *
005716 Flash memory control register 0 FMR0
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
The blank area is reserved and cannot be used by user.
*: User cannot use this. Do not access to the register.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
38
Address Register
006016
006116
006216
006316
006416
006516
006616
006716
006816 DMA0 interrupt control register DM0IC
006916 Timer B5 interrupt control register TB5IC
006A16 DMA2 interrupt control register DM2IC
006B16 UART2 receive /ACK interrupt control register S2RIC
006C16 Timer A0 interrupt control register TA0IC
006D16 UART3 receive /ACK interrupt control register S3RIC
006E16 Timer A2 interrupt control register TA2IC
006F16 UART4 receive /ACK interrupt control register S4RIC
007016 Timer A4 interrupt control register TA4IC
007116
UART0/UART3 bus collision detection interrupt control register BCN0IC
007216 UART0 receive/ACK interrupt control register S0RIC
007316 A-D0 interrupt control register AD0IC
007416 UART1 receive/ACK interrupt control register S1RIC
007516 Intelligent I/O interrupt control register 0 IIO0IC
007616 Timer B1 interrupt control register TB1IC
007716 Intelligent I/O interrupt control register 2 IIO2IC
007816 Timer B3 interrupt control register TB3IC
007916 Intelligent I/O interrupt control register 4 IIO4IC
007A16 INT5 interrupt control register INT5IC
007B16 Intelligent I/O interrupt control register 6 IIO6IC
007C16 INT3 interrupt control register INT3IC
007D16 Intelligent I/O interrupt control register 8 IIO8IC
007E16 INT1 interrupt control register INT1IC
007F16 Intelligent I/O interrupt control register 10/ IIO10IC
CAN interrupt 1 control register CAN1ICI
008016
008116 Intelligent I/O interrupt control register 11/
IIO11IC
CAN interrupt 2 control register
CAN2IC
008216
008316
008416
008516
008616 A-D1 interrupt control register AD1IC
008716
008816 DMA1 interrupt control register DM1IC
008916 UART2 transmit /NACK interrupt control register S2TIC
008A16 DMA3 interrupt control register DM3IC
008B16 UART3 transmit /NACK interrupt control register S3TIC
008C16 Timer A1 interrupt control register TA1IC
008D16 UART4 transmit /NACK interrupt control register S4TIC
008E16 Timer A3 interrupt control register TA3IC
008F16
UART2 bus collision detection interrupt control register BCN2IC
Address Register
009016 UART0 transmit /NACK interrupt control register S0TIC
009116
UART1/UART4 bus collision detection interrupt control register BCN1IC
009216 UART1 transmit/NACK interruptcontrol register S1TIC
009316 Key input interrupt control register KUPIC
009416 Timer B0 interrupt control register TB0IC
009516 Intelligent I/O interrupt control register 1 IIO1IC
009616 Timer B2 interrupt control register TB2IC
009716 Intelligent I/O interrupt control register 3 IIO3IC
009816 Timer B4 interrupt control register TB4IC
009916 Intelligent I/O interrupt control register 5 IIO5IC
009A16 INT4 interrupt control register INT4IC
009B16 Intelligent I/O interrupt control register 7 IIO7IC
009C16 INT2 interrupt control register INT2IC
009D16 Intelligent I/O interrupt control register 9/
IIO9IC
CAN interrupt 0 control register
CAN0ICI
009E16 INT0 interrupt control register INT0IC
009F16 Exit priority register RLVL
00A016 Interrupt request register 0 IIO0IR
00A116 Interrupt request register 1 IIO1IR
00A216 Interrupt request register 2 IIO2IR
00A316 Interrupt request register 3 IIO3IR
00A416 Interrupt request register 4 IIO4IR
00A516 Interrupt request register 5 IIO5IR
00A616 Interrupt request register 6 IIO6IR
00A716 Interrupt request register 7 IIO7IR
00A816 Interrupt request register 8 IIO8IR
00A916 Interrupt request register 9 IIO9IR
00AA16 Interrupt request register 10 IIO10IR
00AB16 Interrupt request register 11 IIO11IR
00AC16
00AD16
00AE16
00AF16
00B016 Interrupt enable register 0 IIO0IE
00B116 Interrupt enable register 1 IIO1IE
00B216 Interrupt enable register 2 IIO2IE
00B316 Interrupt enable register 3 IIO3IE
00B416 Interrupt enable register 4 IIO4IE
00B516 Interrupt enable register 5 IIO5IE
00B616 Interrupt enable register 6 IIO6IE
00B716 Interrupt enable register 7 IIO7IE
00B816 Interrupt enable register 8 IIO8IE
00B916 Interrupt enable register 9 IIO9IE
00BA16 Interrupt enable register 10 IIO10IE
00BB16 Interrupt enable register 11 IIO11IE
00BC16
00BD16
00BE16
00BF16
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
39
Address Register
00C016 Group 0 TM /WG register 0 G0TM0/G0PO0
00C116
00C216 Group 0 TM /WG register 1 G0TM1/G0PO1
00C316
00C416 Group 0 TM /WG register 2 G0TM2/G0PO2
00C516
00C616 Group 0 TM /WG register 3 G0TM3/G0PO3
00C716
00C816 Group 0 TM /WG register 4 G0TM4/G0PO4
00C916
00CA16 Group 0 TM /WG register 5 G0TM5/G0PO5
00CB16
00CC16 Group 0 TM /WG register 6 G0TM6/G0PO6
00CD16
00CE16 Group 0 TM /WG register 7 G0TM7/G0PO7
00CF16
00D016 Group 0 waveform generate control register 0 G0POCR0
00D116 Group 0 waveform generate control register 1 G0POCR1
00D216
00D316
00D416 Group 0 waveform generate control register 4 G0POCR4
00D516 Group 0 waveform generate control register 5 G0POCR5
00D616
00D716
00D816 Group 0 time measurement control register 0 G0TMCR0
00D916 Group 0 time measurement control register 1 G0TMCR1
00DA16 Group 0 time measurement control register 2 G0TMCR2
00DB16 Group 0 time measurement control register 3 G0TMCR3
00DC16 Group 0 time measurement control register 4 G0TMCR4
00DD16 Group 0 time measurement control register 5 G0TMCR5
00DE16 Group 0 time measurement control register 6 G0TMCR6
00DF16 Group 0 time measurement control register 7 G0TMCR7
00E016 Group 0 base timer register G0BT
00E116
00E216 Group 0 base timer control register 0 G0BCR0
00E316 Group 0 base timer control register 1 G0BCR1
00E416 Group 0 time measurement prescaler register 6 G0TPR6
00E516 Group 0 time measurement prescaler register 7 G0TPR7
00E616 Group 0 function enable register G0FE
00E716 Group 0 function select register G0FS
00E816 Group 0 SI/O receive buffer register G0BF
00E916
00EA16 Group 0 transmit buffer/receive data register G0DR
00EB16
00EC16 Group 0 receive input register G0RI
00ED16 Group 0 SI/O communication mode register G0MR
00EE16 Group 0 transmit output register G0TO
00EF16 Group 0 SI/O communication control register G0CR
Address Register
00F016 Group 0 data compare register 0 G0CMP0
00F116 Group 0 data compare register 1 G0CMP1
00F216 Group 0 data compare register 2 G0CMP2
00F316 Group 0 data compare register 3 G0CMP3
00F416 Group 0 data mask register 0 G0MSK0
00F516 Group 0 data mask register 1 G0MSK1
00F616
00F716
00F816 Group 0 receive CRC code register G0RCRC
00F916
00FA16 Group 0 transmit CRC code register G0TCRC
00FB16
00FC16 Group 0 SI/O expansion mode register G0EMR
00FD16 Group 0 SI/O expansion receive control register G0ERC
00FE16
Group 0 SI/O special communication interrupt detect register
G0IRF
00FF16 Group 0 SI/O expansion transmit control register G0ETC
010016 Group 1 TM /WG register 0 G1TM0/G1PO0
010116
010216 Group 1 TM /WG register 1 G1TM1/G1PO1
010316
010416 Group 1 TM /WG register 2 G1TM2/G1PO2
010516
010616 Group 1 TM /WG register 3 G1TM3/G1PO3
010716
010816 Group 1 TM /WG register 4 G1TM4/G1PO4
010916
010A16 Group 1 TM /WG register 5 G1TM5/G1PO5
010B16
010C16 Group 1 TM /WG register 6 G1TM6/G1PO6
010D16
010E16 Group 1 TM /WG register 7 G1TM7/G1PO7
010F16
011016 Group 1 waveform generate control register 0 G1POCR0
011116 Group 1 waveform generate control register 1 G1POCR1
011216 Group 1 waveform generate control register 2 G1POCR2
011316 Group 1 waveform generate control register 3 G1POCR3
011416 Group 1 waveform generate control register 4 G1POCR4
011516 Group 1 waveform generate control register 5 G1POCR5
011616 Group 1 waveform generate control register 6 G1POCR6
011716 Group 1 waveform generate control register 7 G1POCR7
011816
011916 Group 1 time measurement control register 1 G1TMCR1
011A16 Group 1 time measurement control register 2 G1TMCR2
011B16
011C16
011D16
011E16 Group 1 time measurement control register 6 G1TMCR6
011F16 Group 1 time measurement control register 7 G1TMCR7
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
40
Address Register
012016 Group 1 base timer register G1BT
012116
012216 Group 1 base timer control register 0 G1BCR0
012316 Group 1 base timer control register 1 G1BCR1
012416 Group 1 time measurement prescaler register 6 G1TPR6
012516 Group 1 time measurement prescaler register 7 G1TPR7
012616 Group 1 function enable register G1FE
012716 Group 1 function select register G1FS
012816
Group 1 SI/O receive buffer register G1BF
012916
012A16 Group 1 transmit buffer/receive data register G1DR
012B16
012C16 Group 1 receive input register G1RI
012D16 Group 1 SI/O communication mode register G1MR
012E16 Group 1 transmit output register G1TO
012F16 Group 1 SI/O communication control register G1CR
013016 Group 1 data compare register 0 G1CMP0
013116 Group 1 data compare register 1 G1CMP1
013216 Group 1 data compare register 2 G1CMP2
013316 Group 1 data compare register 3 G1CMP3
013416 Group 1 data mask register 0 G1MSK0
013516 Group 1 data mask register 1 G1MSK1
013616
013716
013816 Group 1 receive CRC code register G1RCRC
013916
013A16 Group 1 transmit CRC code register G1TCRC
013B16
013C16 Group 1 SI/O expansion mode register G1EMR
013D16 Group 1 SI/O expansion receive control register G1ERC
013E16
Group 1 SI/O special communication interrupt detect register
G1IRF
013F16 Group 1 SI/O expansion transmit control register G1ETC
014016 Group 2 waveform generate register 0 G2PO0
014116
014216 Group 2 waveform generate register 1 G2PO1
014316
014416 Group 2 waveform generate register 2 G2PO2
014516
014616 Group 2 waveform generate register 3 G2PO3
014716
014816 Group 2 waveform generate register 4 G2PO4
014916
014A16 Group 2 waveform generate register 5 G2PO5
014B16
014C16 Group 2 waveform generate register 6 G2PO6
014D16
014E16 Group 2 waveform generate register 7 G2PO7
014F16
Address Register
015016 Group 2 waveform generate control register 0 G2POCR0
015116 Group 2 waveform generate control register 1 G2POCR1
015216 Group 2 waveform generate control register 2 G2POCR2
015316 Group 2 waveform generate control register 3 G2POCR3
015416 Group 2 waveform generate control register 4 G2POCR4
015516 Group 2 waveform generate control register 5 G2POCR5
015616 Group 2 waveform generate control register 6 G2POCR6
015716 Group 2 waveform generate control register 7 G2POCR7
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016 Group 2 base timer register G2BT
016116
016216 Group 2 base timer control register 0 G2BCR0
016316 Group 2 base timer control register 1 G2BCR1
016416 Base timer start register BTSR
016516
016616 Group 2 function enable register G2FE
016716 Group 2 RTP output buffer register G2RTP
016816
016916
016A16 Group 2 SI/O communication mode register G2MR
016B16 Group 2 SI/O communication control register G2CR
016C16 Group 2 SI/O transmit buffer register G2TB
016D16
016E16 Group 2 SI/O receive buffer register G2RB
016F16
017016 Group 2 IEBus address register IEAR
017116
017216 Group 2 IEBus control register IECR
017316
Group 2 IEBus transmit interrupt cause detect register
IETIF
017416
Group 2 IEBus receive interrupt cause detect register
IERIF
017516
017616
017716
017816 Input function select register IPS
017916
017A16 Group 3 SI/O communication mode register G3MR
017B16 Group 3 SI/O communication control register G3CR
017C16 Group 3 SI/O transmit buffer register G3TB
017D16
017E16
Group 3 SI/O receive buffer register G3RB
017F16
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
41
Address Register
018016 Group 3 waveform generate register 0 G3PO0
018116
018216 Group 3 waveform generate register 1 G3PO1
018316
018416 Group 3 waveform generate register 2 G3PO2
018516
018616 Group 3 waveform generate register 3 G3PO3
018716
018816 Group 3 waveform generate register 4 G3PO4
018916
018A16 Group 3 waveform generate register 5 G3PO5
018B16
018C16 Group 3 waveform generate register 6 G3PO6
018D16
018E16 Group 3 waveform generate register 7 G3PO7
018F16
019016 Group 3 waveform generate control register 0 G3POCR0
019116 Group 3 waveform generate control register 1 G3POCR1
019216 Group 3 waveform generate control register 2 G3POCR2
019316 Group 3 waveform generate control register 3 G3POCR3
019416 Group 3 waveform generate control register 4 G3POCR4
019516 Group 3 waveform generate control register 5 G3POCR5
019616 Group 3 waveform generate control register 6 G3POCR6
019716 Group 3 waveform generate control register 7 G3POCR7
019816 Group 3 waveform generate mask register 4 G3MK4
019916
019A16 Group 3 waveform generate mask register 5 G3MK5
019B16
019C16 Group 3 waveform generate mask register 6 G3MK6
019D16
019E16 Group 3 waveform generate mask register 7 G3MK7
019F16
01A016 Group 3 base timer register G3BT
01A116
01A216 Group 3 base timer control register 0 G3BCR0
01A316 Group 3 base timer control register 1 G3BCR1
01A416
01A516
01A616 Group 3 function enable register G3FE
01A716 Group 3 RTP output buffer register G3RTP
01A816
01A916
01AA16
01AB16
Group 3 high-speed HDLC communication control register 1 HDLC1
01AC16
Group 3 high-speed HDLC communication control register
HDLC
01AD16 Group 3 high-speed HDLC communication register
HDLCF
01AE16 Group 3 high-speed HDLC transmit counter HDLCC
01AF16
Address Register
01B016
Group 3 high-speed HDLC data compare register 0 HDLCCP0
01B116
01B216
Group 3 high-speed HDLC data mask register 0 HDLCMK0
01B316
01B416
Group 3 high-speed HDLC data compare register1 HDLCCP1
01B516
01B616
Group 3 high-speed HDLC data mask register 1 HDLCMK1
01B716
01B816
Group 3 high-speed HDLC data compare register 2 HDLCCP2
01B916
01BA16
Group 3 high-speed HDLC data mask register 2 HDLCMK2
01BB16
01BC16
Group 3 high-speed HDLC data compare register 3 HDLCCP3
01BD16
01BE16
Group 3 high-speed HDLC data mask register 3 HDLCMK3
01BF16
01C016 A-D1 register 0 AD10
01C116
01C216 A-D1 register 1 AD11
01C316
01C416 A-D1 register 2 AD12
01C516
01C616 A-D1 register 3 AD13
01C716
01C816 A-D1 register 4 AD14
01C916
01CA16 A-D1 register 5 AD15
01CB16
01CC16 A-D1 register 6 AD16
01CD16
01CE16 A-D1 register 7 AD17
01CF16
01D016
01D116
01D216
01D316
01D416 A-D1 control register 2 AD1CON2
01D516
01D616 A-D1 control register 0 AD1CON0
01D716 A-D1 control register 1 AD1CON1
01D816
01D916
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
42
Address Register
01E016 CAN0 message slot buffer 0 standard ID0 C0SLOT0_0
01E116 CAN0 message slot buffer 0 standard ID1 C0SLOT0_1
01E216 CAN0 message slot buffer 0 extend ID0 C0SLOT0_2
01E316 CAN0 message slot buffer 0 extend ID1 C0SLOT0_3
01E416 CAN0 message slot buffer 0 extend ID2 C0SLOT0_4
01E516 CAN0 message slot buffer 0 data length code C0SLOT0_5
01E616 CAN0 message slot buffer 0 data 0 C0SLOT0_6
01E716 CAN0 message slot buffer 0 data 1 C0SLOT0_7
01E816 CAN0 message slot buffer 0 data 2 C0SLOT0_8
01E916 CAN0 message slot buffer 0 data 3 C0SLOT0_9
01EA16 CAN0 message slot buffer 0 data 4 C0SLOT0_10
01EB16 CAN0 message slot buffer 0 data 5 C0SLOT0_11
01EC16 CAN0 message slot buffer 0 data 6 C0SLOT0_12
01ED16 CAN0 message slot buffer 0 data 7 C0SLOT0_13
01EE16 CAN0 message slot buffer 0 time stamp highC0SLOT0_14
01EF16 CAN0 message slot buffer 0 time stamp low C0SLOT0_15
01F016 CAN0 message slot buffer 1 standard ID0 C0SLOT1_0
01F116 CAN0 message slot buffer 1 standard ID1 C0SLOT1_1
01F216 CAN0 message slot buffer 1 extend ID0 C0SLOT1_2
01F316 CAN0 message slot buffer 1 extend ID1 C0SLOT1_3
01F416 CAN0 message slot buffer 1 extend ID2 C0SLOT1_4
01F516 CAN0 message slot buffer 1 data length code C0SLOT1_5
01F616 CAN0 message slot buffer 1 data 0 C0SLOT1_6
01F716 CAN0 message slot buffer 1 data 1 C0SLOT1_7
01F816 CAN0 message slot buffer 1 data 2 C0SLOT1_8
01F916 CAN0 message slot buffer 1 data 3 C0SLOT1_9
01FA16 CAN0 message slot buffer 1 data 4 C0SLOT1_10
01FB16 CAN0 message slot buffer 1 data 5 C0SLOT1_11
01FC16 CAN0 message slot buffer 1 data 6 C0SLOT1_12
01FD16 CAN0 message slot buffer 1 data 7 C0SLOT1_13
01FE16 CAN0 message slot buffer 1 time stamp highC0SLOT1_14
01FF16 CAN0 message slot buffer 1 time stamp low C0SLOT1_15
020016 CAN0 control register 0 C0CTLR0
020116
020216 CAN0 status register C0STR
020316
020416 CAN0 expansion ID register C0IDR
020516
020616 CAN0 configuration register C0CONR
020716
020816 CAN0 time stamp register C0TSR
020916
020A16 CAN0 transmit error count register C0TEC
020B16 CAN0 receive error count register C0REC
020C16 CAN0 slot interrupt status register C0SISTR
020D16
020E16
020F16
Address Register
021016 CAN0 slot interrupt mask register C0SIMKR
021116
021216
021316
021416 CAN0 error interrupt mask register C0EIMKR
021516 CAN0 error interrupt status register C0EISTR
021616
021716 CAN0 baud rate prescaler C0BPR
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816 CAN0 global mask register standard ID0 C0GMR0
022916 CAN0 global mask register standard ID1 C0GMR1
022A16 CAN0 global mask register extend ID0 C0GMR2
022B16 CAN0 global mask register extend ID1 C0GMR3
022C16 CAN0 global mask register extend ID2 C0GMR4
022D16
022E16
022F16
023016 CAN0 message slot 0 control register / C0MCTL0/
CAN0 local mask register A standard ID0 C0LMAR0
023116 CAN0 message slot 1 control register / C0MCTL1/
CAN0 local mask register A standard ID1 C0LMAR1
023216 CAN0 message slot 2 control register / C0MCTL2/
CAN0 local mask register A extend ID0 C0LMAR2
023316 CAN0 message slot 3 control register / C0MCTL3/
CAN0 local mask register A extend ID1 C0LMAR3
023416 CAN0 message slot 4 control register / C0MCTL4/
CAN0 local mask register A extend ID2 C0LMAR4
023516 CAN0 message slot 5 control register C0MCTL5
023616 CAN0 message slot 6 control register C0MCTL6
023716 CAN0 message slot 7 control register C0MCTL7
023816 CAN0 message slot 8 control register / C0MCTL8/
CAN0 local mask register B standard ID0 C0LMBR0
The blank area is reserved and cannot be used by user.
Note 1: CAN0 message slot i control registers (i=0 to 15) are allocated to addresses 023016 to 023F16 by switching
banks.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
43
Address Register
023916 CAN0 message slot 9 control register / C0MCTL9/
CAN0 local mask register B standard ID1 C0LMBR1
023A16 CAN0 message slot 10 control register / C0MCTL10/
CAN0 local mask register B extend ID0 C0LMBR2
023B16 CAN0 message slot 11 control register / C0MCTL11/
CAN0 local mask register B extend ID1 C0LMBR3
023C16 CAN0 message slot 12 control register / C0MCTL12/
CAN0 local mask register B extend ID2 C0LMBR4
023D16 CAN0 message slot 13 control register C0MCTL13
023E16 CAN0 message slot 14 control register C0MCTL14
023F16 CAN0 message slot 15 control register C0MCTL15
024016 CAN0 slot buffer select register C0SBS
024116 CAN0 control register 1 C0CTLR1
024216 CAN0 sleep control register C0SLPR
024316
024416 CAN0 acceptance filter support register C0AFS
024516
Address Register
02C016 X0 register/Y0 register X0R/Y0R
02C116
02C216 X1 register/Y1 register X1R/Y1R
02C316
02C416 X2 register/Y2 register X2R/Y2R
02C516
02C616 X3 register/Y3 register X3R/Y3R
02C716
02C816 X4 register/Y4 register X4R/Y4R
02C916
02CA16 X5 register/Y5 register X5R/Y5R
02CB16
02CC16 X6 register/Y6 register X6R/Y6R
02CD16
02CE16 X7 register/Y7 register X7R/Y7R
02CF16
02D016 X8 register/Y8 register X8R/Y8R
02D116
02D216 X9 register/Y9 register X9R/Y9R
02D316
02D416 X10 register/Y10 register X10R/Y10R
02D516
02D616 X11 register/Y11 register X11R/Y11R
02D716
02D816 X12 register/Y12 register X12R/Y12R
02D916
02DA16 X13 register/Y13 register X13R/Y13R
02DB16
02DC16 X14 register/Y14 register X14R/Y14R
02DD16
02DE16 X15 register/Y15 register X15R/Y15R
02DF16
02E016 XY control register XYC
02E116
02E216
02E316
02E416 UART1 special mode register 4 U1SMR4
02E516 UART1 special mode register 3 U1SMR3
02E616 UART1 special mode register 2 U1SMR2
02E716 UART1 special mode register U1SMR
02E816 UART1 transmit-receive mode register U1MR
02E916 UART1 bit rate generator U1BRG
02EA16 UART1 transmit buffer register U1TB
02EB16
02EC16 UART1 transmit-receive control register 0 U1C0
02ED16 UART1 transmit-receive control register 1 U1C1
02EE16 UART1 receive buffer register U1RB
02EF16
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
44
Address Register
02F016
02F116
02F216
02F316
02F416 UART4 special mode register 4 U4SMR4
02F516 UART4 special mode register 3 U4SMR3
02F616 UART4 special mode register 2 U4SMR2
02F716 UART4 special mode register U4SMR
02F816 UART4 transmit-receive mode register U4MR
02F916 UART4 bit rate generator U4BRG
02FA16 UART4 transmit buffer register U4TB
02FB16
02FC16 UART4 transmit-receive control register 0 U4C0
02FD16 UART4 transmit-receive control register 1 U4C1
02FE16 UART4 receive buffer register U4RB
02FF16
030016 Timer B3,B4,B5 count start flag TBSR
030116
030216 Timer A1-1 register TA11
030316
030416 Timer A2-1 register TA21
030516
030616 Timer A4-1 register TA41
030716
030816 Three-phase PWM control register 0 INVC0
030916 Three-phase PWM control register 1 INVC1
030A16 Three-phase output buffer register 0 IDB0
030B16 Three-phase output buffer register 1 IDB1
030C16 Dead time timer DTT
030D16
Timer B2 interrupt occurrence frequency set counter
ICTB2
030E16
030F16
031016 Timer B3 register TB3
031116
031216 Timer B4 register TB4
031316
031416 Timer B5 register TB5
031516
031616
031716
031816
031916
031A16
031B16 Timer B3 mode register TB3MR
031C16 Timer B4 mode register TB4MR
031D16 Timer B5 mode register TB5MR
031E16
031F16 External interrupt cause select register IFSR
Address Register
032016
032116
032216
032316
032416 UART3 special mode register 4 U3SMR4
032516 UART3 special mode register 3 U3SMR3
032616 UART3 special mode register 2 U3SMR2
032716 UART3 special mode register U3SMR
032816 UART3 transmit-receive mode register U3MR
032916 UART3 bit rate generator U3BRG
032A16 UART3 transmit buffer register U3TB
032B16
032C16 UART3 transmit-receive control register 0 U3C0
032D16 UART3 transmit-receive control register 1 U3C1
032E16 UART3 receive buffer register U3RB
032F16
033016
033116
033216
033316
033416 UART2 special mode register 4 U2SMR4
033516 UART2 special mode register 3 U2SMR3
033616 UART2 special mode register 2 U2SMR2
033716 UART2 special mode register U2SMR
033816 UART2 transmit-receive mode register U2MR
033916 UART2 bit rate generator U2BRG
033A16 UART2 transmit buffer register U2TB
033B16
033C16 UART2 transmit/receive control register 0 U2C0
033D16 UART2 transmit/receive control register 1 U2C1
033E16 UART2 receive buffer register U2RB
033F16
034016 Count start flag TABSR
034116 Clock prescaler reset flag CPSRF
034216 One-shot start flag ONSF
034316 Trigger select register TRGSR
034416 Up-down flag UDF
034516
034616 Timer A0 register TA0
034716
034816 Timer A1 register TA1
034916
034A16 Timer A2 register TA2
034B16
034C16 Timer A3 register TA3
034D16
034E16 Timer A4 register TA4
034F16
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
45
Address Register
035016 Timer B0 register TB0
035116
035216 Timer B1 register TA1
035316
035416 Timer B2 register TA2
035516
035616 Timer A0 mode register TA0MR
035716 Timer A1 mode register TA1MR
035816 Timer A2 mode register TA2MR
035916 Timer A3 mode register TA3MR
035A16 Timer A4 mode register TA4MR
035B16 Timer B0 mode register TB0MR
035C16 Timer B1 mode register TB1MR
035D16 Timer B2 mode register TB2MR
035E16 Timer B2 special mode register TB2SC
035F16 Count source prescaler register TCSPR
036016
036116
036216
036316
036416 UART0 special mode register 4 U0SMR4
036516 UART0 special mode register 3 U0SMR3
036616 UART0 special mode register 2 U0SMR2
036716 UART0 special mode register U0SMR
036816 UART0 transmit/receive mode register U0MR
036916 UART0 bit rate generator U0BRG
036A16 UART0 transmit buffer register U0TB
036B16
036C16 UART0 transmit/receive control register 0 U0C0
036D16 UART0 transmit/receive control register 1 U0C1
036E16 UART0 receive buffer register U0RB
036F16
037016
037116
037216
037316
037416
037516
037616 PLL control register 0 PLC0
037716
037816 DMA0 cause select register DM0SL
037916 DMA1 cause select register DM1SL
037A16 DMA2 cause select register DM2SL
037B16 DMA3 cause select register DM3SL
037C16 CRC data register CRCD
037D16
037E16 CRC input register CRCIN
037F16
The blank area is reserved and cannot be used by user.
Address Register
038016 A-D0 register 0 AD00
038116
038216 A-D0 register 1 AD01
038316
038416 A-D0 register 2 AD02
038516
038616 A-D0 register 3 AD03
038716
038816 A-D0 register 4 AD04
038916
038A16 A-D0 register 5 AD05
038B16
038C16 A-D0 register 6 AD06
038D16
038E16 A-D0 register 7 AD07
038F16
039016
039116
039216
039316
039416 A-D0 control register 2 AD0CON2
039516
039616 A-D0 control register 0 AD0CON0
039716 A-D0 control register 1 AD0CON1
039816 D-A register 0 DA0
039916
039A16 D-A register 1 DA1
039B16
039C16 D-A control register DACON
039D16
039E16
039F16
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
46
<144-pin version>
Address Register
03A016 Function select register A8 PS8
03A116 Function select register A9 PS9
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16 Function select register C PSC
03B016 Function select register A0 PS0
03B116 Function select register A1 PS1
03B216 Function select register B0 PSL0
03B316 Function select register B1 PSL1
03B416 Function select register A2 PS2
03B516 Function select register A3 PS2
03B616 Function select register B2 PSL2
03B716 Function select register B3 PSL3
03B816
03B916 Function select register A5 PS5
03BA16
03BB16
03BC16 Function select register A6 PS6
03BD16 Function select register A7 PS7
03BE16
03BF16
03C016 Port P6 register P6
03C116 Port P7 register P7
03C216 Port P6 direction register PD6
03C316 Port P7 direction register PD7
03C416 Port P8 register P8
03C516 Port P9 register P9
03C616 Port P8 direction register PD8
03C716 Port P9 direction register PD9
03C816 Port P10 register P10
03C916 Port P11 register P11
03CA16 Port P10 direction register PD10
03CB16 Port P11 direction register PD11
03CC16 Port P12 register P12
03CD16 Port P13 register P13
03CE16 Port P12 direction register PD12
03CF16 Port P13 direction register PD13
Address Register
03D016 Port P14 register P14
03D116 Port P15 register P15
03D216 Port P14 direction register PD14
03D316 Port P15 direction register PD15
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-up control register 2 PUR2
03DB16 Pull-up control register 3 PUR3
03DC16 Pull-up control register 4 PUR4
03DD16
03DE16
03DF16
03E016 Port P0 register P0
03E116 Port P1 register P1
03E216 Port P0 direction register PD0
03E316 Port P1 direction register PD1
03E416 Port P2 register P2
03E516 Port P3 register P3
03E616 Port P2 direction register PD2
03E716 Port P3 direction register PD3
03E816 Port P4 register P4
03E916 Port P5 register P5
03EA16 Port P4 direction register PD4
03EB16 Port P5 direction register PD5
03EC16
03ED16
03EE16
03EF16
03F016 Pull-up control register 0 PUR0
03F116 Pull-up control register 1 PUR1
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16 Port control register PCR
The blank area is reserved and cannot be used by user.
SFR
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
47
1234567890123456789012345678901212345678901234567890123456789012
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1234567890123456789012345678901212345678901234567890123456789012
1234567890123456789012345678901212345678901234567890123456789012
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1
23456789012345678901234567890121234567890123456789012345678901
2
1234567890123456789012345678901212345678901234567890123456789012
12345678901234567890123456789012123456789
1
234567890123456789012345678901212345678
9
12345678901234567890123456789012123456789
12345678901234567890123456789
1
234567890123456789012345678
9
1
234567890123456789012345678
9
12345678901234567890123456789
12345678901234567890123456789
1
234567890123456789012345678
9
1
234567890123456789012345678
9
12345678901234567890123456789
12345678901234567890123456789
1
234567890123456789012345678
9
12345678901234567890123456789
12345678901234567890123456789
1
234567890123456789012345678
9
1
234567890123456789012345678
9
12345678901234567890123456789
12345678901234567890123456789
1
234567890123456789012345678
9
12345678901234567890123456789
12345678901234567890123456789
1
234567890123456789012345678
9
1
234567890123456789012345678
9
12345678901234567890123456789
<100-pin version>
Address Register
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16 Function select register C PSC
03B016 Function select register A0 PS0
03B116 Function select register A1 PS1
03B216 Function select register B0 PSL0
03B316 Function select register B1 PSL1
03B416 Function select register A2 PS2
03B516 Function select register A3 PS3
03B616 Function select register B2 PSL2
03B716 Function select register B3 PSL3
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016 Port P6 register P6
03C116 Port P7 register P7
03C216 Port P6 direction register PD6
03C316 Port P7 direction register PD7
03C416 Port P8 register P8
03C516 Port P9 register P9
03C616 Port P8 direction register PD8
03C716 Port P9 direction register PD9
03C816 Port P10 register P10
03C916
03CA16 Port P10 direction register PD10
03CB16
03CC16
03CD16
03CE16
03CF16
Address Register
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-up control register 2 PUR2
03DB16 Pull-up control register 3 PUR3
03DC16
03DD16
03DE16
03DF16
03E016 Port P0 register P0
03E116 Port P1 register P1
03E216 Port P0 direction register PD0
03E316 Port P1 direction register PD1
03E416 Port P2 register P2
03E516 Port P3 register P3
03E616 Port P2 direction register PD2
03E716 Port P3 direction register PD3
03E816 Port P4 register P4
03E916 Port P5 register P5
03EA16 Port P4 direction register PD4
03EB16 Port P5 direction register PD5
03EC16
03ED16
03EE16
03EF16
03F016 Pull-up control register 0 PUR0
03F116 Pull-up control register 1 PUR1
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16 Port control register PCR
1234567
1
23456
7
1
23456
7
1234567
12345
1
234
5
12345
The blank area is reserved and cannot be used by user.
Note 1: Addresses 03CB16, 03CE16, 03CF16, 03D216, 03D316 does not exist in 100-pin version. Must set
"FF16" to the addresses at initial setting.
Note 2:
Addresses 03DC
16
area does not exist in 100-pin version. Must set "00
16
" to addresses 03DC
16
at initial setting.
Note 3: Addresses 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16, 03CD16, 03D3016, 03D116
does not exist in 100-pin version.
1234
1234
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
48
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, memory map, and access space differ according to the
selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P15 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as an address bus, a data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. There-
fore, never change the processor mode bits when changing the contents of other bits. Also do not
attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1.
Figure 1.6.3 shows the memory maps applicable for each processor modes.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
49
Processor Mode
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
0 1 : Allocated to CS1 space
1 1 : Allocated to entire CS space
(Note 5)
Note 1: Set bit 1 of the protect register (address 000A
16
) to "1" when writing new values to this register.
Note 2: Do not set the processor mode bits and other bits simultaneously when setting the processor
mode bits to 012 or 112 . Set the other bits first,and then change the processor mode bits.
Note 3: When using 16-bit bus width in DRAM controler, must set this bit to "1".
Note 4: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus
when mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 5: After the reset has been released, the M32C/83 group MCU operates using the separate bus. As
a result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries, for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 6: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock
output in microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0
(CM00) and bit 1 (CM01) of system clock control register 0 (address 0006
16
) = "0". "L" is now
output from P5
3
.
Note 7: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Symbol Address When reset
PM0 0004
16
80
16 (CNVss = "L")
03
16 (CNVss = "H")
Processor mode register 0 (Note 1)
RW
b1 b0
b5 b4
0: RD / BHE / WR
1: RD / WRH / WRL
PM00
PM01
PM02
(Note 3)
(Note 2)
PM03
Software reset bit
R/W mode select bit
PM04
PM05
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
Must always be set to "0"
PM07
BCLK output disable bit
(Note 6)
Reserved bit
0 : BCLK is output (Note 7)
1 : Function set by bit 0,1 of system
clock control register 0
The device is reset when this bit is
set to "1". The value of this bit is "0"
when read
Bit name Function
Bit
symbol
Processor mode bit
Multiplexed bus space
select bit
(Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Figure 1.6.1. Processor mode register 0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
50
Processor Mode
Processor mode register 1
(Note 1)
When reset
0X000000
2
Address
0005
16
Symbol
PM1
RW
PM10
PM11
PM12
External memory area
mode bit (Note 2)
PM13
Internal memory wait bit 0 : No wait state
1 : Wait state inserted
SFR area wait bit 0
Reserved bit Must set to "0"
0 : One wait state inserted
1 : Two wait states inserted (Note 4)
PM14
PM15
PM17
ALE pin select bit
(Note 2)
0 0 : No ALE
0 1 : P53/BCLK (Note 5)
1 0 : P56/RAS
1 1 : P54/HLDA
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 0 : Mode 0 (P44 to P47 : A20 to A23)
0 1 : Mode 1 (P44: A20,
P45 to P47: CS2 to CS0)
1 0 : Mode 2 (P44, P45 : A20, A21,
P46, P47 : CS1, CS0)
1 1 : Mode 3 (Note 3)
(P44 to P47 : CS3 to CS0)
b1 b0
b5 b4
Bit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: Valid in memory expansion mode or in microprocessor mode.
Note 3: When mode 3 is selected, DRAMC is not used.
Note 4: When accessing SFR area for CAN, PM13 must be set to "1".
Note 5: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
0
Figure 1.6.2. Processor mode register 1
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
51
Processor Mode
Single chip
mode Memory expanded mode Microprocessor mode
SFR area
Internal RAM area Internal reserved area
Internal ROM area
No use
External area 0
CS2
2Mbytes
External area 1
CS0
2Mbytes
External area 3
No use
Internal ROM area
Internal reserved area Internal ROM area
Internal reserved area Internal ROM area
Internal reserved area
CS0
3Mbytes
External area 3
CS1
4Mbytes
(Note2)
External area 0
External area 3
No use
CS0
2Mbytes
External area 3
CS0
4Mbytes
External area 3
000000
16
000400
16
000800
16
200000
16
400000
16
C00000
16
E00000
16
F00000
16
FFFFFF
16
Each CS0 to CS3 can set 0 to 3 WAIT.
Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2
SFR area
Internal RAM area Internal reserved area
SFR area
Internal RAM area Internal reserved area
SFR area
Internal RAM area Internal reserved area
SFR area
Internal RAM area Internal reserved area
SFR area
Internal RAM area Internal reserved area
SFR area
Internal RAM area
Mode 3
Internal reserved area
SFR area
Internal RAM area
Internal ROM area
Internal reserved area
CS1, 1Mbytes
External area 0
Mode 3
Internal reserved area
SFR area
Internal RAM area
No use
CS2, 1Mbytes
External area 1
No use
Connect with
DRAM
0, 0.5 to 8MB
(When not
connect with
DRAM, use as
external area.)
Connect with
DRAM
0, 0.5 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
Connect with
DRAM
0, 0.5 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
Connect with
DRAM
0, 0.5 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
No use
(Cannot use as
DRAM area or
external area.)
Connect with
DRAM
0, 0.5 to 8MB
(When not
connect with
DRAM, use as
external area.)
Connect with
DRAM
0, 0.5 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
No use
(Cannot use as
DRAM area or
external area.)
No use
No use
No use
CS1
2Mbytes
(Note1)
External area 0
No use
Note 1: 200000
16
–008000
16
=2016 Kbytes. 32 K less than 2 MB.
Note 2: 400000
16
–008000
16
=4064 Kbytes. 32 K less than 4 MB.
External area 1
External area 0
CS2
2Mbytes
External area 1
CS1
4Mbytes
(Note2)
External area 0
CS1, 1Mbytes
External area 0
CS2, 1Mbytes
External area 1
CS1
2Mbytes
(Note1)
External area 0
External area 1
(External area 2) (External area 2) (External area 2) (External area 2) (External area 2) (External area 2)
External area 3
CS3, 1Mbytes
External area 2
CS0, 1Mbytes
External area 3
CS3, 1Mbytes
External area 2
CS0, 1Mbytes
External area 3
Processor Mode
Figure 1.6.3. Memory maps in each processor mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
52
Table 1.7.1. Factors for switching bus settings
Bus Settings
The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the
processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address
000516) are used to change the bus settings.
Table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width
control register and table 1.7.2 shows external area 0 to 3 and external area mode.
Bus setting Switching factor
Switching external address bus width External data bus width control register
Switching external data bus width BYTE pin (external area 3 only)
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
Selecting external area Bits 0 and 1 of processor mode register 1
(1) Selecting external address bus width
You can select the width of the address bus output externally from the 16 Mbytes address space, the
number of chip select signals, and the address area of the chip select signals. (Note, however, that
____
when you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits
0 and 1 of the processor mode register 1 allow you to set the external area mode.
When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row
and column addresses.
(2) Selecting external data bus width
You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When
the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;
when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for
external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after
a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16
bits).
During operation, fix the level of the BYTE pin to “H” or “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this bus configuration, input and output is performed on separate data and address buses. The data
bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all
programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is
a programmable IO port. When the external data bus width is set to 16 bits for any of the external
areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data buses.
When accessing memory using the separate bus configuration, you can select a software wait using
the wait control register.
• Multiplex bus
In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas
for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7
are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the external
data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to A15. When
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
53
External data bus width control register
Symbol Address When reset
DS 000B
16 XXXXX0002
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DS3
DS1
DS0 External area 0 data bus
width bit
DS2
External area 1 data bus
width bit
External area 2 data bus
width bit
External area 3 data bus
width bit (Note)
0 : 8 bits data bus width
1 : 16 bits data bus width
Note: The value after a reset is determined by the input via the BYTE pin.
When BYTE pin is "L", DS3 is "1". When "H", it is "0".
WR
AA
A
AA
A
AA
A
AA
A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 : 8 bits data bus width
1 : 16 bits data bus width
0 : 8 bits data bus width
1 : 16 bits data bus width
0 : 8 bits data bus width
1 : 16 bits data bus width
External area mode
(Note 2) Mode 0 Mode 1 Mode 2 Mode 3
External
area 0
External
area 1
External
area 2
External
area 3
Memory expansion mode
Memory expansion mode
,
Microprocessor mode
Microprocessor mode
Memory expansion mode
,
Microprocessor mode
008000
16
to
1FFFFF
16
200000
16
to
3FFFFF
16
400000
16
to
BFFFFF
16
(Note 1)
C00000
16
to
EFFFFF
16
C00000
16
to
FFFFFF
16
<CS1 area>
008000
16
to
1FFFFF
16
<CS2 area>
200000
16
to
3FFFFF
16
<DRAMC area>
400000
16
to
BFFFFF
16
<CS0 area>
C00000
16
to
EFFFFF
16
<CS0 area>
E00000
16
to
FFFFFF
16
<CS1 area>
008000
16
to
1FFFFF
16
<DRAMC area>
400000
16
to
BFFFFF
16
<CS0 area>
C00000
16
to
EFFFFF
16
<CS0 area>
C00000
16
to
FFFFFF
16
<CS1 area>
100000
16
to
1FFFFF
16
<CS2 area>
200000
16
to
2FFFFF
16
<CS3 area>
C00000
16
to
CFFFFF
16
<CS0 area>
E00000
16
to
EFFFFF
16
<CS0 area>
F00000
16
to
FFFFFF
16
Memory expansion mode
,
Microprocessor mode
No area is
selected.
accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether
you select “No wait” or “1 wait” in the appropriate bit of the wait control register.
____
The default after a reset is a separate bus configuration, and the full CS space multiplex bus configu-
____
ration cannot be selected in microprocessor mode. If you select “Full CS space multiplex bus”, the 16
bits from A0 to A15 are output for the address
Figure 1.7.1. External data bus width control register
Table 1.7.2. External area 0 to 3 and external area mode
Note 1: DRAMC area when using DRAMC.
Note 2:Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register
1 (address 000516).
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
54
P0
0
to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port I/O port
CS1 or CS2 : multiplexed
bus, and the other :
separate bus
Separate bus All space multiplexed
bus
Single-chip
mode Memory expansion mode/microprocessor modes Memory
expansion mode
Data bus width
BYTE pin level
“01”, “10”“00”“11” (Note 1)
All external
area is 8 bits
Some external
area is 16 bits
All external
area is 8 bits Some external
area is 16 bits
Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected the DRAM controller and access the DRAM area, these are outputs CASL, CASH, DW, and
BCLK.
Note 5: The CS signal and address bus selection are set by the external area mode.
Processor
mode
Multiplexed
bus space
select bit
CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”) (Note 3,4)
P1
0
to P1
7
I/O port I/O port I/O port Data bus I/O port I/O port I/O port
P2
0
to P2
7
I/O port Address bus Address bus Address bus Address bus Address bus Address bus
/data bus /data bus /data bus /data bus
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port I/O port
P4
4
to P4
6
I/O port CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3)
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD HOLD
P5
6
I/O port RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3)
P5
7
I/O port RDY RDY RDY RDY RDY RDY
P3
0
to P3
7
I/O port Address bus Address bus Address bus Address bus Address bus Address bus
/data bus /data bus
(Note 2) (Note 2)
(Note 2)
All external
area is 8 bits Some external
area is 16 bits
Table 1.7.3. Each processor mode and port function
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
55
Processor mode
Memory space
expansion
mode
Specified address range
Memory expansion mode
Mode 0
Chip select signal
CS0 CS1 CS2 CS3
C00000
16
to
DFFFFF
16
(2 Mbytes)
Microprocessor mode
Memory expansion mode
008000
16
to
1FFFFF
16
(2016 Kbytes)
200000
16
to
3FFFFF
16
(2 Mbytes)
008000
16
to
3FFFFF
16
(4064 Kbytes)
Microprocessor mode
E00000
16
to
FFFFFF
16
(2 Mbytes)
C00000
16
to
EFFFFF
16
(3 Mbytes)
C00000
16
to
FFFFFF
16
(4 Mbytes)
E00000
16
to
EFFFFF
16
(1 Mbytes) 100000
16
to
1FFFFF
16
(1 Mbytes)
Mode 1
Mode 2
Mode 3
Memory expansion mode
Microprocessor mode F00000
16
to
FFFFFF
16
(1 Mbytes)
200000
16
to
2FFFFF
16
(1 Mbytes)
C00000
16
to
CFFFFF
16
(1 Mbytes)
(A22) (A21) (A20)
(A23)
(A21) (A20)
(A20)
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expan-
sion mode and microprocessor mode.
(1) Address bus/data bus _____
There are 24 pins, A0 to A22 and A23 for the address bus for accessing the 16 Mbytes address space.
_____
A23 is an inverted output of the MSB of the address.
The data bus consists of pins for data IO. The external data bus control register (address 000B16)
selects the 8-bit data bus, D0 to D7 for each external area, or the 16-bit data bus, D0 to D15. After a reset,
there is by default an 8-bit data bus for the external area 3 when the BYTE pin is High, or a 16-bit data
bus when the BYTE pin is Low.
When shifting from single-chip mode to extended memory mode, the value on the address bus is unde-
fined until an external area is accessed.
When accessing a DRAM area with DRAM control in use, a multiplexed signal consisting of row address
and column address is output to A8 to A20.
(2) Chip select signals _____
The chip select signals share A0 to A22 and A23. You can use bits 0 and 1 of the processor mode register
1 (address 000516) to set the external area mode, then select the chip select area and number of
address outputs.
In microprocessor mode, external area mode 0 is selected after a reset. The external area can be split
into a maximum of four Blocks or Areas using the chip select signals. Table 1.7.4 shows the external
areas specified by the chip select signals.
Table 1.7.4. External areas specified by the chip select signals
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
56
Example 1: After accessing the external area, the
address bus and chip select signal both are
changed in the next cycle.
The following example shows the other chip select
signal accessing area (j) in the cycle after having
accessed external area (i). In this case, the address
bus and chip select signal both change between the
two cycles.
Note: These examples show the address bus and chip select signal for two consecutive cycles.
By combining these examples, chip select signal can be extended beyond two cycles.
Data bus
Address bus
Chip select
(CSi)
Access to
external
area (i)
Chip select
(CSj)
Access to
external
area (j)
Address
Data
Data
Example 2: After accessing the external area, only the
chip select signal is changed in the next
cycle. (The address bus does not change.)
The following example shows the CPU accesses the
internal ROM/RAM area in the cycle after having
accessed external area. In this case, the chip select
signal changes between the two cycles but the
address bus does not.
Example 3: After accessing the external area, only the
address bus is changed in the next cycle.
(The chip select signal does not change.)
The following example shows the same chip select
signal accessing area (i) in the cycle after having
accessed external area (i). In this case, the address
bus changes between the two cycles, but the chip
select signal does not.
Data bus
Address bus
Chip select
(CSi)
Data
Address
Data bus
Address bus
Chip select
Data
Address
Access to
external
area No access
Access to
external
area (i)
Access to
external
area (i)
Data bus
Address bus
Chip select
Data
Address
Example 4: After accessing the external area, the
address bus and chip select signal both are
not changed in the next cycle.
The following example shows CPU does not access
any area in the cycle after having accessed external
area (no instruction pre-fetch is occurred). In this
case, the address bus and the chip select signal do
not change between the two cycles.
Data
Access to
external
area
Access to
internal
ROM/RAM
area
The chip select signal turns Low (active) in synchronize with the address bus. However, its turning High
depends on the area accessed in the next cycle. Figure 1.7.2 shows the output examples of the address
bus and chip select signals.
Figure 1.7.2. Example of address bus and chip select signal outputs (Separate bus)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
57
Status of external data bus
RD BHEWR
HLL
LHL
HLH
LHH
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width A0
H
H
L
L
HLLL
LHLL
HL H / L
LH H / L
8-bit
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
Not used
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRHWRLRD
Data bus width
16-bit H
H
H
H
L
H
L
H
H
L
L
L
HH (Note)
L (Note)
LNot used Write 1 byte of data
Read 1 byte of data
Not used
8-bit
(3) Read/write signals
With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) selects the combinations
_____ ________ ______ _____ ________ _________
of RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
_____ ______ ________
combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths to access a 8-bit data bus
_____ ______ ________
area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 000416).
Tables 1.7.5 and 1.7.6 show the operation of these signals.
_____ ______ ________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically se-
lected. _____ _________ _________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of
the processor mode register 0 (address 000416) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protect register (address 000A16) to “1”._____ ________ _________
Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
_____ ________ _________
Table 1.7.5. Operation of RD, WRL, and WRH signals
______
Note: It becomes WR signal.
_____ ______ ________
Table 1.7.6. Operation of RD, WR, and BHE signals
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When BYTE pin = “H”When BYTE pin = “L”
ALE
Address Data
Address
D
0
/A
0
to D
7
/A
7
A
8
to A
15
ALE
Address Data
Address
D
0
/A
0
to D
15
/A
15
A
16
to A
19
Note 1: Floating when reading.
Note 2: When full space multiplexed bus is selected, these are I/O ports.
Address
Address or CS
A
20
to A
22
, A
23
Address or CS
A
20
to A
22
, A
23
A
16
to A
19
(Note 1) (Note 1)
(Note 2)(Note 2)
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when
the ALE signal falls. The ALE output pin is selected using bits 4 and 5 of the processor mode register 1
(address 000516).
The ALE signal is occurred regardless of internal area and external area.
Figure 1.7.3. ALE signal and address/data bus
(5) Ready signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
________
Figure 1.7.2, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter
________
the ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table
_____
1.7.7 shows the microcomputer status in the ready state. Figure 1.7.4 shows the example of the RD
________
signal being extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is
________
applied. When no software wait is operating, the RDY signal is ignored, but even in this case, unused
pins must be pulled up.
Table 1.7.7. Microcomputer status in ready state (Note)
Note: The ready signal cannot be received immediately prior to a software wait.
Item Status
Oscillation On
_____ _____ _____
RD/WR signal, address bus, data bus, CS Maintain status when ready signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
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RDY received timing
AA
Separate bus (2 wait)
Multiplexed bus (2 wait)
BCLK
RD
CS
i
(i=0 to 3)
RDY
AAAAAA
AAAAAA
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AAAAAAAA
AAAAAAAA
1st cycle 2nd cycle 3rd cycle 4th cycle
tsu(RDY - BCLK)
RDY received timing
tsu(RDY-BCLK)=RDY input setup time
RDY signal received timing for i wait(s): i + 1 cycles (i = 1 to 3)
1st cycle 2nd cycle 3rd cycle 4th cycle
: Wait using RDY signal
: Wait using software
(Note)
(Note)
Note: Chip select (CSi) may get longer by a state of CPU such as an instruction queue buffer.
_____ ________
Figure 1.7.4. Example of RD signal extended by RDY signal
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__________
HOLD > DMAC > CPU
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L”
__________
to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This
__________ __________
status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table
1.7.8 shows the microcomputer status in the hold state. The bus is used in the following descending
__________
order of priority: HOLD, DMAC, CPU.
_____ ________
Figure 1.7.5. Example of RD signal extended by RDY signal
Table 1.7.8. Microcomputer status in hold state
Item Status
Oscillation ON
_____ _____ _____ _______
RD/WR signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports: P0 to P15 Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Output “L”
(7) External bus status when accessing to internal area
Table 1.7.9 shows external bus status when accessing to internal area
Table 1.7.9. External bus status when accessing to internal area
Item SFR accessing status Internal ROM/RAM accessing status
Address bus Remain address of external area accessed immediately before
Data bus When read Floating
When write Floating
_____ ______ ________ _________
RD, WR, WRL, WRH Output "H"
________
BHE Remain external area status accessed immediately before
____
CS Output "H"
ALE ALE output
(8) BCLK output
BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit
1 and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0”
and CM01 and CM00 to “00” outputs the BCLK signal from P53. However, in single chip mode, BCLK
signal is inactive. When setting PM07 to “1”, the function is set by CM01 and CM00.
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Status of external data bus
RAS CASHCASL
LLL
LLH
LLH
LLL
Read data from both even and odd addresses
Read 1 byte of data from even address
Read 1 byte of data from odd address
Write data to both even and odd addresses
Data bus width DW
H
H
H
L
LLHL
LHLL
LL H
LL L
8-bit
Write 1 byte of data to even address
Write 1 byte of data to odd address
Read 1 byte of data
Write 1 byte of data
16-bit
Not used
Not used
_______ __________ __________ _____
(9) DRAM controller signals (RAS, CASL, CASH, and DW)
Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the
DRAM controller. The DRAM controller signals are output when the DRAM area is accessed. Table
1.7.10 shows the operation of the respective signals.
_______ __________ __________ _____
Table 1.7.10. Operation of RAS, CASL, CASH, and DW signals
(10) Software wait
A software wait can be inserted by setting the wait control register (address 000816). Figure 1.7.6 shows
wait control register.
You can use the external area i wait bits (where i = 0 to 3) of the wait control register to specify from “No
wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in
the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing
external memory using the multiplex bus, access has two waits regardless of whether you specify “No
wait” or “1 wait” in the appropriate external area i wait bits in the wait control register.
Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal
memory wait bits of the processor mode register 1 (address 000516). Setting the internal memory wait
bit = “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait.
SFR area is accessed with either "1 wait" (BCLK 2-cycle) or "2 waits" (BCLK 3-cycle) by setting the SFR
wait bit (bit 3) of the processor mode register 1 (address 000516). SFR area of CAN must be accessed
with "2 waits".
Table 1.7.11 shows the software waits and bus cycles. Figures 1.7.7 and 1.7.8 show example bus timing
when using software waits.
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Area Bus status Internal
memory wait bit External memory
area i wait bit Bus cycle
12 BCLK cycles
External
memory
area
00
2
Read :1 BCLK cycle
Separate bus
Write : 2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
Multiplex bus
4 BCLK cycles
SFR
Internal
ROM/RAM 01 BCLK cycle
2 BCLK cycles
3 BCLK cycle
3 BCLK cycles
3 BCLK cycles
4 BCLK cycles
01
2
11
2
00
2
01
2
11
2
10
2
10
2
3 BCLK cycles
SFR area
wait bit
0
1
Wait control register (Note 1, 2)
Symbol Address When reset
WCR 0008
16
FF
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Without wait
0 1: With 1 wait
1 0: With 2 waits
1 1: With 3 waits
b1 b0
WCR3
WCR1
WCR0 External area 0
wait bit
WCR2 External area 1
wait bit
External area 2
wait bit
WCR4
External area 3
wait bit
WCR5
WCR7
Note 1: When using the multiplex bus configuration, there are two waits regardless of whether you have
specified "No wait" or "1 wait". However, you can specify "2 waits" or "3 waits".
Note 2: When using the separate bus configuration, the read bus cycle is executed in the BCLK1 cycle,
and the write cycle is executed in the BCLK2 cycle (with 1 wait).
WR
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
WCR6
0 0: Without wait
0 1: With 1 wait
1 0: With 2 waits
1 1: With 3 waits
b3 b2
0 0: Without wait
0 1: With 1 wait
1 0: With 2 waits
1 1: With 3 waits
b5 b4
0 0: Without wait
0 1: With 1 wait
1 0: With 2 waits
1 1: With 3 waits
b7 b6
Figure 1.7.6. Wait control register
Table 1.7.11. Software waits and bus cycles
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Output Input
Address Address
Bus cycle (Note)
< Separate bus (with wait) >
BCLK
Read signal
Write signal
Data bus
Address bus (Note 2)
Chip select (Note 2,3)
BCLK
Read signal
Data bus
Chip select (Note 2,3)
Data output
Address
Address bus (Note 2) Address
Input
< Separate bus with 2 wait >
Write signal
BCLK
Read signal
Write signal
Address bus (Note 2) Address
Bus cycle (Note)
< Separate bus (no wait) >
Output
Data bus
Chip select (Note 2,3)
Input
Bus cycle (Note)
Bus cycle (Note)
Bus cycle (Note 1) Bus cycle (Note 1)
Address
Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer depending on the state of CPU such as an instruction
queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.
Figure 1.7.7. Typical bus timings using software wait
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Bus Control
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BCLK
Read signal
Write signal
Address bus/Data bus
(Note 2)
Chip select
(Note 2,3)
Address
Address
Address
Data output
Address
Address
Input
ALE
Bus cycle (Note)
< Multiplexed bus (with 2 wait) > Bus cycle (Note)
BCLK
Read signal
Write signal
Chip select
(Note 2,3)
Bus cycle (Note)
< Separate bus (with 3 wait) >
Address
Address
(Note 2) Address
Bus cycle (Note)
Data bus Data output
Input
BCLK
Read signal
Write signal
Address bus
/Data bus (
Note 2)
Chip select
(Note 2,3)
Address
Address
Data output
Address
Input
Bus cycle (Note)
< Multiplexed bus (with 3 wait) >
Address Address
ALE
Bus cycle (Note)
Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer depending on the state of CPU such as an instruction
queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.
Figure 1.7.8. Typical bus timings using software wait
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Clock Generating Circuit
65
Table 1.8.2. Control registers for each clock generating circuits
Clock generating circuit Control register
Main clock System clock control register 0 (address 000616) :CM0
System clock control register 1 (address 000716) :CM1
Main clock divide register (address 000C16) : MCD
Sub clock System clock control register 0 (address 000616) : CM0
System clock control register 1 (address 000716) :CM1
Oscillation stop detect function Oscillation stop detect register (address 000D16) : CM2
Note : CM0, CM1, CM2 and MCD registers are protected from a false write by program runaway. When you
want to rewrite these registers, set "1" to bit 0 of protect register (address 000A16) to release protect,
then rewrite the register.
System Clock
Clock Generating Circuit
The clock generating circuit contains three oscillator circuits as follows:
(1) Main clock generating circuit
(2) Sub clock generating circuit
(3) Ring oscillator (oscillation stop detect function)
Table 1.8.1 lists the clock generating circuit specifications and Table 1.8.2 lists registers controlling each
clock generating circuit. Figure 1.8.1 shows block diagram of the system clock generating circuit. Figure
1.8.2 to 1.8.5 show clock control related registers.
• CPU's operating
clock source
• Internal peripheral
unit's operating
clock source
Use of clock
Main clock
generating circuit Sub clock
generating circuit
Item
• CPU's operating
clock source
• Timer A/B's count
clock source
Clock frequency 0 to 30 MHz 32.768 kHz
• Ceramic oscillator
• Crystal oscillator
Usable oscillator • Crystal oscillator
X
IN
, X
OUT
Pins to connect
oscillator X
CIN
, X
COUT
Presence
Oscillation stop/
restart function Presence
Oscillating
Oscillator status
after reset Stopped
Externally derived clock can be input
Other
Ring oscillator
• CPU's operating
clock source when
main clock
frequency stops
About 1 MHz
Presence
Stopped
Table 1.8.1. The clock oscillation circuit specifications
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Interrupt
request signal
Clock
from
X
IN
Ring oscillator
clock
Ring oscillator circuit
Charge and
discharge
circuit
Interrupt
generating
circuit
Clock edge detect
/charge and
discharge
circuit control
Watchdog timer
interrupt
CM21 switch
select signal
BCLK
CM05
CM02
CM07
f
C
X
IN
X
OUT
X
CIN
X
COUT
Main clock
Sub clock
CM04
f
C32
1/32
S Q
R
S Q
R
NMI
RESET
Interrupt request level
judgment output
Software reset
(Wait mode) WAIT instruction
(Stop mode) Write "1" to CM10
Divide rate m (m=1,2,3,4,6,8,10,12,14,16 ) is set by bit 0 to 4 at main clock divide register (address 000C
16
)
1/m
e f
Divider 3
Ring
oscillator
Divider 1
1/2 1/2 1/2
a
1/21/n
cd
Divide rate 2n (n=0 to 15) is set by bit 0 to 3 at count source prescaler register (address 035F
16
)
Bit 7 at address 035F
16
Divider 2
ef
Divider 3
f
AD
f
1
Divider 1
ab
f
2
n
cd
Divider 2
CM0i : Bit i at system clock control register 0 (address 0006
16
)
CM1i : Bit i at system clock control register 1 (address 0007
16
)
CM2i : Bit i at oscillation stop detect register (address 000D
16
)
Ring oscillator
circuit
CM21
f
8
b
Figure 1.8.1. Clock generating circuit
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Clock Generating Circuit
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Figure 1.8.2. Clock control related register (1)
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16
0000 X000
2
Bit
name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
3
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM01
CM02
CM00 Clock output function
select bit (Note 2)
WAIT peripheral
function clock stop bit 0 : Do not stop peripheral clock
in wait mode
1 : Stop peripheral clock in
wait mode (Note 3)
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 4)
Main clock (X
IN
-X
OUT
)
stop bit (Note 5) 0 : Main clock On
1 : Main clock Off (Note 6)
System clock select bit
(Note 8) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
WR
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
CM06 Watchdog timer
function select bit 0 : Watchdog timer interrupt
1 : Reset (Note 7)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: The port P5
3
dose not function as an I/O port in microprocessor or memory expansion
mode.
When outputting ALE to P5
3
(bits 5 and 4 of processor mode register 0 is "01"), set
these bits to "00".
The port P5
3
function is not selected, even when you set "00" in microprocessor or
memory expansion mode and bit 7 of the processor mode register 0 is "1".
Note 3: fc
32
is not included. When this bit is set to "1", PLL cannot be used in WAIT.
Note 4: When Xc
IN
-Xc
OUT
is used, set port P8
6
and P8
7
to no pull-up resistance with the input
port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop
the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is
stable. Then set this bit to "1".
When X
IN
is used after returning from stop mode, set this bit to "0".
When this bit is "1", X
OUT
is "H". Also, the internal feedback resistance remains ON, so
X
IN
is pulled up to X
OUT
("H" level) via the feedback resistance.
Note 6: When the main clock is stopped, the main clock division register (address 000C
16
) is set
to the division by 8 mode.
However, in ring oscillator mode, the main clock division register is not set to the division
by 8 mode when X
IN
-X
OUT
is stopped by this bit.
Note 7: When "1" has been set once, "0" cannot be written by software.
Note 8: Set this bit "0" to "1" when sub clock oscillation is stable by setting CM04 to "1".
Set this bit "1" to "0" when main clock oscillation is stable by setting CM05 to "0".
Do not set CM04 and CM05 simultaneously.
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System clock control register 1 (Note 1)
Symbol Address When reset
CM1 0007
16
00100000
2
Bit
name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note 2) 0 : Clock on
1 : All clocks off (stop mode) (Note 3)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
“1” before writing to this register.
Note 2: When this bit is "1", X
OUT
is "H", and the internal feedback resistance is disabled. X
CIN
and X
COUT
are high-inpedance.
Note 3: When all clocks are stopped (stop mode), the main clock division register
(address 000C
16
) is set to the division by 8 mode.
WR
Reserved bit Must set to
“0”
0000
A
A
A
A
A
A
A
A
A
A
A
A
Reserved bit Must set to
“0”
A
A
00
Reserved bit Must set to
“1”
1
Main clock division register (Note 1)
Symbol Address When reset
MCD 000C16 XXX010002
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 1 0 : No division mode
0 0 0 1 0 : Division by 2 mode
0 0 0 1 1 : Division by 3 mode
0 0 1 0 0 : Division by 4 mode
0 0 1 1 0 : Division by 6 mode
0 1 0 0 0 : Division by 8 mode
0 1 0 1 0 : Division by 10 mode
0 1 1 0 0 : Division by 12 mode
0 1 1 1 0 : Division by 14 mode
0 0 0 0 0 : Division by 16 mode
b4 b3 b2 b1 b0
MCD4
MCD3
MCD1
MCD2
MCD0 Main clock division select
bit (Note 2, 4)
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: These bits are "010002" (8-division mode) when main clock is stopped or you shift to stop
mode. However, in ring oscillator mode, this register is not set to the division by 8 mode when
XIN-XOUT is stopped by main clock stop bit.
Note 3: Do not attempt to set combinations of values other than those shown in this figure.
Note 4: SFR area of CAN is accessed with no division mode.
WR
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Figure 1.8.3. Clock control related registers (2)
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CM20
CM21
CM22
CM23
(Note 2,3)
(Note 4)
(Note 5)
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: When XIN oscillation stop is detected in CM20="1", this bit becomes "1".
After this, although XIN starts oscillating, this bit does not become "0". When you change to XIN as
system clock after XIN restarts oscillating, write "0" to this bit.
Note 3: When CM20="1" and CM22="1", this bit cannot be written.
Note 4: When detecting oscillation stop, this bit becomes "1". "0" can be written by software.
When "0" is written during XIN oscillation stop, this bit does not becomes "1" although XIN oscillating stops.
Note 5: XIN state is judged by reading this bit several times in oscillation stop interrupt process program.
Oscillation stop detect register (Note 1)
Main clock switching bit
Oscillation stop detect
enable bit
XIN clock monitor flag
Oscillation stop detect
flag
Reserved bit
0: XIN oscillating
1: XIN not oscillating
0: XIN selected
1: Ring oscillator selected
0: Ignored
1: Detect oscillation stop
0: Oscillation stop detect function disabled
1: Oscillation stop detect function enabled
Must set to "0"
Symbol Address When reset
CM2 000D16 0016
RW
FunctionBit name
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
0000
Figure 1.8.4. Clock control related register (3)
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CNT0
CNT1
CNT2
CNT3
CST
(Note)
Note : Write to these bits during the count stop.
Count source prescale register
Division rate select bit
Operation enable bit 0: Divider stops
1: Divider starts
0 0 0 0: No-division
0 0 0 1: Division by 2
0 0 1 0: Division by 4
0 0 1 1: Division by 6
•
•
•
1 1 0 1: Division by 26
1 1 1 0: Division by 28
1 1 1 1: Division by 30
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Symbol Address When reset
TCSPR 035F
16
0XXX 0000
2
RW
b
3
b
2
b
1
b
0
FunctionBit name
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.8.5. Clock control related register (4)
Reserved bit Must set to "0"
PLV00 (Note 2)
Function
Note 1: When rewriting this register, set bit 3 of protect regiser (address 000A
16
) to "1".
Note 2: Set this bit to "0" before shifting to stop mode.
VDC control register for PLL (Note 1)
PLL VDC enable bit 0 : Cut off power to PLL
1 : Power to PLL
Bit name
Bit
symbol
Symbol Address When reset
PLV 0017
16
XXXXXX01
2
RW
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
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Clock Generating Circuit
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(1) Main clock
The main clock is a clock source for CPU operation and peripheral I/O. Figure 1.8.6 shows example of a
main clock. When a reset, the clock oscillates and after a reset, the clock is divided by 8 to the BCLK
(CPU operating clock).
(a) Main clock On/Off function
• Main clock (XIN-XOUT) stop bit of system control register 0 (bit 5 at address 000616)
0: Main clock On
1: Main clock Off
Also, the clock is stopped by shifting to the stop mode.
• All clock stop control bit of system control register 1 (bit 0 at address 000716)
0: Clock on
1: All clocks off (stop mode)
Figure 1.8.6. Examples of main clock
Microcomputer
(Built-in feedback resistance)
X
IN XOUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistance)
X
IN XOUT
R
d
CIN COUT
(Note)
Note: Insert a damping resistance if required. The resistance will vary depending on
the oscillator setting. Use the value recommended by the maker of the oscillator.
Insert a feedback resistance between XIN and XOUT when an oscillation
manufacture required.
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(2) Sub clock
The sub clock is a clock source for CPU operation and count source for timer A and B. Figure 1.8.7
shows example of sub clock. When the sub clock is used, set ports P86 and P87 to no pull-up resistance
with the input port. No sub clock is generated during and after a reset.
(a) Sub clock On/Off function
When you want to use sub clock, set the following bit and sub clock enabled.
• Port Xc select bit of system control register 0 (bit 4 at address 000616)
0: I/O port (sub clock off)
1: XIN-XOUT generation (sub-clock on)
Also, shifting to the stop mode stops the clock.
• All clock stop control bit of system control register 1 (bit 0 at address 000716)
0: Clock On
1: All clock stop (stop mode)
Clock Generating Circuit
Figure 1.8.7. Examples of sub clock
Microcomputer
(Built-in feedback resistance)
X
CIN XCOUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistance if required. The resistance will vary depending on
the oscillator and the oscillation drive capacity setting. Use the value
recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Insert a feedback resistance between X
CIN
and X
COUT
when an oscillation
manufacture required.
Microcomputer
(Built-in feedback resistance)
X
CIN XCOUT
(Note)
CCIN CCOUT
RCd
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(3) Oscillation stop detect function (OSD function)
This function monitor the main clock (XIN pin). When main clock is stopped, internal ring oscillator starts
ocsillation and replace the main clock. Then oscillation stop detect interrupt process is operated.
When frequency of main clock is less or equal than 2MHz, this function does not work.
(a) OSD function enable/disable
• OSD enable bit of oscillation stop detect register (bit 0 at address 000D16)
0: OSD function disabled
1: OSD function enabled
Set OSD enable bit (bit 0) of oscillation stop detect register to "0" to disable OSD function before
setting stop mode. Stop mode is canceled before setting this bit to "1".
(b) Operation when oscillation stop detects
1) When XIN oscillation stops, a built in ring oscillation starts as a main clock automatically.
2) OSD interrupt request is generated, jump to an address FFFFF016 to FFFFF316 allocated fixed
vector table (watchdog timer interrupt vector) and execute program of jump address.
3) OSD interrupt shares vector table with watchdog timer interrupt. When using both OSD and watch-
dog timer interrupts, read and judge OSD flag in interrupt process routine.
OSD flag of oscillation stop detect register (bit 2 at address 000D16)
1: Oscillation stop detects
4) XIN does not become main clock although XIN On after oscillation stop detects. When you want XIN
to be main clock, execute a process shown in Figure 1.8.8.
XIN switching
XIN is ON
Confirm XIN is ON
Write "0" to OSD flag
Write "0" to main clock
select bit
End
OFF
ON
Confirm XIN is ON several times
Oscillation stop detect register (address 000D16)
bit 3: XIN clock monitor flag
0: XIN ON
1: XIN OFF
bit2: Oscillation stop detect flag
bit 1: Main clock select bit
0: XIN selected
1: Ring oscillator selected
Figure 1.8.8. Main clock switching sequence
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CPU clock (BCLK)
Main clock, sub clock or clock from ring oscillator can be selected as clock source for BCLK.
System clock select bit of system clock control register (bit 7 at address 000616)
0: Main clock is selected (XIN-XOUT)
1: Sub clock is selected (XCIN-XCOUT)
Main clock select bit of oscillation stop detect register (bit 1 at address 000D16)
0: Main clock is selected (XIN-XOUT)
1: Clock from ring oscillator is selected
Table 1.8.3. BCLK source and setting bit
BCLK source System clock select bit Main clock select bit
(Bit 7 of address 000616) (Bit 1 of address 000D16)
Main clock (XIN-XOUT) 0 0
Sub clock (XCIN-XCOUT) 1 0
Ring oscillator 0 1
When main clock or ring oscillator clock is selected as clock source for BCLK, the BCLK is the clock
derived by dividing the main clock or ring oscillator clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16.
Main clock divide rate select bit of main clock division register (bit 0 to 4 at address 000C16)
The BCLK is derived by dividing the main clock (XIN-XOUT) by 8 after a reset. (Main clock division register
= "XXX010002")
When main clock is stopped under changing to stop mode or selecting XIN-XOUT (main clock select bit =
"0"), the main clock division register is set to the division by 8 ("XXX010002").
When ring oscillator clock is selected as clock source for BCLK, although main clock is stoped, the
contents of main clock division register is maintained.
Peripheral function clock
Main clock, sub clock, PLL clock or ring oscillator clock can be selected as clock source for peripheral
function.
(1) f1, f8, f2n
The clock is derived from the main clock or by dividing it by 1, 8 or 2n (n=1 to 15). It is used for the
timer A and timer B counts and serial I/O and UART operation clock.
The f2n division rate is set by the count source prescaler register. Figure 1.8.5 shows the count source
prescaler register.
(2) fAD
This clock has the same frequency as the main clock or ring oscillator clock and is used for A-D
conversion.
(3) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(4) fPLL
This clock is 80 MHz generated by PLL synthesizer. It is used for the intelligent I/O group 3.
Wait Mode
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Clock Output
You can output clock from the P53 pin.
• BCLK output function select bit of processor mode register 0 (bit 7 at address 000416)
• ALE select bits of processor mode register 1 (bit 4 and 5 at address 000516)
• Clock output function select bits of system clock select register (bits 1 and 0 at address 000616)
Table 1.8.4 shows clock output setting (single chip mode) and Table 1.8.5 shows clock output setting
(memory expansion/microprocessor mode).
Table 1.8.4. Clock output setting (single chip mode)
PM07 CM01 CM00 PM14
P53/BCLK/ALE/CLKOUT
pin function
1
1
1
0
0
1
1
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
PM15 P53 I/O port
fc output
f8 output
f32 output
BCLK output function
select bit Clock output function
select bit ALE pin select bit
0
1
0
1
Note :Must use P57 as input port.
(Note)
(Note)
(Note)
Ignored
Table 1.8.5. Clock output setting (memory expansion/microprocessor mode)
0
1
1
1
0
0
0
1
"0, 0"
"1, 0"
"1, 1"
BCLK output
"L" output (not P53)
fc output
f8 output
0
0
1
0
11
001
f32 output
ALE output
1
0
PM07 CM01 CM00 PM14
P53/BCLK/ALE/CLKOUT
pin function
Ignored
PM15
BCLK output function
select bit Clock output function
select bit ALE pin select bit
Note: The processor mode register 0 and 1 are protected from false write by program run away.
Set bit 1 to "1" at protect register (address 000A16) and release protect before rewriting processor
mode register 0 and 1.
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Power Saving
Power Saving
There are three power save modes. Figure 1.8.9 shows the clock transition between each of the three
modes, (1), (2), and (3).
• Normal operating mode
CPU and peripheral function operate when supplying clock. Power dissipation is reduced by making
BCLK slow.
• Wait mode
BCLK is stopped. Peripheral function clock is stopped as desired. Main clock and sub clock isn't
stopped. Power dissipation is reduced than normal operating mode.
• Stop mode (Note 1)
Main clock, sub clock and PLL synthesizer are stopped. CPU and peripheral function clock are
stopped. Power dissipation is the most few in this mode.
Note :When using stop mode, oscillation stop detect function must be canceled.
(1) Normal operating mode
High-speed mode
Main clock one cycle forms CPU operating clock.
Medium-speed mode
The main clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms CPU operating clock.
Low-speed mode
Subclock (fc) forms CPU operating clock.
Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. Only the peripheral
functions for which the subclock was selected as the count source continue to run.
Ring oscillator mode
The ring oscillator clock divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 forms CPU operating clock.
Ring oscillator low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode.
When switching BCLK from ring oscillator to main clock, switch clock after main clock oscillates fully
stable. After setting divided by 8 (main clock division register =0816) in ring oscilltor mode, switching
to the middle mode (divided by 8) is recommended.
(2) Wait mode
In wait mode, BCLK is stopped and CPU and watchdog timer operated by BCLK are halted. The main
clock, subclock and ring oscillator clock continue to run.
(a) Shifting to wait mode
Execute WAIT instruction.
(b) Peripheral function clock stop function
The f1, f8 and f2n being supplied to the internal peripheral functions stops. The internal peripheral
functions operated by the clock stop.
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Power Saving
WAIT peripheral function clock stop bit of system clock control register 0 (bit 2 at address 000616)
0: Do not stop f1, f8 and f2n in wait mode and do not stop supplying clock to PLL circuit
1: Stop f1, f8 and f2n in wait mode and stop supplying clock to PLL circuit
(c) The status of the ports in wait mode
Table 1.8.6 shows the status of the ports in wait mode.
(d) Exit from wait mode
Wait mode is cancelled by a hardware reset or interrupt. If a peripheral function interrupt is used to
cancel wait mode, set the following registers.
Interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address
009F16) :RLVL0 to RLVL2
Set the same level as the flag register (FLG) processor interrupt level (IPL).
Interrupt priority set bits of interrupt control register (bits 0 to 2)
Set to a priority level above the level set by RLVL0 to RLVL2 bits
Interrupt enable flag of FLG register
I = 1
When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was oper-
ating when the WAIT command was executed as BCLK from the interrupt routine.
Table 1.8.6. Port status during wait mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3, Retains status before wait mode
________
BHE
_____ ______ ________ _________ ______ _________ ________
RD, WR, WRL, WRH, DW, CASL, CASH “H” (Note)
________
RAS “H” (Note)
__________
HLDA,BCLK “H”
ALE “L”
Port Retains status before wait mode
CLKOUT When fC selected Does not stop
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is
“0”. When the WAIT peripheral function clock stop bit is “1”, the
status immediately prior to entering wait mode is maint ained.
________ ________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
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Power Saving
(3) Stop mode
All oscillation, main clock, subclock, and PLL synthesizer stop in this mode. Because the oscillation of
BCLK and peripheral clock stops in stop mode, peripheral functions such as the A-D converter, timer A
and B, serial I/O, intelligent I/O and watchdog timer do not function.
The content of the internal RAM is retained provided that VCC remains above 2.5V.
When changing to stop mode, the main clock division register (000C16) is set to “XXX010002” (division by
8 mode).
(a) Changing to stop mode
All clock stop control bit of system clock control register 1 (bit 0 at address 000716)
0: Clock ON
1: All clocks off (stop mode)
Before changing to stop mode, set bit 7 of PLL control register 0 (address 037616) to "0" to stop PLL.
Also, set bit 0 of VDC control register for PLL (address 001716) to "1" to turn PLL circuit power off.
(b) The status of the ports in stop mode
Table 1.8.7 shows the status of the ports in stop mode.
(c) Exit from stop mode
Stop mode is cancelled by a hardware reset or interrupt. If a peripheral function interrupt is used to
cancel stop mode, set the following registers.
• Interrupt priority set bits for exiting a stop/wait state of exit priority register (bits 0 to 2 at address 009F 16) :RLVL0 to RLVL2
Set the same level as the flag register (FLG) processor interrupt level (IPL).
• Interrupt priority set bits of interrupt control register (bits 0 to 2)
Set to a priority level above the level set by RLVL0 to RLVL2 bits
• Interrupt enable flag of FLG register
I = 1
When exiting from stop mode using peripheral interrupt request, CPU operates the following BCLK
and the relevant interrupt routine is executed.
• When subclock was set as BCLK before changing to stop mode, subclock is set to BCLK after
cancelled stop mode
• When main clock was set as BCLK before changing to stop mode, the main clock division by 8 is set
to BCLK after cancelled stop mode.
Table 1.8.7. Port status during stop mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______ _______
Address bus, data bus, CS0 to CS3, BHE Retains status before stop mode
_____ ______ ________ _________ ______ _________ ________
RD, WR, WRL, WRH, DW, CASL, CASH “H” (Note)
________
RAS “H” (Note)
__________
HLDA, BCLK “H”
ALE “H”
Port Retains status before stop mode
CLKOUT When fc selected “H”
When f8, f32 selected Retains status before stop mode
________ ________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
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Power Saving
Reset
Middle-speed mode
(divided by 8 mode)
High-speed /
middle-speed mode
Low-speed/ low power
dissipation mode
Note 1
Note 1, 5 Note 2, 4
Stop mode
Detect
oscillation stop
Stop mode
Wait mode
Note 1
CM10="1"
CM10="1"
All oscillation is stopped
All oscillation is stopped
Interrupt
Interrupt
Interrupt
X
IN
oscillation is stopped
interrupt
WAIT instruction
WAIT instruction
WAIT instruction
interrupt
interrupt
Normal operation mode
Note 1 :Switch clocks after the main clock oscillation is fully stabled.
Note 2 :Switch clocks after oscillation of sub clock is fully stable.
Note 3 :The main clock division register is set to the division by 8 mode (MCD="08
16
").
Note 4 :When changing to low power dissipation mode, the main clock division register is set to
the division by 8 mode (MCD="08
16
").
Note 5 :Low power dissipation mode can not be changed to high-speed / middle-speed mode.
Note 6 :Other oscillation mode cannot be changed to low power dissipation mode.
Note 3
Note 6
Ring oscillator / ring oscillator
low power dissipation mode
CPU operation
is stopped
Wait mode
Wait mode
Figure 1.8.9. Clock transition
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BCLK :f(XIN)/8
CM07=“0” MCD=“0816”
Main clock is oscillating
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: Set to divided by 8 mode (MCD is set to "0816").
Main clock is oscillating
Sub clock is stopped
CM04=“1”
MCD=“XX16”
Note 1, 3
CM04=“0”
BCLK :f(XIN)
/division rate
CM07=“0” MCD=“XX16”
Note 3
BCLK :f(XIN)
CM07=“0” MCD=“1216”
High-speed mode
Middle-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
BCLK :f(XIN)
/division rate
CM07=“0” MCD=“XX16”
Note 3
BCLK :f(XIN)
CM07=“0” MCD=“1216”
High-speed mode
Middle-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
Middle-speed mode (divided-by-8 mode)
Transition of normal mode
CM04=“1”
CM05=“0”
Note 4
BCLK :f(XCIN)
CM07=“1”
Low-speed mode
BCLK :f(XCIN)
CM07=“1”
Main clock is oscillating
Sub clock is oscillating
MCD=“XX16”
Note 1, 3
CM07=“0”
Note 1
MCD=“XX16”
Note 3
CM07=“1”
Note 2
CM07=“0”
Note 1
MCD=“XX16”
Note 3
CM04=“0”
Low power
dissipation mode
CM05=“1”
Please change according to a direction of an arrow.
CM07=“1”
Note 2
CM05=“1”
High-speed/middle-speed mode
Low-speed/low power dissipation mode
Main clock is stopped
Sub clock is oscillating
CM05=“0”
(CM04="1")
Ring oscillator mode
BCLK: Ring oscillator clock/division rate
CM21="1"
CM05="1"
Ring oscillator is selected
Main clock is oscillating
Sub clock is oscillating (stopped)
Ring oscillator low power
dissipation mode
CM05=“1”
CM04="0"
Ring oscillator/ring oscillator low power dissipation mode
Ring oscillator is selected
Main clock is stopped
Sub clock is stopped
BCLK: Ring oscillator clock/division rate
CM21="1"
CM05="0"
CM21=“1”
Note 1
CM21=“0”
Note 1
Figure 1.8.10. Clock transition
Power Saving
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Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.8.11 shows the protect register. The following registers are
protected by the protect register.
(1) Registers protected by PRC0 (bit 0)
• System clock control registers 0 and 1 (addresses 000616 and 000716)
• Main clock division register (address 000C16)
• Oscillation stop detect register (address 000D16)
• PLL control register 0 (address 037616)
(2) Registers protected by PRC1 (bit 1)
• Processor mode registers 0 and 1 (addresses 000416 and 000516)
• Three-phase PWM control registers 0 and 1 (addresses 030816 and 030916)
(3) Registers protected by PRC2 (bit 2)
• Port P9 direction register (address 03C716)
• Function select register A3 (address 03B516)
(4) Registers protected by PRC3 (bit 3)
• VDC control register for PLL (address 001716)
• VDC control register 0 (address 001F16)
If, after “1” (write-enabled) has been written to the PRC2, a value is written to any address, the bit automati-
cally reverts to “0” (write-inhibited). Change port P9 input/output and function select register A3 immedi-
ately after setting "1" to PRC2. Interrupt and DMA transfer should not be inserted between instructions.
However, the PRC0, PRC1 and PRC3 do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
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Protect register
Symbol Address When reset
PRCR 000A
16
XXXX0000
2
Bit name
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
PRC1
PRC0
PRC2
Protect bit 1
Function
Protect bit 0
Protect bit 2
(Note 1)
WR
Nothing is assigned.
When write, set “0”. When read, their contents are indeterminate.
Note 1: Writing a value to an address after “1” is written to this bit returns the bit
to “0”. Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Note 2: User cannot use. Writing to VDC control registers 0 and 1 (addresses
001F16, 001B16) is enabled so that a careful handling is required.
A
A
A
A
A
A
A
A
Enables writing to processor mode registers 0 and
1 (addresses 0004
16
and 0005
16
) and three-
phase PWM control register 0 and 1 (addresses
0308
16
and 0309
16
)
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock control registers 0
and 1 (addresses 0006
16
and 0007
16
), main clock
division register (address 000C
16
), oscillation stop
detect register (address 000D
16
) and PLL control
register 0 (address 0376
16
)
0 : Write-inhibited
1 : Write-enabled
Enables writing to port P9 direction register (
address 03C7
16
) and function select register A3
(address 03B5
16
)
0 : Write-inhibited
1 : Write-enabled
Protect bit 3
Enables writing to VDC control register for PLL (
address 0017
16
), VDC control register 0 and 1 (
addresses 001F
16
and 001B
16
)
0 : Write-inhibited
1 : Write-enabled
PRC3
(Note 2)
Figure 1.8.11. Protect register
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Interrupts
83
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
BRK2 instruction
INT instruction
Software
Hardware
Interrupt
Reset
_______
NMI
Watchdog timer
Ocsillation stop detection
Single step
Address matched
Special
Peripheral I/O*1
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer
system. High-speed interrupt can be used as highest priority in peripheral I/O interrupts.
Interrupt Outline
Types of Interrupts
• Maskable interrupt : An interrupt which can be disabled by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be disabled by the interrupt enable flag (I flag) or
whose interrupt priority cannot be changed by priority level.
Figure 1.9.1 lists the types of interrupts.
Software Interrupts
Software interrupts are generated by some instruction that generates an interrupt request when ex-
ecuted. Software interrupts are nonmaskable interrupts.
(1) Undefined-instruction interrupt
This interrupt occurs when the UND instruction is executed.
(2) Overflow interrupt
This interrupt occurs if the INTO instruction is executed when the O flag is 1.
The following lists the instructions that cause the O flag to change:
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA,
SUB, SUBX
(3) BRK interrupt
This interrupt occurs when the BRK instruction is executed.
(4) BRK2 interrupt
This interrupt occurs when the BRK2 instruction is executed. This interrupt is used exclusively for
debugger purposes. You normally do not need to use this interrupt.
Figure 1.9.1. Classification of interrupts
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(5) INT instruction interrupt
This interrupt occurs when the INT instruction is executed after specifying a software interrupt number
from 0 to 63. Note that software interrupt numbers 7 to 54 and 57 are assigned to peripheral I/O
interrupts. This means that by executing the INT instruction, you can execute the same interrupt
routine as used in peripheral I/O interrupts.
The stack pointer used in INT instruction interrupt varies depending on the software interrupt number.
For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The
previous U flag before the interrupt occurred is restored when control returns from the interrupt rou-
tine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur.
However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose ISP.
Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software
interrupt number 32 to 54 and 57.
Hardware Interrupts
There are Two types of hardware Interrupts; special interrupts and Peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
• Reset ____________
A reset occurs when the RESET pin is pulled low.
______
• NMI interrupt ______
This interrupt occurs when the NMI pin is pulled low.
• Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
• Ocsillation stop detect interrupt
This interrupt is caused by the ocsillation stop detect function.
It occurs when detecting the XIN ocsillation is stopped.
• Single-step interrupt
This interrupt is used exclusively for debugger purposes. These interrupts normally do not need to use
this interrupt. A single-step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is
generated each time an instruction is executed.
• Address-match interrupt
This interrupt occurs when the program's execution address matches the contents of the address
match register while the address match interrupt enable bit is set (= 1).
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
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(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral
functions are dependent on classes of products, so the interrupt factors too are dependent on classes
of products. The interrupt vector table is the same as the one for software interrupt numbers 7 through
54 and 57 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• UART related interrupt (UART0 to 4)
- UART transmission/NACK interrupt
- UART reception/ACK interrupt
- Bus collision detection, start/stop condition detection interrupts
This is an interrupt that the serial I/O bus collision detection generates. When I2C mode is selected,
start, stop condition interrupt is selected.
• DMA0 through DMA3 interrupts
• Key-input interrupt ___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt (AD0, 1)
• Timer A interrupt (TA0 to 4)
• Timer B interrupt (TB0 to 5)
_____ _______ ________
• INT interrupt (INT0 to INT5 )
_____ _____
An INT interrupt selects an edge sense or a level sense. In edge sense, an INT interrupt occurs if
_____ _____
either a rising edge or a falling edge is input to the INT pin. In level sense, an INT interrupt occurs if
_____
either a "H" level or a "L" level is input to the INT pin.
• Intelligent I/O interrupt
• CAN interrupt
High-speed interrupts
High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3
cycles.
When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to
the save flag register (SVF) and save PC register (SVP) and the program is executed from the address
shown in the vector register (VCT).
Execute an FREIT instruction to return from the high-speed interrupt routine.
High-speed interrupts can be set by setting “1” in the high-speed interrupt specification bit allocated to bit
3 of the exit priority register. Setting “1” in the high-speed interrupt specification bit makes the interrupt set
to level 7 in the interrupt control register a high-speed interrupt.
You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set
multiple interrupts as level 7 interrupts. When using high speed interrupt, DMA II cannot be used.
The interrupt vector for a high-speed interrupt must be set in the vector register (VCT).
When using a high-speed interrupt, you can use a maximum of two DMAC channels.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.
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Interrupts
86
AAAAAAAA
AAAAAAAA
Mid address
AAAAAAAA
AAAAAAAA
Low address
AAAAAAAA
AAAAAAAA
High address
AAAAAAAA
AAAAAAAA
0 0 16
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.9.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table, in which addresses are fixed, and
relocatable vector table, in which addresses can be varied by the setting.
Figure 1.9.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFFDC16 to FFFFFF16. Each vector comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.9.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.9.1. Interrupt factors (fixed interrupt vector addresses)
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFFDC16 to FFFFDF16 Interrupt on UND instruction
Overflow FFFFE016 to FFFFE316 Interrupt on INTO instruction
BRK instruction FFFFE416 to FFFFE716 If contents of FFFFE716 is filled with FF16, program
execution starts from the address shown by the vector in
the relocatable vector table
Address match FFFFE816 to FFFFEB16 There is an address-matching interrupt enable bit
Watchdog timer FFFFF016 to FFFFF3 16 Share it with watchdog timer and oscillation stop detect
interrupt
_______
NMI FFFFF816 to FFFFFB16 _______
External interrupt by input to NMI pin
Reset FFFFFC16 to FFFFFF16
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• Vector table dedicated for emulator
Table 1.9.2 shows interrupt vector address, which is vector table register dedicated for emulator (ad-
dress 00002016 to 00002216). These instructions are not effected with interrupt enable flag (I flag)
(non maskable interrupt).
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. Do not access the interrupt vector table register dedicated for emulator (address 00002016 to
00002216).
Table 1.9.2. Interrupt vector table register for emulator
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
BRK2 instruction Interrupt vector table register for emulator Interrupt for debugger
Single step 00002016 to 00002216
• Relocatable vector tables
The addresses in the relocatable vector table can be modified, according to the user’s settings. Indi-
cate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the
address the INTB indicates becomes the area for the relocatable vector tables. One vector table
comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.9.3
shows the interrupts assigned to the relocatable vector tables and addresses of vector tables.
Set an even address to the start address of vector table setting in INTB so that operating efficiency is
increased.
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Table 1.9.3. Interrupt causes (variable interrupt vector addresses) (1/2)
Softwear interrupt number Vector table address Interrutp source
Address(L)to address(H) (Note 1)
Softwear interrupt number 0
(Note 2)
+0 to +3 (000016 to 000316) BRK instruction
Softwear interrupt number 7 +28 to +31 (001C16 to 001F16) A-D channel 1
Softwear interrupt number 8 +32 to +35 (002016 to 002316) DMA0
Softwear interrupt number 9 +36 to +39 (002416 to 002716) DMA1
Softwear interrupt number 10 +40 to +43 (002816 to 002B16) DMA2
Softwear interrupt number 11 +44 to +47 (002C16 to 002F16) DMA3
Softwear interrupt number 12 +48 to +51 (003016 to 003316) Timer A0
Softwear interrupt number 13 +52 to +55 (003416 to 003716) Timer A1
Softwear interrupt number 14 +56 to +59 (003816 to 003B16) Timer A2
Softwear interrupt number 15 +60 to +63 (003C16 to 003F16) Timer A3
Softwear interrupt number 16 +64 to +67 (004016 to 004316) Timer A4
Softwear interrupt number 17 +68 to +71 (004416 to 004716) UART0 transmit/NACK (Note 3)
Softwear interrupt number 18 +72 to +75 (004816 to 004B16) UART0 receive/ACK (Note 3)
Softwear interrupt number 19 +76 to +79 (004C16 to 004F16) UART1 transmit/NACK (Note 3)
Softwear interrupt number 20 +80 to +83 (005016 to 005316) UART1 receive/ACK (Note 3)
Softwear interrupt number 21 +84 to +87 (005416 to 005716) Timer B0
Softwear interrupt number 22 +88 to +91 (005816 to 005B16) Timer B1
Softwear interrupt number 23 +92 to +95 (005C16 to 005F16) Timer B2
Softwear interrupt number 24 +96 to +99 (006016 to 006316) Timer B3
Softwear interrupt number 25 +100 to +103 (006416 to 006716) Timer B4
Softwear interrupt number 26 +104 to +107 (006816 to 006B16) INT5
Softwear interrupt number 27 +108 to +111 (006C16 to 006F16) INT4
Softwear interrupt number 28 +112 to +115 (007016 to 007316) INT3
Softwear interrupt number 29 +116 to +119 (007416 to 007716) INT2
Softwear interrupt number 30 +120 to +123 (007816 to 007B16) INT1
Softwear interrupt number 31 +124 to +127 (007C16 to 007F16) INT0
Softwear interrupt number 32 +128 to +131 (008016 to 008316) Timer B5
Softwear interrupt number 33 +132 to +135 (008416 to 008716) UART2 transmit/NACK (Note 3)
Softwear interrupt number 34 +136 to +139 (008816 to 008B16) UART2 receive/ACK (Note 3)
Softwear interrupt number 35 +140 to +143 (008C16 to 008F16) UART3 transmit/NACK (Note 3)
Softwear interrupt number 36 +144 to +147 (009016 to 009316) UART3 receive/ACK (Note 3)
Softwear interrupt number 37 +148 to +151 (009416 to 009716) UART4 transmit/NACK (Note 3)
Softwear interrupt number 38 +152 to +155 (009816 to 009B16) UART4 receive/ACK (Note 3)
Softwear interrupt number 39 +156 to +159 (009C16 to 009F16) Bus collision detection, start/stop condition
detection (UART2)(Note 3)
Softwear interrupt number 40 +160 to +163 (00A016 to 00A316) Bus collision detection, start/stop condition
detection (UART3/UART0)(Note 3)
Softwear interrupt number 41 +164 to +167 (00A416 to 00A716) Bus collision detection, start/stop condition
detection (UART4/UART1)(Note 3)
Softwear interrupt number 42 +168 to +171 (00A816 to 00AB16) A-D channel 0
Softwear interrupt number 43 +172 to +175 (00AC16 to 00AF16) Key input interrupt
Softwear interrupt number 44 +176 to +179 (00B016 to 00B316) Intelligent I/O interrupt 0
Softwear interrupt number 45 +180 to +183 (00B416 to 00B716) Intelligent I/O interrupt 1
Softwear interrupt number 46 +184 to +187 (00B816 to 00BB16) Intelligent I/O interrupt 2
Softwear interrupt number 47 +188 to +191 (00BC16 to 00BF16) Intelligent I/O interrupt 3
Softwear interrupt number 48 +192 to +195 (00C016 to 00C316) Intelligent I/O interrupt 4
Softwear interrupt number 49 +196 to +199 (00C416 to 00C716) Intelligent I/O interrupt 5
Softwear interrupt number 50 +200 to +203 (00C816 to 00CB16) Intelligent I/O interrupt 6
Softwear interrupt number 51 +204 to +207 (00CC16 to 00CF16) Intelligent I/O interrupt 7
Softwear interrupt number 52 +208 to +211 (00D016 to 00D316) Intelligent I/O interrupt 8
Softwear interrupt number 53 +212 to +215 (00D416 to 00D716) Intelligent I/O interrupt 9/CAN interrupt 0
Softwear interrupt number 54 +216 to +219 (00D816 to 00DB16) Intelligent I/O interrupt 10/CAN interrupt 1
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Table 1.9.3. Interrupt causes (variable interrupt vector addresses) (2/2)
Softwear interrupt number Vector table address Interrutp source
Address(L)to address(H) (Note 1)
Softwear interrupt number 55 +220 to +223 (00DC16 to 00DF16) Softwea interrupt
Softwear interrupt number 56 +224 to +227 (00E016 to 00E316) Softwea interrupt
Softwear interrupt number 57 +228 to +231 (00E416 to 00E716) Intelligent I/O interrupt 11/CAN interrupt 2
Softwear interrupt number 58
(Note 2)
+232 to +235 (00E816 to 00EB16) Softwea interrupt
to to
Softwear interrupt number 63 +252 to +255 (00FC16 to 00FF16)
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: Cannot be masked by I flag.
Note 3: When IIC mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. The fault error
____
interrupt is selected when SS pin is selected.
Interrupt request reception
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag) = 1
• Interrupt request bit = 1
• Interrupt priority level > Processor interrupt priority level (IPL)
The interrupt enable flag (I flag), the processor interrupt priority level (IPL), interrupt request bit and
interrupt priority level select bit are all independent of each other, so they do not affect any other bit.
There are I flag and IPL in flag register (FLG). This flag and bit are described below.
Interrupt Enable Flag (I Flag) and processor Interrupt Priority Level (IPL)
I flag is used to disable/enable maskable interrupts. When this flag is set (= 1), all maskable interrupts
are enabled; when the flag is cleared to 0, they are disabled. This flag is automatically cleared to 0
after a reset.
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
Table 1.9.4 shows interrupt enable levels in relation to the processor interrupt priority level (IPL).
Table 1.9.4. IPL and Interrupt Enable Levels
Processor interrupt priority level (IPL) Enabled interrupt priority levels
IPL2IPL1IPL0
0 0 0 Interrupt levels 1 and above are enabled.
0 0 1 Interrupt levels 2 and above are enabled.
0 1 0 Interrupt levels 3 and above are enabled.
0 1 1 Interrupt levels 4 and above are enabled.
1 0 0 Interrupt levels 5 and above are enabled.
1 0 1 Interrupt levels 6 and above are enabled.
1 1 0 Interrupt levels 7 and above are enabled.
1 1 1 All maskable interrupts are disabled.
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Interrupts
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Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
AA
AA
Bit name FunctionBit symbol
WR
Symbol Address When reset
TAiIC(i=0 to 4) 006C
16
, 008C
16
, 006E
16
, 008E
16
, 0070
16
XXXXX000
2
TBiIC(i=0 to 5) 0094
16
, 0076
16
, 0096
16
, 0078
16
, 0098
16
, 0069
16
XXXXX000
2
SiTIC(i=0 to 4) 0090
16
, 0092
16
, 0089
16
, 008B
16
, 008D
16
XXXXX000
2
SiRIC(i=0 to 4) 0072
16
, 0074
16
, 006B
16
, 006D
16
, 006F
16
XXXXX000
2
BCNiIC(i=0 to 4) 0071
16
, 0091
16
, 008F
16
, 0071
16(Note 1)
, 0091
16(Note 2)
XXXXX000
2
DMiIC(i=0 to 3) 0068
16
, 0088
16
, 006A
16
, 008A
16
XXXXX000
2
ADiIC(i=0,1) 0073
16
, 0086
16
XXXXX000
2
KUPIC (i=0) 0093
16
XXXXX000
2
IIOiIC(i=0 to 5) 0075
16
, 0095
16
, 0077
16
, 0097
16
, 0079
16
, 0099
16
XXXXX000
2
IIOiIC(i=6 to 11) 007B
16
, 009B
16
, 007D
16
, 009D
16
, 007F
16
, 0081
16
XXXXX000
2
CANiIC(i=0 to 2) 009D
16
, 007F
16
, 0081
16
XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
(Note 3)
Note 1: UART0 bus collision and start/stop condition detection interrupt control register is shared with UART3.
Note 2: UART1 bus collision and start/stop condition detection interrupt control register is shared with UART4.
Note 3: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Figure 1.9.3. Interrupt control register (1)
Interrupt control registers and Exit priority register
Peripheral I/O interrupts have their own interrupt control registers. Figure 1.9.3 and 1.9.4 show the
interrupt control registers and figure 1.9.5 shows exit priority register.
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Interrupts
91
Symbol Address When reset
INTiIC(i=0 to 2) 009E16, 007E16, 009C16 XX00 X0002
INTiIC(i=3 to 5)(*1) 007C16, 009A16, 007A16 XX00 X0002
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
ILVL0
IR
POL
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Level sense/edge
sense select bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge or L level
1 : Selects rising edge or H level
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: When related bit of external interrupt cause select register (address 031F16) are used for both edge,
select the falling edge (=0).
Note 3: When level sense is selected, set related bit of external interrupt cause select register (address 031F16) to
one edge.
(Note 1)
Interrupt control register
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : Edge sense
1 : Level sense
LVS
(Note 2)
(Note 3)
*1 When using 16-bit data bus width in microprocessor mode or memory expansion mode, INT3 to INT5 are used
for data bus. In this case, set the interrupt disabled to INT3IC, INT4IC and INT5IC.
Figure 1.9.4. Interrupt control register (2)
Bit 0 to 2: Interrupt Priority Level Select Bits (ILVL0 to ILVL2)
Interrupt priority levels are set by ILVL0 to ILVL2 bits. When an interrupt request is generated, the
interrupt priority level of this interrupt is compared with IPL. This interrupt is enabled only when its
interrupt priority level is greater than IPL. This means that you can disable any particular interrupt by
setting its interrupt priority level to 0.
Bit 3: Interrupt Request Bit (IR)
This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared (= 0) by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared (= 0) (but never be set to 1) in software.
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Exit priority register
When reset
XX0X00002
Address
009F16
Symbol
RLVL
RW
RLVL0
RLVL1
RLVL2
Interrupt priority set bits
for exiting Stop/Wait
state (Note 1)
FSIT High-speed interrupt
set bit (Note 2)
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 =
high-speed interrupt
DMA II DMA II select bit
(Note 3)
0: Interrupt priority level 7 = normal
interrupt or high-speed interrupt
1: Interrupt priority level 7 =
DMA II transfer
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
Bit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than
that set in the exit priority register.
Set to the same value as the processor interrupt priority level (IPL) set in the flag
register (FLG).
Note 2: The high-speed interrupt can only be specified for interrupts with interrupt priority level
7. Specify interrupt priority level 7 for only one interrupt.
Note 3: Do not set this bit to 0 after once setting it to 1.
When this bit is 1, do not set the high-speed interrupt select bit to 0. (This cannot be
used simultaneously with the high-speed interrupt.)
Transfers by DMAC II are unaffected by the interrupt enable flag (I flag) and processor
interrupt priority level (IPL).
Figure 1.9.5. Exit priority register
Bit 0 to 2: Interrupt priority set bits for exiting Stop/Wait state (RLVL0 to RLVL2)
When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must be enabled and
set to a priority level above the level set by the RLVL0 to RLVL2 bits. Set the RLVL0 to RLVL2 bits to
the same level as the flag register (FLG) IPL.
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Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU,
SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed,
and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 00000016 (address 00000216 when high-speed interrupt). After this, the related interrupt
request bit is "0".
(2) Saves the contents of the flag register (FLG) immediately before the start of interrupt sequence in the
temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the contents of the temporary register (Note) within the CPU in the stack area. Saves in the
flag save register (SVF) in high-speed interrupt.
(5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register
(SVP) in high-speed interrupt.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the occur-
rence of an interrupt to the completion of the instruction under execution at that moment (a) and the time
required for executing the interrupt sequence (b). Figure 1.9.6 shows the interrupt response time.
Figure 1.9.6. Interrupt response time
(a) The period from the occurrence of an interrupt to the completion of the instruction under execution.
(b) The time required for executing the interrupt sequence.
(a) (b)
Time
Instruction
Interrupt response time
Instruction in interrupt
routine
Interrupt sequence
Interrupt request acknowledged
Interrupt request generated
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Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time of
29* cycles.
Time (b) is shown in table 1.9.5.
* It is when the divisor is immediate or register. When the divisor is memory, the following value is
added.
• Normal addressing : 2 + X
• Index addressing : 3 + X
• Indirect addressing : 5 + X + 2Y
• Indirect index addressing : 6 + X + 2Y
X is number of wait of the divisor area. Y is number of wait of the indirect address stored area.
When X and Y are in odd address or in 8 bit bus area, double the value of X and Y.
Table 1.9.5 Interrupt Sequence Execution Time
Note 1: Allocate interrupt vector addresses in even addresses as much as possible.
Note 2: The vector table is fixed to even address.
Note 3: The high-speed interrupt is independent of these conditions.
8 bits data bus
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
16 cycles
19 cycles
19 cycles
21 cycles
16 bits data bus
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
14 cycles
17 cycles
19 cycles
19 cycles
Interrupt vector address
Even address
Odd address (Note 1)
Even address
Odd address (Note 1)
Even address (Note 2)
Even address (Note 2)
Even address
Odd address (Note 1)
Even address (Note 2)
Vector table is internal register
Interrupt
Peripheral I/O
INT instruction
_______
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
BRK instruction (Relocatable vector table)
Single step
BRK2 instruction
BRK instruction (Fixed vector table)
High-speed interrupt (Note 3) 5 cycles
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Value that is set to IPL
7
0
Not changed
Figure 1.9.7. Stack status before and after an interrupt request is acknowledged
Changes of IPL When Interrupt Request Acknowledged
When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 1.9.6 is set to the IPL.
Table 1.9.6 Relationship between Interrupts without Interrupt Priority Levels and IPL
Interrupt sources without interrupt priority levels
_______
Watchdog timer, NMI
Reset
Other
Saving Registers
In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are
saved to the stack area.
The order in which these contents are saved are as follows: First, the FLG register is saved to the stack
area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are
saved. Figure 1.9.7 shows the stack status before an interrupt request is acknowledged and the stack
status after an interrupt request is acknowledged.
In a high-speed interrupt sequence, the contents of the flag register (FLG) are saved to the flag save
register (SVF) and program counter (PC) are saved to PC save register (SVP).
If there are any other registers you want to be saved, save them in software at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP)
by a single instruction.
In high speed interrupt, switch register bank, then register bank 1 is used as high speed interrupt register.
In this case, switch register bank mode for high-speed interrupt routine.
[SP]
Stack pointer
value before
interrupt occurs
Stack status before interrupt request is acknowledged
Address
Stack status after interrupt request is acknowledged
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
LSBMSB
LSB
MSB
Address Stack area Stack area
Flag register
(FLGL)
Program counter
(PCH)
Flag register
(FLGH)
Content of
previous stack
Content of
previous stack
Content of
previous stack
Content of
previous stack
Program counter
(PCL)
Program counter
(PCM)
[SP]
New stack
pointer value
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
0 0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
96
Return from Interrupt Routine
As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register
(FLG) and program counter (PC) that have been saved to the stack area immediately preceding the
interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT in-
struction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter
(PC) that have been saved to the save registers immediately preceding the interrupt sequence are auto-
matically restored.
Then control returns to the routine that was under execution before the interrupt request was acknowl-
edged, and processing is resumed from where control left off.
If there are any registers you saved via software in the interrupt routine, be sure to restore them using an
instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction.
When switching the register bank before executing REIT and FREIT instruction, switched to the register
bank immediately before the interrupt sequence.
Interrupt Priority
If two or more interrupt requests are sampled active at the same time, the interrupt with the highest
priority will be acknowledged.
Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the inter-
rupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level,
the priority between these interrupts are resolved by the priority that is set in hardware.
Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer
interrupt have their priority levels set in hardware. Figure 1.9.8 lists the hardware priority levels of these
interrupts.
Software interrupts are not subjected to interrupt priority. They always cause control to branch to an
interrupt routine whenever the relevant instruction is executed.
Interrupt Resolution Circuit
Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are
sampled active at the same time.
Figure 1.9.9 shows the interrupt resolution circuit.
_______
Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match
Figure 1.9.8. Interrupt priority that is set in hardware
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
97
Timer B2
Timer B0
Timer A0
Timer A1
Timer B1
UART1 reception/ACK
UART0 reception/ACK
Intelligent I/O interrupt 1
A-D0 conversion
UART1 transmission/NACK
UART0 transmission/NACK
Intelligent I/O interrupt 0
Key input interrupt
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
Watchdog timer
Reset
DBC
NMI
Interrupt
request
accepted.
To CPU
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
UART2 reception/ACK
Address match
Timer B4
Timer B3
DMA0
DMA1
DMA2
DMA3
Timer A2
Timer A3
Timer A4
UART2 transmission/NACK
UART3 reception/ACK
UART3 transmission/NACK
UART4 reception/ACK
UART4 transmission/NACK
Bus collision/start, stop
condition/fault error (UART0,3)
Bus collision/start, stop
condition/fault error (UART1,4)
Instruction fetch
Stop/wait return interrupt level
(RLVL)
Interrupt
request
accepted.
To CLK
A-D1 conversion
Bus collision/start, stop
condition(UART2)
Intelligent I/O interrupt 2
Intelligent I/O interrupt 3
Intelligent I/O interrupt 4
Intelligent I/O interrupt 5
Intelligent I/O interrupt 6
Intelligent I/O interrupt 7
Intelligent I/O interrupt 8
Intelligent I/O interrupt 9
/CAN interrupt 0
Intelligent I/O interrupt 10
/CAN interrupt 1
Intelligent I/O interrupt 11
/CAN interrupt 2
INT3
INT5
INT4
INT1
INT2
INT0
Timer B5
Figure 1.9.9. Interrupt resolution circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
98
External interrupt request cause select register
Bit name Function
Bit symbol
WR
Symbol Address When reset
IFSR 031F
16
00
16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
A
AA
AA
A
INT0 interrupt polarity
select bit (Note) 0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
select bit (Note)
INT2 interrupt polarity
select bit (Note)
INT3 interrupt polarity
select bit (Note)
INT4 interrupt polarity
select bit (Note)
INT5 interrupt polarity
select bit (Note) 0 : One edge
1 : Both edges
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
Note :When level sense is selected, set this bit to "0".
When both edges are selected, set the corresponding polarity switching bit of INT interrupt control
register to "0" (falling edge).
0 : UART3 bus collision /start,stop
detect/false error detect
1 : UART0 bus collision /start,stop
detect/false error detect
UART0/3 interrupt
cause select bit
UART1/4 interrupt
cause select bit
IFSR6
IFSR7
AA
AA
A
A
AA
AA
A
A
0 : UART4 bus collision /start,stop
detect/false error detect
1 : UART1 bus collision /start,stop
detect/false error detect
______
INT Interrupts
________ ________
INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control
register select the input signal level and edge at which the interrupt can be set to occur on input signal level
and input signal edge. The polarity bit selects the polarity.
With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling
edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address
031F16) to “1”. When you select both edges, set the polarity switch bit of the corresponding interrupt control
register to the falling edge (“0”).
When you select level sense, set the INTi interrupt polarity switch bit of the interrupt request select register
(address 031F16) to “0”.
Figure 1.9.10 shows the interrupt request select register.
Figure 1.9.10. External interrupt request cause select register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
99
Interrupt control
circuit
Key input interrupt control
register (address 0093
16
)
Key input interrupt
request
P10
7
/KI
3
P10
6
/KI
2
P10
5
/KI
1
P10
4
/KI
0
Port P10
4
-P10
7
pull-up
select bit
Port P10
7
direction
register
Pull-up
transistor
Port P10
7
direction register
Port P10
6
direction
register
Port P10
5
direction
register
Port P10
4
direction
register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03C416).
This pin cannot be used as a normal port input.
Notes: ______ ______ ______
When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI
interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.9.11 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Setting the key input interrupt disable bit (bit 7 at address 03AF16) to “1” disables key input interrupts from
occurring, regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt
disable register, there is no input via the port pin even when the direction register is set to input.
Figure 1.9.11. Block diagram of key input interrupt
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
100
Bit nameBit symbol
Symbol Address When reset
AIER 0009
16
XXXX0000
2
Address match interrupt enable register
Function WR
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Symbol Address When reset
RMAD0 0012
16
to 0010
16
000000
16
RMAD1 0016
16
to 0014
16
000000
16
RMAD2 001A
16
to 0018
16
000000
16
RMAD3 001E
16
to 001C
16
000000
16
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
WR
Address setting register for address match
interrupt
Function Values that can be set
Address match interrupt register i (i = 0, 1)
000000
16
to FFFFFF
16
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0
(b16) b7 b0
(b15) (b8)
b7
(b23)
AA
A
AA
A
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Address match interrupt 2
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER2
Address match interrupt 3
enable bit
AIER3 0 : Interrupt disabled
1 : Interrupt enabled
AA
A
AA
AA
A
A
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Four address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.9.12 shows the address match interrupt-related registers.
Set the start address of an instruction to the address match interrupt register.
Address match interrupt is not generated when address such as the middle of instruction or table data is
set.
Figure 1.9.12. Address match interrupt-related registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
101
Interrupt
request bit
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
Interrupt request A
DQ
R
Interrupt
enable bit A
Write "0" to interrupt
request flag A
Interrupt request B
DQ
R
Interrupt
enable bit B
Write "0" to interrupt
request flag B
Interrupt request n
DQ
R
Interrupt
enable bit n
Write "0" to interrupt
request flag n Interrupt request flag
n=A to L
"0"
"1"
"0"
"1"
"0"
"1"
Interrupt request
latch bit
DQ
R
Cleared when
an Interrupt
request
received
Intelligent I/O and CAN Interrupt
Group 0 to 3 intelligent I/O interrupts and CAN interrupt are assigned to software interrupt numbers 44 to 54
and 57.
As intelligent I/O interrupt request, there are base timer interrupt request signals, time measurement inter-
rupt request signals, waveform generation interrupt request signals and interrupt request signals from vari-
ous communication circuits.
Figure 1.9.13 shows the intelligent I/O interrupts and CAN interrupt block diagram, figure 1.9.14 shows the
interrupt request register and figure 1.9.15 shows interrupt enable register.
Figure 1.9.13. Intelligent I/O and CAN interrupt block diagram
When using the intelligent I/O or CAN interrupt as an starting factor for DMA II, the interrupt latch bit must be
set to "0" in order to enable only the interrupt request factor used by the interrupt enable register.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
102
Function
Interrupt request register
Bit name
Bit
symbol
Address
See below When reset
0000 000X2
Symbol
IIOiIR
RW
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
0 : Interrupt request not present
1 : Interrupt request present
IRF1
IRF2
IRF3
Interrupt request flag 1
Interrupt request flag 2
Interrupt request flag 3
0 : Interrupt request not present
1 : Interrupt request present
0 : Interrupt request not present
1 : Interrupt request presence
IRF4
Interrupt request flag 4 0 : Interrupt request not present
1 : Interrupt request present
IRF5
Interrupt request flag 5 0 : Interrupt request not present
1 : Interrupt request present
IRF6
IRF7
Interrupt request flag 6
Interrupt request flag 7
0 : Interrupt request not present
1 : Interrupt request present
0 : Interrupt request not present
1 : Interrupt request present
Note: "0" can be written.
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Symbol
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
Address
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
bit7
(IRF7) bit6
(IRF6) bit5
(IRF5) bit4
(IRF4) bit3
(IRF3) bit2
(IRF2) bit1
(IRF1)
-
-
-
-
BEAN0
-
-
IE0
IE1
CAN0
CAN1
CAN2
-
-
-
-
BEAN1
-
-
-
IE2
-
-
-
SIO0r
SIO0t
SIO1r
SIO1t
-
-
-
-
-
-
-
-
G0RI
G0TO
G1RI
G1TO
BT1
SIO2r
SIO2t
BT0
BT2
-
-
BT3
-
-
-
PO27
PO32
PO33
PO34
PO35
PO36
PO31
PO30
PO37
PO13
PO14
TM12/PO12
PO10
TM17/PO17
PO21
PO20
PO22
PO23
PO24
PO25
PO26
TM02
TM00/PO00
-
TM03
TM04/PO04
TM05/PO05
TM06
TM07
TM11/PO11
PO15
TM16/PO16
TM01/PO01
Interrupt request register table
BTi
TMij
POij
SIOir/SIOit
GiTO/GiRI
BEANi
IE
CANi
-
: Interrupt request from base timer of intelligent I/O group i
: Interrupt request from time measurement function ch j of intelligent I/O group i
: Interrupt request from waveform generator function ch j of intelligent I/O group i
: Interrupt request from communication function of intelligent I/O group i (r:reception, t:transmission)
: Interrupt request from HDLC data processing function of intelligent I/O group i
(RI:reception input, TO:transmission output)
: Interrupt request from special communication function of intelligent I/O group i (i=0,1)
: Interrupt request from IEBus communication function of intelligent I/O group 2
: Interrupt request from AN communication function (i=0 to 2)
: Nothing is assigned in this bit.
-
-
-
-
-
-
-
-
-
-
-
-
bit0
-
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.9.14. Interrupt request registers
Bit 1 to bit 7: Interrupt request flag (IRF1 to IRF7)
To retain respective interrupt requests and judge interrupt kind occurred in the interrupt process rou-
tine.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
103
Function
Interrupt enable register
Bit name
Bit
symbol
Address
See below When reset
0016
Symbol
IIOiIE
RW
0: Interrupt of corresponding interrupt
request flag (IRF2) disabled
1: Interrupt of corresponding interrupt
request flag (IRF2) enabled
ITE1
IRLT
ITE2
ITE3
Interrupt enable bit 1
Interrupt enable bit 2
Interrupt enable bit 3
0: Interrupt of corresponding interrupt
request flag (IRF1) disabled
1: Interrupt of corresponding interrupt
request flag (IRF1) enabled
0: Interrupt of corresponding interrupt
request flag (IRF3) disabled
1: Interrupt of corresponding interrupt
request flag (IRF3) enabled
ITE4
Interrupt enable bit 4 0: Interrupt of corresponding interrupt
request flag (IRF4) disabled
1: Interrupt of corresponding interrupt
request flag (IRF4) enabled
ITE5
Interrupt enable bit 5 0: Interrupt of corresponding interrupt
request flag (IRF5) disabled
1: Interrupt of corresponding interrupt
request flag (IRF5) enabled
ITE6
ITE7
Interrupt enable bit 6
Interrupt enable bit 7
0: Interrupt of corresponding interrupt
request flag (IRF6) disabled
1: Interrupt of corresponding interrupt
request flag (IRF6) enabled
0: Interrupt of corresponding interrupt
request flag (IRF7) disabled
1: Interrupt of corresponding interrupt
request flag (IRF7) enabled
Symbol
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
Address
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
bit7
(ITE7) bit6
(ITE6) bit5
(ITE5) bit4
(ITE4) bit3
(ITE3) bit2
(ITE2) bit1
(ITE1)
-
-
-
-
BEAN0
-
-
IE0
IE1
CAN0
CAN1
CAN2
-
-
-
-
BEAN1
-
-
-
IE2
-
-
-
SIO0r
SIO0t
SIO1r
SIO1t
-
-
-
-
-
-
-
-
G0RI
G0TO
G1RI
G1TO
BT1
SIO2r
SIO2t
BT0
BT2
-
-
BT3
-
-
-
PO27
PO32
PO33
PO34
PO35
PO36
PO31
PO30
PO37
PO13
PO14
TM12/PO12
PO10
TM17/PO17
PO21
PO20
PO22
PO23
PO24
PO25
PO26
TM02
TM00/PO00
-
TM03
TM04/PO04
TM05/PO05
TM06
TM07
TM11/PO11
PO15
TM16/PO16
TM01/PO01
Interrupt request register table
BTi
TMij
POij
SIOir/SIOit
GiTO/GiRI
BEANi
IE
CANi
-
: Interrupt request from base timer of intelligent I/O group i is enabled
: Interrupt request from time measurement function ch j of intelligent I/O group i is enabled
: Interrupt request from waveform generator function ch j of intelligent I/O group i is enabled
: Interrupt request from communication function of intelligent I/O group i (r:reception, t:transmission) is enabled
: Interrupt request from HDLC data processing function of intelligent I/O group i (RI:reception input,
TO:transmission output) is enabled
: Interrupt request from special communication function of intelligent I/O group i (i=0,1) is enabled
: Interrupt request from IEBus communication function of intelligent I/O group 2 is enabled
: Interrupt request from CAN communication function (i=0 to 2) is enabled
: Nothing is assigned in this bit. (Set "0" to these bits.)
Interrupt request latch bit
0: Interrupt request is not latched(used by DMA II)
1: Interrupt request is latched(used by interrupt)
bit1
(IRLT)
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
IRLT
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.9.15. Interrupt enable registers
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
104
Bit 0: Interrupt request latch bit (IRLT)
An interrupt signal or latched signal of the interrupt signal is selected as an interrupt request signal.
When the latched signal of an interrupt signal is used, this flag must be set to "0" after interrupt request
flag is read in interrupt process routine, . If this flag is not set to "0" and interrupt process is completed,
although interrupt request occurs again, interrupt will not occur.
Bit 1 to bit 7: Interrupt enable bit (ITE 1 to ITE 7)
To enable/disable respective interrupts.
Precautions for Interrupts
(1) Reading addresses 00000016 and 00000216
• When maskable interrupt occurs, CPU reads the interrupt information (the interrupt number and inter-
rupt request level) in the interrupt sequence from address 00000016. When a high-speed interrupt
occurs, CPU reads from address 00000216.
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 00000016 and 00000216 by software does not set request bit to “0”.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt
before setting a value in the stack pointer may cause runaway. Be sure to set a value in the stack
_______
pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the
_______
beginning of a program. Any interrupt including the NMI interrupt is generated immediately after ex-
ecuting the first instruction after reset. Set an even number to the stack pointer. Set an even address
to the stack pointer so that operating efficiency is increased.
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, this interrupt cannot be disabled. Connect it to the Vcc pin via a pull-up
resistor if unused.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input. _______
• A low level signal with more than 1 clock cycle (BCLK) is necessary for NMI pin.
(4) External interrupt
• Edge sense
Either a low level or a high level for at least 250 ns is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either a low level or a high level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
105
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt priority level to level 0
(Disable
INTi
interrupt)
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.9.12 shows the procedure for
______
changing the INT interrupt generate factor.
______
Figure 1.9.16. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
(6) Rewrite interrupt request register
• When writing to "0" to this register, the following instructions must be used.
Instructions : AND, BCLR
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
106
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a
watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer.
Watchdog timer interrupt is selected when bit 6 (CM06) of the system control register 0 (address 000816) is
"0" and reset is selected when CM06 is "1". No value other than "1" can be written in CM06. Once reset is
selected (CM06="1"), watchdog timer interrupt cannot be selected by software.
When XIN is selected for the BCLK, bit 7 (WDC7) of the watchdog timer control register (address 000F16)
selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is
set for division by 2 regardless of WDC7. Therefore, the watchdog timer cycle can be calculated as follows.
However, errors can arise in the watchdog timer cycle due to the prescaler.
When XIN is selected in BCLK
Watchdog timer cycle =
When XCIN is selected in BCLK
Watchdog timer cycle =
For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is
approximately 26.2 ms, and approximately 17.5 ms when BCLK is 30MHz.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). CM06 is initialized only at reset. After reset,
watchdog timer interrupt is selected.
The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these
modes and status, counting starts from the previous value.
In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released. Figure 1.10.1 shows the block diagram
of the watchdog timer. Figure 1.10.2 and 1.10.3 show the watchdog timer-related registers.
"CM06=0"
Watchdog timer
interrupt request
"CM06=1"
Reset
BCLK
Write to the watchdog timer
start register
(address 000E16)
RESET
Watchdog timer
Set to
“7FFF16”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
HOLD
1/2
Prescaler
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
Figure 1.10.1. Block diagram of watchdog timer
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
107
WDC7
Reserved bit
Prescaler select bit
Watchdog timer control register
High-order bit of watchdog timer
0 : Divided by 16
1 : Divided by 128
Must always be set to "0"
Symbol Address When reset
WDC 000F
16
000XXXXX
2
RWBit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Watchdog timer start register
Symbol Address When reset
WDTS 000E
16
Indeterminate
RW
Function
The watchdog timer is initialized and starts counting after a write
instruction to this register. The watchdog timer value is always initialized
to "7FFF16" regardless of the value written.
b7 b0
Figure 1.10.2. Watchdog timer control and start registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
108
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16
0000 X000
2
Bit
name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
3
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM01
CM02
CM00 Clock output function
select bit (Note 2)
WAIT peripheral
function clock stop bit 0 : Do not stop peripheral clock
in wait mode
1 : Stop peripheral clock in
wait mode (Note 3)
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 4)
Main clock (X
IN
-X
OUT
)
stop bit (Note 5) 0 : Main clock On
1 : Main clock Off (Note 6)
System clock select bit
(Note 8) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
WR
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
CM06 Watchdog timer
function select bit 0 : Watchdog timer interrupt
1 : Reset (Note 7)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: The port P5
3
dose not function as an I/O port in microprocessor or memory expansion
mode.
When outputting ALE to P5
3
(bits 5 and 4 of processor mode register 0 is "01"), set
these bits to "00".
The port P5
3
function is not selected, even when you set "00" in microprocessor or
memory expansion mode and bit 7 of the processor mode register 0 is "1".
Note 3: fc
32
is not included. When this bit is set to "1", PLL cannot be used in WAIT.
Note 4: When Xc
IN
-Xc
OUT
is used, set port P8
6
and P8
7
to no pull-up resistance with the input
port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop
the main clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is
stable. Then set this bit to "1".
When X
IN
is used after returning from stop mode, set this bit to "0".
When this bit is "1", X
OUT
is "H". Also, the internal feedback resistance remains ON, so
X
IN
is pulled up to X
OUT
("H" level) via the feedback resistance.
Note 6: When the main clock is stopped, the main clock division register (address 000C
16
) is set
to the division by 8 mode.
However, in ring oscillator mode, the main clock division register is not set to the division
by 8 mode when X
IN
-X
OUT
is stopped by this bit.
Note 7: When "1" has been set once, "0" cannot be written by software.
Note 8: Set this bit "0" to "1" when sub clock oscillation is stable by setting CM04 to "1".
Set this bit "1" to "0" when main clock oscillation is stable by setting CM05 to "0".
Do not set CM04 and CM05 simultaneously.
Figure 1.10.3. System clock control register 0
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
109
DMAC
This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. DMAC is a function that transmit delete data of a source address (8 bits
/16 bits) to a destination address when transmission request occurs. When using three or more DMAC
channels, the register bank 1 and high-speed interrupt register are used as DMAC registers. If you are
using three or more DMAC channels, you cannot use high-speed interrupts. The CPU and DMAC use the
same data bus, but the DMAC has a higher bus access privilege than the CPU, and because of the use of
cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one
word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 1.11.1 shows the mapping of registers used
by the DMAC.
Table 1.11.1 shows DMAC specifications. Figures 1.11.2 to 1.11.5 show the structures of the
registers used.
As the registers shown in Figure 1.11.1 are allocated in the CPU, use LDC instruction when writing. When
writing to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use
MOV instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank
select flag (B flag) to "1" and use LDC instruction to set SB and FB registers.
DMA mode register 0, 1
DMA 0, 1 transfer count register
DMA 0, 1 transfer count reload register
DMA 0, 1 memory address register
DMA 0, 1 SFR address register
DMA 0, 1 memory address reload register
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
DMAC related registers
When using three or more DMAC channels
The high-speed interrupt register is used as a DMAC
register
DMA2 transfer count register
DMA2 transfer count reload register
DMA2 memory address register
DMA2 SFR address register
DCT2 (R0)
DCT3 (R1)
DRC2 (R2)
DRC3 (R3)
DMA2 (A0)
DMA3 (A1)
DSA2 (SB)
DSA3 (FB)
When using DMA2 and DMA3, use the CPU
registers shown in parentheses.
When using three or more DMAC channels
The register bank 1 is used as a DMAC register
DMA3 transfer count register
DMA3 transfer count reload register
DMA3 memory address register
DMA3 SFR address register
SVF
DMA2 memory address reload register
DRA2 (SVP)
DRA1 (VCT)
Flag save register
DMA3 memory address reload register
Figure 1.11.1. Register map using DMAC
In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals
output from the functions specified in the DMA request factor select bits are also used. However, in contrast
to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag.
(Note, however, that the number of actual transfers may not match the number of transfer requests if the
DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC
request bit.)
Under
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
110
Item Specification
No. of channels 4 (cycle steal method)
Transfer memory space •From any address in the 16 Mbytes space to a fixed address (16
Mbytes space)
•From a fixed address (16 Mbytes space) to any address in the 16 M
bytes space
Maximum No. of bytes transferred
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA request factors (Note) ________ ________
Falling edge of INT0 to INT3 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmission and reception interrupt requests
A-D conversion interrupt requests
Intelligent I/O interrupt
Software triggers
Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority)
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode •Single transfer
Transfer ends when the transfer count register is "000016".
•Repeat transfer
When the transfer counter is "000016", the value in the transfer
counter reload register is reloaded into the transfer counter and the
DMA transfer is continued
DMA interrupt request generation timing
When the transfer counter register changes from "000116" to "000016".
DMA startup •Single transfer
Transfer starts when DMA transfer count register is more than
"000116" and the DMA is requested after “012” is written to the
channel i transfer mode select bits
•Repeat transfer
Transfer starts when the DMA is requested after “112” is written to the
channel i transfer mode select bits
DMA shutdown •Single transfer
When “002” is written to the channel i transfer mode select bits and
DMA transfer count register becomes "000016" by DMA transfer or
write
•Repeat transfer
When “002” is written to the channel i transfer mode select bits
Reload timing When the transfer counter register changes from "000116" to "000016" in
repeat transfer mode.
Reading / writing the register Registers are always read/write enabled.
Number of DMA transfer cycles Between SFR and internal RAM : 3 cycles
Between external I/O and external memory : minimum 3 cycles
Table 1.11.1. DMAC specifications
Note: DMA transfer doed not affect any interrupt.
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
111
DMAi request cause select register
(i=0 to 3)
RW
DSEL0
DSEL1
DSEL2 DMA request cause
select bit (Note 1)
DSEL3
DSEL4
Software DMA
request bit (Note 2)
DSR
Nothing is assigned. When write, set "0".
When read, its content is indeterminate.
Refer to function table
DRQ DMA request bit
(Note 2, 3) 0 : Not requested
1 : Requested
Note 1: Set DMA inhibit before changing the DMA request cause. Set DRQ bit to "1" simultaneously.
e.g.) MOV.B #083h, DMiSL ; Set timer A0
Note 2: When setting DSR to "1", set DRQ bit to "1" using OR instruction etc. simultaneously.
e.g.) OR.B #0A0h, DMiSL
Note 3: Do not write "0" to this bit. There is no need to clear the DMA request bit.
Symbol Address When reset
DMiSL(i=0 to 3) 0378
16,
0379
16,
037A
16,
037B
16
0X000000
2
FunctionBit name
Bit
symbol
If software trigger is selected, a DMA request
is generated by setting this bit to "1" (When
read, the value of this bit is always "0")
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.11.2. DMAC register (1)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
112
Setting value DMA request cause
b4 b3 b2 b1 b0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
DMA0
Falling edge of INT0 pin
Both edges of INT0
DMA1 DMA2
Falling edge of INT2 pin
Both edges of INT2
DMA3
Falling edge of INT3 pin
Both edges of INT3
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
UART0 transmit
UART0 receive /ACK
UART1 transmit
UART1 receive /ACK
UART2 transmit
UART2 receive /ACK
UART3 transmit
UART3 receive /ACK
UART4 transmit
UART4 receive /ACK
Falling edge of INT1 pin
Both edges of INT1
A-D0
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
Intelligent I/O interrupt
control register 4
Intelligent I/O interrupt
control register 5
Intelligent I/O
interrupt
control register 6
A-D1
Intelligent I/O interrupt
control register 7
Intelligent I/O interrupt
control register 8
Intelligent I/O interrupt
control register 9
Intelligent I/O interrupt
control register 10
Intelligent I/O interrupt
control register 11
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
A-D0
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
Intelligent I/O interrupt
control register 4
Intelligent I/O interrupt
control register 5
Intelligent I/O interrupt
control register 6
Intelligent I/O interrupt
control register 7
Intelligent I/O interrupt
control register 8
A-D1
Intelligent I/O interrupt
control register 9
Intelligent I/O interrupt
control register 10
Intelligent I/O interrupt
control register 11
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Note 1: When INT3 pin is data bus in microprocessor mode, INT3 edge cannot be used as DMA3 request cause.
Note 2: UARTi receive /ACK switched by setting of UARTi special mode register and UARTi special mode
register 2 (i=0 to 3)
(Note 1)
(Note 1)
Table 1.11.2. DMAi request cause select register function
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
113
DMA mode register 0
(CPU internal register) Symbol When reset
DMD0 00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Channel 0 transfer
mode select bit
MD00
RW
MD01
BW0
RW0
MD11
b1 b0
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Must not be set
1 1 : Repeat transfer
A
AA
A
AA
A
AA
A
A
AA
AA
Bit name
MD10
Channel 0 transfer
unit select bit 0 : 8 bits
1 : 16 bits
Channel 0 transfer
direction select bit 0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
Channel 1 transfer
mode select bit
BW1
RW1
b5 b4
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Must not be set
1 1 : Repeat transfer
A
A
AA
AA
A
AA
A
AA
A
AA
Channel 1 transfer
unit select bit 0 : 8 bits
1 : 16 bits
Channel 1 transfer
direction select bit
DMA mode register 1
(CPU internal register) Symbol When reset
DMD1 0016
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Channel 2 transfer
mode select bit
MD20
RW
MD21
BW2
RW2
MD31
b1 b0
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Must not be set
1 1 : Repeat transfer
A
AA
A
AA
A
AA
A
AA
Bit name
MD30
Channel 2 transfer
unit select bit 0 : 8 bits
1 : 16 bits
Channel 2 transfer
direction select bit
Channel 3 transfer
mode select bit
BW3
RW3
b5 b4
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Must not be set
1 1 : Repeat transfer
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
Channel 3 transfer
unit select bit 0 : 8 bits
1 : 16 bits
Channel 3 transfer
direction select bit
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
Figure 1.11.3. DMAC register (2)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
114
Function
RW
Set transfer number
DMAi transfer count register (i = 0 to 3)
(CPU internal register)
Setting range
000016 to FFFF16
A
AA
Note 1: When "0" is set to this register, data transfer is not done even if DMA
is requested.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DCT2 and DCT3, set "1" to the register bank select flag
(B flag) of flag register (FLG), then set desired value to R0 and R1 of
register bank 1. Use MOV instruction to write to this register.
b15 b0
Function
RW
Set transfer number
Symbol Address When reset
DRC0 (Note 1) (CPU internal register) XXXX16
DRC1 (Note 1) (CPU internal register) XXXX16
DRC2 (bank 1;R2) (Note 2) (CPU internal register) 000016
DRC3 (bank 1;R3) (Note 2) (CPU internal register) 000016
DMAi transfer count reload register (i = 0 to 3)
(CPU internal register)
000016 to FFFF16
A
A
AA
AA
Note 1: Use LDC instruction to write to this register.
Note 2: When setting DRC2 and DRC3, set "1" to the register bank select
flag (B flag) of flag register (FLG), then set desired value to R2 and
R3 of register bank 1. Use MOV instruction to write to this register.
b15 b0
Symbol Address When reset
DCT0 (Note 2) (CPU internal register) XXXX16
DCT1 (Note 2) (CPU internal register) XXXX16
DCT2 (bank 1;R0) (Note 3) (CPU internal register) 000016
DCT3 (bank 1;R1) (Note 3) (CPU internal register) 000016
Setting range
Figure 1.11.4. DMAC register (3)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
115
b23 b0
Function RW
Set source or destination memory address
DMAi memory address register (i = 0 to 3)
(CPU internal register)
Setting range
000000
16
to FFFFFF
16
(16 Mbytes area)
A
A
AA
AA
Note 1: When the transfer direction select bit is "0" (fixed address to memory), this register
is destination memory address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is source memory address.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DMA2 and DMA3, set "1" to the register bank select flag (B flag) of
flag register (FLG), and set desired value to A0 and A1 of register bank 1. Use
MOV instruction to write to this register.
b0
Function RW
Set source or destination fixed address
DMAi SFR address register (i = 0 to 3)
(CPU internal register)
000000
16
to FFFFFF
16
(16 Mbytes area)
A
AA
Note 1: When the transfer direction select bit is "0" (fixed address to memory), this register
is source fixed address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is destination fixed address.
Note 2: Use LDC instruction to write to this register.
Note 3: When setting DSA2, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to SB of register bank 1. Use LDC instruction to write
to this register.
Note 4: When setting DSA3, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to FB of register bank 1. Use LDC instruction to write
to this register.
b0
Function RW
Set source or destination memory address
DMAi memory address reload register (i = 0 to 3) (Note 1)
(CPU internal register)
000000
16
to FFFFFF
16
(16 Mbytes area)
A
AA
Note 1: Use LDC instruction to write to this register.
Note 2: When setting DRA2, set desired value to save PC register (SVP).
Note 3: When setting DRA3, set desired value to vector register (VCT).
b23
b23
Setting range
Setting range
Symbol Address When reset
DMA0 (Note 2) (CPU internal register) XXXXXX
16
DMA1 (Note 2) (CPU internal register) XXXXXX
16
DMA2 (bank 1;A0) (Note 3) (CPU internal register) 000000
16
DMA3 (bank 1;A1) (Note 3) (CPU internal register) 000000
16
Symbol Address When reset
DSA0 (Note 2) (CPU internal register) XXXXXX
16
DSA1 (Note 2) (CPU internal register) XXXXXX
16
DSA2 (bank 1;SB) (Note 3) (CPU internal register) 000000
16
DSA3 (bank 1;FB) (Note 4) (CPU internal register) 000000
16
Symbol Address When reset
DRA0 (CPU internal register) XXXXXX
16
DRA1 (CPU internal register) XXXXXX
16
DRA2 (bank 1;SVP) (Note 2) (CPU internal register) XXXXXX
16
DRA3 (bank 1;VCT) (Note 3) (CPU internal register) XXXXXX
16
(Note 1)
(Note 1)
Figure 1.11.5. DMAC register (4)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
116
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of external data bus width control register
When in memory expansion mode or microprocessor mode, the transfer cycle changes according to
the data bus width at the source and destination.
1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8
bits (data bus width bit = “0”), there are two 8-bit data transfers. Therefore, two bus cycles are
required for reading and two cycles for writing.
2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit
= “0”) and the data bus width at the destination is 16 bits (data bus width bit = “1”), the data is read
in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading
and one cycle for writing.
3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit
= “1”) and the data bus width at the destination is 8 bits (data bus width bit = “0”), 16 bits of data are
read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two
cycles for writing.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the soffware wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.11.6 shows the example of the transfer cycles for a source read. Figure 1.11.6 shows the desti-
nation is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source
read cycles for the different conditions. In reality, the destination write cycle is subject to the same condi-
tions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer
cycle, remember to apply the respective conditions to both the destination write cycle and the source read
cycle. For example (2) in Figure 1.11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus
cycles are required for both the source read cycle and the destination write cycle.
Under
development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
117
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
(1) •When 8-bit data is transferred
•When 16-bit data is transferred on a 16-bit data bus and the source address is even
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU use
Source
Source
(3) •When one wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Source + 1
Source + 1
(2) •When 16-bit data is transferred and the source address is odd
•When 16-bit data is transferred and the width of data bus at the source is 8-bit
(When the width of data bus at the destination is 8-bit, there are also two destination write cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Source + 1
Source + 1
(4) •When one wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are
two destination write cycles).
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Figure 1.11.6. Example of the transfer cycles for a source read
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
118
Memory expansion mode
Microprocessor mode
Single-chip mode
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.11.2. No. of DMAC transfer cycles
Transfer unit Bus width Access address No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1 1 1 1
8-bit transfers (DSi = “1”) Odd 1 1 1 1
(BWi = “0”) 8-bit Even —— 11
(DSi = “0”) Odd —— 11
16-bit Even 1 1 1 1
16-bit transfers (DSi = “1”) Odd 2 2 2 2
(BWi = “1”) 8-bit Even —— 22
(DSi = “0”) Odd —— 22
Coefficient j, k
Internal memory
External memory
Coefficient j Coefficient k
Internal ROM/RAM No wait 1 1
Internal ROM/RAM One wait 2 2
SFR area 2 2
Separate bus No wait 1 2
Separate bus One wait 2 2
Separate bus Two waits 3 3
Separate bus Three waits 4 4
Multiplex bus 3 3
DMA Request Bit
The DMAC can issue DMA requests using preselected DMA request factors for each channel as triggers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i
transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request
is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.
Under
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
119
BCLK
AAA
AAA
DMA0
AAA
AAA
DMA1
DMA0
request bit
DMA1
request bit
AAA
AAAAAAA
A
A
A
CPU
INT0
INT1
In this example, DMA transfer request signals are input simultaneously from
external factors and the DMA transfers are executed in the minimum cycles.
AA
AA
AA
Bus
priviledge
acquired
AA
AA
(1) Internal factors
The DMAi request flag is set to “1” in response to internal factors at the same time as the interrupt
request bit of the interrupt control register for each factor is set. This is because, except for software
trigger DMA factors, they use the interrupt request signals output by each function.
The DMAi request bit is cleared to "0" when the DMA transfer starts or the DMA transfer is disabled
(channel i transfer mode select bits are "00" and the DMAi transfer count register is "0").
(2) External factors ______
These are DMA request factors that are generated by the input edge from the INTi pin (where i indi-
______
cates the DMAC channel). When the INTi pin is selected by the DMAi request factor select bit as an
external factor, the inputs from these pins become the DMA request signals.
When an external factor is selected, the DMAi request bit is set, according to the function specified in the
______
DMA request factor select bit, on either the falling edge of the signal input via the INTi pins, or both edges.
When an external factor is selected, the DMAi request bit is cleared, in the same way as the DMAi
request bit is cleared for internal factors, when the DMA transfer starts or the DMA transfer is in
disable state.
(3) Relationship between external factor request input and DMAi request bits, and DMA transfer timing
When the request inputs to DMAi occur in the same sampling cycle (between the falling edge of BCLK
and the next falling edge), the DMAi request bits are set simultaneously, but if the DMAi enable bits
are all set, DMA0 takes priority and the transfer starts. When one transfer unit is complete, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, DMA1 transfer starts,
and, when one transfer unit is complete, the privilege is again returned to the CPU.
The priority is as follows: DMA0 > DMA1 > DMA2 > DMA3.
Figure 1.11.7. DMA transfer example by external factors shows what happens when DMA0 and DMA1
requests occur in the same sampling cycle.
Figure 1.11.7. DMA transfer example by external factors
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
120
At least 8 + 6 x N cycles
(N: enabled channel number)
Precautions for DMAC
(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M32C/83, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is
not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select
register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to
the DMA request bit, simultaneously. In this case, the corresponding DMA channel is set to disabled. At
least 8 + 6 x N (N: enabled channel number) clock cycles are needed from the instruction to write to the
DMAi request cause select bit to enable DMA.
e.g.) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after
DMA initial setting
push.w R0 ; Store R0 register
stc DMD0, R0 ; Read DMA mode register 0
and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00"
ldc R0, DMD0 ; DMA0 disabled
mov.b #10000011b, DM0SL ; Select timer A0
; (Write "1" to DMA request bit simultaneously)
nop
:
ldc R0, DMD0 ; DMA0 enabled
pop.w R0 ; Restore R0 register
DMAC II
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121
Causes to activate DMAC II
Transfer data
Unit of transfer
Direction of transfer
Transfer space
Transfer mode
Chained transfer function
Interrupt at end of transfer
Interrupt request from any peripheral I/O whose interrupt priority is set to
"level 7" by the Interrupt Control Register
(1) Memory -> memory (memory-to-memory transfer)
(2) Immediate data -> memory (immediate data transfer)
(3) Memory (or immediate data) + memory -> memory (arithmetic transfer)
Transferred in 8 or 16 bits
64-Kbyte space at address up to 0FFFF
16
Fixed or forward address
Can be selected individually for the source and the destination of transfer.
(1) Single transfer
(2) Burst transfer
Parameters (transfer count, transfer address, and other information)
are switched over when the transfer counter reaches zero.
Interrupt is generated when the transfer counter reaches zero.
Item Specification
Multiple transfer function Multiple data transfers can be performed by one DMA II transfer request generated.
(Note)
DMAC II
When requested by an interrupt from any peripheral I/O, the DMAC performs a memory-to-memory trans-
fer, an immediate data transfer, or an arithmetic transfer (to transfer the sum of two data added).
Specifications of DMAC II are shown in Table 1.12.1.
Table 1.12.1 Specifications of DMAC II
Note : When transfer unit is 16 bits and destination address is 0FFFF16, data is transfered to addresses
0FFFF16 and 1000016. When source address is 0FFFF16, data is transfered as in the previous.
Settings of DMAC II
DMAC II can be enabled for use by setting up the following registers and tables.
• Exit Priority Register (address 009F16)
• DMAC II Index
• Interrupt Control Register for the peripheral I/O that requests a transfer by DMAC II
• Relocatable Vector Table for the peripheral I/O that requests a transfer by DMAC II
• When using an intelligent I/O or CAN interrupt, Interrupt Enable Register’s interrupt request latch bit
(bit 0)
(1) Exit priority register (address 009F16)
If this register’s DMAC II select bit (bit 5) and fast interrupt select bit (bit 3) respectively are set to 1 and
0, DMAC II is activated by an interrupt request from any peripheral I/O whose interrupt priority is set to
“level 7” by the interrupt priority level select bit.
The configuration of the exit priority register is shown in Figure 1.12.1.
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
122
Exit priority register
When reset
XX0X00002
Address
009F16
Symbol
RLVL
RW
RLVL0
RLVL1
RLVL2
Interrupt priority set bits
for exiting Stop/Wait
state (Note 1)
FSIT High-speed interrupt
set bit (Note 2)
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 =
high-speed interrupt
DMA II DMA II select bit
(Note 3)
0: Interrupt priority level 7 = normal
interrupt or high-speed interrupt
1: Interrupt priority level 7 =
DMA II transfer
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
Bit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than
that set in the exit priority register.
Set to the same value as the processor interrupt priority level (IPL) set in the flag
register (FLG).
Note 2: The high-speed interrupt can only be specified for interrupts with interrupt priority level
7. Specify interrupt priority level 7 for only one interrupt.
Note 3: Do not set this bit to 0 after once setting it to 1.
When this bit is 1, do not set the high-speed interrupt select bit to 0. (This cannot be
used simultaneously with the high-speed interrupt.)
Transfers by DMAC II are unaffected by the interrupt enable flag (I flag) and processor
interrupt priority level (IPL).
Figure 1.12.1. Exit priority register
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
123
Transfer mode (MOD)
Transfer counter (COUNT)
Transfer source address (or imm data)(SADR)
Operation address (OADR)
Transfer destination address (DADR)
Chained transfer address (CADR0)
Chained transfer address (CADR1)
End-of-transfer interrupt address (IADR0)
End-of-transfer interrupt address (IADR1)
16 bits
DMAC II Index
start address (BASE)
BASE + 2
BASE + 4
BASE + 6
BASE + 8
BASE + 10
BASE + 14
BASE + 16
BASE + 12
(Note1)
(Note2)
(Note2)
(Note3)
(Note3)
Transfer mode (MOD)
Transfer counter (COUNT)
Transfer source address (SADR1)
Transfer destination address (DADR1)
Transfer source address (SADR2)
Transfer destination address (DADR2)
Transfer source address (SADR7)
Transfer destination address (DADR7)
16 bits
BASE
BASE + 2
BASE + 4
BASE + 6
BASE + 8
BASE + 10
BASE + 28
BASE + 30
Memory-to-memory transfer, Immediate transfer,
Arithmetic transfer Multiple transfer
Note 1: Delete this data when not using the arithmetic transfer function.
Note 2: Delete this data when not using the chained transfer function.
Note 3: Delete this data when not using an end-of-transfer interrupt.
(2) DMAC II Index
The DMAC II Index is a data table, comprised of 8 to 18 bytes (max. 32 kbytes when multiple transfer
function is selected), which contains such parameters as transfer mode, transfer counter, transfer
source address (or immediate data), operation address, transfer destination address, chained trans-
fer address, and end-of-transfer interrupt address.
This DMAC II Index is located in the RAM area.
Configuration of the DMAC II Index is shown in Figure 1.12.2. The configuration of the DMAC II Index
by transfer mode is shown in Table 1.12.2.
• Transfer mode (MOD)
This two-byte data sets DMAC II transfer mode. Configuration of transfer modes is shown in Figure
1.12.3.
• Transfer counter (COUNT)
This two-byte data sets the number of times transfer is performed.
• Transfer source address (SADR)
This two-byte data sets the memory address from which data is transferred or immediate data.
• Operation address (OADR)
This two-byte data sets the memory address to be operated on for calculation. This data is added to
the table only when using the arithmetic transfer function.
• Transfer destination address (DADR)
This two-byte data sets the memory address to which data is transferred.
• Chained transfer address (CADR)
This four-byte data sets the DMAC II Index start address for the next DMAC II transfer to be per-
formed. This data is added to the table only when using the chained transfer function.
• End-of-transfer interrupt address (IADR)
This four-byte data sets the jump address for end-of-transfer interrupt processing. This data is added
to the table only when using an end-of-transfer interrupt.
Figure 1.12.2. DMAC II index
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
124
Transmit data Memory-to-memory transfer
/immediate data transfer Arithmetic transfer
Multiple transfer
Chained transfer
Interrupt at
end of transfer
Not use
Not use Not use
Not useUse Not use
Not use Not use
Use
Use
Not use
Use
Use
Use
Cannot use
Cannot use
Use
Use
DMAC II
index
COUNT
MOD
SADR
DADR
COUNT
MOD
SADR
DADR
CADR0
CADR1
COUNT
MOD
SADR
OADR
OADR OADR
DADR
IADR0
IADR1
COUNT
MOD
SADR
DADR
IADR0
IADR1
COUNT
MOD
SADR
DADR
CADR0
CADR1
IADR0
IADR1
OADR
8 bytes
12 bytes
COUNT
MOD
SADR
DADR
COUNT
MOD
SADR
DADR
CADR0
CADR1
10 bytes
14 bytes
12 bytes
14 bytes
18 bytes
COUNT
MOD
SADR
DADR
CADR0
CADR1
IADR0
IADR1
16 bytes
COUNT
MOD
SADR1
DADR1
SADRi
DADRi
i=1 to 7
Max. 32 bytes
(when i=7)
Function
(MULT=0) Function
(MULT=1)
Transfer mode(MOD)
RW
SIZE
IMM
UPDS
Transfer unit
select bit
UPDD
INTE
/CNT2
Transfer distination
direction select bit 0: Fixed address
1: Forward address
0: Single transfer
1: Burst transfer
Alithmatic transfer
function select bit 0: Not used
1: Used
0: 8 bits
1: 16 bits
BRST
/CNT1
OPER
/CNT0
CHAIN
Transfer data
select bit
Transfer source
direction select bit
Burst transfer
select bit
End of transfer
interrupt select bit
Chained transfer
select bit
0: Immedeate data
1: Memory Must set to "1"
Must set to "0"
MULT Multiple transfer
select bit
0: Not multiple transfer
1: Multiple transfer
0: Fixed address
1: Forward address
0: Interrupt not used
1: Interrupt used
0: Chained transfer not used
1: Chained transfer used
b6 b5 b4
0 0 0: Do not
set this
0 0 1: Once
0 1 0: Twice
:
:
1 1 0: 6 times
1 1 1: 7 times
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Bit name
Bit
symbol
b7 b0
b15
(b7) b8
(b0)
Table 1.12.2. The configuration of the DMAC II Index by transfer mode
Figure 1.12.3. Transfer mode
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
125
(3) Interrupt Control Register for Peripheral I/O
For peripheral I/O interrupts used to request a transfer by DMAC II, set the Interrupt Control Register
for each peripheral I/O to select “level 7” for their interrupt priority.
(4) Relocatable Vector Table for Peripheral I/O
In the relocatable vector table for each peripheral I/O that requests a transfer by DMAC II, set the
DMAC II Index start address. (When using chained transfers, the relocatable vector table must be
located in the RAM.)
(5) Interrupt Enable Register’s interrupt request latch bit (bit 0)
When using an intelligent I/O or CAN interrupt to activate DMAC II, set to 0 the Interrupt Enable
Register’s interrupt request latch bit (bit 0) for the intelligent I/O or CAN interrupt that requests a
transfer by DMAC II.
Operation of DMAC II
The DMAC II function is selected by setting the DMAC II select bit (bit 5 at address 009F16) to 1. All
peripheral I/O interrupt requests which have had their interrupt priorities set to “level 7” by the Interrupt
Control Register comprise DMAC II interrupt requests. These interrupt requests (priority level = 7) do not
generate an interrupt, however.
When an interrupt request is generated by any peripheral I/O whose interrupt priority is set to “level 7,”
DMAC II is activated no matter which state the I flag and processor interrupt priority level(IPL) is in. If an
_______
interrupt request with higher priority than that (e.g., NMI or watchdog timer) occurs, this higher priority
interrupt has precedence over and is accepted before DMAC II transfers. The pending DMAC II transfer
is started after the interrupt processing sequence for that interrupt finishes.
Transfer data
DMAC II transfers data in units of 8 or 16 bits as described below.
• Memory-to-memory transfer: Data is transferred from any memory location in the 64-Kbyte space to
any memory location in the same space.
• Immediate data transfer: Data is transferred as immediate data to any memory location in the 64-
Kbyte space.
• Arithmetic transfer: Two 8 or16 bits of data are added together and the result is transferred to any
memory location in the 64-Kbyte space.
When transfer unit is 16 bits and destination address is 0FFFF16, data is transfered to addresses
0FFFF16 and 1000016. When source address is 0FFFF16, data is transfered as in the previous.
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
126
(1) Memory-to-memory transfer
Data can be transferred from any memory location in the 64-Kbyte space to any memory location in
the same space in one of the following four ways:
• Transfer from a fixed address to another fixed address
• Transfer from a fixed address to a variable address
• Transfer from a variable address to a fixed address
• Transfer from a variable address to another variable address
If variable address mode is selected, the transfer address is incremented for the next DMA II transfer
to be performed. When transferred in units of 8 bits, the transfer address is incremented by one; when
transferred in units of 16 bits, the transfer address is incremented by two. If the transfer source or
destination address exceeds 0FFFF16 as a result of address incrementation, the transfer source or
destination address recycles back to 0000016.
(2) Immediate data transfer
Data is transferred as immediate data to any memory location in the 64-Kbyte space. A fixed or
variable address can be selected for the transfer destination address. Store the immediate data in the
DMAC II Index’s transfer source address. When transferring 8-bit immediate data, set the data in the
lower byte position of the transfer source address. (The upper byte is ignored.)
(3) Arithmetic transfer
Data in two memory locations of the 64-Kbyte space or immediate data and data in any memory
location of the 64-Kbyte space are added together and the result is transferred to any memory location
in the 64-Kbyte space. Set the memory location to be operated on or immediate data in the DMAC II
Index’s transfer source address field and the other memory location to be operated on in the DMAC II
Index’s operation address field. When performing this mode of transfer on two memory locations, a
fixed or variable address can be selected for the transfer source and transfer destination addresses. If
the transfer source address is chosen to be variable, the operation address also becomes variable.
When performing this mode of transfer on immediate data and any memory location, a fixed or vari-
able address can be selected for the transfer destination address.
Transfer modes
DMAC II supports single and burst transfers. Use the burst transfer select bit (bit 5) for transfer mode
setup in the DMAC II index to choose single or burst transfer mode. Use the DMAC II index transfer
counter to set the number of times a transfer is performed. Neither single transfer nor burst transfer is
performed if the value “000016” is set in the transfer counter.
(1) Single transfer
For a DMAC II transfer request, 8 or 16 bits of data (one transfer unit) is transferred once. If the
transfer source or transfer destination address is chosen to be variable, the next DMA II transfer is
performed on an incremented memory address.
The transfer counter is decremented by each DMA II transfer performed. When using the end-of-transfer
interrupt facility, an end-of-transfer interrupt is generated at the time the transfer counter reaches zero.
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
127
(2) Burst transfer
For a DMAC II transfer request, data transfers are performed in succession a number of times as set
by the DMAC II Index transfer counter. When using the end-of-transfer interrupt facility, an end-of-
transfer interrupt is generated at the time a burst transfer finishes (i.e., when the transfer counter
reaches zero after being decremented for each data transfer performed).
(3) Multiple transfers
For multiple transfers, use the multiple transfer select bit (bit 15) for transfer mode setup in the DMAC
II Index. Setting this bit to 1 selects the multiple transfer function. For the multiple transfer function,
memory to memory transfer can be performed.
Multiple transfers are performed for one DMAC II transfer request received. Use DMAC II Index trans-
fer mode bits 4–6 to set the number of transfers to be performed. (Setting these bits to 001 performs
one transfer; setting these bits to 111 performs 7 transfers. Setting these bits to 000 is inhibited.)
The transfer source and transfer destination addresses are alternately incremented beginning with the
DMAC II Index BASE address + 4 (as many times as the number of transfers performed).
When using multiple transfer function, arithmetic transfer, burst transfer, end-of-transfer interrupt and
chained transfer cannot be used.
(4) Chained transfer
For chained transfers, use the chained transfer select bit (bit 7) for transfer mode setup in the DMAC
II Index. Setting this bit to 1 selects the chained transfer function. The following describes how a
chained transfer is performed.
1) When a DMA II transfer request (interrupt request from any peripheral I/O) is received, a DMAC II
Index transfer is performed corresponding to the received request.
2) When the DMAC II Index transfer counter reaches zero, the chained transfer address in the DMAC
II Index (i.e., the start address of the DMAC II Index that contains a description of the next DMAC II
transfer to be performed) is written to the relocatable vector table for the peripheral I/O.
3) From the next DMA II transfer request on, transfers are performed based on the DMAC II Index
indicated by the rewritten relocatable vector table of the peripheral I/O.
Before the chained transfer function can be used, the relocatable vector table must be located in the
RAM area.
(5) End-of-transfer interrupt
For end-of-transfer interrupts, use the end-of-transfer interrupt select bit (bit 6) for transfer mode setup
in the DMAC II Index. Setting this bit to 1 selects the end-of-transfer interrupt function. Set the jump
address for end-of-transfer interrupt processing in the DMAC II Index’s end-of-transfer interrupt ad-
dress field. An end-of-transfer interrupt is generated when the DMAC II Index transfer counter reaches
zero.
DMAC II
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
128
A=0 B=1 C=0 D=0 E=0
First DMAC II transfer t=6+27X1+4X1=37 cycle
Second DMAC II transfer t=6+27X1+4X0=33 cycle
Transfer counter = 2
Down count of transfer counter
Transfer counter = 1
Transfer counter = 1
Application
program DMAC II transfer
(First time) DMAC II transfer
(Second time)
8
cycles
End of transfer interrupt program
DMAC II transfer request
Down count of transfer counter
Transfer counter = 0
33
cycles
37
cycles
DMAC II transfer request
When using an end-of-transfer interrupt (transfer counter = 2) after performing a memory to memory
single transfer twice from a variable source address to a fixed destination address, with the chained
transfer function unselected
Application
program
Execution time
The number of DMAC II execution cycles is calculated by the equation below.
For other than multiple transfers, t = 6 + (26 + A + B + C + D) X m + (4 + E) X n (cycles)
For multiple transfers, t = 21 + (11 + B + C) X k (cycles)
where
A: If the source of transfer is immediate data, A = 0; if it is memory, A = –1
B: If the source address of transfer is a variable address, B = 0; if it is a fixed address, B = 1
C: If the destination address of transfer is a variable address, C = 0; if it is a fixed address, C = 1
D: If the arithmetic function is not selected, D = 0; if the arithmetic function is selected and the source of
transfer is immediate data or fixed address memory, D = 7; if the arithmetic function is selected and the
source of transfer is variable address memory, D = 8
E: If the chained transfer function is not selected, E = 0; if the chained transfer function is selected, E = 4
m: For single transfer, m = 1; for burst transfer, m = the value set by the transfer counter
n: If the transfer count is one, n = 0; if the transfer count is two or greater, n = 1
k: Number of transfers set by transfer mode bits 4–7
The above equation applies only when all of the following conditions are met, however.
• No bus wait states are inserted.
• The DMAC II Index is set to an even address.
• During word transfer, the transfer source address, transfer destination address, and operation address
all are set to an even address.
Note that the first instruction in end-of-transfer interrupt processing is executed 7 cycles after DMAC II
transfers are completed.
Figure 1.12.4. Transfer Time
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
129
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of timers.
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
TA0
IN
TA1
IN
TA2
IN
TA3
IN
TA4
IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
f
1
f
8
f
2n
f
C32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32 f
C32
1/8
f
1
f
8
f
2n
(n = 0 to 15
however, no division when n=0)
X
IN
X
CIN
Clock prescaler reset flag (bit 7
at address 0341
16
) set to “1”
Reset
Clock prescaler
Timer B2 overflow
1/2n
Count source
prescaler register
Figure 1.13.1. Timer A block diagram
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
130
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
TB0IN
TB1IN
TB2IN
Timer B0
Timer B1
Timer B2
f1 f8 f2n fC32
Timer B0 interrupt
Noise
filter
Noise
filter
Noise
filter
Timer B2 overflow (to timer A count source)
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
TB3IN
TB4IN
TB5IN
Timer B3
Timer B4
Timer B5
Timer B3 interrupt
Noise
filter
Noise
filter
Noise
filter
Timer B1 interrupt
Timer B2 interrupt
Timer B4 interrupt
Timer B5 interrupt
1/32 fC32
1/8
f1
f8
f2n
(n = 0 to 15
however, no division when n=0)
XIN XCIN
Clock prescaler reset flag (bit 7
at address 034116) set to “1”
Reset
Clock prescaler
1/2n
Count source
prescaler register
Figure 1.13.2. Timer B block diagram
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
131
Timer A
Figure 1.14.1 shows the block diagram of timer A. Figures 1.14.2 to 1.14.6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer outputs one effective pulse until the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Count start flag
(Address 0340
16
)
Up count/down count
TAi Addresses TAj TAk
Timer A0 0347
16
0346
16
Timer A4 Timer A1
Timer A1 0349
16
0348
16
Timer A0 Timer A2
Timer A2 034B
16
034A
16
Timer A1 Timer A3
Timer A3 034D
16
034C
16
Timer A2 Timer A4
Timer A4 034F
16
034E
16
Timer A3 Timer A0
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
AAAA
AAAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f
1
f
8
f
32
External
trigger
TAi
IN
(i = 0 to 4)
TB2 overflow
• Event counter
f
C32
Clock selection
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Pulse output
Toggle flip-flop
TAi
OUT
(i = 0 to 4)
Data bus low-order bits
Data bus high-order bits
A
A
A
Up/down flag
Down count
(Address 0344
16
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Polarity
selection
Figure 1.14.1. Block diagram of timer A
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
132
Timer Ai register (i = 0 to 4) (Note 1)
Symbol Address When reset
TAi (i = 0 to 2) 0347
16
,0346
16
, 0349
16
,0348
16
, 034B
16
,034A
16
Indeterminate
TAi (i = 3, 4) 034D
16
,034C
16
, 034F
16
,034E
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
WR
Timer mode
Function
Values that can be set
Event counter
mode
One-shot timer
mode
00
16
to FE
16
(High-order address)
00
16
to FF
16
(Low-order address)
0000
16
to FFFE
16
0000
16
to FFFF
16
0000
16
to FFFF
16
0000
16
to FFFF
16
16-bit counter (set to dividing ratio)
16-bit counter (set to dividing ratio)
16-bit counter (set to one shot width)
Pulse width
modulation mode
(16-bit PWM)
16-bit pulse width modulator
(set to PWM pulse “H” width)
Pulse width
modulation mode
(8-bit PWM)
(Note 2)
(Note 6)
(Note 4, 7)
Low-order 8 bits : 8-bit prescaler
(set to PWM period)
High-order 8 bits : 8-bit pulse width modulator
(set to PWM pulse “H” width)
(Note 5, 7)
(Note 3)
(Note 3)
(Note 3)
Note 1: Read and write data in 16-bit units.
Note 2: Counts pulses from an external source or timer overflow.
Note 3: Use MOV instruction to write to this register.
Note 4: When setting value is n, PWM period and “H” width of PWM pulse are as follows:
PWM period : (2 - 1) / fi
PWM pulse “H” width : n / fi
Note 5: When setting value of high-order address is n and setting value of low-order address is m, PWM period and
“H” width of PWM pulse are as follows:
PWM period : (2 - 1) X (m + 1) / fi
PWM pulse “H” width : (m + 1)n / fi
Note 6: When the timer Ai register is set to "0000
16
", the counter does not operate and the timer Ai interrupt request
is not generated. When the pulse is set to output, the pulse does not output from the TAi
OUT
pin.
Note 7: When the timer Ai register is set to "0000
16
", the pulse width modulator does not operate and the output
level of the TAi
OUT
pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also
occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register
are set to "00
16
".
16
8
Figure 1.14.2. Timer A-related registers (1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
133
Figure 1.14.3. Timer A-related registers (2)
Timer Ai mode register (i = 0 to 4)
Symbol Address When reset
TAiMR(i=0 to 4) 035616, 035716, 035816, 035916, 035A16 00000X002
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each
operation mode
Count source
select bit
Operation mode
select bit
This bit is invalid in M32C/80 series.
Port output control is set by the function select
registers A, B and C.
Function varies with each
operation mode
Symbol Address When reset
TABSR 0340
16
00
16
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count
start flag
Timer B1 count
start flag
Timer B0 count
start flag
Timer A4 count
start flag
Timer A3 count
start flag
Timer A2 count
start flag
Timer A1 count
start flag
Timer A0 count
start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
134
Figure 1.14.4. Timer A-related registers (3)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol Address When reset
UDF 0344
16
00
16
TA4P
TA3P
TA2P
Up/down flag (Note 1)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Note 1: Use MOV instruction to write to this register.
Note 2: This specification becomes valid when the up/down flag content is selected for up/down switching cause.
Note 3: When not using the two-phase pulse signal processing function, set the select bit to “0”.
0 : Down count
1 : Up count
0 : Down count
1 : Up count
0 : Down count
1 : Up count
0 : Down count
1 : Up count
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
WR
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
A
A
A
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 3)
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0342
16
00
16
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA3OS
TA4OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
TA0TGL
TA0TGH
0 0 :
Input on TA0IN is selected
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
Note 1: When read, the value is “0”.
Note 2: Set the corresponding pin output function select register to I/O port, and port direction register to “0”.
WR
0 : Invalid
1 : Timer start
Z phase input enable bitTAZIE 0 : Invalid
1 : Valid
0 : Invalid
1 : Timer start
0 : Invalid
1 : Timer start
0 : Invalid
1 : Timer start
0 : Invalid
1 : Timer start
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
135
Symbol Address When reset
CPSRF 0341
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag 0 : Ignored
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.
TA1TGL
Symbol Address When reset
TRGSR 0343
16
00
16
Timer A1 event/trigger
select bit 0 0 : Input on TA1
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Input on TA2
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Input on TA3
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Timer A2 event/trigger
select bit
Timer A3 event/trigger
select bit
Timer A4 event/trigger
select bit
WR
TA1TGH
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
b1 b0
b3 b2
b5 b4
b7 b6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note: Set the corresponding port function select register A to I/O port, and port direction register to “0”.
A
A
A
A
Figure 1.14.5. Timer A-related registers (4)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
136
Symbol Address When reset
TCSPR 035F
16
0XXXXXXX
2
Count source prescaler register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Count start bit 0 : Stops counting
1 : Starts counting
CST
WR
Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.
A
A
Note 1: Set count start bit to “0” before writing to count value set bits.
Note 2: When this bit is set to “0”, divider circuit is inactive.
A
A
A
A
A
A
A
A
CNT0
CNT1
CNT2
CNT3
Count value set bits 0 0 0 0 : No division
0 0 0 1 : Division by 2
0 0 1 0 : Division by 4
0 0 1 1 : Division by 6
1 1 0 1 : Division by 26
1 1 1 0 : Division by 28
1 1 1 1 : Division by 30
(Note 1)
(Note 2)
b3 b2 b1 b0
Figure 1.14.6. Timer A-related registers (5)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
137
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7
shows the timer Ai mode register in timer mode.
Table 1.14.1. Specifications of timer mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(m+1)m : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output (Setting by corresponding function select
registers A, B and C)
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Figure 1.14.7. Timer Ai mode register in timer mode
Timer Ai mode register
(i = 0 to 4) (Timer mode)
Symbol Address When reset
TAiMR(i=0 to 4) 0356
16
, 0357
16
, 0358
16
, 0359
16
, 035A
16
00000X00
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0 Count source
select bit
Operation mode
select bit
This bit is invalid in M32C/80 series.
Port output control is set by the function select
registers A, B and C.
Note 1: X value can be “0” or “1”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F
16
).
Gate function
select bit 0 X
: Gate function not available
(TAi
IN
pin is a normal port pin)
1 0 : Timer counts only when TA
iIN
pin is held “L”
1 1 : Timer counts only when TA
iIN
pin is held “H”
0 (Set to “0” in timer mode)
(Note 2)
(Note 2)
(Note 1)
(Note 3)
b4 b3
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
b7 b6
Under
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
138
Note: This does not apply when the free-run function is selected.
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal.
Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.8 shows
the timer Ai mode register in event counter mode.
Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item Specification
Count source •External signals input to TAi IN pin (effective edge can be selected by software)
•TB2 overflows or underflows, TAj overflows or underflows
Count operation •Up count or down count can be selected by external signal or software
•When the timer overflows or underflows, it reloads the reload register contents
before continuing counting (Note)
Divide ratio • 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer overflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input (Setting by corre-
sponding function select registers A, B and C)
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function •Free-run count function
Even when the timer overflows or underflows, the reload register content is not
reloaded to it
•Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
139
Timer Ai mode register (i = 0 to 4) (Event counter mode)
Symbol Address When reset
TAiMR(i=0 to 4) 0356
16
, 0357
16
, 0358
16
, 0359
16
, 035A
16
00000X00
2
Bit name Function
Bit
symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 1 : Event counter mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
TMOD0
TCK0
Operation mode
select bit
This bit is invalid in M32C/80 series.
Port output control is set by the function select registers A, B and C.
Note 1: Count source is select by the event/trigger select bit (addresses 0342
16
, 0343
16
) in event counter mode.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Signal of TAi
OUT
pin counts down at the time of “L” and counts up at the time of “H”.
Note 4: This bit is valid for timer A3 mode register.
Timer A0 and A1 can be “0” or “1”.
Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4
processing operation.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 0344
16
) is set to “1”. Also, always be
sure to set the event/trigger select bit (address 0343
16
) to “00”.
0 (Set to “0” in Event counter mode)
(Note 1)
0 (Set to “0” when using
two-phase pulse signal
processing)
(When not using two-phase
pulse signal processing) (When using two-phase
pulse signal processing)
Function
Count polarity
select bit
(Note 2)
0 : Counts external
signal's falling edges
1 : Counts external
signal's rising edges
Up/down
switching cause
select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal
(Note 3)
1 (Set to “1” when using
two-phase pulse signal
processing)
Count operation
type select bit 0 : Reload type
1 : Free-run type
Two-phase pulse
signal processing
operation select
bit (Note 4,Note 5)
0 : Normal processing
operation
1 : Multiply-by-4
processing operation
0 (Set to “0” when not
using two-phase pulse
signal processing)
MR0
Figure 1.14.8. Timer Ai mode register in event counter mode
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
140
Item Specification
Count source Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation •Up count or down count can be selected by two-phase pulse signal
•When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note 1)
Divide ratio •1/ (FFFF 16 - n + 1) for up count
•1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
Timer overflows or underflows
TAiIN pin function Two-phase pulse input
TAiOUT pin function Two-phase pulse input (Set corresponding function select register A for I/O port)
Read from timer Count value can be read out by reading timer A2, A3, or A4 register
Write to timer •When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both reload
register and counter
•When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only reload
register. (Transferred to counter at next reload time.)
Select function (Note 2) •Normal processing operation (TimerA2 and timer A3)
The timer counts up rising edges or counts down falling edges on the TAiIN pin when
input signal on the TAiOUT pin is “H”
•Multiply-by-4 processing operation (TimerA3 and timer A4)
If the phase relationship is such that the TAiIN pin goes “H” when the input signal on
the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and
TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input
signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the
TAiOUT and TAiIN pins.
TAiOUT
Up
count Up
count Up
count Down
count Down
count Down
count
TAiIN
(i=2,3)
TAiOUT
TAiIN
(i=3,4)
Count up all edges
Count up all edges
Count down all edges
Count down all edges
(when processing two-phase pulse signal with timers A2, A3, and A4)
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and timer A4 is fixed to
multiply-by-4 operation.
Table 1.14.3. Timer specifications in event counter mode
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
141
The pulse must be wider than this width. Note: When the rising edge of INT2 is selected.
TA3
OUT
(A phase)
Count source
TA3
IN
(B phase)
INT2
(Note)
(Z phase)
TA3OUT
(A phase)
Count source
TA3IN
(B phase)
Becoming “0” at this timing.
Count value mm+11 2 3 4 5
INT2
(Z phase)
(Note)
Note: When the rising edge of INT2 is selected.
• Counter Resetting by Two-Phase Pulse Signal Processing
This function resets the timer counter to “0” when the Z-phase (counter reset) is input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode, two-phase pulse signal processing,
free-run type, and multiply-by-4 processing. The Z phase is input to the INT2 pin.
When the Z-phase input enable bit (bit 5 at address 034216) is set to “1”, the counter can be reset by
Z-phase input. For the counter to be reset to “0” by Z-phase input, you must first write “000016” to the
timer A3 register (addresses 034D16 and 034C16).
The Z-phase is input when the INT2 input edge is detected. The edge polarity is selected by the INT2
polarity switch bit (bit 4 at address 009C16). The Z-phase must have a pulse width greater than 1 cycle
of the timer A3 count source. Figure 1.14.9 shows the relationship between the two-phase pulse (A
phase and B phase) and the Z phase.
The counter is reset at the count source following Z-phase input. Figure 1.14.10 shows the timing at
which the counter is reset to “0”.
Note that timer A3 interrupt requests occur successively two times when timer A3 underflow and INT2
input reload occures at the same time.
Do not use timer A3 interrupt request when this function is used.
Figure 1.14.9. The relationship between the two-phase pulse (A phase and B phase) and the Z phase
Figure 1.14.10. The counter reset timing
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
142
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts
up and continues operating for a given period. Figure 1.14.11 shows the timer Ai mode register in one-
shot timer mode.
Table 1.14.4. Timer specifications in one-shot timer mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation •The timer counts down
•When the count reaches 000016, the timer stops counting after reloading a new
count
•If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output (Setting by corresponding function select regis-
ters A, B and C)
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer •When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
143
Figure 1.14.11. Timer Ai mode register in one-shot timer mode
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3 0 (Set to “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select register
Trigger select bit
External trigger select bit 0 : Falling edge of TAi
IN
pin's input signal (Note 2)
1 : Rising edge of TAi
IN
pin's input signal (Note 2)
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).
WR
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
This bit is invalid in M32C/80 series.
Port output control is set by the function select registers A, B and C. – –
Timer Ai mode register (i = 0 to 4) (One-shot timer mode)
Symbol Address When reset
TAiMR(i=0 to 4) 0356
16
, 0357
16
, 0358
16
, 0359
16
, 035A
16
00000X00
2
(Note 1)
(Note 3)
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development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
144
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure
1.14.12 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.13 shows the
example of how a 16-bit pulse width modulator operates. Figure 1.14.14 shows the example of how an 8-
bit pulse width modulator operates.
Table 1.14.5. Timer specifications in pulse width modulation mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation
•The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•The timer reloads a new count at a rising edge of PWM pulse and continues counting
•The timer is not affected by a trigger that occurs when counting
16-bit PWM •High level width n / fi n : Set value
•Cycle time (216-1) / fi fixed
8-bit PWM
•
High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
•Cycle time (28-1) (m+1) / fi m:values set to timer Ai register’s low-order address
Count start condition •External trigger is input
•The timer overflows
•The count start flag is set (= 1)
Count stop condition •The count start flag is reset (= 0)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function
Pulse output (TAi
OUT
is selected by corresponding function select registers A, B and C)
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer •When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
•When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
145
Bit name
Timer Ai mode register (i = 0 to 4) (Pulse width modulator mode)
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : Pulse width modulator (PWM) mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
WR
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select bit
0: Falling edge of TAi
IN
pin's input signal (Note 2)
1: Rising edge of TAi
IN
pin's input signal (Note 2)
0: Count start flag is valid
1: Selected by event/trigger select register
Note 1: Valid only when the TA
iIN
pin is selected by the event/trigger select bit
(addresses 0342
16
and 0343
16
). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F
16
).
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
This bit is invalid in M32C/80 series.
Port output control is set by the function select registers A, B and C.
––
Symbol Address When reset
TAiMR(i=0 to 4) 0356
16
, 0357
16
, 0358
16
, 0359
16
, 035A
16
00000X00
2
(Note 3)
(Note 1)
Figure 1.14.12. Timer Ai mode register in pulse width modulation mode
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
146
1 / f
i
X
(2 – 1)
16
Count source
TA
iIN
pin
input signal
PWM pulse output
from TA
iOUT
pin
Condition : Reload register = 0003
16
, when external trigger
(rising edge of TA
iIN
pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
2n
, f
C32
)
Note: n = 0000
16
to FFFE
16
.
1 / f
i
X
n
Count source (Note1)
TAiIN pin input signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TAiOUT pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleaerd by software
fi : Frequency of count source
(f1, f8, f2n, fC32)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 – 1)
8
1 / fi X (m + 1) X n
1 / fi X (m + 1)
Figure 1.14.13. Example of how a 16-bit pulse width modulator operates
Figure 1.14.14. Example of how an 8-bit pulse width modulator operates
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
147
Timer B
Figure 1.15.1 shows the block diagram of timer B. Figures 1.15.2 and 1.15.4 show the timer B-related
registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 1.15.1. Block diagram of timer B
Figure 1.15.2. Timer B-related registers (1)
Clock source selection
(address 034016)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16)
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f1
f8
f32
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Can be selected in only
event counter mode
Count start flag
fC32
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
Counter reset circuit
Counter (16)
TBi Address TBj
Timer B0 035116 035016 Timer B2
Timer B1 035316 035216 Timer B0
Timer B2 035516 035416 Timer B1
Timer B3 031116 031016 Timer B5
Timer B4 031316 031216 Timer B3
Timer B5 031516 031416 Timer B4
Note 1: Read and write data in 16-bit units.
Note 2: Counts external pulses input or a timer overflow.
Timer Bi register
(i = 0 to 6) (Note 1)
Symbol Address When reset
TBi (i = 0 to 2) 0351
16
,0350
16
, 0353
16
,0352
16
, 0355
16
,0354
16
Indeterminate
TBi (i = 3 to 5) 0311
16
,0310
16
, 0313
16
,0312
16
, 0315
16
,0314
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
WR
Timer mode
Function
Values that can be set
Event counter mode
Pulse period / pulse width
measurement mode
0000
16
to FFFF
16
0000
16
to FFFF
16
16-bit counter (set to dividing ratio)
16-bit counter (set to dividing ratio)
Measures a pulse period or width
(Note 2)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
148
Figure 1.15.3. Timer B-related registers (2)
Timer Bi mode register
(i = 0 to 5)
Symbol Address When reset
TBiMR(i=0 to 5) 035B
16
, 035C
16
, 035D
16
, 031B
16
, 031C
16
, 031DB
16
00XX0000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Don't set it up
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each
operation mode
Count source
select bit
Operation mode
select bit
Function varies with each
operation mode
Note 1: Bit 4 is valid only by timer B0 and timer B3.
Note 2: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
(Note 1)
(Note 2)
Symbol Address When reset
TABSR 034016 0016
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count
start flag
Timer B1 count
start flag
Timer B0 count
start flag
Timer A4 count
start flag
Timer A3 count
start flag
Timer A2 count
start flag
Timer A1 count
start flag
Timer A0 count
start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
149
Symbol Address When reset
CPSRF 034116 0XXXXXXX2
Clock prescaler reset flag
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Clock prescaler reset flag 0 : Ignored
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
When write, set “0”. When read, their contents are
indeterminate.
A
A
A
A
Symbol Address When reset
TBSR 0300
16
000XXXXX
2
Timer B3, B4,B5 count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B5 count
start flag
Timer B4 count
start flag
Timer B3 count
start flag
TB5S
TB4S
TB3S 0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Figure 1.15.4. Timer B-related registers (3)
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development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
150
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.15.1.) Figure 1.15.5
shows the timer Bi mode register in timer mode.
Table 1.15.1. Timer specifications in timer mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation •Counts down
•When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(m+1)m : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer •When counting stopped
When a value is written to timer Bi register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Figure 1.15.5. Timer Bi mode register in timer mode
Timer Bi mode register (i = 0 to 5) (Timer mode)
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode.
Can be “0” or “1”.
MR2
MR1
MR3
0 0 : f1
0 1 : f8
1 0 : f2n
1 1 : fC32
TCK1
TCK0 Count source select bit
Nothing is assigned. (i = 1, 2, 4, 5)
When write, set "0". When read, its content is indeterminate.
0 (Set to “0” in timer mode)
b7 b6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Symbol Address When reset
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX00002
Note 1: R/W is valid only in timer B0 and timer B3.
Note 2: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 3: n = 0 to 15. n is set by the count source prescaler register (address 035F16).
(Note 3)
(Note 1)
Invalid in timer mode. When write, set "0". When read in timer
mode, its content is indeterminate.
(Note 2)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
151
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.15.2.)
Figure 1.15.6 shows the timer Bi mode register in event counter mode.
Table 1.15.2. Timer specifications in event counter mode
Item Specification
Count source •External signals input to TBiIN pin
Effective edge of count source can be a rising edge, a falling edge, or falling and
rising edges as selected by software
• TBj overflows or underflows
Count operation •Counts down
•When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function
Count source input (Set the corresponding function select register A to I/O port.)
Read from timer Count value can be read out by reading timer Bi register
Write to timer •When counting stopped
When a value is written to timer Bi register, it is written to both reload register and
counter
•When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register (i = 0 to 5) (Event counter mode)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
Operation mode
select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit
MR2
MR1
MR3
Nothing is assigned. (i = 1, 2, 4, 5)
When write, set “0”. When read, its content is indeterminate.
TCK1
TCK0
0 0 : Counts external signal's falling edges
0 1 : Counts external signal's rising edges
1 0 : Counts external signal's falling and
rising edges
1 1 : Inhibited
b3 b2
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: R/W is valid only in timer B0 and timer B3.
Note 3: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 4: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 5: j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3.
Invalid in event counter mode.
Can be “0” or “1”.
Event clock select bit 0 : Input from TBiIN pin
1 : TBj overflow
0 (Set to “0” in event counter mode)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Symbol Address When reset
TBiMR(i=0 to 5) 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX00002
(Note 1)
(Note 3)
(Note 4)
(Note 5)
Invalid in event counter mode. When write, set "0". When
read in event counter mode, its content is indeterminate.
(Note 2)
Figure 1.15.6. Timer Bi mode register in event counter mode
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development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
152
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.15.3.)
Figure 1.15.7 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.15.8 shows the operation timing when measuring a pulse period. Figure 1.15.9 shows the operation
timing when measuring a pulse width.
Table 1.15.3. Timer specifications in pulse period/pulse width measurement mode
Item Specification
Count source f1, f8, f2n, fC32
Count operation • Count up
•Counter value “000016” is transferred to reload register at measurement pulse's
effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
•When measurement pulse's effective edge is input (Note 1)
•When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value
is written to the timer Bi mode register.)
TBiIN pin function Measurement pulse input (Set the corresponding function select register A to I/O port.)
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started
counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input
after the timer.
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
153
Timer Bi mode register (i = 0 to 5) (Pulse period / pulse width measurement mode)
Bit nameBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR2
MR1
MR3
TCK1
TCK0
0 0 : Pulse period measurement 1
0 1 : Pulse period measurement 2
1 0 : Pulse width measurement
1 1 : Must not be set
Function
b3 b2
Count source
select bit
Timer Bi overflow
flag 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
b7 b6
0 (Set to “0” in pulse period/pulse width measurement mode)
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
Note 1: Do the next measurement, In the measurement mode select bit.
Pulse period measurement 1(bit 3, bit 2=“0 0”) : Interval between measurement pulse's falling edge to falling edge.
Pulse period measurement 2(bit 3, bit 2=“0 1”) : Interval between measurement pulse's rising edge to rising edge.
Pulse width measurement (bit 3, bit 2=“1 0”) : Interval between measurement pulse's falling edge to rising edge,
and between rising edge to falling edge.
Note 2: R/W is valid only in timer B0 and timer B3.
Note 3: In timer B1, timer B2, timer B4 and timer B5, nothing is assigned by bit 4(There is not R/W).
When write, set “0”. When read, its content is indeterminate.
Note 4: It is indeterminate when reset.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 5: n = 0 to 15. n is set by the count source prescaler register (address 035F
16
).
Symbol Address When reset
TBiMR(i=0 to 5) 035B
16
, 035C
16
, 035D
16
, 031B
16
, 031C
16
, 031D
16
00XX0000
2
(Note 4)
(Note 1)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
When write, set "0". When read, its content is indeterminate.
(Note 2)
(Note 5)
Figure 1.15.7. Timer Bi mode register in pulse period/pulse width measurement mode
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
154
Measurement pulse “H”
Count source
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
Timer Bi overflow flag “1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1)
Cleared to “0” when interrupt request is accepted, or cleared by software.
(Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
Count source
Measurement pulse
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
When measuring measurement pulse time interval from falling edge to falling edge
(Note 2)
Cleared to “0” when interrupt request is accepted, or cleared by software.
Transfer
(measured value)
“1”
Reload register counter
transfer timing
Figure 1.15.8. Operation timing when measuring a pulse period
Figure 1.15.9. Operation timing when measuring a pulse width
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155
Three-phase motor control timers’ functions
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms.
Figures 1.16.1 through 1.16.5 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0 (Note 4)
Symbol Address When reset
INVC0 0308
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Effective interrupt output
polarity select bit
INV00
Bit symbol Bit name Description RW
INV01
Effective interrupt output
specification bit
INV02 Mode select bit
INV04 Positive and negative
phases concurrent L output
disable function enable bit
INV07 Software trigger bit
INV06 Modulation mode select
bit
INV05 Positive and negative
phases concurrent L output
detect flag
INV03 Output control bit
0: A timer B2 interrupt occurs when the
timer A1 reload control signal is “1”.
1: A timer B2 interrupt occurs when the
timer A1 reload control signal is “0”.
0: Not specified.
1: Selected by the INV00 bit.
0: Normal mode
1: Three-phase PWM output mode
0: Output disabled
1: Output enabled
0: Feature disabled
1: Feature enabled
0: Not detected yet
1: Already detected
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
0: Ignored
1: Trigger generated
(Note 6)
(Note 7)
(Note 3)
(Note 3)
(Note 8)
(Note 5)
(Note 2)
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Set bit 1 of this register to “1” after setting timer B2 interrupt occurrences frequency set counter.
Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = “1”).
Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,
and the timer B2 interrupt frequency set circuit works.
For U, U, V, V, W and W output from P8
0
, P8
1
, and P7
2
through P7
5
, setting of function select registers A, B and
C is required.
Note 5: No value other than “0” can be written.
Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the
three-phase buffer register to the three-phase output shift register is made only once in synchronization with the
transfer trigger signal after writing to the three-phase output buffer register.
Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger
signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is
made with respect to every transfer trigger.
Note 8: The value, when read, is “0”.
(Note 4)
Figure 1.16.1. Registers related to timers for three-phase motor control
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Three-phase PWM control register 1 (Note 1)
Symbol Address When reset
INVC1 0309
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Timer Ai start trigger signal
select bit
INV10
Bit symbol Bit name Description
RW
INV11
Timer A1-1, A2-1, A4-1
control bit
INV12 Dead time timer count
source select bit
INV14 Output polarity control bit
INV17 Waveform reflect timing
select bit
INV16 Dead time timer trigger
select bit
INV15 Dead time invalid bit
INV13 Carrier wave detect flag
0: Timer B2 overflow signal
1: Timer B2 overflow signal,
signal for writing to timer B2
0: Three-phase mode 0
1: Three-phase mode 1
0 : f
1
1 : f
1
/2
0: Rising edge of triangular waveform
1: Falling edge of triangular waveform
0 : Low active
1 : High active
0: Dead time valid bit
1: Dead time invalid bit
0: Triggers from corresponding timer
1: Rising edge of corresponding phase
output
0: Synchronized with raising edge of
triangular waveform
1: Synchronized with timer B2 overflow
(Note 4)
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: INV13 is valid only in triangular waveform mode (INV06=0) and three-phase mode (INV11=1).
Note 3:Usually set to “1”.
Note 4:INV17 is valid only in three-phase mode 1.
Three-phase output buffer register i (i=0, 1) (Note)
Symbol Address When reset
IDBi (i=0,1) 030A
16
, 030B
16
XX00 0000
2
Bit name Function
Bit Symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
When write, set “0”. When read, their contents are “0”.
DUi
DUBi
DVi
DWi
DVBi
DWBi
U phase output buffer i Setting in U phase output buffer i
V phase output buffer i
W phase output buffer i
U phase output buffer i
V phase output buffer i
W phase output buffer i
Setting in V phase output buffer i
Setting in W phase output buffer i
Setting in W phase output buffer i
Setting in V phase output buffer i
Setting in U phase output buffer i
Note: When executing read instruction of this register, the contents of three-phase shift register is read out.
(Note 3)
(Note 2)
Figure 1.16.2. Registers related to timers for three-phase motor control
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Dead time timer (Note)
Symbol Address When reset
DTT 030C
16
Indeterminate
Function Values that can be set
WR
b7 b0
8-bits counter (set dead time timer) 1 to 255
Note: Use MOV instruction to write to this register.
Timer B2 interrupt occurrences frequency set counter (Note 1 to 4)
Symbol Address When reset
ICTB2 030D
16
Indeterminate
Function Values that can be set
WR
b7 b0
Set occurrence frequency of timer B2
interrupt request 1 to 15
Note 1: Use MOV instruction to write to this register.
Note 2: When the effective interrupt output specification bit (INV01: bit 1 at 0308
16
) is set to “1” and three-phase
motor control timer is operating, do not rewrite to this register.
Note 3: Do not write to this register at the timing of timer B2 overflow.
Note 4: Setting of this register is valid only when bit 2 (INV02) of three-phase PWM control register 0 is set to "1".
Nothing is assigned.
When write, set to “0”.
Symbol Address When reset
TAi (i 1, 2, 4) 0349
16
,0348
16
, 034B
16
,034A
16
, 034F
16
,034E
16
Indeterminate
TAi1 (i 1, 2, 4) 0303
16
,0302
16
, 0305
16
,0304
16
, 0307
16
,0306
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
WR
0000
16
to FFFF
16
Function Values that can be set
Timer Ai, Ai-1 register (Note 1 to 3)
Note 1: Read and write data in 16-bit units.
Note 2: When set “0000
16
” to the timer Ai register, counter doesn't move, and timer Ai interrupt isn't generated.
Note 3: Use MOV instruction to write to this register.
Three-phase PWM pulse width modulator
(decide PWM output pulse width)
Symbol Address When reset
TB2 0355
16
,0354
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
WR
0000
16
to FFFF
16
Function Values that can be set
Timer B2 register (Note)
Note : Read and write data in 16-bit units.
Set the period of carrier wave
Figure 1.16.3. Registers related to timers for three-phase motor control
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PWCOM
Symbol Address When reset
TB2SC 035E16 XXXXXXX02
Timer B2 reload timing
switching bit 0 : Next underflow
1 : Synchronized rising edge of
triangular wave
Timer B2 special mode register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
WR
A
AA
Nothing is assigned.
When write, set “0”. When read, its content is “0”.
TA1TGL
Symbol Address When reset
TRGSR 034316 0016
Timer A1 event/trigger
select bit Set bit 1 and bit 0 to “0 1” before using
to the V phase output control circuit.
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
WR
TA1TGH
A
AA
A
AA
Note: Set the corresponding port function select register A to I/O port, and port direction register to “0”.
TA2TGL Timer A2 event/trigger
select bit Set bit 3 and bit 2 to “0 1” before using
to the W phase output control circuit.
TA2TGH
A
A
AA
AA
A
A
AA
AA
TA4TGL Timer A4 event/trigger
select bit Set bit 7 and bit 6 to “0 1” before using
to the U phase output control circuit.
TA4TGH
A
AA
A
AA
TA3TGL
TA3TGH
(Note)
(Note)
(Note)
Inhibited in Three-phase PWM mode.
Symbol Address When reset
TABSR 034016 0016
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Timer B2 count
start flag
Timer B1 count
start flag
Timer B0 count
start flag
Timer A4 count
start flag
Timer A3 count
start flag
Timer A2 count
start flag
Timer A1 count
start flag
Timer A0 count
start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
0 : Stops counting
1 : Starts counting
Figure 1.16.4. Registers related to timers for three-phase motor control
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Three-phase motor driving waveform output mode (three-phase PWM output mode)
Setting “1” in the mode select bit (bit 2 at 030816) shown in Figure 1.16.1 causes three-phase PWM
output mode that uses four timers A1, A2, A4, and B2. As shown in Figure 1.16.4 and 1.16.5 set timers
A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using
the respective timer mode registers.
Timer Ai mode register (i = 1, 2, 4)
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3 0 (Set to “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
1 : Selected by event/trigger select register
Trigger select bit
External trigger select bit
WR
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
AA
This bit is invalid in M32C/80 series.
Port output control is set by the function select registers A, B and C.
Symbol Address When reset
TAiMR(i=1, 2, 4) 0357
16
, 0358
16
, 035A
16
00000X00
2
Invalid in Three-phase PWM output mode.
0101
Timer B2 mode register
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode
Can be “0” or “1”
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
2n
1 1 : f
C32
TCK1
TCK0 Count source select bit
Invalid in timer mode.
When write, set “0”. When read in timer mode, its content is
indeterminate.
0 (Set to “0” in timer mode)
b7 b6
Symbol Address When reset
TB2MR 035D
16
00XX0000
2
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
000
(Note)
Note: n = 0 to 15. n is set by the count source prescaler register (address 035F
16
).
Note: n = 0 to 15. n is set by the count source prescaler register (address 035F
16
).
(Note)
Figure 1.16.5. Timer mode registers in three-phase PWM output mode
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Figure 1.16.6 shows the block diagram for three-phase waveform mode. The Low active output polarity
in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and
___ ___ ___
negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81,
P72, P73, P74, and P75 as active on the “L” level. Of the timers used in this mode, timer A4 controls the
___ ___
U phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase
___
and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1,
and A2.
In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform
___
output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U
___ ___
phase, V phase, and W phase).
To set short circuit time, use three 8-bit timers, sharing the reload register, for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (030C16), the value is written to the
reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2 at 030916). The timer can receive another
trigger again before the workings due to the previous trigger are completed. In this instance, the timer
performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the
timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to
come. ___ ___
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
___
phase, and W phase) in three-phase waveform mode are output, from respective ports by means of
setting “1” in the output control bit (bit 3 at 030816). Setting “0” in this bit causes the ports to be the high-
impedance state. This bit can be set to “0” not only by use of the applicable instruction, but by entering
_______
a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases
concurrent L output disable function enable bit (bit 4 at 030816) causes one of the pairs of U phase and
___ ___ ___
U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the output
control bit becomes the high-impedance state.
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Timer B2
(Timer mode)
Overflow Interrupt occurrence
frequency set counter Interrupt request bit
U(P80)
U(P81)
V(P72)
V(P73)
W(P74)
W(P75)
NMI
RESET R
D
D
TQ
D
TQ
D
TQ
D
TQ
For short circuit
prevention D
TQ
D
TQ
Q
INV0
3
INV0
5
Diagram for switching to P80, P81 and P72 - P75 is not shown.
INV0
4
Timer A4 counter
(One-shot timer mode)
(One-shot timer mode)
(One-shot timer mode)
Trigger
Timer A4 Reload Timer A4-1
Timer A1 counter
Trigger
Timer A1 Reload Timer A1-1
Timer A2 counter
Trigger
Timer A2 Reload Timer A2-1
INV0
7
TQINV1
1
Dead time timer setting (8)
INV0
0
1
0
INV0
1
INV1
1
DU0
DU1
T
DQ T
DQ
DUB0
DUB1
T
DQ T
DQ
U phase output control circuit
U phase output signal
U phase output signal
V phase output
control circuit
To be set to “0” when timer A4 stops
TQINV1
1
To be set to “0” when timer A1 stops
TQINV1
1
To be set to “0” when timer A2 stops
W phase output
control circuit
V phase output signal
W phase output signal
V phase output signal
W phase output signal
Signal to be
written to B2
Trigger signal for
timer Ai start
Trigger
signal for
transfer
INV1
0
Circuit for interrupt occurrence
frequency set counter
Bit 0 at 030B
16
Bit 0 at 030A
16
Three-phase output
shift register
(U phase)
A
f
1
0
1
1/2
n = 1 to 15
Reload register
Dead time timer setting (8)
n = 1 to 255
Dead time timer setting (8)
n = 1 to 255
n = 1 to 255
Trigger
INV0
6
Trigger
Trigger
Trigger
Trigger
Trigger
INV0
6
INV0
6
INV1
4
INV1
3
Figure 1.16.6. Block diagram for three-phase waveform mode
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Triangular wave modulation
To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit
(bit 6 at 030816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 030916). In this mode,
each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s con-
tent to the counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective
interrupt output specification bit (bit 1 at 030816), the frequency of interrupt requests that occur every
time the timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (030D16)
for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting;
setting ≠ 0).
Setting “1” in the effective interrupt output specification bit (bit 1 at 030816) provides the means to
choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt
request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at
030816).
An example of U phase waveform is shown in Figure 1.16.7, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16). And set “0” in DUB0 (bit 1 at 030A16). In
addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16). Also, set “0” in the
effective interrupt output specification bit (bit 1 at 030816) to set a value in the timer B2 interrupt occur-
rence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s
content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output
specification bit (bit 1 at 030816), set in the effective interrupt polarity select bit (bit 0 at 030816) and set
“1” in the interrupt occurrence frequency set counter (030D16). These settings cause a timer B2 interrupt
to occur every other interval when the U phase output goes to “H”.
When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this
instance, the content of DU1 (bit 0 at 030B16) and that of DU0 (bit 0 at 030A16) are set in the three-phase
output shift register (U phase), the content of DUB1 (bit 1 at 030B16) and that of DUB0 (bit 1 at 030A16)
___
are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected,
however, no setting is made in the shift register even though the timer B2 counter’s content becomes
000016.___
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-
___
tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase
output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time
used for setting the time over which the “L” level of the U phase waveform doesn’t overlap the Low level
___
of the U phase waveform, which has the opposite phase of the former. The U phase waveform output
that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-
shot pulses even though the three-phase output shift register’s content changes from “1” to “0” by the
effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses,
“0” already shifted in the three-phase shift register goes active, and the U phase waveform changes to
the Low level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts count-
ing the value written to timer A4-1 (030716, 030616), and starts outputting one-shot pulses. When timer
A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position,
but if the three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the
output level changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting
one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception
that the three-phase output shift register on the U phase side is used, the workings in generating a U
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Timer A4 output
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer B2
U phase
A carrier wave of triangular waveform
Carrier wave
Signal wave
U phase
output signal
Control signal for
timer A4 reload
U phase
U phase
output signal
mn nmpo
Note 1: When INV14="0" (output wave Low active)
Note 2: When INV14="1" (output wave High active)
Note 3: Set to trian
g
ular wave modulation mode and to three-
p
hase mode 1.
m
INV13(Triangular wave
modulation detect flag)
(Note 1)
(Note 2)
(Note 3)
U phase
U phase
Dead time
Dead time
Timber B2 interrupt occurres
Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
interrupt by use of the interrupt occurrences frequency
set circuit
The three-phase
shift register
shifts in
synchronization
with the falling
edge of the A4
output.
phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating
a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner
in which the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has
the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying
___ ___
the values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W
phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to
___
dealing with the U and U phases to generate an intended waveform.
Figure 1.16.7. Timing chart of operation (1)
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Timer A4 output
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer B2
U phase
Dead time
A carrier wave of triangular waveform
Carrier wave
Signal wave
Rewriting timer A4 every timer B2 interrupt occurres.
U phase
output signal
mnn
mp
o
Note: Set to triangular wave modulation mode and to three-phase mode 1.
Control signal for
timer A4 reload
m
U phase
U phase
output signal
Timer B2 interrupt occurres.
Rewriting three-phase buffer register.
Assigning certain values to DU0 (bit 0 at 030A16) and DUB0 (bit 1 at 030A16), and to DU1 (bit 0 at
030B16) and DUB1 (bit 1 at 030B16) allows you to output the waveforms as shown in Figure 1.16.8, that
___ ___
is, to output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase
alone.
Figure 1.16.8. Timing chart of operation (2)
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Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit
(bit 6 at 030816). Also, set “0” in the timers A4, A1, and A2-1 control bit (bit 1 at 030916). In this mode, the
timer registers of timers A4, A1, and of A2 comprise conventional timers A4, A1, and A2 alone, and
reload the corresponding timer register’s content to the counter every time the timer B2 counter’s con-
tent becomes 000016. The effective interrupt output specification bit (bit 1 at 030816) and the effective
interrupt output polarity select bit (bit 0 at 030816) go nullified.
An example of U phase waveform is shown in Figure 1.16.9, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16), and set “0” in DUB0 (bit 1 at 030A16). In
addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16).
When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase
buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents
of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase
buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content
becomes 000016.___
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted
one position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the
___
U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time
used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level
___
of the U phase waveform, which has the opposite phase of the former. The U phase waveform output
that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-
shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the
effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses,
0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to
the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase
buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of
___
DUB1 and DUB0 are set in the three-phase shift register (U phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-
___ ___
phase output shift register on the U phase side is used, the workings in generating a U phase waveform,
which has the opposite phase of the U phase waveform, are the same as in generating a U phase
waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which
the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the
opposite phase of the U phase waveform. The width of the “L” level can also be adjusted by varying the
___ ___
values of timer B2 and timer A4. In dealing with the V and W phases, and V and W phases, the latter are
of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and
___
U phases to generate an intended waveform.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase motor control timers’ functions
166
Timer B2
Timer A4 output
U phase
U phase
Dead time
Carrier wave
Signal wave
A carrier wave of sawtooth waveform
mnop
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Interrupt occurres.
Rewriting the value of timer A4.
U phase output
signal
U phase
output signal
The three-phase
shift registers
shifts in
synchronization
with the falling
edge of timer A4.
Data transfer is made from the three-
phase buffer registers to the three-
phase shift registers in step with the
timing of the timer B overflow.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Figure 1.16.9. Timing chart of operation (3)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase motor control timers’ functions
167
Timer B2
Timer A4 output
U phase
U phase
Dead time
Carrier wave
Signal wave
A carrier wave of sawtooth waveform
mn p
Note: Set to sawtooth modulation mode and to three-
p
hase mode 0.
U phase
output signal
U phase
output signal
The three-phase
shift registers shifts
in synchronization
with the falling
edge of timer A4.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Interrupt occurres.
Rewriting the value of timer A4.
Rewriting three-phase
output buffer register
Data transfer is made from the three-
phase buffer registers to the three-
phase shift registers in step with the
timing of the timer B overflow.
Interrupt occurres.
Rewriting the value of timer A4.
___
Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U
phase output to “H” as shown in Figure 1.16.10.
Figure 1.16.10. Timing chart of operation (4)
Under
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
168
Serial I/O
Serial I/O is configured as five channels: UART0 to UART4.
UARTi (i=0 to 4) each have an exclusive timer to generate a transfer clock, so they operate independently
of each other.
Figure 1.17.1 shows the block diagram of UARTi.
UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 036816,
02E816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O
or as a UART.
It has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin
are different in level.
Figures 1.17.2 through 1.17.8 show the registers related to UARTi.
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
169
ni : Values set to UARTi bit rate generator (UiBRG)
RxDi
Reception
control circuit
Transmission
control circuit
1 / (ni+1)
1/16
1/16
1/2
Bit rate
generator
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLKi
CTSi / RTSi
f
1
f
8
f
2n
Vcc
RTS2
CTS2
TxDi
RxD polarity
reversing circuit TxD
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
CLK
polarity
reversing
circuit
Internal
External
Clock source selection Transmit/
receive
unit (Note)
Note :UART 2 is not CMOS output but N channel open drain output.
SP SP
PAR
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxDi
UARTi transmit register
PAR
disabled
PAR
enabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0UARTI transmit buffer
register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits) UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxDi
UART
(8 bits)
UART
(9 bits)
Address 036E16
Address 036F16
Address 02EE16
Address 02EF16
Address 033E16
Address 033F16
Address 032E16
Address 032F16
Address 02FE16
Address 02FF16
Address 036A16
Address 036B16
Address 02EA16
Address 02EB16
Address 033A16
Address 033B16
Address 032A16
Address 032B16
Address 02FA16
Address 02FB16
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
“0”
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP : Stop bit
PAR : Parity bit
i : 0 to 4
Figure 1.17.1. Block diagram of UARTi
Under
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
170
UARTi transmit buffer register (i=0 to 4) (Note)
Symbol Address When reset
UiTB(i=0,1,2) 036B
16
, 036A
16
, 02EB
16
, 02EA
16
, 033B
16
, 033A
16
Indeterminate
UiTB(i=3,4) 032B
16
, 032A
16
, 02FB
16
, 02FA
16
Indeterminate
RW
Function
(Clock synchronous serial I/O mode)
Transmit data Transmit data
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Function
(UART mode)
Transmit data (9th bit)
Note: Use MOV instruction to write to this register.
b7 b0
b15
(b7) b8
(b0)
Bit
symbol
UARTi receive buffer register (i = 0 to 4)
Bit name
Bit
symbol
Symbol Address When reset
UiRB(i=0,1,2) 036F16,036E16, 02EF16,02EE16, 033F16,033E16 Indeterminate
UiRB(i=3,4) 032F16,032E16, 02FF16,02FE16 Indeterminate
RW
Note 1: Arbitration lost detecting flag must always write "0".
Note 2: Bits 15 through 12 are set to 0002 when the serial I/O mode select bit (bits 2 to 0 at addresses 036816,
02E816, 033816, 032816, 02F816) are set to "000
2
" or the receive enable bit is set to "0".
(Bit 15 is set to "0" when bits 14 to 12 all are set to "0".)
Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses
036E16, 02EE16, 033E16, 032E16, 02FE16) is read.
Receive data Receive data
ABT
OER
FER
SUM
Function
(Clock synchronous
serial I/O mode)
PER
Function
(UART mode)
Overrun error flag
(Note 2)
Arbitration lost
detecting flag
(Note 1)
Framing error flag
(Note 2)
Parity error flag
(Note 2)
(Note 2)
Error sum flag
Receive data
(9th bit)
0: Not detectet
1: Detected
0: No overrun error
1: Overrun error found
Invalid
Invalid
0: No overrun error
1: Overrun error found
0: No framing error
1: Framing error found
0 : N o parity error
1 : P arity error found
0: No error
1: Error found
Invalid
Invalid
b7 b0
b15
(b7) b8
(b0)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Figure 1.17.2. Serial I/O-related registers (1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
171
Function
UARTi bit rate generator (i=0 to 4) (Note 1, 2)
Values that can be set
Symbol Address When reset
UiBRG(i=0 to 4) 0369
16,
02E9
16,
0339
16,
0329
16,
02F9
16
Indeterminate
RW
Assuming that set value = n, BRGi divides
the count source by n+1 00
16
to FF
16
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
b7 b0
UARTi transmit/receive mode register
(i=0 to 4)
Symbol Address When reset
UiMR(i=0 to 4) 0368
16,
02E8
16,
0338
16,
0328
16,
02F8
16
00
16
RW
CKDIR
STPS
PRY
IOPOL
PRYE
SMD0
SMD2
SMD1 Serial I/O mode
select bit
Internal/external
clock select bit
Stop bit length
select bit
Odd/even parity
select bit
Parity enable bit
TxD,RxD input/
output polarity
switch bit
0 0 0: Serial I/O invalid
0 0 1:
Serial I/O mode
0 1 0: I2C mode
b2 b1 b0
Must not be set
except above
0 0 0: Serial I/O invalid
1 0 0: Transfer data 7 bits long
1 0 1: Transfer data 8 bits long
1 1 0: Transfer data 9 bits long
b2 b1 b0
0 : Internal clock
1 : External clock
(Note 2)
(Note 1)
(Note 2)
Invalid
Invalid
Invalid
0: No reversed
1: Reversed
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
(Note 3)
Note 1: Select CLK output by the corresponding function select registers A, B and C.
Note 2: Set the corresponding function select register A to the I/O port.
Note 3: Normally set "0".
0 : Internal clock
1 : External clock
Bit name
Bit
symbol Function
(Clock synchronous
serial I/O mode) Function
(UART mode)
Must not be set
except above
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.17.3. Serial I/O-related registers (2)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
172
UARTi transmit/receive control register 0
(i=0 to 4)
Symbol Address When reset
UiC0(i=0 to 4) 036C
16,
02EC
16,
033C
16,
032C
16,
02FC
16
08
16
RW
TXEPT
CRD
NCH
(Note 3)
UFORM
CKPOL
b1 b0
CLK0
CRS
CLK1
BRG count source
select bit
CST/RTS function
select bit
Transmit register
empty flag
CTS/RTS disable
bit
Data output select
bit
CLK polarity
select bit
Transfer format
select bit (Note 4)
(Note 2)
(Note 1)
Valid when bit 4 = “0”
0 : CTS function is selected
1 : RTS function is selected
0 0: f1 is selected
0 1: f8 is selected
1 0: f2n is selected
1 1: Must not be set
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel open drain output
0 : Transmit data is output
at falling edge of transfer
clock and receive data
is input at rising edge
1 : Transmit data is output
at rising edge of transfer
clock and receive data
is input at falling edge
0 : LSB first
1 : MSB first
Set to “0”
Bit name
Bit
symbol Function
(Clock synchronous
serial I/O mode) Function
(UART mode)
Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”
Note 2: Select RTS output using the corresponding function select registers A, B and C.
Note 3: UART2 transfer pin (TxD2:P70) is N-channel open drain output. It is not set to CMOS output.
Note 4: Valid only in clock syncronous serial I/O mode and 8 bits UART mode.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.17.4. Serial I/O-related registers (3)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
173
UARTi transmit/receive control register 1
(i=0 to 4)
Symbol Address When reset
UiC1(i=0 to 4) 036D
16,
02ED
16,
033D
16,
032D
16,
02FD
16
02
16
RW
RI
UiIRS
UiRRM
UiLCH
TE
RE
TI
Transmit
enable bit
Transmit buffer
empty flag
Receive
enable bit
Receive
complete flag
Clock divide
synchronizing stop bit
/e
rror signal output
enable bit
SCLKSTPB
/UiERE
UARTi transmit
interrupt cause
select bit
UARTi
continuous
receive mode
enable bit
Data logic
select bit
0: Transmission disabled
1: Transmission enabled
0: Data present in transmit buffer register
0: No data present in transmit buffer register
0: Reception disabled
1: Reception enabled
0: Data present in receive buffer register
0: No data present in receive buffer register
0: Transmit buffer empty (TI = 1)
1: Transmit is completed (TXEPT = 1)
Set to “0”
0: Continuous receive
mode disabled
1: Continuous receive
mode enabled
0: No reverse
1: Reverse
Clock divide synchronizing stop bit
0:
Synchronizing
stop
1: Synchronous start (Note)
Note :When this bit and bit 7 of UARTi special mode register 2 are set, clock synchronizing function is used.
Bit name
Bit
symbol Function
(Clock synchronous
serial I/O mode) Function
(UART mode)
Set to “0”
b7 b6 b5 b4 b3 b2 b1 b0
UARTi special mode register (i=0 to 4)
Symbol Address When reset
UiSMR(i=0 to 4) 0367
16,
02E7
16,
0337
16,
0327
16,
02F7
16
00
16
RW
LSYN
ABSCS
ACSE
SSS
IICM
BBS
ABC
0: Normal mode
1: IIC mode
0: Update per bit
1: Update per byte
0: STOP condition
detected
1: START condition
detected
0: Disabled
1: Enabled
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
0: Ordinary
1: Falling edge of RxDi
0: Rising edge of transfer clock
1: Underflow signal of timer Ai
(Note 2)
Bit name
Bit
symbol Function
(Clock synchronous
serial I/O mode) Function
(UART mode)
IIC mode
select bit
Bus busy flag
Note 1: Nothing but "0" may be written.
Note 2: UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal,
UART3: timer A3 underflow signal, UART4: timer A4 underflow signal.
Note 3: When this bit and bit 7 of UARTi transmit/receive control register 1 are set, clock synchronizing
function is used.
Auto clear function
select bit of transmit
enable bit
SCLL sync
output enable
bit
Arbitration lost
detecting flag
control bit
Bus collision
detect sampling
clock select bit
Transmit start
condition
select bit
0: No auto clear function
1: Auto clear at
occurrence of bus
(Note 1)
SCLKDIV Clock divide
set bit 0: Divided-by-2
1: No divided
(Note 3)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.17.5. Serial I/O-related registers (4)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
174
UARTi special mode register 2 (i=0 to 4)
Symbol Address When reset
UiSMR2(i=0 to 4) 0366
16,
02E6
16,
0336
16,
0326
16,
02F6
16
00
16
RW
ALS
STC
SWC2
SDHI
IICM2
SWC
CSC Clock
synchronous bit
IIC mode select
bit 2
SCL wait output bit
SDA output stop bit
UARTi initialize bit
SCL wait output
bit 2
SDA output inhibit
bit
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: Disabled
1: Enabled
0: UARTi clock
1: 0 output
0: Disabled
1: Enabled (high impedance)
Bit name
Bit
symbol Function
0: NACK/ACK interrupt (DMA source - ACK)
Transfer to receive buffer at the rising
edge of last bit of receive clock
Receive interrupt occurs at the rising edge
of last bit of receive clock
1: UART transfer/receive interrupt (DMA
source - UART receive)
Transfer to receive buffer at the falling
edge of last bit of receive clock
Receive interrupt occurs at the falling
edge of last bit of receive clock
SU1HIM Clock divide
synchronizing
enable bit
0: Synchronous disabled
1: Synchronous enabled
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.17.6. Serial I/O-related registers (5)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
175
UARTi special mode register 3 (i=0 to 4)
Symbol Address When reset
UiSMR3(i=0 to 4) 0365
16,
02E5
16,
0335
16,
0325
16,
02F5
16
00
16
RW
NODC
ERR
DL0
DL1
SSE
DINC
CKPH
DL2
(Note 4)
SS port function
enable bit
Clock phase
set bit
Serial input port
set bit
Clock output
select bit
Fault error flag
SDAi(TxDi) digital
delay time set bit
(Note 1) 0: SS function disabled
1: SS function enabled
0: Without clock delay
1: With clock delay
0: Select TxDi and RxDi (master mode)
0: Select STxDi and SRxDi (slave mode)
0: CLKi is CMOS output
1: CLKi is N-channel open drain output
0: Without fault error
1: With fault error
000 :Without delay
001 :2-cycle of BRG count source
010 :3-cycle of BRG count source
011 :4-cycle of BRG count source
100 :5-cycle of BRG count source
101 :6-cycle of BRG count source
110 :7-cycle of BRG count source
111 :8-cycle of BRG count source
b7 b6 b5
(Note 2)
(Note 3)
(Note 5,6)
Bit name
Bit
symbol Function
Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control
register 0) to "1".
Note 2: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the
RxDi function select register A for input/output port and the port direction register to "0".
Note 3: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and
SRxDi function select register A for input/output port and the port direction register to "0".
Note 4: Nothing but "0" may be written.
Note 5: These bits are used for SDAi (TxDi) output digital delay when using UARTi for IIC interface.
Otherwise, must set to "000".
Note 6: When external clock is selected, delay is increased approximately 100ns.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.17.7. Serial I/O-related registers (6)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
176
UARTi special mode register 4 (i=0 to 4)
Symbol Address When reset
UiSMR4(i=0 to 4) 0364
16,
02E4
16,
0334
16,
0324
16,
02F4
16
00
16
RW
Start condition
generate bit
Restart condition
generate bit
Stop condition
generate bit
SCL, SDA output
select bit
ACK data bit
ACK data output
enable bit
(Note)
0: Clear
1: Start
0: Clear
1: Start
0: Clear
1: Start
0: Ordinal block
1: Start/stop condition generate block
0: ACK
1: NACK
Bit name
Bit
symbol Function
Note :When start condition is generated, these bits automatically become "0".
SCL wait output
bit 3
SCL output stop
enable bit
0: SCL "L" hold disabled
1: SCL "L" hold enabled
0: Disabled
1: Enabled
0: SI/O data output
1: ACKD output
(Note)
(Note)
STSPSEL
ACKD
ACKC
SCLHI
STAREQ
STPREQ
RSTAREQ
SWC9
b7 b6 b5 b4 b3 b2 b1 b0
External interrupt request cause select register
Bit name Function
Bit symbol WR
Symbol Address When reset
IFSR 031F
16
00
16
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
A
A
INT0 interrupt polarity
select bit (Note) 0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
select bit (Note)
INT2 interrupt polarity
select bit (Note)
INT3 interrupt polarity
select bit (Note)
INT4 interrupt polarity
select bit (Note)
INT5 interrupt polarity
select bit (Note) 0 : One edge
1 : Both edges
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note :When level sense is selected, set this bit to "0".
When both edges are selected, set the corresponding polarity switching bit of INT interrupt control
register to "0" (falling edge).
0 : UART3 bus collision /start,stop
detect/false error detect
1 : UART0 bus collision /start,stop
detect/false error detect
UART0/3 interrupt
cause select bit
UART1/4 interrupt
cause select bit
IFSR6
IFSR7
A
A
A
A
0 : UART4 bus collision /start,stop
detect/false error detect
1 : UART1 bus collision /start,stop
detect/false error detect
Figure 1.17.8. Serial I/O-related registers (7)
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(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.18.1
and 1.18.2 list the specifications of the clock synchronous serial I/O mode.
Table 1.18.1. Specifications of clock synchronous serial I/O mode (1/2)
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • When internal clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 = “0”) : fi/ 2(m+1) (Note 1) fi = f1, f8, f2n(Note 2)
_ CLK is selected by the corresponding peripheral function select register A, B and C.
• When external clock is selected (bit 3 at addresses 036816, 02E816, 033816 , 032816,
02F816= “1”) : Input from CLKi pin
_Set the corresponding function select register A to I/O port
Transmission/reception control
_______ _______ _______ _______
• CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 036D16, 02ED16, 033D16, 032D16, 02FD16) = “0”
_______ _______
_ When CTS function selected, CTS input level = “L”
_
TxD output is selected by the corresponding peripheral function select register A, B and C.
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “1”: CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_
Transmit enable bit (bit 0 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “1”: CLKi input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi trans-
fer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi
transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to UARTi
receive buffer register is completed
Interrupt request
generation timing
Note 1: “m” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
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Clock synchronous serial I/O mode
178
Pin name Function Method of selection
TxDi
(P63, P67, P70,
P92, P96)
Serial data output
(Note 1)
Serial data input
(Note 2)
Transfer clock output
(Note 1)
Transfer clock input
(Note 2)
Programmable I/O port
(Note 2)
(Outputs dummy data when performing reception only)
RxDi
(P62, P66, P71,
P91, P97)
CLKi
(P61, P65, P72,
P90, P95)
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “0”
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = “0”
Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) =“0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
CTS input
(Note 2)
RTS output (Note 1)
CTSi/RTSi
(P60, P64, P73,
P93, P94)
Item Specification
Error detection • Overrun error (Note)
This error occurs when the next data is started to receive and 6.5 transfer clock is
elapsed before UARTi receive buffer register are read out.
Select function • CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
•Reversing serial data logic
Whether to reverse data in writing to the transmission buffer register or reading the
reception buffer register can be selected.
• TxD, RxD I/O polarity reverse
This function is reversing TxD port output and RxD port input. All I/O data level is
reversed.
Note : If an overrun error occurs, the UARTi receive buffer will have the next data written in.
Table 1.18.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note
that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin
outputs a “H”. (If the N-channel open drain is selected, this pin is in floating state.)
Table 1.18.3. Input/output pin functions in clock synchronous serial I/O mode
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C.
Note 2: Select I/O port by the corresponding function select register A.
Table 1.18.2. Specifications of clock synchronous serial I/O mode (2/2)
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Clock synchronous serial I/O mode
179
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(m + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
2n
)
m: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Stopped pulsing because CTS = “H”
Transferred from UARTi transmit buffer register to UARTi transmit register
Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
The following conditions are met when the CLKi
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
1 / fEXT
D0D1D2D3D4D5D6D7D0D1D2D3D4D5D0D1D2D3D4D5
D7
D6
Over run error
flag(OER)
D
“0”
“1”
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
Figure 1.18.1. Typical transmit/receive timings in clock synchronous serial I/O mode
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Clock synchronous serial I/O mode
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• When CLK polarity select bit = “1”
Note 2: The CLK pin level when not
transferring data is “L”.
D1D2D3D4D5D6D7
D1D2D3D4D5D6D7
D0
D0
TXDi
RXDi
CLKi
• When CLK polarity select bit = “0”
Note 1: The CLK pin level when not
transferring data is “H”.
D1D2D3D4D5D6D7D0
D1D2D3D4D5D6D7D0
TXDi
RXDi
CLKi
LSB first
• When transfer format select bit = “0”
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
i
R
X
D
i
CLK
i
• When transfer format select bit = “1”
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
i
R
X
D
i
CLK
i
MSB first
Note: This applies when the CLK polarity select bit = “0”.
(a) Polarity select function
As shown in Figure 1.18.2, the CLK polarity select bit (bit 6 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) allows selection of the polarity of the transfer clock.
Figure 1.18.2. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.18.3, when the transfer format select bit (bit 7 at addresses 036C16, 02EC16,
033C16, 032C16, 02FC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format
is “MSB first”.
Figure 1.18.3. Transfer format
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D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxDi
(no reverse)
TxDi
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
•When LSB first
(c) Continuous receive mode
If the continuous receive mode enable bit (bit 5 at address 036D16, 02ED16, 033D16, 032D16,
02FD16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive
buffer register is read out, the unit simultaneously goes to a receive enable state without having to set
dummy data back to the transmit buffer register again.
(d) Serial data logic switch function
When the data logic select bit (bit6 at address 036D16, 02ED16, 033D16, 032D16, 02FD16) = “1”, and
writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure
1.18.4 shows the timing example of serial data logic switch.
Figure 1.18.4. Timing for switching serial data logic
Clock asynchronous serial I/O (UART) mode
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Item Specification
Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock • When internal clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 = “0”) : fi/16(m+1) (Note 1) fi = f1, f8, f2n
• When external clock is selected (bit 3 at addresses 036816, 02E816, 033816, 032816,
02F816 =“1”) : fEXT/16(m+1)(Note 1, 2)
Transmission/reception control
_______ _______ _______ _______
• CTS function, RTS function, CTS/RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 036D
16
, 02ED
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
- Transmit buffer empty flag (bit 1 at addresses 036D16, 02ED16, 033D16, 032D16,
02FD16) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
-
TxD output is selected by the corresponding peripheral function select register A, B
and C.
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 036D 16, 02ED16, 033D16, 032D16, 02FD16) = “1”
- Start bit detection
Interrupt request • When transmitting
generation timing - Transmit interrupt cause select bits (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi transfer
buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bit 4 at address 036D16, 02ED16, 033D16,
032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi
transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to UARTi
receive buffer register is completed
Error detection • Overrun error (Note 3)
This error occurs when the next data is started to receive and 6.5 transfer
clock is elapsed before UARTi receive buffer register are read out.
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.1 and 1.19.2 list the specifications of the UART mode. Figure 1.19.1 shows the
UARTi transmit/receive mode register.
Table 1.19.1. Specifications of UART Mode (1/2)
Note 1: ‘m’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will be over written with the next data.
Clock asynchronous serial I/O (UART) mode
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183
Pin name Function Method of selection
Serial data output
(Note 1)
Serial data input
(Note 2)
Programmable I/O port
(Note 2)
Transfer clock input
(Note 2)
Programmable I/O port
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “0”
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bits 0 and 5 at address 03C716) = “0”
Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) =“0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
CTS input
(Note 2)
RTS output
TxDi
(P63, P67, P70,
P92, P96)
RxDi
(P62, P66, P71,
P91, P97)
CLKi
(P61, P65, P72,
P90, P95)
CTSi/RTSi
(P60, P64, P73,
P93, P94)
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) = “1”
(Note 1)
(Note 2)
Table 1.19.2. Specifications of UART Mode (2/2)
Item Specification
Error detection • Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
If parity is enabled this error occurs when, the number of 1’s in parity and character
bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encoun-
tered
Select function •Serial data logic switch
This function reveres the logic value of transferring data. Start bit, parity bit and stop
bit are not reversed.
•TxD, RxD I/O polarity switch
This function reveres the TxD port output and RxD port input. All I/O data level is
reversed.
Table 1.19.3 lists the functions of the input/output pins in UART mode. Note that for a period from when
the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open drain is selected, this pin is in floating state.)
Table 1.19.3. Input/output pin functions in UART mode
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C.
Note 2: Select I/O port by the corresponding function select register A.
Clock asynchronous serial I/O (UART) mode
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Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
Start
bit Parity
bit
TxDi
CTSi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (m + 1) / fi or 16 (m + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
2n
)
f
EXT
: frequency of BRGi count source (external clock)
m : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (m + 1) / fi or 16 (m + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
2n
)
f
EXT
: frequency of BRGi count source (external clock)
m : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Tc
Transfer clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SP ST PSP D
0
D
1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Data is set in UARTi transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST SP
D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST D
8
D
0
D
1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit Stop
bit
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 1.19.1. Typical transmit timings in UART mode
Clock asynchronous serial I/O (UART) mode
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ST : Start bit
P : Even parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxD
i
(no reverse)
TxD
i
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
• When LSB first, parity enabled, one stop bit
Figure 1.19.3. Timing for switching serial data logic
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
D
0
Start bit
Sampled “L”Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Receive interrupt
request bit “0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D
7
D
1
Cleared to “0” when interrupt request is accepted, or cleared by software
Becomes “L” by reading the receive buffer
Figure 1.19.2. Typical receive timing in UART mode
(a) Function for switching serial data logic
When the data logic select bit (bit 6 of address 036D16, 02ED16, 033D16, 032D16, 02FD16) is assigned
1, data is inverted in writing to the transmission buffer register or reading the reception buffer register.
Figure 1.19.3 shows the example of timing for switching serial data logic.
Clock asynchronous serial I/O (UART) mode
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ST : Start bit
SP : Stop bit
ST
ST
SP
SP
Transfer clock
TxDi
RxDi
Bus collision detection
interrupt request signal
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
(b) TxD, RxD I/O polarity reverse function
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
normal use.
(c) Bus collision detection function
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.19.4
shows the example of detection timing of a bus collision (in UART mode).
UART0 and UART3 are allocated to software interrupt number 40. UART1 and UART4 are allocated
to software interrupt number 41. When selecting UART 0, 3, 1 or 4 bus collision detect function, bit 6
or 7 of external interrupt cause select register (address 031F16) must be set.
Figure 1.19.4. Detection timing of a bus collision (in UART mode)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
187
UARTi Special Mode Register
UARTi (i=0 to 4) operate the IIC bus interface (simple IIC bus) using the UARTi special mode register
(addresses 036716, 02E716, 033716, 032716 and 02F716) and UARTi special mode register 2 (addresses
036616, 02E616, 033616, 032616 and 02F616). UARTi add special functions using UARTi special mode
resister 3 (addresses 036516, 02E516, 035516, 032516 and 02F516).
(1) IIC Bus Interface Mode
The I2C bus interface mode is provided with UARTi.
Table 1.21.1 shows the construction of the UARTi special mode register and UARTi special mode regis-
ter 2.
When the I2C mode select bit (bit 0 in addresses 036716, 02E716, 033716, 032716 and 02F716) is set to
“1”, the I2C bus (simple I2C bus) interface circuit is enabled.
To use the I2C bus, set the SCLi and the SDAi of both master and slave to output with the function select
register. Also, set the data output select bit (bit 5 in address 036C16, 02EC16, 033C16, 032C16 and
02FC16) to N-channel open drain output.
Table 1.21.1 shows the relationship of the IIC mode select bit to control. To use the chip in the clock
synchronized serial I/O mode or UART mode, always set this bit to “0”.
Function Normal mode (IICM=0) I2C mode (IICM=1)
Factor of interrupt number 17, 19, 33, 35, 37 UARTi transmission No acknowledgment detection (NACK)
Factor of interrupt number 18, 20, 34, 36, 38 UARTi reception
Start condition detection or stop
condition detection
UARTi transmission output delay Not delayed Delayed
P63, P67, P70, P92, P96 at the time when UARTi
is in use TxDi (output) SDAi (input/output)
P62, P66, P71, P91, P97 at the time when UARTi
is in use RxDi (input) SCLi (input/output)
P61, P65, P72, P90, P95 at the time when UARTi
is in use CLKi P61, P65, P72, P90, P95
DMA factor at the time UARTi reception Acknowledgment detection (ACK)
Noise filter width 15ns 50ns
Reading P62, P66, P71, P91, P97Reading the terminal when 0 is
assigned to the direction register Reading the terminal regardless of the
value of the direction register
1
2
3
4
5
6
7
8
9
Note 1: Make the settings given below when I2C mode is used.
Set 0 1 0 in bits 2, 1, 0 of the UARTi transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from one factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when IIC mode (IIC mode select bit = "1") is valid and serial I/O is invalid.
Factor of interrupt number 39 to 41 Bus collision detection
Acknowledgment detection (ACK)
10
Initial value of UARTi output H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P63, P67, P70,
P92, P96 when the port is selected
11
(Note 2)
(Note 2)
(Note 2)
(Note 1)
(Note 3)
(Note 3)
Table 1.21.1. Features in I2C mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
188
Selector I/O
Timer
delay
UARTi
Reception register
External clock
Arbitration
Start condition detection
Stop condition detection
Falling edge
detection
UARTi transmission/
NACK interrupt
request
UARTi reception/ACK
interrupt request
DMAi request
9th pulse
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
L-synchronous
output enabling bit
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
Noize
Filter
I/0
Noize
Filter
TXDi/SDA
RxDi/SCL
CLK
control
Internal clock
UARTi
Serector
UARTi
I/0
Timer
CLKi
Data register
D
TQ
DTQ
DTQNACK
ACK
UARTi
UARTi
R
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1 and
IICM2=0
IICM=0
IICM=1
IICM=1
IICM=0
S
RQBus
busy
IICM=1
IICM=0
ALS
R
SSWC
Falling edge of 9th pulse
IICM=1 and
IICM2=0
IICM=0 or IICM2=1
IICM=0 or
IICM2=1
SWC2
SDHI
To DMAi
To DMAi
Selector
Transmission register
UARTi
Noize
Filter
Figure 1.21.1 is a block diagram of the IIC bus interface.
The control bits of the IIC bus interface is explained as follow:
UARTi Special Mode Register (UiSMR:Addresses 036716, 02E716, 033716, 032716, 02F716)
Bit 0 is the IIC mode select bit. When set to “1”, ports operate respectively as the SDAi data transmis-
sion-reception pin, SCLi clock I/O pin and port. A delay circuit is added to SDAi transmission output,
therefore after SCLi is sufficiently L level, SDAi output changes. Port (SCLi) is designed to read pin
level regardless of the content of the port direction register. SDAi transmission output is initially set to
port in this mode. Furthermore, interrupt factors for the bus collision detection interrupt, UARTi trans-
mission interrupt and UARTi reception interrupt change respectively to the start/stop condition detec-
tion interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt.
Figure 1.21.1. Functional block diagram for I2C mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
189
The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected
while the SCLi pin is in the H state. The stop condition detection interrupt is generated when the rising
edge at the SDAi pin is detected while the SCLi pin is in the H state.
The acknowledge non-detection interrupt is generated when the H level at the SDAi pin is detected at
the 9th rise of the transmission clock.
The acknowledge detection interrupt is generated when the L level at the SDAi pin is detected at the
9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de-
tected and UARTi transmission is selected as the DMAi request factor.
Bit 1 is the arbitration lost detection flag control bit (ABC). Arbitration detects a conflict between data
transmitted at SCLi rise and data at the SDAi pin. This detection flag is allocated to bit 11 in UARTi
transmission buffer register (addresses 036F16, 02EF16, 033F16, 032F16, 02FF16). It is set to “1” when
a conflict is detected. With the arbitration lost detection flag control bit, it can be selected to update the
flag in units of bits or bytes. When this bit is set to “1”, update is set to units of byte. If a conflict is then
detected, the arbitration lost detection flag control bit will be set to “1” at the 9th rise of the clock. When
updating in units of byte, always clear (“0” interrupt) the arbitration lost detection flag control bit after
the 1st byte has been acknowledged but before the next byte starts transmitting.
Bit 2 is the bus busy flag (BBS). It is set to “1” when the start condition is detected, and reset to “0”
when the stop condition is detected.
Bit 3 is the SCLi L synchronization output enable bit (LSYN). When this bit is set to “1”, the port data
register is set to “0” in sync with the L level at the SCLi pin.
Bit 4 is the bus collision detection sampling clock select bit (ABSCS). The bus collision detection
interrupt is generated when RxDi and TxDi level do not conflict with one another. When this bit is “0”,
a conflict is detected in sync with the rise of the transfer clock. When this bit is “1”, detection is made
when timer Ai (timer A3 with UART0, timer A4 with UART1, timer A0 with UART2, timer A3 with
UART3 and timer A4 with UART4) underflows. Operation is shown in Figure 1.21.2.
Bit 5 is the transmission enable bit automatic clear select bit (ACSE). By setting this bit to “1”, the
transmission bit is automatically reset to “0” when the bus collision detection interrupt factor bit is “1”
(when a conflict is detected).
Bit 6 is the transmission start condition select bit (SSS). By setting this bit to “1”, TxDi transmission
starts in sync with the rise at the RxDi pin.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
190
1. Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register)
0: Rising edges of the transfer clock
CLKi
Timer Ai
1: Timer Ai underflow
2. Auto clear function select bit of transmit enable bit (Bit 5 of the UARTi special mode
register)
CLKi
TxDi/RxDi
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UARTi special mode register)
CLKi
TxDi Enabling transmission
CLKi
TxDi
RxDi
With "1: falling edge of RxD
i
" selected
0: In normal state
TxDi/RxDi
Figure 1.21.2. Some other functions added
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
191
UARTi Special Mode Register 2 (UiSMR2:Addresses 036616, 02E616, 033616, 032616, 02F616)
Bit 0 is the IIC mode select bit 2 (IICM2). Table 1.21.2 gives control changes by bit when the IIC mode
select bit is “1”. Start and stop condition detection timing characteristics are shown in Figure 1.21.4.
Always set bit 7 (start/stop condition control bit) to “1”.
Bit 1 is the clock synchronizing bit (CSC). When this bit is set to “1”, and the rising edge is detected at
pin SCLi while the internal SCL is High level, the internal SCL is changed to Low level, the baud rate
generator value is reloaded and the Low sector count starts. Also, while the SCLi pin is Low level, and
the internal SCL changes from Low level to High, baud rate generator stops counting. If the SCLi pin
is H level, counting restarts. Because of this function, the UARTi transmission-reception clock takes
the AND condition for the internal SCL and SCLi pin signals. This function operates from the clock half
period before the 1st rise of the UARTi clock to the 9th rise. To use this function, select the internal
clock as the transfer clock.
Bit 2 is the SCL wait output bit (SWC). When this bit is set to “1”, output from the SCLi pin is fixed to L
level at the clock’s 9th rise. When set to “0”, the Low output lock is released.
Bit 3 is the SDA output stop bit (ALS). When this bit is set to “1”, an arbitration lost is generated. If the
arbitration lost detection flag is “1”, then the SDAi pin simultaneously becomes high impedance.
Bit 4 is the UARTi initialize bit (STC). While this bit is set to “1”, the following operations are performed
when the start condition is detected.
1. The transmission shift register is initialized and the content of the transmission register is trans-
mitted to the transmission shift register. As such, transmission starts with the 1st bit of the next
input clock. However, the UARTi output value remains the same as when the start condition was
detected, without changing from when the clock is input to when the 1st bit of data is output.
2. The reception shift register is initialized and reception starts with the 1st bit of the next input
clock.
3. The SCL wait output bit is set to “1”. As such, the SCLi pin becomes Low level at the rise of the
9th bit of the clock.
When UART transmission-reception has started using this function, the content of the transmission
buffer available flag does not change. Also, to use this function, select an external clock as the transfer
clock.
Bit 5 is SCL wait output bit 2 (SWC2). When this bit is set to “1” and serial I/O is selected, an Low level
can be forcefully output from the SCLi pin even during UART operation. When this bit is set to “0', the
Low output from the SCLi pin is canceled and the UARTi clock is input and output.
Bit 6 is the SDA output disable bit (SDHI). When this bit is set to “1”, the SDAi pin is forced to high
impedance. To overwrite this bit, do so at the rise of the UARTi transfer clock. The arbitration lost
detection flag may be set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
192
IICM2 = 0
Acknowledge not detect
(NACK)
Acknowledge detect (ACK)
Acknowledge detect (ACK)
Rising edge of the last bit of re-
ceive clock
Rising edge of the last bit of re-
ceive clock
Function
Interrupt no. 17, 19, 33, 35, 37 fac-
tor
Interrupt no. 18, 20, 34, 36, 38 fac-
tor
DMA factor
Data transfer timing from UART re-
ceive shift register to receive buffer
UART receive / ACK interrupt re-
quest generation timing
IICM2 = 1
UARTi transfer (rising edge of the
last bit)
UARTi receive (falling edge of the
last bit)
UARTi receive (falling edge of the
last bit)
Rising edge of the last bit of re-
ceive clock
Rising edge of the last bit of re-
ceive clock
Set up time Hold time
SCL
SDA
(Start condition)
SDA
(Stop condition)
UARTi Special Mode Register 3 (UiSMR3:Addresses 036516, 02E516, 033516, 032516, 02F516)
Bit 1 is clock phase set bit (CKPH). When both the IIC mode select bit (bit 0 of UARTi special mode
select register) and the IIC mode select bit 2 (bit 0 of UiSMR2 register) are "1", functions changed by
these bits are shown in table 1.21.3 and figure 1.21.4.
Bits 5 to 7 are SDAi digital delay setting bits (DL0 to DL2). By setting these bits, it is possible to turn the
SDAi delay OFF or set the BRG count source delay to 2 to 8 cycles.
Table 1.21.3. Functions changed by clock phase set bits
CKPH = 0, IICM = 1, IICM2 = 1
Initial value = H, last value = L
Rising edge of 9th bit
Falling edge of 9th bit
Function
SCL initial and last value
Transfer interrupt factor
Data transfer times from UART re-
ceive shift register to receive buffer
register
CKPH = 1, IICM = 1, IICM2 = 1
Initial value = L, last value = L
Falling edge of 10th bit
Two times :falling edge of 9th bit
and rising edge of 9th bit
Table 1.21.2. Functions changed by I2C mode select bit 2
Figure 1.21.3. Start/stop condition detect timing characteristics
3 to 6 cycles < set up time (Note)
3 to 6 cycles < hold time (Note)
Note : Cycle number shows main clock input oscillation frequency f(XIN) cycle number.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
193
Figure 1.21.4. Functions changed by clock phase set bits
UARTi Special Mode Register 4 (UiSMR4:Addresses 036416, 02E416, 033416, 032416, 02F416)
Bit 0 is the start condition generate bit (STAREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the start condition is generated.
Bit 1 is the restart condition generate bit (RSTAREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the restart condition is generated.
Bit 2 is the stop condition generate bit (STPREQ). When the SCL, SDA output select bit (bit 3 of
UiSMR4 register) is "1" and this bit is "1", then the stop condition is generated.
Bit 3 is SCL, SDA output select bit (STSPSEL). Functions changed by these bits are shown in table
1.21.4 and figure 1.21.5.
Table 1.21.4. Functions changed by SCL, SDA output select bit
STSPSEL = 0
Output of SI/O control circuit
Start/stop condition detection
Function
SCL, SDA output
Star/stop condition interrupt factor
STSPSEL = 1
Output of start/stop condition
control circuit
Completion of start/stop condition
generation
• CKPH= "1" (IICM=1, IICM2=1)
• CKPH= "0" (IICM=1, IICM2=1)
(Internal clock, transfer data 9 bits long and MSB first selected.)
D
6
D
5
D
4
D
3
D
2
D
1
D
8
D7
SDA
SCL
D
0
Receive interrupt Transmit interrupt
Transfer to receive buffer
(Internal clock, transfer data 9 bits long and MSB first selected.)
D
6
D
5
D
4
D
3
D
2
D
1
D
8
D7
SDA
SCL
D
0
Receive interrupt Transmit interrup
t
Transfer to receive buffer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
194
Figure 1.21.5 Functions changed by SCL, SDA output select bit
Bit 4 is ACK data bit (ACKD). When the SCL, SDA output select bit (bit 3 of UiSMR4 register) is "0"
and the ACK data output enable bit (bit 5 of UiSMR4 register) is "1", then the content of ACK data bit
is output to SDAi pin.
Bit 5 is ACK data output enable bit (ACKC). When the SCL, SDA output select bit (bit 3 of UiSMR4
register) is "0" and this bit is "1", then the content of ACK data bit is output to SDAi pin.
Bit 6 is SCL output stop bit (SCLHI). When this bit is "1", SCLi output is stopped at stop condition
detection. (Hi-impedance status).
Bit 7 is SCL wait output bit 3 (SWC9). When this bit is "1", SCLi output is fixed to "L" at falling edge of
10th bit of clock. When this bit is "0", SCLi output fixed to "L" is released.
SDA
Start condition detection
interrupt Stop condition detection
interrupt
• When slave mode (CKDIR=0, STSPSEL=0)
SCL
SDA
Start condition detection
interrupt Stop condition detection
interrupt
• When master mode (CKDIR=1, STSPSEL=1)
SCL
STAREQ=1 STPREQ=1
STSPSEL=0 STSPSEL=1 STSPSEL=0 STSPSEL=0STSPSEL=1
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
195
P1
3
P1
2
IC1
P9
3(
SS
3
)
P9
2(
TxD
3
)
P9
0(
CLK
3
)
P9
1(
RxD
3
)
IC2
P9
3(
SS
3
)
P9
2(
SRxD
3
)
P9
0(
CLK
3
)
P9
1(
STxD
3
)
IC3
P9
3(
SS
3
)
P9
2(
SRxD
3
)
P9
0(
CLK
3
)
P9
1(
STxD
3
)
M16C/80 (M) M16C/80 (S)
M16C/80 (S)
M :Master
S :Slave
(2) Serial Interface Special Function _____
UARTi can control communications on the serial bus using the SSi input pins (Figure 1.21.6). The master
outputting the transfer clock transfers data to the slave inputting the transfer clock. In this case, in order to
_____
prevent a data collision on the bus, the master floats the output pin of other slaves/masters using the SSi
input pins.
_____
SSi input pins function between the master and slave are as follows.
Figure 1.21.6. Serial bus communication control example using the SS input pins
< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
_____
When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
_____
impedance, hence the clock input is ignored. When an "L" level signal is input to an SSi input pin, the
clock input becomes effective and serial communications are enabled.
< Master Mode (TxDi and RxDi are selected, DINC = 0) >
_____ _____
The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
_____
sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the
trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error
is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans-
mission-reception mode register (addresses 036816, 02E816, 033816, 032816 and 02F816) to “0”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
196
Master SS input
Data output timing
Data input timing
D0D1D2D3D4D6D7D5
"H"
"L"
Clock output
(CKPOL=0, CKPH=0) "H"
"L"
Clock output
(CKPOL=1, CKPH=0) "H"
"L"
Clock output
(CKPOL=0, CKPH=1) "H"
"L"
Clock output
(CKPOL=1, CKPH=1) "H"
"L"
"H"
"L"
Clock Phase Setting
With bit 1 of UARTi special mode register 3 (UiSMR3:addresses 036516, 02E516, 033516, 032516,
02F516) and bit 6 of UARTi transmission-reception control register 0 (addresses 036C16, 02EC16,
033C16, 032C16, 02FC16), four combinations of transfer clock phase and polarity can be selected.
Bit 6 of UARTi transmission-reception control register 0 sets transfer clock polarity, whereas bit 1 of
UiSMR3 register sets transfer clock phase.
Transfer clock phase and polarity must be the same between the master and slave involved in the
transfer.
< Master (Internal Clock) (DINC = 0) >
Figure 1.21.7 shows the transmission and reception timing.
< Slave (External Clock) (DINC = 1) > _____
• With “0” for CKPH bit (bit 1 of UiSMR3 register), when an SSi input pin is H level, output data is high
_____
impedance. When an SSi input pin is L level, the serial transmission start condition is satisfied,
though output is indeterminate. After that, serial transmission is synchronized with the clock. Figure
1.21.8 shows the timing. _____ _____
• With “1” for CKPH bit, when an SSi input pin is H level, output data is high impedance. When an SSi
input pin is L level, the first data is output. After that, serial transmission is synchronized with the
clock.Figure 1.21.9 shows the thing.
Figure 1.21.7. The transmission and reception timing in master mode (internal clock)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
197
High-
inpedance
SS input
Clock input
(CKPOL=0, CKPH=0)
Clock input
(CKPOL=1, CKPH=0)
Data output timing
Data input timing
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
High-
inpedance
D
0
D
1
D
2
D
3
D
4
D
6
D
7
D
5
Indeterminate
Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.
(Note)
High-
inpedance
SS input
Clock input
(CKPOL=0, CKPH=0)
Clock input
(CKPOL=1, CKPH=0)
Data output timing
Data input timing
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L" High-
inpedance
D
0
D
1
D
2
D
3
D
6
D
7
D
4
D
5
Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.
(Note)
Figure 1.21.8. The transmission and reception timing (CKPH=0) in slave mode (external clock)
Figure 1.21.9. The transmission and reception timing (CKPH=1) in slave mode (external clock)
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
198
CAN Module
The microcomputer incorporates Full-CAN modules compliant with CAN (Controller Area Network) 2.0B
specification.
These Full-CAN modules are outlined below.
Table 1.22.1 Outline of the CAN module
Item Description
Protocol Compliant with CAN 2.0B specification
Number of message slots 16 slots
Polarity 0: Dominant
1: Recessive
Acceptance filter Global mask: 1 mask (for message slots 0–13)
Local mask: 2 masks (for message slots 14 and 15 each)
Baud rate 1 time quantum (Tq) = (BRP + 1) / CPU clock (Note)
(BRP = baud rate prescaler set value)
Baud rate = 1 / (Tq period x number of Tq’s in one bit) ---Max. 1 Mbps
BRP: 1-255 (0: Inhibited)
Number of Tq’s in one bit = Synchronization Segment +
Propagation Time Segment +
Phase Buffer Segment 1 +
Phase Buffer Segment 2
Synchronization Segment : 1 Tq (fixed)
Propagation Time Segment : 1 to 8 Tq
Phase Buffer Segment 1 : 2 to 8 Tq
Phase Buffer Segment 2 : 2 to 8 Tq
Remote frame automatic The message slot that received a remote frame automatically transmits it.
answering function
Timestamp function This timestamp function is based on a 16-bit counter. A count period can
be derived from the CAN bus bit period (as the fundamental period) by
dividing it by 1, 2, 3, or 4.
BasicCAN mode The BasicCAN function is realized by using message slots 14 and 15.
Transmit abort function This function is used to cancel a transmit request.
Loopback function The data the CAN module itself transmitted is received.
Return from bus-off function Forcibly placed into an error active state from a bus-off state.
Note: Use a specification conforming resonator whose maximum permissible error of oscillation is not
greater than 1.58%
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
199
Message slot 0
control register
Control register
Expansion ID
register
Configuration
register
Slot interrupt
mask register
Error interrupt
mask register
Baud rate
prescaler
Sleep control
register Global
mask register
Local
mask register A
Local
mask register B
Acceptance
filter support
register
Message
slot buffer 0
Time stamp
register
16 bits timer
Status
register
Transmit error
count register
Receive error
count register
Slot interrupt
status register
Error interrupt
status register
Interrupt request
Message box
(slot 0 to 15)
Message
slot 0
BCLK
Acceptance
Filter
CAN
IN
CAN
OUT CAN protocol
controller
Ver 2.0B
Interrupt
control circuit
Data bus
Slot buffer
select register
Figure 1.22.1 CAN module blobk diagram
CAN0 message slot buffer 0 and 1 can be selected by setting of slot buffer select register. Figure 1.22.2
shows the message slot buffer and 16 bytes of message slots. Figure 1.22.26 to 1.22.30 show related
registers.
Figure 1.22.2. Message slot buffer and message slots
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extended ID0
CAN0 message slot buffer 0 extended ID1
CAN0 message slot buffer 0 extended ID2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot 15 time stamp low
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extended ID0
CAN0 message slot buffer 0 extended ID1
CAN0 message slot buffer 0 extended ID2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp high
CAN0 message slot buffer 1 time stamp low
CAN0 message slot 0 to 15
CAN0 message slot buffer 0 (addresses 01E0
16
to 01EF
16
)
CAN0 message slot buffer 1 (addresses 01F0
16
to 01FF
16
)
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extend ID0
CAN0 message slot buffer 0 extend ID1
CAN0 message slot buffer 0 extend ID2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp high
CAN0 message slot buffer 0 time stamp low
CAN0 message slot 0 standard ID0
CAN0 message slot 0 standard ID1
CAN0 message slot 0 extend ID0
CAN0 message slot 0 extend ID1
CAN0 message slot 0 extend ID2
CAN0 message slot 0 data length code
CAN0 message slot 0 data 0
CAN0 message slot 0 data 1
CAN0 message slot 0 data 2
CAN0 message slot 0 data 3
CAN0 message slot 0 data 4
CAN0 message slot 0 data 5
CAN0 message slot 0 data 6
CAN0 message slot 0 data 7
CAN0 message slot 0 time stamp high
CAN0 message slot 0 time stamp low
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
200
CAN0 control register 0
Symbol Address When reset (Note 1)
C0CTLR0 0201
16,
0200
16
XXXX 0000 XX01 0X01
2
RW
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Note 2: Only writing 1 is accepted. The bit is automatically cleared to 0 in hardware.
Reset 1
TSPre0
TSReset
ECReset
CAN reset bit 1
Time stamp
counter reset bit
Error counter
reset bit
0 : Reset released
1 : Reset requested
Reset 0
Loopback
BasicCAN
CAN reset bit 0
Loop back mode
select bit
Basic CAN mode
select bit
0 0: CAN bus bit clock is selected
0 1: Division b y 2 of CAN b us bit cloc k is selected
1 0: Division b y 3 of CAN b us bit cloc k is selected
1 1: Division b y 4 of CAN b us bit cloc k is selected
b9 b8
0 : Basic CAN mode function disabled
1 : Basic CAN mode function enabled
0: Loop back function disabled
1: Loop back function enabled
0: Reset released
1: Reset requested
TSPre1
0 : Count enabled
1 : Count reset (set 0000
16
) (Note 2)
0 : Normal operation mode
1 : Error counter reset (Note 2)
Time stamp
prescaler select bit
Reserved bit Must set to "0".
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Nothing is assigned. When write, set to "0".
When read, its contents is indeterminate.
b7 b0
b15
(b7) b8
(b0)
0
Figure 1.22.3 CAN0 control register 0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
201
1. CAN0 control register 0
Bit 0: CAN reset bits 0 and 1 (Reset0 and Reset1)
If the Reset0 and Reset1 bits both are set from 1 to 0, CAN communication is enabled after detecting
11 consecutive recessive bits. The CAN Timestamp Register starts counting at the same time com-
munication is enabled.
In no case will the CAN be reset unless transmission of all messages are completed.
Note 1: Reset0 and Reset1 bits must both be cleared to "0" or set to "1" simutnously.
Note 2: Setting a new transmit request is inhibited before the CAN Status Register State_Reset bit is
set to 1 and the CAN module is reset after setting the Reset0 and Reset1 bits to 1.
Note 3: When the CAN module is reset by setting the Reset0 and Reset1 bits to 1, the CAN
Timestamp Register (C0TSR), CAN Transmit Error Counter (C0TEC), and CAN Receive
Error Counter (C0REC) are initialized to 0.
Note 4: If Reset0 and Reset1 bits sre set to "1" during communication, the CANOUT pin output goes
"H" immediately after that. Therefore, setting these bits to 1 while the CAN module is sending
a frame may cause a CAN bus error.
Note 5: To CAN communication, function select register A1 (PS1), function select register A2 (PS2),
function select register B1 (PSL1), function select register B2 (PSL2), function select register
C (PSC) and input function select register (IPS) must be set. These registers must be set
when CAN module is reset.
Bit 1: Loopback mode select bit (LoopBack)
Setting the LoopBack bit to 1 enables loopback mode, so that if any receive slot whose ID matches
that of a frame the CAN module itself transmitted exists, the frame is received.
Note 1: ACK is not returned for the transmit frame.
Note 2: Do not set or reset the LoopBack bit while the CAN module is operating (CAN Status Register
State_Reset bit = 0).
Bit 3: BasicCAN mode select bit (BasicCAN)
If this bit is set to 1, message slots 14 and 15 operate in BasicCAN mode.
• Operation during BasicCAN mode
In BasicCAN mode, message slots 14 and 15 are used with a dual-structured buffer. The received
frames whose IDs are found matching by acceptance filtering are stored in slots 14 and 15 alter-
nately. When slot 14 is active (i.e., the next received frame is to be stored in slot 14), this acceptance
filtering is accomplished using the ID that is set in slot 14 and local mask A; when slot 15 is active, it
is accomplished using the ID that is set in slot 15 and local mask B. Frame types of both data frame
and remote frame can be received.
When using BasicCAN mode, setting the IDs of two slots and the mask registers the same way helps
to reduce the possibility of causing an overrun error.
• Procedure for entering BasicCAN mode
Make the following settings during initialization.
(1) Set the BasicCAN bit to 1.
(2) Set the IDs of slots 14 and 15 and Local Mask Registers A and B. (We recommend setting the
same value)
(3) Set the frame format to be handled with slots 14 and 15 (standard or extended) in the CAN
Extended ID Register. (We recommend setting the same format)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
202
(4) Set the Message Slot Control Registers for slots 14 and 15 to receive data frames.
Note 1: Do not set or reset the BasicCAN bit while the CAN module is operating (CAN Status Regis-
ter State_Reset bit = 0).
Note 2: Slot 14 is the first slot to become active after clearing the Reset0 bit.
Note 3: Even during BasicCAN mode, slot 0 through slot 13 can be used in the same way as when
operating normally.
Bit 8, 9: Timestamp prescaler select bits (TSPre0, 1)
These bits select the count clock source for the timestamp counter.
Note 1: Do not set or reset these TSPre0, 1 bits while the CAN module is operating (CAN Status
Register State_Reset bit = 0).
Bit 10: Timestamp counter reset bit (TSReset)
Setting this bit to 1 clears the value of the CAN Timestamp Register (C0TSR) to 000016. This bit is
automatically cleared after the CAN Timestamp Register (C0TSR) has its value cleared to 000016.
Bit 11: Error counter reset bit (ECReset)
Setting this bit to 1 clears the Receive Error Counter Register (C0REC) and Transmit Error Counter
Register (C0TEC), with the CAN module forcibly placed in an error active state. This bit is automati-
cally cleared upon entering an error active state.
Note 1: When in an error active state, the CAN module becomes ready to communicate when it
detects 11 consecutive recessive bits on the CAN bus.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
203
BankSel
CAN0 control register 1
Symbol Address When reset (Note)
C0CTLR1 0241
16
XX0000XX
2
RW
CAN0 bank select bit 0 : Message slot control register
selected
1 : Mask register selected
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Bit name Function
Bit
symbol
Reserved bit Must set to "0".
Reserved bit Must set to "0".
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b0
000
Figure 1.22.4. CAN0 control register 1
2. CAN0 control register 1
Bit 3: CAN0 bank select bit (BankSel)
This bit selects between registers allocated to the addresses 022016 through 023F16.
Setting the BankSel bit to 0 selects the CAN0 Message Slot Control Register. Setting the BankSel bit
to 1 selects the CAN0 Mask Register.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
204
Sleep
CAN0 sleep control register
Symbol Address When reset
C0SLPR 024216 XXXXXXX02
RW
Sleep mode control bit 0 : Sleep mode On
1 : Sleep mode Off (Note)
Note: After CAN sleep mode is canceled, set up the CAN configuration. While the CAN module is in sleep
mode, no SFR registers for the CAN, except the sleep mode control register, can be accessed for
read or write.
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b0
Figure 1.22.5. CAN0 sleep control register
3. CAN0 sleep control register
Bit 0: Sleep mode control bit (Sleep)
The CAN module isn't supplied with a clock by setting the Sleep bit to 0, and is shifted to sleep mode.
The CAN module is supplied with a clock by setting the Sleep bit to 1, and is released from sleep
mode.
Note: Sleep mode can be shifted to only after CAN is reset (State_Reset bit = 1).
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
205
CAN0 status register
Symbol Address When reset (Note)
C0STR 0203
16,
0202
16
X000 0X01 0000 0000
2
RW
0 0 0 0 : Slot 0
0 0 1 0 : Slot 1
0 0 1 1 : Slot 2
0 1 0 0 : Slot 3
• •
• •
1 1 0 1 : Slot 13
1 1 1 0 : Slot 14
1 1 1 1 : Slot 15
b2b3 b0b1
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
MBox0
TrmSucc
RecSucc
Active slot
determination bit
TrmState
RecState
State_Reset
State_LoopBack
State_BasicCAN
State_BusError
State_ErrPas
State_BusOff
Transmission-finished
status
Reception-finished
status
Transmission status
Reception status
CAN reset status
Loop back status
Basic CAN status
CAN bus error
Error passive status
Bus-off status
0: T ransmission not finished
1: T ransmission finished
0: Reception not finished
1: Reception finished
0: Not transmitting
1: T ransmitting
0: Not receiving
1: Receiving
0: Operating
1: Reset
0: Normal mode
1: Loop back mode
0: Normal mode
1: Basic CAN mode
0: No error occurred
1: Error occurred
0: Not error passive state
1: Error passive state
0: Not bus-off state
1: Bus-off state
MBox1
MBox2
MBox3
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
b7 b0
b15
(b7) b8
(b0)
Figure 1.22.6. CAN0 status register
4. CAN0 status register
Bits 0–3: Active slot determination bits (MBox)
When the CAN module finished transmitting data or finished storing received data, the relevant slot
number is stored in these bits.
The MBox bits cannot be cleared to 0 in software.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
206
Bit 4: Transmission-finished status (TrmSucc)
[Set condition]
This bit is set to 1 when the CAN module finished transmitting data normally.
[Clear condition]
This bit is cleared when the CAN module finished receiving data normally.
Bit 5: Reception-finished status (RecSucc)
[Set condition]
This bit is set to 1 when the CAN module finished receiving data normally (regardless of whether the
received message has been stored in a message slot). However, this bit is not set if the received
message is one that was transmitted in loopback mode.
[Clear condition]
This bit is cleared when the CAN module finished transmitting data normally.
Bit 6: Transmission status (TrmState)
[Set condition]
This bit is set to 1 when the CAN module is operating as a transmit node.
[Clear condition]
This bit is cleared when the CAN module goes to a bus-idle state or starts operating as a receive
node.
Bit 7: Reception status (RecState)
[Set condition]
This bit is set to 1 when the CAN module is operating as a receive node.
[Clear condition]
This bit is cleared when the CAN module goes to a bus-idle state or starts operating as a transmit
node.
Bit 8: CAN reset status (State_Reset)
When the State_Reset bit = 1, it means that the CAN module is in a reset state.
[Set condition]
This bit is set to 1 when CAN module is in a reset state.
[Clear condition]
This bit is cleared by clearing the Reset0 or Reset1 bits to 0.
Bit 9: Loopback status (State_loopBack)
When the State_loopBack bit = 1, it means that the CAN module is operating in loopback mode.
[Set condition]
This bit is set to 1 by setting the CAN control register LoopBack bit to 1.
[Clear condition]
This bit is cleared by clearing the LoopBack bit to 0.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
207
Bit 11: BasicCAN status (State_BasicCAN)
When the State_BasicCAN bit = 1, it means that the CAN module is operating in BasicCAN mode.
[Set condition]
This bit is set to 1 when the CAN module is operating in BasicCAN mode.
Conditions for the CAN module to operate in BasicCAN mode are as follows:
• The CAN Control Register BasicCAN bit is set to 1.
• Slots 14 and 15 both are set for data frame reception.
[Clear condition]
This bit is cleared by clearing the BasicCAN bit to 0.
Bit 12: CAN bus error (State_BusError)
[Set condition]
This bit is set to 1 when an error on the CAN bus is detected.
[Clear condition]
This bit is cleared when the CAN module finished transmitting or receiving normally. Clearing of this
bit does not depend on whether the received message has been stored in a message slot.
Note :When this bit is 1, although CAN module is reset, this bit does not become to 0.
Bit 13: Error passive status (State_ErrPas)
When the State_ErrPas bit = 1, it means that the CAN module is in an error-passive state.
[Set condition]
This bit is set to 1 when the value of C0TEC register or C0REC register exceeds 127, with the CAN
module in an error-passive state.
[Clear condition]
This bit is cleared when the CAN module goes from the error-passive state to any other error state.
Note :When this bit is 1, then CAN module is reset, this bit becomes 0 automatically.
Bit 14: Bus-off status (State_BusOff)
When the State_BusOff bit = 1, it means that the CAN module is in a bus-off state.
[Set condition]
This bit is set to 1 when the value of the C0TEC register exceeds 255, with the CAN module in a bus-
off state.
[Clear condition]
This bit is cleared when the CAN module returns from the bus-off state.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
208
CAN0 extended ID register
Symbol Address When reset (Note)
C0IDR 0205
16,
0204
16
0000
16
RW
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
IDE15
IDE14
IDE13
IDE12
IDE11
IDE10
Expansion ID15 (slot 15)
IDE9
IDE8
IDE7
IDE6
IDE5
0: Standard ID format
1: Extended ID format
IDE4
IDE3
IDE2
IDE1
IDE0
Expansion ID14 (slot 14)
Expansion ID13 (slot 13)
Expansion ID12 (slot 12)
Expansion ID11 (slot 11)
Expansion ID10 (slot 10)
Expansion ID9 (slot 9)
Expansion ID8 (slot 8)
Expansion ID7 (slot 7)
Expansion ID6 (slot 6)
Expansion ID5 (slot 5)
Expansion ID4 (slot 4)
Expansion ID3 (slot 3)
Expansion ID2 (slot 2)
Expansion ID1 (slot 1)
Expansion ID0 (slot 0)
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
0: Standard ID format
1: Extended ID format
Bit name Function
Bit
symbol
b7 b0
b15
(b7) b8
(b0)
Figure 1.22.7. CAN0 extended ID register
5. CAN0 extended ID register
This register selects the format of a frame handled by the message slot that corresponds to each bit
in this register.
Setting any bit to 0 selects the standard (Standard ID) format.
Setting any bit to 1 selects the extended (Extended ID) format.
Note 1: When setting or resetting any bit in this register, make sure the corresponding slot has no
transmit or receive request.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
209
CAN0 configuration register
Symbol Address When reset (Note)
C0CONR 0207
16,
0206
16
000X
16
RW
0 0 0: Propagation Time Segment = 1Tq
0 0 1: Propagation Time Segment = 2Tq
0 1 0: Propagation Time Segment = 3Tq
0 1 1: Propagation Time Segment = 4Tq
1 0 0: Propagation Time Segment = 5Tq
1 0 1: Propagation Time Segment = 6Tq
1 1 0: Propagation Time Segment = 7Tq
1 1 1: Propagation Time Segment = 8Tq
b6b7 b5
0 0 0: Must not be set
0 0 1: Phase Buffer Segment 1 = 2Tq
0 1 0: Phase Buffer Segment 1 = 3Tq
0 1 1: Phase Buffer Segment 1 = 4Tq
1 0 0: Phase Buffer Segment 1 = 5Tq
1 0 1: Phase Buffer Segment 1 = 6Tq
1 1 0: Phase Buffer Segment 1 = 7Tq
1 1 1: Phase Buffer Segment 1 = 8Tq
b9
b10
b8
0 0 0: Must not be set
0 0 1: Phase Buffer Segment 2 = 2Tq
0 1 0: Phase Buffer Segment 2 = 3Tq
0 1 1: Phase Buffer Segment 2 = 4Tq
1 0 0: Phase Buffer Segment 2 = 5Tq
1 0 1: Phase Buffer Segment 2 = 6Tq
1 1 0: Phase Buffer Segment 2 = 7Tq
1 1 1: Phase Buffer Segment 2 = 8Tq
b12b13 b11
0 0: SJW = 1Tq
0 1: SJW = 2Tq
1 0: SJW = 3Tq
1 1: SJW = 4Tq
b14b15
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
PTS1
PBS11
PBS21
Propagation Time
Segment
Phase Buffer
Segment 1
Phase Buffer
Segment 2
reSynchronization
Jump Width
SJW0
SJW1
PBS20
PBS22
PBS10
PBS12
PTS0
PTS2
Bit name Function
Bit
symbol
Sampling number 0: Sampled once
1: Sampled three times
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
SAM
b7 b0
b15
(b7) b8
(b0)
0
Figure 1.22.8. CAN0 configuration register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
210
6. CAN0 configuration register
Bit 4: SAM bit (SAM)
This bit sets the sampling number per one bit.
0: The value sampled at the last of the Phase Buffer Segment 1 becomes the bit value.
1: The bit value is determined by the majority operation circuit using values sampled at the following
three points: the last of the Phase Buffer Segment 1, before 1Tq, and before 2Tq.
Bits 5–7: PTS bits (RTS00-RTS02)
These bits set the width of Propagation Time Segment.
Bits 8–10: PBS1 bits (PBS10-PBS12)
These bits set the width of Phase Buffer Segment 1. The PBS1 bits must be set to 1 or greater.
Bits 11–13: PBS2 bits (PBS20-PBS22)
These bits set the width of Phase Buffer Segment 2. The PBS2 bits must be set to 1 or greater.
Bits 14, 15: SJW bits (SJW0, SJW1)
These bits set the width of reSynchronization Jump Width. The SJW bits must be set to a value equal
to or less than PBS2.
Table 1.22.2 Bit Timing Setup Example when the CPU Clock = 30 MHz
Baud rate BRP Tq period (ns) 1 bit's Tq number PTS+PBS1 PBS2 Sample point
1Mbps 1 66.7 15 12 2 87%
1 66.7 15 11 3 80%
1 66.7 15 10 4 73%
2 100 10 7 2 80%
2 100 10 6 3 70%
2 100 10 5 4 60%
500Kbps 2 100 20 16 3 85%
2 100 20 15 4 80%
2 100 20 14 5 75%
3 133.3 15 12 2 87%
3 133.3 15 11 3 80%
3 133.3 15 10 4 73%
4 166.7 12 9 2 83%
4 166.7 12 8 3 75%
4 166.7 12 7 4 67%
5 200 10 7 2 80%
5 200 10 6 3 70%
5 200 10 5 4 60%
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
211
CAN0 transmit error count register
Symbol Address When reset (Note)
C0TEC 020A
16
00
16
RW
Function
Transmit error count value
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
b7 b0
8-bit
Figure 1.22.9. CAN0 time stamp register
7. CAN0 Timestamp register
The CAN module incorporates a 16-bit counter. The count period for this counter can be derived
from the CAN bus bit period by dividing it by 1, 2, 3, or 4 using the CAN0 control register0
(C0CTLR0)’s TSPre0, 1 bits.
When the CAN module finishes transmitting or receiving, the CAN0 Timestamp Register (C0TSR)
value is captured and the value is automatically stored in a message slot.
The C0TSR register starts counting upon clearing the C0CTLR register’s Reset and Reset1 bits to 0.
Note 1: Setting the C0CTLR0 register’s Reset0 and Reset1 bits to 1 resets CAN, and the C0TSR
register thereby initialized to 000016. Also, setting the TSReset (timestamp counter reset) bit
to 1 initializes the C0TSR register to 000016 on-the-fly (while the CAN remains operating;
CAN0 status register's State_Reset bit is "0").
Note 2: During loopback mode, if any receive slot exists in which a message can be stored, the
C0TSR register value is stored in the corresponding slot when the CAN module finished
receiving. (This storing of the C0TSR register value does not occur at completion of trans-
mission.)
Figure 1.22.10. CAN0 transmit error count register
8. CAN0 transmit error count register
When in an error active or an error passive state, the transmit error count value is stored in this
register. The count is decremented when the CAN module finished transmitting normally or
incremented when an error occurred while transmitting.
When in a bus-off state, an indeterminate value is stored in this register. The register is reset to 0016
upon returning to an error active state.
CAN0 time stamp register
Symbol Address When reset (Note)
C0TSR 020916,020816 000016
RW
Function Setting range
16 bits count value 0000
16
to FFFF
16
b15
(b7)
(Upper 8-bit) (Lower 8-bit)
b8
(b0)b7 b0
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
212
CAN0 baud rate prescaler
Symbol Address When reset (Note 1)
C0BRP 021716 0116
RW
Function Setting range
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Note 2: Do not set to "00
16
" (division by 1).
01
16
to FF
16
Baud rate prescaler value selected (Note 2)
8-bit
b7 b0
Figure 1.22.11. CAN0 reception error count register
9. CAN0 reception error count register
When in an error active or an error passive state, the receive error count value is stored in this
register. The count is decremented when the CAN module finished receiving normally or incremented
when an error occurred while receiving.
When C0REC > 128 (error passive state) at the time the CAN module finished receiving normally, the
C0REC register is set to 127.
When in a bus-off state, an indeterminate value is stored in this register. The register is reset to 0016
upon returning to an error active state.
Figure 1.22.12. CAN0 baud rate register
10. CAN0 baud rate prescaler
This register is used to set the Tq period, the CAN bit time. The CAN baud rate is determined by (Tq
period x number of Tq’s in one bit).
Tq period = (C0BRP+1)/CPU clock
CAN baud rate = 1 / (Tq period x number of Tq’s in one bit)
Number of Tq’s in one bit = Synchronization Segment +
Propagation Time Segment +
Phase Buffer Segment 1 +
Phase Buffer Segment 2
CAN0 reception error count register
Symbol Address When reset (Note)
C0REC 020B16 0016
RW
Function
Reception error count value
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
b7 b0
8-bit
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
213
CAN0 slot interrupt status register
Symbol Address When reset (Note 1)
C0SISTR 020D
16,
020C
16
0000
16
RW
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.
SIS15
SIS14
SIS13
SIS12
SIS11
SIS10
Slot 15 interrupt
request status bit
SIS9
SIS8
SIS7
SIS6
SIS5
Slot 14 interrupt
request status bit
Slot 13 interrupt
request status bit
Slot 12 interrupt
request status bit
Slot 11 interrupt
request status bit
Slot 10 interrupt
request status bit
Slot 9 interrupt
request status bit
Slot 8 interrupt
request status bit
Slot 7 interrupt
request status bit
Slot 6 interrupt
request status bit
Slot 5 interrupt
request status bit
Slot 4 interrupt
request status bit
Slot 3 interrupt
request status bit
Slot 2 interrupt
request status bit
Slot 1 interrupt
request status bit
Slot 0 interrupt
request status bit
SIS4
SIS3
SIS2
SIS1
SIS0
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
Bit name Function
Bit
symbol
b7 b0
b15
(b7) b8
(b0)
Figure 1.22.13. CAN slot interrupt status register
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
214
9. CAN0 slot interrupt status register
When using CAN interrupts, the CAN0 Slot Interrupt Status Register helps to know which slot requested
an interrupt.
• For transmit slots
The status is set to 1 when the CAN module finished storing the CAN Timestamp Register value in
the message slot after completing transmission.
To clear this bit, write 0 in software (Note 1).
• For receive slots
The status is set to 1 when the CAN module finished storing the received message in the message
slot after completing reception.
To clear this bit, write 0 in software (Note 1).
Note 1: To clear any bit of the CAN Interrupt Status Register, write 0 to the bit to be cleared and 1 to
all other bits, without using bit clear instructions.
Example : Assembler language mov.w #07FFFh, C0SISTR
C language c0sister = 0x7FFF;
Note 2: For remote frame receive slots whose automatic answering function is enabled, the slot
interrupt status bit is set when the CAN module finished receiving a remote frame and when
it finished transmitting a data frame.
Note 3: For remote frame transmit slots, the slot interrupt status bit is set when the CAN module
finished transmitting a remote frame and when it finished receiving a data frame.
Note 4: If the slot interrupt status bit is set by an interrupt request at the same time it is cleared by
writing in software, the former has priority, i.e., the slot interrupt status bit is set.
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
215
CAN0 slot interrupt mask register
Symbol Address When reset (Note)
C0SIMKR 021116,021016 000016
RW
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
SIM15
SIM14
SIM13
SIM12
SIM11
SIM10
Slot 15 interrupt
request mask bit
SIM9
SIM8
SIM7
SIM6
SIM5
Slot 14 interrupt
request mask bit
Slot 13 interrupt
request mask bit
Slot 12 interrupt
request mask bit
Slot 11 interrupt
request mask bit
Slot 10 interrupt
request mask bit
Slot 9 interrupt
request mask bit
Slot 8 interrupt
request mask bit
Slot 7 interrupt
request mask bit
Slot 6 interrupt
request mask bit
Slot 5 interrupt
request mask bit
Slot 4 interrupt
request mask bit
Slot 3 interrupt
request mask bit
Slot 2 interrupt
request mask bit
Slot 1 interrupt
request mask bit
Slot 0 interrupt
request mask bit
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
SIM4
SIM3
SIM2
SIM1
SIM0
Bit name Function
Bit
symbol
b7 b0
b15
(b7) b8
(b0)
Figure 1.22.14. CAN0 slot interrupt mask register
12. CAN0 slot interrupt mask register
This register controls CAN interrupts by enabling or disabling interrupt requests generated by each
corresponding slot at completion of transmission or reception. Setting any bit of this register (SIMn
where n = 0–15) to 1 enables the interrupt request to be generated by the corresponding slot at
completion of transmission or reception.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
216
BOIM
EPIM
BEIM
CAN0 error interrupt mask register
Symbol Address When reset (Note)
C0EIMKR 021416 XXXX X0002
RW
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
0: Interrupt request masked (disabled)
1: Interrupt request enabled
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Bit name Function
Bit
symbol
Bus off interrupt
mask bit
Error passive interrupt
mask bit
CAN bus error interrupt
mask bit
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.15. CAN0 error interrupt mask register
13. CAN0 error interrupt mask register
Bit 0: Bus-off interrupt mask bit (BOIM)
This bit controls CAN interrupts by enabling or disabling interrupt requests generated when the CAN
module goes to a bus-off state. Setting this bit to 1 enables a bus-off interrupt request.
Bit 1: Error passive interrupt mask bit (EPIM)
This bit controls CAN interrupts by enabling or disabling interrupt requests generated when the CAN
module goes to an error passive state. Setting this bit to 1 enables an error passive interrupt request.
Bit 2: CAN bus error interrupt mask bit (BEIM)
This bit controls CAN interrupts by enabling or disabling interrupt requests generated by occurrence
of a CAN bus error. Setting this bit to 1 enables a CAN bus error interrupt request.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
217
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 024216) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.
CAN0 error interrupt status register
Symbol Address When reset (Note 1)
C0EISTR 021516 XXXX X0002
RW
BOIS
EPIS
BEIS
Bus off interrupt
status bit
Error passive interrupt
status bit
CAN bus error interrupt
status bit
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
0: Interrupt not requested
1: Interrupt requested (Note 2)
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.16. CAN0 error interrupt status register
14. CAN0 error interrupt status register
When using CAN interrupts, the CAN Error Interrupt Status Register helps to verify the causes of
error-derived interrupts.
Bit 0: Bus-off interrupt status bit (BOIS)
This bit is set to 1 when the CAN module goes to a bus-off state.
To clear this bit, write 0 in software (Note 1).
Bit 1: Error passive interrupt status bit (EPIS)
This bit is set to 1 when the CAN module goes to an error passive state.
To clear this bit, write 0 in software (Note 1).
Bit 2: CAN bus error interrupt status bit (BEIS)
This bit is set to 1 when a CAN communication error is detected.
To clear this bit, write 0 in software (Note 1).
Note 1: To clear any bit of the CAN Error Interrupt Status Register, write 0 to the bit to be cleared and
1 to all other bits, without using bit clear instructions.
Example: Assembler language mov.B #006h, C0EISTR
C language c0eistr = 0x06;
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
218
Slot 8 transmit/receive finished
SIS8
Slot 14 transmit/receive finished
Slot 13 transmit/receive finished
CAN0 transmit/ receive
error interrupt
b0
SIM15
F/F
SIS15
F/F
b0
b1
SIM14
F/F
SIS14
F/F
b1
b2
SIM13
F/F
SIS13
F/F
b2
b3
SIM12
F/F
SIS12
F/F
b3
b4
SIM11
F/F
SIS11
F/F
b4
C0SISTR
C0SIMKR Slot 15 transmit/receive finished
b5
SIM10
F/F
SIS10
F/F
b5
b6
SIM9
F/F
SIS9
F/F
b6
b7
SIM8
F/F
Slot 12 transmit/receive finished
Slot 11 transmit/receive finished
Slot 10 transmit/receive finished
Slot 9 transmit/receive finished
F/F
b7
To 11 other input sources on the next page
Data bus
(Level)
19-source inputs
Figure 1.22.17. CAN0 transmit, receive and error interrupt block diagram (1/3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
219
To previous page
b8
SIM7
F/F
SIS7
F/F
b8
b9
SIM6
F/F
SIS6
F/F
b9
b10
SIM5
F/F
SIS5
F/F
b10
b11
SIM4
F/F
SIS4
F/F
b11
b12
SIM3
F/F
SIS3
F/F
b12
Slot 7 transmit/receive finished
b13
SIM2
F/F
SIS2
F/F
b13
b14
SIM1
F/F
SIS1
F/F
b14
b15
SIM0
F/F
To 3 other input sources on the next page
F/F
b15
SIS0
Slot 6 transmit/receive finished
Slot 5 transmit/receive finished
Slot 4 transmit/receive finished
Slot 3 transmit/receive finished
Slot 2 transmit/receive finished
Slot 1 transmit/receive finished
Slot 0 transmit/receive finished
C0SISTR
C0SIMKR
Data bus
(Level)
19-source inputs
Figure 1.22.18. CAN0 transmit, receive and error interrupt block diagram (2/3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
220
b2
BEIM
F/F
BEIS
F/F
b2
b1
EPIM
F/F
EPIS
F/F
b1
b0
BOIM
F/F
BOIS
F/F
b0
CAN bus error occur
Shift to error passive state
Shift to bus off state
C0EISTR
C0EIMKR
Data bus
(Level)
19-source inputs
To the previous page
Figure 1.22.19. CAN0 transmit, receive and error interrupt block diagram (3/3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
221
CAN0 global mask register standard ID0
CAN0 local mask register A, B standard ID0
Symbol Address When reset (Note)
C0GMR0 0228
16
XXX0 0000
2
C0LMAR0 0230
16
XXX0 0000
2
C0LMBR0 0238
16
XXX0 0000
2
RW
SID6M
SID7M
SID8M
SID9M
Standard ID6 0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
Standard ID7
Standard ID8
Standard ID9
SID10M Standard ID10 0: ID not checked
1: ID checked
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.20. CAN0 global mask register standard ID0 and CAN0 local mask register A, B standard ID0
15. CAN0 global mask register standard ID0
CAN0 local mask register A, B standard ID0
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
222
CAN0 global mask register standard ID1
CAN0 local mask register A, B standard ID1
Symbol Address When reset (Note)
C0GMR1 022916 XX00 00002
C0LMAR1 023116 XX00 00002
C0LMBR1 023916 XX00 00002
RW
Standard ID0 0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
Standard ID1
Standard ID2
Standard ID3
Standard ID4
Standard ID5
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
SID0M
SID1M
SID2M
SID3M
SID4M
SID5M
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(
bit 0 at address 0242
16
)
to 1 after reset.
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.21. CAN0 global mask register standard ID1 and CAN0 local mask register A, B standard ID1
16. CAN0 global mask register standard ID1
CAN0 local mask register A, B standard ID1
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
223
CAN0 global mask register extend ID0
CAN0 local mask register A, B extend ID0
Symbol Address When reset (Note)
C0GMR2 022A
16
XXXX 0000
2
C0LMAR2 0232
16
XXXX 0000
2
C0LMBR2 023A
16
XXXX 0000
2
RW
EID14M
EID15M
EID16M
EID17M
Extend ID14 0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
Extend ID15
Extend ID16
Extend ID17
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.22. CAN0 global mask register extend ID0 and CAN0 local mask register A, B extend ID0
17. CAN0 global mask register extend ID0
CAN0 local mask register A, B extend ID0
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13 whereas local mask registers A and B are
used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
224
CAN0 global mask register extend ID1
CAN0 local mask register A, B extend ID1
Symbol Address When reset (Note)
C0GMR3 022B
16
00
16
C0LMAR3 0233
16
00
16
C0LMBR3 023B
16
00
16
RW
EID6M
EID7M
EID8M
EID9M
EID10M
EID11M
EID13M
EID12M
Extend ID6 0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
Extend ID7
Extend ID8
Extend ID9
Extend ID10
Extend ID11
Extend ID12
Extend ID13
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Bit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.23. CAN0 global mask register extend ID1 and CAN0 local mask register A, B extend ID1
18. CAN0 global mask register extend ID1
CAN0 local mask register A, B extend ID1
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13, whereas local mask registers A and B
are used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
225
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
CAN0 global mask register extend ID2
CAN0 local mask register A, B extend ID2
Symbol Address When reset (Note)
C0GMR4 022C
16
XX00 0000
2
C0LMAR4 0234
16
XX00 0000
2
C0LMBR4 023C
16
XX00 0000
2
RW
EID0M
EID1M
EID2M
EID3M
EID4M
EID5M
Extend ID0 0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
0: ID not checked
1: ID checked
Extend ID1
Extend ID2
Extend ID3
Extend ID4
Extend ID5
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.24. CAN0 global mask register extend ID2 and CAN0 local mask register A, B extend ID2
19. CAN0 global mask register extend ID2
CAN0 local mask register A, B extend ID2
The mask registers used for acceptance filtering consist of the global mask register, local mask
register A, and local mask register B.
The global mask register takes care of message slots 0–13, whereas local mask registers A and B
are used for message slots 14 and 15, respectively.
• If any bit of this register is set to 0, its corresponding ID bit is masked during acceptance filtering.
(The masked bit is not checked for ID; the ID is assumed to be matching.)
• If any bit of this register is set to 1, its corresponding ID bit is compared with the received ID during
acceptance filtering. If it matches the ID that is set in any message slot, the received data is stored
in that slot.
Note 1: The global mask register can only be modified when none of the slots 0–13 has receive
requests set.
Note 2: The local mask register A can only be modified when slot 14 has no receive requests set.
Note 3: The local mask register B can only be modified when slot 15 has no receive requests set.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
226
CAN0 message slot i control register (i=0 to 15)
Symbol Address When reset (Note 1)
C0MCTLi(i=0 to 5) 0230
16,
0231
16,
0232
16,
0233
16,
0234
16,
0235
16
00
16
C0MCTLi(i=6 to 11) 0236
16,
0237
16,
0238
16,
0239
16,
023A
16,
023B
16
00
16
C0MCTLi(i=12 to 15) 023C
16,
023D
16,
023E
16,
023F
16
00
16
RW
When receive,
NewData
When transmit,
SentData
When receive,
InvalData
When transmit,
TrmActive
MsgLost
RemActive
RspLock
Remote
TrmReq
RecReq
Transmit/receive
finished flag
Using BasicCan mode
0: Data flame received (status)
1: Remote flame received (status)
Not using BasicCan mode
0: Data flame
1: Remote flame
0: Automatic ans w ering of remote flame enab le
1: Automatic ans w ering of remote flame disab le
0: Transmit/receive data flame
1: Transmit/receive remote flame
0: Reception not requested
1: Reception requested
0: Transmission not requested
1: Transmission requested
Transmitting/
receiving flag
Overwrite flag
Remote flame
transmit/receive
status flag
Automatic ans wering
disable bit
Remote frame
set bit
Receive
request bit
Transmit
request bit
0: Over run error not occurred
1: Over run error occurred (Note 2)
0: Not transmitted yet 0: Not received yet
1: Finished transmitting 1: Finished receiving
When transmitting When receiving
0: Stopped transmitting 0: Stopped receiving
1: Accepted tr ansmit request 1: Storing receiv ed data
When transmitting When receiving
Bit name Function
Bit
symbol
Note 1: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
Note 2: "0" can be set. When set to "1", the previous value is remained.
(Note 2)
(Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.25. CAN0 message slot i control register
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
227
20. CAN0 message slot i control register
Bit 0: Transmission finished flag /reception finished flag (SentData, NewData)
This bit indicates that the CAN module finished transmitting or receiving a message.
• For transmit slots
The bit is set to 1 when the CAN module finished transmitting from the message slot.
This bit is cleared by writing 0 in software. However, it cannot be cleared when the TrmActive
(transmit/receive status) bit = 1.
• For receive slots
The bit is set to 1 when the CAN module finished receiving a message normally that is to be stored
in the message slot.
This bit is cleared by writing 0 in software. However, it cannot be cleared when the InvalData (trans-
mit/receive status) bit = 1.
Note 1: Before reading received data from the message slot, be sure to clear the NewData (transmis-
sion/reception finished status) bit. Also, if the NewData bit is set to 1 after readout, it means
that new received data has been stored in the message slot while reading out from the slot,
and that the read data contains an indeterminate value. In this case, discard the read data
and clear the NewData bit before reading out from the slot again.
Note 2: The NewData bit is not set by a completion of remote frame transmission or reception.
Bit 1: Transmitting flag /receiving flag (TrmActive, InvalData)
This bit indicates that the CAN module is transmitting or receiving a message, with the message slot
being accessed. The bit is set to 1 when the CAN module is accessing the message slot and set to 0
when not accessing the message slot.
• For transmit slots
This bit is set to 1 when the message slot has its transmit request accepted. If the message slot
failed in arbitration, this bit is cleared to 0 by occurrence of a CAN bus error or completion of trans-
mission.
• For receive slots
This bit is set to 1 when the CAN module is receiving a message, with the received message being
stored in the message slot. Note that the value read out from the message slot while this bit remains
set is indeterminate.
Bit 2: Overwrite flag (MsgLost)
This bit is useful for the receive slots, those that are set for reception. This bit is set to 1 when while
the message slot contains an unread received message, it is overwritten by a new received mes-
sage.
This bit is cleared by writing 0 in software.
Bit 3: Remote frame transmit/receive status flag (RemActive)
This bit functions differently for slots 0–13 and slots 14, 15.
• For slots 0–13
If the slot is set for remote frame transmission (or reception), this bit is set to 1. Then, when the slot
finished transmitting (or receiving) a remote frame, this bit is cleared to 0.
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
228
• For slots 14 and 15
The RemActive bit functions differently depending on how the CAN Control Register’s BasicCAN
(BasicCAN mode) bit is set.
When BasicCAN = 0 (operating normally), if the slot is set for remote frame transmission (or recep-
tion), the RemActive bit is set to 1.
When BasicCAN = 1 (operating in BasicCAN mode), the RemActive bit indicates which frame type
of message was received. During BasicCAN mode, slots 14 and 15 store the received data whether
it be a data frame or a remote frame.
If RemActive = 0, it means that the message stored in the slot is a data frame.
If RemActive = 1, it means that the message stored in the slot is a remote frame.
Bit 4: Automatic answering disable bit (RspLock)
This bit is useful for the slots set for remote frame reception, indicating the processing to be per-
formed after receiving a remote frame.
If this bit is set to 0, the slot automatically changes to a transmit slot after receiving a remote frame
and the message stored in the slot is transmitted as a data frame.
If this bit is set to 1, the slot stops operating after receiving a remote frame.
Note 1: This bit must always be set to 0 for any slots other than those set for remote frame reception.
Bit 5: Remote frame set bit (Remote)
Set this bit to 1 for the message slots that handle a remote frame.
Message slots can be set to handle a remote frame in the following two ways.
• Set to transmit a remote frame and receive a data frame
The message stored in the message slot is transmitted as a remote frame. The slot automatically
changes to a data frame receive slot after it finished transmitting.
However, if it receives a data frame before it finishes transmitting a remote frame, the data frame is
stored in the message slot and the remote frame is not transmitted.
• Set to receive a remote frame and transmit a data frame
The slot receives a remote frame. The processing to be performed after receiving a remote frame
depends on how the RspLock (automatic answering disable) bit is set.
Bit 6: Receive request bit (RecReq)
Set this bit to 1 when using any message slot as a receive slot.
Set this bit to 0 when using any message slot as a data frame transmit or remote frame transmit slot.
If the TrmReq (transmit request) bit and RecReq (receive request) bit both are set to 1, the operation
of the CAN module is indeterminate.
Bit 7: Transmit request bit (TrmReq)
Set this bit to 1 when using any message slot as a transmit slot.
Set this bit to 0 when using any message slot as a data frame receive or remote frame receive slot.
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
229
Note 1: There is a total of 16 CAN0 message slots for transmission and reception uses, respectively.
Each message slot can be selected for use as a transmit or a receive slot.
Note 2: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
CAN0 slot buffer select register
Symbol Address When reset (Note 2)
C0SBS 0240
16
00
16
RW
SBS00
SBS01 CAN0 message
slot buffer 0
number select bit
CAN0 message
slot buffer 1
number select bit
SBS02
SBS03
SBS10
SBS11
SBS12
SBS13
0 0 0 0 : slot 0
0 0 1 0 : slot 1
0 0 1 1 : slot 2
0 1 0 0 : slot 3 (Note 1)
(Note 1)
Bit name Function
Bit
symbol
b3 b2 b1 b0
1 1 0 0 : slot 12
1 1 0 1 : slot 13
1 1 1 0 : slot 14
1 1 1 1 : slot 15
•
•
••
•
•
0 0 0 0 : slot 0
0 0 1 0 : slot 1
0 0 1 1 : slot 2
0 1 0 0 : slot 3
b3 b2 b1 b0
1 1 0 0 : slot 12
1 1 0 1 : slot 13
1 1 1 0 : slot 14
1 1 1 1 : slot 15
•
•
•
•
•
•
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.26. CAN0 slot buffer select register
21. CAN0 slot buffer select register
Bits 0-3: CAN0 message slot buffer 0 slot number select bits (SBS0)
The message slot whose number is selected with these bits appears in CAN0 message slot buffer 0.
Bits 4-7: CAN0 message slot buffer 1 slot number select bits (SBS1)
The message slot whose number is selected with these bits appears in CAN0 message slot buffer 1.
The selected message slot can be identified by reading the message slot buffer.
A message written to the message slot buffer is stored in the selected message slot.
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
230
CAN0 message slot buffer i standard ID1(i=0,1) (Note)
Symbol Address When reset
C0SLOTi_1(i=0,1) 01E116, 01F116 Indeterminate
RW
SID0
SID1
SID2
SID3
SID4
SID5
Standard ID0 Message slot j (j=0 to 15)
Standard ID1
Standard ID2
Standard ID3
Standard ID4
Standard ID5
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Note: CAN0 message slot j standard ID1 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.
CAN0 message slot buffer i standard ID0 (i=0,1) (Note)
Symbol Address When reset
C0SLOTi_0(i=0,1) 01E0
16,
01F0
16
Indeterminate
RW
SID6
SID7
SID8
SID9
SID10
Standard ID6
Standard ID7
Standard ID8
Standard ID9
Standard ID10
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Note: CAN0 message slot j standard ID0 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.
Figure 1.22.27. CAN0 message slot buffer i standard ID0 and ID1
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
231
CAN0 message slot buffer i extend ID1
(i=0,1) (Note 1,2)
Symbol Address When reset
C0SLOTi_3(i=0,1) 01E3
16,
01F3
16
Indeterminate
RW
EID6
EID7
EID8
EID9
Extended ID6 Message slot j (j=0 to 15)
Extended ID7
Extended ID8
Extended ID9
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
EID10
EID11
Extended ID10
Extended ID11
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
EID12
EID13
Extended ID12
Extended ID13
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Bit name Function
Bit
symbol
Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID1 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.
b7 b6 b5 b4 b3 b2 b1 b0
CAN0 message slot buffer i extend ID0 (i=0,1) (Note 1, 2)
Symbol Address When reset
C0SLOTi_2(i=0,1) 01E2
16,
01F2
16
Indeterminate
RW
EID14
EID15
Extended ID14
Extended ID15
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
EID16
EID17
Extended ID16
Extended ID17
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Bit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID0 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.
Figure 1.22.28. CAN0 message slot buffer i extended ID0 and ID1
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
232
CAN0 message slot buffer i data length code (i=0,1)(Note)
Symbol Address When reset
C0SLOTi_5(i=0,1) 01E5
16,
01F5
16
Indeterminate
RW
Message slot j (j=0 to 15)
DLC0
DLC1
DLC2
DLC3
Data length set bit
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Bit name Function
Bit
symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note : CAN0 message slot j data length code (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.
CAN0 message slot buffer i extend ID2 (i=0,1) (Note 1,2)
Symbol Address When reset
C0SLOTi_4(i=0,1) 01E4
16,
01F4
16
Indeterminate
RW
EID0
EID1
EID2
EID3
Extended ID0 Message slot j (j=0 to 15)
Extended ID1
Extended ID2
Extended ID3
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
EID4
EID5
Extended ID4
Extended ID5
Message slot j (j=0 to 15)
Message slot j (j=0 to 15)
Bit name Function
Bit
symbol
Note 1: When receive slot is standard ID format, EID bits are indeterminate when saving received data.
Note 2: CAN0 message slot j extend ID2 (j=0 to 15) is stored in this register. j is selected with the slot
buffer select register.
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.22.29. CAN0 message slot buffer i extended ID2 and CAN0 message slot buffer i data lengthcode
CAN Module
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
233
CAN0 message slot buffer i time stamp high
(i=0,1) (Note)
Symbol Address When reset
C0SLOTi_14(i=0,1) 01EE
16,
01FE
16
Indeterminate
R W
Function Setting range
Message slot j time stamp high (j=0 to 15) 00
16
to FF
16
Note : CAN0 message slot j time stamp high (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.
b7 b0
CAN0 message slot buffer i time stamp low (i=0,1) (Note)
Symbol Address When reset
C0SLOTi_15(i=0,1) 01EF16, 01FF16 Indeterminate
R W
Function Setting range
Message slot j time stamp low (j=0 to 15) 00
16
to FF
16
Note : CAN0 message slot j time stamp low (j=0 to 15) is stored in this register. j is selected with the
slot buffer select register.
b7 b0
Figure 1.22.30. CAN0 message slot buffer i data m and CAN0 message slot buffer i time stamp
CAN0 message slot buffer i data m
(i=0,1 m=0 to 7)
Symbol Address When reset
C0SLOT0_n(n=m+6,m=0 to 3) 01E616, 01E716, 01E816, 01E916 Indeterminate
C0SLOT0_n(n=m+6,m=4 to 7) 01EA16, 01EB16, 01EC16, 01ED16 Indeterminate
C0SLOT1_n(n=m+6,m=0 to 3) 01F616, 01F716, 01F816, 01F916 Indeterminate
C0SLOT1_n(n=m+6,m=4 to 7) 01FA16, 01FB16, 01FC16, 01FD16 Indeterminate
R W
Function Setting range
Message slot j data m (j=0 to 15, m=0 to 7) 0016 to FF16
Note: j is selected with the slot buffer select register
(Note)
b7 b0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
234
When receive ID is "6F316"
Write to C0AFS
0011001100011011
SID4 SID3 SID2 SID1 SID0 SID10SID9 SID8 SID7 SID6
11011110011
"6" "F" "3"
"D" "E" "3"
SID10 SID0
Read from C0AFS
0000100011011110
Divide to 8 bits and 3 bits
Receive ID
"D" "E""08
16
"
Bit search information Address search information
SID5
b7b8 b0b15
b7b8 b0
b7 b0
b15
01
16
02
16
04
16
08
16
10
16
20
16
40
16
80
16
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0
16
1
16
2
16
3
16
4
16
5
16
6
16
7
16
Bit search information Low-order 3 bits of receive ID
8 bits 3 bits
Because the value of
these three bits is 3,
bit 3 in the table below
is 1. (If the value of
these three bits is 4,
bit 4 in the table below
is 1.)
b3
CAN0 acceptance filter support register
Symbol Address When reset (Note)
C0AFS 024516,024416 010016
RW
Function Setting range
Produces receive ID determination data
000016 to FFFF16
Note: This applies when the CAN module is supplied with a clock by setting the sleep mode control bit
(bit 0 at address 0242
16
) to 1 after reset.
b15 b0b8 b7
b15 b0
SID5 SID4 SID3 SID2 SID1 SID0
SID10
SID9 SID8 SID7 SID6
SID5 SID4 SID3
CSID2 CSID1 CSID0
SID10
SID9 SID8 SID7 SID6
CSID5 CSID4 CSID3CSID7 CSID6
Write
Read
3-8 decode b7
b8
b15 b0
From the receive ID of the standard for-
mat, this register produces data with
which to search the data table. After
searching the table using this data, the
CAN module determines whether the
receive ID is valid or not.
007
16
"0" 006
16
"0" 005
16
"0" 004
16
"0" 003
16
"0" 002
16
"0" 001
16
"1" 000
16
"0"
00F
16
"1" 00E
16
"0" 00D
16
"0" 00C
16
"0" 00B
16
"0" 00A
16
"0" 009
16
"0" 008
16
"0"
6F7
16
"0" 6F6
16
"0" 6F5
16
"0" 6F4
16
"0" 6F3
16
"1" 6F2
16
"0" 6F1
16
"0" 6F0
16
"0"
7F7
16
"0" 7F6
16
"0" 7F5
16
"0" 7F4
16
"0" 7F3
16
"0" 7F2
16
"0" 7F1
16
"0" 7F0
16
"1"
7FF
16
"0" 7FE
16
"0" 7FD
16
"1" 7FC
16
"0" 7FB
16
"0" 7FA
16
"0" 7F9
16
"0" 7F8
16
"0"
Top+00
16
Top+01
16
Top+FE
16
Top+FF
16
Top+DE
16
b7 b6 b5 b4 b3 b2 b1 b0
Address search information Bit search information
Figure 1.22.31. CAN0 acceptance filter support register
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O
235
Intelligent I/O
Intelligent I/O uses multifunctional I/O ports for time measurement, waveform generation, clock-synchro-
nous/asynchronous (UART) serial I/O, IE bus (Note) communications, HDLC data processing and more. A
single Intelligent I/O group comes with one 16-bit base timer for free running, eight 16-bit registers for time
measurement and waveform generation, and two shift registers for 8-bit and 16-bit communications.
The M32C/83 has four internal Intelligent I/O groups. Table 1.23.1 lists functions by group.
Table 1.23.1. List of functions of intelligent I/O
Function Group 0 Group 1 Group 2 Group 3 Group 0,1
cascaded
Configuration
•Base timer 1 1 1 1 1
•TM 4ch(2ch) –– – –
•TM/WG register (shared) 4chs(1ch) 4chs(2chs) –– 8chs(3chs)
•WG register –4chs(1ch) 8chs 8chs(3chs) 8chs(2chs)
•Communication shift register 8bits X 2chs 8bits X 2chs 8bits X 2chs ––
Time measurement functions Max. 8chs Max. 4chs –– Max. 8chs
(3chs) (2chs) (3chs)
•Digital filter function √√–– √
•Trigger input prescale function 2chs 2chs –– 2chs
•Gate function for trigger input 2chs 2chs –– 2chs
WG function Max. 4chs Max. 8chs Max. 8chs Max. 8chs Max. 8chs
(1ch) (3chs) (3chs) (2chs) (1ch)
•Single phase waveform output √√√ √ √
•Phase delayed waveform output √√√ √ √
•Set/reset waveform output √√√ √ √
•Bit modulation PWM output ––√√ –
•Real-time port output ––√√ –
•Parallel real-time port output ––√√ –
Communication functions
•Bit length 8 bits fixed 8 bits fixed Variable length ––
•Communication mode
1. Clock synchronous serial I/O √√√ ––
2. UART √√–– –
3. HDLC data processing √√–– –
4. IE Bus sub set ––√––
Note 1: IE Bus is a trademark of NEC.
Note 2: 100-pin specification are in parentheses.
√ : Present
– : Not present
TM:Time Measurement
WG:Waveform Genaration
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O
236
Ch0 TM/WG
register
16-bit
Base timer
PWM
output
Reset
Reset request from
communication block
Gr1 base timer reset
2 x (n+1)
Divider
f
1
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
Edge
select
Digital
filter
PWM
output
PWM
output
INPC00
INPC01
/ISCLK0
INPC02
/ISRxD0
INPC03
INPC04
INPC05
INPC06
INPC07
BTS
BT0S
DF
DF
DF
DF
DF
DF
DF
DF GT
GT PR
PR
8
/Ch0 to ch7
interrupt request signal
OUTC00/
IST x D0
OUTC01/
ISCLK0
OUTC04
OUTC05
Arbitration
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Special
interrupt
check
4
/
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
4
/
Buffer
register
Data register
(8-bit)
Shift
register
4
/
Prescale
function
Prescale
function
Start bit
generation circuit
Bit insert circuit
SOF
generation circuit
Parity bit
generation circuit
Stop bit
generation circuit
Transmit latch
Transmit data
generation circuit
Transmit
CRC
Clock wait
control
circuit
SI/O transmit
buffer register
(8-bit)
Transmit
register
Transmit
buffer
Transmit output
register
(8-bit)
SI/O receive
buffer register
(8bit)
Receive data
generation circuit
Start bit
check
Parity bit
check
Bit insert
check
Stop bit
check
Receive
CRC
Receive input register
(8bit)
Polarity
reversing
Clock
selector
Clock
selector
TM input to Gr1
(When cascaded)
Start bit
HDLC data
process interrupt
Transmit interrupt
HDLC data
transmit interrupt
Receive interrupt
Special
communication
interrupt
WG input to Gr1
(When cascaded)
Polarity
reversing
Transmit
buffer
Receive
buffer
Receive shift
register
Receive shit
register
TM: Time Measurement
WG: W av ef orm Generation
Receive
buffer
Ch1 TM/WG
register
Ch2 TM register
Ch3 TM register
Ch4 TM/WG
register
Ch5 TM/WG
register
Ch6 TM register
Ch7 TM register
Transmission
Reception
Base timer carry output
(Note 1)
(Note 1)
Transmit
shift register
Note 1: These pins aren't connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.
Block diagrams for groups 0 to 3 are given in Figures 1.23.1 to 1.23.4.
Figure 1. 23. 1. Block diagram of intelligent I/O group 0
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O
237
Transmission
Reception
Ch1 TM/WG
register
Ch2 TM/WG
register
Ch3 TM/WG
register
Ch4 TM/WG
register
Ch5 TM/WG
register
Ch6 TM/WG
register
Ch7 TM/WG
register
PWM
output
2 x (n+1)
Divider
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Gate
function
Edge
select
Digital
filter
Edge
select
Digital
filter
PWM
output
PWM
output
INPC11
INPC12
INPC16
INPC17
BTS
BT1S
DF
DF
DF
DF GT
GT PR
PR
8
/
OUTC10
/IST x D1
/BE1OUT
OUTC11
/ISCLK1
OUTC14
OUTC15
Arbitration
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Comparator
(8-bit)
Special
interrupt
check
4
/
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
Comparison
register
(8-bit)
4
/
Buffer
register
Data register
(8-bit)
Shift
register
4
/
Prescale
function
Prescale
function
Start bit
generation circuit
Bit insert circuit
SOF
generation circuit
Parity bit
generation circuit
Stop bit
generation circuit
Transmit latch
Transmit data
generation circuit
Clock wait
control
circuit
SI/O transmit
buffer register
(8-bit)
Transmit
register
Transmit
buffer
Transmit output
register (8-bit)
Receive shift
register
Receive data
generation circuit
Start bit
check
Parity bit
check
Bit insert
check
Stop bit
check
Receive
CRC
Clock
selector
Clock
selector
PWM
output
OUTC16
OUTC17
OUTC12
OUTC13
f
1
TM input from Gr0
(When cascaded)
WG input from Gr0
(When cascaded) Ch0 TM/WG
register
16bits
Base timer
Reset
Reset request from
communication block
Gr0 base timer reset
Ch0 to ch7
interrupt request signal
Transmit interrupt
Transmit
CRC
Polarity
reversing
Transmit
buffer
HDLC data
transmit interrupt
Receive interrupt
SI/O receive
buffer register
(8bit)
Receive
buffer
Special
communication
interrupt
TM: Time Measurement
WG: W av ef orm Generation
Polarity
reversing
Receive input register
(8bit)
Receive shit
register
Receive
buffer
HDLC data
process interrupt
Start bit
Base timer carry input
(Note)
Note 1: Ch0 TM register can be used in 32-bit cascade connections.
Note 2: These pins aren't connected with external pins in 100-pin version.
Note 3: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.
(Note 2)
(Note 2)
Transmit shift
register
Figure 1. 23. 2. Block diagram of intelligent I/O group 1
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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PWM
output
control
ch0 WG register
ch1 WG register
ch2 WG register
ch3 WG register
ch4 WG register
ch5 WG register
ch6 WG register
ch7 WG register
16-bit
Base timer
Reset Reset request from communication block
Gr1 base timer reset
2 x (n+1)
Divider ch0 interrupt request signal
f1
BT2S
BTS
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
PWM
output
control
PWM
output
control
OUTC20
/ISTxD2
PWM
output
control OUTC21
/ISCLK2
OUTC22
OUTC23
OUTC24
OUTC25
OUTC26
OUTC27
Waveform
generation
interrupt
Clock
selector
Serial I/O receive interrupt
Serial I/O transmit interrupt
Input
inverted Receive shift
register (8-bit)
Output control
function
IE start bit interrupt
8
ISCLK21
ISRxD21
ISRxD20Digital
filter DF
0
1
00
01
IPS4,5
Real time port
output value
Digital
filter DF
0
1
0
1
IPS6
ISCLK20
10
ISRxD22
Bit
counter Transmit
register (8-bit)
Transmit buffer
register(8-bit)
Transmit parity
operation
Output
inverted
Arbitration
lost detect
Byte counter
IE, serial I/O
interrupt control IE receive interrupt
IE transmit interrupt
8
ACK operation
Receive parity
operation
Start bit
detect
Receive buffer
register (8-bit)
ID detect
ALL "F" detect
Address detect
Statement
length detect
Transmit
latch
WG: W av ef orm Generation
Note 1: These pins aren't connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.
(Note 1)
Figure 1. 23. 3. Block diagram of intelligent I/O group 2
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ch4 mask register
ch5 mask register
ch6 mask register
ch7 mask register
PWM
output
control
ch0 WG register
ch1 WG register
ch2 WG register
ch3 WG register
ch4 WG register
ch5 WG register
ch6 WG register
ch7 WG register
16-bit
Base timer
Reset
2 x (n+1)
Divider
f
1
BT3S
BTS
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
Bit modulation
PWM
PWM
output
control
PWM
output
control
OUTC3
0
PWM
output
control OUTC3
1
OUTC3
2
OUTC3
3
OUTC3
4
OUTC3
5
OUTC3
6
OUTC3
7
Waveform
generation
interrupt
8
Real time port
output value
Gr2 base timer reset
ch0 interrupt request signal
WG: Waveform Generation
Note 1: These pins aren’t connected with external pins in 100-pin version.
Note 2: Each register becomes reset status after supplying a clock by setting of the base timer control register 0.
(Note 1)
Figure 1. 23 . 4. Block diagram of intelligent I/O group 3
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Group i base timer control register 0 (i=0 to 3) (Note)
Symbol Address When reset
GiBCR0 (i=0 to 3) 00E2
16
, 0122
16
, 0162
16
, 01A2
16
00
16
RWBit name Function
Bit
symbol
: Clock stop
: Must not be set
: Must not be set
: f
1
b1
0
0
1
1
b0
0
1
0
1
BCK0
BCK1
DIV0
Count source
select bit
DIV1
Count source
division ratio
select bit
DIV2
DIV3
IT Base timer
interrupt select bit 0 : Bit 15 overflow
1 : Bit 14 overflow
DIV4
Divides the count source by 2x(n + 1)
for a setting value n (n = 0 to 31).
(n=0) 0 0 0 0 0 : Division by 2
(n=1) 0 0 0 0 1 : Division by 4
(n=2) 0 0 0 1 0 : Division by 6
:
(n=30) 1 1 1 1 0 : Division by 62
(n=31) 1 1 1 1 1 : No division
b6 b5 b4 b3 b2
Note: In cascade connections, set the same value to the base timer control register 0 of groups 0 and 1.
b7 b0
Base timer (group 0 to 3)
The internally generated count source is a free run source. Base timer specifications are given in Table
1.23.2, base timer registers in Figures 1.23.5 to 1.23.9 and a block diagram in Figure 1.23.10.
Figure 1. 23. 5. Base timer-related register (1)
Group i base timer register (i=0 to 3)
Symbol Address When reset
GiBT (i=0,1) 00E116, 00E016, 012116, 012016 Indeterminate
GiBT (i=2,3) 016116, 016016, 01A116, 01A016 Indeterminate
RWFunction
(b7) b0
Setting range
Count value of the 16-bit base timer 000016 to FFFF16(Note)
Note : When this register is read while the base timer is being reset, the value is indeterminate.
The counter value is read if the register is output while the timer is running.
Written value while the base timer is being reset is ignored. The count starts from "000016" after
starting the base timer. When writing value while the base timer is operating, the count starts from
the written value immediately after written.
b8b15 b7(b0)
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Figure 1. 23. 6. Base timer-related register (2)
Group i base timer control register 1 (i=0,1)
Symbol Address When reset
GiBCR1 (i=0,1)
00E3
16
, 0123
16
00
16
R WBit name Function
Bit
symbol
b6
0
0
1
1
b5
0
1
0
1
RST0
RST1
RST2
Base timer reset
cause select bit 0
Base timer
start bit
BTS
UD0
CAS
UD1
Base timer reset
cause select bit 1
Base timer reset
cause select bit 2
Up / down
control bit
0: Synchronizes the base timer reset
without resetting the timer
1: Synchronizes the base timer reset
with resetting the timer
0: Does not reset the base timer when
it matches WG register ch0
1: Reset the base timer when it matches
WG register ch0
0: Base timer reset
1: Base timer count start
: Up mode
: Up / down mode (triangle wave)
: Two-phase pulse signal processing
mode (Note 4)
: Must not be set
(Note1)
Groups 0 and 1
cascaded function
select bit
0: 16-bit TM / WG function
1: 32-bit TM / WG function
(Note 5)
(Note 2)
(Note 3)
0: Does not reset the base timer when
input to the INT pin is "L" level
1: Reset the base timer when input to
the INT pin is "L" level
Note 1: With group 0, reset synchronizing with group 1 base timer. With group 1, reset synchronizing with
group 0 base timer.
Note 2: The base timer is reset 2 clock cycles after it matches waveform generation register ch0.
Note 3: With group 0, the base timer is reset when "L" level is input to INT0. With group 1, it resets when
"L" level is input to INT1.
Note 4:Operation of this mode is equal to Timer A two-phase pulse signal processing except count value.
Note 5: In cascade connections, set to "8116" for group 0 base timer control register 1. Set to "1000 0XX02"
for group 1 base timer control register 1.
Reserved bit Must always set to "0".
b7 b0
0
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Group 2 base timer control register 1
Symbol Address When reset
G2BCR1 016316 0016
RWBit name Function
Bit
symbol
Note : The base timer is reset 2 clock cycles after it matches waveform generation register ch0.
b7 b0
RST0
RST1
RST2
Base timer
reset cause
select bit 0
Base timer
start bit
BTS
Base timer
reset cause
select bit 1
Base timer
reset cause
select bit 2
0 : Synchronizes the group 1 base timer reset
without resetting the timer
1 : Synchronizes the group 1 base timer reset
with resetting the timer
0 :
Does not reset the base timer when it matches WG
register ch0
1 :
Reset the base timer when it matches WG register ch0
0 : Does not reset the base timer when a reset is requested
from the communication additional circuit
1 :
Reset the base timer when a reset is requested from
the communication additional circuit
Must always set to "0".
0 : Base timer reset
1 : Base timer count start
Parallel real-time
port function
select bit
PRP 0 : Not use
1 : Use
(Note)
RST3
UD0
UD1 Reserve bit
Reserve bit
Must always set to "0".
000
Figure 1. 23. 7. Base timer-related register (3)
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Figure 1. 23. 8. Base timer-related register (4)
Group 3 base timer control register 1
Symbol Address When reset
G3BCR1 01A316 0XX0 X0002
RWBit name Function
Bit
symbol
Note : The base timer is reset 2 clock cycles after it matches waveform generation register ch0.
b7 b0
RST0
RST1
Base timer
reset cause
select bit 0
Base timer
start bit
BTS
Base timer
reset cause
select bit 1
0 : Synchronizes the base timer 2 reset
without resetting the timer
1 : Synchronizes the base timer 2 reset
with resetting the timer
0 :
Does not reset the base timer when it matches WG
register ch0
1 :
Reset the base timer when it matches WG register ch0
Nothing is assigned. When write, set to "0".
When read, the content is indeterminate.
0 : Base timer reset
1 : Base timer count start
Parallel real-time
port function
select bit
PRP 0 : Not use
1 : Use
(Note)
WG: Waveform Generation
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Must always set to "0". Reserved bit
0
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Figure 1. 23. 9. Base timer-related register (5)
Base timer start register
(Note 1, 2)
Symbol Address When reset
BSTR
0164
16
XXXX 0000
2
RWBit name Function
Bit
symbol
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
BT0S
BT1S
BT2S
Group 0 base timer
start bit
BT3S
0 : Base timer reset
1 : Base timer count start
0 : Base timer reset
1 : Base timer count start
0 : Base timer reset
1 : Base timer count start
0 : Base timer reset
1 : Base timer count start
Group 1 base timer
start bit
Group 2 base timer
start bit
Group 3 base timer
start bit
(Note 2)
b7 b0
Note 1: When starting multiple base timer with this register at the same time (including group 0 and 1
cascaded connection), do the followings. Do not need when starting base timer individually.
* Set the same values to each group’s base timer clock division ratio ( bits 6 to 0 of base timer
control register).
* When changing base timer clock division ratio, start base timer twice with the following
procedure.
(1) Start each group base timer using the base timer start register.
(2) After one clock, stop base timer by setting "00
16
" to base timer start register.
(3) Further after one clock, restart each group base timer using the base timer start register.
Note 2: This register is enabled after when group 2 base timer control register 0 is set.
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Table 1. 23.2. Base timer specifications
Item Specifications
Count source f1/2(n+1)
n: Set by count source division ratio select bit
(n=0 to 31, however, please note when n=31, the counter source is not divided.)
Count operation Up count / down count
Count start condition Writes "1" for the start bit in the base timer start register or base timer control
register 1. (After writing the bit, the base timer resets to "000016" and
counting starts.)
Count stop condition Writes "0" for both the start bit in the base timer start register and base timer
control register 1.
Count reset condition Group 0, 1 (1) Synchronizes and resets the base timer with that of another group.
Group 0: Synchronizes base timer reset with the group 1 base timer.
Group 1: Synchronizes base timer reset with the group 0 base timer.
(2) Matches the value of the base timer to the value of WG register 0.
(3) Input "L" to INT pin
Group 0 : INT 0 pin Group 1 : INT 1 pin
The above 3 factors can be used in conjunction with one another.
Group 2, 3 (1) Synchronizes and resets the base timer with that of another group.
Group 2: Synchronizes base timer reset with the group 1 base timer.
Group 3: Synchronizes base timer reset with the group 2 base timer.
(2) Matches the value of the base timer to the value of WG register 0.
(3) Reset request from communication additional circuit (group 2 only)
The above 3 factors can be used in conjunction with one another.
Interrupt request generation timing When bit 14 or bit 15 overflows
Read from timer •When the base timer is running
The count is output when the base timer is read.
•When the base timer not running
An undefined value is output when the base timer is read.
Write to timer Possible. Values that are written while the base timer is resetting are
ignored. If values are written while the base timer is running, counting
continues after the values are written.
f1
2(n+1) divider
RST0
RST1
RST2
Other base timer reset
Base timer i
b14 b15
Overflow signal
Base timer i
interrupt request
Count source
switching select bit
Interrupt timing
select bit
Reset signal
BT0S
BTS
Input "L" to INT pin
Matched to waveform
generation register 0
(Group 0,1)
Figure 1. 23.10. Base timer block diagram
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Figure 1. 23.11. Operation timing of base timer
FFFF16
800016
Contents of counter
000016
b14
(Overflow signal)
b15
"1"
"0"
"0"
"1"
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Figure 1. 23. 12. Time measurement-related register (1)
Time measurement (group 0 and 1)
Synchronizes external trigger input and stores the base timer value in the time measurement register j.
Specifications for the time measurement function are given in Table 1.23.3, the time measurement control
registers in Figures 1.23.12 to 1.23.13, and the operating timing of the time measurement function in Figure
1.23.14 and 15.
Group i time measurement control register j (i=0,1/j=0 to 7) (Note 1)
Symbol Address When reset
GiTMCRj(i=0/j=0 to 3) 00D816, 00D916, 00DA16, 00DB16 0016
GiTMCRj(i=0/j=4 to 7) 00DC16, 00DD16, 00DE16, 00DF16 0016
GiTMCRj(i=1/j=1, 2) 011916, 011A16 0016
GiTMCRj(i=1/j=6, 7) 011E16, 011F16 0016
RWBit name Function
Bit
symbol
CST0
CST1
DF0
Time measurement
trigger select bit
DF1
Gate function
select bit
GT
GOC
PR
GSC
Digital filter function
select bit
Gate function release
select bit
0 : Gate function not used
1 : Gate function used
Gate function release
bit
Prescaler function
select bit
b1
0
0
1
1
b0
0
1
0
1
: No time measurement
: Rising edge
: Falling edge
: Both edges
b3
0
0
1
1
b2
0
1
0
1
: No digital filter
: Must not be set
: Base timer clock
: f1
(Note 2, 4)
(Note 2, 3)
(Note 2)
0 : No effect
1 : Release the gate when it
matches WG register
0 : No effect
1 : Gate released
0 : Not used
1 : Used
Note 1: The 16-bit time measurement function is available for 8 channels (ch0 to 7) with group 0 and 4 channels
(ch1, 2, 6 and 7) with group 1. When using the 16-bit time measurement function, use the time
measurement register values for ch0, 3, 4 and 5 of group 1 as they are, or, if writing values, write "0016".
The 32-bit time measurement function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1.
When using the 32-bit time measurement function, write the same value for time measurement registers
of similar channels in groups 0 and 1.
Note 2: These functions are available only for time measurement ch6 and 7 (time measurement registers 6
and 7). For ch0 to 5, set "0" for bits 4 to 7 of the time measurement register.
Note 3: These bits are valid only when "1" is set for the gate function select bit.
Note 4: The gate function cannot be used at the same time as the 32-bit time measurement function.
(Note 2, 3)
WG: Waveform Generation
b7 b0
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Group i time measurement register j (i=0,1/j=0 to 7)
Symbol Address When reset
GiTMj(i=0/j=0 to 2) 00C1
16,
00C0
16,
00C3
16,
00C2
16,
00C5
16,
00C4
16
0000
16
GiTMj(i=0/j=3 to 5) 00C7
16,
00C6
16,
00C9
16,
00C8
16,
00CB
16,
00CA
16
0000
16
GiTMj(i=0/j=6,7) 00CD
16,
00CC
16,
00CF
16,
00CE
16
0000
16
GiTMj(i=1/j=0 to 2) 0101
16,
0100
16,
0103
16,
0102
16,
0105
16,
0104
16
0000
16
GiTMj(i=1/j=3 to 5) 0107
16,
0106
16,
0109
16,
0108
16,
010B
16,
010A
16
0000
16
GiTMj(i=1/j=6,7) 010D
16,
010C
16,
010F
16,
010E
16
0000
16
RWFunction Setting range
b15
(b7) b8
(b0)
When an event occures, the value of the base
timer is stored.
b7 b0
Group i time measurement prescale register j (i=0,1/j=6,7)
Symbol Address When reset
GiTPRj(i=0/j=6, 7) 00E4
16
, 00E5
16
00
16
GiTPRj(i=1/j=6, 7) 0124
16
, 0125
16
00
16
RWFunction Setting range
Prescales time measurement events.
(Generates the time measurement request after
an n + 1 count.) 00
16 to
FF
16
(Note)
Note : This function is only built into time measurement ch6 and 7 of Intelligent I/O groups 0 and 1.
b7 b0
Figure 1. 23. 13. Time measurement-related register (2)
Group i function select register (i=0, 1)
Symbol Address When reset
GiFS (i=0,1) 00E7
16
, 0127
16
00
16
RWBit name
Bit
symbol
b7 b0
FSC0
FSC1
FSC2
Ch0 TM/WG function
select bit
FSC3
FSC4
FSC5
FSC7
Function
FSC6
Whether the corresponding port
functions as TM or WG is selected
0 : WG function is selected
1 : TM function is selected
Note : In group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
In group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
Ch1 TM/WG function
select bit
Ch2 TM/WG function
select bit
Ch3 TM/WG function
select bit
Ch4 TM/WG function
select bit
Ch5 TM/WG function
select bit
Ch6 TM/WG function
select bit
Ch7 TM/WG function
select bit
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Table 1. 23.3. Specifications of time measurement function
Item Specifications
Time resolution t=1/(base timer count source)
Trigger input polarity select •Rising edge •Falling edge •Both edges
Measurement start condition (Note) Write "1" to the function enable bit
Measurement stop condition Write "0" to the function enable bit
Time measurement timing •Prescaler (only ch6 and ch7) : Every the (m+1) trigger input
•No prescaler : Every trigger input
Interrupt request generation timing Same timing as time measurement
INPC pin function Trigger input pin
(Set the corresponding pin to input with the function select register)
Select function •Digital filter function
Pulses will pass when they match either f1 or the base timerclock 3 times .
•Prescaler function (only for ch6 and ch7)
Counts trigger inputs and measures time by inputting a trigger of +1 the
value of the time measurement prescale register.
•Gate function (only for ch6 and ch7)
Prohibits the reception of trigger inputs after the time measurement starts
for the first trigger input. Trigger input is newly enabled when the below
conditions are satisfied.
(1) When the base timer i matches the value in WG register j
(2) When “1” is written for the gate function release bit
This bit automatically becomes “0” after the gate function is released.
Note: On channels where both the time measurement function and waveform output function can be used, select the
time measurement function for the function select register (addresses 00E716 and 012716).
Table 1. 23.4. List of time measurement channels with prescaler function and gate function
Group Channel TM register WG register matehes signal to release gate function
ch6 TM register 6 Base timer 0 matches to WG register 4
Group 0 ch7 TM register 7 Base timer 0 matches to WG register 5
ch6 TM register 6 Base timer 1 matches to WG register 4
Group 1 ch7 TM register 7 Base timer 1 matches to WG register 5
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Figure 1. 23. 14 Operation timing of time measurement function
Delay by 1 clock
Base timer
count source
Base timer
value
Trigger input
Time measurement
interrupts request
signal
Time measurement
register
(a) When the rising edge has been selected as the trigger input polarity
(b) When both edges have been selected as the trigger input polarity
Digital filter
count source
Trigger input
Triggers signal
after passing
through digital filter Trigger signal delayed
by digital filter
Max. 3.5 clock cycles
(c) When digital filter is used (count of digital filter)
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
n n+5 n+8
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
n n+2 n+5 n+8 n+12
Base timer
count source
Base timer
value
Trigger input
Time measurement
interrupts request
signal
Time measurement
register
Signals which do not match
3 times are stripped off
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Figure 1. 23. 15. Operation timing when gate function and prescaler function is used
Base timer
counter source
Base timer
Trigger input
Time measurement
interrupts request signal
Time measurement
register
Internal time
measurement trigger
Prescaler
(a) When prescaler function is used (the value of time measurement prescaler register is "2".)
(b) When gate function is used (gate function released by matching WG register)
Base timer
counter source
Base timer
Trigger input
Internal time
measurement trigger
Function enabled
flag
Waveform generation
register match signal
Gate signal
Time measurement
register
Time measurement
interrupts request signal
WG register value (XXXX
16)
This trigger input is invalid
because of gate function.
210
FFFF
16
000016
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
n+1 n+13
2
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Group i waveform generation register j (i=0 to 3/j=0 to 7)
Symbol Address When reset
GiPOj(i=0/j=0 to 2) 00C116,00C016, 00C316,00C216, 00C516,00C416 XXXX16
GiPOj(i=0/j=3 to 5) 00C716,00C616, 00C916,00C816, 00CB16,00CA16 XXXX16
GiPOj(i=0/j=6,7) 00CD16,00CC16, 00CF16,00CE16 XXXX16
GiPOj(i=1/j=0 to 2) 010116,010016, 010316,010216, 010516,010416 XXXX16
GiPOj(i=1/j=3 to 5) 010716,010616, 010916,010816, 010B16,010A16 XXXX16
GiPOj(i=1/j=6,7) 010D16,010C16, 010F16,010E16 XXXX16
GiPOj(i=2/j=0 to 2) 014116,014016, 014316,014216, 014516,014416 XXXX16
GiPOj(i=2/j=3 to 5) 014716,014616, 014916,014816, 014B16,014A16 XXXX16
GiPOj(i=2/j=6,7) 014D16,014C16, 014F16,014E16 XXXX16
GiPOj(i=3/j=0 to 2) 018116,018016, 018316,018216, 018516,018416 XXXX16
GiPOj(i=3/j=3 to 5) 018716,018616, 018916,018816, 018B16,018A16 XXXX16
GiPOj(i=3/j=6,7) 018D16,018C16, 018F16,018E16 XXXX16
RWFunction Setting range
b15
(b7) b8
(b0)
A compared value for waveform generation
is stored.
b7 b0
0000
16 to
FFFF
16
(Note)
Note: When resetting the base timer on ch0, the timer is reset 2 clock cycles after it matches the waveform
generation register of ch0.
WG: Waveform Generation
Group 3 waveform generation mask register j (j=4 to 7)
Symbol Address When reset
G3MKj (j=4,5) 019916,019816, 019B16,019A16 XXXX16
G3MKj (j=6,7) 019D16,019C16, 019F16,019E16 XXXX16
RWFunction
Note 1: This function is provided only for the waveform generation functions on ch 4 to 7 of Intelligent I/O group 3.
Note 2: Comparison results are masked in bit positions where a "1" has been set for the register bits.
b7 b0
Setting range
Masks base timer value 000016 to FFFF16
(Note 1)
(Note 2)
(b7) (b0)
b15 b8
Waveform generation (WG) function (group 0 to 3)
Waveforms are generated when the base timer value matches the value of WG register j.
There are five mode in WG function: single phase waveform output mode (group 0 to 3), phase delayed
waveform output mode (group 0 to 3), SR (Set/Reset) waveform output mode (group 0 to 3), bit modulation
PWM output mode (group 2 and 3) and parallel real-time port output mode (group 2 and 3).
The WG function related registers are shown in Figures 1.23.16 to 1.23.19.
Figure 1. 23. 16. WG-related register (1)
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Group i waveform generation control register j (i=0 to 1/ j=0 to 7) (Note 1)
Symbol Address When reset
GiPOCRj (i=0/j=0,1) 00D016, 00D116 0X00X0002
GiPOCRj (i=0/j=4,5) 00D416, 00D516 0X00X0002
GiPOCRj (i=1/j=0 to 3) 011016, 011116, 011216, 011316 0X00X0002
GiPOCRj (i=1/j=4 to 7) 011416, 011516, 011616, 011716 0X00X0002
RWBit name Function
Bit
symbol
MOD0
MOD1
MOD2
Operation mode
select bit
Output initial value
select bit
IVL
RLD
INV
0: Outputs "0" as the initial value
1: Outputs "1" as the initial value
Inverted output function
select bit
b1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
: Single PWM mode
: S-R PWM mode
: Phase delayed PWM mode
: Must not be set
: Must not be set
: Must not be set
: Must not be set
: Assigns communication output
to a port
0: Reloads a new count when CPU
writes the count
1: Reloads a new count when the
base timer i is reset
0: Output is not inverted
1: Output is inverted
b2
0
0
0
0
1
1
1
1
Must always set to "0"
When read, the value of this bit is indeterminate.
Reload timing
select bit
(Note 3)
(Note 4)
(Note 5)
Must always set "0"
When read, the value of this bit is indeterminate.
(Note 2)
Note 1: Group 0 and 1 have 16-bit WG function and 32-bit WG function.
The 16-bit WG function is available for 4 channels (ch=0,1,4,5) with group 0 and 8 channels
(ch=0 to 7) with group 1. When using the 16-bit WG function, use the WG register values for ch2,
3, 6 and 7 of group 0 as they are, or, if writing values, write "0016".
The 32-bit WG function can be used with 8 channels (ch0 to 7) by linking groups 0 and 1.
When using the 32-bit WG function, write the same value for WG registers of similar channels in
groups 0 and 1.
Note 2: This setting is valid only on even-numbered channels. When this mode is selected, settings for
corresponding odd-numbered (even number + 1) channels are ignored. Waveforms are output for
even-numbered channels, not output for odd-numbered channels.
Note 3: When receiving in UART mode of group 0 and 1, group i WG control register 2 is set to be
"000001102".
Note 4: This setting is valid only for WG function ch0 and 1. Do not set this value for other channels.
Note 5: Inverted output function is allocated at the final stage of WG circuit. Therefore, when selecting
b7 b0
Figure 1. 23. 17. WG-related register (2)
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Group i function enable register (i=0 to 3)
Symbol Address When reset
GiFE (i=0 to 3) 00E616, 012616, 016616, 01A616 0016
b7 b0
RWBit name
Bit
symbol
IFE0
IFE1
IFE2
Ch0 function enable bit
IFE3
IFE4
IFE5
IFE7
Function
IFE6
Whether the corresponding port
functions is selected
0 : Disables function on ch i
1 : Enables function on ch i
Ch1 function enable bit
Ch2 function enable bit
Ch3 function enable bit
Ch4 function enable bit
Ch5 function enable bit
Ch6 function enable bit
Ch7 function enable bit
Figure 1. 23. 18. WG-related register (3)
Group i waveform generation control register j (i=2 to 3/ j=0 to 7)
Symbol Address When reset
GiPOCRj (i=2/j=0 to 3) 0150
16
, 0151
16
, 0152
16
, 0153
16
0X00 X000
2
GiPOCRj (i=2/j=4 to 7) 0154
16
, 0155
16
, 0156
16
, 0157
16
0X00 X000
2
GiPOCRj (i=3/j=0 to 3) 0190
16
, 0191
16
, 0192
16
, 0193
16
0X00 X000
2
GiPOCRj (i=3/j=4 to 7) 0194
16
, 0195
16
, 0196
16
, 0197
16
0X00 X000
2
RWBit name Function
Bit
symbol
MOD0
MOD1
MOD2
Operation mode
select bit
Output initial value
select bit
IVL
RLD
INV
0: Outputs "0" as the initial value
1: Outputs "1" as the initial value
Parallel RTP output
trigger select bit
PRT 0: Match of WG register j isn’t trigger
1: Match of WG register j is trigger
Inverted output function
select bit
b1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
: Single PWM mode
: S-R PWM mode
: Phase delayed PWM mode
: Must not be set
:
Bit modulation PWM mode
: Must not be set
: Must not be set
: Assigns communication output
to a port
0: Reloads a new count when CPU
writes the count
1: Reloads a new count when the
base timer i is reset
0: Output is not inverted
1: Output is inverted
RTP RTP port function
select bit 0: Not use
1: Use
b2
0
0
0
0
1
1
1
1
Reload timing
select bit
(Note 2)
(Note 3)
(Note 1)
Note 1: This setting is valid only on even-numbered channels. When this mode is selected, settings for
corresponding odd-numbered (even number + 1) channels are ignored. Waveforms are output for
even-numbered channels, not output for odd-numbered channels.
Note 2: This setting is valid only for group 2 WG function ch0 and 1. Do not set this value for other channels.
Note 3: Inverted output function is allocated at the final stage of WG circuit. Therefore, when selecting "0"
output by IVL bit and inverted output by INV bit, "1" is output.
b7 b0
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Figure 1. 23. 19. WG-related register (4)
Group i RTP output buffer register (i=2,3)
Symbol Address When reset
GiRTP (i=2,3) 016716, 01A716 0016
b7 b0
RWBit name
Bit
symbol
RTP0
RTP1
RTP2
Ch0 RTP output buffer
RTP3
RTP4
RTP5
RTP7
Function
RTP6
The corresponding port's output
value is set
0 : Output "0"
1 : Output "1"
Ch1 RTP output buffer
Ch2 RTP output buffer
Ch3 RTP output buffer
Ch4 RTP output buffer
Ch5 RTP output buffer
Ch6 RTP output buffer
Ch7 RTP output buffer
Group i function select register (i=0, 1)
Symbol Address When reset
GiFS (i=0,1)
00E716, 012716 0016
RWBit name
Bit
symbol
b7 b0
FSC0
FSC1
FSC2
Ch0 TM/WG function
select bit
FSC3
FSC4
FSC5
FSC7
Function
FSC6
Whether the corresponding port
functions as TM or WG is selected
0 : WG function is selected
1 : TM function is selected
Note : In group 0, channles 2, 3, 6 and 7 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
In group 1, channles 0 and 3 to 5 cannot be selected in 16-bit mode. All channel can be selected
in 32-bit mode.
Ch1 TM/WG function
select bit
Ch2 TM/WG function
select bit
Ch3 TM/WG function
select bit
Ch4 TM/WG function
select bit
Ch5 TM/WG function
select bit
Ch6 TM/WG function
select bit
Ch7 TM/WG function
select bit
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(1) Single phase waveform output mode (group 0 to 3)
This mode is set when the base timer value matches the value of WG register j, and reset when the base
timer overflows or the count is reset. Specifications for the single phase waveform output mode are given
in Table 1.23.5 and an operating chart for the single phase waveform output mode in Figure 1.23.20.
Table 1. 23.5. Specifications of single phase waveform output mode
Item Specifications
Output waveform •When free run operation
Period : Base timer count source x 1/65536
"H" level width : 1/base timer count source x (65536 - m)
•Resetting when the base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2)
"H" level width : 1/base timer count source x (k+2-m)
m : values set to WG register j k: values set to WG register 0
Waveform output start condition Write "1" to the function enable bit(Note)
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register j
OUTC pin Pulse output (Corresponding pins are set with the function select register.)
Read from the WG register 0 The set value is output
Write to the WG register 0 Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin
Note: On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).
Figure 1. 23. 20. Operation timing in single phase waveform output mode
Base timer xxxa xxxb xxxc xxxd xxxe ffff 0000 0001
Count source
xxxa xxxb 0000 0001 0002 0003
Reset when channel 0 (xxxa
16
) is matched
Cleared by software.
Output
waveform
When WG register is "xxxa
16
"
Interrupt
request flag
"H"
"L"
"0"
"1"
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(2) Phase delayed waveform output mode (group 0 to 3)
This mode is repeatedly set and reset when the base timer value matches the value of WG register j.
Specifications for the phase delayed waveform output mode are given in Table 1.23.6 and an operation
timing in phase delayed waveform output mode in Figure 1.23.21.
Table 1. 23.6. Specifications of phase delayed waveform output mode
Item Specifications
Output waveform •When free run operation
Period : Base timer count source x 1/65536 x 1/2
"H" and "L" level width : 1/base timer count source x 65536
•Resetting when group i base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2) x 1/2
"H" and "L" level width : 1/base timer count source x (k+2)
k : values set to WG register 0
Waveform output start condition Write "1" to the function enable bit (Note)
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register j
OUTCij pin Pulse output (Corresponding pins are set with the function select register.)
Read from the WG register The set value is output
Write to the WG register Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin
Note : On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).
Figure 1. 23. 21. Operation timing in phase delayed waveform output mode
xxxa xxxb xxxc ffff 0000 0001 xxxa xxxb xxxc xxxd
"H"
"L"
"0"
"1"
Base timer
Count source
Cleared by software.
Output
waveform
When WG register is "xxxb
16
"
Interrupt
request flag
Cleared by software.
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(3) SR (Set/Reset) waveform output mode (group 0 to 3)
This mode is set when the base timer value matches the value of WG register j (j is an even-numbered
channel), and reset when the base timer matches the WG register (j + 1) or the base timer value is “0”.
Specifications for the SR waveform output mode are given in Table 1.23.7 and an operating chart for the
SR waveform output mode in Figure 1.23.22.
Table 1. 23.7. Specifications of SR waveform output mode
Item Specifications
Output waveform •When free run operation
Period : Base timer count source x 1/65536
"H" level width : 1/base timer count source x (m-p)
•Resetting when base timer matches WG register 0 (ch0)
Period : Base timer count source x 1/(k+2) (Note 1)
"H" level width : 1/base timer count source x (m-p)
m : values set to WG register j p : values set to WG register i(j+1)
k : values set to WG register 0 (j is an even-numbered channel) (Note 2)
Waveform output start condition Write "1" to the function enable bit (Note 3)
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register j
OUTC pin (Note 4) Pulse output (Corresponding pins are set with the function select register.)
Read from the WG register The set value is output
Write to the WG register Can always write
Select function (Note 5) •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin
Note 1: The SR waveform output function that sets and resets the mode on ch0 and 1 cannot be used when the base
timer is reset by WG register 0 (ch0).
Note 2: Set WG register values for odd-numbered channels that are lower than even-numbered channels.
Note 3: On channels where both the time measurement function and waveform output function can be used, select the
waveform output function for the function select register (addresses 00E716 and 012716).
Note 4: SR waveforms are output for even-numbered channels only.
Note 5: Settings for the WG control register on the odd-numbered channels are ignored.
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Figure 1. 23. 22. Operation timing in SR waveform output mode
xxxa xxxb xxxc yyy9 yyya yyyb yyyc
"H"
"L"
"0"
"1"
"0"
"1"
Base timer
Count source
Cleared by software.
Cleared by software.
Output
waveform
When WG register j is "xxxb
16
" and WG register j + 1 is "yyya
16
"
Channel j Interrupt
request flag
Channel j+1 Interrupt
request flag
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(4) Bit modulation PWM output mode (group 2 and 3)
This mode performs PWM to improve output resolution. Specifications for the bit modulation PWM mode
are given in Table 1.23.8 and an operating chart for the bit modulation PWM mode in Figure 1.23.23.
Table 1. 23.8. Specifications of bit modulation PWM mode
Item Specifications
Output waveform Period : Base timer count source x 1/64
"H" level width(avelage) : 1/base timer count source x [k+(m/1024)]
k : values set to WG register j (six high-order bits)
m : values set to WG register j (ten lower-order bits)
Waveform output start condition Write "1" to the function enable bit
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register j
OUTC pin Pulse output (Corresponding pins are set with the function select register.)
Read from the WG register j The set value is output
Write to the WG register j Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the OUTC pin
Figure 1. 23. 23. Operation timing in bit modulation PWM mode
A
A
00
16
3F
16
AA
AA
k
b15 b10 b9 b0
00
16
3F
16
k+1
k
Set value k
1024 pulses
Increases the "L" level width for
1 clock cycle for an m number of
pulses out of 1,024
Base timer 6
low-order bits
Sets PWM width
k=0 to 63 (3F
16
)Sets bit modulation frequency
m=0 to 1023 (3FF
16
)
WG register j
Set value k
Internal signal
Base timer
6 low-order bits
Base timer
count source
Output waveform
Output waveform
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(5) Real-time port output mode (group 2 and 3)
This mode outputs the value set in the real-time port register from the OUTC pin when the base timer
value matches the value of WG register j. Specifications for the real-time port output mode are given in
Table 1.23.9 and a block diagram and timing chart of the real-time port output function in Figure 1.23.24.
Table 1. 23.9. Specifications of real-time port output mode
Item Specifications
Waveform output start condition Write "1" to the function enable bit
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register j
OUTC pin
RTP output (Corresponding pins are set with the function select register.)
Read from the WG register j The set value is output
Write to the WG register j Can always write
Read from the RTP output buffer register The set value is output
Write to the RTP output buffer register Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the
OUTC pin
Base timer
Output waveform
xxx5 xxx6 xxx7 xxx8 xxx9 xxxa xxxb xxxc xxxd xxxe xxxf
Count source
When WG register j = "xxx8
16
" and
bit j of RTP output buffer register = "1" (previous value is 0)
Channel i
interrupt request flag
Cleared by software.
"H"
"L"
"0"
"1"
AAA
AAA
AAA
AAA
AAA
AAA
WG register 0
Base timer
DQ
T
bit0
bit6
bit7
DQ
T
DQ
T
WG register 6
WG register 7
RTP output
OUTCi0
OUTCi6
OUTCi7
RTP output buffer register
(i=2, 3
)
Figure 1. 23. 24. Block diagram and operation timing of real-time port output function
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(6) Parallel real-time port output mode (group 2 and 3)
This mode outputs the value set in the real-time port register from the OUTC pin when the base timer
value matches the value of WG register j. Specifications for the parallel real-time port output mode are
given in Table 1.23.10 and a block diagram and timing chart of the real-time port output function in Figure
1.23.25.
Table 1. 23.10. Specifications of parallel real-time port output mode
Item Specifications
Waveform output start condition Write "1" to the function enable bit
Waveform output stop condition Write "0" to the function enable bit
Interrupt generation timing When the base timer value matches the WG register
OUTC pin RTP output (Corresponding pins are set with the function select
register.)
Read from the WG register The set value is output
Write to the WG register Can always write
Read from the RTP output buffer register The set value is output
Write to the RTP output buffer register Can always write
Select function •Initial value setting function
Sets output level used at waveform output start
•Inverted output function
Inverts waveform output level and outputs the waveform from the
OUTC pin
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AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
DQ
T
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
Real-time port output
Real-time port output
buffer register
WG register 0
Base timer
WG register 1
WG register 2
WG register 3
WG register 4
WG register 5
WG register 6
WG register 7
OUTCi
0
OUTCi
1
OUTCi
2
OUTCi
3
OUTCi
4
OUTCi
5
OUTCi
6
OUTCi
7
(i=2, 3)
xxx1 xxx2 xxx3 xxx4 xxx5 xxx6 xxx7 xxxc xxxd xxxe xxxf
"H"
"L"
"H"
"L"
"H"
"L"
"0"
"1"
"0"
"1"
"0"
"1"
Base timer
Output waveform
OUTCi0
Output waveform
OUTCi1
Output waveform
OUTCi7
Count source
When WG register j = "xxx116" RTP output buffer register = "0xxx xx012"
WG register j + 1 = "xxx516" RTP output buffer register = "1xxx xx102"
(this value is saved to RTP output buffer register as channel j interrupt request trigger)
WG register j + 2 = "xxxC16" RTP output buffer register = "1xxx xx112"
(this value is saved to RTP output buffer register as channel j+1 interrupt request trigger)
Channel j
interrupt request flag
Channel j+1
interrupt request flag
Channel j+2
interrupt request flag
Cleared by software.
Cleared by software.
Cleared by software.
Figure 1. 23. 25. Block diagram and operation timing of parallel real-time port output function
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264
Serial I/O (group 0 to 2)
Intelligent I/O groups 0 to 2 each have two internal 8-bit shift registers. When used in conjunction with the
time measurement (TM) function or WG function, these shift registers enable clock synchronous/asyn-
chronous serial communications.
(1) Clock synchronous serial I/O mode (group 0, 1)
Intelligent I/O groups 0 and 1 each have communication block that have two internal 8-bit shift registers.
When used in conjunction with the communication block and WG function, these shift registers enable
8-bit clock synchronous and HDLC data process function. When used in conjunction with the communi-
cation block, TM function and WG function, these shift registers enable 8-bit clock asynchronous com-
munication.
Table 1.23.11 lists using registers in group 0 and 1, figure 1.23.26 to 1.23.29 shows the related regis-
ters.
Table 1.23.11. Using registers in group 0 and 1
Clock synchronous serial I/O UART HDLC
Base timer control register 0 √√√
Base timer control register 1 √√√
Time measument control register 2 –√–
Waveform generate control register 0 √√√
Waveform generate control register 1 ––√
Waveform generate control register 2 √√–
Waveform generate control register 3 √√–
Waveform generate register 0 √√√
Waveform generate register 1 √–√
Time measument /Waveform generate register 2 √√–
Waveform generate register 3 √√–
Function select register √√√
Function enable register √√√
SI/O communication mode register √√√
SI/O extended mode register ––√
SI/O communication control register √√√
SI/O extended transmit control register ––√
SI/O extended receive control register ––√
SI/O special communication interrupt detect register ––√
SI/O receive buffer register √√√
Transmit buffer √√√
(Receive data register ) ––√
Data compare register j (j=0 to 3) ––√
Data mask register j (j=0, 1) ––√
Transmit CRC code register ––√
Receive CRC code register ––√
Transmit output register ––√
Receive input register ––√
√ : Use – : Not use
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265
Figure 1. 23. 26. Group 0 and 1 related register (1)
Group i receive input register (i=0,1)
Symbol Address When reset
GiRI (i=0, 1) 00EC16, 012C16 Indeterminate
RWFunction Setting range
b7 b0
Data that is input to the receive data
process unit 0016 to FF16
Group i transmit output register (i=0,1)
Symbol Address When reset
GiTO (i=0, 1) 00EE16, 012E16 Indeterminate
RWFunction Setting range
b7 b0
Data that is output from the transmit data
process unit
Group i SI/O communication control register (i=0,1)
Symbol Address When reset
GiCR (i=0,1) 00EF16, 012F16 0000 X0002
RWBit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, the contents is indeterminate.
b7 b0
TI
TXEPT
RI
Transmit buffer
empty flag
TE
RE
IPOL
OPOL
Receive complete
flag
Transmit enable bit
Receive enable bit
RxD input polarity
reverse select bit
TxD output polarity
reverse select bit
0 :
No data present in receive buffer register
1 : Data present in receive buffer register
0 : Transmission disabled
1 : Transmission enabled
0 : Reception disabled
1 : Reception enabled
0 : No reverse (Usually set to "0")
1 : Reverse
Transmit register
empty flag
0 :
Data present in transmit buffer register
1 :
No data present in transmit buffer register
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
0 : No reverse (Usually set to "0")
1 : Reverse
(Note)
(Note)
Note :This bit is set to "1" in UART mode.
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Figure 1. 23. 27. Group 0 and 1 related register (2)
Group i SI/O communication mode register (i=0,1)
Symbol Address When reset
GiMR (i=0,1)
00ED
16
, 012D
16
00
16
RWBit name Function
Bit
symbol
Note 1: Can be used only in the UART mode.
Note 2: Select a pin for clock output by setting the waveform generation control register, input function select
register, and function select registers A, B and C.
Data transmission pins are the same as clock output pins.
Note 3: Select which pins will input the clock with the input function select register and set those pins to the
input port using function select register A.
Data input pins are the same as with clock input pins.
b7 b0
GMD0
GMD1
CKDIR
Communication mode
select bit
STPS
PRY
PRYE
UFORM
IRS
Internal/external clock
select bit
Stop bit length
select bit
Odd/even parity
select bit
Parity enable
select bit
Transfer direction
select bit
Transmit interrupt
cause select bit
0 : Internal clock
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : LSB first
1 : MSB first
0 : Transmit buffer is empty
1 : Transmit is completed
: UART mode
: Serial I/O mode
: Special communication mode
: HDLC data process mode
b1
0
0
1
1
b0
0
1
0
1
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 3)
Function
Group i SI/O receive buffer register (i=0,1)
Bit name
Bit
symbol
Symbol Address When reset
GiBF(i=0,1) 00E9
16,
00E8
16,
0129
16,
0128
16
Indeterminate
RW
Note: Only effective for receive data.
FER
Receive data
PER 0 : No parity error
1 : Parity error found
OER 0 : No overrun error
1 : Overrun error found
Nothing is assigned.
When read, their value are indeterminate.
Nothing is assigned.
When read, its value is indeterminate.
(Note)
Framing error flag 0 : No Framing error
1 : Framing error found
Parity error flag (Note)
Overrun error flag (Note)
Receive buffer
b7 b0
b15
(b7)b14
(b6)b13
(b5)b12
(b4)b11
(b3)b10
(b2) b9
(b1) b8
(b0)
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267
Figure 1. 23. 28. Group 0 and 1 related register (3)
Group i SI/O expansion mode register (i=0,1) (Note 1)
Symbol Address When reset
GiEMR (i=0,1) 00FC16, 013C16 0016
RWBit name Function
Bit
symbol
Note 1: Other than when in the special communication mode or HDLC data process mode, either
use the reset state as is or write "00
16
".
Note 2: Initialized when the data compare register matches.
b7 b0
SMODE
CRCV
ACRC
BSINT
RXSL
TXSL
CRC0
CRC1
Synchronous mode
select bit
Reception source
select bit
Transmission source
select bit
0 : Not initialize
1 : Initialize
0 : Not use
1 : Use
0 : RxD pin
1 : Receive input register
0 : TxD pin
1 : Transmit output register
0 : Normal mode
1 : Resynchronous mode
CRC initial value
select bit 0 : "0000
16
" is set
1 : "FFFF
16
" is set
CRC initialization
select bit
Bit stuffing error
interrupt select bit
CRC polynomial
select bit
: X
8
+X
4
+X+1
: Must not be set
: X
16
+X
15
+X
2
+1
: X
16
+X
12
+X
5
+1
b7
0
0
1
1
b6
0
1
0
1
(Note 2)
Group i SI/O expansion transmit control register (i=0,1) (Note)
Symbol Address When reset
GiETC (i=0,1)
00FF
16
, 013F
16
00000XXX
2
RWBit name Function
Bit
symbol
Note : Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "00
16
".
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
b7 b0
SOF
TCRCE
ABTE
TBSF0
TBSF1
Transmit CRC
enable bit
Arbitration enable bit
Transmit bit stuffing "1"
insert select bit
0 : Not use
1 : Use
0 : Not use
1 : Use
SOF transmit
request bit 0 : No SOF transmit request
1 : SOF transmit request
Transmit bit stuffing "0"
insert select bit
0 : "1" is not inserted
1 : "1" is inserted
0 : "0" is not inserted
1 : "0" is inserted
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268
Figure 1. 23. 29. Group 0 and 1 related register (4)
Group i special communication interrupt detect register (i=0,1) (Note)
Symbol Address When reset
GiIRF (i=0,1)
00FE16, 013E16 0000 00XX2
RWBit name Function
Bit
symbol
Note : Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "0016".
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
b7 b0
ABT
BSERR
Arbitration lost
detecting flag
Bit stuffing error
detecting flag
0 : Not detected
1 : Detected
0 : Not detected
1 : Detected
IRF0
IRF1
IRF2
Interrupt cause
determination
flag 0
IRF3
0 : Received data does not match data
compare register 0
1 :
Received data matches data compare register 0
Interrupt cause
determination
flag 1
Interrupt cause
determination
flag 2
Interrupt cause
determination
flag 3
0 : Received data does not match data
compare register 1
1 :
Received data matches data compare register 1
0 : Received data does not match data
compare register 2
1 :
Received data matches data compare register 2
0 : Received data does not match data
compare register 3
1 :
Received data matches data compare register 3
Group i SI/O expansion receive control register (i=0,1) (Note 1)
Symbol Address When reset
GiERC (i=0,1)
00FD16, 013D16 0016
RWBit name Function
Bit
symbol
Note 1: Other than when in the special communication mode or HDLC data processing mode, either
use the reset state as is or write "0016".
Note 2: To use the CRC initialization function (when bit 2 of SI/O expansion mode register is set to "1"),
set bit 3 to "1".
b7 b0
CMP0E
CMP1E
CMP2E
Data compare
function 0
select bit
CMP3E
RCRCE
RSHTE
RBSF0
RBSF1
Receive CRC
enable bit
Receive shift
operation
enable bit
0 : Not enable
1 : Enable
0 : Receive shift operation disabled
1 : Receive shift operation enabled
0 : Does not compare the received data with
data compare register 0
1 :
Compare the received data with data compare register 0
Data compare
function 1
select bit
Data compare
function 2
select bit
Data compare
function 3
select bit
Receive bit
stuffing "1" delete
select bit
Receive bit
stuffing "1" delete
select bit
0 : "1" is not deleted
1 : "1" is deleted
0 : "0" is not deleted
1 : "0" is deleted
0 : Does not compare the received data with
data compare register 1
1 :
Compare the received data with data compare register 1
0 : Does not compare the received data with
data compare register 2
1 :
Compare the received data with data compare register 2
0 : Does not compare the received data with
data compare register 3
1 :
Compare the received data with data compare register 3
(Note 2)
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Figure 1. 23. 30. Group 0 and 1 related register (5)
Group i transmit buffer/receive data register (i=0,1)
Symbol Address When reset
GiDR (i=0,1) 00EA16, 012A16 Indeterminate
RWFunction Setting range
b7 b0
Transmit data for data compare is stored
Receive data for data compare is stored
Group i data compare register j (i=0,1/j=0 to 3)
Symbol Address When reset
GiCMPj (i=0/j=o to 3)
00F0
16
, 00F1
16
, 00F2
16
, 00F3
16
Indeterminate
GiCMPj (i=1/j=o to 3)
0130
16
, 0131
16
, 0132
16
, 0133
16
Indeterminate
RWFunction Setting range
b7 b0
Compare data 0016 to FF16
Note : When using the data compare registers 0 and 1, the data mask registers 0 and 1 must be set.
Group i data mask register j (i=0,1/j=0,1)
Symbol Address When reset
GiMSKj (i=0/j=0, 1) 00F416, 00F516 Indeterminate
GiMSKj (i=1/j=0, 1) 013416, 013516 Indeterminate
RWFunction Setting range
b7 b0
Mask data for receive data (masked by "1") 0016 to FF16
Group i transmit CRC code register (i=0,1)
Symbol Address When reset
GiTCRC (i=0, 1) 00FB16,00FA16, 013B16, 013A16 000016
RWFunction Setting range
(b7) b0
Transmit CRC calculation results (Note)
Note : Computed results are initialized when the transmit CRC enable bit (bit 4 of group i expanded
transmit control register) is set to "0".
b7(b0)
b15 b8
Group i receive CRC code register (i=0,1)
Symbol Address When reset
GiRCRC (i=0, 1) 00F916,00F816, 013916, 013816 000016
RWFunction Setting range
(b7) b0
Receive CRC calculation results
b7(b0)
b15 b8
Note 1: Computed results are initialized when the receive CRC enable bit (bit 4 of group i expanded
reseive control register) is set to "0", or when the CRC initialization bit (bit 2 of group i SI/O
expansion mode register) is set to "1" and values match the data comparison register.
Note 2: Initialize to selected value when starting to receive.
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Interrupt request
generation timing
• Clock synchronous serial I/O mode (group 0 and 1)
Table 1.23.12 gives specifications for the clock synchronous serial I/O mode.
Table 1.23.12. Specifications of clock synchronous serial I/O mode (group 0 and 1)
Item Specification
Transfer data format • Transfer data length: 8 bits fixed
Transfer clock • When internal clock is selected
_
Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2
k : values set to WG register 0
_ Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : ch2 WG function
Sets the same value in the WG registers on ch2 and ch3
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
• Transmit enable bit = “1”
• Write data to transmit buffer
Reception start condition To start reception, the following requirements must be met:
• Receive enable bit = “1”
• When transmitting
_
When transmit buffer is empty, transmit interrupt cause select bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
When data is transferred to SI/O receive buffer register
Error detection • Overrun error
This error occurs when the next data is ready before the contents of SI/O receive
buffer register are read out
Select function • LSB first/MSB first selection
When transmission/reception begins with bit 0 or bit 7, it can be selected
• Transmit/receive data polarity switching
This function is reversing ISTxD pin output and ISRxD pin input.
(All I/O data level is reversed.)
Note: Set the transmission clock to at least 6 divisions of the base timer clock.
Table 1.23.13 lists I/O pin functions for the clock synchronous serial I/O mode of groups 0 and 1.
From when the operating mode is selected until transmission starts, the ISTxDi pin is "H" level. Figure
1.23.31 shows typical transmit/receive timings in clock synchronous serial I/O mode in group 0 and 1.
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Figure 1.23.31. Typical transmit/receive timings in clock synchronous serial I/O mode in group 0 and 1
Table 1.23.13. I/O pin functions in clock synchronous serial I/O mode of group 0, group 1
Pin name Function Selected method
ISTxD Serial data output • Use the ch0 WG function
(P76, P150, P73, P110)• Sets "111" for the operating mode select bit (bits 2, 1 and 0) in
WG control register 0
• Selects ISTxD output for the port using function select registers
A, B and C
ISRxD Serial data input • Selects a using port with input function select register
(P80, P152, P75, P112)• Selects I/O with function select register A
• Sets a selected port to input using the port direction register
ISCLK Transfer clock output • Use the ch1 WG function
(P77, P151, P74, P111)• Sets "111" for the operating mode select bit (bits 2, 1 and 0) in
WG control register 1
• Sets "0" for the internal/external clock select bit (bit 2) of the
SI/O communication mode register
• Selects ISCLK output for the port using function select registers
A, B and C
Transfer clock input • Selects a using port with input function select register
• Sets "1" for the internal/external clock select bit (bit 2) of the
SI/O communication mode register
• Sets a selected port to input using the port direction register
• Selects I/O port with function select register A
T
t
Base timer
Receive data
Base timer resets using
ch0 WG function
(Input to INPCi
2
/ISRxD
i
pin
(i=0,1))
Receive clock using
ch2 WG function
Transmit data
Transmit clock using
ch3 WG function
bit 1 bit 2 bit 6 bit 7bit 0
Write to transmit buffer
T: Transfer rate/2
bit 1 bit 6 bit 7
t : Values set to ch2 WG register
Values set to ch3 WG register
bit 0
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Interrupt request
generation timing
(2) Clock asynchronous serial I/O mode (UART) (group 0 and 1)
Table 1.23.14 lists the specifications for the UART mode.
Table 1.23.14. Specifications of UART mode
Item Specification
Transfer data format • Character bit (transfer data) : 8 bits
• Start bit : 1 bit
• Parity bit : Odd, even, or nothing selected
• Stop bit : 1 bit or 2 bits selected
Transfer clock • When internal clock is selected (Generates the transmit/receive clock in the phase
delayed waveform output mode)
_
Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2) / 2
k : values set to WG register 0
_ Transfer clock is generated when the transfer clock in the phase delayed
waveform output mode
Transmit clock : ch3 WG function
Receive clock : Change ch2 TM function to WG function
Detects falling edge of start bit
Changes to the WG mode when the time measurement interrupt arrives
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin
Transmission start condition To start transmission, the following requirements must be met:
• Transmit enable bit = “1”
• Write data to transmit buffer
Reception start condition To start reception, the following requirements must be met:
• Receive enable bit = “1”
• When transmitting
_
When transmit buffer is empty, transmit interrupt cause select bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
_ When data is transferred to SI/O receive buffer register
Error detection • Overrun error : This error occurs when the next data is ready before contents
of SI/O receive buffer register are read out
• Framing error :
This error occurs when the number of stop bits set is not detected
• Parity error : This error occurs when if parity is enabled, the number of 1’s in
parity and character bits does not match the number of 1’s set
Select function • Stop bit length : Stop bit length can be selected as 1 bit or 2 bits
• Parity : Parity can be turned on/off
: When parity is on, odd/even parity can be selected
• LSB first/MSB first selection :
Whether transmit/receive begins with bit 0 or bit 7 can be selected
• Transmit/receive data polarity switching :
This function is reversing ISTxD port output and ISRxD port input. (All I/O data level
are reversed.)
• Data transfer bit length : Transmission data length can be set between 1 to 8 bits
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Figure 1.23.32. Typical transmit timings in UART mode
Figure 1.23.33. Typical receive timing in UART mode
TxD, RxD I/O polarity reverse function
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) are reversed. TxD output polarity reverse select bit is
set to “0” (not to reverse) for usual use.
k + 2
t
Base timer
Transmit data
Base timer resets using ch0 WG function
Transmit clock using
ch3 WG function
t : Values set to ch3 WG register
Write to transmit buffer
Start Bit bit 0 bit 7 Parity Stop Bit (1 bit)
k+2
t
Base timer
Receive data
Base timer resets using ch0 WG function
(Input to INPCi2/ISRxDi pin
(i=0,1))
Receive clock using
ch2 WG function
Interrupt request
signal
Start Bit bit 0 bit 7 Parity Stop Bit (1 bit)
t : Values set to ch2 WG register
Reception completed
interrupt request
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(2) Clock synchronous serial I/O mode (group 2)
Intelligent I/O groups 2 has communication block that have two internal 8-bit shift registers. When used
in conjunction with the communication block and WG function, these shift registers enable variable clock
synchronous and IE Bus (Note) communications.
Table 1.23.16 lists using registers in group 2, figure 1.23.34 to 1.23.37 shows the related registers.
Note : IE Bus is a trademark of NEC corporation.
Table 1.23.16. Using registers in group 2 Clock synchronous serial I/O IE Bus
Base timer control register 0 √√
Base timer control register 1 √√
Waveform generate control register 0 √√
Waveform generate control register 1 –√
Waveform generate control register 2 √√
Waveform generate control register 3 –√
Waveform generate control register 4 – √ (Note 1)
Waveform generate control register 5 –√
Waveform generate control register 6 –√
Waveform generate control register 7 –√
Waveform generate register 0 √√
Waveform generate register 1 –√
Waveform generate register 2 √√
Waveform generate register 3 –√
Waveform generate register 4 –√
Waveform generate register 5 –√
Waveform generate register 6 –√
Waveform generate register 7 –√
Function enable register √√
SI/O communication mode register √√
SI/O communication control register √√
IE Bus control register –√
IE Bus address register –√
IE Bus transmit interrupt cause detect register –√
IE Bus receive interrupt cause detect register –√
SI/O receive buffer register √√
SI/O transmit buffer register √√
√ : Use – : Not use
Note 1: When receiving slave, set corresponding value with 32.5 µs. Don't set 170 µs.
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Function
Group 2 SI/O transmit buffer register
Bit name
Bit
symbol
Symbol Address When reset
G2TB
016D
16
, 016C
16
Indeterminate
RW
SZ0
SZ2
SZ1
b7 b0
b15
(b7)b14
(b6)b13
(b5)b12
(b4)b11
(b3)b10
(b2) b9
(b1) b8
(b0)
Transfer bit length
select bit
Transmit buffer Transmit data
b9
0
0
1
1
0
0
1
1
b8
0
1
0
1
0
1
0
1
: 8-bit long
: 1-bit long
: 2-bit long
: 3-bit long
: 4-bit long
: 5-bit long
: 6-bit long
: 7-bit long
b10
0
0
0
0
1
1
1
1
A
PC
P
ACK function
select bit
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Parity operation
continuing bit
Parity function
select bit
0 : No function
1 : Adds an ACK bit after the final
transmission bit
0 :
Adds the parity bit after the transmitted data
1 : Repeats the parity check with the next
transmission
0 : No parity
1 : Parity (Only even parity)
Note: When this bit is set to "1", set the parity function select bit to "0".
(Note)
Function
Group 2 SI/O receive buffer register
Bit name
Bit
symbol
Symbol Address When reset
G2RB
016F
16
, 016E
16
Indeterminate
RW
Note : This bit is automatically set to "0" when communication unit reset is selected for the communication
mode select bit and the reception enable bit is set to "0".
Receive data
OER
0 : No overrun error
1 : Overrun error found
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Receive buffer
Overrun error flag
(Note)
b7 b0
b15
(b7)b14
(b6)b13
(b5)b12
(b4)b11
(b3)b10
(b2) b9
(b1) b8
(b0)
Figure 1. 23. 34. Group 2 Intelligent I/O-related register (1)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O (Serial I/O)
276
Group 2 IE Bus control register
Symbol Address When reset
IECR 017216 00XXX0002
RWBit name Function
Bit
symbol
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
b7 b0
0 : Idle state
1 :
Busy state (start condition detected)
IEB
IETS
IEBBS
IE Bus enable bit
DF
IE Bus transmit start
request bit
Digital filter
select bit
0 : Transmit completed
1 : Transmit start
0 : IE Bus disabled
1 : IE Bus enabled
0 : No digital filter
1 : Digital filter
IEM
IE Bus busy flag
IE Bus mode
select bit 0 : Mode 1
1 : Mode 2
(Note)
Note :When this bit is set to "0", hold "0" for at least 1 cycle of base timer .
Group 2 IE Bus address register
Symbol Address When reset
IEAR 0171
16
, 0170
16
Indeterminate
RWFunction
b7 b0
Address data
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Address data
(b7)(b6)(b5)(b4)(b3)(b2)(b1)(b0)
b15b14b13b12 b11b10 b9 b8
Figure 1. 23. 35. Group 2 Intelligent I/O-related register (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O (Serial I/O)
277
Figure 1. 23. 36. Group 2 Intelligent I/O-related register (3)
Group 2 IE Bus transmit interrupt cause determination register
Symbol Address When reset
IETIF
017316 XXX000002
RWBit name Function
Bit
symbol
Note : Only "0" can be written for this bit. Also, it is cleared to "0" when "0" is written for bit 0 of the IE Bus
control register. At this time, hold "0" for at least 1 cycle of base timer clock.
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
b7 b0
(Note)
IETNF
IEACK
IETMB
Normal termination
flag
IETT
IEABL
ACK error flag
Arbitration lost flag
0 : No error
1 : Error found
0 : Terminated in error
1 : Terminated normally
Max. transfer byte
error flag
Timing error flag
0 : No error
1 : Error found
0 : No error
1 : Error found
0 : No error
1 : Error found
(Note)
(Note)
(Note)
(Note)
Group 2 IE Bus receive interrupt cause determination register
Symbol Address When reset
IERIF
017416 XXX000002
RWBit name Function
Bit
symbol
Note : Only "0" can be written for this bit. Also, it is cleared to "0" when "0" is written for bit 0 of the IE Bus
control register. At this time, hold "0" for at least 1 cycle of base timer clock.
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
b7 b0
(Note)
IERNF
IEPAR
IERMB
IERT
IERETC
Parity error flag
Other cause receive
completed flag
0 : No error
1 : Error found
Max. transfer byte
error flag
Timing error flag
0 : No error
1 : Error found
0 : No error
1 : Error found
0 : No error
1 : Error found
(Note)
(Note)
(Note)
(Note)
Normal termination
flag 0 : Terminated in error
1 : Terminated normally
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Intelligent I/O (Serial I/O)
278
Figure 1. 23. 37. Group 2 Intelligent I/O-related register (4)
b7 b0
GMD0
GMD1
CKDIR
Communication mode
select bit
UFORM
IRS
Internal/external clock
select bit
Transfer direction
select bit
Transmit interrupt
cause select bit
0 : Internal clock
1 : External clock
0 : LSB first
1 : MSB first
0 : Transmit buffer is empty
1 : Transmit is completed
: Communication part is reset
(Overrun error flag is cleared)
: Serial I/O mode
: Special communication mode
: HDLC data process mode
b1
0
0
1
1
b0
0
1
0
1
(Note 2)
(Note 3)
Group 2 SI/O communication mode register
Symbol Address When reset
G2MR 016A
16
00XXX000
2
RWBit name Function
Bit
symbol
Note 1: Intelligent I/O group 2 has IE bus communication function as special communication function.
Note 2: Select a pin for clock output by setting the waveform generation control register, input function select
register, and function select registers A, B and C. Data transmission pins are the same as clock
output pins.
Note 3: Select which pins will input the clock with the input function select register and set those pins to the
input port using function select register A. Data input pins are the same as with clock input pins.
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Group 2 SI/O communication control register
Symbol Address When reset
G2CR 016B16 0000 X0002
RWBit name Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, the contents is indeterminate.
b7 b0
TE
TXEPT
RI
Transmit enable bit
TI
RE
IPOL
OPOL
Receive complete
flag
Transmit buffer
empty flag
Receive enable bit
RxD input polarity
reverse select bit
TxD output polarity
reverse select bit
0 :
No data present in receive buffer register
1 : Data present in receive buffer register
0 :
Data present in transmit buffer register
1 :
No data present in transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No reverse (Usually set to "0")
1 : Reverse
Transmit register
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
0 : No reverse (Usually set to "0")
1 : Reverse
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O (Serial I/O)
279
• Clock synchronous serial I/O mode (group 2)
Table 1.23.17 gives specifications for the group 2 clock synchronous serial I/O mode.
Table 1.23.17. Specifications of clock synchronous serial I/O mode
Item Specification
Transfer data format • Transfer data length: Variable length (group2)
Transfer clock • When internal clock is selected, the transfer clock in the single waveform output
mode is generated.
_
Transfer speed is determined when the base timer is reset by the ch0 WG function
Transfer rate (bps) = base timer count source (frequency) / (k+2)
k : values set to WG register 0
_ Transfer clock is generated by ch2 single phase WG function
Ch3 WG register = (k+2)/2 (Note 1)
• When external clock is selected
_ Transfer rate (bps) = Clock input to ISCLK pin (Note 2)
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit = “1”
_ Write data to SI/O transmit buffer register
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit = “1”
_ Transmit enable bit = “1”
_ Write data to SI/O transmit buffer register
• When transmitting
_ When SI/O communication buffer register is empty, transmit interrupt cause select
bit = “0”
_ When transmission is completed, transmit interrupt cause select bit = “1”
• When receiving
_ When data is transferred to SI/O receive buffer register
Error detection • Overrun error
This error occurs when the next data is ready before the contents of SI/O receive
buffer register are read out
Select function • LSB first/MSB first selection
When transmission/reception begins with bit 0 or bit 7, it can be selected.
• Transmit/receive data polarity switching
_ This function is reversing ISTxD pin output and ISRxD pin input.
(All I/O data level is reversed.)
• Data transfer bit length
_ Transmission data length can be set between 1 to 8 bits
Note 1: When the transfer clock and transfer data are transmission, transfer clock is set to at least 6 divi-
sions of the base timer clock. Except this, transfer clock is set to at least 20 divisions of the base
timer clock.
Note 2: Transfer clock is set to at least 20 divisions of the base timer clock.
Interrupt request
generation timing
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Intelligent I/O (Serial I/O)
280
k + 2
t
Base timer
Second writing to
the transmit buffer
Receive data
Writes data to the transmit register
(8 bits)
bit 0 bit 1
bit 2
bit 7
bit 6
bit 8 bit 9
bit 10
bit 11
bit 0 bit 1
bit 2
bit 7
bit 6 bit 8 bit 9
bit 10
bit 11
bit 5
Writes data to the transmit register
(4 bits)
Transfer to the receive register
Transfer to the receive register
First writing to
the transmit buffer
Base timer resets using
ch0 WG function
Transmit/Receive clock
using ch2 WG function
t : Values set to ch2 WG register
Values set to ch3 WG register
Figure 1. 23. 38. Typical transmit/receive timings in clock synchronous serial I/O mode in group 2
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
281
A-D Converter
The A-D converter consists of two 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P150 to P157, P00 to P07, P20 to P27, P95, and P96 are shared as the
analog signal input pins. Pins P150 to P157, P00 to P07 and P20 to P27 can be used as the analog signal
input pins and switched by analog input port select bit. However, P00 to P07 and P20 to P27 can be used in
single chip mode. Set input to direction register corresponding to a pin doing A-D conversion.
The result of A-D conversion is stored in the A-D registers of the selected pins.
Table 1.24.1 shows the performance of the A-D converter. Figure 1.24.1 shows the block diagram of the
A-D converter, and Figures 1.24.2 to 1.24.7 show the A-D converter-related registers.
This section is described to 144-pin version as example.
In 100-pin version, AN10 to AN17 cannot be selected because there is no P15.
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A-D Converter
282
A-D1 register 0
A-D1 register 1
A-D1 register 2
A-D1 register 3
A-D1 register 4
A-D1 register 5
A-D1 register 6
A-D1 register 7
Decoder
(01C1
16
, 01C0
16
)
(01C3
16
, 01C2
16
)
(01C5
16
, 01C4
16
)
(01C7
16
, 01C6
16
)
(01C9
16
, 01C8
16
)
(01CB
16
, 01CA
16
)
(01CD
16
, 01CC
16
)
(01CF
16
, 01CE
16
)
AD1 control register 0
(address 01D6
16
)
000
AN
0
001
AN
1
010
AN
2
011
AN
3
100
AN
4
AN
5
101
110
AN
6
111
AN
7
000
AN2
0
001
AN2
1
010
AN2
2
011
AN2
3
100
AN2
4
AN2
5
101
110
AN2
6
111
AN2
7
000
AN15
0
001
AN15
1
010
AN15
2
011
AN15
3
100
AN15
4
AN15
5
101
110
AN15
6
111
AN15
7
A-D0 register 0
A-D0 register 1
A-D0 register 2
A-D0 register 3
A-D0 register 4
A-D0 register 5
A-D0 register 6
A-D0 register 7
Decoder
(0381
16
, 0380
16
)
(0383
16
, 0382
16
)
(0385
16
, 0384
16
)
(0387
16
, 0386
16
)
(0389
16
, 0388
16
)
(038B
16
, 038A
16
)
(038D
16
, 038C
16
)
(038F
16
, 038E
16
)
000
AN0
0
001
AN0
1
010
AN0
2
011
AN0
3
100
AN0
4
AN0
5
101
110
AN0
6
111
AN0
7
Successive
conversion register
Resister ladder
AD0 control register 0
(address 0396
16
)
AD1 control register 1
(address 01D7
16
)
AD0 control register 1
(address 0397
16
)
1/3
1/21/2
0
1
0
1
0
1
AD1CON0 : CSK0
AD1CON1 : CSK1
f
AD
ØAD1
1/3
1/21/2
0
1
0
1
0
1
AD0CON0 : CSK0
AD0CON1 : CSK1
f
AD
ØAD0
ANEX0
ANEX1
AD0CON1 :
OPA0, OPA1
ADiCON2 :
TRG1, TRG0
ADiCON0 :
TRG
EX TRGi
X1
1X 11 01
00
AD0CON0 :
CH2, CH1, CH0 AD1CON0 :
CH2, CH1, CH0
10
00
01
11
AD1CON2 :
APS1, APS0
AD0CON2 : ADS
P2
P0
P15
P10
AD
TRG
TB2INT
IIOG2 ch1 INT (i=0)
or
IIOG3 ch1 INT (i=1)
P9
6
P9
5
0101
Comparator 0 Comparator 1 Address
Address
Successive
conversion register
Resister ladder
Figure 1.24.1. Block diagram of A-D converter
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A-D Converter
283
Table 1.24.1. Performance of A-D converter
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock ØAD (Note 2) fAD, fAD/2, fAD/3 , fAD/4 fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 34 pins
AN, AN0, AN2, AN15(Note 3) each 8 pins
Extended input 2 pins (ANEX0(Note 4) and ANEX1(Note 5))
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts by outbreak of the following factors chosen among in three
(Note 6)
· ADTRG/P97 input changes from “H” to “L”
· Timer B2 interrupt occurrences frequency counter overflow
· Interrupt of Intelligent I/O group 2 or 3 channel 1
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 ØAD cycles
10-bit resolution: 59 ØAD cycles
• With sample and hold function
8-bit resolution: 28 ØAD cycles
10-bit resolution: 33 ØAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Without sample and hold function, set the fAD frequency to 250kHz or more.
With the sample and hold function, set the fAD frequency to 1MHz or more.
Note 3: When port P15 is used as analog input port, port P15 input peripheral function select bit (bit 2 of address
017816) must set to be "1".
Note 4: When port P95 is used as analog input port, port P95 output peripheral function select bit (bit 5 of address
03B716) must set to be "1".
Note 5: When port P96 is used as analog input port, port P96 output peripheral function select bit (bit 6 of address
03B716) must set to be "1".
Note 6: Set the port direction register to input.
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A-D Converter
284
Function
A-D0 control register 0 (Note 1)
Bit name
Bit
symbol
Symbol Address When reset
AD0CON0 0396
16
00
16
RW
CH0
CH1
CH2
Analog input pin
select bit
MD0
MD1
TRG
CKS0
ADST
A-D operation
mode select bit 0
A-D conversion
start flag
Trigger select bit
Frequency select
bit
0 : Software trigger
1 : External trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/3 or fAD/4 is selected
1 : fAD/1 or fAD/2 is selected
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
b1 b0
0 0 0 : AN0
0 0 1 : AN1
0 1 0 : AN2
0 1 1 : AN3
1 0 0 : AN4
1 0 1 : AN5
1 1 0 : AN6
1 1 1 : AN7
b2
b3b4
(Note 2, 3)
(Note 2)
(Note 5)
(Note 6)
Note 1: If the A-D0 control register 0 is re written during A-D conversion, the con v ersion result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
Note 4: External trigger request cause can be selected in external trigger request cause select bit (bit5
and bit 6 of address 039416).
Note 5: When External trigger is selected, set to "1" after selecting the external trigger request cause
using the external trigger request cause select bit.
Note 6: When f(XIN) is o v er 10 MHz, the AD frequency must be under 10 MHz b y dividing.
(Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.24.2. A-D converter-related registers (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
285
Function
A-D0 control register 1 (Note 1)
Bit name
Bit
symbol
Symbol Address When reset
AD0CON1 0397
16
00
16
RW
SCAN0
SCAN1
MD2
A-D sweep pin
select bit
BITS
CKS1
VCUT
OPA1
OPA0
8/10-bit mode
select bit
External op-amp
connection mode
bit
0 : V
REF
not connectec
1 : V
REF
connectec
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
V
REF
connect bit
0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
/1 or f
AD
/3 is selected
0 : 8-bit mode
1 : 10-bit mode
A-D operation
mode select bit 1
0 0 : ANj
0
, ANj
1
(ANj
0
)
0 1 : ANj
0
to ANj
3
(ANj
0
, ANj
1
)
1 0 : ANj
0
to ANj
5
(ANj
0
to ANj
2
)
1 1 : ANj
0
to ANj
7
(ANj
0
to ANj
3
)
0 :
Any mode other than repeat sweep mode 1
1 : Repeat sweep mode 1
(Note 2, 3)
Frequency select
bit (Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
b1b0
b7b6
Note 1: If the A-D0 control register 1 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: This bit is invalid in One-shot mode and Repeat mode. Channel shown in the parentheses,
becomes valid when repeat sweep mode 1(bit2="1") is selected.
Note 3: When f(X
IN
) is ov er 10 MHz, the
AD
frequency must be under 10 MHz by dividing.
Note 4: In single sweep mode and repeat sweep mode 0, 1, bit 7 and bit 6 cannot be set "01" and "10".
Note 5: When this bit is set, set "00" to bit6 and bit5 of function select register B3.
Note 6: When this bit is set, set "1" to bit5 of function select register B3.
Note 7: When this bit is set, set "1" to bit6 of function select register B3.
Note 8: When this bit is set, set "11" to bit6 and bit5 of function select register B3.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.24.3. A-D converter-related registers (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
286
Function
A-D0 control register 2
(Note 1)
Bit name
Bit
Symbol
Symbol Address When reset
AD0CON2 0394
16
X000 0000
2
RW
SMP
ADS
TRG0
TRG1
Note 1: If the A-D0 control register 2 is rewritten during A-D conversion, the conversion result is indeterminat
e
Note 2: When the A-D circuit of either of A-D0 and A-D1 are operated, do not write "1" to this bit.
Note 3: This bit is valid when software trigger is selected.
Note 4: When this bit read, the value is indeterminate.
Note 5: This is valid in three-phase PWM mode.
Note 6: Turn every setting of A-D0 and A-D1 into same, and start at the same time in sweep mode.
A-D conversion
method select bit 0 : Without sample and hold
1 : With sample and hold
Reserved bit Must always set to "0"
0 : Channel replace is invalid
1 : Channel replace is valid
PST
External trigger
request cause
select bit
A-D Channel replace
select bit
Simultaneous start bit 0 : Invalid
1 : 2 circuit A-D simultaneous start
0 0 : AD
TRG
is selected
0 1 : Timer B2 interrupt occurrence
frequency counter overflow is
selected
(Note 3)
1 0 : Group 2 channel 1 interrupt is
selected
1 1 : Must not be set
(Note 2)
(Note 6)
b6 b5
(Note 5)(Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
000
Function
A-D0 register j (j=0 to 7)
Symbol Address When reset
AD0j(j=0 to 2) 0381
16
,0380
16
, 0383
16
,0382
16
, 0385
16
,0384
16
indeterminate
AD0j(j=3 to 5) 0387
16
,0386
16
, 0389
16
,0388
16
, 038B
16
,038A
16
indeterminate
AD0j(j=6,7) 038D
16
,038C
16
, 038F
16
,038E
16
indeterminate
RW
Eight low-order bits of A-D conversion result
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
During 10-bit mode
During 8-bit mode : Two high-order bits of A-D conversion result
: When read, their contents are indeterminate
b7 b0
b15
(b7) b8
(b0)
Figure 1.24.4. A-D converter-related registers (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
287
Function
A-D1 control register 0 (Note 1)
Bit name
Bit
symbol
Symbol Address When reset
AD1CON0 01D616 0016
RW
CH0
CH1
CH2
Analog input pin
select bit
MD0
MD1
TRG
CKS0
ADST
A-D operation
mode select bit 0
A-D conversion
start flag
Trigger select bit
Frequency select
bit
0 : Software trigger
1 : External trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : f
AD
/3 or f
AD
/4 is selected
1 : f
AD
/1 or f
AD
/2 is selected
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
0 0 0 : ANj
0
0 0 1 : ANj
1
0 1 0 : ANj
2
0 1 1 : ANj
3
1 0 0 : ANj
4
1 0 1 : ANj
5
1 1 0 : ANj
6
1 1 1 : ANj
7
(Note 2, 3, 4)
(Note 2)
(Note 7)
(Note 5, 6)
(Note 8)
b2 b1
b4 b3
b0
Note 1: If the A-D1 control register 0 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1.
Note 4: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01D4
16
).
Note 5: External trigger request cause can be selected in external trigger request cause select bit (bit5
and bit 6 of address 01D4
16
).
Note 6: After selecting external trigger request cause, set to "1".
Note 7: When External trigger is selected, set to "1" after selecting the external trigger.
Note 8: When f(X
IN
) is over 10 MHz, the
AD
frequency must be under 10 MHz by dividing.
(j=0, 2, 15)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.24.5. A-D converter-related registers (4)
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A-D Converter
288
Function
A-D1 control register 1 (Note 1)
Bit name
Bit
symbol
Symbol Address When reset
AD1CON1 01D7
16
XX000000
2
RW
SCAN0
SCAN1
MD2
A-D sweep pin
select bit
BITS
CKS1
VCUT
8/10-bit mode
select bit
V
REF
connect bit 0 : V
REF
not connectec
1 : V
REF
connectec
Frequency select
bit 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
/1 or f
AD
/3 is selected
0 : 8-bit mode
1 : 10-bit mode
A-D operation
mode select bit 1
0 0 : ANj
0
,ANj
1
(ANj
0
)
0 1 : ANj
0
to ANj
3
(ANj
0
,ANj
1
)
1 0 : ANj
0
to ANj
5
(ANj
0
to ANj
2
)
1 1 : ANj
0
to ANj
7
(ANj
0
to ANj
3
) (j=0, 2, 15)
0 :
Any mode except repeat sweep mode 1
1 : Repeat sweep mode 1
(Note 4)
(Note 2, 3)
b1 b0
Nothing is assigned.
When write, set to "0". When read,
their contents are indeterminate
.
Note 1: If the A-D1 control register 1 is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: This bit is invalid in one-shot mode and repeat mode. Channel shown in the parentheses,
becomes valid when repeat sweep mode 1(bit 2 = "1") is selected.
Note 3: j=0, 2, 15 is selected by analog input port select bits (bit1 and bit 2 of address 01D4
16
).
Note 4: When f(X
IN
) is ov er 10 MHz, the
AD
frequency must be under 10 MHz by dividing.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.24.6. A-D converter-related registers (5)
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A-D Converter
289
Bit name
A-D1 control register 2 (Note 1)
Bit name
Bit
Symbol
Symbol Address When reset
AD1CON2 01D4
16
X00XX000
2
RW
SMP
APS0
APS1
A-D conversion
method select bit
Note 1: If the A-D1 control register 2 is rewritten during A-D conversion, the conversion.
Note 2: This is valid in three-phase PWM mode.
0 : Without sample and hold
1 : With sample and hold
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
Nothing is assigned.
When write, set to "0". When read, their contents are
indeterminate.
TRG0
TRG1
External trigger
request cause
select bit
0 0 : ADTRG is selected
0 1 : Timer B2 interrupt occurrence
frequency counter overflow is
selected (Note 2)
1 0 : Group 3 channel 1 interrupt is
selected
1 1 : Must not be set
b6
Analog input port
select bit
0 0 : P15
0 1 : Must not be set
1 0 : P0
1 1 : P2
b2 b1
b5
b7 b6 b5 b4 b3 b2 b1 b0
Function
A-D1 register j (j=0 to 7)
Symbol Address When reset
AD1j(j=0 to 2) 01C1
16
,01C0
16
, 01C3
16
,01C2
16
, 01C5
16
,01C4
16
indeterminate
AD1j(j=3 to 5) 01C7
16
,01C6
16
, 01C9
16
,01C8
16
, 01CB
16
,01CA
16
indeterminate
AD1j(j=6,7) 01CD
16
,01CC
16
, 01CF
16
,01CE
16
indeterminate
RW
Eight low-order bits of A-D conversion result
Nothing is assigned.
When write, set to "0". When read, their contents are indeterminate.
During 10-bit mode
During 8-bit mode : Two high-order bits of A-D conversion result
: When read, their contents are indeterminate
b7 b0
b15
(b7) b8
(b0)
Figure 1.24.7. A-D converter-related registers (6)
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A-D Converter
290
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.24.2 shows the specifications of one-shot mode.
Table 1.24.2. One-shot mode specifications
Item Specification
Function The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-Di conversion start flag, external trigger
Stop condition •End of A-Di conversion (A-Di conversion start flag changes to “0”, except when
external trigger is selected)
•Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin One of ANj0 to ANj7 (j =non, 0, 2, 15), ANEX0, ANEX1
Reading of result of A-D converter
Read A-D register corresponding to selected pin
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.24.3 shows the A-D control register in repeat mode.
Table 1.24.3. Repeat mode specifications
Item Specification
Function The pin selected by the analog input pin select bit is used for repeated A-D con-
version
Start condition Writing “1” to A-D conversion start flag, external trigger
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin One of ANj0 to ANj7 (j =non, 0, 2, 15), ANEX0, ANEX1
Reading of result of A-D converter
Read A-D register corresponding to selected pin
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.24.4 shows the A-D control register in single sweep mode.
Table 1.24.4. Single sweep mode specifications
Item Specification
Function The pins selected by the A-Di sweep pin select bit are used for one-by-one
A-D conversion
Start condition Writing “1” to A-D converter start flag, external trigger
Stop condition •End of A-Di conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
•Writing “0” to A-Di conversion start flag
Interrupt request generation timing
End of sweep
Input pin ANj0 and ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7
(8 pins) (j =non, 0, 2, 15)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
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A-D Converter
291
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.24.5 shows the specifications of repeat sweep mode 0.
Table 1.24.5. Repeat sweep mode 0 specifications
Item Specification
Function The pins selected by the A-D sweep pin select bit are used for repeat sweep
A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin ANj0 and ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to AN7
(8 pins) (j =non, 0, 2, 15)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.26.6 shows the specifications of repeat sweep mode 1.
Table 1.26.6. Repeat sweep mode 1 specifications
Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins
selected by the A-D sweep pin select bit
Example : AN0 selected
ANj0ANj1ANj0ANj2ANj0ANj3etc. (j =non, 0, 2, 15)
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin ANj0 to ANj7 (j =non, 0, 2, 15)
With emphasis on the pin ANj0 (1 pin), ANj0 and ANj1 (2 pins), ANj0 to ANj2 (3 pins), ANj0 to ANj3 (4 pins) (j
=non, 0, 2, 15)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
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A-D Converter
292
(a) Resolution select function
8/10-bit mode select bit of A-D control register 1 (bit 3 at address 039716, 01D716)
When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd
addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses.
(b) Sample and hold
Sample and hold are selected by setting bit 0 of the A-D control register 2 (address 039416, 01D416) to
“1”. When sample and hold are selected, the rate of conversion of each pin increases. As a result, a 28
ØAD cycle is achieved with 8-bit resolution and 33 ØAD with 10-bit resolution. Sample and hold can be
selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether
sample and hold are to be used.
(c) Trigger select function
Can appoint start of conversion, by a combination of setting of trigger select bit (bit 5 at address 039616,
01D616) and external trigger request cause select bit (bit 5 and bit 6 at address 039416, 01D416), as
follows.
Table 1.24.7. Trigger select function setting
Trigger select bit="1"
Trigger select bit=
"0"
External trigger cause select bits
00 01 10
A-D0 Software trigger ADTRG Timer B2 OFCOI(Note) Group 2 channel 1 interrupt
A-D1 Software trigger ADTRG Timer B2 OFCOI(Note) Group 3 channel 1 interrupt
Timer B2 OFCOI : Timer B2 occurrence frequency counter overflow interrupt
Note :Valid in three-phase PWM mode.
(d) Two circuit same time start (software trigger)
Two A-D converters can start at the same time by setting simultaneous start bit (bit 7 of address 039416)
to “1”.
During the A-D circuit of either of A-D0 and A-D1 are operated, do not set “1” to the simultaneous start bit.
Do not set to "1" when external trigger is selected. When using this bit, do not set A-D conversion start
flag (bit 6 of address 039616, 01D616) to "1".
(e) Replace function of input pin
Setting "1" to A-D channel replace select bit of A-D0 control register 2 (ADS:bit 4 at address 039416) can
replace channel of A-D0 and A-D1. A-D conversion reliability is confirmed by replacing channels.
When ADS bit is "1", a corresponding pin of A-D0 register i is selected by analog input port select bits of
A-D1 control register 2 (bits 2 and 1 at address 01D416). In this case, A-D0 control register 0 and A-D1
control register 0 must be set to same value.
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A-D Converter
293
Table 1.24.8. Setting of analog input port replace of A-D converter
Setting value A-D channel replace select bit 1
A-D conversion stored register
Analog output port select bit 00 10 11
A-D0 register 0 AN150AN00AN20
A-D0 register 1 AN151AN01AN21
A-D0 register 2 AN152AN02AN22
A-D0 register 3 AN153AN03AN23
A-D0 register 4 AN154AN04AN24
A-D0 register 5 AN155AN05AN25
A-D0 register 6 AN156AN06AN26
A-D0 register 7 AN157AN07AN27
A-D1 register 0 AN0
A-D1 register 1 AN1
A-D1 register 2 AN2
A-D1 register 3 AN3
A-D1 register 4 AN4
A-D1 register 5 AN5
A-D1 register 6 AN6
A-D1 register 7 AN7
(f) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital as AN0 and AN1 analog input signal respectively.
Set the related input peripheral function of the function select register B3 to disabled.
(g) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 and bit 7 of the A-D control register 1 (address 039716) is “11”, input via AN0 to AN7 is output
from ANEX0.
The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D
register. The speed of A-D conversion depends on the response of the external operation amp. Do not
connect the ANEX0 and ANEX1 pins directly. Figure 1.24.8 is an example of how to connect the pins in
external operation amp mode.
Set the related input peripheral function of the function select register B3 to disabled.
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A-D Converter
294
Table 1.24.9. Setting of extended analog input pins
A-D0 control register 1 ANEX0 function ANEX1 function
Bit 7 Bit 6
0 0 Not used Not used
0 1 P95 analog input Not used
1 0 Not used P96 analog input
1 1 Output to external ope-amp Input from external ope-amp
Figure 1.24.8. Example of external op-amp connection mode
(h) Power consumption reduction function
VREF connect bit (bit 5 at addresses 039716, 01D716)
The VREF connect bit (bit 5 at address 039716, 01D716) can be used to isolate the resistance ladder of the
A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so
stops any current flowing into the resistance ladder from VREF, reducing the power dissipation.
When using the A-D converter, start A-D conversion only after connecting VREF.
Do not write A-D conversion start flag and VREF connect bit to “1” at the same time. Do not clear VREF
connect bit to “0” during A-D conversion. This VREF is without reference to D-A converter's VREF.
Analog
input
External op-amp
AN
0
AN
7
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
ANEX1
ANEX0
Resistance ladder
Successive conversion register
Comparator
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A-D Converter
295
Precaution
After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D conver-
sion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D register. This
happens when the internal CPU clock is selected from divided main clock or sub-clock.
• When using the one-shot or single sweep mode
Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
• When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
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D-A Conversion
296
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Set the
function select register A3 to I/O port, the related input peripheral function of the function select register B3
to disabled and the direction register to input mode. Do not set the target port to pulled-up when D-A output
is enabled.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
(This is unrelated to bit 5 of A-D control register 1 (addresses 039716, 01D716)
Table 1.25.1 lists the performance of the D-A converter. Figure 1.25.1 shows the block diagram of the D-A
converter. Figure 1.25.2 shows the D-A control register. Figure 1.25.3 shows the D-A converter equivalent
circuit.
When the D-A converter is not used, set the D-A register to "00" and D-A output enable bit to "0".
Item Performance
Conversion method R-2R method
Resolution 8 bits
Analog output pin 2 channels
Table 1.25.1. Performance of D-A converter
D-A register i (8) (i = 0, 1)
R-2R resistance ladder
(Address 039816, 039A16)
D-Ai output enable bit (i = 0, 1)
A
AAAAAA
AAAAAA
P93 / DA0
AAAAAA
P94 / DA1
Data bus low-order bits
Figure 1.25.1. Block diagram of D-A converter
D-A Conversion
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297
Function
D-A control register
Bit name
Bit
symbol
Symbol Address When reset
DACON 039C
16
XXXXXX00
2
RW
D-A0 output enable bit
D-A1 output enable bit
Nothing is assigned.
When write, set to "0". When read, their contents are "0".
0 : Output disabled
1 : Output enabled
0 : Output disabled
1 : Output enabled
DA1E
DA0E
b7 b6 b5 b4 b3 b2 b1 b0
D-A register i
Symbol Address When reset
DAi(i=0,1) 0398
16
, 039A
16
Indeterminate
RW
Function Setting range
Output value of D-A conversion 0016 to FF16
b7 b0
V
REF
AV
SS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
D-A0 output enable bit
DA0 "1"
"0"
MSB LSB
D-A register 0 "0" "1"
Note 1: In the above figure, the D-A register value is "2A
16
".
Note 2: This circuit is the same in D-A1.
Note 3: To save power dissipation when not using the D-A converter, set the D-A output enable bit to
"0" and the D-A register to "00
16
", and prevent current flowing to the R-2R resistance.
R
Figure 1.25.2. D-A control register
Figure 1.25.3. D-A converter equivalent circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
298
AAAAA
AAAAA
Eight low-order bits
AAAAAA
AAAAAA
Eight high-order bits
Data bus high-order bits
Data bus low-order bits
AAAAAAAAAA
AAAAAAAAAA
AAAAA
AAAAA
CRC data register (16)
CRC input register (8)
AAAAAAAAAA
A
AAAAAAAA
A
AAAAAAAAAA
CRC code generating circuit
x
16
+ x
12
+ x
5
+ 1
(Addresses 037D
16
, 037C
16
)
(Address 037E
16
)
Setting range
CRC data register
Function
Symbol Address When reset
CRCD 037D
16
, 037C
16
Indeterminate
RW
CRC calculation output register 000016 to FFFF16
b15
(b7) b8
(b0) b7 b0
Setting range
CRC input register
Function
Symbol Address When reset
CRCIN 037E
16
Indeterminate
RW
Data input register 00
16
to FF
16
b7 b0
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.26.1 shows the block diagram of the CRC circuit. Figure 1.26.2 shows the CRC-related registers.
Figure 1.26.3 shows the CRC example.
Figure 1.26.1. Block diagram of CRC circuit
Figure 1.26.2. CRC-related registers
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CRC
299
b15 b0
(1) Setting 0000
16
CRC data register CRCD
[037D
16
, 037C
16
]
b0b7
b15 b0
(2) Setting 01
16
CRC input register CRCIN
[037E
16
]
2 cycles
After CRC calculation is complete
CRC data register CRCD
[037D
16
, 037C
16
]
1189
16
Stores CRC code
b0b7
b15 b0
(3) Setting 23
16
CRC input register CRCIN
[037E
16
]
After CRC calculation is complete
CRC data register CRCD
[037D
16
, 037C
16
]
0A41
16
Stores CRC code
The code resulting from sending 01
16
in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X
16
+ X
12
+ X
5
+ 1), becomes the remainder resulting from dividing (1000 0000) X
16
by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189
16
in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M32C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
1000 1000
LSB MSB
LSB MSB
98 1 1
Modulo-2 operation is
operation that complies
with the law given below.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
Figure 1.26.3. CRC example
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X-Y Converter
300
X-Y Converter
X-Y conversion rotates the 16 x 16 matrix data by 90 degrees. It can also be used to invert the top and
bottom of the 16-bit data. Figure 1.27.1 shows the XY control register.
The Xi and the Yi registers are 16-bit registers. There are 16 of each (where i= 0 to 15).
The Xi and Yi registers are mapped to the same address. The Xi register is a write-only register, while the
Yi register is a read-only register. Be sure to access the Xi and Yi registers in 16-bit units from an even
address. Operation cannot be guaranteed if you attempt to access these registers in 8-bit units.
Function
XY control register
Bit name
Bit
symbol
Symbol Address When reset
XYC 02E016 XXXXXX002
RW
Read-mode set bit
Write-mode set bit
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
0 : Data conversion
1 : No data conversion
0 : No bit mapping conversion
1 : Bit mapping conversion
XYC1
XYC0
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.27.1. XY control register
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X-Y Converter
301
X0 register (0002C0
16
)
X1 register (0002C2
16
)
X2 register (0002C4
16
)
X3 register (0002C6
16
)
X4 register (0002C8
16
)
X5 register (0002CA
16
)
X6 register (0002CC
16
)
X7 register (0002CE
16
)
X8 register (0002D0
16
)
X9 register (0002D2
16
)
X10 register (0002D4
16
)
X11 register (0002D6
16
)
X12 register (0002D8
16
)
X13 register (0002DA
16
)
X14 register (0002DC
16
)
X15 register (0002DE
16
)
Bit of Xi register b0
b15
b0 b15
Bit of Yi register
Y0 register (0002C0
16
)
Y1 register (0002C2
16
)
Y2 register (0002C4
16
)
Y3 register (0002C6
16
)
Y4 register (0002C8
16
)
Y5 register (0002CA
16
)
Y6 register (0002CC
16
)
Y7 register (0002CE
16
)
Y8 register (0002D0
16
)
Y9 register (0002D2
16
)
Y10 register (0002D4
16
)
Y11 register (0002D6
16
)
Y12 register (0002D8
16
)
Y13 register (0002DA
16
)
Y14 register (0002DC
16
)
Y15 register (0002DE
16
)
Write address
Read address
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
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AA
AA
AA
AA
AA
AA
AA
X0-Reg
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
(X register)
Y0-Reg
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
A
A
AA
AA
A
A
AA
AA
A
A
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
A
A
A
A
A
AA
AA
A
AA
AA
A
AA
(Y register)
The reading of the Yi register is controlled by the read-mode set bit (bit 0 at address 02E016).
When the read-mode set bit (bit 0 at address 02E016) is “0”, specific bits in the Xi register can be read at the
same time as the Yi register is read.
For example, when you read the Y0 register, bit 0 is read as bit 0 of the X0 register, bit 1 is read as bit 0 of
the X1 register, ..., bit 14 is read as bit 0 of the X14 register, bit 15 as bit 0 of the X15 register. Similarly,
when you read the Y15 register, bit 0 is bit 15 of the X0 register, bit 1 is bit 15 of the X1 register, ..., bit 14 is
bit 15 of the X14 register, bit 15 is bit 15 of the X15 register.
Figure 1.27.2 shows the conversion table when the read mode set bit = “0”. Figure 1.27.3 shows the X-Y
conversion example.
Figure 1.27.2. Conversion table when the read mode set bit = “0”
Figure 1.27.3. X-Y conversion example
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
X-Y Converter
302
X0,Y0 register (0002C0
16
)
X1,Y1 register (0002C2
16
)
X2,Y2 register (0002C4
16
)
X3,Y3 register (0002C6
16
)
X4,Y4 register (0002C8
16
)
X5,Y5 register (0002CA
16
)
X6,Y6 register (0002CC
16
)
X7,Y7 register (0002CE
16
)
X8,Y8 register (0002D0
16
)
X9,Y9 register (0002D2
16
)
X10,Y10 register (0002D4
16
)
X11,Y11 register (0002D6
16
)
X12,Y12 register (0002D8
16
)
X13,Y13 register (0002DA
16
)
X14,Y14 register (0002DC
16
)
X15,Y15 register (0002DE
16
)
b
0
b15
A
A
A
A
A
A
A
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AA
Bit of Xi register
Bit of Yi register
Write address
Read address
b15 b0
b15 b0
Bit of Xi register
Write address
When the read-mode set bit (bit 0 at address 02E016) is “1”, you can read the value written to the Xi register
by reading the Yi register. Figure 1.27.4 shows the conversion table when the read mode set bit = “1”.
The value written to the Xi register is controlled by the write mode set bit (bit 1 at address 02E016).
When the write mode set bit (bit 1 at address 02E016) is “0” and data is written to the Xi register, the bit
stream is written directly.
When the write mode set bit (bit 1 at address 02E016) is “1” and data is written to the Xi register, the bit
sequence is reversed so that the high becomes low and vice versa. Figure 1.27.5 shows the conversion
table when the write mode set bit = “1”.
Figure 1.27.4. Conversion table when the read mode set bit = “1”
Figure 1.27.5. Conversion table when the write mode set bit = “1”
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
303
DRAM Controller
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 1.28.1 shows the functions of the DRAM controller.
DRAM space 512KB, 1MB, 2MB, 4MB, 8MB
Bus control 2CAS/1W
Refresh ________ ________
CAS before RAS refresh, Self refresh-compatible
Function modes EDO-compatible, fast page mode-compatible
Waits 1 wait or 2 waits, programmable
To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 004016)
to specify the DRAM size. Figure 1.28.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 000516 are “112”).
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 000416).
Set wait time between after DRAM power ON and before memory processing, and processing necessary
for dummy cycle to refresh DRAM by software.
(Note 1)
Function
DRAM Control register
Bit name
Bit
symbol
Symbol Address When reset
DRAMCONT 0040
16
Indeterminate
RW
AR1
AR2
DRAM space select bit
WT
AR0
SREF
Note 1: After reset, the content of this register is indeterminate. DRAM controller starts operation after
writing to this register.
Note 2: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 3: When you set to "1", both RAS and CAS change to "L". When you set to "0", RAS and CAS
change to "H" and then normal operation (read/write, refresh) is resumed. In stop mode, there is
no control.
Note 4: Set the bus width using the external data bus width control register (address 000B16). When
selecting 8-bit bus width, CASH is indeterminate.
Self-refresh mode bit
(Note 3)
0 : Two wait
1 : One wait
b3 b2 b1
0 0 0 : DRAM ignored
0 0 1 : Must not be set
0 1 0 : 0.5MB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Must not be set
0 : Self-refresh OFF
1 : Self-refresh ON
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Wait select bit
(Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Table 1.28.1. DRAM Controller Functions
Figure 1.28.1. DRAM control register
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
304
A9(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10
A0(A22) (A22) A8 A7 A6 A5 A4 A3 A2 A1
8-bit bus mode
(A9)
(A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10)
512KB, 1MB
2MB, 4MB
8MB
MA1
MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2
A9(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10
A0(A22) A8 A7 A6 A5 A4 A3 A2 A1
A19
A19
A20
A21
A9A18 A17 A16 A15 A14 A13 A12 A11 A10
A0
(A22) A8 A7 A6 A5 A4 A3 A2 A1
A19
A21
A22
A20
(A9)
(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10
(A0)
(A22) (A20) A8 A7 A6 A5 A4 A3 A2 A1
16-bit bus mode
(A9)(A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10)
Pin function
512KB
1MB, 2MB
4MB, 8MB (Note 2)
MA1
MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2
(A9)
(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10
(A0)(A22) A8 A7 A6 A5 A4 A3 A2 A1
A19
A9
A9
A20
(A9)A18 A17 A16 A15 A14 A13 A12 A11 A10
(A0)
A8 A7 A6 A5 A4 A3 A2 A1
Row address
A19
A9
A21
A20
A22
Note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, DRAM
space).
Note 2: The figure is for 4Mx1 or 4Mx4 memory configuration. If you are using a 4Mx16 configuration,
use combinations of the following: For row addresses, MA0 to MA12; for column addresses
MA2 to MA8, MA11, and MA12. Or for row addresses MA1 to MA12; for column addresses
MA2 to MA9, MA11, MA12.
Note 3: "–" is indetermimate.
–
–
(A8)
MA0
–
–
–
–
–
–
(A8)
MA0
–
–
–
–
Row address
Row address
Pin function
Row address
Row address
Row address
Column address
Column address
Column address
Column address
Column address
Column address
• DRAM Controller Multiplex Address Output
The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the
address bus A8 to A20. Figure 1.28.2 shows the output format for multiplexed addresses.
Figure 1.28.2. Output format for multiplexed addresses
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
305
(Note)
Function
DRAM refresh interval set register
Bit name
Bit
symbol
Symbol Address When reset
REFCNT 004116 Indeterminate
RW
0 0 0 0 0 0 0 0 : 1.1 µs
0 0 0 0 0 0 0 1 : 2.1 µs
0 0 0 0 0 0 1 0 : 3.2 µs
1 1 1 1 1 1 1 1 : 272.8 µs
Note. Refresh interval at 30 MHz operating (no division).
Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32
Refresh interval set bit
REFCNT7
REFCNT6
REFCNT5
REFCNT3
REFCNT4
REFCNT1
REFCNT2
REFCNT0 b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
• Refresh _______ _______
The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set
register (address 004116). The refresh signal is not output in HOLD state. Figure 1.28.3 shows the
DRAM refresh interval set register.
Use the following formula to determine the value to set in the refresh interval set register.
Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1
Figure 1.28.3. DRAM refresh interval set register
The DRAM self-refresh operates in STOP mode, etc.
When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
306
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected
mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait
nop ;Two nops are needed
nop ;
•••
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT ;Select 4MB and one wait
nop ;Inhibit instruction to access DRAM area
nop
•••
Figures 1.28.4 to 1.28.6 show the bus timing during DRAM access.
Under
development
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
307
BCLK
MA0 to MA12
RAS
CASH
CASL
DW
D
0
to D
15
(EDO mode)
BCLK
MA0 to MA12
RAS
CASH
CASL
DW
D
0
to D
15
'H'
< Read cycle (wait control bit = 0) >
< Write cycle (wait control bit = 0) >
Row
address
Row
address
Note : Only CASL is operating in 8-bit data bus width.
Note : Only CASL is operating in 8-bit data bus width.
Column
address 1 Column
address 2 Column
address 3
Column
address 1 Column
address 2 Column
address 3
Figure 1.28.4. The bus timing during DRAM access (1)
Under
development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
308
BCLK
MA0 to MA12
RAS
CASH
CASL
DW
D0 to D15
(EDO mode)
BCLK
MA0 to MA12
RAS
CASH
CASL
DW
D0 to D15
< Read cycle (wait control bit = 1) >
< Write cycle (wait control bit = 1) >
Row
address
Row
address
'H'
Note : Only CASL is operating in 8-bit data bus width.
Note : Only CASL is operating in 8-bit data bus width.
Column
address 1 Column
address 2 Column
address 3 Column
address 4
Column
address 1 Column
address 2 Column
address 3 Column
address 4
Figure 1.28.5. The bus timing during DRAM access (2)
Under
development
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
309
BCLK
RAS
CASH
CASL
BCLK
RAS
< Self refresh cycle >
Note : Only CASL is operating in 8-bit data bus width.
"H"
DW
< CAS before RAS refresh cycle >
CASH
CASL
"H"
DW
Note : Only CASL is operating in 8-bit data bus width.
Figure 1.28.6. The bus timing during DRAM access (3)
Under
development
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
310
Programmable I/O Ports
There are 123 programmable I/O ports in 144-pin version: P0 to P15 (excluding P85). There are 87 pro-
grammable I/O ports in 100-pin version: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.29.1 to 1.29.4 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), set the corresponding function select registers A, B and C. When pins are to be used as the outputs
for the D-A converter, set the function select register A3 of each pin to I/O port, and set the direction
registers to input mode.
See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figurs 1.29.5 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____
A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/
_________ _________ _______ _______
ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.29.6 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in a port register corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to
_____ _______ _______ _______ _____ _________ _______ _______ _______ _____ _____
A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/
_________ _________ _______ _______
CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
(3) Function select register A
Figures 1.29.7 to 1.29.11 show the function select registers A.
The register is used to select port output and peripheral function output when the port functions for both
port output and peripheral function output.
Each bit of this register corresponds to each pin that functions for both port output and peripheral function
output.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
311
(4) Function select register B
Figures 1.29.12 and 1.29.13 show the function select registers B.
This register selects the first peripheral function output and second peripheral function output when mul-
tiple peripheral function outputs are assigned to a pin. For pins with a third peripheral function, this regis-
ter selects whether to enable the function select register C, or output the second peripheral function.
Each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it.
This register is enabled when the bits of the corresponding function select register A are set for peripheral
functions.
The bit 3 to bit 6 of function select register B3 is ignored bit for input peripheral function. When using DA0/DA1
and ANEX0/ANEX1, set related bit to“1”. When not using DA0/DA1 or ANEX0/ANEX1, set related bit to “0”.
(5) Function select register C
Figure 1.29.14 shows the function select register C.
This register is used to select the first peripheral function output and the third peripheral function output
when three peripheral function outputs are assigned to a pin.
This register is effective when the bits of the function select register A of the counterpart pin have selected
a peripheral function and when the function select register B has made effective the function select
register C.
The bit 7 (PSC_7) is assigned the key-in interrupt inhibit bit. Setting “1” in the key-in interrupt inhibit bit
causes no key-in interrupts regardless of the settings in the interrupt control register even if “L” is entered
______ ______
in pins KI0 to KI3. With “1” set in the key-in interrupt inhibit bit, input from a port pin cannot be effected
even if the port direction register is set to input mode.
(6) Pull-up control registers
Figures 1.29.15 to 1.29.17 show the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the
pull-up control register. However, it is possible to select pull-up resistance presence to the usable port as
I/O port by setting.
(7) Port control register
Figure 1.29.18 shows the port control register.
This register is used to choose whether to make port P1 a CMOS port or an Nch open drain. In the Nch
open drain, the CMOS port’s Pch is kept always turned off so that the port P1 cannot be a complete open
drain. Thus the absolute maximum rating of the input voltage falls within the range from “- 0.3 V to Vcc +
0.3 V”.
The port control register functions similarly to the above. Also in the case in which port P1 can be used as
a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in
memory expansion mode.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
312
Direction register
Port latch
Input to respective peripheral functions
Analog signal
Pull-up selection
Data bus
A
B
C
P0
0
to P0
7
P2
0
to P2
7
P3
0
to P3
7
P4
0
to P4
7
P5
0
to P5
2
P5
4
P5
5
P5
6
P5
7
P8
3
, P8
4
P8
6
P8
7
P10
0
to P10
3
P10
4
to P10
7
P11
4
P14
4
to P14
6
P15
2
, P15
3
P15
6
, P15
7
Option
Port
(A)
Hysteresis presence
Circuit (B)
Input to respective
peripheral functions
Circuit (C)
Analog I/F
(Note)
Note: These ports exist in 144-pin version.
: Present, : Not present
Programmable I/O ports
Figure 1.29.1. Programmable I/O ports (1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
313
P1
0
to P1
4
Option
Port
(A)
Hysteresis presence
Circuit (B)
Input to respective
peripheral functions
P1
5
to P1
7
Direction register
Port latch
Input to respective peripheral functions
Pull-up selection
Data bus
A
B
Port P1 control
register
: Present, : Not present
Programmable I/O ports with port control register
Figure 1.29.2. Programmable I/O ports (2)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
314
A
B
C
P53
P60, P61
P63 to P65, P67
P82
P90 to P92
P93 to P96
P111, P112
P113
P120
P135, P136
P121, P122
P123 to P127
P130 to P134
P137
P140, P141
P150, P151
P154, P155
Option
Port
(A)
Hysteresis presence
Circuit (B)
Input to respective
peripheral functions
Circuit (C)
Analog I/F
P70, P71
P72 to P77
P80, P81
P97
P110
P142, P143
Circuit (D)
Direction register
Port latch
Input to respective peripheral functions
Analog signal
Pull-up selection
Data bus
Function select
register A (Note 1)
Note 1: P53 is clock output select bit for BCLK.
Note 2: P70 and P71 are N-channel open drain output.
Note 3: These ports exist in 144-pin version.
D
Output from each
peripheral function
(Note 1)
(Note 2)
(Note 3)
: Present, : Not present
Programmable I/O ports with function select register
Figure 1.29.3. Programmable I/O ports (3)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
315
NMI
Data bus
Input-only port
Function
Port Pi direction register (Note 1, 2, 3)
Bit name
Bit
Symbol
Symbol Address When reset
PDi(i=0 to 5) 03E216, 03E316, 03E616, 03E716, 03EA16, 03EB16 0016
PDi(i=6 to 11) 03C216, 03C316, 03C616, 03C716, 03CA16, 03CB16 0016
PDi(i=12 to 15) 03CE16, 03CF16, 03D216, 03D316 0016
RW
PDi_0
PDi_1
PDi_2
Port Pi
0
direction
register
PDi_3
PDi_4
PDi_5
PDi_7
PDi_6
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
Port Pi
1
direction
register
Port Pi
2
direction
register
Port Pi
3
direction
register
Port Pi
4
direction
register
Port Pi
5
direction
register
Port Pi
6
direction
register
Port Pi
7
direction
register
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
0 : Input mode (Functions as an input port)
1 : Output mode (Functions as an output port)
(Note 4)
Note 1: Set bit 2 of protect register (address 000A
16
) to "1" before rewriting to the port P9 direction register.
Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register
of pins A
0
to A
22
, A
23
, D
0
to D
15
, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH,
RD/DW, BCLK/ALE/CLK
OUT
, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 3: Port 11 to 15 registers exist in 144-pin version.
Note 4: Nothing is assigned in bit5 of Port P8 direction register, bit7 to bit5 of port P11 direction register and
bit7 of port P14 direction register.
When write, set to "0". When read, its content is indeterminate.
(Note 4)
(Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.4. Programmable I/O ports (4)
Figure 1.29.5. Direction register
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
316
Function
Port Pi register (Note 1, 2, 3)
Bit name
Bit
symbol
Symbol Address When reset
Pi(i=0 to 5) 03E0
16
, 03E1
16
, 03E4
16
, 03E5
16
, 03E8
16
, 03E9
16
Indeterminate
Pi(i=6 to 11) 03C0
16
, 03C1
16
, 03C4
16
, 03C5
16
, 03C8
16
, 03C9
16
Indeterminate
Pi(i=12 to 15) 03CC
16
, 03CD
16
, 03D0
16
, 03D1
16
Indeterminate
RW
Pi_0
Pi_1
Pi_2
Port Pi
0
register
Pi_3
Pi_4
Pi_5
Pi_7
Pi_6
Port Pi
1
register
Port Pi
2
register
Port Pi
3
register
Port Pi
4
register
Port Pi
5
register
Port Pi
6
register
Port Pi
7
register
: "L" level
: "H" level
0
1
: "L" level
: "H" level
0
1
: "L" level
: "H" level
0
1
: "L" level
: "H" level
0
1
: "L" level
: "H" level
0
1
: "L" level
: "H" level
0
1(Note 5) (Note 6)
: "L" level
: "H" level
0
1 (Note 6)
: "L" level
: "H" level
0
1(Note 6)
(Note 4)
(Note 4)
Note 1: Data is input and output to and from each pin by reading and writing to and from each corresponding bit.
Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register
of pins A
0
to A
22
, A
23
, D
0
to D
15
, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, WRH/BHE/CASH,
RD/DW, BCLK/ALE/CLK
OUT
, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 3: Port 11 to 15 direction registers exist in 144-pin version.
Note 4: Port P7
0
and P7
1
output high impedance because of N-channel open drain output.
Note 5: Port P8
5
is read only (There is not W).
Note 6: Nothing is assigned in bit7 to bit5 of port P11 and bit7 of port P14.
When write, set to "0". When read, its content is indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.6. Port register
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
317
Function
Function select register A0
Bit name
Bit
symbol
Symbol Address When reset
PS0 03B0
16
00
16
RW
PS0_0
PS0_1
Port P60 function
select bit
PS0_3
PS0_4
PS0_5
PS0_7
0 : I/O port
1 : UART0 output (RTS0)
0 : I/O port
1 : UART0 output (CLK0 output)
0 : I/O port
1 : UART0 output (TXD0/SDA0)
0 : I/O port
1 : Function that was selected in bit4 of
function select register B0
0 : I/O port
1 : UART1 output (CLK1 output)
0 : I/O port
1 : UART1 output (TXD1/SDA1)
Port P61 function
select bit
Port P63 function
select bit
Port P64 function
select bit
Port P65 function
select bit
Port P67 function
select bit
PS0_2 Port P62 function
select bit
0 : I/O port
1 : Function that was selected in bit2 of
function select register B0
PS0_6 Port P66 function
select bit
0 : I/O port
1 : Function that was selected in bit6 of
function select register B0
b7 b6 b5 b4 b3 b2 b1 b0
Function
Function select register A1
Bit name
Bit
symbol
Symbol Address When reset
PS1 03B1
16
00
16
RW
PS1_0
PS1_1
Port P7
0
function
select bit
PS1_3
PS1_4
PS1_5
PS1_7
0 : I/O port
1 : Function that was selected in bit0 of
function select register B1
0 : I/O port
1 : Function that was selected in bit1 of
function select register B1
0 : I/O port
1 : Function that was selected in bit3 of
function select register B1
0 : I/O port
1 : Function that was selected in bit4 of
function select register B1
0 : I/O port
1 : Function that was selected in bit5 of
function select register B1
0 : I/O port
1 : Intelligent I/O group 0 output
(OUTC0
1
/ISCLK
0
)
Port P7
1
function
select bit
Port P7
3
function
select bit
Port P7
4
function
select bit
Port P7
5
function
select bit
Port P7
7
function
select bit
PS1_6 0 : I/O port
1 : Function that was selected in bit6 of
function select register B1
Port P7
6
function
select bit
PS1_2 Port P7
2
function
select bit
0 : I/O port
1 : Function that was selected in bit2 of
function select register B1
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.7. Function select register A (1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
318
Function
Function select register A2
Bit name
Bit
symbol
Symbol Address When reset
PS2 03B416 00X000002
RW
PS2_0
PS2_1
Port P80 function
select bit
0 : I/O port
1 : Function that was selected in bit0 of
function select register B2
0 : I/O port
1 : Function that was selected in bit1 of
function select register B2
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Port P81 function
select bit
PS2_2 Port P82 function
select bit
0 : I/O port
1 : Function that was selected in bit2 of
function select register B2
Reserve bit Must always be "0".
Reserve bit Must always be "0".
b7 b6 b5 b4 b3 b2 b1 b0
0000
Function
Function select register A3 (Note)
Bit Name
Bit
symbol
Symbol Address When reset
PS3 03B516 0016
RW
PS3_0
PS3_1
Port P90 function
select bit
PS3_3
PS3_4
PS3_5
PS3_7
0 : I/O port
1 : UART3 output (CLK3)
0 : I/O port
1 : Function that was selected in bit1 of
function select register B3
0 : I/O port
1 : UART3 output (RTS3)
0 : I/O port
1 : UART4 output (CLK4)
0 : I/O port
1 : Function that was selected in bit7 of
function select register B3
Port P91 function
select bit
Port P93 function
select bit
Port P94 function
select bit
Port P95 function
select bit
Port P97 function
select bit
PS3_6 0 : I/O port
1 : UART4 output (TXD4/SDA4)
Port P96 function
select bit
PS3_2 Port P92 function
select bit
0 : I/O port
1 : Function that was selected in bit2 of
function select register B3
0 : I/O port
1 : UART4 output (RTS4)
Note :Set bit 2 of protect register (address 000A16) to "1" before rewriting to this register.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.8. Function select register A (2)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
319
Function
Function select register A5
Bit name
Bit
symbol
Symbol Address When reset
PS5 03B916 XXX0 00002
RW
PS5_0
PS5_1
Port P110 function
select bit
0 : I/O port
1 : Intelligent I/O group 1 output
(OUTC10/ ISTXD1/BE1OUT)
0 : I/O port
1 : Intelligent I/O group 1 output
(OUTC11/ ISCLK1)
Note: This register exists in 144-pin version.
Port P111 function
select bit
PS5_2 Port P112 function
select bit 0 : I/O port
1 : Intelligent I/O group 1 output (OUTC12)
PS5_3 Port P113 function
select bit 0 : I/O port
1 : Intelligent I/O group 1 output (OUTC13)
Reserve bit Must always be "0".
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
Function
Function select register A6
Bit name
Bit
symbol
Symbol Address When reset
PS6 03BC
16
00
16
RW
PS6_0
PS6_1
Port P120 function
select bit
PS6_3
PS6_4
PS6_5
PS6_7
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC30)
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC31)
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC33)
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC34)
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC35)
0 : I/O port
1 : Intelligent I/O group 3 output (OUTC37)
Port P121 function
select bit
Port P123 function
select bit
Port P124 function
select bit
Port P125 function
select bit
Port P127 function
select bit
PS6_6 0 : I/O port
1 : Intelligent I/O group 3 output (OUTC36)
Port P126 function
select bit
PS6_2 Port P122 function
select bit 0 : I/O port
1 : Intelligent I/O group 3 output (OUTC32)
Note: This register exists in 144-pin version.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.9. Function select register A (3)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
320
Function
Function select register A7
Bit name
Bit
symbol
Symbol Address When reset
PS7 03BD
16
00
16
RW
PS7_0
PS7_1
Port P13
0
function
select bit
PS7_3
PS7_4
PS7_5
PS7_7
0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
4
)
0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
5
)
0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
3
)
0 : I/O port
1 : Intelligent I/O group 2 output
(OUTC2
0
/IST
X
D
2
/IE
OUT
)
0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
2
)
0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
7
)
Port P13
1
function
select bit
Port P13
3
function
select bit
Port P13
4
function
select bit
Port P13
5
function
select bit
Port P13
7
function
select bit
PS7_6 0 : I/O port
1 : Intelligent I/O group 2 output
(OUTC2
1
/ISCLK
2
)
Port P13
6
function
select bit
PS7_2 Port P13
2
function
select bit 0 : I/O port
1 : Intelligent I/O group 2 output (OUTC2
6
)
Note: This register exists in 144-pin version.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Function
Function select register A8
Bit name
Bit
symbol
Symbol Address When reset
PS8 03A016 X00000002
RW
PS8_0
PS8_1
Port P140 function
select bit 0 : I/O port
1 : Intelligent I/O group 1 output (OUTC14)
0 : I/O port
1 : Intelligent I/O group 1 output (OUTC15)
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Port P141 function
select bit
PS8_2 Port P142 function
select bit 0 : I/O port
1 : Intelligent I/O group 1 output (OUTC16)
0 : I/O port
1 : Intelligent I/O group 1 output (OUTC17)
PS8_3 Port P143 function
select bit
000
Reserve bit Must always be "0".
Note: This register exists in 144-pin version.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.10. Function select register A (4)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
321
Function
Function select register A9
Bit name
Bit
symbol
Symbol Address When reset
PS9 03A116 0016
RW
PS9_0
PS9_1
Port P150 function
select bit
PS9_4
PS9_5
0 : I/O port
1 : Intelligent I/O group 0 output
(OUTC00/ ISTXD0/BE0OUT)
0 : I/O port
1 : Intelligent I/O group 0 output
(OUTC01/ ISCLK0)
0 : I/O port
1 : Intelligent I/O group 0 output (OUTC04)
0 : I/O port
1 : Intelligent I/O group 0 output (OUTC05)
Port P151 function
select bit
Port P154 function
select bit
Port P155 function
select bit
Reserve bit Must always be "0".
Reserve bit Must always be "0".
Note: This register exists in 144-pin version.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Figure 1.29.11. Function select register A (5)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
322
Function
Function select register B1
Bit name
Bit
symbol
Symbol Address When reset
PSL1 03B316 0016
RW
PSL1_0
PSL1_1
Port P70 peripheral
function select bit
PSL1_3
PSL1_4
PSL1_5
0 : Function that was selected in bit0 of
function select register C
1 : Timer output (TA0OUT)
0 : Function that was selected in bit1 of
function select register C
1 : UART2 output (STXD2)
0 : Function that was selected in bit3 of
function select register C
1 : Three-phase PWM output (V)
0 : Function that was selected in bit4 of
function select register C
1 : Three-phase PWM output (W)
0 : Three-phase PWM output (W)
1 :
Intelligent I/O group 1 output (OUTC12)
Port P71 peripheral
function select bit
Port P73 peripheral
function select bit
Port P74 peripheral
function select bit
Port P75 peripheral
function select bit
PSL1_6 0 : Function that was selected in bit6 of
function select register C
1 : Timer output (TA3OUT)
Port P76 peripheral
function select bit
PSL1_2 Port P72 peripheral
function select bit
0 : Function that was selected in bit2 of
function select register C
1 : Timer output (TA1OUT)
Reserve bit Must always be "0".
b7 b6 b5 b4 b3 b2 b1 b0
0
Function
Function select register B0
Bit name
Bit
symbol
Symbol Address When reset
PSL0 03B216 0016
RW
PSL0_4 Port P64 peripheral
function select bit
0 : UART1 output (RTS1)
1 : Intelligent I/O group 2 output
(OUTC21/ISCLK2)
PSL0_6 Port P66 peripheral
function select bit 0 : UART1 output (SCL1)
1 : UART1 output (STXD1)
PSL0_2 Port P62 peripheral
function select bit 0 : UART0 output (SCL0)
1 : UART0 output (STXD0)
Reserve bit Must always be "0".
Reserve bit Must always be "0".
Reserve bit Must always be "0".
Reserve bit Must always be "0".
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Figure 1.29.12. Function select register B (1)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
323
Function
Function select register B2
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Bit name
Bit
symbol
Symbol Address When reset
PSL2 03B616 00X000002
RW
PSL2_0
PSL2_1
Port P8
0
peripheral
function select bit 0 : Timer output (TA4
OUT
)
1 : Three-phase PWM output (U)
Port P8
1
peripheral
function select bit
PSL2_2 0 :
Intelligent I/O group 3 output (OUTC3
2
)
1 : CAN output (CAN
OUT
)
Port P8
2
peripheral
function select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : Three-phase PWM output (U)
1 : Intelligent I/O group 3 output
(OUTC3
0
)
Reserve bit Must always be "0".
Reserve bit Must always be "0".
0000
Function
Function select register B3
Bit name
Bit
symbol
Symbol Address When reset
PSL3 03B7
16
00
16
RW
PSL3_1
PSL3_3
PSL3_4
PSL3_5
PSL3_7
0 : UART3 output (SCL
3
)
1 : UART3 output (ST
X
D
3
)
0 : Input peripheral function enabled
(Expect DA0 output)
1 :
Input peripheral function disabled (DA0 output)
0 : Input peripheral function enabled
(Expect DA1 output)
1 :
Input peripheral function disabled (DA1 output)
0 : Input peripheral function enabled
(Expect ANEX0 output)
1 :
Input peripheral function disabled (ANEX0 output)
0 : UART4 output (SCL
4
)
1 : UART4 output (ST
X
D
4
)
Port P9
1
peripheral
function select bit
Port P9
3
peripheral
function select bit
Port P9
4
peripheral
function select bit
Port P9
5
peripheral
function select bit
Port P9
7
peripheral
function select bit
PSL3_6 0 : Input peripheral function enabled
(Expect ANEX1 output)
1 :
Input peripheral function disabled (ANEX1 output)
Port P9
6
peripheral
function select bit
PSL3_2 Port P9
2
peripheral
function select bit
0 : UART3 output (T
X
D
3
/SDA
3
)
1 : Intelligent I/O group 2 output
(OUTC2
0
/IE
OUT
)
(Note)
(Note)
(Note)
(Note)
Note: Although DA0, DA1, ANEX0 and ANEX1 can be used when "0" is set in these bits, the power supply
may be increased.
b7 b6 b5 b4 b3 b2 b1 b0
Reserve bit Must always be "0".
0
Figure 1.29.13. Function select register B (2)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
324
Function
Function select register C
Bit name
Bit
symbol
Symbol Address When reset
PSC 03AF16 00X000002
RW
PSC_0
PSC_3
PSC_4
PSC_7
0 : UART2 output (TXD2/SDA2)
1 : Intelligent I/O group 2 output
(OUTC20/ ISTXD2/IEOUT)
0 : UART2 output (RTS2)
1 : Intelligent I/O group 1 output
(OUTC10/ ISTXD1/BE1OUT)
0 : Timer output (TA2OUT)
1 : Intelligent I/O group 1 output
(OUTC11/ ISCLK1)
0 : Enabled
1 : Disabled
Port P70 peripheral
function select bit
Port P73 peripheral
function select bit
Port P74 peripheral
function select bit
Key input interrupt
disable bit
PSC_6 0 : Intelligent I/O group 0 output
(OUTC00/ISTXD0/BE0OUT)
1 : CAN output (CANOUT)
Port P76 peripheral
function select bit
PSC_2 Port P72 peripheral
function select bit 0 : UART2 output (CLK2)
1 : Three-phase PWM output (V)
Noting is assigned. When write, set to "0".
When read, its content is indeterminate.
PSC_1 Port P71 peripheral
function select bit 0 : UART2 output (SCL2)
1 : Intelligent I/O group 2 output (OUTC22)
(Note)
Note: Although DA0, DA1, ANEX0 and ANEX1 can be used when "0" is set in this bit, the power supply
may be increased.
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.14. Function select register C
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
325
Function
Pull-up control register 0
Bit name
Bit
symbol
Symbol Address When reset
PUR0 03F0
16
00000000
2
RW
PU00
PU01
PU02
P0
0
to P0
3
pull-up
PU03
PU04
PU05
PU07
PU06
0 : Not pulled high
1 : Pulled high
P0
4
to P0
7
pull-up
P1
0
to P1
3
pull-up
P1
4
to P1
7
pull-up
P2
0
to P2
3
pull-up
P2
4
to P2
7
pull-up
P3
0
to P3
3
pull-up
P3
4
to P3
7
pull-up
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode,
do not set the pull-up control register. However, it is possible to select pull-up resistance
presence to the usable port as I/O port by setting.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Function
Pull-up control register 1
Bit name
Bit
symbol
Symbol Address When reset
PUR1 03F116 XXXX00002
RW
PU10
PU11
PU12
P40 to P43 pull-up
PU13
0 : Not pulled high
1 : Pulled high
P44 to P47 pull-up
P50 to P53 pull-up
P54 to P57 pull-up
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode,
do not set the pull-up control register. However, it is possible to select pull-up resistance
presence to the usable port as I/O port by setting.
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.15. Pull-up control register (1)
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
326
Function
Pull-up control register 3
Bit name
Bit
symbol
Symbol Address When reset
PUR3 03DB
16
00000000
2
RW
PU30
PU31
PU32
P10
0
to P10
3
pull-up
PU33
PU34
PU35
PU37
PU36
0 : Not pulled high
1 : Pulled high
P10
4
to P10
7
pull-up
P11
0
to P11
3
pull-up
P11
4
pull-up
P12
0
to P12
3
pull-up
P12
4
to P12
7
pull-up
P13
0
to P13
3
pull-up
P13
4
to P13
7
pull-up
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
<144-pin version>
b7 b6 b5 b4 b3 b2 b1 b0
Function
Pull-up control register 2
Bit name
Bit
symbol
Symbol Address When reset
PUR2 03DA16 000000002
RW
PU20
PU21
PU22
P6
0
to P6
3
pull-up
PU23
PU24
PU25
PU27
PU26
0 : Not pulled high
1 : Pulled high
P6
4
to P6
7
pull-up
P7
0
to P7
3
pull-up
P7
4
to P7
7
pull-up
P8
0
to P8
3
pull-up
P8
4
to P8
7
pull-up
P9
0
to P9
3
pull-up
P9
4
to P9
7
pull-up
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
(Note 2)
(Note 3)
Note 1: Since P7
0
and P7
1
are N-channel open drain ports, pull-up is not available for them.
Note 2: Except port P8
5
.
(Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.16. Pull-up control register (2)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
327
Function
Pull-up control register 4
Bit name
Bit
symbol
Symbol Address When reset
PUR4 03DC
16
XXXX0000
2
RW
PU40
PU41
PU42
P14
0
to P14
3
pull-up
PU43
0 : Not pulled high
1 : Pulled high
P14
4
to P14
6
pull-up
P15
0
to P15
3
pull-up
P15
4
to P15
7
pull-up
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
0 : Not pulled high
1 : Pulled high
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Note: This register exists in 144-pin version..
(Note)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.17. Pull-up control register (3)
Function
Pull-up control register 3
Bit name
Bit
symbol
Symbol Address When reset
PUR3 03DB16 0016
RW
PU30
PU31
P100 to P103 pull-up 0 : Not pulled high
1 : Pulled high
P104 to P107 pull-up 0 : Not pulled high
1 : Pulled high
Reserve bit Must always be "0".
<100-pin version>
b7 b6 b5 b4 b3 b2 b1 b0
000000
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
328
Function
Port control register
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Bit name
Bit
symbol
Symbol Address When reset
PCR 03FF16 XXXXXXX02
RW
PCR0 Port P1 control
register 0 : Function as common CMOS port
1 : Function as N-ch open drain port
(Note 2)
Note 1: Since P1 operates as the data bus in memory expansion mode and microprocessor
mode, do not set the port control register. However, it is possible to select CMOS port
or N-channel open drain pin to the usable port as I/O port by setting.
Note 2: This function is designed to permanently turn OFF the Pch of the CMOS port.
It dose not make port P1 a full open drain.
Therefore, the absolute maximum input voltage rating is [-3 to VCC + 3.0V].
(Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.29.18. Port control register and input function select register
Input function select register
Symbol Address When reset
IPS
017816 00000X002
RWBit name Function
Bit
symbol
b7 b0
IPS0
IPS1
Group 0 input pin
select bit 0
ISRxD2/IEIN function
pin select bit
IPS5
IPS6 0 : P64
1 : P136
Assigns functions of INPC00, INPC01
/ISCLK0 and INPC02/ISRxD0/BE0IN
to the following ports.
0 : P76, P77, P80
1 : P150, P151, P152
: P71
: P91
: P135
: Must not be set
b5
0
0
1
1
b4
0
1
0
1
Assigns functions of INPC11/ISCLK1
and INPC12/ISRxD1/BE1IN to the
following ports.
0 : P74, P75
1 : P111, P112
Group 1 input pin
select bit 1
IPS2
0 : Input peripheral function is enabled
1 : Input peripheral function is disabled
P15 input peripheral
function select bit
ISCLK2 function
pin select bit
IPS4
IPS3 0 : P77
1 : P83
CANIN function
pin select bit
(Note)
Note: Although AD input pin can be used when "0" is set in this bit,
the power supply may be increased.
Reserve bit Must always be "0".
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
329
Pin name Connection
Ports P0 to P15 (excluding P85)
XOUT (Note 2)
AVSS, VREF, BYTE
AVCC
After setting for input mode, connect every pin to VSS via a resistance
(pull-down); or after setting for output mode, leave these pins open.
Open
Connect to VCC
Connect to VSS
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.
NMI Connect via resistance to VCC (pull-up)
(Note 1)
Pin name Connection
Ports P6 to P15 (excluding P85)
AVSS, VREF
AVCC
Open
Connect to VCC
Connect to VSS
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.
HOLD, RDY, NMI Connect via resistance to VCC (pull-up)
BHE, ALE, HLDA,
XOUT(Note 2), BCLK
After setting for input mode, connect every pin to VSS via a resistance
(pull-down); or after setting for output mode, leave these pins open.
(Note 1)
Port P0 to P15 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
X
OUT
AV
CC
BYTE
AV
SS
V
REF
Microcomputer
V
CC
V
SS
In single-chip mode
Port P6 to P15 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
X
OUT
AV
CC
AV
SS
V
REF
Open
Microcomputer
V
CC
V
SS
In memory expansion mode or
in microprocessor mode
HOLD
RDY
ALE
BCLK
BHE
HLDA
Open
Open Open
·
·
··
·
·
Note : Ports P11 to P15 exist in 144-pin version.
(Note)
Table 1.29.1. Example connection of unused pins in single-chip mode
Table 1.29.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Figure 1.29.19. Example connection of unused pins
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
330
Table 1.29.3. Port P6 output control
PS0 register PSL0 register
Bit 0 0: P60Must set to "0"
________
1: UART0 output (RTS0)(Note)
Bit 1 0: P61Must set to "0"
1: UART0 output (CLK0)(Note)
Bit 2 0: P620: UART0 output (SCL0)
1: Selected by PSL0 register 1: UART0 output (STxD0)
Bit 3 0: P63Must set to "0"
1: UART0 output (TxD0/SDA0)(Note)
Bit 4 0: P64________
0: UART1 output (RTS1)
1: Selected by PSL0 register 1: Intelligent I/O group 2 (OUTC21/ISCLK2)
Bit 5 0: P65Must set to "0"
1: UART1 output (CLK1)(Note)
Bit 6 0: P660: UART1 output (SCL1)
1: Selected by PSL0 register 1: UART1 output (STxD1)
Bit 7 0: P67Must set to "0"
1: UART1 output (TxD1/SDA1)(Note)
PS0 register: Function select register A0
PSL0 register: Function select register B0
Note : Select "0" in corresponding bit of PSL0 register.
Table 1.29.4. Port P7 output control
PS1 register PSL1 register PSC register
Bit 0 0: P700: Selected by PSC register 0: UART2 output (TxD2/SDA2)
1: Selected by PSL1 register 1: TImer output (TA0OUT)(Note 1) 1: Intelligent I/O group 2
(OUTC20/ISTxD2/IEOUT)
Bit 1 0: P710: Selected by PSC register 0: UART2 output (SCL2)
1: Selected by PSL1 register 1: UART2 output (STxD2)(Note 1) 1: Intelligent I/O group 2
(OUTC22)
Bit 2 0: P720: Selected by PSC register 0: UART2 output (CLK2)
1: Selected by PSL1 register 1: TImer output (TA1OUT)(Note 1) 1: Three-phase PWM output (V)
Bit 3 0: P730: Selected by PSC register _______
0: UART2 output (RTS2)
1: Selected by PSL1 register __
1: Three-phase PWM output (V)(Note 1) 1: Intelligent I/O group 1
(OUTC10/ISTxD1/BE1OUT)
Bit 4 0: P740: Selected by PSC register 0: TImer output (TA2OUT)
1: Selected by PSL1 register 1: Three-phase PWM output (W)(Note 1) 1: Intelligent I/O group 1
(OUTC11/ISCLK1)
Bit 5 0: P75___
0: Three-phase PWM output (W)(Note 1) Must set to "0"
1: Selected by PSL1 register 1: Intelligent I/O group 1
(OUTC12)
Bit 6 0: P760: Selected by PSC register 0: Intelligent I/O group 0
(OUTC00/ISTxD0/BE0OUT)
1: Selected by PSL1 register 1: TImer output (TA3OUT) 1: CAN output (CANOUT)
Bit 7 0: P77Must set to "0"
0: Key input interrupt signal enabled
1: Intelligent I/O group 0
1: Key input interrupt signal disabled
(OUTC01/ISCLK0)
PS1 register: Function select register A1
PSL1 register: Function select register B1
PSC register: Function select register C
Note 1: Select "0" in corresponding bit of PSC register.
Note 2: Select "0" in corresponding bit of PSL1 register.
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
331
Table 1.29.5. Port P8 output control
PS2 register PSL2 register
Bit 0 0: P800: Timer output (TA4OUT)
1: Selected by PSL2 register 1: Three-phase PWM output (U)
Bit 1 0: P81____
0: Three-phase PWM output (U)
1: Selected by PSL2 register 1: Intelligent I/O group 3(OUTC30)
Bit 2 0: P820: Intelligent I/O group 3(OUTC32)
1: Selected by PSL2 register 1: CAN output (CANOUT)
Bit 3 to 7 Must set to "0"
PS2 register: Function select register A2
PSL2 register: Function select register B2
Table 1.29.6. Port P9 output control
PS3 register PSL3 register
Bit 0 0: P90Must set to "0"
1: UART3 output (CLK3)(Note)
Bit 1 0: P910: UART3 output (SCL3)
1: Selected by PSL3 register 1: UART3 output (STxD3)
Bit 2 0: P920: UART3 output (TxD3/SDA3)
1: Selected by PSL3 register 1: Intelligent I/O group 2 (OUTC2 0/IEOUT)
Bit 3 0: P930: Except DA0 output
________
1: UART3 output (RTS3)(Note) 1: DA0 output
Bit 4 0: P940: Except DA1 output
________
1: UART4 output (RTS4)(Note) 1: DA1 output
Bit 5 0: P950: Except ANEX0
1: UART4 output (CLK4)(Note) 1: ANEX0
Bit 6 0: P960: Except ANEX1
1: UART4 output (TxD4/SDA4)(Note) 1: ANEX1
Bit 7 0: P970: UART4 output (SCL4)
1: Selected by PSL3 register 1: UART4 output (STxD4)
PS3 register: Function select register A3
PSL3 register: Function select register B3
Note : Select "0" in corresponding bit of PSL3 register.
Table 1.29.7. Port P11 output control
PS5 register
Bit 0 0: P110
1: Intelligent I/O group 1(OUTC10/ISTxD1/BE1OUT)
Bit 1 0: P111
1: Intelligent I/O group 1(OUTC11/ISCLK1)
Bit 2 0: P112
1: Intelligent I/O group 1(OUTC12)
Bit 3 0: P113
1: Intelligent I/O group 1(OUTC13)
Bit 4 to 7 Must set to "0"
PS5 register: Function select register A5
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
332
Table 1.29.8. Port P12 output control
PS6 register
Bit 0 0: P120
1: Intelligent I/O group 3(OUTC30)
Bit 1 0: P121
1: Intelligent I/O group 3(OUTC31)
Bit 2 0: P122
1: Intelligent I/O group 3(OUTC32)
Bit 3 0: P123
1: Intelligent I/O group 3(OUTC33)
Bit 4 0: P124
1: Intelligent I/O group 3(OUTC34)
Bit 5 0: P125
1: Intelligent I/O group 3(OUTC35)
Bit 6 0: P126
1: Intelligent I/O group 3(OUTC36)
Bit 7 0: P127
1: Intelligent I/O group 3(OUTC37)
PS6 register: Function select register A6
Table 1.29.9. Port P13 output control
PS7 register
Bit 0 0: P130
1: Intelligent I/O group 2(OUTC24)
Bit 1 0: P131
1: Intelligent I/O group 2(OUTC25)
Bit 2 0: P132
1: Intelligent I/O group 2(OUTC26)
Bit 3 0: P133
1: Intelligent I/O group 2(OUTC23)
Bit 4 0: P134
1: Intelligent I/O group 2(OUTC20/ISTxD2/IEOUT)
Bit 5 0: P135
1: Intelligent I/O group 2(OUTC22)
Bit 6 0: P136
1: Intelligent I/O group 2(OUTC21/ISCLK2)
Bit 7 0: P137
1: Intelligent I/O group 2(OUTC27)
PS7 register: Function select register A7
Table 1.29.10. Port P14 output control
PS8 register
Bit 0 0: P140
1: Intelligent I/O group 1(OUTC14)
Bit 1 0: P141
1: Intelligent I/O group 1(OUTC15)
Bit 2 0: P142
1: Intelligent I/O group 1(OUTC16)
Bit 3 0: P143
1: Intelligent I/O group 1(OUTC17)
Bit 4 to 7 Must set to "0"
PS8 register: Function select register A8
Under
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Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
333
Table 1.29.11. Port P15 output control
PS9 register
Bit 0 0: P150
1: Intelligent I/O group 0 (OUTC00/ISTxD0/BEOUT)
Bit 1 0: P151
1: Intelligent I/O group 0 (OUTC01/ISCLK0)
Bit 2 to 3 Must set to "0"
Bit 4 0: P154
1: Intelligent I/O group 0 (OUTC04)
Bit 5 0: P155
1: Intelligent I/O group 0 (OUTC05)
Bit 6 to 7 Must set to "0"
PS9 register: Function select register A9
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VDC
334
VDC
When power-supply voltage is 3.3V or under, set the internal VDC (Voltage Down Converter) unused.
Follow the steps given below to disable the VDC.
(1) Set bit 3 of the protect register to "1".
(2) Set the VDC control register 0 to "0F16".
(3) Set the VDC control register 0 to "8F16".
(4) Set bit 3 of the protect register to "0".
These steps must be performed after reset as immediately as possible with divide-by-8 clock. When the
VDC select bit has been set to "112" once, do not set any other values.
Figure 1.30.1 shows the VDC control register 0.
VDC00
VDC01
VDC02
VDC03
VDC05
VDC07
VDC04
(Note 2)
Function
Note 1: Set bit 3 of the protect register (address 000A16) to "1" before rewriting this register.
Rewriting this register should be performed only when the VDC is to be off.
Note 2: This bit enables the setting of bit 0 to bit 3.
Set bit 7 to "0" first, and then write values to bit 0 to bit 3. After that, write "1" to bit 7.
The state changes at the time "1" is written to bit 7.
VDC control register 0 (Note 1)
VDC select bit
Reserved bit
VDC enable bit
1 1: VDC unused
0: VDC Off
1: VDC On
Must set to "0"
Bit name
Bit
symbol
Symbol Address When reset
VDC0 001B16 0016
RW
b1b0
b2
VDC06
Do not set any values other than "11".
b3
1 1: VDC reference voltage Off
Do not set any values other than "11".
VDC reference voltage
select bit
b7 b6 b5 b4 b3 b2 b1 b0
Figure 1.30.1. VDC control register
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
335
Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register while reloading gets “FFFF16”. Reading the timer Ai
register after setting a value in the timer Ai register with a count halted but before the counter starts
counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register while reloading gets “FFFF16” by underflow or
“000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a
count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
(3) In the case of using as “Free-Run type”, the timer register contents may be unknown when counting
begins. If the timer register is set before counting has started, then the starting value will be unknown.
• In the case where the up/down count will not be changed.
Enable the “Reload” function and write to the timer register before counting begins. Rewrite
the value to the timer register immediately after counting has started. If counting up, rewrite
“000016” to the timer register. If counting down, rewrite “FFFF16” to the timer register. This
will cause the same operation as “Free-Run type” mode.
• In the case where the up/down count has changed.
First set to “Reload type” operation. Once the first counting pulse has occurred, the timer
may be changed to “Free-Run type”.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The output from the one-shot timer synchronizes with the count source generated internally. There-
fore, when an external trigger has been selected, a delay of one cycle of count source as maximum
occurs between the trigger input to the TAiIN pin and the one-shot timer output.
(3) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
•Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(4) If a trigger occurs while a count is in progress, after the counter performs one down count following the
reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To
generate a trigger while a count is in progress, generate the second trigger after an elapse longer
than one cycle of the timer's count source after the previous trigger occurred.
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
336
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
•Changing operation mode from timer mode to PWM mode.
•Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Bi register while reloading gets “FFFF16”. Reading the timer Bi
register after setting a value in the timer Bi register with a count halted but before the counter starts
counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
(3) The value of the counter is indeterminate at the beginning of a count. Therefore, the timer Bi overflow
flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count
start and an effective edge input.
Stop Mode and Wait Mode ____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading from the WAIT instruc-
tion and the instruction that sets all clock stop control bits to “1” in the instruction queue. Therefore,
insert a minimum of 4 NOPs after the WAIT instruction and the instruction that sets all clock stop
control bits to “1” in order to flush the instruction queue.
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A-D Converter
(1) Write to each bit (except bit 6) of A-D i (i=0,1) control register 0, to each bit of A-D i control register 1,
and to each bit of A-D i control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
(5) When f(XIN) is faster than 10 MHz, make the frequency 10 MHz or less by dividing.
(6) Output impedance of sensor at A-D conversion (Reference value)
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 1.31.1 has to
be completed within a specified period of time T. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-
D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
Vc is generally VC = VIN {1 – e}
And when t = T, VC=VIN – VIN=VIN(1 – )
e =
– =ln
Hence, R0 = – – R
With the model shown in Figure 1.31.1 as an example, when the difference between VIN and VC becomes
0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in
time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at
time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added
to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 µs in the A-D conversion mode with sample & hold. Output
impedance R0 for sufficiently charging capacitor C within time T is determined as follows.
T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence,
R0 = –– 7.8 X103 3.0 X 103
C (R0 +R)
T
C (R0 + R)
T
–
C (R0 + R)
t
–
Y
XY
X
Y
X
Y
X
C • ln
T
Y
X
3.0 X 10 –12 • ln 1024
0.1
0.3 X 10-6
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V
C
C (3.0pF)
V
IN
Internal circuit of microprocesso
r
Sensor-equivalent circuit
R (7.8k )
R
0
Ω
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con-
verter turns out to be approximately 3.0 kΩ. Tables 1.31.1 and 1.31.2 show output impedance values
based on the LSB values.
Figure 1.31.1 A circuit equivalent to the A-D conversion terminal
(7) After A-D conversion is complete, if the CPU reads the A-D register at the same time as the A-D
conversion result is being saved to A-D register, wrong A-D conversion value is saved into the A-D
register. This happens when the internal CPU clock is selected from divided main clock or sub-clock.
• When using the one-shot or single sweep mode
Confirm that A-D conversion is complete before reading the A-D register.
(Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.)
• When using the repeat mode or repeat sweep mode 0 or 1
Use the undivided main clock as the internal CPU clock.
Interrupts
(1) Setting the stack pointer
• The value of the stack pointer is initialized to 00000016 immediately after reset. Accepting an
interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard-
_______
ing the first instruction immediately after reset, generating any interrupts including the NMI inter-
rupt is prohibited.
Set an even address to the stack pointer so that operating efficiency is increased.
_______
(2) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin via a
resistance (pulled-up) if unused.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8
register allows reading the pin value. Use the reading of this pin only for establishing the pin level
_______
at the time when the NMI interrupt is input. _______
• Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI
pin.
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Tables 1.31.1. Output impedance values based on the LSB values (10-bit mode) Reference value
Tables 1.31.2. Output impedance values based on the LSB values (8-bit mode) Reference value
f(X
IN
)
(MHz) Cycle
(µs) Sampling time
(µs) R
(kΩ)C
(pF) Resolution
(LSB) R0max
(kΩ)
10 0.1 0.3
(3 X cycle,
Sample & hold
bit is enabled)
7.8 3.0 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
3.0
4.5
5.3
5.9
6.4
6.8
7.2
7.5
7.8
8.1
0.4
0.9
1.3
1.7
2.0
2.2
2.4
2.6
2.8
10 0.1 0.2
(2 X cycle,
Sample & hold
bit is disabled)
7.8 3.0
f(X
IN
)
(MHz) Cycle
(µs) Sampling time
(µs) R
(kΩ)C
(pF) Resolution
(LSB) R0max
(kΩ)
10 0.1 0.3
(3 X cycle,
Sample & hold
bit is enabled)
7.8 3.0 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
4.9
7.0
8.2
9.1
9.9
10.5
11.1
11.7
12.1
12.6
0.7
2.1
2.9
3.5
4.0
4.4
4.8
5.2
5.5
5.8
10 0.1 0.2
(2 X cycle,
Sample & hold
bit is disabled)
7.8 3.0
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(3) External interrupt
• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins
_______ _______
INT0 to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the
_______ _______
signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=30MHz and
no division mode, at least 233 ns width is necessary.)
_______ _______
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to
"1". After changing the polarity, set the interrupt request bit to "0". Figure 1.31.2 shows the
______
procedure for changing the INT interrupt generate factor.
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt priority level to level 0
(Disable
INTi
interrupt)
______
Figure 1.31.2. Switching condition of INT interrupt request
(4) Rewrite the interrupt control register
• When a instruction to rewrite the interrupt control register is executed but the interrupt is dis-
abled, the interrupt request bit is not set sometimes even if the interrupt request for that register
has been generated. This will depend on the instructions. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET
DMAC
(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M32C/83, when a DMA request is generated while the channel is disabled (Note), the DMA trans-
fer is not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause
select register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1"
to the DMA request bit, simultaneously. In this case, disable the corresponding DMA channel to
disabled before changing the DMAi request cause select bit. To enable DMA at least 8+6xN cycles
(N: enabled channel number) following the instruction to write to the DMAi request cause select
register are needed.
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Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer
after DMA initial setting
push.w R0 ; Store R0 register
stc DMD0, R0 ; Read DMA mode register 0
and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00"
ldc R0, DMD0 ; DMA0 disabled
mov.b #10000011b, DM0SL ; Select timer A0
; (Write "1" to DMA request bit simultaneously)
nop
:
ldc R0, DMD0 ; DMA0 enabled
pop.wR0 ; Restore R0 register
Noise
(1) A bypass capacitor should be inserted between Vcc-Vss line for reducing noise and latch-up
Connect a bypass capacitor (approx. 0.1µF) between the Vcc and Vss pins using short wiring and
thicker circuit traces.
Precautions for using CLKOUT pin
When using the Clock Output function of P53/CLKOUT pin (f8, f32 or fc output) in single chip mode, use
port P57 as an input only port (port P57 direction register is "0").
Although port P57 may be set as an output port (port P57 direction register is "1"), it will become high
impedance and will not output "H" or "L" levels.
__________
HOLD signal __________
When using the HOLD input while P40 to P47 and P50 to P52 are set as output ports in single-chip mode,
you must first set all pins for P40 to P47 and P50 to P52 as input ports, then shift to microprocessor mode
or memory expansion mode.
Reducing power consumption
(1) When A-D conversion is not performed, select the Vref not connected with the Vref connect bit of A-D
control register 1. When A-D conversion is performed, start the A-D conversion at least 1 µs or longer
after connecting Vref.
(2) When using AN4 (P104) to AN7 (P107), select the input disable of the key input interrupt signal with the
key input interrupt disable bit of the function select register C .
When selecting the input disable of the key input interrupt signal, the key input interrupt cannot be
used. Also, the port cannot be input even if the direction register of P104 to P107 is set to input (the
input result becomes undefined). When the input disable of the key input interrupt signal is selected,
use all AN4 to AN7 as A-D inputs.
(3) When ANEX0 and ANEX1 are used, select the input peripheral function disable with port P95 and P96
input peripheral function select bit of the function select register B3.
When the input peripheral function disable is selected, the port cannot be input even if the port direc-
tion register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function except ANEX0 and ANEX1.
At least 8 + 6 x N cycles
(N: enabled channel number)
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(4) When D-A converter is not used, set output disabled with the D-A output enable bit of D-A control
register and set the D-A register to "0016".
(5) When D-A conversion is used, select the input peripheral function disabled with port P93 and P94 input
peripheral function select bit of the function select register B3.
When the input peripheral function disabled is selected, the port cannot be input even if the port
direction register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function.
DRAM controller
The DRAM self-refresh operates in stop mode, etc.
When shifting to self-refresh, select DRAM is ignored by the DRAM space select bit. In the next instruc-
tion, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also,
insert two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM is ignored by the DRAM space select bit and
self-refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT ;DRAM is ignored, one wait is selected
mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait
nop ;Two nops are needed
nop ;
•••
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT ;Select 4MB and one wait
nop ;Inhibit instruction to access DRAM area
nop
•••
Setting the registers
The registers shown in Table 1.31.3 include indeterminate bit when read. Set immidiate to these regis-
ters.
Store the content of the frequently used register to RAM, change the content of RAM, then transfer to the
register.
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Table 1.31.3 The object registers
Register name Symbol Address
Watchdog timer start register WDTS 000E16
Group0 receive input register G0RI 00EC16
Group1 receive input register G1RI 012C16
Group2 SI/O transmit buffer register G2TB 016D16, 016C16
UART4 bit rate generator U4BRG 02F916
UART4 transfer buffer register U4TB 02FB16, 02FA16
Timer A1-1 register TA11 030316, 030216
Timer A2-1 register TA21 030516, 030416
Timer A4-1 register TA41 030716, 030616
Dead time timer DTT 030C16
Timer B2 interrupt occurrence frequency set counter ICTB2 030D16
UART3 bit rate generator U3BRG 032916
UART3 transfer buffer register U3TB 032B16, 032A16
UART2 bit rate generator U2BRG 033916
UART2 transfer buffer register U2TB 033B16, 033A16
Up-down flag UDF 034416
Timer A0 register (Note) TA0 034716, 034616
Timer A1 register (Note) TA1 034916, 034816
Timer A2 register (Note) TA2 034B16, 034A16
Timer A3 register (Note) TA3 034D16, 034C16
Timer A4 register (Note) TA4 034F16, 034E16
UART0 bit rate generator U0BRG 036916
UART0 transfer buffer register U0TB 036B16, 036A16
UART1 bit rate generator U1BRG 02E916
UART1 transfer buffer register U1TB 02EB16, 02EA16
A-D0 control register 2 ADCON2 039416
Note: In one-shot timer mode and pulse width modulation mode.
Notes on the microprocessor mode and transition after shifting from the micropro-
cessor mode to the memory expansion mode / single-chip mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed.
For that reason, the internal ROM area cannot be accessed.
After the reset has been released and the operation of shifting from the microprocessor mode has started
(“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the
memory expansion mode or single-chip mode.
Notes on CNVss pin reset at "H" level
When the CNVss pin is reset at "H" level, the contents of internal ROM cannot be read out.
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Electrical characteristics
Table 1.32.1. Absolute maximum ratings
Symbol Parameter Condition Rated value Unit
VCC Supply voltage VCC=AVCC -0.3 to 6.0 V
AVCC Analog supply voltage VCC=AVCC -0.3 to 6.0 V
VIInput voltage -0.3 to Vcc+0.3 V
-0.3 to 6.0 V
VOOutput voltage -0.3 to Vcc+0.3 V
-0.3 to 6.0 V
Pd Power dissipation Topr=25°C 500 mW
Topr Operating ambient temperature -20 to 85/-40 to 85(Note 2) °C
Tstg Storage temperature -65 to 150 °C
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: Specify a product of -40 to 85°C to use it.
______________
RESET, CNVss, BYTE, P00-P07, P10-P17,
P20-P27, P30-P37, P40-P47, P50-P57, P60-
P67, P72-P77, P80-P87, P90-P97, P100-P107,
P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note1), VREF, XIN
P70, P71
P00-P07, P10-P17, P20-P27, P30-P37, P40-
P47, P50-P57, P60-P67, P72-P77, P80-P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1),
VREF, XIN
P70, P71
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Table 1.32.2. Recommended operating conditions (referenced to VCC = 3.0V to 5.5V at Topr = – 20
to 85oC / – 40 to 85oC(Note3) unless otherwise specified)
Standard
Symbol Parameter Unit
Min. Typ. Max.
VCC Supply voltage(When VDC-ON) 3.0 5.0 5.5 V
Supply voltage(When VDC-pass through) 3.0 3.3 3.6 V
AVCC Analog supply voltage V CC V
VSS Supply voltage 0V
AVSS Analog supply voltage 0 V
VIH "H" input voltage 0.8Vcc Vcc V
0.8Vcc 6.0 V
0.8Vcc Vcc V
0.5Vcc Vcc V
VIL "L" input voltage 0 0.2Vcc V
0 0.2Vcc V
0 0.16Vcc V
IOH(peak) "H" peak output -10.0 mA
current
IOH(avg) "H" average -5.0 mA
output current
IOL(peak) "L" peak output 10.0 mA
current
IOL(avg) "L" average 5.0 mA
output current
f(XIN) Main clock input frequency VDC-ON Vcc=4.2 to 5.5V 0 30 MHz
Vcc=3.0 to 4.2V 0 20 MHz
VDC-pass through Vcc=3.0 to 3.6V 0 20 MHz
f(XCIN) Sub-clock oscillation frequency 32.768 kHz
P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-
P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-
P127, P130-P137, P140-P146, P150-P157(Note5), XIN,
____________
RESET, CNVss, BYTE
P70, P71
P00-P07, P10-P17
(during single-chip mode)
P00-P07, P10-P17
(during memory-expansion and microprocessor modes)
P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-
P77, P80-P87, P90-P97, P100-P107, P110-P114, P120-
P127, P130-P137, P140-P146, P150-P157(Note5), XIN,
____________
RESET, CNVss, BYTE
P00-P07, P10-P17
(during single-chip mode)
P00-P07, P10-P17
(during memory-expansion and microprocessor modes)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140-
P146, P150-P157(Note5)
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA max. The total
IOH (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA max. The total IOL (peak)
for ports P3, P4, P5, P6, P7,P80 to P84, P12 and P13 must be 80mA max. The total IOH (peak) for ports P3, P4,
P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA max.
Note 3: Specify a product of -40 to 85°C to use it.
Note 4: The specification of VIH and VIL of P87 is not when using as XCIN but when using programmable input port.
Note 5: Port P11 to P15 exist in 144-pin version.
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VCC = 5V
Table 1.32.3. Electrical characteristics (referenced to VCC=5V, VSS=0V at
Topr=25oC, f(XIN)=30MHZ unless otherwise specified) Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
VOH
"H" output voltage
IOH=-5mA 3.0 V
VOH
"H" output voltage
IOH=-200µA 4.7 V
VOH
"H" output voltage
XOUT HIGH POWER IOH=-1mA 3.0 V
LOW POWER I OH=-0.5mA 3.0 V
"H" output voltage
XCOUT No load applied 3.0 V
VOL
"L" output voltage
IOH=5mA 2.0 V
VOL
"L" output voltage
IOH=200µA 0.45 V
VOL
"L" output voltage
XOUT HIGH POWER IOL=1mA 2.0 V
LOW POWER I OL=0.5mA 2.0 V
"L" output voltage
XCOUT No load applied 0 V
VT+-VT- Hysteresis 0.2 1.0 V
V
T+
-V
T-
Hysteresis 0.2 1.8 V
IIH
"H" input current
VI=5V 5.0 µA
IIL "L" input current VI=0V -5.0 µA
RPULLUP
Pull-up resistance
VI=0V 30 50 167 kΩ
RfXIN
Feedback resistance
XIN 1.5 MΩ
RfXCIN
Feedback resistance
XCIN 10 MΩ
VRAM
RAM retention voltage
VDC-ON 2.5 V
ICC Power supply
f(X
IN
)=30MHz, square wave, no division
38 54 mA
current
f(X
CIN
)=32kHz, with WAIT instruction executed
470 µA
when clock is stopped Topr=25oC 0.4 20 µA
Note 1: Port P11 to P15 exist in 144-pin version.
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
__________ _______ ________
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-
________ ________ ________
INT5, ADTRG, CTS0-CTS4, CLK0-CLK4,
_______ ______ ______
TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
___________
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-
P137, P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-
P137, P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
Measuring condition:
In sigle-chip mode, the out-
put pins are open and other
pins are Vss.
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Electrical characteristics (Vcc = 5V)
347
VCC = 5V
Table 1.32.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS =
0V at Topr = 25oC, f(XIN) = 30MHZ unless otherwise specified)
µs
Standard
Min. Typ. Max.
Resolution
Integral nonlinearity error Bits
LSB
VREF
=
VCC
±3
10
Symbol Parameter Measuring condition Unit
RLADDER
tCONV
Ladder resistance
Conversion time(10bit)
Reference voltage
Analog input voltage V
VIA
VREF
V0
2
10
VCC
VREF
40
3.3
Conversion time(8bit) 2.8tCONV
tSAMP Sampling time 0.3
VREF
=
VCC
Offset error
AN
0
to AN
7
AN
EX0
, AN
EX1
External op-amp
connection mode
LSB
LSB
±7
Gain error ±3 LSB
Min. Typ. Max.
tsu
RO
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
mA
IVREF
1.0
1.5
8
3
Symbol Parameter Measuring condition Unit
20104µs
(
Note
)
Standard
µs
µs
±3
Note: Divide the frequency if f(X
IN
) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.
VREF =
VCC = 5V
kΩ
kΩ
INL
DNL Differential nonlinearity error LSB
±1
Table 1.32.5. D-A conversion characteristics (referenced to VCC = VREF = 5V, VSS = AVSS = 0V
at Topr = 25oC, f(XIN) = 30MHZ unless otherwise specified)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the Vref is unconnected at the A-D control register 1, IVREF is sent.
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Timing (Vcc = 5V)
348
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)
Table 1.32.6. External clock input
(Note)
(Note)
(Note)
26
26
0
0
30
025
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H)
t
w(L)
t
f
ParameterSymbol Unit
Standard
5
33
13
13 5
Min.
Data input setup time ns
t
su(DB-BCLK)
t
su(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
ns
RDY input setup time
Data input hold time ns
t
h(RD-DB)
t
h(BCLK -RDY)
ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (RD standard, no wait) ns
t
ac1(RD-DB)
ns
ns
t
ac2(RD-DB)
t
ac3(RD-DB)
Data input access time (RD standard, with wait)
Data input access time
(RD standard, when accessing multiplex bus area)
ns
t
d(BCLK-HLDA )
HLDA output delay time
t
ac1(RD – DB)
=f
(BCLK)
X 2 – 35
10
9
[ns]
t
ac2(RD – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
(Note)Data input access time (AD standard, CS standard, no wait) ns
t
ac1(AD-DB)
(Note) ns
t
ac2(AD-DB)
Data input access time (AD standard, CS standard, with wait)
(Note) ns
t
ac3(AD-DB)
Data input access time
(AD standard, CS standard, when accessing
multiplex bus area)
t
ac1(AD – DB)
=f
(BCLK)
– 35
10
9
[ns]
t
ac2(AD – DB)
= – 35
10 X n
9
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
t
ac3(RD – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
t
ac3(AD – DB)
=f
(BCLK)
X 2 – 35
10 X n
9
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
(Note) ns
t
ac4(CAS-DB)
Data input access time (CAS standard, DRAM access) (Note) ns
t
ac4(RAS-DB)
Data input access time (RAS standard, DRAM access)
(Note) ns
t
ac4(CAD-DB)
Data input access time (CAD standard, DRAM access)
t
ac4(RAS – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
t
ac4(CAS – DB)
= – 35
10 X n
9
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
t
ac4(CAD – DB)
=f
(BCLK)
– 35
10 X l
9
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
f
(BCLK)
f
(BCLK)
X 2
ns
0
t
h(CAS -DB)
Data input hold time
Table 1.32.7. Memory expansion and microprocessor modes
VCC = 5V
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Timing (Vcc = 5V)
349
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)
Table 1.32.8. Timer A input (count input in event counter mode)
Table 1.32.9. Timer A input (gating input in timer mode)
Table 1.32.10. Timer A input (external trigger input in one-shot timer mode)
Table 1.32.11. Timer A input (external trigger input in pulse width modulation mode)
Table 1.32.12. Timer A input (up/down input in event counter mode)
VCC = 5V
Standard
Max.
ns
TAiIN input LOW pulse width
tw(TAL)
Min. ns
ns
Unit
Standard
Max.Min. ns
ns
ns
Unit
Standard
Max.Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
Unit
Standard
Max.Min. ns
ns
ns
Unit
ns
ns
TAiIN input HIGH pulse width
tw(TAH)
ParameterSymbol
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
TAiIN input cycle time
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
tc(TA)
tw(TAH)
tw(TAL)
Symbol Parameter
tw(TAH)
tw(TAL)
Symbol Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Symbol Parameter
tc(TA) TAiIN input cycle time
TAiOUT input cycle time
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
40
100
40
400
200
200
200
100
100
100
100
2000
1000
1000
400
400
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Timing (Vcc = 5V)
350
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified)
Table 1.32.13. Timer B input (count input in event counter mode)
Table 1.28.14. Timer B input (pulse period measurement mode)
Table 1.32.15. Timer B input (pulse width measurement mode)
Table 1.32.16. A-D trigger input
Table 1.32.17. Serial I/O
_______
Table 1.32.18. External interrupt INTi inputs
VCC = 5V
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
ns
ns
ns
tc(TB)
tw(TBH)
tw(TBL)
ParameterSymbol Unit
tc(TB)
tw(TBL)
tw(TBH) ns
ns
ns
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
TBiIN input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
tc(TB)
tw(TBH)
Symbol Parameter Unit
tw(TBL) ns
TBiIN input HIGH pulse width
TBiIN input cycle time
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(TB)
Symbol Parameter Unit
tw(TBL) ns
tw(TBH) TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Standard
Max.
Min. ns
ns
tc(AD)
tw(ADL)
Symbol Parameter Unit
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Standard
Max.
Min. ns
ns
tw(INH)
tw(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
tc(CK)
tw(CKH)
tw(CKL)
ParameterSymbol Unit
td(C-Q)
tsu(D-C)
th(C-Q) TxDi hold time
RxDi input setup time
TxDi output delay time
th(C-D) RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
1000
125
250
250
200
100
100
0
30
90
80
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Timing (Vcc = 5V)
351
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC, CM15 = “1” unless
otherwise specified)
VCC = 5V
Figure 1.32.1
Table 1.32.19. Memory expansion mode and microprocessor mode (no wait)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) -3 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time – 2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time -5 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time -3 ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
td(DB-WR) Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
10 9– 20 [ns]
td(BCLK-CS) Chip select output delay time 18 ns
th(RD-AD) Address output hold time (RD standard) 0 ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
th(WR – DB) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – CS) =f(BCLK) X 2
10 9– 10 [ns]
tw(WR) WR signal width ns
(Note)
tw(WR) =f(BCLK) X 2
10 9– 15
[
ns
]
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Timing (Vcc = 5V)
352
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)
VCC = 5V
Figure 1.32.1
Table 1.32.20. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 18 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) – 3 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) – 3 ns
t
d(BCLK-ALE)
ALE signal output delay time 18 ns
t
h(BCLK-ALE)
ALE signal output hold time – 2 ns
t
d(BCLK-RD)
RD signal output delay time 18 ns
t
h(BCLK-RD)
RD signal output hold time – 5 ns
t
d(BCLK-WR)
WR signal output delay time 18 ns
t
h(BCLK-WR)
WR signal output hold time – 3 ns
t
h(WR-DB)
Data output hold time (WR standard) (Note) ns
t
d(DB-WR)
Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
t
d(BCLK-CS)
Chip select output delay time 18 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
h(WR-AD)
Address output hold time (WR standard) (Note) ns
t
h(RD-CS)
Chip select output hold time (RD standard) 0 ns
t
h(WR-CS)
Chip select output hold time (WR standard) (Note) ns
t
d(DB – WR)
= f
(BCLK)
10 X n
9
– 20
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – CS)
=f
(BCLK)
X 2
10
9
– 10 [ns]
t
w(WR)
WR signal width (Note) ns
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
t
w( WR)
= 10 X n
9
– 15
f
(
BCLK
)
X 2
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Timing (Vcc = 5V)
353
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)
VCC = 5V
Table 1.32.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Figure 1.32.1
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) -3 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard) 18 ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard) – 2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time -5 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time -3 ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
td(DB-WR) Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
td(DB – WR) = 10 X m
9– 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
td(BCLK-CS) Chip select output delay time 18 ns
th(RD-AD) Address output hold time (RD standard) (Note) ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
th(RD-CS) Chip select output hold time (RD standard) ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
th(RD – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(RD – CS) = f(BCLK) X 2
10 9– 10 [ns]
td(AD-ALE) ALE signal output delay time (address standard) ns
th(ALE-AD) ALE signal output hold time (address standard) ns
tdz(RD-AD) Address output flowting start time ns
(Note)
(Note) 8
th(WR – CS) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – DB) = f(BCLK) X 2
10 9– 10 [ns]
td(AD – ALE) = f(BCLK) X 2
10 9– 20 [ns]
th(ALE – AD) = f(BCLK) X 2
10 9– 10 [ns]
f(BCLK) X 2
(Note)
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Timing (Vcc = 5V)
354
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise
specified)
VCC = 5V
Table 1.32.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, DRAM area selected)
Symbol Standard
Measuring
condition Max.Min.
Parameter Unit
td(BCLK-RAD) Row address output delay time 18 ns
th(BCLK-RAD) Row address output hold time (BCLK standard) -3 ns
td(BCLK-RAS) RAS output delay time (BCLK standard) -3 ns
tsu(DB-CAS) CAS output setup time after DB output
18
ns
th(BCLK-DB) DB signal output hold time (BCLK standard) (Note) ns
18
td(BCLK-CAS) CAS output delay time (BCLK standard) -3 ns
th(BCLK-CAS) CAS output hold time (BCLK standard)
(Note)
ns
td(BCLK-DW) DW output delay time (BCLK standard) ns
-7
Note: Calculated according to the BCLK frequency as follows:
tsu(CAS – RAS) = f
(
BCLK
)
X 2
10
9– 13
[
ns
]
th(RAS-RAD) Row address output hold time after RAS output
18
ns
td(BCLK-CAD) String address output delay time -3 ns
th(BCLK-CAD) String address output hold time (BCLK standard) (Note) ns
th(BCLK-RAS) RAS output hold time (BCLK standard) ns
tRP RAS "H" hold time ns
th(RAS – RAD) = f(BCLK) X 2
10 9– 13 [ns]
tRP = f(BCLK) X 2
10
9 X 3 – 20 [ns]
tsu(CAS-RAS) CAS output setup time before RAS output (refresh)
18
ns
(Note)
tsu(DB – CAS) = f(BCLK)
10 9– 20 [ns]
th(BCLK-DW) DW output hold time (BCLK standard) ns
-5
Figure 1.32.1
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Timing (Vcc = 5V)
355
Figure 1.32.1. Port P0 to P15 measurement circuit
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
P14
P13
P12
P15
P11
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Timing (Vcc = 5V)
356
BCLK
ALE
-2ns.min
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
0ns.min
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
su(DB-BCLK)
t
d(BCLK-RD)
26ns.min*1
CSi
t
d(BCLK-CS)
18ns.max*1
ADi
t
h(BCLK-AD)
-3ns.min
t
h(BCLK-CS)
-3ns.min
BHE
tcyc
t
d(BCLK-AD) 0ns.min
t
ac1(AD-DB)*2
t
ac1(RD-DB)
=(tcyc/2-35)ns.max
t
ac1(AD-DB)
=(tcyc-35)ns.max
WR,WRL,
WRH
18ns.max
-3ns.min
BCLK
CSi
t
d(BCLK-CS)
18ns.max
ADi t
d(BCLK-AD)
18ns.max
t
d(BCLK-ALE)
-3ns.min
-3ns.min
tcyc
BHE
DBi
t
d(BCLK-WR)
ALE
18ns.max
-2ns.min
t
h(WR-DB)*3
t
d(DB-WR)
=(tcyc-20)ns.min
t
h(WR-DB)
=(tcyc/2-10)ns.min
t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min
t
w(WR)
=(tcyc/2-15)ns.min
Vcc=5V
t
h(BCLK-RD)
t
h(RD-DB)
t
h(RD-AD)
t
h(RD-CS)
t
h(BCLK-WR)
t
h(BCLK-ALE)
t
h(BCLK-AD)
t
h(BCLK-CS)
t
h(WR-CS)*3
t
h(WR-AD)*3
t
w(WR)*3
t
ac1(RD-DB)*2
18ns.max*1
Read Timing
Write Timing ( Written by 2 cycles in selecting no wait)
*3:It depends on operation frequency. Measuring conditions
• V
CC
=5V±10%
• Input timing voltage :Determined with V
IH
=2.5V, V
IL
=0.8V
• Output timing voltage :Determined with V
OH
=2.0V, V
OL
=0.8V
Memory Expansion Mode and Microprocessor Mode (without wait)
*1:It is a guarantee value with being alone. 35ns.max garantees as t
d(BCLK-AD)
+t
su(DB-BCLK)
.
*2:It depends on operation frequency.
18ns.max
t
d(DB-WR)*3
Figure 1.32.2. VCC=5V timing diagram (1)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
357
BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-5ns.min
Hi-Z
DB
0ns.min
0ns.min
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(BCLK-RD)
26ns.min*1
t
ac2(RD-DB)*2
CSi
t
d(BCLK-CS)
18ns.max*1
ADi
18ns.max*1
t
h(BCLK-AD)
-3ns.min
t
h(BCLK-CS)
-3ns.min
BHE
tcyc
t
d(BCLK-AD)
t
ac2(AD-DB)*2
t
ac2(RD-DB)
=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
t
ac2(AD-DB)
=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
WR,WRL,
WRH
18ns.max
-3ns.min
BCLK
CSi
18ns.max
ADi
18ns.max -3ns.min
-3ns.min
tcyc
BHE
DBi
t
d(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=5V
t
h(BCLK-RD)
t
h(RD-DB)
t
su(DB-BCLK)
t
h(RD-CS)
0ns.min
t
d(BCLK-CS)
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-AD)
t
h(BCLK-CS)
t
h(WR-CS)*3
t
d(DB-WR)*3
t
h(WR-DB)*3
t
h(WR-AD)*3
t
d(DB-WR)
=(tcyc x n-20)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
t
h(WR-DB)
=(tcyc/2-10)ns.min
t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min
t
w(WR)
=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
*3:It depends on operation frequency. Measuring conditions
• V
CC
=5V±10%
• Input timing voltage
:Determined with V
IH
=2.5V, V
IL
=0.8V
• Output timing voltage
:Determined with V
OH
=2.0V, V
OL
=0.8V
*1:It is a guarantee value with being alone. 35ns.max garantees as t
d(BCLK-AD)
+t
su(DB-BCLK)
.
*2:It depends on operation frequency.
t
h(BCLK-ALE)
Read Timing
Write Timing ( Written by 2 cycles in selecting no wait)
Memory Expansion Mode and Microprocessor Mode (with wait)
t
h(RD-AD)
t
w(WR)*3
t
h(BCLK-WR)
Figure 1.32.3. VCC=5V timing diagram (2)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
358
BCLK
CSi
18ns.max
ADi
18ns.max
RD
18ns.max -5ns.min
t
h(BCLK-AD)
-3ns.min
-3ns.min
BHE
ADi
/DBi
0ns.min
18ns.max -3ns.min
BCLK
CSi
18ns.max
ADi
18ns.max -3ns.min
-3ns.min
tcyc
BHE
ADi
/DBi Data output
WR,WRL,
WRH
Address
AddressData input
26ns.min
t
d(BCLK-RD)
t
h(WR-CS)*2
Address
t
d(AD-ALE)*2
Address
t
su(DB-BCLK)
t
ac3(RD-DB)*1
t
dz(RD-AD)
8ns.max
ALE
-2ns.min
t
d(BCLK-ALE)
18ns.max
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
ALE
18ns.max
-2ns.min
t
d(BCLK-ALE)
t
h(ALE-AD)*2
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(m=3 and 5 when 2 wait and 3 wait, respectively.)
Vcc=5V
t
d(BCLK-CS)
t
d(AD-ALE)*1
t
h(ALE-AD)*1
t
h(BCLK-RD)
t
h(RD-AD)*1
t
h(RD-DB)
t
d(BCLK-AD)
t
h(BCLK-CS)
t
h(RD-CS)*1
t
d(BCLK-WR)
t
h(BCLK-WR)
t
d(BCLK-CS)
t
d(BCLK-AD)
t
h(BCLK-AD)
t
h(BCLK-CS)
t
h(WR-AD)*2
t
d(DB-WR)*2
t
h(WR-DB)*2
t
h(BCLK-ALE)
t
h(BCLK-ALE)
tcyc
*2:It depends on operation frequency. Measuring conditions
• V
CC
=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH
=
2.0V, VOL
=
0.8V
*1:It depends on operation frequency.
Read Timing
Write Timing (Written by 2 cycles in selecting no wait)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
)
t
ac3(AD-DB)*1
Figure 1.32.4. VCC=5V timing diagram (3)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
359
Figure 1.32.5. VCC=5V timing diagram (4)
BCLK
DW
DB
MAi
t
d(BCLK-RAS)
+ t
su(DB-BCLK)
t
d(BCLK-CAS)
+ t
su(DB-BCLK)
t
d(BCLK-CAD)
+ t
su(DB-BCLK)
t
ac4(RAS-DB)
=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
t
ac4(CAS-DB)
=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
t
ac4(CAD-DB)
=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
t
h(RAS-RAD)
=(tcyc/2-13)ns.min
t
RP
=(tcyc/2 x 3-20)ns.min
Vcc=5V
RAS
CASL
CASH
Hi-Z
tac4(CAS-DB)*2
18ns.max th(BCLK-CAD)
-3ns.min
tcyc
td(BCLK-RAD)
tac4(RAS-DB)*2
Row address String address
th(BCLK-RAD)
-3ns.min 18ns.max*1
td(BCLK-CAD)
18ns.max*1
td(BCLK-RAS) 18ns.max*1
td(BCLK-CAS)
th(RAS-RAD)*2 tRP*2
tac4(CAD-DB)*2
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
0ns.min
tsu(DB-BCLK)
26ns.min*1 th(CAS-DB)
*2:It depends on operation frequency.
Measuring conditions
• V
CC
=5V±10%
• Input timing voltage
:Determined with V
IH
=2.5V, V
IL
=0.8V
• Output timing voltage
:Determined with V
OH
=2.0V, V
OL
=0.8V
Read Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing DRAM area)
*1:It is a guarantee value with being alone. 35ns.max garantees as follows:
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
360
BCLK
DW
DB
MAi
t
h(RAS-RAD)
=(tcyc/2-13)ns.min
t
RP
=(tcyc/2 x 3-20)ns.min
t
su(DB-CAS)
=(tcyc-20)ns.min
Vcc=5V
RAS
CASL
CASH
Hi-Z
t
h(BCLK-DB)
-7ns.min
18ns.max
t
h(BCLK-CAD)
-3ns.min
tcyc
t
d(BCLK-RAD)
t
h(BCLK-RAD)
-3ns.min 18ns.max
t
d(BCLK-CAD)
18ns.max
t
d(BCLK-RAS)
18ns.max
t
d(BCLK-CAS)
t
h(RAS-RAD)*1
t
RP*1
18ns.max
t
d(BCLK-DW)
t
su(DB-CAS)*1
t
h(BCLK-RAS)
-3ns.min
t
h(BCLK-CAS)
-3ns.min
t
h(BCLK-DW)
-5ns.min
Row address String address
*1:It depends on operation frequency.
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with V
IH
=2.5V, V
IL
=0.8V
• Output timing voltage
:Determined with V
OH
=2.0V, V
OL
=0.8V
Write Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing DRAM area)
Figure 1.32.6. VCC=5V timing diagram (5)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
361
tcyc
18ns.max
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
tsu(CAS-RAS)*1
18ns.max
tcyc
td(BCLK-CAS)
tsu(CAS-RAS)*1 th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
18ns.max
td(BCLK-RAS)
BCLK
DW
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Vcc=5V
RAS
CASL
CASH
BCLK
DW
tsu(CAS-RAS)=(tcyc/2-13)ns.min
RAS
CASL
CASH
*1:It depends on operation frequency.
Measuring conditions
• V
CC
=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Refresh Timing (CAS before RAS refresh)
Memory expansion Mode and Microprocessor Mode
*1:It depends on operation frequency.
Refresh Timing (Self-refresh)
Figure 1.32.7. VCC=5V timing diagram (6)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
362
Figure 1.32.8. VCC=5V timing diagram (7)
tsu(D–C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLKi
TxDi
RxDi
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C–Q) th(C–D)
th(C–Q)
th(T
IN–UP)
tsu(UP–T
IN)
TAi
IN
input
(When count on falling
edge is selected)
TAi
IN
input
(When count on rising
edge is selected)
TAi
OUT
input
(Up/down input)
INTi input
AD
TRG
input
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
363
Figure 1.32.9. VCC=5V timing diagram (8)
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
Measuring conditions :
• V
CC
=
5V±10%
• Input timing voltage : Determined with V
IH
=4.0V, V
IL
=1.0V
• Output timing voltage : Determined with V
OH
=2.5V, V
OL
=2.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
0
to P5
2
(Valid with or without wait)
(Valid only with wait)
RDY input
t
su(RDY–BCLK)
t
h(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Regardless of the level of the BYTE pin input and the setting of the port P4
0
to
P4
3
function select bit (PM06) of the processor mode register 0, all ports above
become the high-impedance state.
Note:
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
364
VCC = 3V
Electrical characteristics (Vcc = 3V)
Table 1.32.23. Electrical characteristics (referenced to VCC=3.3V, VSS=0V at
Topr=25oC, f(XIN)=20MHZ unless otherwise specified) Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
VOH
"H" output voltage
IOH=-1mA 2.7 V
VOH
"H" output voltage
XOUT HIGH POWER IOH=-0.1mA 2.7 V
LOW POWER IOH=-50µA 2.7 V
"H" output voltage
XCOUT No load applied 3.0 V
VOL
"L" output voltage
IOL=1mA 0.5
VOL
"L" output voltage
XOUT HIGH POWER IOL=0.1mA 0.5 V
LOW POWER IOL=50µA 0.5 V
"L" output voltage
XCOUT No load applied 0 V
VT+-VT- Hysteresis 0.2 1.0 V
VT+-VT- Hysteresis 0.2 1.8 V
IIH "H" input current VI=3V 4.0 µA
IIL "L" input current VI=0V -4.0 µA
RPULLUP
Pull-up resistance
VI=0V 66 120 500 kΩ
RfXIN
Feedback resistance
XIN 3.0 MΩ
RfXCIN
Feedback resistance
XCIN 20.0 MΩ
VRAM
RAM retention voltage
VDC-ON 2.5 V
VDC-pass through 2.0 V
ICC Power supply f(XIN)=20MHz, square wave, no division 26 38 mA
current
f(X
CIN
)=32kHz, with WAIT, VDC-pass through
5.0 µA
f(X
CIN
)=32kHz, with WAIT, VDC-ON
340 µA
when clock is stopped Topr=25oC 0.4 20 µA
Note 1: Port P11 to P15 exist in 144-pin version.
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P70-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
__________ _______ ________
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-
________ ________ ________
INT5, ADTRG, CTS0-CTS4, CLK0-CLK4,
_______ ______ ______
TA0OUT-TA4OUT, NMI, KI0-KI3, RxD0-RxD4,
SCL0-SCL4, SDA0-SDA4
___________
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(Note1),
___________
XIN, RESET, CNVss, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P60-P67, P72-P77, P80-P84, P86, P87,
P90-P97, P100-P107, P110Å`P114, P120-P127,
P130-P137, P140-P146, P150-P157(Note1)
Measuring condition:
In sigle-chip mode,
the output pins are
open and other pins
are Vss.
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
365
Table 1.32.24.
A-D conversion characteristics (referenced to V
CC
= AV
CC
= V
REF
= 3V, V
SS
= AV
SS
=
0V
at Topr = 25oC, f(XIN) = 20MHZ unless otherwise specified)
VCC = 3V
Table 1.32.25. D-A conversion characteristics (referenced to VCC = VREF = 3V, VSS = AVSS = 0V,
at Topr = 25oC, f(XIN) = 20MHZ unless otherwise specified)
Note :This applies when using one D-A converter, with the D-A register for the unused D-A converter
set to “0016”. The A-D converter's ladder resistance is not included.
Also, the Vref is unconnected at the A-D control register 1, IVREF is sent.
Standard
Min. Typ. Max
t
su
R
O
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Bits
%
mAI
VREF
1.0
1.0
8
3
Symbol Parameter Measuring condition Unit
20104
(Note)
Standard
Min. Typ. Max
Resolution
Bits
LSB
V
REF
= V
CC
±2
10
Symbol Parameter Measuring condition Unit
No S&H function(8-bit)
µs
R
LADDER Ladder resistance
Reference voltage
Analog input voltage
V
V
IA
V
REF
V0
2.7
10
V
CC
V
REF
40
Conversion time
(8bit) 9.8t
CONV
V
REF
= V
CC
µs
kΩ
kΩ
LSB±1 LSB
±2 LSB
±2
Integral nonlinearity error
Differential nonlinearity error
No S&H function(8-bit)
No S&H function(8-bit)
No S&H function(8-bit)
Offset error
Gain error
ISL
DSL
S&H: Sample and hold
Note: Divide the frequency if f(XIN) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
366
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)
(Note)
(Note)
(Note)
30
40
0
0
60
025
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H)
t
w(L)
t
f
ParameterSymbol Unit
Standard
5
50
22
22 5
Min.
Data input setup time ns
t
su(DB-BCLK)
t
su(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
ns
RDY input setup time
Data input hold time ns
t
h(RD-DB)
t
h(BCLK -RDY)
ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (RD standard, no wait) ns
t
ac1(RD-DB)
ns
ns
t
ac2(RD-DB)
t
ac3(RD-DB)
Data input access time (RD standard, with wait)
Data input access time
(RD standard, when accessing multiplex bus area)
nst
d(BCLK-HLDA )
HLDA output delay time
t
ac1(RD – DB)
=f
(BCLK)
X 2 – 35
10
9
[ns]
t
ac2(RD – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
(Note)Data input access time (AD standard, CS standard, no wait) ns
t
ac1(AD-DB)
(Note) ns
t
ac2(AD-DB)
Data input access time (AD standard, CS standard, with wait)
(Note) ns
t
ac3(AD-DB)
Data input access time
(AD standard, CS standard, when accessing
multiplex bus area)
t
ac1(AD – DB)
=f
(BCLK)
– 35
10
9
[ns]
t
ac2(AD – DB)
= – 35
10 X n
9
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
t
ac3(RD – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
t
ac3(AD – DB)
=f
(BCLK)
X 2 – 35
10 X n
9
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
(Note) ns
t
ac4(CAS-DB)
Data input access time (CAS standard, DRAM access) (Note) ns
t
ac4(RAS-DB)
Data input access time (RAS standard, DRAM access)
(Note) ns
t
ac4(CAD-DB)
Data input access time (CAD standard, DRAM access)
t
ac4(RAS – DB)
=f
(BCLK)
X 2 – 35
10 X m
9
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
t
ac4(CAS – DB)
= – 35
10 X n
9
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
t
ac4(CAD – DB)
=f
(BCLK)
– 35
10 X l
9
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
f
(BCLK)
f
(BCLK)
X 2
0
Data input hold time ns
t
h(CAS-DB)
VCC = 3V
Table 1.32.26. External clock input
Table 1.32.27. Memory expansion and microprocessor modes
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
367
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)
Standard
Max.Min. UnitParameterSymbol
nst
w(TAL)
TAi
IN
input LOW pulse width 40
nst
c(TA)
TAi
IN
input cycle time 100 nst
w(TAH)
TAi
IN
input HIGH pulse width 40
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 400 nst
w(TAH)
TAi
IN
input HIGH pulse width 200 nst
w(TAL)
TAi
IN
input LOW pulse width 200
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 200 nst
w(TAH)
TAi
IN
input HIGH pulse width 100 nst
w(TAL)
TAi
IN
input LOW pulse width 100
Standard
Max.Min. UnitParameterSymbol
nst
w(TAH)
TAi
IN
input HIGH pulse width 100 nst
w(TAL)
TAi
IN
input LOW pulse width 100
Standard
Max.Min. UnitParameterSymbol
nst
c(UP)
TAi
OUT
input cycle time 2000 nst
w(UPH)
TAi
OUT
input HIGH pulse width 1000 nst
w(UPL)
TAi
OUT
input LOW pulse width 1000 nst
su(UP-T
IN
)
TAi
OUT
input setup time 400 nst
h(T
IN-
UP)
TAi
OUT
input hold time 400
Table 1.32.29. Timer A input (gating input in timer mode)
Table 1.32.30. Timer A input (external trigger input in one-shot timer mode)
Table 1.32.31. Timer A input (external trigger input in pulse width modulation mode)
Table 1.32.32. Timer A input (up/down input in event counter mode)
Table 1.32.28. Timer A input (counter input in event counter mode)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
368
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified)
VCC = 3V
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time (counted on one edge) 100 nst
w(TBH)
TBi
IN
input HIGH pulse width (counted on one edge) 40 nst
w(TBL)
TBi
IN
input LOW pulse width (counted on one edge) 40
t
w(TBH)
nsTBi
IN
input HIGH pulse width (counted on both edges) 80
t
w(TBL)
nsTBi
IN
input LOW pulse width (counted on both edges) 80
t
c(TB)
nsTBi
IN
input cycle time (counted on both edges) 200
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 400 nst
w(TBH)
TBi
IN
input HIGH pulse width 200
t
w(TBL)
nsTBi
IN
input LOW pulse width 200
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 400 nst
w(TBH)
TBi
IN
input HIGH pulse width 200
t
w(TBL)
nsTBi
IN
input LOW pulse width 200
Standard
Max.Min.
ParameterSymbol Unit
nst
c(AD)
AD
TRG
input cycle time (trigger able minimum) 1000 nst
w(ADL)
AD
TRG
input LOW pulse width 125
Standard
Max.Min.
ParameterSymbol Unit
nst
w(INH)
INTi input HIGH pulse width 250 nst
w(INL)
INTi input LOW pulse width 250
Standard
Max.Min.
ParameterSymbol Unit
nst
c(CK)
CLKi input cycle time 200 nst
w(CKH)
CLKi input HIGH pulse width 100 nst
w(CKL)
CLKi input LOW pulse width 100
t
h(C-Q)
nsTxDi hold time 0
t
su(D-C)
nsRxDi input setup time 30
t
h(C-D)
nsRxDi input hold time 90
t
d(C-Q)
nsTxDi output delay time 80
Table 1.32.33. Timer B input (counter input in event counter mode)
Table 1.32.34. Timer B input (pulse period measurement mode)
Table 1.32.35. Timer B input (pulse width measurement mode)
Table 1.32.36. A-D trigger input
Table 1.32.37. Serial I/O
_______
Table 1.32.38. External interrupt INTi inputs
Under
development
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
369
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) 0ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 0ns
td(BCLK-ALE) ALE signal output delay time 18 ns
th(BCLK-ALE) ALE signal output hold time – 2 ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time – 3 ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time 0 ns
(Note) ns
td(DB-WR) Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
10 9– 20 [ns]
td(BCLK-CS) Chip select output delay time 18 ns
th(RD-AD) Address output hold time (RD standard) 0ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
th(RD-CS) Chip select output hold time (RD standard) 0 ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
th(WR – DB) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – CS) =f(BCLK) X 2
10 9– 10 [ns]
tw(WR) Write pulse width
tw(WR) =f
(BCLK) X2
10 9– 15
[ns]
th(WR-DB) Data output hold time (WR standard) ns
(Note)
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC, CM15="1" unless
otherwise specified)
VCC = 3V
Figure 1.32.1
Table 1.32.39. Memory expansion and microprocessor modes (with no wait)
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
370
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)
VCC = 3V
Figure 1.32.1
Table 1.32.40. Memory expansion and microprocessor modes
(with wait, accessing external memory)
Symbol Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 18 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 0ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 0ns
t
d(BCLK-ALE)
ALE signal output delay time 18 ns
t
h(BCLK-ALE)
ALE signal output hold time – 2 ns
t
d(BCLK-RD)
RD signal output delay time 18 ns
t
h(BCLK-RD)
RD signal output hold time – 3 ns
t
d(BCLK-WR)
WR signal output delay time 18 ns
t
h(BCLK-WR)
WR signal output hold time 0ns
t
h(WR-DB)
Data output hold time (WR standard) (Note) ns
t
d(DB-WR)
Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
t
d(BCLK-CS)
Chip select output delay time 18 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
h(WR-AD)
Address output hold time (WR standard) (Note) ns
t
h(RD-CS)
Chip select output hold time (RD standard) 0 ns
t
h(WR-CS)
Chip select output hold time (WR standard) (Note) ns
t
d(DB – WR)
= f
(BCLK)
10 X n
9
– 20
t
h(WR – DB)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – AD)
= f
(BCLK)
X 2
10
9
– 10 [ns]
t
h(WR – CS)
=f
(BCLK)
X 2
10
9
– 10 [ns]
t
w(WR)
Write pulse width
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
t
w( WR)
= 10 X n
9
– 15
(Note) ns
f
(
BCLK
)
X 2
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
371
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)
Table 1.32.41. Memory expansion and microprocessor modes
(with wait, accessing external memory, multiplex bus area selected)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 18 ns
th(BCLK-AD) Address output hold time (BCLK standard) 0 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard) 18 ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard) – 2ns
td(BCLK-RD) RD signal output delay time 18 ns
th(BCLK-RD) RD signal output hold time ns
td(BCLK-WR) WR signal output delay time 18 ns
th(BCLK-WR) WR signal output hold time 0 ns
th(WR-DB) Data output hold time (WR standard) (Note) ns
td(DB-WR) Data output delay time (WR standard) ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
td(DB – WR) = 10 X m
9– 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
td(BCLK-CS) Chip select output delay time 18 ns
th(RD-AD) Address output hold time (RD standard) (Note) ns
th(WR-AD) Address output hold time (WR standard) (Note) ns
th(RD-CS) Chip select output hold time (RD standard) ns
th(WR-CS) Chip select output hold time (WR standard) (Note) ns
th(RD – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – AD) = f(BCLK) X 2
10 9– 10 [ns]
th(RD – CS) = f(BCLK) X 2
10 9–10 [ns]
td(AD-ALE) ALE signal output delay time (address standard) ns
th(ALE-AD) ALE signal output hold time (address standard) ns
tdz(RD-AD) Address output flowting start time ns
(Note)
(Note) 8
th(WR – CS) = f(BCLK) X 2
10 9– 10 [ns]
th(WR – DB) = f(BCLK) X 2
10 9– 10 [ns]
td(AD – ALE) = f(BCLK) X 2
10 9– 20 [ns]
th(ALE – AD) = f(BCLK) X 2
10 9– 10 [ns]
f(BCLK) X 2
(Note)
– 3
Figure 1.32.1
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
372
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise
specified)
Table 1.32.42. Memory expansion and microprocessor modes
(with wait, accessing external memory, DRAM area selected)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-RAD) Row address output delay time 18 ns
th(BCLK-RAD) Row address output hold time (BCLK standard) 0ns
td(BCLK-RAS) RAS output delay time (BCLK standard) 0ns
tsu(DB-CAS) CAS after DB output setup time
18
ns
th(BCLK-DB) DB signal output hold time (BCLK standard) (Note) ns
18
td(BCLK-CAS) CAS output delay time (BCLK standard)
– 3
ns
th(BCLK-CAS) CAS output hold time (BCLK standard)
(Note)
ns
td(BCLK-DW) Data output delay time (BCLK standard) ns
– 7
Note: Calculated according to the BCLK frequency as follows:
tsu(CAS – RAS) = f
(
BCLK
)
X 2
10
9– 13
[
ns
]
th(RAS-RAD) Row address output hold time after RAS output
18
ns
td(BCLK-CAD) String address output delay time 0ns
th(BCLK-CAD) String address output hold time (BCLK standard) (Note) ns
th(BCLK-RAS) RAS output hold time (BCLK standard) ns
tRP RAS "H" hold time ns
th(RAS – RAD) = f(BCLK) X 2
10 9– 13 [ns]
tRP = f(BCLK) X 2
10 X 3
9 – 20 [ns]
tsu(CAS-RAS) CAS output setup time before RAS output (refresh)
18
ns
(Note)
tsu(DB – CAS) = f(BCLK)
10 9– 20 [ns]
th(BCLK-DW) Data output hold time (BCLK standard) ns
0
Figure 1.32.1
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
373
Figure 1.32.10. VCC=3V timing diagram (1)
BCLK
ALE
-2ns.min
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
0ns.min
td(BCLK-ALE) th(BCLK-ALE)
tsu(DB-BCLK)
td(BCLK-RD)
30ns.min*1
CSi
td(BCLK-CS)
18ns.max*1
ADi
th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD) 0ns.min
tac2(AD-DB)*2
t
ac2(RD-DB)
=(tcyc/2-35)ns.max
t
ac2(AD-DB)
=(tcyc-35)ns.max
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
td(BCLK-CS)
18ns.max
ADi
td(BCLK-AD)
18ns.max
td(BCLK-ALE)
0ns.min
0ns.min
tcyc
BHE
td(DB-WR)*3
DBi
td(BCLK-WR)
ALE
-2ns.min
th(WR-DB)*3
t
d(DB-WR)
=(tcyc-20)ns.min
t
h(WR-DB)
=(tcyc/2-10)ns.min
t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min
t
w(WR)
=(tcyc/2-15)ns.min
Vcc=3V
t
h(BCLK-RD)
th(RD-DB)
th(RD-AD)
th(RD-CS)
th(BCLK-WR)
th(BCLK-ALE)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)*3
th(WR-AD)*3
tac2(RD-DB)*2
18ns.max*1
Read Timing
Write Timing
*3:It depends on operation frequency. Measuring conditions
• VCC=3V±10%
• Input timing voltage :Determined with V
IH
=1.5V, V
IL
=0.5V
• Output timing voltage :Determined with V
OH
=1.5V, V
OL
=1.5V
Memory expansion Mode and Microprocessor Mode (without wait)
*1:It is a guarantee value with being alone. 35ns.max garantees as t
d(BCLK-AD)
+t
su(DB-BCLK)
.
*2:It depends on operation frequency.
18ns.max
tw(WR)*3
18ns.max
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
374
Figure 1.32.11. VCC=3V timing diagram (2)
BCLK
ALE
18ns.max
-2ns.min
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
0ns.min
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(BCLK-RD)
30ns.min*1
t
ac2(RD-DB)*2
CSi
t
d(BCLK-CS)
18ns.max*1
ADi
18ns.max*1
t
h(BCLK-AD)
0ns.min
t
h(BCLK-CS)
0ns.min
BHE
tcyc
t
d(BCLK-AD)
t
ac2(AD-DB)*2
t
ac2(RD-DB)
=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
t
ac2(AD-DB)
=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max 0ns.min
0ns.min
tcyc
BHE
DBi
t
d(BCLK-WR)
ALE
18ns.max
-2ns.min
Vcc=3V
t
h(BCLK-RD)
t
h(RD-DB)
t
h(RD-AD)
t
su(DB-BCLK)
t
h(RD-CS)
0ns.min
t
h(BCLK-WR)
t
d(BCLK-CS)
t
d(BCLK-AD)
t
d(BCLK-ALE)
t
h(BCLK-AD)
t
h(BCLK-CS)
t
h(WR-CS)*3
t
d(DB-WR)*3
t
h(WR-DB)*3
t
h(WR-AD)*3
t
d(DB-WR)
=(tcyc x n-20)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
t
h(WR-DB)
=(tcyc/2-10)ns.min
t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min
t
w(WR)
=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
*3:It depends on operation frequency. Measuring conditions
• V
CC
=3V±10%
• Input timing voltage
:Determined with V
IH
=1.5V, V
IL
=0.5V
• Output timing voltage
:Determined with V
OH
=1.5V, V
OL
=1.5V
*1:It is a guarantee value with being alone. 35ns.max garantees as t
d(BCLK-AD)
+t
su(DB-BCLK)
.
*2:It depends on operation frequency.
t
h(BCLK-ALE)
Read Timing
Write Timing
Memory expansion Mode and Microprocessor Mode (with wait)
t
w(WR)*3
Under
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Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
375
Figure 1.32.12. VCC=3V timing diagram (3)
BCLK
CSi
18ns.max
ADi
18ns.max
RD
18ns.max -3ns.min
th(BCLK-AD)
0ns.min
0ns.min
BHE
ADi
/DBi
0ns.min
18ns.max 0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max 0ns.min
0ns.min
tcyc
BHE
ADi
/DBi Data output
WR,WRL,
WRH
Address
Address
Data input
30ns.min
td(BCLK-RD)
th(WR-CS)*2
Address
td(AD-ALE)*2
Address
tsu(DB-BCLK)
tac3(RD-DB)*1
tdz(RD-AD)
8ns.max
ALE
-2ns.min
td(BCLK-ALE)
18ns.max
t
d(AD-ALE)
=(tcyc/2-20)ns.min
t
h(ALE-AD)
=(tcyc/2-10)ns.min, t
h(RD-AD)
=(tcyc/2-10)ns.min, t
h(RD-CS)
=(tcyc/2-10)ns.min
t
ac3(RD-DB)
=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
t
ac3(AD-DB)
=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
ALE
-2ns.min
td(BCLK-ALE)
th(ALE-AD)*2
t
d(AD-ALE)
=(tcyc/2-20)ns.min
t
h(ALE-AD)
=(tcyc/2-10)ns.min, t
h(WR-AD)
=(tcyc/2-10)ns.min
t
h(WR-CS)
=(tcyc/2-10)ns.min, t
h(WR-DB)
=(tcyc/2-10)ns.min
t
d(DB-WR)
=(tcyc/2 x m-25)ns.min
(m=3 and 5 when 2 wait and 3 wait, respectively.)
Vcc=3V
td(BCLK-CS)
td(AD-ALE)*1 th(ALE-AD)*1
th(BCLK-RD) th(RD-AD)*1
th(RD-DB)
td(BCLK-AD)
th(BCLK-CS)
th(RD-CS)*1
td(BCLK-WR) th(BCLK-WR)
td(BCLK-CS)
td(BCLK-AD) th(BCLK-AD)
th(BCLK-CS)
th(WR-AD)*2
td(DB-WR)*2 th(WR-DB)*2
th(BCLK-ALE)
th(BCLK-ALE)
tcyc
*2:It depends on operation frequency. Measuring conditions
• V
CC
=3V±10%
• Input timing voltage
:Determined with V
IH
=1.5V, V
IL
=0.5V
• Output timing voltage
:Determined with V
OH
=1.5V, V
OL
=1.5V
*1:It depends on operation frequency.
Read Timing
Write Timing
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
18ns.max
tac3(AD-DB)*1
Under
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Rev.B2 for proof reading Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
376
Figure 1.32.13. VCC=3V timing diagram (4)
BCLK
DW
DB
MAi
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Vcc=3V
RAS
CASL
CASH
Hi-Z
tac4(CAS-DB)*2
18ns.max*1 th(BCLK-CAD)
0ns.min
tcyc
td(BCLK-RAD)
tac4(RAS-DB)*2
Row address String address
th(BCLK-RAD)
0ns.min 18ns.max*1
td(BCLK-CAD)
18ns.max*1
td(BCLK-RAS) 18ns.max*1
td(BCLK-CAS)
th(RAS-RAD)*2 tRP*2
tac4(CAD-DB)*2
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
0ns.min
tsu(DB-BCLK)
30ns.min*1 th(CAS-DB)
*2:It depends on operation frequency.
Measuring conditions
• V
CC
=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Read Timing
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
*1:It is a guarantee value with being alone. 35ns.max garantees as follows:
Under
development
Rev.B2 for proof reading Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
377
Figure 1.32.14. VCC=3V timing diagram (5)
BCLK
DW
DB
MAi
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min
Vcc=3V
RAS
CASL
CASH
Hi-Z
th(BCLK-DB)
-7ns.min
18ns.max th(BCLK-CAD)
0ns.min
tcyc
td(BCLK-RAD) th(BCLK-RAD)
0ns.min 18ns.max
td(BCLK-CAD)
18ns.max
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
tRP*1
18ns.max
td(BCLK-DW)
tsu(DB-CAS)*1
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
-3ns.min
th(BCLK-DW)
0ns.min
Row address String address
*1:It depends on operation frequency.
Measuring conditions
• V
CC
=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Write Timing
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
th(RAS-RAD)*1
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
378
Figure 1.32.15. VCC=3V timing diagram (6)
tcyc
18ns.max
t
d(BCLK-RAS)
18ns.max
t
d(BCLK-CAS)
t
h(BCLK-RAS)
0ns.min
t
h(BCLK-CAS)
0ns.min
t
su(CAS-RAS)*1
18ns.max
t
cyc
t
d(BCLK-CAS)
t
su(CAS-RAS)*1
t
h(BCLK-RAS)
0ns.min
t
h(BCLK-CAS)
0ns.min
18ns.max
t
d(BCLK-RAS)
BCLK
DW
t
su(CAS-RAS)
=(tcyc/2-13)ns.min
Vcc=3V
RAS
CASL
CASH
BCLK
DW
t
su(CAS-RAS)
=(tcyc/2-13)ns.min
RAS
CASL
CASH
*1:It depends on operation frequency.
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with V
IH
=1.5V, V
IL
=0.5V
• Output timing voltage
:Determined with V
OH
=1.5V, V
OL
=1.5V
Refresh Timing (CAS before RAS refresh)
Memory expansion Mode and Microprocessor Mode
*1:It depends on operation frequency.
Refresh Timing (Self-refresh)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
379
Figure 1.32.16. VCC=3V timing diagram (7)
tsu(D–C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLKi
TxDi
RxDi
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C–Q) th(C–D)
th(C–Q)
th(TIN–UP) tsu(UP–TIN)
TAi
IN
input
(When count on falling
edge is selected)
TAi
IN
input
(When count on rising
edge is selected)
TAi
OUT
input
(Up/down input)
INTi input
AD
TRG
input
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
380
Figure 1.32.17. VCC=3V timing diagram (8)
Measuring conditions :
• VCC=3V±10%
• Input timing voltage : Determined with VIH=2.4V, VIL=0.6V
• Output timing voltage : Determined with VOH=1.5V, VOL=1.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P50 to P52
(Valid with or without wait)
(Valid only with wait)
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Hi–Z
th(BCLK–HOLD)
tsu(HOLD–BCLK)
td(BCLK–HLDA)
td(BCLK–HLDA)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
381
Item
Power supply voltage
Program/erase voltage
Flash memory operation mode
Erase block
division
Program method
Erase method
Program/erase control method
Protect method
Number of commands
Program/erase count
ROM code protect
Performance
f(X
IN
)=30MHz, without wait, 4.2V to 5.5V
f(X
IN
)=20MHz, without wait, 3.0V to 3.6V
4.2V to 5.5 V : f(
BCLK
)=12.5MHz, with one wait
: f(
BCLK
)=6.25MHz, without wait
Three modes (parallel I/O, standard serial I/O, CPU rewrite)
See Figure 1.33.3
One division (8 Kbytes)
In units of pages (in units of 256 bytes)
Collective erase/block erase
Program/erase control by software command
Protected for each block by lock bit
8 commands
100 times
Parallel I/O and standard serial modes are supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in
it when shipped from the factory. This area can be erased and programmed in only parallel
I/O mode.
User ROM area
Boot ROM area
Data holding 10 years
(Note 1)
Outline Performance
Table 1.33.1 shows the outline performance of the M32C/83 (flash memory version).
Table 1.33.1. Outline Performance of the M32C/83 (flash memory version)
The following shows Mitsubishi plans to develop a line of M32C/83 products (flash memory version).
(1) ROM capacity
(2) Package 100P6S-A ... Plastic molded QFP
100P6Q-A ... Plastic molded QFP
144P6Q-A ... Plastic molded QFP
Figure 1.33.1. ROM Expansion
ROM size
(Bytes)
Flash memory version
External
ROM
256K
128K
512K M30835FJGP
M30833FJFP
M30833FJGP
Description (Flash Memory Version)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
382
** : Under development
31 Kbytes
512 Kbytes 100P6S-A
100P6Q-A
**
**
**
RAM capacity
ROM capacity Package type RemarksType No
As of Nov., 2001
144P6Q-A
M30835FJGP
M30833FJGP
M30833FJFP
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM No.
Omitted for external ROM version
and blank flash memory version
ROM capacity:
J : 512K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Type No. M 3 0 8 3 5 F J – X X X F P
M32C/83 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
The following lists the M32C/83 products to be supported in the future.
Table 1.33.2. Product List
Figure 1.33.2. Type No., memory size, and package
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
383
User ROM area Boot ROM area
Note 1: The boot ROM area can be rewritten in only parallel input/
output mode. (Access to any other areas is inhibited.)
Note 2: To specify a block, use the maximum address in the block
that is an even address.
8K bytes
0FFE00016
0FFFFFF16
0FF000016 Block 3 : 32K bytes
0FF800016 Block 2 : 8K bytes
0FFA00016 Block 1 : 8K bytes
Block 0 : 16K bytes
0FFC00016
0FFFFFF16
0FD000016 Block 5 : 64K bytes
0FC000016 Block 6 : 64K bytes
0FE000016 Block 4 : 64K bytes
Block 8 : 64K bytes
Block 9 : 64K bytes
Block 7 : 64K bytes
Block 10 : 64K bytes
0FB000016
0FA000016
0F9000016
0F8000016
Flash Memory
The M32C/83 (flash memory version) contains the flash memory that can be rewritten with a single voltage
of 5 V. For this flash memory, three flash memory modes are available in which to read, program, and
erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro-
cessing Unit (CPU). Each mode is detailed in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 1.33.3, so that memory can be erased
one block at a time. Each block has a lock bit to enable or disable execution of an erase or program
operation, allowing for data in each block to be protected.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Figure 1.33.3. Block diagram of flash memory version
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
384
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.33.3 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.33.3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the “boot”
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, lock bit program command, and read lock status command.
Outline Performance of CPU Rewrite Mode
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 037716) is set to “1”, transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-
dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered
address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 1.34.1 shows the flash memory control register 0.
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
385
Flash memory control register 0
Symbol Address When reset
FMR0 005716 XX0000012
WR
b7 b6 b5 b4 b3 b2 b1 b0
FMR00
Bit symbol Bit name Function RW
0: Busy (being written or erased)
1: Ready
CPU rewrite mode
select bit (Note 1) 0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMR01
0: Boot ROM area is accessed
1: User ROM area is accessed
Lock bit disable bit
(Note 2) 0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
Flash memory reset bit
(Note 3) 0: Normal operation
1: Reset
User ROM area select bit (
Note 4) (Effective in only
boot mode)
FMR02
FMR03
FMR05
0
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit. Also write to this
bit when NMI pin is "H" level.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to this bit.
AA
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
A
RY/BY signal status bit
Reserved bit Must always be set to “0”
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
Figure 1.34.1. Flash memory control register
Flash memory control register (address 005716)
_____
Bit 0 of the flash memory control register 0 is the RY/BY signal status bit used exclusively to read the
operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is
“1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession when NMI pin is "H" level. The bit can be set to “0” by only writing a “0” .
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
386
Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to “1”, it is possible to
disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit
only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation
is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To
set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated
only when the CPU rewrite mode select bit = “1”.
Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access
has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To
release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to
rewrite this bit.
Figure 1.34.2 shows a flowchart for setting/releasing the CPU rewrite mode. Always perform operation as
indicated in these flowcharts.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
387
End
Start
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Single-chip mode, memory expansion
mode, or boot mode
Set processor mode register (Note 1)
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Transfer CPU rewrite mode control
program to internal RAM
Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C
16
):
6.25 MHz or less when wait bit (bit 2 at address 0005
16
) = “0” (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 0005
16
) = “1” (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Use the program except in the internal
flash memory for write to this bit. Also write to this bit when NMI pin is "H" level.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
Write “0” to CPU rewrite mode select bit
(Boot mode only)
Set user ROM area select bit to “1”
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
*1
*1
Program in ROM Program in RAM
Figure 1.34.2. CPU rewrite mode set/reset flowchart
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
388
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
_______
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur-
_______
rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter-
rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be
performed over again.
(4) Reset
Reset input is always accepted.
(5) Access disable
Write CPU rewrite mode select bit and user ROM area select bit in an area other than the internal flash
memory.
(6) How to access
For CPU rewrite mode select bit and lock bit disable bit to be set to “1”, the user needs to write a “0”
and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is neces-
sary to ensure that no interrupt or DMA transfer will be executed during the interval.
Write to the CPU rewrite mode select bit when NMI pin is "H" level.
(7)Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
(8)Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
389
Command
Page program
Clear status register
Read array
Read status register
X
X
X
X
(Note 3)
First bus cycle Second bus cycle Third bus cycle
FF
16
70
16
50
16
41
16
Write
Write
Write
Write
XSRDRead
Write
Lock bit program X77
16
Write BA D0
16
Write
Erase all unlock block XA7
16
Write XD0
16
Write
WA1 WD1
Write
(Note 2)
WA0
(Note 3)
WD0
(Note 3)
Block erase X20
16
Write D0
16
Write BA
(Note 4)
Read lock bit status X71
16
Write BA D
6
Read
(Note 5)
Mode Address Mode Address Mode Address
Data
(D
0
to D
7
)
Data
(D
0
to D
7
)Data
(D
0
to D
7
)
(Note 6)
Note 1: When a software command is input, the high-order byte of data (D
8
to D
15
) is ignored.
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 00
16
to FE
16
(byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D
6
corresponds to the block lock status. Block not locked when D
6
= 1, block locked when D
6
= 0.
Note 6: X denotes a given address in the user ROM area (that is an even address).
Software Commands
Table 1.34.1 lists the software commands available with the M16C/62A (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
Table 1.34.1. List of software commands (CPU rewrite mode)
Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0–D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle, the content of the status register is
read out at the data bus (D0–D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
390
n = FE16
Start
Write 4116
n = 0
Write address n and
data n
Check full status
Page program
completed
n = n + 2
NO
YES
NO
YES
RY/BY signal
status bit
= 1?
Page Program Command (4116)
Page program allows for high-speed programming in units of 256 bytes. Page program operation
starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through
the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses
A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to
1 upon completion of the auto write operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY signal status bit of the flash memory control register 0 is 0 during auto write operation and
1 when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 1.34.3 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes to the already programmed pages are prohibited.
Figure 1.34.3. Page program flowchart
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
391
Write 2016
Write D016
Block address
Check full status check
Block erase
completed
Start
NO
YES
RY/BY signal
status bit
= 1?
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY signal status bit of the flash memory control register 0 is 0 during auto erase operation and
1 when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 1.34.4 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
Figure 1.34.4. Block erase flowchart
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
392
Write 7716
Write D016
block address
SR4 = 0? NO
Lock bit program
completed
Lock bit program in
error
YES
Start
RY/BY signal
status bit
= 1?
NO
YES
Erase All Unlock Blocks Command (A716/D016)
By writing the command code “A716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter
how the lock bit is set. On the other hand, when the lock bit disable bit = 0, the function of the lock bit
is effective and only nonlocked blocks (where lock bit data = 1) are erased.
Lock Bit Program Command (7716/D016)
By writing the command code “7716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system sets the
lock bit for the specified block to 0 (locked).
Figure 1.34.5 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit
data) can be read out by a read lock bit status command.
Whether the lock bit program command is terminated can be confirmed by reading the status register
or the flash memory control register 0, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.
Figure 1.34.5. Lock bit program flowchart
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
393
Write 7116
Enter block address
D6 = 0? NO
Blocks locked Blocks not locked
YES
Start
Read Lock Bit Status Command (7116)
By writing the command code “7116” in the first bus cycle and then the block address of a flash
memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the
specified block on to the data (D6).
Figure 1.34.6 shows an example of a read lock bit program flowchart.
Figure 1.34.6. Read lock bit status flowchart
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
394
Data Protect Function (Block Lock)
Each block in Figure 1.33.3 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0’s lock bit disable bit is set.
(1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status
(lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write.
On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/
write.
(2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are
enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after
erasure, so that the lock bit-actuated lock is removed.
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 1.34.2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to “8016.”
Each bit in this register is explained below.
Write state machine (WSM) status (SR7)
After power-on, the write state machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device, as for output on the
____
RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon
completion of these operations.
Erase status (SR5)
The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
395
Each bit of
SRD
SR4 (bit4)
SR5 (bit5)
SR7 (bit7)
SR6 (bit6)
Status name Definition
SR1 (bit1)
SR2 (bit2)
SR3 (bit3)
SR0 (bit0)
"1" "0"
Program status
Erase status
Write state machine (WSM) status
Reserved
Reserved
Reserved
Block status after program
Reserved
Ready Busy
Terminated in error
Terminated in error
Terminated in error
Terminated normally
Terminated normally
Terminated normally
-
-
-
-
-
-
-
-
Program status (SR4)
The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status = 1, the following commands entered by command write are
not accepted.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase
(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is
entered, read array is assumed and the command that has been set up in the first bus cycle is
canceled.
Block status after program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
Table 1.34.2. Definition of each bit in status register
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
396
Read status register
SR4=1 and SR5
=1 ?NO
Command
sequence error
YES
SR5=0?
YES
Block erase error
NO
SR4=0?
YES
Program error (page
or lock bit)
NO
SR3=0?
YES
Program error
(block)
NO
End (block erase, program)
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should a block erase error occur, the block in error
cannot be used.
Execute the read lock bit status command (7116) to
see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be used.
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program
operations. Figure 1.34.7 shows a full status check flowchart and the action to be taken when each
error occurs.
Figure 1.34.7. Full status check flowchart and remedial procedure for errors
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory (Flash Memory Version)
397
Symbol Address When reset
ROMCP 0FFFFFF16 FF16
ROM code protect level
2 set bit (Note 1, 2) 00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
ROM code protect control address
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
ROM code protect reset
bit (Note 3)
ROM code protect level
1 set bit (Note 1)
ROMCP2
ROMCR
ROMCP1
b3 b2
b5 b4
b7 b6
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.
Reserved bit Always set this bit to 1.
11
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM code protect function
The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFFF16) during parallel I/O mode. Figure 1.34.8 shows
the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification. ROM code protect is imple-
mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
Figure 1.34.8. ROM code protect control address
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory (Flash Memory Version)
398
Reset vector
Watchdog timer vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
NMI vector
0FFFFFC16 to 0FFFFFF16
0FFFFF816 to 0FFFFFB16
0FFFFF416 to 0FFFFF716
0FFFFF016 to 0FFFFF316
0FFFFEC16 to 0FFFFEF16
0FFFFE816 to 0FFFFEB16
0FFFFE416 to 0FFFFE716
0FFFFE016 to 0FFFFE316
0FFFFDC16 to 0FFFFDF16
4 bytes
Address
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID
code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they
match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFFDF16, 0FFFFE316,
0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716, and 0FFFFFB16. Write a program which has had the
ID code preset at these addresses to the flash memory.
Figure 1.34.9. ID code store addresses
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash Memory Version)
399
Parallel I/O Mode
In this mode, the M32C/83 (flash memory version) operates in a manner similar to the flash memory
M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not avail-
able with the microcomputer and matters related to memory capacity, the M32C/83 cannot be programed
by a programer for the flash memory.
Use an exclusive programer supporting M32C/83 (flash memory version).
Refer to the instruction manual of each programer maker for the details of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.33.3 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 1.33.3.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FFE00016 through
0FFFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, you do not need to write to the boot
ROM area.
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
400
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
_____ ________
leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H"
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 1.35.1 to 1.35.3 show the pin connections for the standard serial
I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O
switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of
CLK1 pin when the reset is released.
To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and the TxD1 pin to "L"
level, and release the reset. The CLK1 pin is connected to Vcc via pull-up resistance and the TxD1 is
connected to Vss via pull-down resistance. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and
RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input.
The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and
an "H" level when reception starts.
To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset.
The operation uses the two UART1 pins RxD1 and TxD1.
In the standard serial I/O mode, only the user ROM area indicated in Figure 1.35.20 can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
401
Pin Description
VCC,VSS Apply 4.2V to 5.5V to Vcc pin and 0 V to Vss pin.
CNVSS Connect to Vcc pin.
RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
XIN Connect a ceramic resonator or crystal oscillator between XIN
and XOUT pins. To input an externally generated clock, input it
to XIN pin and open XOUT pin.
XOUT
BYTE Connect this pin to Vcc or Vss.
AVCC, AVSS
VREF
Connect AVSS to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for A-D converter from this pin.
P00 to P07Input "H" or "L" level signal or open.
P10 to P17Input "H" or "L" level signal or open.
P20 to P27Input "H" or "L" level signal or open.
P30 to P37Input "H" or "L" level signal or open.
P40 to P47Input "H" or "L" level signal or open.
P51 to P54,
P56, P57Input "H" or "L" level signal or open.
P50Input "H" level signal.
P55Input "L" level signal.
P60 to P63Input "H" or "L" level signal or open.
P64
P65
P66Serial data input pin
P67
P70 to P77Input "H" or "L" level signal or open.
P80 to P84, P86,
P87Input "H" or "L" level signal or open.
P90 to P97Input "H" or "L" level signal or open.
P100 to P107Input "H" or "L" level signal or open.
Name
Power input
CNVSS
Reset input
Clock input
Clock output
BYTE
Analog power supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
Input port P5
CE input
EPM input
Input port P6
BUSY output
SCLK input
RxD input
TxD output
Input port P7
Input port P8
Input port P9
Input port P10
I/O
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
O
I
I
O
I
I
I
I
P85NMI input IConnect this pin to Vcc.
I
Standard serial mode 1: BUSY signal output pin
Standard serial mode 2: Monitors the program operation check
Standard serial mode 1: Serial clock input pin
Standard serial mode 2: Input "L" level signal.
P110 to P114Input "H" or "L" level signal or open. (Note)
Input port P11 I
P120 to P127Input "H" or "L" level signal or open. (Note)
Input port P12 I
P130 to P137Input "H" or "L" level signal or open. (Note)
Input port P13 I
P140 to P146Input "H" or "L" level signal or open. (Note)
Input port P14 I
P150 to P157Input "H" or "L" level signal or open. (Note)
Input port P15 I
Serial data output pin. When using standard serial mode 1, an
"L" level must be input to TxD pin while the RESET pin is “L”.
For this reason, this pin should be pulled down. After being reset,
this pin functions as a data output pin. Thus adjust pull-down
resistance value with the system not to affect data transfer.
Note: Port P11 to P15 exist in 144-pin version.
Pin functions (Flash memory standard serial I/O mode)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
402
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
5152
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Vcc
Vss
TxD
RxD SCLK
CNVss
CE
EPM
BUSY
RESET
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc
Mode setting
Connect
oscillation
circuit
M32C/83(100-pin) Group
Flash Memory Version
(100P6S)
Figure 1.35.1. Pin connections for standard serial I/O mode (1)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
403
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CNV
SS
RESET
V
SS
V
CC
CE
BUSY
EPM
SCLK
R
X
DT
X
D
Connect
oscillation
circuit
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc
Mode setting
M32C/83(100-pin) Group
Flash Memory Version
(100P6Q)
Figure 1.35.2. Pin connections for standard serial I/O mode (2)
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
404
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144 37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
7374757677798081828384858687888990919293949596979899
100101102103104105106107108
78
1234 7689101112131415161718192021222324252627282930531 32 33 34 35 36
CNV
SS
RESET
EPM
CE
V
CC
V
SS
TxD
RxD
SCLK BUSY
M32C/83(144-pin) Group
Flash Memory Version
(144P6Q)
Signal Value
CNVss Vcc
EPM Vss
RESET Vss >> Vcc
CE Vcc
Mode setting
Connect
oscillation
circuit
Figure 1.35.3. Pin connections for standard serial I/O mode (3)
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Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
405
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1).
Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level.
In reception, software commands, addresses and program data are synchronized with the rise of the trans-
fer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the
read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin.
The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first.
When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is
"H" level. Accordingly, always start the next transfer after the RST1 (BUSY) pin is "L" level.
Also, data and status registers in memory can be read after inputting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained software commands, status
registers, etc.
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M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
406
Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte
1 Page read
2 Page program
3 Block erase
4 Erase all unlocked blocks
5 Read status register
6 Clear status register
7 Read lock bit status
8 Lock bit program
9 Lock bit enable
10 Lock bit disable
11 Code processing function
12 Download function
13 Version data output function
14 Boot ROM area output
function
15 Read check data
Address
(middle)
Address
(middle)
Address
(middle)
D016
SRD
output
Address
(middle)
Address
(middle)
Address
(low)
Size (low)
Version
data
output
Address
(middle)
Check
data (low)
Address
(high)
Address
(high)
Address
(high)
SRD1
output
Address
(high)
Address
(high)
Address
(middle)
Size
(high)
Version
data
output
Address
(high)
Check
data
(high)
Data
output
Data
input
D016
Lock bit
data
output
D016
Address
(high)
Check-
sum
Version
data
output
Data
output
Data
output
Data
input
ID size
Data
input
Version
data
output
Data
output
Data
output
Data
input
ID1
To
required
number
of times
Version
data
output
Data
output
Data
output to
259th byte
Data input
to 259th
byte
To ID7
Version
data
output to
9th byte
Data
output to
259th
byte
FF16
4116
2016
A716
7016
5016
7116
7716
7A16
7516
F516
FA16
FB16
FC16
FD16
When ID is
not verified
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
1st byte
transfer
Software Commands
Table 1.35.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Software commands are
explained here below.
Table 1.35.1. Software commands (Standard serial I/O mode 1)
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register data1 .
Note 3:All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
407
data0 data255
CLK1
RxD1
TxD1
RTS1(BUSY)
A8 to
A15 A16 to
A23
FF16
(M32C reception data)
(M32C transmit data)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
Figure 1.35.4. Timing for page read
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2)
Transfer addresses A
8
to A
15
and A
16
to A
23
with the 2nd and 3rd bytes respectively.
(3)
From the 4th byte onward, as write data (D
0
–D
7
) for the page (256 bytes) specified with addresses
A
8
to A
23
is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
408
CLK1
RxD1
TxD1
RTS1(BUSY)
A8 to
A15 A16 to
A23
4116 data0 data255
(M32C reception data)
(M32C transmit data)
A8 to
A15 A16 to
A23
2016 D016
CLK1
RxD1
TxD1
RTS1(BUSY)
(M32C reception data)
(M32C transmit data)
Figure 1.35.5. Timing for the page program
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
Figure 1.35.6. Timing for block erasing
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
409
CLK1
RxD1
TxD1
RTS1(BUSY)
A716 D016
(M32C reception data)
(M32C transmit data)
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register. Each block can be erase-protected with the
lock bit. For more information, see the section on the data protection function.
Figure 1.35.7. Timing for erasing all unlocked blocks
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
Figure 1.35.8. Timing for reading the status register
SRD
output SRD1
output
CLK1
RxD1
TxD1
RTS1(BUSY)
7016
(M32C reception data)
(M32C transmit data)
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
410
CLK1
RxD1
TxD1
RTS1(BUSY)
A8 to
A15 A16 to
A23
7116
DQ6
(M32C reception data)
(M32C transmit data)
CLK1
RxD1
TxD1
RTS1(BUSY)
5016
(M32C reception data)
(M32C transmit data)
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L”
level.
Figure 1.35.9. Timing for clearing the status register
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data
is the lock bit data. Write the highest address of the specified block for addresses A8 to A23.
Figure 1.35.10. Timing for reading lock bit status
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
411
CLK1
RxD1
TxD1
RTS1(BUSY)
A8 to
A15 A16 to
A23
7716 D016
(M32C reception data)
(M32C transmit data)
Lock Bit Program Command
This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, reset proce-
dure and so on, see the section on the data protection function.
Figure 1.35.11. Timing for the lock bit program
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
Figure 1.35.12. Timing for enabling the lock bit
7A16
CLK1
RxD1
TxD1
RTS1(BUSY)
(M32C reception data)
(M32C transmit data)
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
412
ID size ID1 ID7
CLK1
RxD1
TxD1
RTS1(BUSY)
F516 DF16 FF16 0F16
(M32C reception
data)
(M32C transmit
data)
75
16
CLK1
RxD1
TxD1
RTS1(BUSY)
(M32C reception data)
(M32C transmit data)
Lock Bit Disable Command
This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
Figure 1.35.13. Timing for disabling the lock bit
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
Figure 1.35.14. Timing for the ID check
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
413
FA
16 Program
data
Data size (high)
Data size (low)
Check
sum
CLK1
RxD1
TxD1
RTS1(BUSY)
(M32C reception data)
(M32C transmit data)
Program
data
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
Figure 1.35.15. Timing for download
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
Figure 1.35.16. Timing for version information output
FB16
'X'
'V' 'E' 'R'
CLK1
RxD1
TxD1
RTS1(BUSY)
(M32C reception data)
(M32C transmit data)
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
414
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
data0 data255
CLK1
RxD1
TxD1
RTS1(BUSY)
A
8
to
A
15
A
16
to
A
23
FC
16
(M32C reception data)
(M32C transmit data)
Figure 1.35.17. Timing for boot ROM area output
Read Check Data
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
415
Check data (low)
CLK1
RxD1
TxD1
RTS1(BUSY)
FD16
(M32C reception data)
(M32C transmit data)
Check data (high)
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.
Figure 1.35.19. ID code storage addresses
Reset vector
Watchdog timer vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
NMI vector
0FFFFFC16 to 0FFFFFF16
0FFFFF816 to 0FFFFFB16
0FFFFF416 to 0FFFFF716
0FFFFF016 to 0FFFFF316
0FFFFEC16 to 0FFFFEF16
0FFFFE816 to 0FFFFEB16
0FFFFE416 to 0FFFFE716
0FFFFE016 to 0FFFFE316
0FFFFDC16 to 0FFFFDF16
4 bytes
Address
Figure 1.35.18. Timing for the read check data
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
416
User ROM area
0FF0000
16
Block 3 : 32K bytes
0FF8000
16
Block 2 : 8K bytes
0FFA000
16
Block 1 : 8K bytes
Block 0 : 16K bytes
0FFC000
16
0FFFFFF
16
0FD0000
16
Block 5 : 64K bytes
0FC0000
16
Block 6 : 64K bytes
0FE0000
16
Block 4 : 64K bytes
Block 8 : 64K bytes
Block 9 : 64K bytes
Block 7 : 64K bytes
Block 10 : 64K bytes
0FB0000
16
0FA0000
16
0F90000
16
0F80000
16
Data Protection (Block Lock)
Each of the blocks in Figure 1.35.20 have a nonvolatile lock bit that specifies protection (block lock)
against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command.
Also, the lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable and lock enable bit commands.
(1) After the reset has been cancelled and the lock bit enable command executed, the specified block
can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked
and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked
and can be erased or written in.
(2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that was “0” before the block
was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.
Figure 1.35.20. Blocks in the user area
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
417
SRD bits
SR0 (bit0)
SR1 (bit1)
SR2 (bit2)
SR3 (bit3)
SR4 (bit4)
SR5 (bit5)
SR6 (bit6)
SR7 (bit7)
Status name
Reserved
Reserved
Reserved
Block status after program
Program status
Erase status
Reserved
Write state machine (WSM) status
Definition
"1" "0"
-
-
-
Terminated in error
Terminated in error
Terminated in error
-
Ready
-
-
-
Terminated normally
Terminated normally
Terminated normally
Busy
-
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.35.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table 1.35.2. Status register (SRD)
Program Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
418
SRD1 bits
SR8 (bit0)
SR9 (bit1)
SR10 (bit2)
SR11 (bit3)
SR12 (bit4)
SR13 (bit5)
SR14 (bit6)
SR15 (bit7)
Status name
Reserved
Data receive time out
ID check completed bits
Checksum match bit
Reserved
Reserved
Boot update completed bit
Definition
"1" "0"
-
Time out
00
01
10
11
Match
-
-
Update completed
-
Normal operation
Mismatch
-
-
Not update
Not verified
Verification mismatch
Reserved
Verified
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.35.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON
and the flag status is maintained even after the reset.
Table 1.35.3. Status register 1 (SRD1)
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
419
Clock input
(1) Control pins and external circuitry will vary according to peripheral unit (programmer). For more
information, see the peripheral unit (programmer) manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
BUSY output RTS1(BUSY)
CLK1
Data input RXD1
Data output TXD1
CNVss
P50(CE)
P55(EPM) NMI
M32C/83
Flash memory version
Read status register
SR4=1 and SR5
=1 ?NO
Command
sequence error
YES
SR5=0?
YES
Block erase error
NO
SR4=0?
YES
Program error (page
or lock bit)
NO
SR3=0?
YES
Program error
(block)
NO
End (block erase, program)
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should a block erase error occur, the block in error
cannot be used.
Execute the read lock bit status command (7116) to
see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be used.
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure
1.35.21 shows a flowchart of the full status check and explains how to remedy errors which occur.
Figure 1.35.21. Full status check flowchart and remedial procedure for errors
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for
more information.
Figure 1.35.22. Example circuit application for the standard serial I/O mode 1
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
420
Overview of standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1).
Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level.
The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.
After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-
ure 1.35.23) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz
input oscillation frequency. Baud rate can be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200
bps by executing software commands. However, communication errors may occur because of the oscilla-
tion frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud
rate.
After executing commands from a peripheral unit that requires time to erase and write data, as with erase
and program commands, allow a sufficient time interval or execute the read status command and check
how processing ended, before executing the next command.
Data and status registers in memory can be read after transmitting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained initial communications with
peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-
quency of the main clock, by sending the code as prescribed by the protocol for initial communications
with peripheral units (Figure 1.35.23).
(1) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit
rate generator so that "0016" can be successfully received.)
(2) The MCU with internal flash memory outputs the "B016" check code and initial communications end
successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer
interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.
*1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main
clock.
MCU with internal
flash memory
Peripheral unit
(1) Transfer "0016" 16 times
At least 15ms
transfer interval
1st
2nd
15 th
16th (2) Transfer check code "B016"
"0016"
"0016"
"0016"
"B016"
"0016"
Reset
The bit rate generator setting completes (9600bps)
Figure 1.35.23. Peripheral unit and initial communication
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
421
Operation frequency
(MH
Z
)Baud rate
9,600bps Baud rate
19,200bps Baud rate
38,400bps Baud rate
57,600bps
30MHz
20MHz
16MH
Z
12MH
Z
11MH
Z
10MH
Z
8MH
Z
7.3728MH
Z
6MH
Z
5MH
Z
4.5MH
Z
4.194304MH
Z
4MH
Z
3.58MH
Z
3MH
Z
2MH
Z
: Communications possible
– : Communications not possible
–
–
–
–
–
–
–
–
–
Baud rate
115,200bps
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
How frequency is identified
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the
bit rate generator is set to match the operating frequency (2 - 30 MHz). The highest speed is taken from
the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit
rate generator value for a baud rate of 9,600 bps.
Baud rate cannot be attained with some operating frequencies. Table 1.35.4 gives the operation fre-
quency and the baud rate that can be attained for.
Table 1.35.4 Operation frequency and the baud rate
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
422
Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte
1 Page read
2 Page program
3 Block erase
4 Erase all unlocked blocks
5 Read status register
6 Clear status register
7 Read lock bit status
8 Lock bit program
9 Lock bit enable
10 Lock bit disable
11 Code processing function
12 Download function
13 Version data output function
14 Boot ROM area output
function
15 Read check data
16 Baud rate 9600
17 Baud rate 19200
18 Baud rate 38400
19 Baud rate 57600
20 Baud rate 115200
Address
(middle)
Address
(middle)
Address
(middle)
D016
SRD
output
Address
(middle)
Address
(middle)
Address
(low)
Size (low)
Version
data
output
Address
(middle)
Check
data (low)
B016
B116
B216
B316
B416
Address
(high)
Address
(high)
Address
(high)
SRD1
output
Address
(high)
Address
(high)
Address
(middle)
Size
(high)
Version
data
output
Address
(high)
Check
data
(high)
Data
output
Data
input
D016
Lock bit
data
output
D016
Address
(high)
Check-
sum
Version
data
output
Data
output
Data
output
Data
input
ID size
Data
input
Version
data
output
Data
output
Data
output
Data
input
ID1
To
required
number
of times
Version
data
output
Data
output
Data
output to
259th byte
Data input
to 259th
byte
To ID7
Version
data
output to
9th byte
Data
output to
259th byte
FF16
4116
2016
A716
7016
5016
7116
7716
7A16
7516
F516
FA16
FB16
FC16
FD16
B016
B116
B216
B316
B416
When ID is
not verified
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Acceptable
Acceptable
Acceptable
Acceptable
Acceptable
1st byte
transfer
Software Commands
Table 1.35.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2
adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft-
ware commands of standard serial I/O mode 1. Software commands are explained here below.
Table 1.35.5. Software commands (Standard serial I/O mode 2)
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register data 1.
Note 3:All commands can be accepted when the flash memory is totally blank.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
423
data0 data255
RxD1
TxD1
A8 to
A15 A16 to
A23
FF16
(M32C reception data)
(M32C transmit data)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
Figure 1.35.24. Timing for page read
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2)
Transfer addresses A
8
to A
15
and A
16
to A
23
with the 2nd and 3rd bytes respectively.
(3)
From the 4th byte onward, as write data (D
0
–D
7
) for the page (256 bytes) specified with addresses
A
8
to A
23
is input sequentially from the smallest address first, that page is automatically written.
The result of the page program can be known by reading the status register. For more information, see
the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
Figure 1.35.25. Timing for the page program
RxD1
TxD1
A
8
to
A
15
A
16
to
A
23
41
16
data0 data255
(M32C reception data)
(M32C transmit data)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
424
A8 to
A15 A16 to
A23
2016 D016
RxD1
TxD1
(M32C reception data)
(M32C transmit data)
RxD1
TxD1
A716 D016
(M32C reception data)
(M32C transmit data)
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.
After block erase ends, the result of the block erase operation can be known by reading the status
register. For more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
Figure 1.35.26. Timing for block erasing
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
The result of the erase operation can be known by reading the status register. Each block can be erase-
protected with the lock bit. For more information, see the section on the data protection function.
Figure 1.35.27. Timing for erasing all unlocked blocks
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
425
SRD
output SRD1
output
RxD1
TxD1
70
16
(M32C reception data)
(M32C transmit data)
RxD1
TxD1
50
16
(M32C reception data)
(M32C transmit data)
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
Figure 1.35.28. Timing for reading the status register
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
Figure 1.35.29. Timing for clearing the status register
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data
is the lock bit data. Write the highest address of the specified block for addresses A8 to A23.
RxD1
TxD1
A8 to
A15 A16 to
A23
7116
DQ6
(M32C reception data)
(M32C transmit data)
Figure 1.35.30. Timing for reading lock bit status
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
426
7A
16
RxD1
TxD1
(M32C reception data)
(M32C transmit data)
RxD1
TxD1
A
8
to
A
15
A
16
to
A
23
77
16
D0
16
(M32C reception data)
(M32C transmit data)
Lock Bit Program Command
This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
Lock bit status can be read with the read lock bit status command. For information on the lock bit
function, reset procedure and so on, see the section on the data protection function.
Figure 1.35.31. Timing for the lock bit program
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
Figure 1.35.32. Timing for enabling the lock bit
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
427
7516
RxD1
TxD1
(M32C reception data)
(M32C transmit data)
Lock Bit Disable Command
This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
Figure 1.35.33. Timing for disabling the lock bit
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
Figure 1.35.34. Timing for the ID check
ID size ID1 ID7
RxD1
TxD1
F5
16
DF
16
FF
16
0F
16
(M32C reception
data)
(M32C transmit
data
)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
428
FB16
'X'
'V' 'E' 'R'
RxD1
TxD1
(M32C reception data)
(M32C transmit data)
FA16 Program
data
Data size (high)
Data size (low)
Check
sum
RxD1
TxD1
(M32C reception data)
(M32C transmit data)
Program
data
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
Figure 1.35.35. Timing for download
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
Figure 1.35.36. Timing for version information output
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
429
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
data0 data255
CLK1
RxD1
TxD1
RTS1(BUSY)
A
8
to
A
15
A
16
to
A
23
FC
16
(M32C reception data)
(M32C transmit data)
Figure 1.35.37. Timing for boot ROM area output
Read Check Data
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.
Figure 1.35.38. Timing for the read check data
Check data (low)
RxD1
TxD1
FD16
(M32C reception data)
(M32C transmit data)
Check data (high)
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
430
RxD1
TxD1
B116
(M32C reception data)
(M32C transmit data) B116
RxD1
TxD1
B216
(M32C reception data)
(M32C transmit data) B216
RxD1
TxD1
B016
(M32C reception data)
(M32C transmit data) B016
Baud Rate 9600
This command changes baud rate to 9,600 bps. Execute it as follows.
(1) Transfer the "B016" command code with the 1st byte.
(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
Figure 1.35.39. Timing of baud rate 9600
Baud Rate 19200
This command changes baud rate to 19,200 bps. Execute it as follows.
(1) Transfer the "B116" command code with the 1st byte.
(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
Figure 1.35.41. Timing of baud rate 38400
Figure 1.35.40. Timing of baud rate 19200
Baud Rate 38400
This command changes baud rate to 38,400 bps. Execute it as follows.
(1) Transfer the "B216" command code with the 1st byte.
(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
431
RxD1
TxD1
B316
(M32C reception data)
(M32C transmit data) B316
Baud Rate 57600
This command changes baud rate to 57,600 bps. Execute it as follows.
(1) Transfer the "B316" command code with the 1st byte.
(2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
Figure 1.35.42. Timing of baud rate 57600
Baud Rate 115200
This command changes baud rate to 115,200 bps. Execute it as follows.
(1) Transfer the "B416" command code with the 1st byte.
(2) After the "B416" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
Figure 1.35.43. Timing of baud rate 115200
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.
RxD1
TxD1
B416
(M32C reception data)
(M32C transmit data) B416
Under
development
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
432
Monitor output
Data input
Data output
RTS1(BUSY)
CLK1
RXD1
TXD1
CNVss
P50(CE)
P55(EPM)
NMI
M32C/80 Flash
memory version
In this example, the microprocessor mode and standard serial I/O mode
are switched via a switch.
Reset vector
Watchdog timer vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
NMI vector
0FFFFFC16 to 0FFFFFF16
0FFFFF816 to 0FFFFFB16
0FFFFF416 to 0FFFFF716
0FFFFF016 to 0FFFFF316
0FFFFEC16 to 0FFFFEF16
0FFFFE816 to 0FFFFEB16
0FFFFE416 to 0FFFFE716
0FFFFE016 to 0FFFFE316
0FFFFDC16 to 0FFFFDF16
4 bytes
Address
Figure 1.35.44. ID code storage addresses
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
Figure 1.35.45. Example circuit application for the standard serial I/O mode 2
REVISION HISTORY M32C/83 GROUP DATA SHEET
Rev.
Date Description
Page Errror Correct
( 1 / 7 )
B1
1/8/2001 100-pin version is added.
Flash memory version is added.
Others
2,3 Tables 1.1.1 and 1.1.2
Interrupt: 12 internal/external sources
(intelligent I/O and CAN module) Delate
Supply voltage 3.0 to 3.6V (f(XIN)=20MHz without wait) add
3 A-D converter
10 bits (8 channels) x 2 circuits, max 26 inputs 10 bits x 2 circuits, standard 10 inputs, max 26 inputs
7 Table 1.1.3 Pin 26 CANIN addition
10-12 Figures 1.1.4, 1.1.5, Table 1.1.7 CANIN is added to Pin 17(GP) and pin 19(FP)
11 Figure 1.1.5 Pin 97 AN00AN0
12 Pin 32 (FP) Vcc Delate
Pin 34 (FP) Vss Delate
13 Vcc position to pin 64(FP) Pin 62
Vss position to pin 66(FP) Pin 64
RxD4/SCL4/STxD4 position to pin 98 (FP) Pin 100
14 Table 1.1.5 AN20 to AN27AN00 to AN07
AN30 to AN37AN20 to AN27
17 Table1.1.12 P120 to P127 ISCLK description Delate
AN10 to AN17AN150 to AN157
18 Figure 1.1.6 System clock oscillation circuit PLL oscillation stop detect addition
28, 29 Figure 1.4.3 (122), (167) Group0 receive buffer register, Group1 receive buffer
register
(123), (168) Group0 transmit buffer/receive data register, Group1
transmit buffer/receive data register
46 Note 1: Addresses 03C916, 03CB16 to 03D316 Addresses 03A016, 03A116, 03B916, 03BC16, 03BD16,
03C916, 03CB16 to 03D316
48 Figure 1.6.1 Note 2 Addition. Displase after the former Note 2
70 Figure 1.8.6
When reset of PLL control register 0
0X11 0100 0011 0100
72 Figure 1.8.8 Count value set bit Division rate select bit
Count start bit Operation enable bit
Count stop/start Divider stops/starts
Note 2 Delate
76 Line 10 Addition Stop mode is canceled before setting this bit to "1".
77 Line 8 1:Sub clock is selected 1: Clock from ring oscillator is selected
135 Figure 1.14.2 Values that can be set Pulse width
modulation mode (8-bit PWM)
0016 to FF16(High-order and low-order address) 0016 to FE16(High-order address) 0016 to FF16(Low-
order address)
230 Line 5, Bit 1 TrmActive TrmData
266 Table1.23.11 Waveform generate control register
1when clock synchronous serial I/O
-√
280 Table1.23.17 Note 1: When the transfer clock and transfer data are trans-
mission, transfer clock is set to at least 6 divisions of
B1
30/8/
2001
REVISION HISTORY M32C/83 GROUP DATA SHEET
Rev.
Date Description
Page Errror Correct
( 2 / 7 )
the base timer clock. Except this, transfer clock is set
to at least 20 divisions of the base timer clock.
Note 2 Addition
285 Figure 1.23.37 Delay timing of base timer
284 Table1.24.1 A-D conversion start condition
• Timer B2 interrupt • Timer B2 interrupt occurrences frequency counter
overflow
B2
Feb/1/
2002
2, 3, 4 Table 1.1.1, 1.1.2
Clock generating circuit 4 built-in...circuit 3 built-in clock generation circuits
PLL freq. synthe. Delete
Power consumption 29mA 26mA
44mA 38mA
6,10, Fig 1.1.3-1.1.5 Note: P70 and P71 are N-channel...output.-> Add
11
18 Fig 1.1.6 System clock generator
PLL Delete
Oscillation stop detection Ring oscillator
24 7th line Since the value.....due to the interruption. -> Add
27 Fig 1.4.3 (1)
(2) Processor mode register 1 XX00 X000 -> X000 00XX
(3) System clock control register 0 80 -> 0000 X000
(10) Oscillation stop detect register XXXX 0000 -> 00
(17) VDC control register 1 Add
(21) DRAM refresh interval set register XXXX ?000 -> ??
(46) CAN interrupt 1 control register Add
(47) CAN interrupt 2 control register Add
28 Fig 1.4.3 (2)
(70) CAN interrupt 0 control register Add
28-31 Fig 1.4.3(2) (97)-(104), Fig 1.4.3(3) (142)-(149),
Fig 1.4.3(4) (187)-(194), Fig 1.4.3(5) (222)-(229)
Group 0 -3 time measurement/
waveform generation register 0-7 00 -> ??
29, 30 Fig 1.4.3(3) (124), Fig 1.4.3(4) (169)
Group 0,1 SI/O communication buffer register Group 0,1 SI/O receive buffer register
Fig 1.4.3(3) (125), Fig 1.4.3(4) (170)
Group 0,1 receive data register Group 0,1 transmit buffer/receive data register
(129) Group 0 SI/O comm cont register X000 XXX -> 000 X011
(186) Group 1 SI/O expansion trans cont register 0000 00XX -> 0000 0XXX
31 Fig 1.4.3(5) (238)-(241)
Group 3 waveform generate mask register 4-7 00 -> ??
32 Fig 1.4.3(6) (270)-(308) Note added
(270)-(302) Reset value changed
33 Fig 1.4.3(7) (309)-(338) Note added
(314)-(318),(321),(323),(329),(331),(336) Reset values changed
(337) CAN0 clock control register CAN0 sleep control register
36 Fig 1.4.3(10) (461) A-D control register 2 X000 XXX0 -> X000 0000
REVISION HISTORY M32C/83 GROUP DATA SHEET
Rev.
Date Description
Page Errror Correct
( 3 / 7 )
38 Address 007F16 CAN interrupt 1 control register added
Address 008116 CAN interrupt 2 control register added
Address 009D16 CAN interrupt 0 control register added
61 (10) Software wait, 11th line
SFR area is accessed.....with “2 waits”.Add
67 Fig 1.8.2 System clock control register 0
When reset: 0816 0000 X0002
Note 3: When selecting fc,.....as input port. Delete
79 Fig 1.8.9
Note 7: When using PLL.....cannot be used. Delete
90 Fig 1.9.3, Symbol CAN0ICi CANiIC
110 Table 1.11.1, DMA request factors Intelligent I/O interrupt -> add
128 Fig 1.12.4, the number of cycles Change
133 Fig 1.14.3, Timer Ai mode register, MR0
Port output.....registers A and B. Port output.....registers A, B and C.
137, Table 1.14.1, 1.14.2, 1.14,4, 1.14,5
138, TAiOUT pin function Function select register C -> add
142,
144
137 Fig 1.14.7 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
Location of Note 3 (b7, b6): 11 10
139 Fig 1.14.8 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
143, Fig 1.14.11, 1.14.12 Timer Ai mode register
145 bit 2 (MR0) Function select register C -> add
Location of Note 3 (b7, b6): 11 10
159 Fig 1.16.5 Timer Ai mode register
bit 2 (MR0) Function select register C -> add
161 Fig 1.16.6 Reload register Reload register
n = 1 to 255
172 Fig 1.17.4 UARTi transmit/receive control register 0
Note 2 Function select register C -> add
173 Fig 1.17.5 UARTi transmit/receive control register 1
Function of bit 7: Error signal output enable bit Set to “0”
199 Fig 1.22.1 Clock control register Sleep control register
Time stamp count register Time stamp register
200 Fig 1.22.3 Bit 4 0: Forced reset 0: Reset requested
Bit 10 Time stamp count reset bit Time stamp counter reset bit
201 5th line: In no case will the CAN module be ..... In no case will the CAN be.....
Bit 3: BasicCAN mode bit Bit 3: BasicCAN mode select bit
202 Bit 8,9: Timestamp prescaler bits Bit 8, 9: Timestamp prescaler select bits
Bit 11, 1st line: Receive Error Counter Receive Error Counter Register
Transmit Error Counter Transmit Error Counter Register
209 Fig 1.22.8 bit 4: Reserved bit Sampling number
210 6. CAN0 configuration register Explanation of Bit 4 -> add
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211 Note:1 Setting the C0CTLR0 register’s Reset0 bit
to 1 resets the CAN protocol control unit, with the
C0TSR register thereby initialized to 000016. Also,
setting the TSReset (timestamp count reset) bit to
1 initializes the C0TSR register to 000016 on-the-
fly (while the CAN protocol control unit remains
operating).
Note 1: Setting the C0CTLR0 register’s Reset0 and
Reset1 bits to 1 resets the CAN, and the C0TSR
register is thereby initialized to 000016. Also, setting
the TSReset (timestamp counter reset) bit to 1 ini-
tializes the C0TSR register to 000016 on-the-fly (while
the CAN remains operating; CAN0 status register’s
State_Reset bit is “0”).
212 Tq period = (C0BRP+1) Tq period = (C0BRP+1)/CPU clock
220 Fig 1.22.19 b0 b2
b2 b1
226 Fig 1.22.25 bit 0 Note 2 -> add
bit 1, When transmit, TrmData When transmit, TrmActive
bit 3 Note 2 -> add
bit 6, 7, Transmit request flag Transmit request bit
229 Fig 1.22.26, explanation of function Change
230, Fig 1.22.27, 1.22.28, 1.22.29
231, Explanation of function Message slot j (j=0 to 15) -> change
232
233 Fig 1.22.30, CAN0 message slot butter i data m
Symbol C0SLOT0_m (m=0 to 3) C0SLOT0_n (n=m+6, m=0 to 3)
C0SLOT0_m (m=4 to 7) C0SLOT0_n (n=m+6, m=4 to 7)
C0SLOT1_m (m=0 to 3) C0SLOT1_n (n=m+6, m=0 to 3)
C0SLOT1_m (m=4 to 7) C0SLOT1_n (n=m+6, m=4 to 7)
235 Table 1.23.1 Group 2, WG register - -> 8chs
Group 3 Comm shift register 16bits x 2chs -> -
240 Fig 1.23.5, Group i base timer cont reg 0
Bit 2 to bit 6, explanations on fPLL Delete
245 Table 1.23.2, Count reset condition, Group 2, 3
(3) Reset request ..... circuit (3) Reset request ..... circuit (group 2 only)
245 Fig 1.23.10 fPLL Delete
246 Fig 1.23.11 Newly added
248 Fig 1.23.13, the values when reset: 0016 000016
249 Table 1.23.3, select function, digital filter function
Strips off pulses less than 3 cycles long from f1Pulses will pass when they match either f1 or the base
and the base timerclock. timerclock 3 times.
250 Fig 1.23.14, (c) Change
252 Fig 1.23.16, reset values for both registers 000016 -> XXXX16
256 Fig 1.23.20, When WG register is “xxxb16”When WG register is “xxxa16”
270 Table 1.23.12
Transmission start condition
• Write data to transmit buffer register • Write data to transmit buffer
Interrupt request generation timing
•When transmitting
- When SI/O transmit buffer register is..... - When transmit buffer is .....
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register
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Date Description
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270 Select function
This.....TxD pin output and RxD pin input. This.....ISTxD pin output and ISRxD pin input.
271 Table 1.23.13, Transfer clock input
•Selects I/O with function..... •Select I/O port with function.....
271 Fig 1.23.31
Write to communication buffer Write to receive buffer
(Input to INPC2/ISRxD0 pin) (Input to INPCi2/ISRxDi pin (i=0, 1))
272 Table 1.23.14
Transmission start condition
• Write data to transmit buffer register • Write data to transmit buffer
Interrupt request generation timing
•When transmitting
- When SI/O transmit buffer register is..... - When transmit buffer is .....
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register
Error detection
• Overrun error:
.....before contents of receive buffer register.... .....before contents o SI/O receive buffer register.....
273 Fig 1.23.32
Write to communication buffer Write to receive buffer
273 Fig 1.23.33
(Input to INPC2/ISRxD0 pin) (Input to INPCi2/ISRxDi pin (i=0, 1))
279 Table 1.23.17
Transmission start condition
• Write data to transmit buffer register • Write data to SI/O transmit buffer register
Reception start condition
• Write data to transmit buffer register • Write data to SI/O transmit buffer register
Interrupt request generation timing
•When receiving
When....to SI/O communication buffer register When.....to SI/O receive buffer register
Select function
This.....TxD pin output and RxD pin input. This.....ISTxD pin output and ISRxD pin input.
286 Fig 1.24.4, A-D control register 2
When reset: X000 XXX02X000 00002
287, Fig 1.24.5, Note 4 and Fig 1.24.6, Note 3
288 ..... by A-D sweep pin select bits..... .....by analog input port select bits.....
292 (e) Replace function of input pin
2nd line: .....of A-D0 and A-D2. .....of A-D0 and A-D1.
293 (f) , at the end of 2nd line as AN0.....respectively. -> add
(g) 3rd line: ....., input via AN00 to AN07 is..... , input via AN0 to AN7 is.....
294 Table 1.24.9 P00 analog input P95 analog input
P01 analog input P96 analog input
312 Fig 1.29.1, P00 to P07, P20 to P27: -
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Page Errror Correct
( 6 / 7 )
313 Fig 1.29.2 Delete
Direction register
Port latch
Pull-up selection
Data bus
Port P1 control
register
Direction register
Port latch
Pull-up selection
Data bus
Port P1 control
register
Circuit (C) Delete
P15 to P17, Circuit (B): -
314 Fig 1.29.3 Add
Direction register
Pull-up selection
Function select
register A (Note 1)
D
Output from each
peripheral function
Direction register
Pull-up selection
Function select
register A (Note 1)
D
Output from each
peripheral function
P121, P122, Circuit (B): -
326 Fig 1.29.16, Pull-up register 2, Note 1 Delete
331 Table 1.29.5 _____
Bit 0, 1: Three-phase PWM output (U) 1: Three-phase PWM output (U)
Bit 1, 0: Three-phase PWM output (U) _____
0: Three-phase PWM output (U)
331 Table 1.29.6, PS4 PS3
PSL4 PSL3
Bit 1, UART0 UART3
Bit 2, UART4 UART3
Bit 3, UART1 UART3
Bit 4, 5 UART1 UART4
A4 A3
B4 B3
334 VDC Add
337 A-D Converter
1st line: A-D A-D i (i=0,1)
1st line: A-D A-D i
2nd line: .....and to bit 0 of A-D control register 2... .....and to each bit of A-D i control register 2.....
340 (3) External interrupt
• Level sense, 2nd line: (When XIN=20MHz and..) (When XIN=30MHz and .....)
3rd line: (....., at least 250 ns.....) (....., at least 233 ns.....)
• When the polarity of INT0 to INT5 pins is..... _______ _______
• When the polarity of INT0 and INT5 pins is.....
341 Reducing power consumption, (2)
1st line, last line: AN04, AN07AN4, AN7
343 Table 1.30.3 G0CR 00EF16 G0RI 00EC 16
G1RI 012F16 G1RI 012C16
U0BRG 036116 U0BRG 036916
U0TB 036316, 036216 U0TB 036B16, 036A16
U1BRG 036916 U1BRG 02E916
U1TB 036B16, 036A16 U1TB 02EB16, 02EA16
343 Notes on CNVss pin reset at “H” level Add
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Rev.
Date Description
Page Errror Correct
( 7 / 7 )
344- Electric characteristics Add
380
385 Fig 1.34.1, Address 037716 Address 005716
_____
Bit 0: RY/BY status bit _____
RY/BY signal status bit
385 Flash memory control register (address 005716)
_____
1st line: .....the RY/BY status flag..... _____
.....the RY/BY signal status bit.....
390 13th line of Page Program Command (4116) and
_____
Fig 1.34.3: RY/BY status flag _____
RY/BY signal status bit
391 11th line of Block Erase Command (2016/D016)
_____
and Fig 1.34.4: RY/BY status flag _____
RY/BY signal status bit
392 _____
Fig 1.34.5: RY/BY status flag _____
RY/BY signal status bit
400 3rd paragraph, 1st line
....., set the CLK1 pin to “H” level and.... ....., set the CLK1 pin to “H” level and the TxD1 pin to
“L” level, and.....
400 3rd paragraph, 2nd line
The CLK1 pin is connected to Vcc.....resistance. Add
401 P67 When using standard.....transfer. Add
419 Fig 1.35.22, Data output Pulled down
421 How frequency is identified, 2nd line: (2 - 20MHz) (2 - 30MHz)
Keep safety first in your circuit designs!
Notes regarding these materials
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
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MITSUBISHI SEMICONDUCTORS
M32C/83 Group DATA SHEET REV. B2
February First Edition 2002
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©2002 MITSUBISHI ELECTRIC CORPORATION
