SLVS522D − JULY 2004 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoFreeWafer Chip Scale Packages
DOutput Tolerance of
− 1% (A Grade)
− 1.5% (Standard Grade)
DUltra-Low Dropout, Typically
− 280 mV at Full Load of 150 mA
− 7 mV at 1 mA
DWide VIN Range
− 16 V Max (DBV Package)
− 12 V Max (YZQ/YZU Package)
DLow IQ... 850 µA at Full Load at 150 mA
DShutdown Current...0.01 µA Typ
DLow Noise ...30 µVRMS With 10-nF Bypass
Capacitor
DStable With Low-ESR Capacitors, Including
Ceramic
DOvercurrent and Thermal Protection
DHigh Peak-Current Capability
DPortable Applications
− Cellular Phones
− Palmtop and Laptop Computers
− Personal Digital Assistants (PDAs)
− Digital Cameras and Camcorders
− CD Players
− MP3 Players
DBV (SOT-23) PACKAGE
(TOP VIEW)
1
2
3
5
4
VIN
GND
ON/OFF
VOUT
BYPASS
VOUT
YZQ OR YZU (WCSP) PACKAGE
(TOP VIEW)
B2
C1
C3
A1A3
VIN
ON/OFF
BYPASS
GND
description/ordering information
The LP2985 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for
both portable and nonportable applications. Available in voltages of 1.25 V, 1.5 V, 1.8 V, 2.5 V, 2.8 V, 2.85 V,
3 V, 3.1 V, 3.3 V, and 5 V, the family has an output tolerance of 1% for the A version (1.5% for the non-A version)
and is capable of delivering 150-mA continuous load current. Standard regulator features, such as overcurrent
and overtemperature protection, are included.
The LP2985 has a host of features that makes the regulator an ideal candidate for a variety of portable
applications:
•Low dropout: A PNP pass element allows a typical dropout of 280 mV at 150-mA load current and 7 mV
at 1-mA load.
•Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are
considerably lower than those associated with traditional lateral PNP regulators.
•Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the
ON/OFF pin is pulled low.
•Low-ESR-capacitor friendly: The regulator is stable with low-ESR capacitors, allowing the use of small,
inexpensive, ceramic capacitors in cost-sensitive applications.
•Low noise: A BYPASS pin allows for low-noise operation, with a typical output noise of 30 µV (RMS),
with the use of a 10-nF bypass capacitor.
•Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package,
as well as NanoFree wafer chip scale packaging, of fering an even smaller size with improved thermal
and electrical characteristics. NanoFree package technology is a major breakthrough in IC packaging
concepts, using the die as the package.
Copyright 2005, Texas Instruments Incorporated
NanoFree and NanoStar are trademarks of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
SLVS522D − JULY 2004 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TJPART
GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
1.25 V
Reel of 3000 LP2985A-125DBVR
PREVIEW
1.25 V Reel of 250 LP2985A-125DBVT
PREVIEW
1.5 V
Reel of 3000 LP2985A-15DBVR
PREVIEW
1.5 V Reel of 250 LP2985A-15DBVT
PREVIEW
1.8 V
Reel of 3000 LP2985A-18DBVR
PREVIEW
1.8 V Reel of 250 LP2985A-18DBVT
PREVIEW
2.5 V
Reel of 3000 LP2985A-25DBVR
PREVIEW
2.5 V Reel of 250 LP2985A-25DBVT
PREVIEW
A grade:
2.8 V
Reel of 3000 LP2985A-28DBVR
LPJ_
A grade:
1% tolerance
2.8 V
SOT-23-5 (DBV)
Reel of 250 LP2985A-28DBVT LPJ_
1% tolerance
2.85 V
SOT-23-5 (DBV) Reel of 3000 LP2985A-285DBVR
PREVIEW
2.85 V Reel of 250 LP2985A-285DBVT
PREVIEW
3 V
Reel of 3000 LP2985A-30DBVR
PREVIEW
3 V Reel of 250 LP2985A-30DBVT
PREVIEW
3.1 V
Reel of 3000 LP2985A-31DBVR
PREVIEW
3.1 V Reel of 250 LP2985A-31DBVT
PREVIEW
3.3 V
Reel of 3000 LP2985A-33DBVR
LPK_
3.3 V Reel of 250 LP2985A-33DBVT LPK_
5 V
Reel of 3000 LP2985A-50DBVR
PREVIEW
−40°C to 125°C
5 V Reel of 250 LP2985A-50DBVT
PREVIEW
−40°C to 125°C
1.25 V
Reel of 3000 LP2985-125DBVR
PREVIEW
1.25 V Reel of 250 LP2985-125DBVT
PREVIEW
1.5 V
Reel of 3000 LP2985-15DBVR
PREVIEW
1.5 V Reel of 250 LP2985-15DBVT
PREVIEW
1.8 V
Reel of 3000 LP2985-18DBVR
PREVIEW
1.8 V Reel of 250 LP2985-18DBVT
PREVIEW
2.5 V
Reel of 3000 LP2985-25DBVR
PREVIEW
2.5 V Reel of 250 LP2985-25DBVT
PREVIEW
Standard
2.8 V
Reel of 3000 LP2985-28DBVR
LPG_
Standard
grade: 1.5%
2.8 V
SOT-23-5 (DBV)
Reel of 250 LP2985-28DBVT LPG_
grade: 1.5%
tolerance
2.85 V
SOT-23-5 (DBV) Reel of 3000 LP2985-285DBVR
PREVIEW
tolerance
2.85 V Reel of 250 LP2985-285DBVT
PREVIEW
3 V
Reel of 3000 LP2985-30DBVR
PREVIEW
3 V Reel of 250 LP2985-30DBVT
PREVIEW
3.1 V
Reel of 3000 LP2985-31DBVR
PREVIEW
3.1 V Reel of 250 LP2985-31DBVT
PREVIEW
3.3 V
Reel of 3000 LP2985-33DBVR
LPF_
3.3 V Reel of 250 LP2985-33DBVT LPF_
5 V
Reel of 3000 LP2985-50DBVR
PREVIEW
5 V Reel of 250 LP2985-50DBVT
PREVIEW
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV: The actual top-side marking has one additional character that designates the assembly/test site.
SLVS522D − JULY 2004 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART
GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
1.25 V LP2985A-125YZQR
1.5 V LP2985A-15YZQR
1.8 V LP2985A-18YZQR
2.5 V
NanoFree − WCSP
LP2985A-25YZQR
2.8 V NanoFree − WCSP
0.17-mm Bump
Reel of 3000
LP2985A-28YZQR
PREVIEW
2.85 V
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000 LP2985A-285YZQR
PREVIEW
3 V
(YZQ, Pb-free)
LP2985A-30YZQR
3.1 V LP2985A-31YZQR
3.3 V LP2985A-33YZQR
A grade:
5 V LP2985A-50YZQR
A grade:
1% tolerance 1.25 V LP2985A-125YZUR
1% tolerance
1.5 V LP2985A-15YZUR
1.8 V LP2985A-18YZUR
2.5 V
NanoFree − WCSP
LP2985A-25YZUR
2.8 V NanoFree − WCSP
0.30-mm Bump
Reel of 3000
LP2985A-28YZUR
PREVIEW
2.85 V
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000 LP2985A-285YZUR
PREVIEW
3 V
(YZU, Pb-free)
LP2985A-30YZUR
3.1 V LP2985A-31YZUR
3.3 V LP2985A-33YZUR
−40°C to 125°C
5 V LP2985A-50YZUR
−40
°
C to 125
°
C
1.25 V LP2985-125YZQR
1.5 V LP2985-15YZQR
1.8 V LP2985-18YZQR
2.5 V
NanoFree − WCSP
LP2985-25YZQR
2.8 V NanoFree − WCSP
0.17-mm Bump
Reel of 3000
LP2985-28YZQR
PREVIEW
2.85 V
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000 LP2985-285YZQR
PREVIEW
3 V
(YZQ, Pb-free)
LP2985-30YZQR
3.1 V LP2985-31YZQR
Standard
3.3 V LP2985-33YZQR
Standard
grade: 1.5%
5 V LP2985-50YZQR
grade: 1.5%
tolerance
1.25 V LP2985-125YZUR
tolerance
1.5 V LP2985-15YZUR
1.8 V LP2985-18YZUR
2.5 V
NanoFree − WCSP
LP2985-25YZUR
2.8 V NanoFree − WCSP
0.30-mm Bump
Reel of 3000
LP2985-28YZUR
PREVIEW
2.85 V
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000
LP2985-285YZUR
PREVIEW
3 V
(YZU, Pb-free)
LP2985-30YZUR
3.1 V LP2985-31YZUR
3.3 V LP2985-33YZUR
5 V LP2985-50YZUR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡YZQ/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character
to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
SLVS522D − JULY 2004 − REVISED APRIL 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
VIN
VOUT
ON/OFF
Overcurrent/
Overtemperature
Protection
VREF 1.23 V −
+
BYPASS
basic application circuit
VOUT
2.2 µF†
10 nF§
1 µF†
VIN 1
ON/OFF‡
†Minimum COUT value for stability (can be increased without limit for improved stability and transient response)
‡ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used.
§Optional BYPASS capacitor for low-noise operation
2GND
3
5
4BYPASS
LP2985A-xxDBVR
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)†
Continuous input voltage range, VIN:DBV package −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YZQ/YZU package −0.3 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON/OFF input voltage range, VON/OFF:DBV package −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YZQ/YZU package −0.3 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (see Note 1) −0.3 V to 9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/output voltage differential range, VIN-VOUT (see Note 2):DBV package −0.3 V to 16 V. . . . . . . . . . . . .
YZQ/YZU package −0.3 V to 12 V. . . . . . . . .
Output current, IO (see Note 3) Internally limited (short-circuit protected). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 3 and 4): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . .
YZQ package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . .
YZU package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. If load is returned to a negative power supply in a dual-supply system, the output must be diode clamped to GND.
2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode normally is reverse biased
(VIN > VOUT), but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information
for more details).
3. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN MAX UNIT
VIN
Supply input voltage
DBV package 2.2†16
V
VIN Supply input voltage YZQ/YZU package 2.2†12 V
VON/OFF ON/OFF input voltage 0 VIN V
IOUT Output current 150 mA
TJVirtual junction temperature −40 125 °C
‡Recommended minimum VIN is the greater of:
a) 2.5 V or
b) VOUT(max) + rated dropout voltage (max) for operating IL
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified virtual junction temperature range,
VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V , CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ
LP2985A-XX LP2985-XX
UNIT
PARAMETER
TEST CONDITIONS
TJMIN TYP MAX MIN TYP MAX
UNIT
IL = 1 mA 25°C −1 1 −1.5 1.5
Output voltage
1 mA ≤IL ≤ 50 mA
25°C −1.5 1.5 −2.5 2.5
nV
OUT
Output voltage
tolerance
1 mA ≤IL ≤ 50 mA −40°C to 125°C −2.5 2.5 −3.5 3.5 %V
NOM
nVOUT
tolerance
1 mA ≤IL ≤ 150 mA
25°C −2.5 2.5 −3.0 3.0
%VNOM
1 mA ≤IL ≤ 150 mA −40°C to 125°C −3.5 3.5 −4.0 4.0
Line regulation
DBV package: VIN =
[VOUT(NOM) + 1 V] to 16 V
25°C 0.007 0.014 0.007 0.014
%/V
Line regulation
[VOUT(NOM) + 1 V] to 16 V
YZQ/YZU package: VIN =
[V
OUT(NOM)
+ 1 V] to 12 V −40°C to 125°C 0.032 0.032 %/V
IL = 0
25°C 1 3 1 3
IL = 0 −40°C to 125°C 5 5
IL = 1 mA
25°C 7 10 7 10
IL = 1 mA −40°C to 125°C 15 15
VIN-VOUT
Dropout voltage
IL = 10 mA
25°C 40 60 40 60
mV
VIN-VOUT
Dropout voltage
(see Note 5) IL = 10 mA −40°C to 125°C 90 90 mV
(see Note 5)
IL = 50 mA
25°C 120 150 120 150
IL = 50 mA −40°C to 125°C 225 225
IL = 150 mA
25°C 280 350 280 350
IL = 150 mA −40°C to 125°C 575 575
IL = 0
25°C 65 95 65 95
IL = 0 −40°C to 125°C 125 125
IL = 1 mA
25°C 75 110 75 110
IL = 1 mA −40°C to 125°C 170 170
IL = 10 mA
25°C 120 220 120 220
IL = 10 mA −40°C to 125°C 400 400
I
GND
Ground pin curren
t
IL = 50 mA
25°C 350 600 350 600 µA
IGND
Ground pin current
IL = 50 mA −40°C to 125°C 1000 1000
µA
IL = 150 mA
25°C 850 1500 850 1500
IL = 150 mA −40°C to 125°C 2500 2500
VON/OFF < 0.3 V (OFF) 25°C 0.01 0.8 0.01 0.8
VON/OFF 0.15 V (OFF)
−40°C to 105°C 0.05 2 0.05 2
VON/OFF < 0.15 V (OFF
)
−40°C to 125°C 5 5
ON/OFF input
VON/OFF = HIGH
!25°C 1.4 1.4
VON/OFF
ON/OFF input
voltage
VON/OFF = HIGH !
O/P ON −40°C to 125°C 1.6 1.6
V
VON/OFF
voltage
(see Note 6)
VON/OFF = LOW
!25°C 0.55 0.55 V
(see Note 6)
VON/OFF = LOW !
O/P OFF −40°C to 125°C 0.15 0.15
VON/OFF = 0
25°C 0.01 0.01
ION/OFF
ON/OFF input
VON/OFF = 0 −40°C to 125°C −2 −2
µA
I
ON/OFF
ON/OFF input
current
VON/OFF = 5 V
25°C 5 5 µ
A
current
V
ON/OFF
= 5 V
−40°C to 125°C 15 15
NOTES: 5. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value
measured with a 1-V differential.
6. The ON/OFF input must be driven properly for reliable operation (see Application Information).
SLVS522D − JULY 2004 − REVISED APRIL 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified virtual junction temperature range,
VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V , CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted)
(continued)
PARAMETER
TEST CONDITIONS
TJ
LP2985A-XX LP2985-XX
UNIT
PARAMETER
TEST CONDITIONS
TJMIN TYP MAX MIN TYP MAX
UNIT
VnOutput noise
(RMS)
BW = 300 Hz to 50 kHz,
COUT = 10 µF,
CBYPASS = 10 nF 25°C 30 30 µV
nVOUT/nVIN Ripple
rejection
f = 1kHz,
COUT = 10 µF,
CBYPASS = 10 nF 25°C 45 45 dB
IOUT(PK) Peak output
current VOUT ≥VO(NOM) − 5% 25°C 350 350 mA
IOUT(SC) Short-circuit
current RL = 0 (steady state)
(see Note 7) 25°C 400 400 mA
NOTE 7: See Figure 6 under typical performance characteristics.
SLVS522D − JULY 2004 − REVISED APRIL 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitors
input capacitor (Cin)
A minimum value of 1 F (over the entire operating temperature range) is required at the input of the LP2985.
In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog
ground. There are no Equivalent Series Resistance (ESR) requirements for this capacitor, and the capacitance
can be increased without limit.
output capacitor (Cout)
As an advantage over other regulators, the LP2985 permits the use of low-ESR capacitors at the output,
including ceramic capacitors that can have an ESR as low as 5 mΩ. Tantalum and film capacitors also can be
used if size and cost are not issues. The output capacitor also should be located within 1 cm of the output pin
and be returned to a clean analog ground.
As with other PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and
an ESR that falls within a certain range.
Minimum Cout: 2.2 µF (can be increased without limit to improve transient response stability margin)
ESR range: see Figure 1
ESR − Ω
Load Current − mA
Figure 1. 2.2-V/3.3-µF ESR Curves
It is critical that both the minimum capacitance and ESR requirement be met over the entire operating
temperature range. Depending on the type of capacitors used, both these parameters can vary significantly with
temperature (see capacitor characteristics).
noise bypass capacitor (Cbypass)
The LP2985 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal
bandgap reference via the BYPASS pin. This high-impedance bandgap circuitry is biased in the microampere
range and, thus, cannot be loaded significantly, otherwise, its output − and, correspondingly, the output of the
regulator − will change. Thus, for best output accuracy, dc leakage current through Cbypass should be minimized
as much as possible and never should exceed 100 nA.
A 10-nF capacitor is recommended for Cbypass; ceramic and film capacitors are well suited for this purpose.
SLVS522D − JULY 2004 − REVISED APRIL 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitor characteristics
ceramics
Ceramic capacitors are ideal choices for use on the output of the LP2985 for several reasons. For capacitances
in the range of 2.2 µF to 4.7 µF, ceramic capacitors have the lowest cost and the lowest ESR, making them
choice candidates for filtering high-frequency noise. For instance, a typical 2.2-µF ceramic capacitor has an
ESR in the range of 10 mΩ to 20 mΩ and, thus, satisfies minimum ESR requirements of the regulator.
Ceramic capacitors have one glaring disadvantage that must be taken into account − a poor temperature
coefficient, where the capacitance can vary significantly with temperature. For instance, a large-value ceramic
capacitor ( ≥2.2 µF) can lose more than half of its capacitance as the temperature rises from 25°C to 85°C. Thus,
a 2.2-µF capacitor at 25°C will drop well below the minimum Cout required for stability, as ambient temperature
rises. For this reason, select an output capacitor that maintains the minimum 2.2 µF required for stability over
the entire operating temperature range. Note that there are some ceramic capacitors that can maintain a ±15%
capacitance tolerance over temperature.
tantalum
Tantalum capacitors can be used at the output of the LP2985, but there are significant disadvantages that could
prohibit their use:
•In the 1-µF to 4.7-µF range, tantalum capacitors are more expensive than ceramics of the equivalent
capacitance and voltage ratings.
•Tantalum capacitors have higher ESRs than their equivalent-sized ceramic counterparts. Thus, to meet
the ESR requirements, a higher-capacitance tantalum may be required, at the expense of larger size
and higher cost.
•The ESR of a tantalum capacitor increases as temperature drops, as much as double from 25°C to
−40°C. Thus, ESR margins must be maintained over the temperature range to prevent regulator
instability.
ON/OFF operation
The LP2985 allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤0.3 V) turns the device
OFF; conversely, a HIGH (≥1.6 V) turns the device ON. If the shutdown feature is not used, ON/OFF should be
connected to the input to ensure that the regulator is on at all times. For proper operation, do not leave ON/OFF
unconnected, and apply a signal with a slew rate of ≥40 mV/µs.
SLVS522D − JULY 2004 − REVISED APRIL 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
reverse input-output voltage
There is an inherent diode present across the PNP pass element of the LP2985.
VOUT
VIN
With the anode connected to the output, this diode is reverse biased during normal operation, since the input
voltage is higher than the output. However, if the output is pulled higher than the input for any reason, this diode
is forward biased and can cause a parasitic silicon-controlled rectifier (SCR) to latch, resulting in high current
flowing from the output to the input. Thus, to prevent possible damage to the regulator in any application where
the output may be pulled above the input, an external Schottky diode should be connected between the output
and input. With the anode on output, this Schottky limits the reverse voltage across the output and input pins
to 0.3 V, preventing the regulator’s internal diode from forward biasing.
VOUT
VIN
Schottky
LP2985
SLVS522D − JULY 2004 − REVISED APRIL 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
OUTPUT VOLTAGE
vs
TEMPERATURE
Figure 2
3.295
3.305
3.315
3.325
3.335
3.345
−50 −25 0 25 50 75 100 125 15
0
Output Voltage − V
VI = 4.3 V
VO = 3.3 V
Ci = 1 µF
Co = 4.7 µF
IO = 1 mA
Temperature − °CFigure 3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
−50 −25 0 25 50 75 100 125 15
0
DROPOUT VOLTAGE
vs
TEMPERATURE
VO = 3.3 V
Cbyp = 10 nF
Dropout − V
150 mA
50 mA
10 mA
1 mA
Temperature − °C
Figure 4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−500 0500 1000 1500 200
0
Time − ms
Short-Circuit Current − A
SHORT-CIRCUIT CURRENT
vs
TIME
VI = 6 V
VO = 3.3 V
Ci = 1 µF
Cbyp = 0.01 µF
−100 100 300 500 700
Time − ms
Figure 5
SHORT-CIRCUIT CURRENT
vs
TIME
VI = 16 V (12 V for YZQ/YZU package)
VO = 3.3 V
Ci = 1 µF
Cbyp = 0.01 µF
Short-Circuit Current − A
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
SLVS522D − JULY 2004 − REVISED APRIL 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
200
220
240
260
280
300
320
0 0.5 1 1.5 2 2.5 3 3
.5
Output Voltage − V
Figure 6
SHORT-CIRCUIT CURRENT
vs
OUTPUT VOLTAGE
I
SC
− mA
VO = 3.3 V
Figure 7
GROUND-PIN CURRENT
vs
LOAD CURRENT
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
020 40 60 80 100 120 140
Load Current − mA 16
0
VO = 3.3 V
Cbyp = 10 nF
Ground Pin Current − µA
0
10
20
30
40
50
60
70
80
90
100
10 100 1K 10K 100K 1M
Frequency − Hz
Ripple Rejection − dB
Figure 8
RIPPLE REJECTION
vs
FREQUENCY
VI = 5 V
VO = 3.3 V
Co = 10 µF
Cbyp = 0 nF
50 mA
150 mA
1 mA
0
10
20
30
40
50
60
70
80
90
100
10 100 1K 10K 100K 1
M
Frequency − Hz
Ripple Rejection − dB
Figure 9
RIPPLE REJECTION
vs
FREQUENCY
50 mA
150 mA
1 mA
VI = 3.7 V
VO = 3.3 V
Co = 10 µF
Cbyp = 0 nF
SLVS522D − JULY 2004 − REVISED APRIL 2005
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
0
10
20
30
40
50
60
70
80
90
100
10 100 1K 10K 100K 1M
Frequency − Hz
Ripple Rejection − dB
Figure 10
RIPPLE REJECTION
vs
FREQUENCY
VI = 5 V
VO = 3.3 V
Co = 4.7 µF
Cbyp = 10 nF
50 mA
150 mA
1 mA
0
10
20
30
40
50
60
70
80
90
100
10 100 1K 10K 100K 1M
Frequency − Hz
Ripple Rejection − dB
Figure 11
RIPPLE REJECTION
vs
FREQUENCY
VI = 5 V
VO = 3.3 V
Co = 4.7 µF
Cbyp = 10 nF
10 mA
100 mA
1 mA
0.001
0.01
0.1
1
10
10 100 1K 10K 100K 1M
Frequency − Hz
Figure 12
OUTPUT IMPEDANCE
vs
FREQUENCY
Ci = 1 µF
Co = 10 µF
VO = 3.3 V
10 mA
100 mA
1 mA
Output Impedance − Ω
OUTPUT IMPEDANCE
vs
FREQUENCY
Figure 13
0.001
0.01
0.1
1
10
10 100 1K 10K 100K 1M
Frequency − Hz
Ci = 1 µF
Co = 4.7 µF
VO = 3.3 V
10 mA
100 mA
1 mA
Output Impedance − Ω
SLVS522D − JULY 2004 − REVISED APRIL 2005
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
Figure 14
OUTPUT NOISE DENSITY
vs
FREQUENCY
0.01
0.1
1
10
0.1 1 10 100
Frequency − kHz
Noise Density − nV/
Cbyp = 1 nF
Cbyp = 10 nF
Cbyp = 100 nF
ILOAD = 150 mA
Hz
OUTPUT NOISE DENSITY
vs
FREQUENCY
0.01
0.1
1
10
0.1 1 10 100
Frequency − kHz
Noise Density − nV/
Figure 15
ILOAD = 1 mA
Cbyp = 1 nF
Cbyp = 10 nF
Cbyp = 100 nF
Hz
Figure 16
INPUT CURRENT
vs
INPUT VOLTAGE
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
012345
6
Input Voltage − V
Input Current − mA
RL = Open
RL = 3.3 kΩ
VO = 3.3 V
Cbyp = 10 nF
0
200
400
600
800
1000
1200
1400
−50 −25 0 25 50 75 100 125 15
0
Ground Current − C
0 mA
Figure 17
GROUND-PIN CURRENT
vs
TEMPERATURE
Temperature − °C
150 mA
50 mA
10 mA
1 mA
VO = 3.3 V
Cbyp = 10 nF
SLVS522D − JULY 2004 − REVISED APRIL 2005
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
Output Voltage − V
−250
−200
−150
−100
−50
0
50
100
150
200
Load Current − mA
20 µs/div"
Figure 18
LOAD TRANSIENT RESPONSE
VO = 3.3 V
Cbyp = 10 nF
∆IL = 100 mA
IL
VO
Figure 19
LOAD TRANSIENT RESPONSE
Output Voltage − V
Load Current − mA
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
−250
−200
−150
−100
−50
0
50
100
150
200
VO = 3.3 V
Cbyp = 10 nF
∆IL = 150 mA
IL
VO
20 µs/div"
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
−250
−200
−150
−100
−50
0
50
100
150
200
Figure 20
LOAD TRANSIENT RESPONSE
Output Voltage − V
Load Current − mA
IL
VO
VO = 3.3 V
Cbyp = 0 nF
∆IL = 150 mA
20 µs/div"
Figure 21
3.27
3.29
3.31
3.33
3.35
3.37
3.39
3.41
2
2.5
3
3.5
4
4.5
5
5.5
VI
VO
LINE TRANSIENT RESPONSE
Output Voltage − V
Input Voltage − V
20 µs/div"
VO = 3.3 V
Cbyp = 0 nF
IO = 150 mA
SLVS522D − JULY 2004 − REVISED APRIL 2005
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
Figure 22
LINE TRANSIENT RESPONSE
Output Voltage − V
3.27
3.29
3.31
3.33
3.35
3.37
3.39
3.41
2
2.5
3
3.5
4
4.5
5
5.5
VO = 3.3 V
Cbyp = 10 nF
IO = 150 mA
Input Voltage − V
VI
VO
20 µs/div"
Figure 23
LINE TRANSIENT RESPONSE
Output Voltage − V
3.27
3.29
3.31
3.33
3.35
3.37
3.39
3.41
2
2.5
3
3.5
4
4.5
5
5.5
VO = 3.3 V
Cbyp = 0 nF
IO = 1 mA
Input Voltage − V
VI
VO
20 µs/div"
3.27
3.29
3.31
3.33
3.35
3.37
3.39
3.41
2
2.5
3
3.5
4
4.5
5
5.5
Figure 24
LINE TRANSIENT RESPONSE
Output Voltage − V
VO = 3.3 V
Cbyp = 10 nF
IO = 1 mA
Input Voltage − V
VIN
VO
100 µs/div"
0
2
4
6
8
10
−4
−3
−2
−1
0
1
2
3
4
Figure 25
TURN-ON TIME
Output Voltage − V
VON/OFF − V
VO
VON/OFF
100 µs/div"
VO = 3.3 V
Cbyp = 0
IO = 150 mA
SLVS522D − JULY 2004 − REVISED APRIL 2005
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL PERFORMANCE CHARACTERISTICS
CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN
(unless otherwise specified)
−4
−3
−2
−1
0
1
2
3
4
0
2
4
6
8
10
Figure 26
TURN-ON TIME
Output Voltage − V
VON/OFF − V
VO
VON/OFF
200 µs/div"
VO = 3.3 V
Cbyp = 100 pF
ILOAD = 150 mA
−4
−3
−2
−1
0
1
2
3
4
0
2
4
6
8
10
Figure 27
TURN-ON TIME
Output Voltage − V
VON/OFF − V
VO
VON/OFF
2 ms/div"
VO = 3.3 V
Cbyp = 1 nF
ILOAD = 150 mA
Figure 28
TURN-ON TIME
Output Voltage − V
−4
−3
−2
−1
0
1
2
3
4
0
2
4
6
8
10
VON/OFF − V
Input
Output
VO = 3.3 V
Cbyp = 10 nF
ILOAD = 150 mA
20 ms/div"
SLVS522D − JULY 2004 − REVISED APRIL 2005
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WAFER CHIP SCALE INFORMATION
LP2985x-xxYZQ NanoFree (0.17-mm Pb-Free Bump)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStart package configuration
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
1,287
1,337
Pin A1 Index Area 0,19
0,15
0,15
0,10
987
1,037
0,625 Max
SLVS522D − JULY 2004 − REVISED APRIL 2005
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WAFER CHIP SCALE INFORMATION
LP2985x-xxYZU NanoFree (0.30-mm Pb-Free Bump)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
1,287
1,337
Pin A1 Index Area 0,35
0,25
0,30
0,20
987
1,037
0,75 Max
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