HEF4020BT,652 - NXP - Pdf.Support

1. General description

The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and twelve fully bu ffered outputs (Q0, and Q3 to

Q13). The counter advances on the HIGH to LOW tr ansition of CP . A HIGH on MR clears

all counter stages and forces all outputs LOW, independent of the state of CP. Each

counter stage is a static toggle flip-flop. A feature of the device is its high speed

(typ. 35 MHz at VDD =15V).

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

High speed opera tio n

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +85 C

Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4020B

14-stage binary counter

Rev. 8 — 18 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4020BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4020BT SO16 plastic small outline package; 16 leads; bo dy width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 18 November 2011 2 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

4. Functional diagram

Fig 1. Functiona l di agram

001aad722

14-STAGE COUNTER

Q10

Q11

Q12

Q13

11 T

Fig 2. Logic symbol Fig 3. IEC Logic symbol

001aad723

Q0 9

11 MR

10 CP

Q3 7

Q4 5

Q5 4

Q6 6

Q7 13

Q8 12

Q9 14

Q10 15

Q11 1

Q12 2

Q13 3

001aad724

11 CT

CTR14

13 3

Fig 4. Logic di ag ra m

001aad725

RD Q

Q10

Q11

Q12

Q13

Product data sheet Rev. 8 — 18 November 2011 3 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition.

Fig 5. Pin configurat io n

HEF4020B

Q11 V

Q12 Q10

Q13 Q9

Q5 Q7

Q4 Q8

Q6 MR

Q3 CP

001aaj101

Table 2. Pin description

Symbol Pin Description

Q3 to Q13 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 parallel output (Q3 to Q13)

VSS 8 ground supply voltage

Q0 9 parallel output

CP 10 clock input (HIGH-to-LOW edge triggered)

MR 11 master reset input (active HIGH)

VDD 16 supply voltage

Table 3. Functional table[1]

Input Output

CP MR Q0, Q3 to Q13

L no change

L count

XHL

Product data sheet Rev. 8 — 18 November 2011 4 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Fig 6. Timi ng diagram

001aad726

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

CP input

MR input

Q10

Q11

8192 16384

Q12

Q13

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5V or V

I>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping curre nt VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +85 C

Ptot total power dissipation Tamb 40 C to +85 C

DIP16 package [1] - 750 mW

SO16 package [2] - 500 mW

P power dissipation per output - 100 mW

Product data sheet Rev. 8 — 18 November 2011 5 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +85 C

t/V input transition rise and fall rate VDD = 5 V --3.75s/V

VDD = 10 V --0.5s/V

VDD = 15 V --0.08s/V

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage IO < 1 A 5 V -1.5-1.5-1.5V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4. 95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA

VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA

VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA

VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A

10 V - 40 - 40 - 300 A

15 V - 80 - 80 - 600 A

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 8 — 18 November 2011 6 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

10. Dynamic characteristics

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25



C; for test circuit see Figure 8.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP to Q0;

see Figure 7 5 V 78 ns + (0.55 ns/pF)CL-105210ns

10 V 34 ns + (0.23 ns/pF)CL- 4590ns

15 V 22 ns + (0.16 ns/pF)CL- 3065ns

Qn to Qn + 1 5 V 53 ns + (0.55 ns/pF)CL- 80 160 ns

10 V 19 ns + (0.23 ns/pF)CL- 3060ns

15 V 12 ns + (0.16 ns/pF)CL- 2040ns

MR to Qn;

see Figure 7 5 V 153 ns + (0.55 ns/pF)CL-180360ns

10 V 79 ns + (0.23 ns/pF)CL- 90 180 ns

15 V 62 ns + (0.16 ns/pF)CL- 70 140 ns

tPLH LOW to HIGH

propagation delay CP to Q0;

see Figure 7 5 V 78 ns + (0.55 ns/pF)CL-105210ns

10 V 39 ns + (0.23 ns/pF)CL- 5095ns

15 V 27 ns + (0.16 ns/pF)CL- 3570ns

Qn to Qn + 1 5 V 43 ns + (0.55 ns/pF)CL- 70 140 ns

10 V 14 ns + (0.23 ns/pF)CL- 2550ns

15 V 12 ns + (0.16 ns/pF)CL- 2040ns

tttransition time see Figure 7 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL- 3060ns

15 V 6 ns + (0.28 ns/pF)CL- 2040ns

tWpulse width CP = HIGH;

minimum width;

see Figure 7

5 V 50 25 - ns

10 V 25 15 - ns

15 V 20 10 - ns

MR = HIGH;

minimum width;

see Figure 7

5 V 130 65 - ns

10 V 95 50 - ns

15 V 90 45 - ns

trec recovery time MR input;

see Figure 7 5 V 115 60 - ns

10 V 65 35 - ns

15 V 55 25 - ns

fmax maximum

frequency see Figure 7 5 V 5 10 - MHz

10 V 13 25 - MHz

15 V 18 35 - MHz

Product data sheet Rev. 8 — 18 November 2011 7 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

11. Waveforms

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula for PD (W) where:

PDdynamic power

dissipation 5V P

D = 600  fi + (fo  CL)  VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

(fo  CL) = sum of the outputs.

10 V PD = 2800  fi + (fo  CL)  VDD2

15 V PD = 8200  fi + (fo  CL)  VDD2

Measurement points are given in Table 9.

Fig 7. Propaga tion delay s, minimum puls e widths, transition and recovery times and maximum clock frequency

MR INPUT

Q0 or Qn

OUTPUT

PHL

rec

1/f

max

001aae591

PLH

PHL

CP INPUT

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 8 — 18 November 2011 8 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

a. Input waveforms

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL= load capacitance including jig and probe capacitance.

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 8. Test circuit for measuring switching times

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD 20 ns 50 pF

Product data sheet Rev. 8 — 18 November 2011 9 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

12. Package outline

Fig 9. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 8 — 18 November 2011 10 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

Fig 10. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 18 November 2011 11 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4020B v.8 20111118 Product data sheet - HEF4020B v.7

Modifications: •Legal pages updated.

•Changes in “General description” and “Features and benefits”.

•Section “Applications” removed.

HEF4020B v.7 20111010 Product data sheet - HEF4020B v.6

HEF4020B v.6 20091127 Product data sheet - H EF4020B v.5

HEF4020B v.5 20090707 Product data sheet - HEF4020B v.4

HEF4020B v.4 20081204 Product data sheet - HEF40 20B_CNV v.3

HEF4020B_CNV v.3 19950101 Product specification - HEF4020B_CNV v.2

HEF4020B_CNV v.2 19950101 Produ ct specification - -

Product data sheet Rev. 8 — 18 November 2011 12 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information se e the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

14.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specifica tion.

Product data sheet Rev. 8 — 18 November 2011 13 of 14

NXP Semiconductors HEF4020B

14-stage binary counter

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product i s automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automo tive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

14.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4020B

14-stage binary counter

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 18 November 2011

Document iden tifier: HEF4020B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

16. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

15 Contact information. . . . . . . . . . . . . . . . . . . . . 13

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14