64K x 16 Static RAM
CY62127BV
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 14, 2000
Features
• 2.7V–3.6V operation
• CMOS for optimum speed/power
• Low acti ve power (70 ns, LL ver sion)
— 54 m W ( max .) (1 5 mA)
• Low standby power (70 ns, LL version)
—54 µW (max.) (15 µA)
• A utomat ic power -down when deselected
—Power down either with CE or BHE and BLE HIGH
• Independent control of Upper and Lower Bytes
• Available in 44-pin TSOP II (forwar d) and fBGA
Functional Description
The CY62127BV is a high-performance CMOS Static RAM
organized as 65,536 words by 16 bits. This de vice has an au-
tomatic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH or wh en CE is LOW and
both BLE and BHE are HIGH .
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 th rough A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If By te Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O 8. If Byte High Enable (BHE) is
LO W, then data f rom memory will app ear on I /O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write m odes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs a re disabled (OE HIGH), the BHE and BLE
are di sabled (BHE, BLE HIGH), or during a write operation (CE
LO W, and WE LOW).
The CY62127BV is a vailab le in standard 44-pin TSOP Type II
(forward pinout) and fBGA pack ages.
Logic Block Diagram Pin Configurations
64K x 16
RAM Array I/O1–I/O8
ROW DECODER
A10
A9
A7
A6
A3
A0
COLUMN DECODER
A5
A8
A13
A14
A15
1024 X 1024
SENSE AMPS
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
A4
A11
A12
62127BV–1 62127BV–2
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top Vie w
TSOP II (For wa rd)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21 23
24 NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
CY62127BV
2
Maximum Ratings
(Above which the useful life may be impa ired. For use r gui de-
li nes, not tested.)
Storage Temperature ..... ..... .. .. ..... .......... ....–65°C to +15 0°C
Ambient Temperature with
Power Applied.............................................–55°C to +12 5°C
Supply Voltage on VCC to Relative GND[1] ....–0.5V to +4.6V
DC Voltage Appli ed to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Volt age[1].................................–0.5V to VCC + 0.5V
Cu r re n t in to Output s (L OW )........ .. .. ..... ... .. ..... .. ... ..... .. .. 20 mA
Static Discharge Voltage ...... .. .......... .. .. ..... ....... ........ >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current............... .. ..... .......... .. ..... ..... .. ..... . >200 mA
Notes:
1. VIL ( min.) = –2.0V f or puls e durat ions of les s than 20 ns.
2. TA is the “In st ant On” case temperat ure .
Pin Configurations (continued)
fBGA
Selection Guide 62127BV-55 62127BV-70 Units
Maximum Access Time 55 70 ns
Maximum Operating Current 20 15 mA
Maximum CMOS Standby Current 15 15 µA
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O11
I/O9
I/O10
A4
A5
I/O12
I/O14
I/O13
I/O15
I/O16
VSS
A9
A8
OE
VSS
A7
I/O1
BHE
NC
NC
A2
A1
BLE
VCC
I/O3
I/O2
I/O4
I/O5
I/O6I/O7
I/O8
A15
A14
A13
A12
NC
NC
NC NC
62127BV–3
3
265
4
1
D
E
B
A
C
F
G
H
Operating Range
Range Ambient
Temperature[2] VCC
Industrial –40°C to +8 5 °C2.7V–3.6V
CY62127BV
3
Electrical Characteristics Over th e Ope rating Range
62127BV–55, 70
Parameter Description Test Conditions Min. Typ.[3] Max. Unit
VOH Out put HI GH Volt age VCC = Min., IOH = –1.0 mA 2.2 V
VOL Out put LOW Volt age VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC+
0.3 V
VIL Input LOW Voltage[1] –0.3 0.4 V
IIX Input Load Current GND ≤ VI ≤ VCC –1+1 µA
IOZ Out put Leakage Current GND ≤ VI ≤ VCC,
Output Disabled –1+1 µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
55 ns 20 mA
70 ns 15 mA
ISB1 Autom a ti c C E
Power-Down Current
—TTL Inputs
Max. VCC, CE ≥ VIH
VIN ≥ VIH or
VIN ≤ VIL, f = f MAX
2mA
ISB2 Autom a ti c C E
Power-Down Current
—CMOS Inputs
Max. VCC,
CE ≥ VCC – 0.3 V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0. 3V, f=0
0.5 15 µA
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 9pF
COUT Output Capacitance 9pF
AC Test Loads and Waveforms
Notes:
3. Typical specifications are the mean values measured over a l arge sample size across normal production process variations and are taken at nominal
conditions (TA = 25°C, V CC=3.0V). Pa rameters are guaranteed by design and characterization, and not 100% tested.
4. Tested initially and after any design or process changes that may affect these parameters.
62127BV-4
90%
10%
VCC
GND
90%
10%
ALL INPUT PUL SES
3.0V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.0V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R1 1076ΩΩ
R2
1262ΩR2
581Ω
Equiva lent to: THÉVENIN
EQUIVALENT 1.62V
R1 1076
1262Ω
Rise Time:
1 V/ns Fall Time
1 V/ns
CY62127BV
4
Switching Characteristics[5] Ov er the Operating Range
62127BV–55 62127BV–70
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Ad dress to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LO W to Low Z[7] 5 5 ns
tHZOE OE HIGH to High Z[6, 7] 20 25 ns
tLZCE CE LOW to Low Z[7] 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 20 25 ns
tPU CE LOW to P ower-Up 0 0ns
tPD CE HIGH to Po wer-Down 55 70 ns
tDBE By te Enable to Data Val id 55 70 ns
tLZBE Byte En a ble to LOW Z[7] 5 5 ns
tHZBE Byte Disable to HIGH Z [6, 7] 20 25 ns
WRITE CYCLE[8]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Ad dress Set-Up to Write End 45 60 ns
tHA Ad dress Hold fro m Write End 0 0ns
tSA Ad dress Set-Up to Write Start 0 0ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0ns
tLZWE WE HIGH to Lo w Z[7] 5 5 ns
tHZWE WE LOW to High Z[6, 7] 25 25 ns
tBW Byte Enable to End of Write 45 60 ns
Notes:
5. Test conditions assume signal tr ansition time of 5 ns or less, timing reference lev els of 1.5V, input pulse le vels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30 pF loa d capac itance.
6. tHZOE, tHZCE, tHZWE, and tHZBE are sp ecified with a load capac itance of 5 p F as i n part (b) of A C Test Loads . Tra nsitio n is meas ured ±500 mV from stead y-s tate voltage .
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZWE is less than tLZWE, and tHZBE is less than tLZBE, for any given device.
8. The internal write time of the memory i s defined by the ov erlap of CE LOW and WE LO W . CE and WE mu st be LO W to initiat e a write, and t he transition of any of these
signal s can terminate the w rite. The input d ata s et-up a nd hol d ti ming shoul d be refe renced to th e leadi ng e dge of the s ignal t hat t erminates the write. Re f er to truth ta ble f or
further conditi ons from B HE and BLE.
CY62127BV
5
Data Rete n ti o n C h ar acteristics (Ov er the Operati ng Range f or “L” and “LL” version only)
Parameter Description Conditions[9] Min. Typ Max. Unit
VDR VCC for Data Retention 2.0 3.6 V
ICCDR Data Rete nti on Current VCC = VDR = 2.0V,
CE > VCC-0.3V,
VIN > VCC - 0.3V or,
VIN < 0.3V.
0.5 15 µA
tCDR[4] Chip Deselect to Data Retention Time 0 ns
tROper ati on Recove ry Time tRC ns
Data Retention Waveform
Switching Wavef orms
Read Cycle No.1[10, 11]
Notes:
9. No input may exceed VCC + 0.3V.
10. Device is continuously selected. OE, CE, BHE, BLE = VIL.
11. WE is HIGH for read cycle .
62127BV–5
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62127BV-6
ADDRESS
DATA OUT
CY62127BV
6
Read Cycle No. 2 (OE Controlled)[11, 12, 13]
Write Cycle No. 1 (CE Controlled) [13, 14]
Notes:
12. Address valid prior to or coincident with CE tr ansitio n LO W.
13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH.
14. If CE, BHE, or BLE go HIGH s imult aneousl y with W E go ing HIGH, the o utput remain s in a hi gh-i mpedance sta te.
Switching Wavef orms (continued )
62127BV-7
50%
50%
DATA VAL ID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
V
OE
DATA OUT
CC
SUPPLY
CURRENT
BHE, BLE
ICC
ISB
HIGH
IMPEDANCE
ADDRESS
tLZBEtDBE tHZBE
CE
62127BV-8
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE
ADDRESS
WE
DATA I/O
BHE, BLE
tBW
CY62127BV
7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Wavef orms (continued )
62127BV-9
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE15
BHE, BLE tBW
62127BV-10
D ATA VAL ID
tHD
tSD
tLZWE
tPWE
tSA tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 15
BHE, BLE tBW
CY62127BV
8
Truth Ta ble
CE OE WE BLE BHE I/O1–I/O8I/O9–I/O16 Mode Power
H X X X X High Z High Z Power Down St a ndby (ISB)
L L H L L Data Out Data Out Re ad A ll B its Active (ICC)
L L H L H Data Out High Z Read Lower Bits On ly Active (ICC)
L L H H L High Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write Al l Bits Active (ICC)
L X L L H Data In High Z Write Lower Bits Only Active (ICC)
L X L H L High Z Data In Write Upper Bits Only Active (ICC)
L H H L L High Z High Z Selected, O u tp uts Dis a bled Active (ICC)
L X X H H High Z High Z Power Down St a ndby (ISB)
Ordering Information
Speed
(ns) Ordering Code Package
Name P ackage Type Operating
Range
55 CY62127BVLL-55ZI Z44 44-Lead TSOP II Industrial
CY62127BVLL-55BAI BA48 48-Ball Fine Pitch Ball Grid Array (fBGA)
70 CY62127BVLL-70ZI Z44 44-Lead TSOP II
CY62127BVLL-70BAI BA48 48-Ball Fine Pitch Ball Grid Array (fBGA)
Document #: 38-01018 -* *
CY62127BV
9
Package D i ag r ams
48-Ball (7. 00 mm x 7.00 mm) Fine Pitc h BGA BA48
51-85096-C
CY62127BV
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circu itry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or other rights . Cypr ess Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag r ams (conti nued)
44-Pin TSOP II Z44
51-85087-A
