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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

LM9061 and LM9061-Q1 High-Side Protection Controller

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device HBM ESD Classification Level 2

– Device CDM ESD Classification Level C4B

• Withstands 60-V Supply Transients

• Overvoltage Shut-OFF With VCC > 30 V

• Lossless Overcurrent Protection Latch-OFF

– Current Sense Resistor is Not Required

– Minimizes Power Loss With High Current

Loads

• Programmable Delay of Protection Latch-OFF

• Gradual Turnoff to Minimize Inductive Load

Transient Voltages

• CMOS Logic-Compatible ON and OFF Control

Input

2 Applications

• Transmission Control Units (TCU)

• Engine Control Units (ECU)

• Valve, Relay, and Solenoid Drivers

• Lamp Drivers

• DC Motor PWM Drivers

• Logic-Controlled Power Supply Distribution

Switches

• Electronic Circuit Breakers

• High-Power Audio Speakers

3 Description

The LM9061 family consists of charge-pump devices

which provides the gate drive to an external power

MOSFET of any size configured as a high-side driver

or switch. This includes multiple parallel connected

MOSFETs for very high current applications. A

CMOS logic-compatible ON and OFF input controls

the output gate drive voltage. In the ON state, the

charge pump voltage, which is well above the

available VCC supply, is directly applied to the gate of

the MOSFET. A built-in 15-V Zener clamps the

maximum gate to source voltage of the MOSFET.

When commanded OFF a 110-µA current sink

discharges the gate capacitances of the MOSFET for

a gradual turnoff characteristic to minimize the

duration of inductive load transient voltages and

further protect the power MOSFET.

Lossless protection of the power MOSFET is a key

feature of the LM9061. The voltage drop (VDS) across

the power device is continually monitored and

compared against an externally programmable

threshold voltage. A small current-sensing resistor in

series with the load, which causes a loss of available

energy, is not required for the protection circuitry. If

the VDS voltage, due to excessive load current,

exceeds the threshold voltage, the output is latched

OFF in a more gradual fashion (through a 10-µA

output current sink) after a programmable delay time

interval.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM9061, LM9061-Q1 SOIC (8) 4.9 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

High-Side Driving and Protection to a Connected Load

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings: LM9061 .............................................. 4

6.3 ESD Ratings: LM9061-Q1 ........................................ 4

6.4 Recommended Operating Conditions....................... 4

6.5 Thermal Information.................................................. 5

6.6 Electrical Characteristics........................................... 5

6.7 Switching Characteristics.......................................... 6

6.8 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 10

7.1 Overview................................................................. 10

7.2 Functional Block Diagram....................................... 10

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 20

8 Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Applications ................................................ 21

9 Power Supply Recommendations...................... 24

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Examples................................................... 25

11 Device and Documentation Support................. 26

11.1 Documentation Support ........................................ 26

11.2 Related Links ........................................................ 26

11.3 Receiving Notification of Documentation Updates 26

11.4 Community Resources.......................................... 26

11.5 Trademarks........................................................... 26

11.6 Electrostatic Discharge Caution............................ 26

11.7 Glossary................................................................ 26

12 Mechanical, Packaging, and Orderable

Information........................................................... 26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (January 2015) to Revision I Page

• Updated data sheet text to the latest TI documentation and translations standards and flow............................................... 1

• Added Bidirectional Applications section ............................................................................................................................. 23

Changes from Revision G (November 2014) to Revision H Page

• Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4

• Added content to Application and Implementation section................................................................................................... 21

• Changed Layout Example figure ......................................................................................................................................... 25

Changes from Revision F (April 1995) to Revision G Page

• Added AEC-Q100 Qualification ............................................................................................................................................. 1

• Added Handling Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,

Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 4

Changes from Revision E (April 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 19

1Sense 8 Delay

2Threshold 7 On/Off

3Ground 6 IREF

4Output 5 VCC

Not to scale

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5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

Sense 1 I The inverting input to the protection comparator, connected to the external MOSFET source pin and

the load.

Threshold 2 I The noninverting input to the protection comparator, and a current sink for the threshold resistor to

set the allowed voltage drop across the external MOSFET.

Ground 3 — Ground

Output 4 O The gate drive connection. Charges, and discharges, the MOSFET gate.

VCC 5 I The voltage supply pin. The VCC operating range has a minimum value of 7 V, and a maximum value

of 26 V.

IREF 6 O A resistor on this pin to ground sets the current through the threshold resistor, which sets the allowed

voltage drop across the external MOSFET.

On/Off 7 I The control pin. A low voltage, VIN(0), will disable device operation, while a high voltage, VIN(1), will

enable device operation.

Delay 8 O A capacitor on this pin to ground will provide a delay time between when the protection comparator

detects excessive VGS across the MOSFET and when the gate drive circuitry is latched-OFF.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions(). Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Supply voltage 60 V

Output voltage VCC + 15 V

Voltage at sense and threshold (through 1 kΩ)−25 60 V

ON/OFF input voltage −0.3 VCC + 0.3 V

Reverse supply current 20 mA

Junction temperature 150 °C

Lead temperature soldering, 10 seconds 260 °C

Storage temperature, Tstg −55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings: LM9061 VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings: LM9061-Q1 VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V

Charged-device model (CDM), per AEC

Q100-011 All pins except 1, 4, 5, and 8 ±1000

Pins 1, 4, 5, and 8 ±1000

(1) Operating Ratings indicate conditions for which the device is intended to be functional, but may not meet the ensured specific

performance limits. For ensured specifications and test conditions see the Typical Characteristics.

6.4 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Supply voltage 7 26 V

ON/OFF input voltage −0.3 VCC V

Ambient temperature: LM9061 −40 125 °C

Junction temperature: LM9061-Q1 −40 125 °C

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(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Thermal Information

THERMAL METRIC(1)

LM9061, LM9061-

Q1 UNIT

D (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 150 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 46.7 °C/W

RθJB Junction-to-board thermal resistance 49.1 °C/W

ψJT Junction-to-top characterization parameter 6.2 °C/W

ψJB Junction-to-board characterization parameter 48.4 °C/W

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

7 V ≤VCC ≤20 V, RREF = 15.4 kΩ,−40°C ≤TJ≤+125°C, unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY

IQQuiescent supply current ON/OFF = 0 5 mA

ICC Operating supply current ON/OFF = 1, CLOAD = 0.025 µF,

includes turnon

transient output current 40 mA

ON/OFF CONTROL INPUT

VIN(0) ON/OFF input logic 0 VOUT = OFF 1.5 V

VIN(1) ON/OFF input logic 1 VOUT = ON 3.5 V

VHYST ON/OFF input hysteresis Peak-to-peak 0.8 2 V

IIN ON/OFF input pulldown current VON/OFF = 5 V 50 250 µA

GATE DRIVE OUTPUT

VOH Charge pump output voltage ON/OFF = 1 VCC + 7 VCC + 15 V

VOL OFF output voltage ON/OFF = 0, ISINK = 110 µA 0.9 V

VCLAMP Sense to output

clamp voltage ON/OFF = 1,

VSENSE = VTHRESHOLD 11 15 V

ISINK(Normal-

OFF) Output sink current

normal operation ON/OFF = 0, VDELAY = 0 V,

VSENSE = VTHRESHOLD 75 145 µA

ISINK(Latch-OFF) Output sink current with

protection comparator tripped VDELAY = 7 V,

VSENSE < VTHRESHOLD 5 15 µA

PROTECTION CIRCUITRY

VREF Reference voltage 1.15 1.35 V

IREF Threshold pin reference current VSENSE = VTHRESHOLD 75 88 µA

ITHR(LEAKAGE) Threshold pin leakage current VCC = Open, 7 V ≤VTHRESHOLD ≤20

V10 µA

ISENSE Sense pin input bias current VSENSE = VTHRESHOLD 10 µA

DELAY TIMER

VTIMER Delay timer threshold voltage 5 6.2 V

VSAT Discharge transistor saturation

voltage IDIS = 1 mA 0.4 V

IDIS Delay capacitor discharge current VDELAY = 5 V 2 10 mA

IDELAY Delay pin source current 6.74 15.44 µA

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(1) The AC Timing specifications for TOFF are not production tested, and therefore are not specifically ensured. Limits are provided for

reference purposes only. Smaller load capacitances will have proportionally faster turn-ON and turn-OFF times.

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

7V ≤VCC ≤20V, RREF = 15.4 kΩ,−40°C ≤TJ≤+125°C, CLOAD = 0.025 µF, CDELAY = 0.022 µF, unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TON Output turnon time CLOAD = 0.025 µF

7V ≤VCC ≤10 V, VOUT ≥

VCC + 7 V 1.5 ms

10V ≤VCC ≤20 V, VOUT ≥

VCC + 11 V 1.5

TOFF(NORMAL) Output turnoff time,

normal operation(1) CLOAD = 0.025 µF

VCC = 14 V, VOUT ≥25 V

VSENSE = VTHRESHOLD 4 10 ms

TOFF(Latch-OFF) Output turnoff time,

protection comparator

tripped(1)

CLOAD = 0.025 µF

VCC = 14 V, VOUT ≥25 V

VSENSE = VTHRESHOLD 45 140 ms

TDELAY Delay timer interval CDELAY = 0.022 µF 8 18 ms

Figure 1. Typical Operating Waveforms

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Figure 2. Timing Definitions

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6.8 Typical Characteristics

Figure 3. Standby Supply Current vs VCC Figure 4. Operating Supply Current vs VCC

Figure 5. Output Voltage vs VCC Figure 6. Output Sink Current vs Temperature

Figure 7. Output Sink Current vs Temperature Figure 8. Output Source Current vs Output Voltage

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Typical Characteristics (continued)

Figure 9. Reference Voltage vs Temperature Figure 10. Delay Threshold vs Temperature

Figure 11. Delay Charge Current vs Temperature

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7 Detailed Description

7.1 Overview

The LM9061 is a high-side controller that can protect the load from overcurrent and overvoltage. An internal

charge pump circuit generates the gate voltage to drive the high-side MOSFET. The voltage drop, VDS, across

the MOSFET is monitored to protect from excessive current. If the VDS voltage, due to excessive load current,

exceed the threshold voltage, the output is latched OFF after a programmable delay time interval.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 MOSFET Gate Drive

The LM9061 contains a charge pump circuit that generates a voltage in excess of the applied supply voltage to

provide the gate drive to high-side MOSFET transistors. Any size of N-channel power MOSFET, including

multiple parallel connected MOSFETs for very high current applications, can be used to apply power to a ground

referenced load circuit in what is referred to as high-side drive applications. Figure 12 shows the basic

application of the LM9061.

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Feature Description (continued)

Figure 12. Basic Application Circuit

7.3.2 Basic Operation

When commanded ON by a logic 1 input to pin 7 the gate drive output, pin 4, rises quickly to the VCC supply

potential at pin 5. Once the gate voltage exceeds the gate-source threshold voltage of the MOSFET, VGS(ON),

(the source is connected to ground through the load) the MOSFET turns ON and connects the supply voltage to

the load. With the source at near the supply potential, the charge pump continues to provide a gate voltage

greater than the supply to keep the MOSFET turned ON. To protect the gate of the MOSFET, the output voltage

of the LM9061 is clamped to limit the maximum VGS to 15 V.

It is important to remember that during the Turnon of the MOSFET the output current to the Gate is drawn from

the VCC supply pin. The VCC pin must be bypassed with a capacitor with a value of at least 10 times the Gate

capacitance, and no less than 0.1 μF. The output current into the Gate will typically be 30 mA with VCC at 14 V

and the Gate at 0 V. As the Gate voltage rises to VCC, the output current decreases. When the Gate voltage

reaches VCC, the output current will typically be 1 mA with VCC at 14 V.

A logic 0 on pin 7 turns the MOSFET OFF. When commanded OFF a 110-µA current sink is connected to the

output pin. This current discharges the gate capacitances of the MOSFET linearly. When the gate voltage equals

the source voltage (which is near the supply voltage) plus the VGS(ON) threshold of the MOSFET, the source

voltage starts following the gate voltage and ramps toward ground. Eventually the source voltage equals 0 V and

the gate continues to ramp to zero thus turning OFF the power device. This gradual turnoff characteristic, instead

of an abrupt removal of the gate drive, can, in some applications, minimize the power dissipation in the MOSFET

or reduce the duration of negative transients, as is the case when driving inductive loads. In the event of an

overstress condition on the power device, the turnoff characteristic is even more gradual as the output sinking

current is only 10 µA (see Lossless Overcurrent Protection).

7.3.3 Turn On and Turn Off Characteristics

The actual rate of change of the voltage applied to the gate of the power device is directly dependent on the

input capacitances of the MOSFET used. These times are important to know if the power to the load is to be

applied repetitively as is the case with pulse width modulation drive. Of concern are the capacitances from gate

to drain, CGD, and from gate to source, CGS.Figure 13 details the turnon and turnoff intervals in a typical

application. An inductive load is assumed to illustrate the output transient voltage to be expected. At time t1, the

ON/OFF input goes high. The output, which drives the gate of the MOSFET, immediately pulls the gate voltage

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Feature Description (continued)

towards the VCC supply of the LM9061. The source current from pin 4 is typically 30 mA which quickly charges

CGD and CGS. As soon as the gate reaches the VGS(ON) threshold of the MOSFET, the switch turns ON and the

source voltage starts rising towards VCC. VGS remains equal to the threshold voltage until the source reaches

VCC. While VGS is constant only CGD is charging. When the source voltage reaches VCC, at time t2, the charge

pump takes over the drive of the gate to ensure that the MOSFET remains ON.

The charge pump is basically a small internal capacitor that acquires and transfers charge to the output pin. The

clock rate is set internally at typically 300 kHz. In effect the charge pump acts as a switched capacitor resistor

(approximately 67k) connected to a voltage that is clamped at 13 V above the Sense input pin of the LM9061

which is equal to the VCC supply in typical applications. The gate voltage rises above VCC in an exponential

fashion with a time constant dependent upon the sum of CGD and CGS. At this time however the load is fully

energized. At time t3, the charge pump reaches its maximum potential and the switch remains ON.

At time t4, the ON/OFF input goes low to turn off the MOSFET and remove power from the load. At this time the

charge pump is disconnected and an internal 110-µA current sink begins to discharge the gate input

capacitances to ground. The discharge rate (ΔV/ΔT) is equal to 110 µA/ (CGD + CGS).

The load is still fully energized until time t5 when the gate voltage has reached a potential of the source voltage

(VCC) plus the VGS(ON) threshold voltage of the MOSFET. Between time t5 and t6, the VGS voltage remains

constant and the source voltage follows the gate voltage. With the voltage on CGD held constant the discharge

rate now becomes 110 µA/CGD.

At time t6 the source voltage reaches 0 V. As the gate moves below the VGS(ON) threshold the MOSFET tries to

turn off. With an inductive load, if the current in the load has not collapsed to zero by time t6, the action of the

MOSFET turning off creates a negative voltage transient (flyback) across the load. The negative transient will be

clamped to −VGS(ON) because the MOSFET must turn itself back on to continue conducting the load current until

the energy in the inductance has been dissipated (at time t7).

7.3.4 Lossless Overcurrent Protection

A unique feature of the LM9061 is the ability to sense excessive power dissipation in the MOSFET and latch it

OFF to prevent permanent failure. Instead of sensing the actual current flowing through the MOSFET to the load,

which typically requires a small valued power resistor in series with the load, the LM9061 monitors the voltage

drop from drain to source, VDS, across the MOSFET. This lossless technique allows all of the energy available

from the supply to be conducted to the load as required. The only power loss is that of the MOSFET itself and

proper selection of a particular power device for an application minimizes this concern. Another benefit of this

technique is that all applications use only standard inexpensive ¼W or less resistors.

To use this lossless protection technique requires knowledge of key characteristics of the power MOSFET used.

In any application the emphasis for protection can be placed on either the power MOSFET or on the amount of

current delivered to the load, with the assumption that the selected MOSFET can safely handle the maximum

load current.

LOAD MAX

DS ON (MIN)

( )

DS (MAX) D (MAX) DS(ON) (MAX)

V = P R´

DISS

DS ON

( )

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Feature Description (continued)

Figure 13. Turnon and Turnoff Waveforms

To protect the MOSFET from exceeding its maximum junction temperature rating, the power dissipation must be

limited. The maximum power dissipation allowed (derated for temperature) and the maximum drain to source ON

resistance, RDS(ON), with both at the maximum operating ambient temperature, must be determined. When

switched ON the power dissipation in the MOSFET is calculated by Equation 1:

(1)

The VDS voltage to limit the maximum power dissipation is therefore calculated by Equation 2:

(2)

With this restriction, the actual load current and power dissipation obtained is a direct function of the actual

RDS(ON) of the MOSFET at any particular ambient temperature but the junction temperature of the power device

never exceeds its rated maximum.

To limit the maximum load current requires an estimate of the minimum RDS(ON) of the MOSFET (the minimum

RDS(ON) of discrete MOSFETs is rarely specified) over the required operating temperature range.

The maximum current to the load is calculated by Equation 3:

(3)

The maximum junction temperature of the MOSFET or the maximum current to the load can be limited by

monitoring and setting a maximum operational value for the drain to source voltage drop, VDS. In addition, in the

event that the load is inadvertently shorted to ground, the power device is automatically be turned off.

In all cases, if the MOSFET be switched OFF by the built in protection comparator, the output sink current is

switched to only 10 µA to gradually turn off the power device.

Figure 14 illustrates how the threshold voltage for the internal protection comparator is established.

REF

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Feature Description (continued)

Two resistors connect the drain and source of the MOSFET to the LM9061. The Sense input, pin 1, monitors the

source voltage while the Threshold input, pin 2, is connected to the drain, which is also connected to the

constant load power supply. Both of these inputs are the two inputs to the protection comparator. If the voltage at

the sense input ever drop below the voltage at the threshold input, the protection comparator output goes high

and initiates an automatic latch-OFF function to protect the power device. Therefore the switching threshold

voltage of the comparator directly controls the maximum VDS allowed across the MOSFET while conducting load

current.

The threshold voltage is set by the voltage drop across resistor RTHRESHOLD. A reference current is fixed by a

resistor to ground at IREF, pin 6. To precisely regulate the reference current over temperature, a stable band gap

reference voltage is provided to bias a constant current sink. The reference current is set by Equation 4:

(4)

The reference current sink output is internally connected to the threshold pin. IREF then flows from the load supply

through RTHRESHOLD. The fixed voltage drop across RTHRESHOLD is approximately equal to the maximum value of

VDS across the MOSFET before the protection comparator trips.

It is important to note that the programmed reference current serves a multiple purpose as it is used internally for

biasing and also has a direct effect on the internal charge pump switching frequency. The design of the LM9061

is optimized for a reference current of approximately 80 µA, set with a 15.4 kΩ±1% resistor for RREF. To obtain

the ensured performance characteristics, TI recommends using a 15.4-kΩresistor for RREF.

The protection comparator is configured such that during normal operation, when the output of the comparator is

low, the differential input stage of the comparator is switched in a manner that there is virtually no current flowing

into the noninverting input of the comparator. Therefore, only IREF flows through resistor RTHRESHOLD. All of the

input bias current, 20 µA maximum, for the comparator input stage (twice the ISENSE specification of 10 µA

maximum, defined for equal potentials on each of the comparator inputs) however flows into the inverting input

through resistor RSENSE. At the comparator threshold, the current through RSENSE is no more than the ISENSE

specification of 10 µA.

Figure 14. Protection Comparator Biasing

To tailor the VDS (MAX) threshold for any particular application, the resistor RTHRESHOLD can be selected per

Equation 5:

TIMER DELAY

DELAY

V C

( )´

REF THR

DS (MAX) SENSE SENSE OS

REF

V R

V = I R V

R( )

- ´ +

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Feature Description (continued)

where

• RREF = 15.4 kΩ.

• ISENSE is the input bias current to the protection comparator.

• RSENSE is the resistor connected to pin 1.

• VOS is the offset voltage of the protection comparator (typically in the range of ±10 mV). (5)

The resistor RSENSE is optional, but TI strongly recommends proving transient protection for the Sense pin,

especially when driving inductive type loads. A minimum value of 1 kΩprotects the pin from transients ranging

from −25 V to +60 V. This resistor must be equal to, or less than, the resistor used for RTHRESHOLD. Never set

RSENSE to a value larger than RTHRESHOLD. When the protection comparator output goes high, the total bias

current for the input stage transfers from the Sense pin to the Threshold pin, thereby changing the voltages

present at the inputs to the comparator. For consistent switching of the comparator right at the desired threshold

point, the voltage drop that occurs at the noninverting input (Threshold) must equal, or exceed, the rise in voltage

at the inverting input (Sense).

A bypass capacitor across RREF is optional and is used to help keep the reference voltage constant in

applications where the VCC supply is subject to high levels of transient noise. This bypass capacitor must be no

larger than 0.1 µF, and is not needed for most applications.

7.3.5 Delay Timer

To allow the MOSFET to conduct currents beyond the protection threshold for a brief period of time, a delay

timer function is provided. This timer delays the actual latching OFF of the MOSFET for a programmable interval.

This feature is important to drive loads which require a surge of current in excess of the normal ON current upon

start-up, or at any point in time, such as lamps and motors. Figure 15 details the delay timer circuitry. A capacitor

connected from the Delay pin 8, to ground sets the delay time interval. With the MOSFET turned ON and all

conditions normal, the output of the protection comparator is low and this keeps the discharge transistor ON. This

transistor keeps the delay capacitor discharged. If a surge of load current trips the protection comparator high,

the discharge transistor turns off and an internal 10-µA current source begins linearly charging the delay

capacitor.

If the surge current, with excessive VDS voltage, lasts long enough for the capacitor to charge to the timing

comparator threshold of typically 5.5 V, the output of the comparator goes high to set a flip-flop and immediately

latch the MOSFET OFF. It does not restart until the ON/OFF Input is toggled low then high.

The delay time interval is set by the selection of CDELAY and can be found in Equation 6:

where

• Typically, VTIMER = 5.5 V.

• IDELAY = 10 µA. (6)

Charging of the delay capacitor is clamped at approximately 7.5 V which is the internal bias voltage for the 10-µA

current source.

DELAY START -UP

DELAY

TIMER

I T

( )´

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Feature Description (continued)

Figure 15. Delay Timer

7.3.5.1 Minimum Delay Time

A minimum delay time interval is required in all applications due to the nature of the protection circuitry. At the

instant the MOSFET is commanded ON, the voltage across the MOSFET, VDS, is equal to the full load supply

voltage because the source is held at ground by the load. This condition immediately trips the protection

comparator. Without a minimum delay time set, the timing comparator trips and forces the MOSFET to latch-OFF

thereby never allowing the load to be energized.

To prevent this situation a delay capacitor is required at pin 8. The selection of a minimum capacitor value to

ensure proper start-up depends primarily on the load characteristics and how much time is required for the

MOSFET to raise the load voltage to the point where the Sense input is more positive than the Threshold input

(TSTART-UP). Some experimentation is required if a specific minimum delay time characteristic is desired (see

Equation 7).

(7)

In the absence of a specific delay time requirement, TI recommends a value for CDELAY of 0.1 µF.

7.3.6 Overvoltage Protection

The LM9061 remains operational with up to +26 V on VCC. If VCC increases to more than typically +30 V the

LM9061 will turn off the MOSFET to protect the load from excessive voltage. When VCC has returned to the

normal operating range the device will return to normal operation without requiring toggling the ON/OFF input.

This feature allows MOSFET operation to continue in applications that are subject to periodic voltage transients,

such as automotive applications.

For circuits where the load is sensitive to high voltages, the circuit shown in Figure 16 can be used. The addition

of a Zener on the Sense input (pin 1) provides a maximum voltage reference for the Protection Comparator. The

Sense resistor is required in this application to limit the Zener current. When the device is ON, and the load

supply attempts to rise higher than (VZENER + VTHRESHOLD), the Protection comparator trips, and the Delay Timer

starts. If the high supply voltage condition lasts long enough for the Delay Timer to time out, the MOSFET is

latched off. The ON/OFF input must be toggled to restart the MOSFET.

LM9061

LM9061-Q1

www.ti.com

SNOS738I –APRIL 1995–REVISED JANUARY 2017

Product Folder Links: LM9061 LM9061-Q1

Feature Description (continued)

Figure 16. Adding Overvoltage Protection

7.3.7 Reverse Battery

If the VCC supply must be taken negative with respect to ground, the current from the VCC pin must be limited to

20 mA. The addition of a diode in series with the VCC input is recommended. This diode drop does not subtract

significantly from the charge pump gate overdrive output voltage.

7.3.8 Low Battery

An additional feature of the LM9061 is an Undervoltage Shutoff function (UVSO). The typical UVSO threshold is

6.2 V, and does not have hysteresis. When VCC is between the ensured minimum operating voltage of 7 V, and

the UVSO threshold, the operation of the MOSFET gate drive, the delay timer, and the protection circuitry is not

ensured. Operation in this region must be avoided. When VCC falls below the UVSO threshold, the charge pump

is disabled and the gate is discharged at the normal OFF current sink rate, typically 110 μA.

Figure 17 shows the LM9061 used as an electronic circuit breaker. This circuit provides low voltage shutdown,

overvoltage latch-OFF, and overcurrent latch-OFF.

The low voltage shutdown uses the ON and OFF voltage thresholds, and the typical 1.2 V of hysteresis, to

disable the LM9061 if VCC falls near, or below, the 7 V minimum operating voltage. The low voltage shutdown is

accomplished with a voltage divider biased off VCC. The voltage divider is formed by R1 (30 kΩ), R2 (82 kΩ), and

the internal pulldown resistor of the ON/OFF pin (30 kΩtypical). In normal operation, VCC is above the minimum

operating voltage of 7 V, and the ON/OFF pin is biased above the OFF threshold of 1.5-V maximum (1.8-V

typical). When VCC falls to 7 V the ON/OFF pin voltage falls below the OFF threshold voltage and the LM9061 is

turned off.

In the event of a latch-OFF shutdown, the circuit can be reset by shutting the main supply off, then back on. An

optional, normally open, switch (Clear) from the ON/OFF pin to ground, allows a push button clear of the circuit

after latching OFF.

30 NŸ

15.4 NŸ

2 NŸ

1 NŸ

NDP606A

Set

Clear

82 NŸ

Supply > 7.0V

1 µF 0.1 µF

1234

8765

N.O.

8A Load

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LM9061 LM9061-Q1

Feature Description (continued)

Figure 17. Electronic Circuit Breaker

This voltage divider arrangement requires a mechanism to raise the ON/OFF pin above the ON threshold of 3.5-

V minimum (3.1-V typical) when VCC is less than typically 16 V. This can be accomplished with a second,

normally open, switch from the ON/OFF pin across R2 (Set), so that closing the switch shorts R2 and the voltage

at the ON/OFF pin is typically one-half of VCC. When VCC is at the minimum operating voltage of 7 V this biases

the ON/OFF pin to about 3.5 V, causing the LM9061 to turn on. When VCC is above typically 16.5 V, the resistor

divider has the ON/OFF pin biased above 3.5 V and shorting of the resistor R2 is not be needed.

While the scaling of the external resistor values between VCC and the ON/OFF input pin, against the internal

30-kΩresistor, can be used to increase the start-up voltage, it is important that the resistor ratio always has the

ON/OFF pin biased below the OFF threshold (1.5 V) when VCC falls below the minimum operating voltage of 7 V.

LM9061

LM9061-Q1

www.ti.com

SNOS738I –APRIL 1995–REVISED JANUARY 2017

Product Folder Links: LM9061 LM9061-Q1

Feature Description (continued)

The accuracy of this voltage divider arrangement is affected by normal manufacturing variations of the ON and

OFF voltage thresholds and the value of internal resistor at the ON/OFF pin. If any application needs to detect

with greater precision when VCC is near to 7 V, an external voltage monitor must be used to drive the ON/OFF

pin. The external voltage monitor would also eliminate both the need for the switch to short R2 to start the

LM9061, as well as R2.

7.3.9 Increasing MOSFET Turnon Time

The ability of the LM9061 to quickly turn on the MOSFET is an important factor in the management of the

MOSFET power dissipation. Exercise caution when trying to increase the MOSFET turnon time by limiting the

Gate drive current. The MOSFET average dissipation, and the LM9061 Delay time, must be recalculated with the

extended switching transition time.

Figure 18 shows a method of increasing the MOSFET turnon time, without affecting the turnoff time. In this

method the Gate is charged at an exponential rate set by the added external Gate resistor and the MOSFET

Gate capacitances.

Figure 18. Increasing MOSFET Turnon Time

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LM9061 LM9061-Q1

7.4 Device Functional Modes

7.4.1 Operation With VCC > 30 V

If VCC increases to more than typically 30 V, the LM9061 turns off the MOSFET to protect the load from

excessive voltage. When VCC has returned to the normal operating range, the device returns to normal operation

without requiring toggling the ON/OFF input. This feature allows MOSFET operation to continue in applications

that are subject to periodic voltage transients, such as automotive applications.

7.4.2 Operation With VCC < 6.2 V

When VCC falls below the UVSO threshold of 6.2 V, the charge pump is disabled and the gate is discharged at

the normal OFF current sink rate, typically 110 μA.

7.4.3 Operation With ON/OFF Control

In the ON state, the charge pump voltage, which is well above the available VCC supply, is directly applied to the

gate of the MOSFET. When commanded OFF a 110-µA current sink discharges the gate capacitances of the

MOSFET for a gradual turnoff characteristic to minimize the duration of inductive load transient voltages and

further protect the power MOSFET.

7.4.4 MOSFET Latch-OFF

In the event of excessive power dissipation in the MOSFET as detected by the LM9061 sense and threshold

pins, the MOSFET is latched OFF to prevent permanent failure. It does not restart until the ON/OFF Input is

toggled low then high.

LM9061

LM9061-Q1

www.ti.com

SNOS738I –APRIL 1995–REVISED JANUARY 2017

Product Folder Links: LM9061 LM9061-Q1

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM9061 can be configured to drive the gate to any size external high-side power MOSFET, including

multiple parallel connected MOSFETs for very high current applications. See Basic Operation for details on the

gate drive operation and Turn On and Turn Off Characteristics for details on the gate drive timing characteristics.

8.2 Typical Applications

8.2.1 TITLE NEEDED

The LM9061 is an ideal driver for any application that requires multiple parallel MOSFETs to provide the

necessary load current. Figure 19 shows a circuit with four parallel NDP706A MOSFETs. This circuit

configuration provides a typical maximum load current of 150 A at 25°C, and a typical maximum load current of

100 A at 125°C.

Figure 19. Driving Multiple MOSFETs

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LM9061 LM9061-Q1

Typical Applications (continued)

8.2.1.1 Design Requirements

Only a few common sense precautions need to be observed. All MOSFETs in the array must have identical

electrical and thermal characteristics. This can be solved by using the same part number from the same

manufacturer for all of the MOSFETs in the array. Also, all MOSFETs must have the same style heat sink or,

ideally, all mounted on the same heat sink. The electrical connection of the MOSFETs should get special

attention. With typical RDS(ON) values in the range of tens of mΩ, a poor electrical connection for one of the

MOSFETs can render it useless in the circuit. Also, consider the MOSFET dissipation during the normal OFF

discharge of the gate capacitance (70-µA minimum and 110-µA typical).

CAUTION

In the event of a fault condition, the Latch-OFF current sink, 10-µA typical, may not be

able to discharge the total gate capacitance in a timely manner to prevent damage to

the MOSFETs.

8.2.1.2 Detailed Design Procedure

The NDP706A MOSFET has a typical RDS(ON) of 0.013 Ωwith a TJof 25°C, and 0.02 Ωwith a TJof +125°C. An

RTHRESHOLD value of 6.2 kΩas shown in Figure 19 sets the VDS threshold voltage to approximately 500 mV. This

provides a typical maximum load current of 150 A at 25°C, and a typical maximum load current of 100 A at

125°C. See Lossless Overcurrent Protection for details on calculating RTHRESHOLD.

The maximum dissipation, per MOSFET, is nearly 20 W at 25°C, and 12.5 W at 125°C. With up to 20 W being

dissipated by each of the four devices, an effective heat sink is required to keep the TJas low as possible when

operating near the maximum load currents.

8.2.1.3 Application Curves

Figure 20. MOSFET Gate During Start-Up, Total Gate

Capacitance = 11200 pF Figure 21. MOSFET Gate During Shutdown, Total Gate

Capacitance = 11200 pF

ON/OFF

OUT 4

SENSE

IREF 6

THR

DELAY 8

VCC

5GND 3

LM9061M

220

0.1uF

15.4k

100

D2D1

GND

I/O 1

GND GND

I/O 2

ON/OFF

LM9061

LM9061-Q1

www.ti.com

SNOS738I –APRIL 1995–REVISED JANUARY 2017

Product Folder Links: LM9061 LM9061-Q1

Typical Applications (continued)

8.2.2 Bidirectional Applications

8.2.2.1 Back-to-Back MOSFET Configuration

Due to the orientation of the FET, the typical configuration of LM9061 is only able to toggle conduction when

current flows from the drain to the source. In applications where reverse current may occur, the body diode

always provides a path from load to supply. For the LM9061’s OFF state to fully disconnect the load and supply

and prevent any bidirectional current, an additional FET must be placed in series with the original. This back-to-

back configuration shown in Figure 22 allows either input to be the supply side or the load side.

NOTE

An increase in turnon and turnoff time occurs due to the increased gate capacitance from

the additional FET.

To provide the LM9061 with proper supply voltage, two diodes connect both inputs to VCC. This feeds the device

with whichever side has a higher potential, ensuring that it does not disconnect itself from the voltage supply

during operation.

Figure 22. Bidirectional Switch

8.2.2.1.1 Application Curve

Here the bidirectional switch is being used to charge and discharge a capacitive load. As long as the switch is

enabled ON, current is allowed to flow in and out of the capacitor in response to the steps in input voltage.

However, when the switch is enabled OFF, current ceases to flow and the capacitor voltage is isolated from the

input. Operation continues normally once the switch is returned to an ON state.

Figure 23. Bidirectional Switch Controlling Current to a Capacitive Load

ON/OFF

OUT 4

SENSE

IREF 6

THR

DELAY 8

VCC

5GND 3

LM9061M

220

0.1uF

15.4k

100

D2D1

ON/OFF 7

OUT

4SENSE 1

IREF

6THR 2

DELAY

VCC 5

GND

LM9061M

15.4k

0.1uF

GND

220

100

I/O 1

GND GND

I/O 2

ON/OFF

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LM9061 LM9061-Q1

Typical Applications (continued)

8.2.2.2 Bidirectional Switch With Reverse Overcurrent Protection

While Figure 22 functions as a bidirectional switch, it does not monitor for overcurrent in both directions. Because

overcurrent is detected when the potential at the sense pin is lower than the potential at the threshold pin by a

user set amount, the LM9061 only offers OCP when the current flows through the FET before reaching the sense

pin. To implement a bidirectional switch that also has bidirectional overcurrent protection, each FET should be

controlled by its own LM9061 device. Figure 24 shows the two LM9061 and FET pairs in a mirrored back-to-back

configuration. By tying the ON/OFF pins together, the switch can still be toggled from a single line.

Figure 24. Bidirectional Switch Including Reverse OCP

8.2.2.2.1 Application Curve

The application curve below shows the reverse overcurrent protection. Even with the bidirectional current, the

device goes into overcurrent shutdown if the current reaches the current limit threshold. Note that the reverse

overcurrent protection is accomplished using two separate LM9061 devices as shown in Figure 24.

Figure 25. Reverse Overcurrent Protection for Bidirectional Switch

9 Power Supply Recommendations

It is important to remember that during the Turnon of the MOSFET the output current to the Gate is drawn from

the VCC supply pin. The VCC pin must be bypassed with a capacitor with a value of at least ten times the Gate

capacitance, and no less than 0.1 μF. If the VCC supply must be taken negative with respect to ground, for

example during a reverse battery condition, the current from the VCC pin must be limited to 20 mA. The addition

of a diode in series with the VCC input is recommended. This diode drop does not subtract significantly from the

charge pump gate overdrive output voltage.

LM9061

LM9061-Q1

www.ti.com

SNOS738I –APRIL 1995–REVISED JANUARY 2017

Product Folder Links: LM9061 LM9061-Q1

10 Layout

10.1 Layout Guidelines

1. The bypass capacitor for VCC must be placed as close as possible to the VCC pin.

2. The resistor RREF must be placed as close as possible to the IREF and Ground pins with minimal trace length

to keep the IREF current as accurate as possible. The LM9061 is optimized for use with a 15.4 kΩ±1%

resistor for RREF.

3. In applications where the VCC supply is subject to high levels of transient noise, a bypass capacitor across

RREF is recommended. This bypass capacitor must be no larger than 0.1 μF and must be placed as close as

possible to the IREF pin.

4. The RTHRESHOLD and RSENSE resistors must be placed as close as possible to the MOSFET drain and source

pins respectively. This allows accurate monitoring of the VDS voltage across the MOSFET.

5. An array of vias can be placed along the high current path to the output load. These vias can help conduct

heat to any inner plane areas or to a bottom-side copper plane.

10.2 Layout Examples

Figure 26 and Figure 27 are layout examples for the LM9061 and LM9061-Q1. These examples are taken from

the LM9061EVM. For information on the operation and schematic of the EVM, see LM9061 High-Side Protection

Controller EVM (SNOU132).

Figure 26. LM9061EVM Layout Example (Top)

Figure 27. LM9061EVM Layout Example (Bottom)

LM9061

LM9061-Q1

SNOS738I –APRIL 1995–REVISED JANUARY 2017

www.ti.com

Product Folder Links: LM9061 LM9061-Q1

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

LM9061 High-Side Protection Controller EVM (SNOU132)

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LM9061 Click here Click here Click here Click here Click here

LM9061-Q1 Click here Click here Click here Click here Click here

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM9061M/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM90

61M

LM9061MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM90

61M

LM9061QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) NIPDAU Level-3-260C-168HRS -40 to 125 9061Q1

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM9061, LM9061-Q1 :

•Catalog: LM9061

•Automotive: LM9061-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM9061MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM9061QDRQ1 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM9061MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM9061QDRQ1 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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