General Description
The MAX15040 high-efficiency switching regulator
delivers up to 4A load current at output voltages from
0.6V to (0.9 x VIN). The device operates from 2.4V to
3.6V, making it ideal for on-board point-of-load and
postregulation applications. Total output-voltage accu-
racy is within ±1% over load, line, and temperature.
The MAX15040 features 1MHz fixed-frequency PWM
mode operation. The high operating frequency allows
for small-size external components.
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical parasitic
inductances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
The MAX15040 incorporates a high-bandwidth
(> 15MHz) voltage-error amplifier. The voltage-mode
control architecture and the voltage-error amplifier per-
mit a Type III compensation scheme to achieve maxi-
mum loop bandwidth, up to 200kHz. High loop
bandwidth provides fast transient response, resulting in
less required output capacitance and allowing for all-
ceramic capacitor designs.
The MAX15040 features an output overload hiccup pro-
tection and peak current limit on both high-side (sourc-
ing current) and low-side (sinking and sourcing current)
MOSFETs, for ultra-safe operations in case of high out-
put prebias, short-circuit conditions, severe overloads,
or in converters with bulk electrolytic capacitors.
The MAX15040 features an adjustable output voltage.
The output voltage is adjustable by using two external
resistors at the feedback or by applying an external ref-
erence voltage to the REFIN/SS input. The MAX15040
offers programmable soft-start time using one capacitor
to reduce input inrush current. A built-in thermal shut-
down protection assures safe operation under all condi-
tions. The MAX15040 is available in a 2mm x 2mm,
16-bump (4 x 4 array), 0.5mm pitch WLP package.
Applications
Server Power Supplies
Point-of-Load
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
Features
oInternal 15mΩ RDS(ON) MOSFETs
oContinuous 4A Output Current
o±1% Output-Voltage Accuracy Over Load, Line,
and Temperature
oOperates from 2.4V to 3.6V Supply
oAdjustable Output from 0.6V to (0.9 x VIN)
oAdjustable Soft-Start Reduces Inrush Supply
Current
oFactory-Trimmed 1MHz Switching Frequency
oCompatible with Ceramic, Polymer, and
Electrolytic Output Capacitors
oSafe Startup into Prebias Output
oEnable Input/Power-Good Output
oFully Protected Against Overcurrent and
Overtemperature
oOverload Hiccup Protection
oSink/Source Current in DDR Applications
o2mm x 2mm, 16-Bump (4 x 4 Array), 0.5mm Pitch
WLP Package
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4426; Rev 2; 7/10
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
M AX 15040E WE + - 40°C to + 85°C 16 WLP
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
OUTPUT
INPUT
2.4V TO 3.6V
BST
LX
IN
EN
VDD
GND
FB
VDD
COMP
PWRGD
REFIN/SS
GND
MAX15040
Typical Operating Circuit
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, VDD, PWRGD to GND ......................................-0.3V to +4.5V
LX to GND....................-0.3V to the lower of 4.5V or (VIN + 0.3V)
LX Transient ..............(VGND - 1.5V, <50ns), (VIN + 1.5V, <50ns)
COMP, FB, REFIN/SS,
EN to GND..............-0.3V to the lower of 4.5V or (VDD + 0.3V)
LX RMS Current (Note 1) .........................................................5A
BST to LX..................................................................-0.3V to +4V
BST to GND ..............................................................-0.3V to +8V
Continuous Power Dissipation (TA= +70°C)
16-Bump (4 x 4 Array), 0.5mm Pitch WLP
(derated 12.5mW/°C above +70°C)...........................1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Continuous Operating Temperature at
Full Load Current (Note 2) ...........................................+105°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed
the package power dissipation limit of the device.
Note 2: Continuous operation at full current beyond +105°C may degrade product life.
PARAMETER CONDITIONS MIN TYP MAX UNITS
IN/VDD
IN and VDD Voltage Range 2.40 3.60 V
VIN = 2.5V 0.52 1
IN Supply Current No load, no switching VIN = 3.3V 0.8 1.5 mA
VIN = 2.5V 3.7 5.5
VDD Supply Current No load, no switching VIN = 3.3V 4 6 mA
VIN = VDD = 2.5V 12
Total Supply Current (IN + VDD) No load VIN = VDD = 3.3V 23 mA
Total Shutdown Current from IN
and VDD VIN = VDD = VBST - VLX = 3.6V, VEN = 0V 0.1 2 µA
VDD rising 2 2.2
VDD Undervoltage Lockout
Threshold LX starts/stops switching VDD falling 1.75 1.9 V
VDD UVLO Deglitching 2µs
BST
TA = +25°C 2
BST Leakage Current VBST = VDD = VIN = 3.6V,
VLX = 3.6V or 0V, VEN = 0V TA = +85°C 0.025 µA
PWM COMPARATOR
PWM Comparator Propagation
Delay 10mV overdrive 10 ns
COMP
COMP Clamp Voltage High VDD = 2.4V to 3.6V 2.03 V
COMP Clamp Voltage Low VDD = 2.4V to 3.6V 0.73 V
COMP Slew Rate 1.6 V/µs
PWM Ramp Valley VDD = 2.4V to 3.6V 830 mV
PWM Ramp Amplitude 1V
COMP Shutdown Resistance From COMP to GND, VEN = 0V 8 Ω
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
FB Regulation Accuracy Using internal reference 0.594 0.600 0.606 V
Open-Loop Voltage Gain 1kΩ from COMP to GND (Note 4) 115 dB
Error-Amplifier Unity-Gain
Bandwidth Series 5kΩ, 100nF from COMP to GND (Note 4) 26 MHz
VDD = 2.4V to 2.6V 0 VDD - 1.80
Error-Amplifier Common-Mode
Input Range VDD = 2.6V to 3.6V 0 VDD - 1.85 V
VCOMP = 1.2V, sinking 500
Error-Amplifier Minimum Output
Current VCOMP = 1.0V, sourcing 1000 µA
FB Input Bias Current VFB = 0.7V, using internal reference, TA = +25°C -200 -100 nA
REFIN/SS
REFIN/SS Charging Current VREFIN/SS = 0.45V 7 8 9 µA
REFIN/SS Discharge Resistance 520 Ω
VDD = 2.4V to 2.6V 0 VDD - 1.80
REFIN/SS Common-Mode Range VDD = 2.6V to 3.6V 0 VDD - 1.85 V
TA = +25°C 30 µV
REFIN/SS Offset Voltage Error amplifier offset -4.5 +4.5 mV
LX (ALL BUMPS COMBINED)
VIN = VBST - VLX = 2.5V 21
LX On-Resistance, High Side ILX = -0.4A VIN = VBST - VLX = 3.3V 19 mΩ
VIN = 2.5V 16
LX On-Resistance, Low Side ILX = 0.4A VIN = 3.3V 15 mΩ
High-side sourcing 5.5 7
LX Peak Current-Limit Threshold VIN = 2.5V Low-side sinking 5.5 7 A
VLX = 0V -2
TA = +25°C VLX = 3.6V +2LX Leakage Current VIN = 3.6V, VEN = 0V
TA = +85°C 0.2
µA
LX Switching Frequency VIN = 2.5V to 3.3V, TA = +25°C 0.92 1 1.03 MHz
LX Maximum Duty Cycle VIN = 2.5V to 3.3V, TA = +25°C 92 96 %
LX Minimum On-Time 80 ns
RMS LX Output Current 4A
ENABLE
EN Input Logic-Low Threshold 0.7 V
EN Input Logic-High Threshold 1.7 V
TA = +25°C 1
EN Input Current VEN = 0 or 3.6V,
VIN = VDD = 3.6V TA = +85°C 0.3 µA
EFFICIENCY
vs. OUTPUT CURRENT
MAX15040 toc01
OUTPUT CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VDD = VIN = 3.3V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 2.5V
EFFICIENCY
vs. OUTPUT CURRENT
MAX15040 toc02
OUTPUT CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VIN = VDD = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.5V
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
4 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
THERMAL SHUTDOWN
Thermal-Shutdown Threshold Rising +165 °C
Thermal-Shutdown Hysteresis 20 °C
POWER-GOOD (PWRGD)
VFB falling, VREFIN/SS = 0.6V 87 90 93
Power-Good Threshold Voltage VFB rising, VREFIN/SS = 0.6V 92.5
% of
VRE F IN /S S
Power-Good Edge Deglitch VFB falling or rising 48 Clock
cycles
PWRGD Output-Voltage Low IPWRGD = 4mA (sinking) 0.03 0.15 V
PWRGD Leakage Current VDD = VPWRGD = 3.6V, VFB = 0.9V 0.01 µA
OVERCURRENT LIMIT (HICCUP MODE)
Current-Limit Startup Blanking 112 Clock
cycles
Restart Time 896 Clock
cycles
FB Hiccup Threshold VFB falling 70 % of
VRE F IN /S S
Hiccup Threshold Blanking Time VFB falling 36 µs
Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and characterization.
Note 4: Guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
Typical Operating Characteristics
(VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________
5
EFFICIENCY
vs. OUTPUT CURRENT
MAX15040 toc03
OUTPUT CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VDD = 3.3V
VIN = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.5V
FREQUENCY
vs. INPUT VOLTAGE
MAX15040 toc04
INPUT VOLTAGE (V)
FREQUENCY (MHz)
3.43.22.6 2.8 3.0
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
0.80
2.4 3.6
TA = -40°C
TA = +25°C
TA = +85°C
LINE REGULATION
MAX15040 toc05
INPUT VOLTAGE (V)
OUTPUT VOLTAGE ERROR (%)
3.43.23.02.82.6
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
2.4 3.6
VOUT = 1.8V
VOUT = 1.2V
LOAD REGULATION
MAX15040 toc06
LOAD CURRENT (A)
OUTPUT VOLTAGE ERROR (%)
321
-0.40
-0.30
-0.20
-0.10
0
0.10
-0.50
04
VOUT = 1.8V
VOUT = 1.2V
VOUT = 2.5V
VOUT = 1.5V
INTERNAL REFERENCE
LOAD-TRANSIENT RESPONSE
MAX15040 toc07
40µs/div
VOUT
IOUT
AC-COUPLED
100mV/div
0
1A/div
SWITCHING WAVEFORMS
MAX15040 toc08
400ns/div
ILX
VOUT
VLX
AC-COUPLED
50mV/div
0
0
2A/div
2V/div
SHUTDOWN WAVEFORM
MAX15040 toc09
10µs/div
VEN
VOUT
2V/div
0
0
1V/div
IOUT = 1.8A
SOFT-START WAVEFORM
MAX15040 toc10
400µs/div
VEN
VOUT
2V/div
0
0
1V/div
Typical Operating Characteristics (continued)
(VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
6 _______________________________________________________________________________________
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
MAX15040 toc11
INPUT VOLTAGE (V)
INPUT SHUTDOWN CURRENT (nA)
3.43.23.02.82.6
4
8
12
16
20
0
2.4 3.6
VEN = 0
HICCUP CURRENT LIMIT
MAX15040 toc12
1ms/div
VOUT
IIN
IOUT
1V/div
0
10A/div
5A/div
0
0
RMS INPUT CURRENT DURING
SHORT CIRCUIT vs. INPUT VOLTAGE
MAX15040 toc13
INPUT VOLTAGE (V)
RMS INPUT CURRENT (A)
3.43.23.02.82.6
0.1
0.2
0.3
0.4
0.5
0
2.4 3.6
VOUT = 0
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX15040 toc14
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
603510-15
0.592
0.594
0.596
0.598
0.600
0.602
0.604
0.606
0.608
0.610
0.590
-40 85
NO LOAD
SOFT-START WITH REFIN/SS
MAX15040 toc15
200µs/div
IIN
VOUT
VREFIN/SS
2A/div
0
0
0
0
VPWRGD 2V/div
500mV/div
1V/div
Typical Operating Characteristics (continued)
(VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
STARTING INTO PREBIAS OUTPUT
WITH 2A LOAD
MAX15040 toc16
400µs/div
VEN
IOUT
VOUT
2V/div
0
0
0
0
VPWRGD 2V/div
1V/div
2A/div
STARTING INTO PREBIAS OUTPUT
WITH NO LOAD
MAX15040 toc17
400µs/div
VEN
VOUT
2V/div
0
0
0
VPWRGD 2V/div
1V/div
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VIN = VDD = 3.3V, output voltage = 1.8V, ILOAD = 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
Pin Description
BUMP NAME FUNCTION
A1, A2 GND Analog/Power Ground. Connect GND to the PCB ground plane at one point near the input bypass
capacitor return terminal as close as possible to the device.
A3, A4 IN Power-Supply Input. Input supply range is from 2.4V to 3.6V. Bypass IN to GND with a 22µF ceramic
capacitor in parallel to a 0.1µ F ceramic capacitor as close as possible to the device.
B1, B2,
B3 LX Inductor Connection. All LX bumps are internally connected together. Connect all LX bumps to the
switched side of the inductor. LX is high impedance when the device is in shutdown mode.
B4 VDD Supply Input. VDD powers the internal analog core. Connect VDD to IN with a 10Ω resistor. Connect a 1µF
ceramic capacitor from VDD to GND.
C1 BST High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor.
C2, C3 I.C. Internally Connected. Leave unconnected or connect to ground.
C4 EN Enable Input. Connect EN to GND to disable the device. Connect EN to VDD to enable the device.
D1 PWRGD
Power-Good Output. PWRGD is an open-drain output that goes high impedance when VFB exceeds 92.5%
of VREFIN/SS and VREFIN/SS is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% of
VREFIN/SS or VREFIN/SS is below 0.54V. PWRGD is internally pulled low when the device is in shutdown
mode, VDD is below the internal UVLO threshold, or the device is in thermal shutdown.
D2 FB Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set
the output voltage from 0.6V to 90% of VIN.
D3 COMP
Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to FB and the
converter output (see the Compensation Design section). COMP is internally pulled to GND when the
device is in shutdown mode.
D4 REFIN/SS
External Reference Input/Soft-Start Timing Capacitor Connection. Connect REFIN/SS to a system voltage to
force FB to regulate to REFIN/SS voltage. REFIN/SS is internally pulled to GND when the device is in
shutdown and thermal shutdown mode. If no external reference is applied, the internal 0.6V reference is
automatically selected. REFIN/SS is also used to perform soft-start. Connect a minimum of 1nF capacitor
from REFIN/SS to GND to set the startup time (see the Soft-Start and Reference Input (REFIN/SS) section).
STARTING INTO PREBIAS OUTPUT ABOVE
NOMINAL SETPOINT WITH NO LOAD
MAX15040 toc18
1ms/div
VEN
VOUT
2V/div
0
VPWRGD
2V/div
0
1V/div
CASE TEMPERATURE
vs. AMBIENT TEMPERATURE
MAX15040 toc19
AMBIENT TEMPERATURE (°C)
CASE TEMPERATURE (°C)
6035-15 10
-20
0
20
40
80
60
100
120
-40
-40 85
CASE = TOP SIDE OF DEVICE
MEASURED ON A MAX15040EVKIT
IOUT = 4A
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
8 _______________________________________________________________________________________
Block Diagram
CONTROL
LOGIC
IN
LX
GND
ILIM
THRESHOLD
IN
BST
THERMAL
SHUTDOWN
SOFT-START
VOLTAGE
REFERENCE
BIAS
GENERATOR
OSCILLATOR
1VP-P
SHUTDOWN
CONTROL
UVLO
CIRCUITRY
VDD
SHDN
FB
0.9 x VREFIN/SS
FB
COMP
GND
PWRGD
ERROR
AMPLIFIER PWM
COMPARATOR
CURRENT-LIMIT
COMPARATOR
ILIM THRESHOLD
BST SWITCH
SHDN
LX
COMP CLAMPS
EN
REFIN/SS
CURRENT-LIMIT
COMPARATOR
MAX15040
MAX15040
C9
0.1µF
OPTIONAL
C1
22µF
OUTPUT
1.8V/4A
INPUT
2.4V TO 3.6V
C3
0.1µF
BST
LX
IN
VDD
FB
COMP
C12
33pF
C11
820pF
R4
5.1kΩ
R5
20kΩ
PWRGD
L1
0.47µH
C8
0.033µF
C2
22µF
C4
0.01µF
C10
470pF
R6
430Ω
C5
1µF
R1
10Ω
REFIN/SS
GND
VDD
MAX15040
U1
IN
EN
ON
OFF
BST
LX
LX
R10
2.2Ω
C15
1000pF
GND
R3
8.06kΩ
1%
R7
4.02kΩ
1%
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 9
Figure 1. All-Ceramic Capacitor Design with VOUT = 1.8V
Detailed Description
The MAX15040 high-efficiency, voltage-mode switching
regulator is capable of delivering up to 4A of output
current. The MAX15040 provides output voltages from
0.6V to (0.9 x VIN) from 2.4V to 3.6V input supplies,
making it ideal for on-board point-of-load applications.
The output-voltage accuracy is better than ±1% over
load, line, and temperature.
The MAX15040 features a 1MHz fixed switching frequen-
cy, allowing the user to achieve all-ceramic capacitor
designs and fast transient responses. The high operating
frequency minimizes the size of external components.
The MAX15040 is available in a 2mm x 2mm, 16-bump
(4 x 4 array), 0.5mm pitch WLP package. The REFIN/SS
function makes the MAX15040 an ideal solution for DDR
and tracking power supplies. Using internal low-RDSON
(15mΩ) n-channel MOSFETs for both high- and low-side
switches maintains high efficiency at both heavy-load
and high-switching frequencies.
The MAX15040 employs voltage-mode control architec-
ture with a high-bandwidth (> 15MHz) error amplifier.
The op-amp voltage-error amplifier works with Type III
compensation to fully utilize the bandwidth of the high-
frequency switching to obtain fast transient response.
Adjustable soft-start time provides flexibilities to mini-
mize input startup inrush current. An open-drain,
power-good (PWRGD) output goes high impedance
when VFB exceeds 92.5% of VREFIN/SS and VREFIN/SS
is above 0.54V. PWRGD goes low when VFB falls below
90% of VREFIN/SS or VREFIN/SS is below 0.54V.
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and tem-
perature protection are not triggered, the controller logic
block takes the output from the PWM comparator and
generates the driver signals for both high-side and low-
side MOSFETs. The control logic block controls the
break-before-make logic and the timing for charging the
bootstrap capacitors. The error signal from the voltage-
error amplifier is compared with the ramp signal generat-
ed by the oscillator at the PWM comparator to produce
the required PWM signal. The high-side switch turns on
at the beginning of the oscillator cycle and turns off when
the ramp voltage exceeds the VCOMP signal or the cur-
rent-limit threshold is exceeded. The low-side switch
then turns on for the remainder of the oscillator cycle.
Typical Application Circuit
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
10 ______________________________________________________________________________________
Current Limit
The internal, high-side MOSFET has a typical 7A peak cur-
rent-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and the
low-side MOSFET turns on. The low-side MOSFET
remains on until the inductor current falls below the low-
side current limit. This lowers the duty cycle and causes
the output voltage to droop until the current limit is no
longer exceeded. The MAX15040 uses a hiccup mode to
prevent overheating during short-circuit output conditions.
During current limit, if VFB drops below 70% of
VREFIN/SS and stays below this level for typically 36µs
(12µs min) or more, the device enters hiccup mode.
The high-side MOSFET and the low-side MOSFET turn
off and both COMP and REFIN/SS are internally pulled
low. The device remains in this state for 896 clock
cycles and then attempts to restart for 112 clock
cycles. If the fault-causing current limit has cleared, the
device resumes normal operation. Otherwise, the
device reenters hiccup mode.
Soft-Start and Reference Input (REFIN/SS)
The MAX15040 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) cur-
rent source charges an external capacitor connected to
REFIN/SS. The soft-start time is adjusted by the value of
the external capacitor from REFIN/SS to GND. The
required capacitance value is determined as:
where tSS is the required soft-start time in seconds.
Connect a minimum 1nF capacitor between REFIN/SS
and GND. REFIN/SS is also an external reference input
(REFIN/SS). The device regulates FB to the voltage
applied to REFIN/SS. The internal soft-start is not avail-
able when using an external reference. Figure 2 shows
a method of soft-start when using an external refer-
ence. If an external reference is not applied, the device
uses the internal 0.6V reference.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VDD is
below 1.9V (typ). Once VDD rises above 2V (typ), UVLO
clears and the soft-start function activates. A 100mV
hysteresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
VIN supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high
impedance when VFB is above 92.5% x VREFIN/SS and
VREFIN/SS is above 0.54V. PWRGD pulls low when VFB
is below 90% of VREFIN/SS for at least 48 clock cycles
or VREFIN/SS is below 0.54V. PWRGD is low during
shutdown.
Setting the Output Voltage
The MAX15040 output voltage is adjustable from 0.6V
to 90% of VIN by connecting FB to the center tap of a
resistor-divider between the output and GND (Figure
3). To determine the values of the resistor-divider, first
select the value of R3 between 2kΩand 10kΩ. Then
use the following equation to calculate R4:
R4 = (VFB x R3)/(VOUT - VFB)
where VFB is equal to the reference voltage at
REFIN/SS and VOUT is the output voltage. For VOUT =
0.6V, remove R4. If no external reference is applied at
REFIN/SS, the internal reference is automatically select-
ed and VFB becomes 0.6V.
CAt
V
SS
=×8
06
µ
.
C
R2
R1
REFIN/SS
MAX15040
Figure 2. Typical Soft-Start Implementation with External
Reference
LX
FB
R3
R4
MAX15040
Figure 3. Setting the Output Voltage with a Resistor Voltage-
Divider
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
______________________________________________________________________________________ 11
Shutdown Mode
Drive EN to GND to shut down the device and reduce
quiescent current to less than 0.1µA. During shutdown,
LX is high impedance. Drive EN high to enable the
MAX15040.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds TJ
= +165°C, a thermal sensor forces the device into shut-
down, allowing the die to cool. The thermal sensor turns
the device on again after the junction temperature cools
by 20°C, causing a pulsed output during continuous
overload conditions. The soft-start sequence begins after
recovery from a thermal-shutdown condition.
Applications Information
IN and VDD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15040, decouple VIN with a 22µF capacitor in
parallel with a 0.1µF capacitor from VIN to GND. Also
decouple VDD with a 1µF capacitor from VDD to GND.
Place these capacitors as close as possible to the device.
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle and fSis the
switching frequency (1MHz). Choose LIR between 20%
to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron or ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15040.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Estimate the output voltage ripple due
to the output capacitance, ESR, and ESL as follows:
where the output ripple due to output capacitance,
ESR, and ESL is:
or whichever is higher.
The peak-to-peak inductor current (IP-P) is:
Use these equations for initial output capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ∆ILOAD. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the
Compen-
sation Design
section for more details.
IVV
fL
xV
V
PP IN OUT
S
OUT
IN
−=−
×
V
RIPPLE ESL( )) =−
I
tx ESL
PP
OFF
VI
tx ESL or
RIPPLE ESL PP
ON
()
=−
VIx
RIPPLE ESR P P()
=−EESR
VI
xC xf
RIPPLE C PP
OUT S
()
=−
8
VV
VV
RIPPLE RIPPLE C
RIPPLE ESR RIPPLE ESL
=+
+
()
() ()
LVVV
f V LIR I
OUT IN OUT
S IN OUT MAX
=×−
×××
()
()
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the device. The total input capacitance must
be equal to or greater than the value given by the fol-
lowing equation to keep the input ripple voltage within
the specification and minimize the high-frequency rip-
ple current being fed back to the input source:
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage, D
is the duty cycle (VOUT/VIN), and TSis the switching
period (1/fS) = 1µs.
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor, L, and the output capacitor, CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
where RLis equal to the sum of the output inductor’s DC
resistance (DCR) and the internal switch resistance,
RDSON. A typical value for RDSON is 15mΩ. ROis the
output load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor.
If there is more than one output capacitor of the same
type in parallel, the value of the ESR in the above equa-
tion is equal to that of the ESR of a single output capaci-
tor divided by the total number of output capacitors.
The MAX15040 high switching frequency allows the use
of ceramic output capacitors. Since the ESR of ceramic
capacitors is typically very low, the frequency of the
associated transfer function zero is higher than the unity-
gain crossover frequency, fC, and the zero cannot be
used to compensate for the double pole created by the
output inductor and capacitor. The double pole produces
a gain drop of 40dB/decade and a phase shift of 180°.
The compensation network must compensate for this
gain drop and phase shift to achieve a stable high-band-
width closed-loop system. Therefore, use type III com-
pensation as shown in Figure 4 and Figure 5. Type III
compensation possesses three poles and two zeros with
the first pole, fP1_EA, located at zero frequency (DC).
Locations of other poles and zeros of the type III compen-
sation are given by:
The above equations are based on the assumptions that
C1 >> C2, and R3 >> R2, which are true in most appli-
cations. Placements of these poles and zeros are deter-
mined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
calculate the required compensation components for
the MAX15040.
The output voltage is determined by:
For VOUT = 0.6V, R4 is not needed.
RR
VOUT
406 3
06
=×
−
()
.
.
fxR xC
PEA
1
223
2_ =π
fx
PEA3
1
2
_=πRRxC12
fxR xC
ZEA2
1
233
_=π
fxR xC
ZEA1
1
211
_=π
fx ESR x C
Z ESR O
_
=1
2π
ff
xLxC xR ESR
RR
PLC P LC
OO
OL
12 1
2
__
== +
+
⎛
⎝
⎜⎞
⎠
⎟
π
II VVV
V
RIPPLE LOAD OUT IN OUT
IN
=× ×−()
CDxT xI
V
IN MIN SOUT
IN RIPPLE
_=
−
12 ______________________________________________________________________________________
MAX15040
The zero-cross frequency of the closed-loop, fC, should
be between 10% and 20% of the switching frequency,
fS (1MHz). A higher zero-cross frequency results in
faster transient response. Once fCis chosen, C1 is cal-
culated from the following equation:
where VP-P = 1VP-P (typ).
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
Setting the second compensation pole, fP2_EA, at
fZ_ESR yields:
Set the third compensation pole at 1/2 of the switching
frequency (500kHz) to gain phase margin. Calculate
C2 as follows:
The above equations provide accurate compensation
when the zero-cross frequency is significantly higher than
the double-pole frequency. When the zero-cross frequen-
cy is near the double-pole frequency, the actual zero-
cross frequency is higher than the calculated frequency.
In this case, lowering the value of R1 reduces the zero-
cross frequency. Also, set the third pole of the type III
compensation close to the switching frequency (1MHz) if
the zero-cross frequency is above 200kHz to boost the
phase margin. The recommended range for R3 is 2kΩto
10kΩ. Note that the loop compensation remains
unchanged if only R4’s resistance is altered to set differ-
ent outputs.
Soft-Starting into a Prebiased Output
The MAX15040 soft-starts into a prebiased output without
discharging the output capacitor. In safe prebiased start-
up, both low-side and high-side switches remain off to
avoid discharging the prebiased output. PWM operation
starts when the voltage on REFIN/SS crosses the voltage
on FB. The PWM activity starts with the low-side switch
turning on first to build the bootstrap capacitor charge.
Power-good (PWRGD) asserts 48 clock cycles after FB
crosses 92.5% of the final regulation set point. After 4096
clock cycles, the device switches from prebiased safe
startup mode to forced PWM mode.
The MAX15040 is capable of starting into a prebias volt-
age higher than the nominal set point without abruptly dis-
charging the output. This is achieved by using the sink
current control of the low-side MOSFET, which has four
internally set sinking current-limit thresholds. An internal
4-bit DAC steps through these thresholds, starting from
the lowest current limit to the highest, in 128 clock cycles
on every power-up.
CxR x f
S
21
1
=π
RC x ESR
C
O
2
3
=
C
xR
xL x C x R ESR
RR
OO
LO
31
08 3
=+
+.
()
R
xC
xL x C x R ESR
RR
OO
LO
11
08 1
=+
+.
()
C
V
V
xxRx R
Rf
IN
PP
L
O
C
1
25
231
=
⎛
⎝
⎜
⎞
⎠
⎟
+×
−
.
()π
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
______________________________________________________________________________________ 13
L
COUT
VOUT
R3
R4
R1
COMP
FB
LX
C1
C3
R2
C2
MAX15040
Figure 4. Type III Compensation Network
DOUBLE POLE
GAIN (dB)
FREQUENCY (Hz)
SECOND
POLE
FIRST AND SECOND ZEROS
POWER-STAGE
TRANSFER
FUNCTION
COMPENSATION
TRANSFER
FUNCTION
OPEN-LOOP
GAIN
THIRD
POLE
Figure 5. Type III Compensation Illustration
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
14 ______________________________________________________________________________________
PCB Layout Considerations and
Thermal Performance
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX15040 evaluation kit layout for optimum performance.
If deviation is necessary, follow these guidelines for good
PCB layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the sig-
nal ground plane.
2) Place capacitors on VDD, IN, and REFIN/SS as close
as possible to the device and the corresponding
bump using direct traces. Keep power ground plane
and signal ground plane separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the out-
put capacitors, and the input capacitors.
4) Connect IN, LX, and GND separately to a large
copper area to help cool the device to further
improve efficiency and long-term reliability.
5) Ensure all feedback connections are short. Place
the feedback resistors and compensation compo-
nents as close to the device as possible.
6) Route high-speed switching nodes, such as LX and
BST, away from sensitive analog areas (FB, COMP).
Chip Information
PROCESS: BiCMOS
WLP
GND IN IN
GND
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
LX LX VDD
LX
I.C. I.C. EN
BST
PWRGD FB COMP REFIN/SS
(BUMPS ON BOTTOM)
TOP VIEW
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 WLP W162B2+1 21-0200 —
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/09 Initial release —
1 5/10 Revised the Absolute Maximum Ratings and Electrical Characteristics. 1–4
2 7/10 Revised the Absolute Maximum Ratings.2
