EDI816256CA20N44I - White Electronic Designs

1White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

HI-RELIABILITY PRODUCT

EDI816256CA

256Kx16 MONOLITHIC SRAM

FEATURES

■256Kx16 bit CMOS Static

■Random Access Memory

•Access Times of 17, 20, 25, 35ns

•Data Retention Function (LPA version)

•TTL Compatible Inputs and Outputs

•Fully Static, No Clocks

■44 lead JEDEC Approved Revolutionary Pinout

•Ceramic SOJ (Package 322)

•Ceramic Flatpack (Package 323)

■ Single +5V (±10%) Supply Operation

PIN CONFIGURATION

TOP VIEW

September 2000 Rev. 7

PIN DESCRIPTION

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

I/O16

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

A14

A13

A12

A11

A10

A0-17 Address Inputs

LB (I/O1-8) Lower-Byte Control (I/O1-8)

UB (I/O9-16) Upper-Byte Control (I/O9-16)

I/O1-16 Data Input/Output

CS Chip Select

OE Output Enable

WE Write Enable

VCC +5.0V Power

VSS Ground

NC No Connection

The EDI816256CA is a 4 megabit Monolithic CMOS Static RAM.

The EDI816256CA uses 16 common input and output lines and has

an output enable pin which operates faster than address access

time at read cycle. The device allows upper and lower byte access

by use of the data byte control pins (LB, UB).

The devices are available in a fully hermetic 44 lead ceramic SOJ

and a 44 lead Ceramic Flatpack. The Ceramic SOJ is pin for pin

compatible with the commercially available plastic SOJ. This

allows the user the luxury of designing a board that can be used

for both the commercial and military market.

A Low Power version with Data Retention (EDI816256LPA) is also

available for battery backed applications. Military product is

available compliant to Appendix A of MIL-PRF-38535.

White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

NOTE:

Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect

device reliability.

Parameter Unit

Voltage on any pin relative to VSS -0.5 to 7.0 V

Operating Temperature TA (Ambient)

Commercial 0 to +70 °C

Industrial -40 to +85 °C

Military -55 to +125 °C

Storage Temperature, Plastic -65 to +125 °C

Power Dissipation 1.5 W

Output Current 20 mA

Junction Temperature, TJ175 °C

Parameter Sym Min Typ Max Units

Supply Voltage VCC 4.5 5.0 5.5 V

Supply Voltage VSS 000V

Input High Voltage VIH 2.2 — Vcc +0.5 V

Input Low Voltage VIL -0.3 — 0.8 V

Parameter

Symbol

Condition Max Unit

Address Lines CI

= Vcc or Vss, f = 1.0MHz

12 pF

Data Lines CD/Q

= Vcc or Vss, f = 1.0MHz

14 pF

These parameters are sampled, not 100% tested.

CAPACITANCE

(TA = +25°C)

Parameter Symbol Conditions Units

Min Max

Input Leakage Current ILI VIN = 0V to VCC 10 µA

Output Leakage Current ILO VI/O = 0V to VCC 10 µA

Operating Power Supply Current ICC1 WE, CS = VIL, II/O = OmA, Min Cycle 300 mA

Standby (TTL) Power Supply Current ICC2 CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH 60 mA

Full Standby Power Supply Current ICC3 CS ≥ VCC -0.2V CA — 25 mA

VIN ≥ Vcc -0.2V or VIN ≤ 0.2V LPA — 16 mA

Output Low Voltage VOL IOL = 8.0mA 0.4 V

Output High Voltage VOH IOH = -4.0mA 2.4 V

NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V

DC CHARACTERISTICS

(VCC = 5V, VSS = 0V, TA = -55°C to +125°C)

Input Pulse Levels VSS to 3.0V

Input Rise and Fall Times 5ns

Input and Output Timing Levels 1.5V

Output Load Figure 1

NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)

30pF

480Ω

Vcc

Figure 1 Figure 2

255Ω5pF

480Ω

Vcc

255Ω

AC TEST CONDITIONS

TRUTH TABLE

CS WE OE LB UB Mode Data I/O Supply

I/O1-8 I/O9-16 Current

H X X X X Not Select High Z High Z ICC2, ICC3

LH HXX Output

LX XHHDisable

L H Data Out High Z

L H L H L Read High Z Data Out ICC1

L L Data Out Data Out

L H Data In High Z

L L X H L Write High Z Data In ICC1

L L Data In Data In

3White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

AC CHARACTERISTICS – READ CYCLE

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Symbol 17ns 20ns 25ns 35ns

Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units

Read Cycle Time tAVAV tRC 17 20 25 35 ns

Address Access Time tAVQV tAA 17 20 25 35 ns

Chip Enable Access Time tELQV tACS 17 20 25 35 ns

Chip Enable to Output in Low Z (1) tELQX tCLZ 2555ns

Chip Disable to Output in High Z (1) tEHQZ tCHZ 07 07 08010ns

Output Hold from Address Change tAVQX tOH 0000ns

Output Enable to Output Valid tGLQV tOE 10 10 12 15 ns

Output Enable to Output in Low Z (1) tGLQX tOLZ 0000ns

Output Disable to Output in High Z(1) tGHQZ tOHZ 07 07 08010ns

LB, UB Access Time tUBLQV tBA 10 10 12 15 ns

tLBLQV

LB, UB Enable to Low Z Output tUBLQX tBLZ 00 0 0 0ns

tLBLQX

LB, UB Disable to High Z Output tUBHQZ tBHZ 07 07 08010ns

tLBHQZ

NOTE:

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS – WRITE CYCLE

(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)

Symbol 17ns 20ns 25ns 35ns

Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units

Write Cycle Time tAVAV tWC 17 20 25 35 ns

Chip Enable to End of Write tELWH tCW 14 15 17 20 ns

tELEH tCW 14 15 17 20 ns

Address Setup Time tAVWL tAS 0000ns

tAVEL tAS 0000ns

tAVUBL tAS 0000ns

Address Valid to End of Write tAVWH tAW 14 15 17 20 ns

tAVEH tAW 14 15 17 20 ns

tAVUBH tAW 14 15 17 20 ns

Write Pulse Width tWLWH tWP 14 14 15 17 ns

tWLEH tWP 14 14 15 17 ns

Write Recovery Time tWHAX tWR 0000ns

tEHAX tWR 0000ns

Data Hold Time tWHDX tDH 0000ns

tEHDX tDH 0000ns

Write to Output in High Z (1) tWLQZ tWHZ 08 08 08010ns

Data to Write Time tDVWH tDW 10 10 12 15 ns

tDVEH tDW 10 10 12 15 ns

Output Active from End of Write (1) tWHQX tWLZ 0000ns

LB, UB Valid to End of Write tLBLLBH tBW 14 16 18 20 ns

tUBLUBH

NOTE:

1. This parameter is guaranteed by design but not tested.

White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

WS32K32-XHX

WRITE CYCLE - CS CONTROLLED WRITE CYCLE - LB, UB CONTROLLED

TIMING WAVEFORM - READ CYCLE

WRITE CYCLE - WE CONTROLLED

ADDRESS

READ CYCLE 2 (WE HIGH)

AVQV

ELQV

GLQV

ELQX

GLQX

AVAV

EHQZ

GHQZ

LBLQX

UBLQX

LBHQZ

UBHQZ

LB, UB

LBLQV

UBLQV

DATA I/O

ADDRESS

DATA I/O

READ CYCLE 1 (WE HIGH; OE, CS LOW)

AVQX

AVQV

AVAV

DATA 2

ADDRESS 1 ADDRESS 2

DATA 1

ADDRESS

DATA IN

WRITE CYCLE 1, WE CONTROLLED

AVWH

ELWH

WHAX

WLWH

DVWH

WLQZ

WHQX

AVWL

WHDX

AVAV

DATA VALID

HIGH

LBLLBH

UBLUBH

DATA OUT

LB, UB

WRITE CYCLE 2, CS CONTROLLED

AVEH

ELEH

EHAX

WLEH

DVEH

EHDX

AVAV

DATA VALID

HIGH

LBLLBH

UBLUBH

AVEL

ADDRESS

DATA IN

LB, UB

DATA OUT

ADDRESS

DATA IN

DATA OUT

WRITE CYCLE 3, LB, UB CONTROLLED

AVWH

AVUBL

WHAV

AVUBH

WLWH

WLQX

AVAV

DATA UNDEFINED

DATA VALID

UBHAV

WHDX

DVWH

UBLUBH

LB, UB

HIGH ZHIGH Z

5White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

Characteristic Sym Conditions Min Typ Max Units

Low Power Version only

Data Retention Voltage VDD VDD = 2.0V 2 – – V

Data Retention Quiescent Current ICCDR CS ≥ VDD -0.2V – – 2.2 mA

Chip Disable to Data Retention Time (1) TCDR VIN ≥ VDD -0.2V 0 – – ns

Operation Recovery Time (1) TRor VIN ≤ 0.2V TAVAV ––ns

DATA RETENTION CHARACTERISTICS (EDI816256LPA ONLY)

(TA = -55°C to +125°C)

WS32K32-XHX

DATA RETENTION - CS CONTROLLED

DATA RETENTION

CS CONTROLLED

Data Retention Mode

Vcc

CDR

CS = V

-0.2V

4.5V4.5V

NOTE:

1. This parameter is guaranteed by design but not tested.

* Read Cycle Time

White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

PACKAGE 322: 44 LEAD, CERAMIC SOJ

0.445

0.435

1.130

1.110

0.155

0.120

0.050 Typ

DIMENSIONS ARE IN INCHES

PACKAGE 323: 44 PIN, CERAMIC FLATPACK

Pin 1

0.019

0.015

0.038

0.032

0.395

0.385

0.115 Max.

0.050 Typ

0.515

0.505

1.00 Ref

0.045

0.015

0.007

0.003 0.370

0.250

1.130

1.110

DIMENSIONS ARE IN INCHES

7White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520

EDI816256CA

ORDERING INFORMATION

WHITE ELECTRONIC DESIGNS

SRAM

ORGANIZATION, 256Kx16

TECHNOLOGY:

CA = CMOS Standard Power

LPA = Low Power

ACCESS TIME (ns)

PACKAGE TYPE:

F44 = 44 pin Ceramic Flatpack (Package 323)

N44 = 44 lead Ceramic SOJ (Package 322)

DEVICE GRADE:

B = MIL-STD-883 Compliant

M = Military Screened -55°C to +125°C

I = Industrial -40°C to +85°C

C = Commercial 0°C to +70°C

EDI 8 16 256 CA X X X