The V850 Series of high-performance microcontrollers answers many different application system needs. It realizes superlatively low power consumption and low noise while offering high performance and a wide array of functions. The broad V850 product lineup provides optimum solutions for the nextgeneration systems of customers. High performance Product deployment Performance range of 20 to over 300 MIPS with Low-end/Middle-range/ high-end/ASSP single instruction set deployment Additional functions System LSIs Rich middleware Smooth transition to system LSIs lineup Development environment Rich development environment lineup 2 Pamphlet U15412EJ4V1PF INDEX Roadmap/Features 04 V850 Series Product Roadmap * * * 4 NEC Electronics Microcontroller Deployment * 5 Set Application Examples * * * * 5 5 Keys of V850 * Low-End Lineup * * * * * * * * * * * * * 8 Middle-Range Lineup * * * * * * * * 10 High-End Lineup * * * * * * * * * * * * 12 ASSP Lineup * * * * * * * * * * * * * * * 14 Memory Lineup * * * * * * * * * * * * * 18 Package Lineup * * * * * * * * * * * * * 19 CPU Roadmap * * * * * * * * * * * * * * 20 CPU Core Function Comparison * * 20 System LSI Support * * * * * * * * * 21 V850 Series Common Architecture * * * 22 V850E1,V850ES Architecture * * * 26 V850E2 Architecture * * * * * * * * * 27 * * * * * * * * * * * * 6 Product Lineup 08 CPU 20 Variety of Peripheral Functions 28 Memory Access Functions * * * * 28 Analog Circuits * * * * * * * * * * * * * 29 Timer/Counter * * * * * * * * * * * * * 30 Serial Interface * * * * * * * * * * * * * * 31 Other * * * * * * * * * * * * * * * * * * * * * * 32 Performance 34 V850 Series Benchmark * * * * * * 34 Low Power Consumption * * * * 34 Low Noise Countermeasures * * 35 Middleware 36 V850 Series Middleware List * * 36 Speech Recognition * * * * * * * * * 37 JPEG * * * * * * * * * * * * * * * * * * * * * 37 Text to Speech (for Japanese Text) Features * * * * * * * * * * * * * * * * * * * * 38 Rewrite Modes * * * * * * * * * * * * * 38 Flash Specifications List * * * * * * 39 Flash Memory Programmers * * * * * * * * * 37 Flash 38 * * 40 Product Specifications List 42 Low-End Lineup * * * * * * * * * * * * 42 Middle-Range Lineup * * * * * * * * 44 ASSP Lineup * * * * * * * * * * * * * * * 47 High-End Lineup * * * * * * * * * * * * 50 Development Environment 52 Low-Price Development Environment Lineup * * * 53 Development Flow * * * * * * * * * * 54 Development Tools * * * * * * * * * * 54 V850 Series Development Environment * * * 57 Software Product * * * * * * * * * * * * 59 Information Dissemination 62 V850 Series Website * * * * * * * * * 62 Pamphlet U15412EJ4V1PF 3 Roadmap/Features V850 Series Product Roadmap Continuously evolving V850 Series through an expanding product lineup CPU core release completed Product deployment under planning V850E2 core 200 to 400 MHz V850E1 core 150 MHz @ 215 MIPS High-end High-end lineup lineup High performance: On-chip MEMC/DMA * Frequency: 33 to 150 MHz * Memory size: ROM: ROM-less to 512 KB RAM: 4 to 128 KB * PKG: 100 to 240 pins (QFP & FBGA) ASSP ASSP lineup lineup Inverter control DVC control Car audio control Power meter control Dashboard control * Frequency: 16 to 64 MHz * Memory size: ROM: ROM-less to 640 KB V850 core Middle-range Middle-range lineup lineup RAM: 4 to 48 KB * PKG: 64 to 257 pins (QFP & FBGA) 33 MHz @ 38 MIPS Realization of low EMI noise * Frequency: 20 to 34 MHz * Memory size: ROM: ROM-loss to 640 KB RAM: 4 to 48 KB * PKG: 100 to 144 pins (QFP & FBGA) V850ES core Low-end Low-end lineup lineup 20 MHz @ 29 MIPS High cost-performance * Frequency: 20 MHz * Memory size: ROM: 64 to 256 KB RAM: 4 to 16 KB * PKG: 64 to 144 pins (QFP) Standard lineups 4 Pamphlet U15412EJ4V1PF Field-specific lineups High performance NEC Electronics Microcontroller Deployment TM VR5000 Series VR4100 Series 64-bit RISC Inverter, DVC, storage ASSP lineup Upward compatible instruction sets 32-bit RISC VR7700 Series V850E/Mxx high-end lineup V850ES/Sxx, V850/Sxx middle-range lineup Kx1 Series V850ES/Kxx, 78K0/Kxx low-end lineup 78K4 78K0 8/16-bit CISC 17K trol m yste con sing ces ro ta p Da S 78K0S 75X/XL 8 to 16-bit applications 32-bit applications 64-bit applications Price Set Application Examples The V850 Series is suitable for various application fields and raises the commercial value of customer systems. Automotive Engines, dashboards, power steering, ABS Audio Car audio, portable audio, component stereo systems Portable devices PDA, IC recorders Camera DVC, DSC, SLR cameras Computer peripherals Laser-beam printers, inkjet printers, scanners, fax machines Home appliances Air conditioners, refrigerators, washing machines, microwave ovens Industrial equipment Industrial motors, control equipment, vending machines, power meters Video and recording equipment DVD players, D-VHS, industrial cameras Other Electronic instruments, electric bidets, toys, learning devices, remote controllers, etc. Pamphlet U15412EJ4V1PF 5 Roadmap/Features 5 Keys of V850 High performance 5 points supporting the high performance of the V850 Series Performance ranging from 20 to over 300 MIPS with single instruction set High performance >200 MHz = Processor products Data processing V850E2 Not compatible 150 MHz Other manufacturers' 32-bit microcontrollers to 8-/16-bit microcontroller, offer a MIPS *Compared performance 10 or more times higher for the same * * V850E1 33 MHz Other Compatible with up to high-end class manufacturers' 16-bit models with MIPS performance up to 10 times higher microcontrollers 32 MHz V850ES V850 20 MHz System control Compatible at object level! Product lineup Low-end/Middle-range/High-end/ASSP deployment High-End lineup Office equipment V850E2 core ASSP lineup On-chip dedicated hardware V850E1 core V850ES core lineup: Kx1 Series of general-purpose *Low-end microcontrollers for 16 to 32-bit market designed for high V850E/xxx V850ES/xxx V850/xxx Low noise, low power consumption V850 core Automotive V850E/Mxx High performance Industrial Middle-range lineup Communication V850ES/Sxx V850/Sxx cost-performance. lineup: Low noise, low power consumption, *Middle-range large-capacity memory lineup, low-voltage operation support lineup: Designed for high performance, on-chip *High-End memory controller and DMA lineup: Field-specific product lineup, on-chip *ASSP dedicated hardware Additional functions 66 MHz V850 Not compatible frequency, and 2 to 3 times higher at the actual application level (based on NEC evaluation) System operation at frequencies 1/2 to 1/3 those of 8/16-bit microcontrollers is enabled, contributing to lowering system power consumption. The V850 core, V850ES core, V850E1 core, and V850E2 core are upward compatible at the object level. Product lineup Compatible with up to middle-range class Home appliances High cost-performance Low-end lineup Consumer electronics V850ES/Kxx Additional functions Rich middleware lineup Amusement machines Portable devices Electronic dictionaries FAX DSC Handwriting recognition JBIG Toys Car audio ADPCM MH/MR/MMR TTS Image processing of systems with high added value through the *Realization addition of supplementary functions to existing systems * * 6 via middleware Realization of functions heretofore realized with peripheral ICs through V850 + middleware, reducing development time and reducing system costs Rich lineup of video, audio, network-related, and other middleware tuned for V850 Series Human interface Speech recognition Middleware JPEG Home appliances Browser AV equipment Pamphlet U15412EJ4V1PF Networks TM Java TCP/IP Phones System LSI Smooth transition to system LSIs System LSI System Design environment Processes Micro-fabrication technology Multi-layer wiring technology Mixed-process technology High-pin-count packages PC I/F Analog IP Memory Flash V850 Series is also being actively expanded for ASIC *The CPU cores, realizing smooth transition to system LSIs following elements essential for system LSIs are provided *The on a timely basis: <1> Leading-edge process technology <2> High-performance CPU core <3> Rich lineup of IP cores <4> Top-down design environment <5> Flexible application design CPU DSP Chip design environment Synthesis/verification Software development environment Hardware/software coordinated design Logic DRAM middleware IP cores Middleware MPU, DSP, DRAM, SRAM, AV, communication, BUS, high-speed I/O Voice recognition/synthesis AV processing (JPEG1, MPEG1, etc.) Modem 1000 Next-generation core 800 to 1000 MIPS 700 Performance (MIPS) Next-generation process 500 0.13 m process Nx85E2 400 MHz V850E2 V850E2/xxx Nx85E2 266 MHz 300 Nx85E2 200 MHz 200 Nx85E 150 MHz 100 V850E1 0.18 m process Nx85E 66 MHz V850E/ME2 66 33 0.25 m process V850 V850E/MA1 MA2 Under planning MA3 Under development 0.35 m process In mass production Generation Development environment Rich development environment lineup Development environment Utilization of existing functions Improved usability development 78K environment PM Project Manager CC (Compiler) RX (Real-time OS) PM Project Manager Improved versatility Improved performance Debugging support , a low-cost high-performance emulator, and *IECUBE N-Wire CARD, an ultra-low cost on-chip emulator are TM available of better connectivity with target boards, addition *Realization of GUI customization function, improved online help, etc. of shorter development TAT through support *Realization of quick and accurate software development via a rich development environment lineup featuring easy operation and sophisticated functions V850 development environment CA (Compiler) RX (Real-time OS) +RD (task debugger) +AZ (Analyzer) SM (Simulator) Debugging support SM (Simulator) ID (Debugger) Improved usability ID (Debugger) V850 products Realization of highperformance powerful development environment making use of * High performance * General-purpose registers * Large memory capacity TW (Performance analysis tuning tool) IE, IECUBE (In-circuit emulator) Pamphlet U15412EJ4V1PF Support of high speed IE, IECUBE (In-circuit emulator) 7 Product Lineup Low-End Lineup Kx1 Series of general-purpose microcontrollers for 16 to 32-bit market designed for high cost-performance Under planning NEXT Generation Under development In mass production V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ 64-pin version 80-pin version 100-pin version V850ES/KJ1+ 144-pin version Single-power-supply flash On-chip POC/LVI On-chip debugging function DMA function (only KG1+, KJ1+) V850ES/KE1 V850ES/KF1 V850ES/KG1 64-pin version 80-pin version 100-pin version V850ES/KJ1 144-pin version 8-bit microcontrollers 78K0/Kxx 78K0S/Kxx Rich memory and package lineup Development environment usable in common for all series Large array of on-chip peripheral functions common with 78K0/Kx1 of 8-bit microcontrollers Wide voltage range support (2.7 to 5.5 V) Single-power-supply flash lineup (self programming, EEPROMTM emulation support) Low EMI noise design Kx1+ features Kx1 Series lineup Kx1+ are microcontrollers featuring additional functions. Rich memory & package lineup ROM (Bytes) 256K V850ES/Kx1+ V850ES/Kx1 V850ES 128K Runaway detection Watchdog timer running plus High-reliability watchdog timer operating function with uninterruptible Ring OSC on main clock Voltage detection circuit 60/64K On-chip voltage detection circuit (LVI: variable detection voltage) None p eu 96K ss Reset functions External reset, WDT reset plus *On-chip reset detection circuit (POC: Fixed voltage) *Also possible with voltage detection circuit (LVI: Variable detection voltage) None plus Fixed at reset release KJ1 KE1+ KF1 KC1+ KD1+ KB1+ 4 on-chip channels (KG1+, KJ1+) 16K KB1 Oscillation stabilization time reduction KG1 KF1+ m a Se 32K KE1+ KF1 78K0 24K DMA function KE1 lin le 48K KF1+ KG1+ KJ1+ KC1 KD1 KE1 44 52 64 8K Can be reduced with optional function 78K0S 4K A/D converter Conversion time 14 s (min.) Successive approximation mode Conversion interval of 3 s (min.) Successive approximation, scan mode LIN bus interface No hardware 1 hardware channel for each product KU1+ 2K KB1+ KA1+ KY1+ 1K 8 16 20 30 80 100 144 pins Product specifications V850ES/Kx1 Item KE1 128 KB 128 KB 4 KB 256 KB/128 KB 128 KB/96 KB 16 KB/6 KB 256 KB/128 KB/96 KB/64 KB 16 KB/6 KB/4 KB 12 KB/6 KB/4 KB 4.5 V to 5.5 V @ 20 MHz 4.0 V to 5.5 V @ 16 MHz 2.7 V to 5.5 V @ 10 MHz - Address: Multiplexed 16-bitx2 ch 16-bitx 2 ch (256 KB: 3 ch) External bus Timer/counter CSIx2 ch, UARTx2 ch I 2 Cx1 ch* Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask version, Typ.) Package CSIx2 ch, UARTx2 ch I 2 Cx1 ch* CSI with automatic transfer functionx1 ch 10-bitx8 ch Address: Multiplexed/separate Data: 8/16-bit 16-bitx6 ch (256 KB: 7 ch) 16-bitx4 ch (256 KB: 5 ch) 8-bitx5 ch WDTx2 ch Watch timerx1 ch CSIx2 ch, UARTx2 ch I 2 Cx1ch* CSI with automatic transfer functionx2 ch 8-bitx2 ch - 51 64-pin TQFP(12x12 mm) 64-pin LQFP(10x10 mm) ROM correction function, real-time output, key return function 67 150 mW (20 MHz @5V) 80-pin TQFP(12x12 mm) 80-pin QFP(14x14 mm) 2 * : Only Y products have an on-chip I C interface. 8 KJ1 KG1 KF1 V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage Pamphlet U15412EJ4V1PF 84 100-pin LQFP(14x14 mm) 100-pin QFP(14x20 mm) CSIx3 ch, UARTx2 ch UART/I 2 Cx1 ch*, I 2 Cx1 ch* CSI with automatic transfer functionx2 ch 10-bitx16 ch On-chip debug function, ROM correction function, real-time output, key-return function 128 144-pin LQFP(20x20 mm) System cost reduction >Set space reduction! Conventional set Voltage drop detection Voltage detector >Lower number of used ports! WDT independent from CPU clock Micro Port X1 >Higher reliability!!! LVI Peripheral functions on single chip VDD Port X2 Kx1 SeriesNote set >Total set cost reduction! Watchdog IC VDD POC RingOSC RESET Clock monitor Oscillation stop monitoring RESET IC RESET output WDT X1 RESET System reset voltage detection External IC External IC X2 RESET Note: V850ES is supported from Kx1+ Common peripheral functions Large array of peripheral functions common with 8-bit 78K0 Series ROM size(bytes) TMP TM0 TM5 TMH TM8 WT WDT(Powerful WDT) WDT DMA CSI Auto CSI UART UART(LIN) IIC A/D D/A Ring-OSC(8 MHz) Ring-OSC(240 kHz) Sub-OSC REG. Key return ROM correction Real-time Output H.MUL/DIV POC/LVI RESET OUT Clock Monitor 78K0S KY1+ KA1+ KB1+ 1K 2K 4K 2K 4K 8K 4K KU1+ 1K 2K 4K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 KB1 KB1+ KC1 8K 8K 16K 16K 24K 24K 16K 24K 32K KC1+ 16K 24K 32K KD1 8K 16K 24K 32K 78K0 KD1+ KE1 16K 8K 24K 24K 16K 32K 32K 48K 60K KE1+ 16K 24K 32K 48K 60K V850ES KF1 KG1 KJ1 KE1 KE1+ KF1+ KG1+ KJ1+ 128K 128K 64K 256K 128K 64K 256K 128K 96K 256K 128K 96K 256K 96K 256K 128K 256K 128K 128K KF1 KF1+ 24K 48K 60K 32K 60K 1 1 2 2 1 1 2 2 2 2 2 1 2 2 2 1 2 2 2 4 2 2 1 4 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 2 2 2 2 1 2 2 1 2 2 2 2 2 2 2 1 8 ch 1 8 ch 2 1 1 1 1 8 ch 1 8 ch 2 ch 1 8 ch 2 ch Y Y Y Y Y Y Y Y Y Y Y* Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 1 1 2 1 1 2 1 1 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 1 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 ch 4 ch 4 ch 4 ch 4 ch 4 ch 4 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 1 8 ch 1 1 1 8 ch Y Y* Y Y* Y Y* Y Y* Y Y Y Y Y Y Y Y Y Y* Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 1 4 2 2 6 2 2 1 6 2 2 1 6 2 2 1 1 1 1 1 1 1 1 1 1 1 1 4 4 2 3 3 3 2 2 2 2 2 3 3 2 1 1 1 2 2 2 8 ch 16 ch 16 ch 16 ch 2 ch 2 ch 2 ch 2 ch Y* Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y* Y Y Y Y Y Y Y * : Only for WDT/TMH Common to all products Common to V850ES products Common to 78K0 products Common to 78K0S products V850ES/Kx1+ Item KE1+ KJ1+ 256 KB/128 KB 128 KB 128 KB 4 KB - 256 KB 16KB/6KB 12 KB/6 KB 4.5 V to 5.5 V @ 20 MHz 4.0 V to 5.5 V @ 16 MHz 2.7 V to 5.5 V @ 10 MHz - Address: Multiplexed 16-bitx2 ch 16-bitx3 ch External bus Timer/counter Serial interface KG1+ KF1+ V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 MHz (subclock) CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage 8-bitx5 ch WDTx 2 ch Watch timerx1 ch CS I x 1 ch, LIN compatible UART x 1 ch CS I x 2 ch, LIN compatible UART x 1 ch UART x 1 ch, I 2 C x 1 ch*, UART/CSI x 1 ch UART x 1 ch, I 2 C x 1 ch* CSI with automatic transfer function x 1 ch CSI with automatic transfer function x 2 ch 10-bitx8 ch CS x 2 ch, LIN compatible UART x 1 ch UART x 1 ch, I 2 C x 1 ch* A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package Address: Multiplexed/separate Data: 8/16 bits 16-bitx5 ch - 51 64-pin TQFP (12x12 mm) 64-pin LQFP (10x10 mm) POC/LVI, Ring OSC, clock monitor function ROM correction function, real-time output, key return function 67 T.B.D. 80-pin TQFP (12x12 mm) 80-pin QFP (14x14 mm) 84 100-pin LQFP (14x14 mm) 100-pin QFP (14x20 mm) 16-bitx7 ch CSI x 2 ch, LIN compatible UART x 1 ch, UART x 1 ch I 2 C x 1ch*, UART/CSI x 1 ch, UART/I 2 C x 1 ch CSI with automatic transfer function x 2 ch 10-bitx16 ch 8-bitx2 ch 4ch On-chip debug function, POC/LVI, Ring OSC, clock monitor function, real-time output, key-return function 127 (Y products, 128) 144-pin LQFP (20x20 mm) 2 * : Only Y products have an on-chip I C interface. Pamphlet U15412EJ4V1PF 9 Product Lineup Middle-Range Lineup Large-capacity memory, 2.5 V/3 V/5 V general-purpose product lineup Under planning Under development In mass production V850/SC1 5 V low-power version 144-pin version V850/SB1 5 V low-power version 100-pin version 5 V generalpurpose low noise PD703229Y 5 V large-capacity RAM version 100-pin version Pin compatible Same peripheral functions V850ES/SJx V850ES/SGx Single-power-supply flash Larger capacity memory Enhanced peripheral functions Large-capacity internal memory V850ES/SJ2 V850ES/SG2 3 V low-power version 3 V low-power version 100-pin version V850/SA1 144-pin version Peripheral function memory capacity optimization ROM-less 3 V low-power version V850ES/ST2 V850ES/SGx ROM-less, high-capacity RAM 120-/144-pin version Single-power-supply flash Lower voltage Enhanced peripheral functions 3 V generalpurpose, Low power consumption, Low noise V850ES/SA2 V850ES/SA3 Low voltage, super-low power consumption 2.5 V generalpurpose, super-low power consumption Product specifications V850ES/SAx Item V850ES/Sx2 SA2 256 KB/128 KB 16 KB/8 KB 256 KB 16 KB Address: Multiplexed/separate Data: 8/16 bits 16-bit x 2 ch 8-bit x 4 ch WDT x 1 ch Timer/counter A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package SJ2 V850ES 29MIPS (@20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 640KB/384KB 640KB/512KB/384KB/256KB 640KB/512KB/384KB 48KB/40KB/32KB/24KB 48KB/40KB/32KB 2.85 V to 3.6 V 2.2 V to 2.7 V External bus Serial interface SG2 SA3 V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 256 KB CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage CSI x 2 ch, CSI/UART x 1 ch UART x 1 ch, CSI/I 2 C x 1 ch* Address: Multiplexed/separate Data: 8/16 bits CSI x 3 ch, CSI/UART x 1 ch UART x 1 ch, CSI/I 2 C x 1 ch* 10-bit x 12 ch 10-bit x 16 ch 8-bitx2 ch 4 ch Real-time counter (watch function), ROM correction function 82 102 38 mW (20 MHz @ 2.5 V) 100-pin TQFP (14 x 14 mm) 121-pin FBGA (12 x 12 mm) Address: Multiplexed Data: 8/16 bits 16-bit x 6 ch WDT x 1 ch Watch timer x 1 ch CSIx1 ch, LIN compatible UART x 3 ch CSI x 3 ch, CSI/LIN compatible UART x 1 ch CSI x 4 ch, CSI/LIN compatible UART x 1 ch CSI/I 2 C x 1 ch* CSI/I 2 C x 1 ch* LIN compatible UART x 1 ch, CSI/I2 C x 1 ch* LIN compatible UART/I 2 C x 2 ch* UART/I2 C x 2 ch* 10-bit x 12 ch 10-bit x 16 ch 10-bit x 12 ch 8-bitx2 ch 4 ch 4 ch On-chip debugging function, CRC circuit, ROM correction function, Ring OSC, On-chip debugging function, ROM correction function, low voltage detection circuit, clock monitoring function, automotive bus (IEBusTM, aFCAN)Note low voltage detection circuit, clock monitoring function 84 128 84 59.4 mW (20 MHz @ 3.3 V) 66 mW (20 MHz @ 3.3 V) 100 mW (20 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 2 * : Only Y products have an on-chip I C interface. 10 16-bit x 11 ch WDT x 1 ch Watch timer x 1 ch 16-bitx8 ch WDTx1 ch Watch timerx1 ch PD70F3229Y PD703229Y V850ES 29MIPS (@20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 384KB 384KB 32KB 3.5 V to 5.5 V (internal) 3.0 V to 5.5 V (external bus) Note Pamphlet U15412EJ4V1PF 144-pin LQFP (20 x 20 mm) 100-pin LQFP (14 x 14 mm) Products without automotive bus, products with on-chip IEBus, and products with on-chip aFCAN are available. Features PD70F3229Y, 703229Y V850ES/SG2, SJ2 Low EMI noise Large-capacity memory 20 MHz @ 2.85 to 3.6 V operation ROM/RAM:384 KB/32 KB 5 V withstand voltage ports incorporated, and 5 V output is possible by setting the N-ch open-drain output 3 V/5 V mixed system support (Internal: 3.3 V/External: 5 V) Peripheral functions and pin assignment common with V850ES/SG2 On-chip large-capacity single-power-supply flash memory 100-pin LQFP ROM/RAM:640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB, 256 KB/24 KB (SG2 only) Automotive on-chip bus support: IEBus*, aFCAN* (*: Only products with on-chip SG2, SJ2) V850ES/ST2 On-chip debugging function ROM-less version 100-pin QFP (SG2)/100-pin LQFP (SG2)/144-pin LQFP (SJ2) On-chip high-capacity RAM (48 KB) 3.3 V, 34 MHz operation Thin-type, compact type packages supported: 120-pin TQFP/144-pin LQFP V850ES/SA2, SA3 Min. 2.2 V low-voltage operation (including A/D, D/A converter, flash) Low power consumption and high-speed operation during 38 mW @ 2.5 V, 20 MHz operation V850/SA1 Single-power-supply flash Low power consumption and high-speed operation during 66 mW @ 3.3 V, 20 MHz operation ROM/RAM: 256 KB/16 KB (SA2, SA3), 128 K/8 KB (SA2 mask ROM version) Large memory selection Thin and compact package support: 100-pin TQFP (SA2)/121-pin FBGA (SA3) ROM/RAM:256 KB/8 KB, 128 KB/4 KB, 64 KB/4 KB 100-pin LQFP/121-pin FBGA V850/SC1 V850/SB1 Low EMI noise Low EMI noise Large-capacity memory and large memory selection Large-capacity memory (ROM/RAM: 512 KB/24 KB) ROM/RAM:512 KB/24 KB, 384 KB/24 KB, 256 KB/16 KB, 128 KB/8 KB Enhanced peripheral functions for SB1 100-pin QFP/100-pin LQFP 144-pin LQFP Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package * V850/SA1 V850/SB1 V850/SC1 V850ES/ST2 V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 256 KB/128 KB 256 KB/128 KB/64 KB 8 KB/4 KB 2.7 V to 3.6 V (@ 17 MHz) 3.0 V to 3.6 V (@ 20 MHz) Address: Multiplexed/separate Data: 16-bits 16-bitx2 ch 8-bitx4 ch WDTx1 ch Watch timerx1 ch CSIx1 ch, CSI/UARTx1 ch CSI/I 2 Cx1 ch*, UARTx1 ch V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 512 KB/384 KB/256 KB 512 KB/384 KB/256 KB/128 KB 24 KB/16 KB/8 KB 4.0 V to 5.5 V V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 512 KB 512 KB 24 KB 3.5 V to 5.5 V (mask ROM versions) 4.0 V to 5.5 V (flash memory versions) Address: Multiplexed/separate Data: 16-bits 16-bitx10 ch WDTx1 ch Watch timerx1 ch V850ES 34 MHz 10-bitx12 ch 3 ch (internal RAM-on-chip peripheral I/O) - 85 66 mW (20 MHz @ 3.3 V) 56 mW (17 MHz @ 3 V) 100-pin LQFP (14x14 mm) 121-pin FBGA (12x12 mm) 2 : Only Y products have an on-chip I C interface. Address: Multiplexed/separate Data: 16-bits 16-bitx2 ch 8-bitx6 ch WDTx1 ch Watch timerx1 ch CSIx1 ch, CSI/UARTx2 ch CSI/I 2 Cx2 ch* ROM-less 48 KB 3.0 V to 3.6 V Address: Separate/multiplexed (selectable only for CS1) Data: 8/16 16-bitx7 ch WDTx1 ch CSIx2 ch, CSI/UARTx2 ch UARTx2 ch, CSI/I 2 Cx2 ch CSIx1 ch, CSI/UARTx1 ch UARTx1 ch 10-bitx12 ch 6ch (internal RAM-on-chip peripheral I/O) ROM correction function 10-bitx12 ch 6 ch (internal RAM-on-chip peripheral I/O) ROM correction function 10-bitx8 ch 8-bitx2 ch Real-time output 83 125 mW (20 MHz @ 5 V) 124 125 mW (20 MHz @ 5 V) 65 T.B.D. 100-pin LQFP (14x14 mm) 100-pin QFP (14x20 mm) 144-pin LQFP (20x20 mm) 120-pin TQFP (14x14 mm) 144-pin LQFP (20x20 mm) Pamphlet U15412EJ4V1PF 11 Product Lineup High-End Lineup Under planning In mass production High performance, on-chip MEMC/DMA Superscalar On-chip instruction cache & RAM Higher performance On-chip instruction cache On-chip USB V850E2/Mxx V850E2/Mxx Higher performance Parallel execution V850E/ME2 150 MHz @ 215 MIPS 176-pin/240-pin On-chip SDRAM controller V850Ex/Mxx V850E/MA3 80 MHz @ 106 MIPS 144-pin/161-pin Higher performance Large-capacity internal memory V850E/MA1 Higher performance Large-capacity internal memory Enhanced peripheral functions 50 MHz @ 67 MIPS 144-pin/161-pin V850E/MA2 40 MHz, ROM-less 100-pin V850E/MS1 V850E/MS2 33 MHz @ 47 MIPS 144-pin/157-pin 33 MHz, ROM-less 100-pin Features V850E/ME2 V850E/MA1,MA2 Large-capacity internal RAM (128 KB), real-time control 215 MIPS @150 MHz, internal 1.5 V/external 3.3 V operation ROM-less microcontroller 67 MIPS @50 MHz Internal 3.3 V/external 5 V tolerant operation single-chip microcontroller (MA1) On-chip SSCG*, EMI peak reduction ROM-less product lineup also available USB full-speed (function), on-chip debugging function On-chip SDRAM interface 40 MHz @3.3 V ROM-less microcontroller (MA2) 176-pin LQFP/240-pin FBGA On-chip SDRAM interface, DMA ROM/RAM: 256 KB/10 KB (MA1), ROM-less/4 KB (MA1, MA2) Spread Spectrum Frequency Synthesizer Clock Generator * 144-pin LQFP/161-pin FBGA (MA1), 100-pin LQFP (MA2) V850E/MA3 V850E/MS1,MS2 106 MIPS @80 MHz, internal 2.5 V/external 3.3 V operation single-chip microcontroller 47 MIPS @33 MHz, 3.3 V & 5 V single-chip microcontroller (MS1) Large-capacity internal ROM/RAM (512 KB/32 KB) ROM-less product (Max. 40 MHz) lineup available Internal single power supply flash 33 MHz @ internal 3.3 V/external 5 V ROM-less microcontroller (MS2) SDRAM interface, motor control function, on-chip debugging function ROM/RAM: 128 KB/4 KB (MS1), ROM-less/4 KB (MS1, MS2) 144-pin LQFP/161-pin FBGA 144-pin LQFP (MS1)/157-pin FBGA (MS1)/100-pin LQFP (MS2) Product specifications V850E/ME2 Item V850E1 CPU core 215 MIPS(@ 150 MHz) Performance 150 MHz Maximum operating frequency Internal flash memory Internal mask ROM Instruction RAM: 128 KB; Data RAM: 16 KB Internal RAM Instruction:8 KB Cache 1.35 V to 1.65 V (internal)Note Power supply voltage 3.0 V to 3.6 V (external) Memory controller External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package V850E/MA3 V850E1 106 MIPS(@ 80 MHz) 80 MHz V850E/MA1 V850E1 67 MIPS(@ 50 MHz) 50 MHz V850E/MA2 V850E1 40 MHz 512 KB 512 KB/256 KB 32 KB/16 KB 2.3 V to 2.7 V (internal) 3.0 V to 3.6 V (external) 256 KB 256 KB/128 KB/ROM-less 10 KB/4 KB 3.0 V to 3.6 V ROM-less 4 KB 3.0 V to 3.6 V SDRAM, SRAM, etc. SDRAM, EDO DRAM, SRAM, etc. Address: Separate/multiplexed Address: Separate Data: 8/16 bits Data: 8/16 bits 16-bitx 9 ch 16-bit x 8 ch WDT x 1 ch CSI x 1 ch, CSI/UART x 1 ch CSI/UART x 3 ch, UART/I 2 C x 1 ch* CSIx1 ch, CSI/UART x 2 ch UART x 1 ch UART x 1 ch 10-bit x 8 ch 10-bit x 8 ch 10-bit x 8 ch 8-bit x 2 ch 4 ch 4 ch 4 ch ROM correction function PWM output: 2 ch USBx1 ch, on-chip debugging On-chip debugging function function (with trace), PWM output: 2 ch 112 115 78 528 mW (50 MHz @ 3.3 V) T.B.D. 200 mW (150 MHz @ 1.5 V) SDRAM, SRAM, etc. Address: Separate Data: 8/16/32 bits 16-bit x 12 ch 176-pin LQFP (24 x 24 mm) 240-pin FBGA (16 x 16 mm) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) 12 ROM-less 4 KB 3.0 V to 3.6 V (internal) /4.5 V to 5.5 V (external) SDRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 6 ch CSI/UART x 2 ch CSIx2 ch, CSI/UART x 2 ch CSI/UART x 2 ch 10-bit x 4 ch 4 ch - 10-bit x 8 ch 4 ch - 10-bit x 4 ch 4 ch - 79 416 mW (40 MHz @ 3.3 V) 100-pin LQFP (14 x 14 mm) * : Only Y products have an on-chip I2C interface. Pamphlet U15412EJ4V1PF V850E/MS2 V850E1 33 MHz V850E/MS1 V850E1 47 MIPS(@ 33 MHz) 33 MHz (internal ROM products) 40 MHz (ROM-less products) 128 KB 128 KB/96 KB/ROM-less 4 KB 3.0 V to 3.6 V (internal/external) (3 V products) 3.0 V to 3.6 V (internal) (5 V products) /4.5 V to 5.5 V (external) EDO DRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 8 ch EDO DRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 6 ch 57 131 330 mW (40 MHz @ 3.3 V) 218 mW (33 MHz @ 3.3 V) 272 mW (33 MHz @ 3.3 V) 100-pin LQFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) 157-pin FBGA (14 x 14 mm) Note : 1.35 V to 1.65 V : @ 10 MHz to 133 MHz 1.40 V to 1.65 V : @ 10 MHz to 150 MHz Application examples MFP (Multifunction printer) ASIC S/H CCD A/D Instruction RAM 128 KB Data RAM 16 KB PORT INTC DMA SDRAM For storing image data CPU Browser function Communication ASIC system Interface control circuit ROM, Flash SRAM Modem Control panel USB PC LAN IEEE1394 NCU Telephone network RTC Image processing Motor SIO JPEG MH/MR/MMR Document Thermal printer Engine controller RPU Memory Multi Function Printer Printer engine Printing paper ;;; ; ;;; SRAM/ SDRAM V850E/MA3 CPU Internal ROM (512 KB) CG-ROM MEMC Address/Data/Control IEEE1284 I/F DMARQ/DMAAK/TC Internal RAM (32 KB) DMAC ASIC Thermal Printer IEEE1284 interface controller TxD/RxD TMP USB interface controller Distributed control RS-232C driver/receiver Driver Sensor DVD player Stepping motor Thermal head Preceding stage processing block Optical pickup unit Latter stage processing block Preceding stage processing processor Motor driver DVD Player V850E/MA2 USB I/F Uart Applied STB Port Data latch SIO Data Clock Thermistor V850E/MA3 TMQ 4-phase PWM ADC serial interface V850E/ME2 V850E/ME2 Image processing Shooting correction/ binarization SDRAM Disk servo control Display driver V850E/MA2, V850ES/ST2 Sub-CPU Remote control MPEG2 decoder Stream control Optical disk control DAC Video amp ADC Audio DAC Flash memory Key input Fax machine System bus V850E/MS1 Optical system Document Image processing Shading correction/ binarization S/H CCD A/D ROM: 128 KB RPU RAM 4 KB MH/MR/MMR JBIG PORT Memory FAX Machine V850E/MS1 Motor driver INTC Motor Operation panel SRAM CPU DMA SIO ROM RAM for storing image data Communication system AFE NCU Telephone network Printing system Watch Real-time clock Pamphlet U15412EJ4V1PF Image processing Paper Printer engine 13 Product Lineup ASSP Lineup (1) Field-specific lineups In mass production Under development V850E/MA3 On-chip inverter and timer, 80 MHz, 144-/161-pin V850E/IA4 V850E/IA3 V850E/IA1 V850E/IA2 On-chip inverter and timer 50 MHz, 144-pin On-chip inverter and timer On-chip inverter and timer 64 MHz, 100-pin Compact version 64 MHz, 80-pin Compact version 40 MHz, 100-pin Inverter control V850ES/IK1 On-chip inverter and timer, 32 MHz, 64-pin DVC control V850E/SV2 V850/SV1 On-chip VCR servo timer Enhanced peripheral functions 257-pin version, on-chip VCR servo timer 3 V low-power version 176/180-pin, on-chip VCR servo timer Power meter instrument measuring control V850ES/PM1 On-chip 16-bit ADC On-chip 16-bit ADC Features V850E/SV2 V850E/IA3, IA4 For inverter control For camcorders (incl. DVC) 82 MIPS @ 64 MHz, internal 2.5 V/external 5 V operation 32-bit servo timer ideal for camcorder control, boundary scan function, on-chip debugging function, and many other on-chip peripheral functions On-chip 6-phase sinusoidal PWM timer, on-chip operational amplifier/comparator, on-chip high-speed A/D 55 MIPS @ 40.5 MHz, 2.5 V low-voltage/high-speed operation On-chip debugging function (IA4 only) ROM/RAM: 256 KB/12 KB, 128 KB/6 KB (mask ROM version only) 80-pin QFP (IA3), 100-pin LQFP/100-pin QFP (IA4) Large-capacity memory (ROM/RAM: 512 KB/24 KB) Internal single-power-supply flash Compact high-pin-count 257-pin FBGA (14x14 mm, 0.65 mm pitch) V850ES/IK1 V850ES/PM1 For inverter control For power meter control 41 MIPS @ 32 MHz, 4.5 V to 5.5 V (on-chip regulator) On-chip 6-phase sinusoidal PWM timer, POC/LVI, and clock monitor functions On-chip high-resolution, high-accuracy 16-bit A/D converter ROM/RAM: 128 KB/10 KB, ROM-less/10 KB ROM/RAM: 128 KB/6 KB, 64 KB/4 KB 29 MIPS @ 20 MHz, 3.0 V to 3.6 V operation 64-pin LQFP 100-pin LQFP Product specifications V850E/IA2 V850E1 54 MIPS (@ 40 MHz) 40 MHz 128 KB 128 KB 6 KB 4.5 V to 5.5 V Timer/counter V850E/IA1 V850E1 67 MIPS (@ 50 MHz) 50 MHz 256 KB 256 KB 10 KB 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) Address: Multiplexed Data: 8/16 bits 16-bit x 8 ch Serial interface CSI x 2ch, UART x 3ch CSI x 1 ch, CSI/UART x 1 ch UART x 1 ch 10-bit x (6 ch + 8 ch) 4 ch - Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package 14 10-bit x (8 ch + 8 ch) 4 ch FCAN x 1 ch 83 630 mW (50 MHz @ 3.3 V) 144-pin LQFP (20 x 20 mm) V850E/IA3 V850E1 82 MIPS (@ 64 MHz) 64 MHz 256 KB 128 KB 12 KB/6 KB 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) - Address: Multiplexed Data: 8/16 bits 16-bit x 7 ch 53 440 mW (40 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) V850E/IA4 V850E1 82 MIPS (@ 64 MHz) 64 MHz 256 KB 256 KB/128 KB 12 KB/6 KB 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) - 16-bi t x 8 ch 16-bit x 9 ch WDT x 1 ch WDT x 1 ch CSI x 1 ch, CSI/UART x 1 ch CSI x 1 ch, CSI/UART x 1 ch UART x 1 ch UART x 1 ch 10-bitx(4 ch + 2 ch), 8/10-bitx6 ch 10-bitx (4 ch + 4 ch), 8/10-bi tx 8 ch 4 ch 4 ch ROM correction function On-chip debugging and ROM correction functions operational amplifier, comparator, pull-up function Operational amplifier, comparator, pull-up function 50 64 175 mW 175 mW (64 MHz @ 2.5 V) (64 MHz @ 2.5 V) 80-pin QFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 100-pin LQFP (14 x 14 mm) Pamphlet U15412EJ4V1PF V850ES/IK1 V850ES 41 MIPS (@ 32 MHz) 32 MHz 128 KB 128 KB/64 KB 6 KB/4 KB 3.5 V to 5.5 V 16-bit x 7 ch WDT x 1 ch CSI x 1 ch, UART x 2 ch 10-bit x (4 ch+4 ch) ROM correction function, pull-up function, POC/LVI, clock monitor function 39 T.B.D. 64-pin LQFP (14 x 14 mm) Application examples Air conditioner Power module ;;; Photocoupler Photocoupler Power module V850E/IA4 A/D converter Air Conditioner V850E/IA4 INT EVDD VDD PC2925 output PWM output V850E1 64M Hz ROM256K RAM12K Timer 10ch SIO3ch A/D16ch CSI N-Wire INT UART WDT EEPROM DVC Camera control block Indoor unit ;;;; Still picture and moving picture processing block A/D, CDS, SGC (camera pre-processing) CCD Lens driver PWM Fan motor M A/D converter Compressor motor M CCD driver Camera DSP processing Digital Video Camera JPEG field memory Camera DSP SDRAM MPEG4 USB2.0 USB JPEG Card Interface SD memory, etc. JPEG SDRAM System controller & servo control microcontroller V850E/SV2 LCD controller Moving picture processing DV processing IEEE1394 V850E/SV2 LCD panel Video head OSD M Head amplifier S1 video input Mike Mike IEEE1394 DV processing SDRAM Audio & video I/O interface ;; ;; ;; ;; ;; ;;;; Motor driver (motor control) Loading M Drum M Capstan System control/servo control block Power meter V850ES/PM1 16-bit A/D ROM Power Meter V850ES/PM1 3-phase 3-wire Main clock 20 MHz Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package V850/SV1 V850 23 MIPS (@ 20 MHz) 20 MHz 384 KB/256 KB 384 KB/256 KB/192 KB 16 KB/8 KB 3.1 V to 3.6 V @ 20 MHz 2.7 V to 3.6 V @ 16 MHz Address: Multiplexed Data: 16 bits 24-bit x 2 ch, 16-bit x 2 ch 8-bitx8ch, WDT x 1 ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I 2 C x 2 ch* 10-bit x 16 ch 6 ch (internal RAM-on-chip peripheral I/O) ROM correction function, dedicated PWM output x 4, Hsync/Vsync separation circuit 151 82 mW (20 MHz @3.3 V) 176-pin LQFP (24 x 24 mm) 180-pin FBGA (13 x 13 mm) RAM 32bit RISC CPU Timers PMWs WDT RTC CSI CSI UART LCD display On-chip LCD C/D 8-bit microcontroller EEPROM Communication function block Subclock 32 kHz V850E/SV2 V850E1 55 MIPS (@ 40.5 MHz) 40.5 MHz 512 KB 512 KB 24 KB 2.3 V to 2.7 V (internal) 2.7 V to 3.6 V (external) Address: Multiplexed/separate Data: 8/16 bits 32-bit x 1 ch, 16-bit x 12 ch 8-bit x 12 ch, WDT x 1 ch CSI x 5 ch, CSI/UART x 1 ch, UARTx1 ch, I 2 C x 1 ch* V850ES/PM1 V850ES 29 MIPS (@20 MHz) 20 MHz 128 KB/ROM-less 10 KB 3.0 V to 3.6 V @ 20 MHz, 2.7 V to 3.6 V @ 10 MHz, 2.2 to 3.6 V @ 32.768 kHz Address : Separate Data : 8/16 bits 16-bit x 6 ch, 8-bit x 2 ch WDT x 1 ch CSI x 2 ch, UART x 2 ch 10-bit x 24 ch 4 ch On-chip debugging function, boundary scan function ROM correction function, dedicated PWM output: 5 ch 195 134 mW (40.5 MHz @ 2.5 V) 257-pin FBGA (14 x 14 mm) 16-bit x 6 ch ROM correction function, dedicated PWM output: 4 ch Real-time counter (watch function) 80 81 mW (20 MHz @3.3 V) 100-pin LQFP (14 x 14 mm) * : Only Y products have an on-chip I2C interface. Pamphlet U15412EJ4V1PF 15 Product Lineup ASSP Lineup (2) Field-specific lineups In mass production Under development Under planning Dashboard control V850/DB1 On-chip meter driver, On-chip DCAN, On-chip LCD driver, V850ES/FE2 On-chip meter driver On-chip LCD driver FJ2 FG2 FF2 Body control 144-pin 100-pin 80-pin On-chip CAN 64-pin Large-capacity internal flash, on-chip aFCAN, on-chip LIN, POC/LVI V850/SC2 Larger capacity 5 V low-power version 19 MHz, 144-pin, IEBus V850ES/SJx V850ES/SJ2 V850/SC3 Car audio control 3 V low-power version 20 MHz, 144-pin, On-chip aFCAN/On-chip IEBus 5 V low-power version 16 MHz, 144-pin, FCAN V850ES/SGx On-chip CAN/ On-chip IEBus Low noise Larger capacity V850/SF1 5 V low-power version 16 MHz, 100-pin, FCAN Peripheral function/ memory capacity Optimization V850ES/SG2 V850/SB2 3 V low-power version 20 MHz, 100-pin, On-chip aFCAN/On-chip IEBus 5 V low-power version 19 MHz, 100-pin, IEBus V850ES/SGx Features V850/DB1 V850ES/FE2, FF2, FG2, FJ2 For automotive electronics (body control applications) For automotive electronics (body control applications) ROM/RAM : 128 KB/6 KB On-chip large-capacity single-power-supply flash memory On-chip DCAN controller (2 ch max.) ROM/RAM: 512 KB/20 KB, 384 KB/16 KB, 256 KB/12 KB, 128 KB/6 KB 18 MIPS @ 16 MHz, 4.0 to 5.5 V operation On-chip aFCAN controller (4 ch max.), LIN function 128-pin QFP compatible UART, POC/LVI 29 MIPS @ 20 MHz, 4.0 to 5.5 V operation V850ES/SG2, SJ2 64-pin TQFP (FE2)/80-pin TQFP (FF2)/100-pin LQFP For car audio On-chip large-capacity single-power-supply flash memory ROM/RAM : 640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB, 256 KB/24 KB (SG2 only) On-chip IEBus controller (1 ch), on-chip aFCAN controller (2 ch max.) 29 MIPS @ 20 MHz, 2.85 to 3.6 V operation 5 V withstand voltage ports incorporated, and 5 V output is possible by setting the N-ch open-drain output (FG2)/144-pin LQFP (FJ2) V850/SF1 For car audio Low EMI noise On-chip FCAN controller (2 ch max.) ROM/RAM: 256 KB/16 KB, 128 KB/12 KB On-chip debugging function 100-pin LQFP/100-pin QFP (SG2), 144-pin LQFP (SJ2) 100-pin LQFP/100-pin QFP Product specifications Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage FE2 FF2 128 KB/64 KB 128 KB/64 KB 6 KB/4 KB 256 KB/128 KB 256 KB/128 KB 12 KB/6 KB V850ES/Fx2 FG2 V850ES 29 MIPS (@ 20 MHz) 20 MHz 384 KB/256 KB/128 KB 256 KB/128 KB 16 KB/12 KB/6 KB 4.0 V to 5.5 V External bus - Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package 16 16-bit x 7 ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, LIN-compatible UART x 3 ch 16-bit x 6 ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, LIN-compatible UART x 2 ch Timer/counter 10-bit x 10 ch FJ2 384 KB/256 KB 16 KB/12 KB Address: Multiplexed bus Data: 8/16 bits 16-bit x 8 ch WDT x 1 ch, watch timer x 1 ch CSI x 3 ch, LIN-compatible UART x 3 ch CSI x 3 ch, LIN-compatible UART x 4 ch 4 ch aFCAN x 1 ch 51 64-pin TQFP (10 x 10 mm) 10 bit x 24 ch 10-bit x 16 ch - 10-bit x 12 ch 512 KB 20 KB 67 155 mW (20 MHz @ 5 V) 80-pin TQFP (12x12 mm) POC/LVI function, clock monitor function, RAM hold flag aFCAN x 2 ch 84 aFCAN x 4 ch 128 200 mW (20 MHz @ 5 V) 100-pin LQFP (14 x14 mm) Pamphlet U15412EJ4V1PF 144-pin LQFP (20 x 20 mm) - V850/SB2 V850/SC2,SC3 Low EMI noise Low EMI noise Large-capacity memory and large memory selection Large-capacity memory (ROM/RAM: 512 KB/24 KB) ROM/RAM:512K/24KB, 384KB/24KB, 256KB/16KB, 128KB/8KB Enhanced peripheral functions for SB1 On-chip IEBus controller (1 ch) On-chip IEBus controller (V850/SC2 : 1 ch) , On-chip FCAN controller (V850/SC3 : 2 ch max.) 100-pin QFP/100-pin LQFP 144-pin LQFP Application examples Dashboard Integrated body control unit Battery voltage (12 V) Power supply unit V850ES/Fx2 Input interface V850ES/Fx2 Analog input * Sensor inputs Output interface General-purpose I/O Switch inputs * Mirror fold-in switch * Left-right switching switch * Ignition switch * Light control switch * Courtesy lamp switch * Door lock switch * Headlamp control * Tail lamp control * Warning indicator * Power window (passenger seat) control * Power window (rear right seat) control * Power window (rear left seat) control * Lighting equipment control Timer unit General-purpose I/O 10-bit A/D converter External I/O interface Dashboard Internal memory ROM/RAM CPU Serial I/O Interrupt controller LIN controller CAN controller * Dashboard control module * Driver seat door module * Passenger seat door Car audio Antenna speaker Tuner unit MPX PLL Microcontroller (CD control) CD unit V850ES/Kx1 PD703229 Car Audio DAC ASSP for CD PD63761 servo DSP MP3,WMA RF V850/SF1 Driver Audio DSP (or electronic volume) MD unit Power supply block V850/SBx, SF1,SCx V850ES/Sx2 V850/SB2 V850/SCx Microcontroller (Display/key control) V850E/ MA1,MA3 CAN, IEBus driver KEY Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package Address: Multiplexed/separate Data: 16-bits 16-bit x 2 ch, 8-bit x 6 ch WDT x 1 ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I2C x 2 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) IEBus x 1 ch ROM correction function 83 125 mW (19 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) Display unit Driver 4/8 stage LCD Power supply system signal Audio system signal V850/SF1 V850/DB1 V850 18 MIPS (@ 16 MHz) 16 MHz V850 18 MIPS (@ 16MHz) 16 MHz 256 KB 256 KB/128 KB 16 KB/12 KB 3.5 V to 5.5 V (mask version), 4.0 V to 5.5 V (flash version) 3.5 V to 5.5 V @ 32.768 kHz Address: Multiplexed Data: 16-bit 16-bit x 8ch WDT x 1ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I2C x 1 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) FCAN x 2 ch, ROM correction function 128 KB 128 KB 6 KB 4.0 V to 5.5 V SC3 SC2 V850 22 MIPS (@ 19 MHz) 19 MHz/13 MHz (main clock) 32.768 kHz (subclock) 512 KB/384 KB/256 KB 512 KB/384 KB/256 KB/128 KB 24 KB/16 KB/8 KB 4.0 V to 5.5 V ACC (power supply when engine on) Power supply detection IC Automotive communication (CAN, IEBus, etc.) CPU core Performance Maximum operating frequency Battery (continuous power supply) Regulator Microcontroller (CD control) CD (MD) changer unit Item Power amplifier V850 21 MIPS (@ 19 MHz) 19 MHz (main clock) 32.768 kHz (subclock) 18MIPS (@ 16 MHz) 16 MHz (main clock) 32.768 kHz (subclock) 512 KB 512 KB 24 KB 3.5 V to 5.5 V (mask version) 4.0 V to 5.5 V (flash version) Address: Multiplexed Address: Multiplexed/separate Data: 16-bit Data: 16-bits 16-bit x 10ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, CSI/UART x 2 ch UART x 2 ch, CSI/I2C x 2 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) FCAN x 2 ch IEBus x 1 ch ROM correction function ROM correction function 124 110 mW (16 MHz @ 5 V) 120 mW (19 MHz @ 5V) 144-pin LQFP (20 x 20 mm) Pamphlet U15412EJ4V1PF 84 75 mW (16 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 16-bit x 3 ch, 8-bit x 2 ch WDT x 1 ch, watch timer x 1 ch CSI x 3 ch, UART x 2 ch 10-bit x 8 ch meter controlPWM (8-bit) x 24 ch DCAN x 2 ch (flash version)/1 ch (mask version) 107 120mW (16 MHz @ 5V) 128-pin QFP (20 x 20 mm) 17 Product Lineup ;; ;; ;; ;; ;; ;; Memory Lineup Flash memory version Mask ROM version Mask ROM/flash memory version SJ2* SJ2 640K SG2* SG2 MA3* FJ2* MA3* MA3 SJ2* SG2* SC3 SC2 512K SC1 SB2 SB1 384K SV1 SB2 FG2* SB1 FJ2* SV1 MA1 IA4 MA3* SA1 IA1 IA3 SA3 V853 256K KF1+* SA2 KF1* KJ1+* FJ2* KJ1* FG2* KG1+* FF2* KG1* SJ2* SJ2 SG2 3229Y SG2* MA3* SV1 SF1 SB2 SB1 SV1 192K MA1 IK1* SB2 MA1 MS1 IA4 SB1 PM1 KE1+* IA3 SA2 KE1 IA2 SA1 KJ1+* V853 SF1 KJ1 KG1+* 128K KG1 KF1+* KF1 DB1 FE2* FF2* FG2* MS1 96K SV2 KJ1 KG1 KF1 V853 ;; ; 64K ROM less ROM Size (bytes) 18 IK1* KF1 KG1 SA1 FE2* MS1 PM1 ST2* ME2 Instruction RAM : 128KB MS2 MA1 MA2 4K 6K 8K 10K 12K 16K 20K 24K 32K 40K 48K * : Under development RAM size (bytes) Pamphlet U15412EJ4V1PF Package Lineup No. of pins Type Size Pitch Thickness Mounted products 121 pins FBGA (F1) 12x12 mm 0.8 mm 1.13 mm SA1, SA3 No. of pins Type Size Pitch Thickness Mounted products 64 pins LQFP (GB) 10x10 mm 0.5 mm 1.4 mm KE1, KE1+ No. of pins Type Size Pitch Thickness Mounted products 161 pins FBGA (F1) 13x13 mm 0.8 mm 1.13 mm MA1, MA3 No. of pins Type Size Pitch Thickness Mounted products 64 pins TQFP (GB) 10x10 mm 0.5 mm 1.0 mm FE2 No. of pins Type Size Pitch Thickness Mounted products 100 pins LQFP (GC) 14x14 mm 0.5 mm 1.4 mm No. of pins Type Size Pitch Thickness Mounted products 180 pins FBGA (F1) 13x13 mm 0.8 mm 1.13 mm SV1 No. of pins Type Size Pitch Thickness Mounted products 64 pins TQFP (GK) 12x12 mm 0.65 mm 1.0 mm KE1, KE1+ No. of pins Type Size Pitch Thickness Mounted products 120 pins TQFP (GC) 14x14 mm 0.4 mm 1.0 mm ST2 No. of pins Type Size Pitch Thickness Mounted products 157 pins FBGA (F1) 14x14 mm 0.8 mm 0.96 mm MS1 No. of pins Type Size Pitch Thickness Mounted products 80 pins TQFP (GK) 12x12 mm 0.5 mm 1.0 mm KF1, KF1+, FF2 No. of pins Type Size Pitch Thickness Mounted products 100 pins QFP (GF) 14x20 mm 0.65 mm 1.4 mm KG1, KG1+, SB1, SB2, SF1, SG2, IA2, IA4 No. of pins Type Size Pitch Thickness Mounted products 257 pins FBGA (F1) 14x14 mm 0.65 mm 1.13 mm SV2 No. of pins Type Size Pitch Thickness Mounted products 64 pins LQFP (GC) 14x14 mm 0.8 mm 1.4 mm IK1 No. of pins Type Size Pitch Thickness Mounted products 128 pins QFP (GJ) 20x20 mm 0.5 mm 1.4 mm DB1 No. of pins Type Size Pitch Thickness Mounted products 240 pins FBGA (F1) 16x16 mm 0.8 mm 1.13 mm ME2 No. of pins Type Size Pitch Thickness Mounted products 80 pins QFP (GC) 14x14 mm 0.65 mm 1.4 mm KF1, KF1+, IA3 No. of pins Type Size Pitch Thickness Mounted products 144 pins LQFP (GJ) 20x20 mm 0.5 mm 1.4 mm No. of pins Type Size Pitch Thickness Mounted products 100 pins TQFP (GC) 14x14 mm 0.5 mm 1.0 mm SA2 No. of pins Type Size Pitch Thickness Mounted products 176 pins LQFP (GM) 24x24 mm 0.5 mm 1.4 mm SV1, ME2 Pamphlet U15412EJ4V1PF KG1, KG1+, SA1, SB1, SB2, SF1, SG2, PM1, FG2, MS2, MA2, IA2, IA4, V853, PD70F3229Y, 703229Y KJ1, KJ1+, SC1, SC2, SC3, SJ2, ST2, FJ2, MS1, MA1, MA3, IA1 19 CPU Roadmap Performance range of 20 to over 300 MIPS with single instruction set 1000 800 to S MIP V850E2 CPU cores V850E2 CPU cores 400 MHz * Utilization of existing software resources * Maintenance of real-time performance * Pursuit of low power consumption V850E2 CPU cores 266 MHz V850E2 CPU cores 200 MHz V850E1 CPU cores 215 MIPS @ 150 MHz Under planning 143 MIPS @ 100 MHz Under development 96 MIPS @ 66 MHz In mass production 43 MIPS @ 32 MHz 38 MIPS @ 33 MHz 29 MIPS @ 20 MHz 23 MIPS @ 20 MHz V850 CPU cores V850ES CPU cores CPU Core Function Comparison CPU Core Function V850 V850ES V850E1 V850E2 Maximum operating frequency 20/33 MHz 20/32 MHz 66100150 MHz 200266400 MHz 47 80 80 89 Maximum program memory space 16 MB 16 MB 64 MB 512 MB (internal 128 MB) Maximum data memory space 16 MB 16 MB 256 MB Instructions Higher performance High code efficiency 20 16x16 bits32 bit multiplication Interrupt responsiveness 11 to 18 clocks Simultaneous execution of 2 instructions with 3 pipelines that can operate independently from each other Improved pipeline * Non-blocking load/store instructions - Parallel instruction execution (instruction execution in internal ROM) * Addition of branching/load pipe * Shift to 3-operand manipulations in 1 slot 2-byte instructions CISC instructions Multiplier 4 GB * 7-stage pipeline 5-stage pipeline Harvard architecture Addition of C language compatible instructions (Switch instruction, Callt instruction, data conversion instruction, Prepare/Dispose instruction) 32-bit relative branch instruction 3-operand instruction Sum-of-products instruction Bit search instruction 16x16 bits32-bit operation 16x16 bits 32-bit operation 32x32 bits64-bit operation 32x32 bits64-bit operation (32-bit multiply instruction support) 4 to 10 clocks Pamphlet U15412EJ4V1PF System LSI Support Use of same development methods for standard V850 Series products, ASIC microcontrollers Quick market introduction of standard products System optimization through shift to system LSIs CPU core development considering system LSIs Release of cores that support on-chip debugging 2-stage structure consisting of 32-bit sync system bus & 16-bit async peripheral function bus Large choice of peripheral function macros ;;;; ;;;; ;;;; ;;; ;;;; ;;;; ;;;; ;;;; ;;; ;;;; Many supported processes and large range of required performance, and power consumption 0.35m CB-9VX/VM 0.18m CB-12M 0.18m CB-12L 0.25m CB-10VX 0.13m CB-130L V850E1 system configuration example NPB: Peripheral I/O bus VSB: System bus VFB: Internal instruction bus VDB: Internal data bus V850E1 system TIMER NBU85ET Instruction Cache interface cache Instruction memory VFB Data memory VDB NPB I/F PWM NPB CSI CPU Core VSB I/F VSB MEMC NBT85E500 UART DMAC PORT INTC etc ... JTAG DCU User circuit (UDL) External bus JTAG IE Flash memory SRAM I/O UDL1 IP UDL2 RAM V850E2 system configuration example NPB: Peripheral I/O bus VSB: System bus V850E2 system iLB: Internal instruction bus Instruction memory iLB Data memory dLB TIMER NPB I/F CPU core INTC I/F NPB INTC QL85E70x VSB I/F DCU PWM CSI Arbiter UART VSB PORT Instruction cache RCU Data cache JTAG dLB: Internal data bus NBA85E2S etc ... MEMC NBT85E535 DMAC NBA85E300 User circuit (UDL) External bus JTAG IE Flash memory SDRAM Pamphlet U15412EJ4V1PF SRAM I/O UDL1 IP UDL2 RAM 21 V850 Series Common Architecture The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following features. 5-stage pipeline processing Harvard architecture 32 general-purpose registers Simple addressing 2-byte basic instruction set Support of CISC-like instructions Multi-status flags DSP function 32-bit barrel shifter 5-stage pipeline processing The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock. Internal system clock IF Instruction1 Instruction2 ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM IF ID EX MEM WB Instruction1 completion Instruction2 completion Instruction3 completion Instruction4 completion Instruction5 completion Instruction6 completion Instruction3 Instruction4 Instruction5 Instruction6 IF ID EX MEM WB : Instruction fetch : Instruction decode : Instruction execution : Memory access to target address : Write execution result to register WB An instruction is executed each clock Harvard architecture The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely independently from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution. CPU Instruction fetch In the case of an architecture other than the Harvard architecture, the MEM stage of instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2 and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the pipeline operation to become disordered and lowers the instruction execution speed. BCU Instruction bus Pipeline Operation of Non-Harvard Architecture Internal ROM Instruction1 External memory Operand data access ID EX MEM WB IF ID --- EX MEM WB IF --- ID --- EX MEM WB IF --- ID EX MEM WB IF ID EX MEM Instruction3 Data bus Internal RAM Instruction2 IF On-chip peripheral I/O Instruction4 Instruction5 ---:Idles inserted due to bus wait 22 Pamphlet U15412EJ4V1PF WB 32 general-purpose registers The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the development environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency and execution performance. Comparison of Performance/Object Efficiency According to Number of Registers Execution time (s) 12 Byte count (bytes) 4000 For example, looking at the program execution time and code size changes when the number of registers used by the compiler is changed using the servo control 3000 9 module, we can see that the larger the number of registers, the better the program execution speed and 2000 6 the smaller the code size. However, from about 26 registers, the improvement in terms of execution speed 1000 3 and code size becomes smaller, and in the neighborhood of 32 registers, there are no more 0 changes. This is why the V850 Series has been provided with 32 registers as the strict minimum requirement. 0 16 18 20 22 24 26 Byte count Used C program: Servo control module 28 Execution time 30 32 Number of registers Software register bank The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs. Unused registers can be used as a software register bank for which save and restore processing is not required during interrupt servicing or task switching, which increases the processing speed. Register bank interrupt Program execution Interrupt servicing instruction execution Save the program counter, etc., to a save register. Execute the interrupt restore instruction. Restore Program execution Actual interrupt servicing time Normal interrupt Program execution the program counter value, etc., from the save register. Interrupt servicing instruction execution Save general-purpose registers to stacks. Restore general-purpose registers from stacks. Program execution Actual interrupt servicing time User interrupt servicing routine execution time Total interrupt servicing time General-purpose register configuration 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 31 PC System register configuration 0 Zero Register Reserved for Address Generation Name Stack Pointer(SP) Global Pointer(GP) Text Pointer(TP) Operation No. r0 Zero register Always holds "0" r1 Assembler reservation Used as working register for address generation r2 r3 Address/data variable register (If real-time OS being used does not use r2) Stack pointer Used for stack frame generation during function call r4 Global pointer Used when accessing global variables in the data area r5 Text pointer Used as register for specifying the beginning of the text area (program code allocation) r6-r29 Element Pointer(EP) Link Pointer(LP) Application r30 Address/data variable register Element pointer 0 Program Counter Supported by other than V850 CPU core products Used as base pointer for address generation during memory access r31 Link pointer Used during function call by compiler PC Program counter Holds instruction addresses during program execution Pamphlet U15412EJ4V1PF System Register Name Operand Specification LDSR Application STSR Register for saving status during interrupt 0 EIPC 1 EIPSW 2 FEPC 3 FEPSW 4 ECR 5 PSW Program status word 16 CTPC 17 CTPSW Register for saving status during CALLT execution 18 DBPC 19 DBPSW 20 CTBP 6-15, 21-31 Register for saving status during NMI x : Access enabled Register for saving status during exception/debug trap CALLT base pointer Reserved x : Access prohibited Interrupt source register x x LDSR: Instruction to load general-purpose register contents to system register STSR: Instruction to store system register contents to general-purpose register 23 Simple addressing The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline operation. As a result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the performance becomes difficult. The V850 Series avoids this problem by supporting only simple addressing. Pipeline Processing Time and CPU Operating Frequency In case of excessive addressing In case of simple addressing Pipeline processing sequence Instruction fetch All processing is standardized and efficient Address calculation Operating frequency held back by slow processing Execution Memory access Writeback Processing time Processing time Addressing mode Instruction addresses Operand addresses *Relative addressing (PC dependent) *Register addressing Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter. 31 Addressing that accesses the general-purpose register specified by the general-purpose specification field or a system register as an operand. 0 26 25 0 PC *Immediate addressing Addressing of 5-bit data or 16-bit data for manipulation in the instruction code. 31 22 21 0 Signed extension disp22 *Based addressing 31 26 25 0 31 0 Addressing that accesses memory, with the sum of the 0 PC contents of the generalpurpose register (reg1) and Memory subject to manipulation reg1 31 16 15 0 disp16 Signed extension Memory subject to manipulation 16-bit displacement (disp16) as the operand address. *Register addressing (register indirect) Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC). 31 26 25 26 25 0 31 0 reg1 bit of 1 byte of the memory space, with the sum of the reg1 31 *Bit addressing Addressing that accesses 1 0 contents of the generalpurpose register (reg1) and 0 16 15 31 Signed extension 0 disp16 Memory subject to manipulation 16-bit displacement (disp16) that has been sign extended PC Memory subject to manipulation to word length as the operand address. 2-byte basic instruction set The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent to 16-bit CISC microcontrollers. *Improved object efficiency through ROMization programming Object Code Size Comparison (Dhrystone 1.1/Large model) Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/ logic operations, and branching. *To realize ease of use, restrictions on 16-bit fixed-length instructions are partially removed through incorporation of 32-bit instructions. *Bit manipulation instructions, etc. 16-bitV(CISC) 1.00 78K4(CISC) 1.03 V850(RISC) 1.02 1.48 VR/MIPSTM32(RISC) 24 Pamphlet U15412EJ4V1PF CISC-like instructions for embedding (bit manipulation instructions) The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in embedding control. Example: Setting (1) bit 6 of ASIM00 register * Improvement of operability of memory mapped I/ Os for control purposes Bit Manipulation Instruction Item * Manipulation of any 1 bit of byte data in the memory space When Used When Not Used 6, ASIM00[r0] ld.b ori st.b with 1 instruction ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] -4, sp Save r20 r20, 0[sp] ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] 0[sp], r20 Restore r20 4, sp Object size 4 bytes 12 bytes 24 bytes Execution time 4 clocks 4 clocks 8 clocks * Provision of test (tst1)/set (set1)/clear (clr1)/invert (not1) * Effective for reducing object size and execution time since flags can be manipulated in 1-bit units add st.w ld.b ori st.b ld.w add Coding example set1 Multi-status flags In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC microcontrollers. Example: Program that branches to positive/negative/zero according to register contents * Easy recording with assembler * Improved object efficiency and execution speed CISC Microcontroller ZERO : Zero processing PLUS : Positive processing MINUS : Negative processing cmp jz jgt jmp V850 cmp bz bgt br ax, 0 ZERO PLUS MINUS Other Manufacturer's RISC Microcontroller 0, r10 ZERO PLUS MINUS cmp/eq bt cmp/pl bt bra nop #0, r10 ZERO r10 PLUS MINUS ;For delay branching DSP function The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital signal processing such as image and speech processing. V850 * Direct data handling via general-purpose registers * Realization of digital signal processing through generalpurpose CPU * High-speed 16-bit (V850, V850ES CPU), 32-bit (V850E1 CPU) multiply/sum-of-products CPU+DSP General-purpose register CPU DSP CPU SAT flag MUL INT MUL ALU ALU (Multiply: 1 to 2 clocks, sum-of-products: 3 clocks) * Effective for filter operations and matrix operations for feedback calculations in speed, position, and other servo control. Memory 32-bit barrel shifter V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock. Example: 27-bit logical right shift * Shifting of any number of bits (0 to 31) executable in 1 instruction per clock Improved execution speed/object efficiency Effective for extracting arbitrary bit lengths of image data and signed data (extracting code during MH/MR/MMR encoding, etc.) Other manufacturer's V850 RISC microcontroller Processing sequence SHR16 Rn SHR8 Rn SHR2 Rn SHR Rn 4 4 Pamphlet U15412EJ4V1PF SHR 27, Rn Number of instructions 1 Number of execution clocks 1 25 V850E1, V850ES Architecture The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following improvements to the V850 CPU core. Non-blocking load/store Addition of branch/load pipes * Improved bus use efficiency * Shorter interrupt insensitivity period * 2-clock branching * Parallel execution of instructions Pipeline configuration EX * Improved code efficiency * 10 to 15% improvement in object efficiency mainly when C compiler used Load instruction WB br/sld Pipeline ID Address calculation stage ID EX MEM (external memory) T1 T2 T3 WB IF ID EX (MEM) WB IF ID EX MEM Next instruction WB MEM IF ADD instruction Async WB Pipeline Load, store buffer (1 stage each) V850E1 CPU : Fetches instructions and increments the fetch pointer. : Decodes instructions, creates immediate data, and reads registers. : Executes decoded instructions. : Accesses memory of corresponding addresses. : Writes execution results to registers. : Transfers execution data to WB stage. EX (ALU, multiplier, barrel shifter execution) MEM (Memory access) WB (Writeback) DF (data fetch) * Improved absolute performance * Example: Synchronous processing of mov + add Conventional (V850 CPU) Pipeline is stopped until MEM stage complete DF IF IF (Instruction fetch) ID (Instruction decode) Addition of high-level language-compatible instructions Non-blocking load/store Master Pipeline (V850 CPU compatible) ID Shift to 3-operand manipulations in 1 slot WB Effective pipeline processing that uses the Async WB Pipeline when appropriate, according to the instruction. Load instruction IF MEM (external memory) T1 T2 ID EX IF ID EX DF WB IF ID EX MEM ADD instruction Next instruction WB WB Addition of branch/load pipes *Pipeline operation with branch instruction Conventional (V850 CPU) *Parallel instruction execution (when executed by internal ROM) Branch destination determined in EX stage Branch instruction IF ID EX Branch destination instruction MEM WB IF ID Conventional (V850 CPU) ADD instruction (16-bit length) EX MEM WB IF ID Branch instruction (16-bit length) EX (MEM) WB ID EX MEM WB IF ID Next instruction EX MEM Branch destination determined in ID stage V850E1 CPU 2-clock reduction V850E1 CPU 1-clock reduction ADD instruction Branch instruction IF ID MEM WB IF ID IF Branch instruction Branch destination instruction EX MEM ID EX DF ID MEM WB IF ID WB WB Next instruction EX MEM WB * The next branch instruction code is also fetched due to the internal 32-bit bus. Shift to 3-operand manipulations in 1 slot Conventional (V850 CPU) mov add r20(src2), r22(src2), r21(dst) r21(dst) * Sequence from mov to arithmetic instruction is detected in the ID stage, and if dst is the same, the next manipulation is performed. src1 src2 dst : Replace with src2 of mov : src2 of arithmetic instruction : As is * mov + add instructions executable in 1 clock Addition of high-level language compatible instructions The V850E1 and V850ES cores have enhanced the instruction set of the V850 core as follows. switch (2 bytes) mov imm32, reg (6 bytes/2 clocks) * C language switch statement processing * Reduction of address setting code converted into instruction callt (2 bytes)/ctret (4 bytes) * Table-reference branching * Reducing size of call code that frequently V850E1 CPU add r22(src2), r20(src1), r21(dst) appears Data conversion instructions (2 bytes) * char, short type cast executed with 1 instruction * sxh, sxb, zxb, and zxh instructions prepare/dispose (4 bytes) * Function start/end processing executed in 1 instruction unsigned Load * Reduction of unsigned manipulation code 26 Pamphlet U15412EJ4V1PF mul/mulu (4 bytes) * Reduction of array address calculation * Improvement of sum-of-products performance Other * Bit manipulation (register indirect bit specification) * cmov (Conditional Move), divide (div/divu/ divhu) * sasf, endian conversion V850E2 Architecture V850E2 core features V850E2 core Main added functions Real-time performance of 250 MIPS 32-bit relative branch instruction - Operation at over 200 MHz - Support of program space expansion - Long-distance branching performance, elimination of code efficiency losses Inheritance of V850E1 performance and features - Upward instruction compatibility with V850E1 and V850ES cores at object level - Use of 7-stage pipeline - Parallel pipeline configuration (2 parallel superscalar) - 128-bit instruction fetch bus 3-operand instructions (addition of target operations) Support of expanding application software sizes - Higher speed 32-bit sum-of-products operation (32 x 32 + 6464 bits) - Address space (program/data) expansion - Strengthened cache memory support Bit search instruction - Higher speed processing of operations such as multiplex add/subtract (64-bit operation, saturate operation) and bit shift, contributing to higher code efficiency Sum-of-products instruction - Bit row change point search for run length measurement, contributing to increased speed of conversion from integers to floating decimals, etc. V850E2 core CPU pipeline configuration Instruction decode unit R MUL unit ALU unit Instruction decode unit L Instruction execution pipeline left (Lpipe) Write back unit ALU unit Register file Instruction execution pipeline right (Rpipe) BSFT unit Dispatch unit Instruction buffer Instruction fetch unit (Bpipe) Instruction fetch pipeline (Fpipe) 2 instructions simultaneously executable using 2 instruction execution units MEM unit Data memory, data cache Instruction memory, instruction cache V850E2 core CPU pipeline operation Execution of up to 2 instructions/clock possible (dependent on instruction set) Time flow <1> <2> IF DP <3> <4> <5> <6> AT DF <7> <8> <9> <10> <11> <12> Internal system clock Processing simultaneously performed by CPU Instruction1 ...... Instruction2 ...... ID EX ID EX Instruction3 ................. IF WB WB ID EX ID EX AT DF Instruction5 ............................ IF WB ID EX ID EX AT DF WB DP Instruction6 ............................ Instruction7 ...................................... IF WB ID EX ID EX AT DF WB DP Instruction8 ...................................... Instruction9 ................................................. IF WB ID EX ID EX AT DF WB DP Instruction10 ................................................. Instruction11 ............................................................ IF : Instruction fetch DP : Dispatch ID : Instruction decode EX : Instruction execution AT : Address transfer DF : Data fetch WB : Writing execution result to register WB DP Instruction4 ................. IF WB ID EX ID EX AT DF WB DP Instruction12 ............................................................ WB Instruction 2 Instruction 4 Instruction 1 Instruction 3 Instruction 5 Instruction 7 Instruction 9 Instruction 11 completion completion Instruction 6 Instruction 8 Instruction 10 Instruction 12 completion completion completion completion completion completion Instructions executed at each clock Pamphlet U15412EJ4V1PF 27 Memory Access Functions SDRAM controller DMA controller (provided in V850E products) Products: V850E/MA1, MA2, MA3, ME2 SDRAM connectable without external circuit CAS latency: 2, 3 supported CBR (automatic) refresh: Self refresh supported Products: V850E/MA1, MA2, MA3, MS1, MS2, IA1, IA2, IA3, IA4, ME2, SV2 Transfer targets: Memory-peripheral I/O, memorymemory Transfer mode: Single, single step, block transfer Transfer units: 8/16 bits Transfer type: 1-cycle transfer, 2-cycle transfer Number of transfers: 65536 Max. A1-A12 A0-A11 A21, A22Note A12, A13 D0-D15 DQ0-DQ15 SDCLK CLK SDCKE CKE CSn Internal RAM CPU core On-chip peripheral I/O External I/O CS RAS SDCAS CAS LDQM LDQM UDQM UDQM WE External RAM 8/16 bit bus WE V850E/MA1 Bus interface DMA SDRAS Data control Address control Count control External ROM 64 Mb SDRAM (1 Mword x 16 bits x 4 banks) Channel control Note The address signal used differs depending on the SDRAM product. DMA controller (provided in V850/Sxx products) Products: V850ES/SA2, SA3, SG2, SJ2, KG1+, KJ1+, FG2, FJ2 PD703229Y, 70F3229Y Transfer targets: Memory-peripheral I/O, memory-memory Transfer mode: Single Transfer units: 8/16 bits Transfer type: 2-cycle transfer Number of transfers: 65536 Max. Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3 Transfer targets: Internal RAM-on-chip peripheral I/O Transfer mode: Single Transfer units: 8/16 bits Transfer clock: 4 clocks Min. Number of transfers: 256 Max. Internal RAM On-chip peripheral bus CPU core On-chip peripheral I/O External I/O External RAM 8/16 bit bus External ROM 28 Bus interface DMA Data control Address control On-chip peripheral I/O CPU core Internal RAM DMA Transfer source address Count control Transfer destination address Channel control Number of transfers Pamphlet U15412EJ4V1PF Internal bus DMA controller (provided in V850ES products) 8/16bit-data Analog Circuits A/D converter High-speed A/D converter Products: V850ES/PM1 High-accuracy 16-bit resolution Sampling frequency selector (4.340 kHz/2.170 kHz) Support of up to 3 lines and 4 phases through multiple input channels Products: V850E/IA3, IA4 Simultaneous 10-bit A/D converter sampling for 2 circuits On-chip operational amplifier (2.5 x/5 x) for input level amplification On-chip overvoltage detection comparator ;; ; ; ;; ; ; ;;; modulator ANI00 ANI01 ANI20 ANI21 ANI40 ANI41 Register & selector Digital filter (LPF) modulator ANI10 ANI11 ANI30 ANI31 ANI50 ANI51 AVDD Digital block Input circuit CPU AMP ANIn1 Digital filter (HPF) AMP ANIn2 INTAD Internal reset signal Internal system clock Sample & hold circuit Voltage comparator Array AMP ANIn3 Successive approximation register (SAR) CMP CMP VREF buffer AVREFIN ANIn0 Selector Analog block Internal bus AVDD AVSS CMPREF AVSS INTCMPn CMP ADTRGn Edge detection/noise elimination circuit TTRGn0 TTRGn1 Selector Reference generator AVREFOUT Control circuit INTADn A/Dn conversion result register m (ADAnCRm/ADAnCRmH) A/D converter (multi-stage buffer type) D/A converter Products: V850E/MA1, MA3, ME2, IA1, IA2, MS1, SV2, V850/SV1, V853, etc. Conversion startable by software or hardware 8 on-chip conversion result registers (24 for SV2) Select/scan mode switching possible Products: V850ES/KG1, KJ1, KG1+, KJ1+, SA2, SA3, SG2, SJ2, V850E/MA3, V853 R-2R ladder method (except for V850ES/SA2, SA3) R string method (V850ES/SA2, SA3 only) 8-bit resolution Operation mode: Normal mode/real-time output mode ANI0 Tap selector Resistor string Selector Conversion value setting register 0 ANIn Successive approximation register AVREF AVSS AVREF1 R-2R ladder or R string ADTRG Conversion control circuit INTAD ANO0 AVSS Conversion value setting register 1 Conversion result register 0 Conversion result register 1 Conversion result register 2 Conversion result register 3 Conversion result register 4 Conversion result register 5 R-2R ladder or R string Conversion result register 6 Conversion result register 7 Pamphlet U15412EJ4V1PF ANO1 29 Timer/Counter Timer configuration during inverter control Up/down counter Products: V850E/IA3, IA4, MA3, V850ES/IK1 0% and 100% output and 6-phase PWM output with deadtime possible Switchable anytime/batch overwrite for compare register A/D converter conversion start trigger generator Products: V850E/IA1, IA2, IA3, IA4, MA3, ME2 16-bit 2-phase encoder input possible Compare registers: 2 Capture/compare registers: 2 TMQ TMQOP INTOVF 16-bit counter Output control Clear Interrupt signal Output period generation 16-bit capture/compare TM output control 16-bit capture/compare Timer Output Interrupt signal U 16-bit capture/compare Timer Output Interrupt signal 16-bit capture/compare INTCC0 U 6-phase PWM output controller Interrupt signal Output duty generation Capture/compare register Capture/compare register V V TCLR INTCC1 W Timer Output W CLR circuit control A/D operation trigger control Sync start supported TMP A/D capture timing generation A/D trigger 16-bit up/down counter timer Selector TCUD Edge detection circuit Output control TO Compare register INTCM0 TIUD Compare register INTCM1 32-bit servo timer Real-time counter Products: V850E/SV2 32-bit timer unit for servo control Capture registers: 12 Compare registers: 2 External input detection circuit with 1 to 256 dividers On-chip 8-bit mask timers: 2 Products: V850ES/SA2, SA3, PM1 On-chip week, day, hour, minute, second counters Counting up to 4095 periods Support of interval interrupt generation at fixed intervals selectable from: 0.015625 s, 0.03125 s, 0.0625 s, 0.125 s, 0.25 s, 0.5 s, 1 s, 1 mn, 1 hr, 1 day fxx-fxx/8 (4) { 6 Clear SLCLK Count clock = 32.768 kHz INTOV3 TM3 (32-bit) 2ch (x=0-1) ICP3x Noise elimination TRGx Edge detection Divider Noise elimination TRGy Edge detection Divider EDVCMx Mask CPTTRGx timer CP3x (32-bit) Capture fXT INTCP3x Prescaler fBRG 3 2ch (y=2-3) ICP3y EDVCMy CP3y (32-bit) Selector Edge detection Clear & count control Capture INTCP3y Selector Noise elimination TI3 Selector TI3 0.015625 s/0.03125 s/0.0625 s/0.125 s/0.25 s/0.5 s INTTI3 fxx Subcount register (15 bits) 1s 1 mn Second count register (6 bits) 1 hr Minute count register (6 bits) Hour count register (5 bits) 1 day Day count register (3 bits) Week count register (12 bits) Count enable/ disable circuit 8ch (z=4-11) ICP3z Noise elimination TRGz Edge detection CP3z (32-bit) CM30 (32-bit) CM31 (32-bit) 30 Capture Match Match INTCP3z INTCM30 INTCM31 Pamphlet U15412EJ4V1PF Second count specification register Minute count specification register Hour count specification register Internal bus INTRTC Day count specification register Week count specification register INTROV Serial Interface Serial interface with automatic send/receive function LINBus Products: V850E/SV2, V850ES/KF1, KG1, KJ1, KF1+, KG1+, KJ1+ 32-byte internal buffer RAM Automatic send/receive function *1 to 32 bytes of transfer bytes specifiable *Transfer interval specifiable (0 to 63 clocks) *Single transfer/repeated transfer specifiable Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2 Low-cost 1-line network bus Sync break field (SBF) send/receive possible through hardware (Send: 13 bits SBF 20 bits; Receive: SBF 11 bits) Also generally usable as UART Port configuration for LIN reception Internal bus DIRn SIAn Buffer RAM (32 bytes) Automatic data transfer address point specification register SBF automatic detection Automatic data transfer address count register Timer output selectable as source clockAny baud rate selectable LIN reception pin Reception circuit External interrupt pin Serial I/O shift register Selector Edge detection interrupt Timer input pin Selector Serial clock counter Interrupt generator Serial transfer control circuit Selector Wakeup detection Internally connectable by software, so external connection not required! Flag SOAn SCKAn Timer Capture input Baud rate error detection through capture timer INTCSIAn Flag fxx/6-fxx/256 LIN transmission circuit SBF automatic transmission LIN transmission pin Transmission circuit MASTERn Selector 6-bit counter Able to invert output Timer Flag Automatic data transfer interval specification register Timer output selectable as source clock Any baud rate selectable!! CAN IEBus controller Products: V850ES/SG2, SJ2, FE2, FF2, FG2, FJ2, V850E/IA1, V850/SF1, SC3, DB1 CAN protocol ver. 2.0 Part B (send/receive of standard and extended frames) Max. transfer rate: 500 kbps (V850/DB1 only) 1 Mbps 32 message buffer Products: V850ES/SG2, SJ2, V850/SB2, SC2 Communication mode 1 supported Max. transfer bytes: 32 bytes/frame Max. transfer speed: Approx. 17 kbps CAN module Register block CTXD CRXD CAN protocol transfer block MAC (Message Access Controller) Control circuit Interrupt request IETX IERX Transmission block Reception block Bit controller CAN RAM (message buffer) Field controller Control block Pamphlet U15412EJ4V1PF Interrupt request 31 Other USB SSCG function (Spread spectrum Frequency Synthesizer Clock Generator) Products: V850E/ME2 Compliant with Universal Serial Bus Specification Support of 12 Mbps (full speed) transfer Many endpoint configurations Products: V850E/ME2 EMI peak noise reduction through input frequency modulation Large reduction in noise countermeasure time and cost possible Frequency modulation rate and modulation period changeable by register setting TCn Frequency modulation rate UFDRQn DMAAKn Endpoint Control transfer: Endpoint0R (64 bytes)/Endpoint0W (64 bytes) Bulk transfer 1: Endpoint1 (64 bytes x 2)/Endpoint2 (64 bytes x 2) Bulk transfer 2: Endpoint3 (64 bytes x 2)/Endpoint4 (64 bytes x 2) Interrupt transfer1/2: Endpoint7 (8 bytes)/Endpoint8 (8 bytes) USB Selector USB function 0 DMA channel select register (UF0CS) Modulation period With frequency modulation rate of -3%Modulation period: 13 to 27 kHz Without frequency modulation I/O Buffer SIE UDM USBSP2B UDP USBSP4B Improvement of 10 dB or more INTUSB0B INTUSB1B RSUM_OUT INTUSB2B INTRSUM fUSB(48 MHz) USB function 0 buffer control register (UF0BC) Remark n = 0 to 3 ROM correction function Explanation of ROM correction operation Products: V850 core :V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 V850E, V850ES cores :V850ES/SA2, SA3, SG2, SJ2, KE1, KF1, KG1, KJ1, KE1+, KF1+, KG1+, PM1, IK1, PD703229Y, 70F3229Y, V850E/MA3, SV2, IA3, IA4 Instructions of address to be modified inserted to replace DBTRAP instruction (JMP r0 instruction in case of V850 core), branching to 0060H (0000H in case of V850 core) Program modification following switch to mask ROM possible Modified addresses: 4 points, 8 pointsNote Note V850E/SV2 RESET Normal flow No ROM correction request flag = 0? ROM correction request flag clear Download modification program Instruction address bus Correction address enable setting information Initialization Jump to modification program Modification program download Correction address = XXXX ROM correction enable flag = 1 Modification program execution Correction address setting ROM correction enable Return to internal ROM Correction point Internal ROM instructionNote DBTRAP generation block Next processing... Main routine Instruction replacement part Output trigger control circuit Note JMP r0 instruction in case of V850 core Instruction data bus Note JMP r0 instruction for the V850 core 32 Pamphlet U15412EJ4V1PF Internal RAM Read modification program to RAM Replace DBTRAP instructionNote Comparator ROM correction flow Yes External ROM, EEPROM, etc. ROM correction address register Internal ROM Low-voltage detection circuit (LVI) Clock monitor function Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1 Detection voltage level changeable by software Usable instead of reset IC, contributing to lower system cost Detection voltage not changeable after mode transition (security protection) Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1 Monitors abnormal stops of main clock with internal Ring- Oscillator During abnormal stop, entire system can be set to reset status Prevention of destruction due to system deadlock or runaway Internal reset signal reset Main clock VDD Reset signal Selector Detection level selection Resistor Resistor Resistor VDD + --- Ring oscillator clock enable Interrupt signal Flag Reference voltage Flag Main clock oscillation monitoring Reset upon abnormal stop Run/stop settable by software On-chip debugging function Boundary scan function Products: V850E/ME2Note, V850E/MA3, IA4, SV2, V850ES/KJ1, KJ1+, SG2, SJ2, FE2, FF2, FG2, FJ2, PD70F3229Y Realization of on-chip debugging of microcontroller with DCU (Debug Control Unit) Compact and low-cost PC card-type emulator Flash programmer function Integrated debugger (ID850) supported Products: V850E/SV2 Use of JTAG (Joint Test Action Group) communication specifications, IEEE1149.1 compliant Progressive scan of device's external I/O pins, test data input/ output possible Connection check of devices soldered on user board possible : Boundary scan target pin : JTAG interface pin : Boundary scan cell Boundary scan register Note Trace function support is possible by using the RTE-2000-TP made by Midas Lab Co., Ltd., or PARTNER-ET II, PARTNER-J made by Kyoto Micro Computer Co., Ltd. I/O I/O Internal logic I/O I/O Target system Bypass register *Break function *Execute function Notebook PC *Pin mask function *Flash programmer function *Execution time measurement *Non-use of user resources ries 0 Se h Flas V85 Decoder TDI Instruction register Selector N-Wire CARD (IE-V850E1-CD-NW) Selector On-chip debug emulator TDO TCS TMS TPA controller TRST Pamphlet U15412EJ4V1PF 33 V850 Series Benchmark The V850 Series realizes high speed, high performance, and high code efficiency. Minimum instruction execution time V850 Series performance 0.2 s Cycle time 0.4 s Performance comparison 32-bit RISC V850ES/Kxx 0.05 4.1 V850ES-20 MHz 16-bit CISC A 16bit 20 MHz 8-bit CISC B 32bit 50 MHz 0.125 78K4 1.7 1.0 A 16bit 16 MHz 0.20 78K0/Kx1 3.6 0 2 1 3 5 (Relative comparison) 4 Code size comparison 0.24 78K0 0.97 V850ES-20 MHz 1.00 A 16bit 20 MHz 0.40 78K0S 1.37 A 16bit 16 MHz 1.18 B 32bit 50 MHz : 12 MHz (0.168 s) supported for some products : 10 MHz (0.2 s) supported for some products 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 (Relative comparison) 1.4 * NEC Electronics measurement results using sample program Low Power Consumption Thanks to thorough energy-saving design, a superior current/performance ratio of 1.1 to 0.7 mA/MIPS is realized, particularly for V850ES and V850/Sxx products. As a result, a reduction in power consumption to 1/5 or less compared to 16-bit CISC microcontrollers of similar performance is realized. Lower system power consumption and higher performance are simultaneously realized through this extremely high power performance. Power performance mA/MIPS 10 Realization of low consumption current that is 1/5 or less compared to 16-bit CISC of similar performance Consumption current/performance 8-bit CISC 9.2 mA/MIPS 16-bit CISC 7.3 mA/MIPS 5 1.1 mA/MIPS 1.1 mA/MIPS V850/SV1 V850/SB1 ;; ;; 0.9 mA/MIPS V850/SA1 0.7 mA/MIPS V850ES/SA2, 3 0 Clock gear function Standby mode CPU Consumption current Normal operation mode Reduction to 1/5th through clock gear (1/8) Approx. 1/2 HALT mode Reduction to 1/10th through clock gear (1/32) Approx. 1/10 IDLE mode Sub normal operation mode Reduction to 1/400 through switch from main clock to subclock fxx Operating frequency (20 MHz) 34 fxx/8 (2.5 MHz) fxx/32 (625 kHz) Peripheral Watch Oscillation circuit function timer Main Sub fXT (32.768 kHz) or Approx. 1/400 Sub IDLE mode or Approx. 1/4000 STOP mode (sub operation) Approx. 1/4000 STOP mode (sub stop) Approx. 1/15000 Consumption current Pamphlet U15412EJ4V1PF Operating Stopped Low Noise Countermeasures Minimizing the influence of electromagnetic interference (EMI) emitted from the microcontroller and the influence of noise applied to the microcontroller (EMS) is a high priority, particularly for AV equipment such as car audio systems, and thus superior noise performance is required of microcontrollers. Various noise countermeasures are implemented in the V850 Series, and noise performance equivalent or superior to that of 16-bit products has been realized. EMS countermeasures EMS measurement results (power supply coupling measurement) Use of PLL for oscillation circuit Noise application voltage LPF 2.0 kV or higher Existing V850 products (PLL-less products) VCO To CPU peripheral functions Oscillation circuit 1.0 kV V850ES/KJ1 Voltage control oscillator Phase comparator 0 kV V850ES/KJ1 (flash version) Divider Existing V850 products VDD=5 V VDD=5 V Resonator: 4 MHz Resonator: 16 MHz Internal operation frequency: 16 MHz (PLL = ON) Internal operation frequency: 16 MHz High-frequency noise cut through PLL filter EMI noise countermeasures: Power supply circuit countermeasures CPU power supply separation Insertion of capacitance between VDD and GND Vport Vcpu Port power supply separation Reg. (OFF setting possible) I/O PORT CPU OSC AMP GNDport GNDcpu Due to the relation between the power supply and GND pad positions and the lead frame, placement is done so as to lower the power supply impedance. EMS noise measurement results Power supply voltage Operating frequency 0 -10 5V 78K0 10MHz V850ES/KJ1 16MHz -20 -30 -40 Noise [dBm] Existing 78K0 -50 -60 -70 -80 -90 V850ES/KJ1 70 75 80 85 90 95 100 Frequency [MHz] Pamphlet U15412EJ4V1PF 105 110 115 120 35 V850 Series Middleware List Middleware plays a major role for maximizing processor performance and realizing high-speed processing of complex data with flexibility and ease. NEC Electronics offers a large array of middleware that is optimized for the CPU architecture and importantly contributes to shortening development time, while also facilitating additions and changes to dedicated functions whose implementation as hardware for devices, etc., used to have high cost and time requirements, and the creation of user-friendly interfaces. Shift to middleware accelerating deployment to optimum processors Dedicated device development not required Shortening of development time Reduction in development cost Realization of latest technology and functions Maximization of system added value An increasing number of processors optimized for various systems and based on NEC Electronics' original technology and the superb technology of third parties, as well as other technologies that have been established as standards, are being deployed from. Customers Easy performance enhancement and function expansion System proposal Demo systems Evaluation systems Planning Middleware development Solution development System design Easy creation of user-friendly interface Consultation Performance verification Development Multimedia processing realizable just with CPU Development support system Original NEC technologies Standards Integration Customization V850 Series Mass production Realization of higher reliability and quality IP vendors RISC Maintenance Platforms Middleware merits: Next-generation processors Middleware product list Category Image Speech Sound Middleware V850 Series JPEG MPEG-4/H.263 Video Text To Speech Speech CODEC Recognition Japanese G.723.1 Annex A/C G.726 (ADPCM) G.729 Annex A/B AMR MPEG-4 CELP Acoustic echo canceller (for hands-free operation) AEC Noise suppressor 3GPP-NS Audio decoder AAC MP3 WMA Sound generator for cellular phone ringer melody Speech recognition Handwriting recognition Security Internet Storage V850 Series Middleware Category Encryption Fingerprint recognition TCP/IP PC-compatible file system Japanese (large vocabulary) Japanese (small vocabulary) Chinese (small vocabulary) English (small vocabulary) Japanese (input frame required) Japanese (input frame not required) CIPERUNICORN : Development completed Middleware performance list Middleware JPEG G.726 (ADPCM) Speech recognition (small vocabulary) 36 Performance QVGAx24 : Enc0.32s/Dec0.24s 32Kbps, 16Kbps 0.4s Power (MIPS) --Enc8/Dec8.2 19 (20 words) 63 (100 words) Pamphlet U15412EJ4V1PF ROM 17.5 KB 9 KB 82 KB RAM 15 KB 80 B 3.5 KB (15 words) Speech Recognition Speech recognition is realized on a single chip using the memory and peripheral I/Os in the V850 Series. Ideal for applications such as games and home appliances that must feature speech recognition but are subject to large restrictions. *Realization of speech recognition with memory and peripheral I/Os contained in V850 Series *Expansion of number of recognized words Recognized number of words: 30 words (in case of V850/SA1, 20 MHz) Expansion of number of recognized words Memory capacity V850 Series Speech recognition system configuration example V850/SA1 (Internal 20 MHz) *Realization of speech recognition using only memory and peripheral I/Os contained in V850 Series *Expansion of number of recognized words Main dictionary Jim, Marc, Sally Sub dictionary 2 . . . Sub dictionary 3 LPF ROM/RAM Sub dictionary 1 Friend Company Reservation Smith, Jones, Brown ROM Description Capacity Program 26 KB Data 40 KB ROM/RAM mix Recognition dictionary (in case of 15 words) 0.5 KB RAM Work area (in case of 15 words) 3.4 KB Stack 0.3 KB ANA, JAL, ticket Recognition dictionary and work vary depending on the number of recognized words. Internal ROM Internal RAM recognition *Speech evaluation system Mike amp A/D (1 ch) NEC Electronics provides an environment allowing easy evaluation for the introduction of speech recognition. For details and the purchasing method, consult your NEC Electronics sales representative. JPEG Text to Speech (for Japanese Text) *Conforms to JPEG international standard *Versatile compression and decompression processing *Speech synthesized from Japanese Kana and Kanji text (SJIS code) *Versatile speech synthesis Conforms to DCT baseline process (non-reverse coding) Synthesis of female voices possible <Compression functions> Various adjustable parameters such as intonation and reading speed *Rhythm of synthesized speech (pitch, phoneme duration) can *User-customizable VRAM input module *User-specified Huffman and quantization tables be designed (Speech Designer compatible) *APPn marker insertion Speech synthesis using natural rhythm possible (synthesis of more natural sounding speech) *Support of special characters (Reading of special characters settable in user dictionaries) Synthesis speed * *Compression suspend function <Decompression processing> *User-customizable VRAM output module *Support of various JPEG markers (DRI, RSTn, DNL) *Decompression suspend function Works also with V850/SA1 (20 MHz). (However, text is placed in internal ROM.) JPEG performance Processing Time Sample Ratio CPU 4:1:1 (Quality75) V850E/MS1 (33MHz)Note QVGA (320x240x24) ROM/RAM Description Decompression Compression Decompression 0.32 s 0.24 s 1.3 s 0.97 s ROM Note Programs are placed in internal ROM, and stack and (some) work areas are placed in internal RAM. The data and other works are placed in external RAM. Program Data 35 KB 1.2 MB RAM Compression Decompression Compression Decompression 10 KB 7.5 KB 5 KB 10 KB 126 KB Dictionary data (approx. 80,000 words) Phoneme data Memory ROM Capacity VGA (640x480x24) Compression 567 KB (8 kHz sampling) 684 KB (11 kHz sampling) RAM Pamphlet U15412EJ4V1PF Work 160 KB Stack 508 bytes Speech output buffer 12 KB 37 Features Flash microcontroller lineup To answer the need for shorter development time and maintenance after shipping, NEC Electronics offers microcontrollers with on-chip flash memory available in a large range of capacities from 64 KB to 640 KB as part of the V850 Series. NEC Electronics' flash memory microcontrollers offer the Flash Memory Size (bytes) 64K RAM size (bytes) 4K 128K 4K 6K 192K 8K 12K 16K 256K 8K 10K 384K 12K 16K 16K 24K 640K 512K 32K 20K 24K 32K 48K V850ES/KE1 V850ES/KF1 / V850ES/KG1 / V850ES/KJ1 / V850ES/KE1+* V850ES/KF1+* following features. V850ES/KG1+* V850ES/KJ1+* Flash capacity V850ES/SG2 64 to 640 KB V850ES/SJ2 PD70F3229Y Overwrite unit Entire memory at one time, or block units V850/SA1 Rewrite method V850/SB1 V850ES/SA2,SA3 Serial communication with dedicated flash memory programmer (on-board, off-board) V850/SB2 Self-flash programming V850E/MA1 Rewrite voltage Single-power-supply flash: Operation voltage Dual-power-supply flash: Operation voltage 7.8 V/10.3 V Rewrite count: V850/SC1,SC2,SC3 V850E/MA3 V850E/MS1 V853 V850E/IA3, IA4 V850E/IA2 V850E/IA1 V850ES/IK1* V850ES/FE2* 100 times V850ES/FF2* V850ES/FG2* V850ES/FJ2* V850E/SV2 V850/SV1 V850/SF1 V850/DB1 / *: Under development : Single power supply : Dual power supply : Single power supply/dual power supply Rewrite Modes To enable integrated use ranging from development to mass production and maintenance, the V850 Series supports a programmer rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites flash memory with user programs. On-board programming mode This programming mode is used to rewrite the flash memory mounted on the target system using a dedicated flash memory programmer. Off-board programming mode This programming mode is used to rewrite flash memory using a dedicated flash memory programmer and dedicated program adapter (FA SeriesNote 1). Self-programming mode This programming mode is used to rewrite flash memory by executing the user program written beforehand to the flash memory using on-board/ off-board programming.Note 2 Notes 1. The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd. 2. Since instruction fetch and data access cannot be performed from the internal flash memory area during self-programming, a program for rewriting internal RAM or external memory must be transferred in advance. Programmer program (on-board/off-board) CSI communication method Dedicated flash memory programmer (PG-FP4, etc.) FLMD0 FLMD1 VDD GND FLMD0 Note 1 Note 2 FLMD1 or VSS VDD VSS RESET SO SI SCK RESET SI0 SO0 Example: V850ES/SA2 SCK0 Note 1. In the case of dual-power-supply flash, VPP 38 Handshake-compatible CSI communication method Dedicated flash memory programmer (PG-FP4, etc.) Note 1 FLMD0 FLMD1 VDD GND FLMD0 Note 2 FLMD1 or VSS VDD VSS RESET SO SI SCK HS RESET SI0 SO0 Example: V850ES/SA2 SCK0 PDH0 UART communication method FLMD0 FLMD1 VDD GND RESET TxD Dedicated flash RxD memory programmer (PG-FP4, etc.) Note 2. In the case of dual-power-supply flash, don't connect. Pamphlet U15412EJ4V1PF Note 1 FLMD0 Note 2 FLMD1 or VSS VDD VSS RESET RXD0 TXD0 Example: V850ES/SA2 Self-programming mode (single-power-supply method) Self-programming flow Flash memory can be erased and rewritten using a self-programming library from a program placed in an area outside the flash memory. Flash memory operation Flash environment initialization processing Normal operation mode Self-programming mode Flash memory Flash memory 3FFFFH Write processing 3FFFFH Library initialization processing * Access to flash area prohibited * Stop instruction execution prohibited * Clock stop prohibited Erase processing Block 7(60KB) Flash information setting processing Block 6(60KB) 256 KB Library end processing Self-programming Library (Erase/Write routine execution) 00000H Internal verify processing Block 5(60KB) Block 4(60KB) 00000H All blocks completed? NO YES Block 3(4KB) Block 2(4KB) Block 1(4KB) Block 0(4KB) Boot area replacement processing Flash environment end processing Caution The number of blocks and block capacity differ depending on the products. (Example: V850ES/SA2) Processing end Flash Specifications List Category Low end Middle range High end ASSP Part No. Rewrite Mode On-Board/Off-Board Programming Flash Memory Capacity Max. Operating Frequency Rewrite Voltage 20 MHZ 20 MHZ VDD 4.5 V to 5.5 V 4.5 V to 5.5 V VPP --------- CSI 128 KB 256 KB/128 KB V850ES/KF1 128 KB 20 MHZ 4.5 V to 5.5 V V850ES/KG1 256 KB/128 KB 20 MHZ 4.5 V to 5.5 V V850ES/KG1 128 KB 20 MHZ V850ES/KJ1 256 KB/128 KB V850ES/KJ1 SelfProgramming UART CSI+HS 10.3 V ----- ----- 4.5 V to 5.5 V 10.3 V 20 MHZ 4.5 V to 5.5 V ----- 128 KB 20 MHZ 4.5 V to 5.5 V 10.3 V V850ES/KE1+* 128 KB 20 MHZ 4.5 V to 5.5 V ----- V850ES/KF1+* V850ES/KG1+* 256 KB/128 KB 256 KB/128 KB 20 MHZ 20 MHZ 4.5 V to 5.5 V 4.5 V to 5.5 V --------- V850ES/KJ1+* 256 KB/128 KB 20 MHZ 4.5 V to 5.5 V V850ES/SG2 640 KB/384 KB 20 MHZ 2.85 V to 3.6 V V850ES/SJ2 640 KB/384 KB 20 MHZ PD70F3229Y 384 KB V850ES/SA2 V850ES/SA3 V850ES/KE1 V850ES/KF1 Rewrite Count (Times) 100 100 100 ----- 100 100 ----- 100 100 100 ----- 100 ----- 100 2.85 V to 3.6 V ----- 100 20 MHZ 3.5 V to 5.5 V ----- 100 256 KB 20 MHZ 2.2 V to 2.7 V ----- 100 256 KB 20 MHZ 2.2 V to 2.7 V ----- 100 V850/SA1 V850/SB1 256 KB/128 KB 512 KB/384 KB/256 KB 20 MHZ 20 MHZ 3.0 V to 3.6 V 4.0 V to 5.5 V 7.8 V 7.8 V 100 100 V850/SC1 512 KB 20 MHZ 3.5 V to 5.5 V 7.8 V 100 V850E/MA3 512 KB 80 MHZ 2.3 V to 2.7 V (internal) 3.0 V to 3.6 V (external) ----- 100 V850E/MA1 256 KB 50 MHZ 3.0 V to 3.6 V 7.8 V 100 128 KB 33 MHZ 3.0 V to 3.6 V 7.8 V ----- V850E/MS1 100 V850E/MS1 128 KB 33 MHZ 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) 7.8 V 100 V853 V850E/IA4 256 KB/128 KB 256 KB 33 MHZ 64 MHZ 4.5 V to 5.5 V 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) 10.3 V ----- ----- 20 100 V850E/IA3 256 KB 64 MHZ 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) ----- 100 V850E/IA2 128 KB 40 MHZ 4.5 V to 5.5 V 7.8 V 100 V850E/IA1 256 KB 50 MHZ 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) 7.8 V 100 V850ES/IK1* 128 KB 32 MHZ 4.5 V to 5.5 V ----- 100 V850E/SV2 512 KB 40.5 MHZ 2.3 V to 2.7 V (internal) 2.7 V to 3.6 V (external) ----- 100 V850ES/FE2* 128 KB/64 KB 20 MHZ 4.0 V to 5.5 V ----- 100 V850ES/FF2* 256 KB/128 KB 20 MHZ 4.0 V to 5.5 V ----- 100 V850ES/FG2* 384 KB/256 KB/128 KB 20 MHZ 4.0 V to 5.5 V ----- 100 V850ES/FJ2* 512 KB/384 KB/256 KB 20 MHZ 4.0 V to 5.5 V ----- 100 V850/SV1 384 KB/256 KB 20 MHZ 3.1 V to 3.6 V 7.8 V 100 V850/SB2 512 KB/384 KB/256 KB 19 MHZ 4.0 V to 5.5 V 7.8 V 100 V850/SC2 512 KB 20 MHZ 3.5 V to 5.5 V 7.8 V 100 V850/SC3 512 KB 20 MHZ 3.5 V to 5.5 V 7.8 V 100 V850/SF1 256 KB 16 MHZ 3.5 V to 5.5 V 7.8 V 100 V850/DB1 128 KB 16 MHZ 4.0 V to 5.5 V 7.8 V 100 100 100 : Under development * Pamphlet U15412EJ4V1PF 39 Flash Memory Programmers NEC Electronics flash memory programmer: PG-FP4 [Features] Supports write to all NEC Electronics microcontrollers with internal flash memory. USB support through host machine interface Allows verification of various types of information, including programmer setting information, error messages, and check-sum, even in stand-alone configuration, from the main unit's LCD. Enables downloading of two types of user code and selecting of valid code Device-specific information required for writing automatically settable with parameter files Supports both on-board programming and program adapter programming. Easy-to-carry A5 size Simple operation either on stand-alone basis and on WindowsTM 95/Windows 98/Windows Me/ Windows 2000/Windows XP, Windows NTTM 4.0 using a dedicated application (Flashpro4) * Flash memory programmer configuration PG-FP4 allows single-microcontroller programming when used with a program adapter (FA Series of Naito Densei Machida Mfg. Co., Ltd.). Onboard programming can also be performed. A sample rewrite environment when using the program adapter is shown below. Rewrite environment example Flash memory program (PG-FP4) Target system Power-supply unit Host machine interface (USB) To host machine Cautions 1. Install the PG-FP4 control software and target device parameter file in the host machine. *PG-FP4 control software: Bundled with PG-FP4 *PG-FP4 parameter file: Distributed via online delivery service 2. In addition to programming using the program adapter, on-board programming on the target system is also possible. * Third-party flash memory programmers (1/2) Programming system Y1000-8 [Manufacturer/Distributor] Wave Technology Co., Ltd. [Target Devices] V850/SV1, SB1 (PD70F3032B, 70F3033B), SB2 (70F3035B, 70F3037H), V850E/IA1 (70F3116), MA1 [Features] Gang programmer enabling simultaneous programming and verification of up to 8 devices Enables reading of master data directly from floppy disk to internal memory Data dump display and editing functions Master data storable on internal hard disk Designed for simple and comfortable operation via touch panel, and superior operability via PASS/FAIL display, check-sum display, and task count display supporting sockets. [Additional information] TEL : +81-3-5304-1885 FAX : +81-3-5304-1886 E-mail : sales@y1000.com Website: http://www.y1000.com/index_e.html 40 Pamphlet U15412EJ4V1PF * Third-party flash memory programmers (2/2) FlashPRO IV: FL-PR4 [Manufacturer/Distributor] Naito Densei Machida Mfg. Co. [Target Devices] V850 Series [Features] Supports writing to all NEC Electronics microcontrollers with internal flash memory. USB support through host machine interface Allows verification of various types of information, including programmer setting information, error messages, and check-sum, even in stand-alone configuration, from the main unit's LCD. Enables downloading of two types of user code and selecting of valid code Device-specific information required for writing automatically settable with parameter files Supports both on-board programming and program adapter programming. Easy-to-carry A5 size Simple operation either on stand-alone basis and on Windows 95/Windows 98/Windows Me/ Windows 2000/Windows XP, Windows NT 4.0 using a dedicated application (Flashpro4) [Additional information] TEL : +81-45-475-4191 FAX : +81-45-475-4091 E-mail : info@ndk-m.co.jp Website: http://www.ndk-m.co.jp/asmis/eng/index.html * NET IMPRESS [Manufacturer/Distributor] Yokogawa Digital Computer Corporation [Target Devices] V850/SB1 (PD70F3033B), SB2(70F3037H), SA1(70F3017A), SC3(70F3089Y), V853(70F3003A, 70F3025A), V850E/MS1(70F3102A), MA1(70F3107), IA1, IA2(70F3114), V850ES/KF1(70F3210), FE2, FF2, FG2, FJ2, SG2, SJ2 [Features] Enables programming of flash memory microcontrollers of various writing specifications solder mounted on user system boards. One control module is the key to this product's versatility. Microcontrollers of the same family are supported by changing parameters, and microcontrollers of different families are supported by purchasing the required license for the descriptor part. Can be used on standalone basis as well as via a host machine. Rich lineup of downloadable freeware [Additional Information] TEL : Japan +81-42-333-6224 U.S.A +408-941-0132 (Yokogawa Corporation of America) Europe +44-1256-811998 (Ashling Microsystems Limited) Korea +82-2-785-3929 (KM DATA INC.) South East Asia +65-6563-2082 (Unidux Electronics Pte Ltd.) FAX : Japan +81-42-352-6109 U.S.A +408-941-0121 (Yokogawa Corporation of America) Europe +44-1256-811761 (Ashling Microsystems Limited) Korea +82-2-785-3117 (KM DATA INC.) South East Asia +65-6569-4661 (Unidux Electronics Pte Ltd.) Website: http://www.ydc.co.jp/micom/index_E.htm * Flash Burner Forward FL-S01, Flash Gang Forward FL-G01 [Manufacturer] Forward Electric Co., Ltd. (Hong Kong) [Distributor] Application Co., Ltd. [Target Devices] V850/SB1(70F3033A), V850E/MA1 [Features] Host machine interface supports USB. Easy operation and rich array of GUI software provided Low cost from development to mass production Compact and easy to carry (FL-S01) Gang programmer enabling simultaneous programming of up to 8 devices (FL-G01) Can be used on standalone basis using compact flash (FL-G01). Programming adapter board (option) usable in common for FL-S01 and FL-G01. [Additional Details] TEL : +81-42-732-1377 FAX : +81-42-732-1378 Website:http://www.apply.co.jp/index_eng.html FL-S01 Pamphlet U15412EJ4V1PF FL-G01 41 Low-End Lineup (1/2) V850ES/KE1 Item PD703207/3207Y Part No. Internal ROM PD703210/3210Y PD703211/3211Y PD70F3210/F3210Y PD70F3210H/F3210HY PD70F3211H/F3211HY V850ES 29 MIPS (@20 MHz: 5 MHz x 4) 128 KB (flash) 64 KB (mask) Bus type 96 KB (mask) 16 bits Data bus - 8/16 bits Chip select signal - 2 - SDRAM, etc. Memory controller Internal External Timer/counter 256 KB (mask) 128 KB (flash) 256 KB (flash) 6 KB 12 KB Multiplexed - Address bus 128 KB (mask) 4 KB 4 KB - Internal RAM Interrupt sources PD703209/3209Y V850ES 128 KB (mask) External bus interface PD703208/3208Y 29 MIPS (@20 MHz: 5 MHz x 4) CPU core CPU performance V850ES/KF1 PD70F3207H/F3207HY 25 (Y products: 26) 25 (Y products: 26) 8 (8)Note 1 16-bit timer/event counter (TM0) x 1 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch 28 (Y products: 29) 8(8)Note 1 16-bit timer/event counter (TM0) x 2 ch 16-bit timer/event counter (TMP) x 1 chNote 3 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch Watchdog timer 2 ch 2 ch Serial interface CSI x 2 ch UART x 2 ch I2Cx1 chNote 2 CSI with automatic transfer function (32-byte buffer) x 1 ch CSI x 2 ch UART x 2 ch I2C x 1 chNote 2 A/D converter D/A converter 10-bitx8 ch - 10 bits x 8 ch - DMA controller - - I/O 43 59 Input 8 - 8 Watch timer: 1 ch, ROM correction function: 4 points, real-time output Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Ports Debug control unit Other peripheral functions Operating frequency Power supply voltage Power consumption (Typ.) Package - 2.7 to 5.5 V 2.7 to 5.5 V 200 mW (128 KB mask products: 20 MHz @5 V operation) 39.6 mW (128 KB mask products: 10 MHz @3.3 V operation) 150 mW (128 KB mask products: 20 MHz @5 V operation) 29.7 mW (128 KB mask products: 10 MHz @3.3 V operation) 64-pin TQFP (12 x 12 mm) 64-pin LQFP (10 x 10 mm) 80-pin TQFP (12 x 12 mm) 80-pin QFP (14 x 14 mm) -40 to +85C -40 to +85C Operating ambient temperature Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. 3. PD703211, 703211Y, 70F3211H, 70F3211HY only V850ES/KG1 Item PD703212/3212Y Part No. PD703213/3213Y V850ES/KJ1 PD703214/3214Y PD703215/3215Y PD703216/3216Y PD703217/3217Y PD70F3214/F3214Y PD70F3215H/F3215HY PD70F3214H/F3214HY 64 KB (mask) 96 KB (mask) 128 KB (mask) 256 KB (mask) 128 KB (flash) 256 KB (flash) 6 KB 16 KB 4 KB Bus type Address bus 128 KB (flash) 6 KB 22 bits 24 bits 8/16 bits 2 4 SRAM, etc. 33 (Y products : 34) 8(8)Note 1 16-bit timer/event counter (TM0) x 4 ch 16-bit timer/event counter (TMP) x 1 chNote 2 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch External Timer/counter 16 KB Multiplexed/separate 8/16 bits 30 (Y products : 31) Internal 256 KB (flash) 128 KB (mask) SRAM, etc. Chip select signal Memory controller 38(Y products : 40) 41(Y products : 43) 8(8)Note 1 16-bit timer/event counter (TM0) x 6 ch 16-bit timer/event counter (TMP) x 1 chNote 3 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch Watchdog timer 2ch 2 ch Serial interface CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 2 ch UART x 2 ch 2 I C x 1 chNote 4 CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 3 ch UART/I2C x 1 chNote 4 UART x 2 ch I2C x 1 chNote 4 A/D converter 10-bit x 8 ch 10-bit x 16 ch D/A converter 8-bit x 2 ch - 8-bit x 2 ch - I/O 76 112 Input 8 - DMA controller Ports Debug control unit Other peripheral functions Operating frequency 16 - Provided(RUN/break) Watch timer: 1 ch, ROM correction function: 4 points, real-time output Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Power supply voltage Power consumption (Typ.) Package Operating ambient temperature 2.7 V to 5.5 V 2.7 V to 5.5 V 150 mW (128 KB mask products: 20 MHz @ 5 V operation) 29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 150 mW (128 KB mask products: 20 MHz @ 5 V operation) 29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 144-pin LQFP (20 x 20 mm) -40 to +85C -40 to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. PD703215, 703215Y, 70F3215H, 70F3215HY only 3. PD70F3218H, 70F3218HY only 4. Only Y products have an on-chip I2C interface. 42 96 KB (mask) Multiplexed/separate Data bus Interrupt sources 29 MIPS (@ 20 MHz: 5 MHz x 4) 29 MIPS (@ 20 MHz: 5 MHz x 4) CPU performance Internal ROM Internal RAM External bus interface V850ES V850ES CPU core PD70F3218H/F3218HY PD70F3217/F3217Y PD70F3217H/F3217HY Pamphlet U15412EJ4V1PF Low-End Lineup (2/2) V850ES/KE1+ Item V850ES/KF1+ PD70F3302/F3302Y PD703302/3302Y Part No. PD70F3306/F3306Y PD703308/3308Y PD70F3308/F3308Y V850ES V850ES CPU core 29 MIPS (@20 MHz: 5 MHz x 4) 29 MIPS (@20 MHz: 5 MHz x 4) CPU performance Internal ROM 128 KB (mask) 128 KB (flash) 128 KB (flash) 256 KB (mask) 256 KB (flash) Internal RAM External bus interface Memory controller Interrupt sources 4 KB 6 KB 12 KB Bus type - Address bus - 16 bits Data bus - 8/16 bits Chip select signal - Multiplexed 2 - SRAM, etc. 29 (Y products: 30) 26 (Y products: 27) Internal External Timer/counter 9(9)Note 1 9(9)Note 1 16-bit timer/event counter (TM0) x 1 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 16-bit timer/event counter (TM0) x 2 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 2 ch 2 ch CSI x 2ch UART x 1ch UART (LIN compatible) x 1 ch I2C x 1 chNote 2 CSI with automatic transfer function (32-byte buffer) x 1 ch CSI x 2 ch UART x 1 ch A/D converter 10-bit x 8 ch 10-bit x 8 ch D/A converter - - DMA controller - - I/O 43 59 Input 8 8 Watchdog timer Serial interface Ports UART (LIN compatible) x 1 ch I2C x 1 chNote 2 - - Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output Operating frequency Using main clock: 2 to 20 MHz Using subclock: 32.768 kHz Ring-OSC: 240 kHz Using main clock: 2 to 20 MHz Using subclock: 32.768 kHz Ring-OSC: 240 kHz Power supply voltage 2.7 to 5.5V Debug control unit Other peripheral functions Power consumption (Typ.) 2.7 to 5.5V 200 mW (128 KB mask products: 20 MHz @ 5 V operation) 39.6 mW (128 KB mask products: 10 MHz @ 3.3 V operation) Package 220 mW (256 KB mask products: 20 MHz @ 5 V operation) 42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation) 64-pin TQFP (12 x 12 mm) 64-pin LQFP (10 x 10 mm) 80-pin TQFP (12 x 12 mm) 80-pin QFP (14 x 14 mm) -40C to +85C -40C to +85C Operating ambient temperature Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. V850ES/KG1+ Item PD70F3311/F3311Y Part No. V850ES/KJ1+ PD703313/3313Y PD70F3316/F3316Y PD70F3318/F3318Y PD70F3313/F3313Y V850ES V850ES 29 MIPS (@ 20 MHz : 5 MHz x 4) 29 MIPS (@ 20 MHz : 5 MHz x 4) CPU core CPU performance Internal ROM Internal RAM External bus interface 128 KB (flash) 256 KB (mask) 128 KB (flash) 6 KB 256 KB (flash) 16 KB 6 KB Bus type Multiplexed/separate Address bus Data bus Chip select signal Memory controller Interrupt sources 24 bits 8/16 bits SRAM, etc. 4 SRAM, etc. 41 (Y products: 42) 46 (Y products: 48) 9 (9)Note 1 9 (9)Note 1 16-bit timer/event counter (TM0) x 6 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch Watchdog timer 2ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 1 ch UART/CSI x 1 ch Serial interface A/D converter D/A converter DMA controller Ports 22 bits 8/16 bits 16-bit timer/event counter (TM0) x 4 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch External Timer/counter 16 KB Multiplexed/separate 2 Internal 256 KB (flash) 2ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 2 ch UARTNote3/CSI x 1 ch UART x 1 ch UARTNote3/I2C x 1 chNote2 UART (LIN compatible) x 1 ch I2C x 1 chNote 2 UART (LIN compatible) x 1 ch UARTx 1 ch, I2C x 1 chNote 2 10-bit x 8 ch 8-bit x 2 ch 10-bit x 16 ch 8-bit x 2 ch 4 ch 4 ch I/O 76 112 Input 8 - Debug control unit Other peripheral functions Operating frequency Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 240 kHz Provided (RUN/break) Watch timer: 1 ch, POC/LVI/clock monitor, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 240 kHz 2.7 to 5.5 V 2.7 to 5.5 V 220 mW (256 KB mask products: 20 MHz @ 5 V operation) 42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation) 275 mW (256 KB flash products: 20 MHz @ 5 V operation) 59.4 mW (256 KB flash products: 10 MHz @ 3.3 V operation) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 144-pin LQFP (20 x 20 mm) -40C to +85C -40C to +85C Power supply voltage Power consumption (Typ.) 16 - Package Operating ambient temperature Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. 3. These UARTs are the identical and the number of channels in KJ1+ totals 3 channels. Pamphlet U15412EJ4V1PF 43 Middle-Range Lineup (1/3) V850ES/SG2 Item Part No. Without IEBus, aFCAN PD703260/3260Y PD703261/3261Y PD70F3261/F3261Y PD703262/3262Y On-chip IEBus PD703270/3270Y PD703280/3280Y PD703271/3271Y PD703281/3281Y PD70F3271/F3271Y PD70F3281/F3281Y PD703272/3272Y PD703282/3282Y On-chip aFCAN CPU core CPU performance Internal ROM Internal RAM External bus interface Memory controller Interrupt sources 256 KB (mask) 24 KB 384 KB (mask) 384 KB (flash) 32 KB Bus type Address bus Data bus Chip select signal 512 KB (mask) 40 KB Multiplexed/separate 22 bits 8/16 bits - 1 ch Serial interface CSI x 3 ch UART(LIN compatible)/CSI x 1 ch CSI/I2C x 1 chNote 4 UART(LIN compatible)/I2C x 2 chNote 4 A/D converter D/A converter DMA controller Ports 10-bit x 12 ch 8-bit x 2 ch - - Provided (RUN/break) Provided (RUN/break) Watch timer: 1 ch IEBus controller x 1 chNote 5 aFCAN controller x 1 chNote 6 ROM correction function : 4 points Real-time output LVI/clock monitor Operating frequency When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 200 kHz Power supply voltage Power consumption (Typ.) 2.85 to 3.6 V (@ 20 MHz) 82.5 mW(3.3 V,@ 20 MHz) 59.4 mW(3.3 V,@ 20 MHz) 59.4 mW(3.3 V,@ 20 MHz) 89.1 mW(3.3 V,@ 20 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) Package -40C to +85C Operating ambient temperature Notes4.Only Y products have an on-chip I2C interface. 5.PD703270 (Y)/3271 (Y)/F3271 (Y)/3272 (Y)/3273 (Y)/F3273 (Y) 6.PD703280 (Y)/3281 (Y)/F3281 (Y)/3282 (Y)/3283 (Y)/F3283 (Y) Notes1.Only products without IEBus or aFCAN 2.Only products with IEBus or aFCAN 3.Number of external interrupts that can be used to release STOP mode V850ES/SG2 Item Without IEBus, aFCAN PD703260/3260Y PD703261/3261Y PD70F3261/F3261Y PD703262/3262Y On-chip IEBus PD703270/3270Y PD703280/3280Y PD703271/3271Y PD703281/3281Y PD70F3271/F3271Y PD70F3281/F3281Y PD703272/3272Y PD703282/3282Y 256 KB (mask) 24 KB 384 KB (mask) 384 KB (flash) On-chip aFCAN PD703263/3263Y PD703273/3273Y PD703283/3283Y PD70F3263/F3263Y PD70F3273/F3273Y PD70F3283/F3283Y V850ES 29 MIPS (@ 20 MHz) 32 KB Bus type Address bus Data bus Chip select signal 512 KB (mask) 40 KB Multiplexed/separate 22 bits 8/16 bits - Watchdog timer 1 ch Serial interface CSI x 3 ch UART(LIN compatible)/CSI x 1 ch CSI/I2C x 1 chNote 4 UART(LIN compatible)/I2C x 2 chNote 4 A/D converter D/A converter DMA controller Ports 10-bit x 12 ch 8-bit x 2 ch - Package Operating ambient temperature Notes 1. Only products without IEBus or aFCAN 2. Only products with IEBus or aFCAN 3. Only products with two aFCAN channels 4. Number of external interrupts that can be used to release STOP mode - Provided (RUN/break) Provided (RUN/break) Watch timer: 1 ch IEBus controller x 1 chNote 5 aFCAN controller x 1 chNote 6 ROM correction function : 4 points Real-time output LVI/clock monitor Operating frequency Power supply voltage Power consumption (Typ.) 640 KB (flash) 48 KB 4 ch 84 - I/O Input Debug control unit Other peripheral functions 640 KB (mask) SRAM, etc. 47Note 1/52Note 2 9(9)Note 1 16-bit interval timer(TMM) x 1 ch 16-bit timer/event counter(TMP) x 6 ch 16-bit timer/event counter(TMQ) x 1 ch Internal External Timer/counter 44 640 KB (flash) 48 KB 4 ch 84 - I/O Input Debug control unit Other peripheral functions Memory controller Interrupt sources 640 KB (mask) SRAM, etc. 47Note 1/52Note 2 9(9)Note 1 16-bit interval timer(TMM) x 1 ch 16-bit timer/event counter(TMP) x 6 ch 16-bit timer/event counter(TMQ) x 1 ch Internal External Watchdog timer CPU core CPU performance Internal ROM Internal RAM External bus interface PD70F3263/F3263Y PD70F3273/F3273Y PD70F3283/F3283Y V850ES 29 MIPS (@ 20 MHz) Timer/counter Part No. PD703263/3263Y PD703273/3273Y PD703283/3283Y When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 200 kHz 59.4 mW(3.3 V,@ 20 MHz) 2.85 to 3.6 V (@ 20 MHz) 82.5 mW(3.3 V,@ 20 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C Notes 5. Only Y products have an on-chip I2C interface. 6. PD703274(Y)/F3274(Y)/3275(Y)/3276(Y)/F3276(Y) 7. PD703284(Y)/F3284(Y)/3285(Y)/3286(Y)/F3286(Y) 8. PD703287(Y)/3288(Y)/F3288(Y) Pamphlet U15412EJ4V1PF 59.4 mW(3.3 V,@ 20 MHz) 89.1 mW(3.3 V,@ 20 MHz) Middle-Range Lineup (2/3) V850/SB1 Item PD703031B/3031BY PD703033B/3033BY PD70F3033B/F3033BY Part No. CPU core V850 CPU performance 23 MIPS (@20 MHz) Internal ROM 128 KB (mask) Internal RAM 8 KB External bus interface 256 KB (mask) 256 KB (flash) 384 KB (mask) 384 KB (flash) 16 KB 512 KB (flash) Multiplexed/separate Bus type Address bus 22 bits Data bus 16 bits - Memory controller SRAM, etc. Internal 31 (Y products: 32) 8(6)Note 1 External 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 6 ch 8-bit timer x 2 ch Timer/counter Watchdog timer 1 ch Serial interface CSI x 1 ch CSI/I2C x 2 chNote 2 CSI/UART x 2 ch A/D converter 10-bit x 12 ch D/A converter - DMA controller 6 ch (dedicated internal RAMon-clip peripheral I/O) Ports 512 KB (mask) 24 KB Chip select signal Interrupt sources PD703030B/3030BY PD70F3030B/F3030BY PD703032B/3032BY PD70F3032B/F3032BY I/O 71 Input 12 - Debug control unit ROM correction function:4 points, watch timer: 1 ch Other peripheral functions Operating frequency When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Power supply voltage 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) 125 mW (5 V, @ 20 MHz) Package 165 mW (5 V, @ 20 MHz) 125 mW (5 V, @ 20 MHz) 185 mW (5 V, @ 20 MHz) 125 mW (5 V, @ 20 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) Operating ambient temperature 210 mW (5 V, @ 20 MHz) 100-pin QFP (14 x 20 mm) -40 to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. PD703229Y Item PD703229Y Part No. V850/SC2 PD703069Y V850/SC3 PD703088Y 384 KB (mask) Internal ROM 512 KB (flash) Multiplexed (can be separated only for V850/SC1, V850/SC2) 18 bits 22 bits 8/16 bits 16 bits 2 - SRAM, etc. SRAM, etc. Chip select signal Internal 38 sources External 9 (9)Note 11 (9)Note 16-bit internal timer (TMM) x 1 ch 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit timer/event counter x 10 ch Timer/counter 23 MIPS (@ 20 MHz) 512 KB (mask) Multiplexed Data bus PD70F3089Y 18 MIPS (@ 16 MHz) 21 MIPS (@ 19 MHz) 24 KB Address bus Memory controller 23 MIPS (@ 20 MHz) 384 KB (flash) 32 KB Internal RAM Bus type V850/SC1,V850/SC2,V850/SC3 PD703089Y V850 29 MIPS (@ 20 MHz) CPU performance Interrupt sources V850/SC1 PD703068Y V850ES CPU core External bus interface PD70F3229Y 42 46 44 49 Watchdog timer 1 ch 1ch Serial interface UART (LIN compatible) x 3 ch CSI x 2 ch CSI/I C x 2 ch CSI x 1 ch 2 CSI/I2C x 1 ch CSI/UART x 2 ch 10-bit x 12 ch 10-bit x 12 ch UART x 2 ch A/D converter D/A converter - - DMA controller 4 ch 6 ch (dedicated internal RAMon-chip peripheral I/O) I/O 84 112 Input - 12 Ports Debug control unit Other peripheral functions - - Provided (RUN, break) ROM correction function : 4 points, watch timer: 1 ch, LVI/clock monitor ROM correction function : 4 points, watch timer: 1 ch, IEBus controller : 1 ch (V850/SC2 only), FCAN controller : 2 ch (1 ch : PD703088Y only) (V850/SC3 only) Operating frequency When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz During Ring OSC operation: 200 kHz Power supply voltage 3.5 to 5.5V When using main clock: 4 to 20 MHz (@5 V) When using main clock: 4 to 19 MHz (@5 V) When using subclock: 32.768 kHz When using subclock: 32.768 kHz Power consumption (Typ.) Package Operating ambient temperature 100 mW (5 V, @ 20MHz) 145 mW (5 V, @ 20MHz) When using main clock: 4 to 16 MHz (@5 V) When using subclock: 32.768 kHz 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 125 mW (5 V, @ 20 MHz) 120 mW (5 V, @ 19 MHz) 100-pin LQFP (14 x 14 mm) 110 mW (5 V, @ 16 MHz) When using main clock: 4 to 20 MHz (@5 V) When using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) 150 mW (5 V, @ 20 MHz) 144-pin LQFP (20 x 20 mm) -40C to +85C -40 to +85C Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ4V1PF 45 Middle-Range Lineup (3/3) V850ES/SA2 Item PD703200/3200Y Part No. V850ES/SA3 PD703201/3201Y PD70F3201/F3201Y CPU core PD703220 V850ES - 29 MIPS (@ 20 MHz) Internal ROM 128 KB (mask) Internal RAM 8 KB 256 KB (mask) 256 KB (flash) Bus type Address bus 256 KB (mask) 256 KB (flash) ROM-less 16 KB 48 KB Multiplexed/separate Separate/multiplexed (selectable only for CS1) 24 bits 22 bits Data bus 22 bits 8/16 bits Internal 8/16 bits 4 4 SRAM, etc. SRAM, etc. Chip select signal Memory controller Interrupt sources V850ES/ST2 PD70F3204/F3204Y V850ES CPU performance External bus interface PD703204/3204Y 31 (Y products: 32) 30 (Y products: 31) Timer/counter 28 8 (8)Note1 9 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch 16-bit interval timer (TMM) x 1 ch 16-bit timer/event counter (TMP) x 6 ch External 1 ch Watchdog timer 1 ch CSI x 2 ch Serial interface CSI x 3 ch CSI x 1 ch CSI/UART x 1 ch UART x 1 ch 10-bit x 16 ch 10-bit x 8 ch CSI/UART x 1 ch CSI/I2C x 1 chNote 2 UART x 1 ch 10-bit x 12 ch A/D converter D/A converter 8-bit x 2 ch DMA controller 4 ch Ports I/O 68 Input 14 8-bit x 2 ch - 84 57 18 8 - - Debug control unit ROM correction function : 4 points, real-time counter (watch timer): 1 ch Real-time output Operating frequency When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 20 to 34 MHz Power supply voltage 2.2 to 2.7 V 3.0 to 3.6 V Other peripheral functions Power consumption (Typ.) 38 mW (2.5 V, @ 20 MHz) 46 mW (2.5 V, @ 20 MHz) 38 mW (2.5 V, @ 20 MHz) 100-pin TQFP (14 x 14 mm) Package 46 mW (2.5 V, @ 20 MHz) T.B.D. 121-pin FBGA (12 x 12 mm) 120-pin TQFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) -40C to +85C Operating ambient temperature -40C to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. Item V850/SA1 PD703014A/3014AY PD703014B/3014BY PD703015A/3015AY PD703015B/3015BY PD70F3015B/F3015BY Part No. CPU core V850 CPU performance 23 MIPS (@ 20 MHz) Internal ROM 64 KB (mask) 128 KB (mask) Internal RAM External bus interface 128 KB (flush) 4 KB Bus type 22 bits Data bus 16 bits - SRAM, etc. Internal 24 External 8 (5)Note 1 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch Timer/counter Watchdog timer 1ch Serial interface CSI x 1 ch, CSI/I2C x 1 chNote 2 CSI/UART x 1 ch UART x 1ch A/D converter 10-bit x 12 ch D/A converter - DMA controller 3 ch (dedicated internal RAMon-chip peripheral I/O) I/O 72 Input 13 - Debug control unit Other peripheral functions Watch timer: 1 ch Operating frequency When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Power supply voltage 3.0 to 3.6 V (@20 MHz) 2.7 to 3.6 V (@17 MHz) Power consumption (Typ.) Package 66 mW (3.3 V, @ 20 MHz) 56 mW (3.0 V, @ 17 MHz) 121-pin FBGA (12 x 12 mm) 100-pin LQFP (14 x 14 mm) 121-pin FBGA (12 x 12 mm) Operating ambient temperature 105 mW (3.3 V, @ 20 MHz) 99 mW (3.0 V, @ 17 MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. 46 256 KB (flash) Multiplexed/separate Address bus Memory controller Ports 256 KB (mask) 8 KB Chip select signal Interrupt sources PD703017A/3017AY PD70F3017A/F3017AY Pamphlet U15412EJ4V1PF 66 mW (3.3 V, @ 20 MHz) 56 mW (3.0 V, @ 17 MHz) 105 mW (3.3 V, @ 20 MHz) 99 mW (3.0 V, @ 17 MHz) 100-pin LQFP (14 x 14 mm) 121-pin FBGA (12 x 12 mm) ASSP Lineup (1/3) V850E/IA4 Item PD703185 Part No. CPU core PD703183 128 KB (mask) Internal RAM 6 KB V850E/IA1 PD70F3184 PD703116 256 KB (flash) 6 KB 12 KB 256 KB (mask) PD70F3114 V850E1 67 MIPS (@ 50 MHz) 128 KB (mask) 12 KB PD703114 V850E1 82 MIPS (@ 64 MHz) 256 KB (flash) 256 KB (mask) V850E/IA2 PD70F3116 V850E1 82 MIPS (@ 64 MHz) Internal ROM 54 MIPS (@ 40 MHz) 256 KB (flash) 128 KB (mask) 128 KB (flash) 10 KB 6 KB Multiplexed Bus type - - Multiplexed Address bus - - 24 bits 22 bits Data bus - - 8/16 bits 8/16 bits Chip select signal - - 8 - - - SRAM, etc. SRAM, etc. Memory controller Interrupt sources PD70F3186 V850E1 CPU performance External bus interface V850E/IA3 PD703186 Internal 53 49 45 42 External 8 (7) Note 7 (6) Note 20(14) Note 16(12) Note 16-bit timer/event counter (TMQ) x 2 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 2 ch 16-bit timer/event counter (TMP) x 2 ch 16-bit timer/counter (TMP) x 2 ch 16-bit interval timer (TMM) x 1 ch 16-bit timer/event counter (TMQ) x 1 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 1 ch 16-bit timer/event counter (TMP) x 2 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit timer/counter (TMP) x 2 ch 16-bit interval timer (TMM) x 1 ch 16-bit 3-phase sinusoidal PWM timer x 2 ch 16-bit encoder counter/timer x 2 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch 16-bit 3-phase sinusoidal PWM timer x 2 ch 16-bit encoder counter/timer x 1 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch Timer/counter Watchdog timer 1 ch 1 ch - - Serial interface CSI x 1 ch UART x 1 ch CSI/UART x 1 ch CSI x 1 ch UART x 1 ch CSI/UART x 1 ch CSI x 2 ch UART x 3 ch CSI x 1 ch CSI/UART x 1 ch UART x 1 ch A/D converter 10-bit x 4 ch, 2 units (conversion time: 2 s) 8/10-bit x 8 ch 10-bit x 4 ch, 10-bit x 2 ch (conversion time: 2 s) 8/10-bit x 6 ch 10-bit x 8 ch, 2 units 10-bit x 6 ch (A/D converter 0) 10-bit x 8 ch (A/D converter 1) D/A converter - - - - DMA controller 4 ch 4 ch 4 ch 4 ch I/O 56 44 75 47 Input 8 6 8 6 - - - Ports Debug control unit - Provided (RUN/break) Other peripheral functions ROM correction function : 4 points, operational amplifier, comparator, software pull-up function ROM correction function : 4 points, operational amplifier, comparator, software pull-up function FCAN controller x 1 ch - Operating frequency 0.5 to 64 MHz 0.5 to 64 MHz 4 to 50 MHz 4 to 40 MHz Power supply voltage 2.5 V (internal), 5 V (A/D converter) 5 V (external) 2.5 V (internal), 5 V (A/D converter) 5 V (external) 3.3 V (internal), 5 V (A/D converter) 5 V (external) 5 V (3.3 V (internal), 5 V (A/D converter)) 5 V (external) (on-chip regulator) Power consumption (Typ.) 175 mW (internal 2.5 V, @ 64 MHz) 175 mW (internal 2.5 V, @ 64 MHz) 630 mW (internal 3.3 V, external 5 V, @ 50 MHz operation) 440 mW (5 V, @ 40 MHz operation) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 80-pin QFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) 100-pin QFP (14 x 20 mm) 100-pin LQFP (14 x 14 mm) -40C to +85C -40C to +85C -40C to +85C (Provided 110C products) -40C to +85C Package Operating ambient temperature Note Number of external interrupts that can be used to release STOP mode. V850ES/IK1 Item PD703327 Part No. CPU core PD703329 PD70F3329 PD703034B/3034BY PD703036H/3036HY PD70F3036H/F3036HY V850ES CPU performance Internal ROM 64 KB (mask) Internal RAM 128 KB (mask) 4 KB 15 MIPS (@ 13 MHz) 128 KB (mask) 6 KB 8 KB 22MIPS (@ 19 MHz) 256 KB (mask) 384 KB (mask) 256 KB (flash) 384 KB (flash) 16 KB Bus type - Multiplexed/separate - 22 bits Data bus - 16 bits Chip select signal - - - SRAM, etc. 36 33 (Y products : 34) Timer/counter 512 KB (mask) 512 KB (flash) 24 KB Address bus Memory controller Internal Interrupt sources External PD703037H/3037HY PD70F3037H/F3037HY V850 41MIPS (@ 32 MHz) 128 KB (flash) External bus interface V850/SB2 PD703035B/3035BY PD70F3035B/F3035BY 7 (6)Note 1 8 (6)Note 1 16-bit timer/event counter (TMQ) x 1ch (inverter timer support possible) 16-bit timer/event counter x 2 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer/event counter x 4 ch 16-bit timer/event counter (TMQ) x 1 ch 8-bit timer x 2 ch 16-bit timer counter (TMP) x 3 ch 16-bit interval timer (TMM) x 1 ch Watchdog timer 1 ch 1 ch Serial interface CSI x 1 ch CSI x 1 ch UART x 2 ch CSI/I C x 2 chNote 2 2 CSI/UART x 2 ch A/D converter 10 bits x 4 ch, 2 units (conversion time 2 s) D/A converter - - DMA controller - 6 ch (dedicated internal RAM 0n-chip peripheral I/O) I/O 39 71 Input - 12 Ports Debug control unit - Other peripheral functions ROM correction function : 4 points, software pull-up function, POC/LVI/clock monitor Operating frequency 20 to 32 MHz Power supply voltage 3.5 to 5.5 V (A/D converter : 4.5 to 5.5 V) Power consumption (Typ.) Package 10-bit x 12 ch T.B.D. 64-pin LQFP (14 x 14 mm) - ROM correction function : 4 points, watch timer x 1 ch, IEBus controller (simple version) : 1 ch When using main clock: 2 to 13 MHz (@ 5 V) When using subclock: 32.768 kHz When using main clock: 2 to 19 MHz (@ 5 V) When using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter : 4.5 to 5.5 V) 125 mW (mask ROM version : @5 V, 19 MHz) 125 mW (mask ROM version : @ 5 V, 19 MHz) 185 mW (flash memory version : @ 5 V, 19 MHz) 210 mW (flash memory version : @ 5 V, 19 MHz) 75 mW (mask ROM version : @ 5 V, 13 MHz) 125 mW (flash memory version : @ 5 V, 13 MHz) 100-pin LQFP (14 x 14mm) 100-pin QFP (14 x 20 mm) 100-pin QFP (14 x 20mm) Operating ambient temperature -40C to +85C -40C to +85C Notes 1. Number of external interrupts that can be used to release STOP mode. 2. Only Y products have an on-chip I2C interface. Pamphlet U15412EJ4V1PF 47 ASSP Lineup (2/3) V850ES/FE2 Item PD703230 Part No. PD70F3230 CPU core CPU performance Internal ROM 64 KB (mask) Internal RAM External bus interface PD70F3231 PD703232 PD70F3232 PD703233 V850ES V850ES 29 MIPS (@20 MHz) 29 MIPS (@20 MHz) 64 KB (flash) 128 KB (mask) 4 KB 128 KB (flash) 128 KB (mask) 6 KB 128 KB (flash) - - - - Data bus - - Chip select signal - - - - 44 44 9(9)Note 9(9)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TQM) x 1 ch 16-bit interval timer (TMM) x 1 ch 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit interval timer (TMM) x 1 ch External Timer/counter Watchdog timer 1 ch 1 ch Serial interface CSI x 2 ch UART (LIN compatible) x 2 ch CSI x 2 ch UART (LIN compatible) x 2 ch A/D converter 10-bit x 10 ch 10-bit x 12 ch D/A converter - - DMA controller - - 51 67 Ports I/O - Input - Debug control unit Other peripheral functions - - Provided (RUN, break) - Provided (RUN, break) - Provided (RUN, break) Provided (RUN, break) Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch When using main clock: 16 to 20 MHz When using main clock: 16 to 20 MHz Operating frequency Power supply voltage Power consumption (Typ.) 256 KB (flash) 12 KB Bus type Internal PD70F3233 256 KB (mask) 6 KB Address bus Memory controller Interrupt sources V850ES/FF2 PD703231 4.0 to 5.5V 155 mW (@5.0 V, 20 MHz) 170 mW (@5.0 V, 20 MHz) Package Operating ambient temperature 4.0 to 5.5V 155 mW (@5.0 V, 20 MHz) 170 mW (@5.0 V, 20 MHz) 155 mW (@5.0 V, 20 MHz) 170 mW (@5.0 V, 20 MHz) 155 mW (@5.0 V, 20 MHz) 64-pin TQFP (10 x 10 mm) 80-pin TQFP (12 x 12mm) -40C to +85C, -40C to +110C -40C to +85C, -40C to +110C 170 mW (@5.0 V, 20 MHz) Note Number of external interrupts that can be used to release STOP mode V850ES/FG2 Item PD703234 Part No. PD70F3234 PD703235 CPU core CPU performance Internal ROM 128 KB (mask) Internal RAM External bus interface 128 KB (flash) PD70F3236 V850ES/FJ2 PD70F3237 PD70F3238 V850ES V850ES 29 MIPS (@ 20 MHz) 29 MIPS (@ 20 MHz) 256 KB (mask) 6 KB 256 KB (flash) 12 KB 384 KB (flash) 256 KB (flash) 384 KB (flash) 16 KB 12 KB 16 KB 512 KB (flash) 20 KB - - Address bus - - 16 bits Data bus - - 8/16 bits Chip select signal - - - - Internal 62 73 External 12 (12)Note Multiplexed 4 SRAM, etc. 83 16 (16)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 2 ch 16-bit interval timer (TMM) x 1 ch Timer/counter 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 3 ch 16-bit interval timer (TMM) x 1 ch Watchdog timer 1 ch Serial interface CSI x 2 ch UART (LIN compatible) x 3 ch A/D converter 10-bit x 16 ch D/A converter - - DMA controller 4 ch 4 ch I/O 84 128 Input - Ports PD70F3239 Bus type Memory controller Interrupt sources PD70F3235 Debug control unit - Other peripheral functions Provided (RUN, break) - 1ch CSI x 3 ch UART (LIN compatible) x 3 ch CSI x 3 ch UART (LIN compatible) x 4 ch 10-bit x 24 ch - Provided (RUN, break) Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 2 ch Provided (RUN, break) Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag aFCAN controller: 2 ch Operating frequency When using main clock: 16 to 20 MHz Power supply voltage Power consumption (Typ.) 4.0 to 5.5V 155 mW (@ 5.0 V, 20 MHz) Package Operating ambient temperature 170 mW (@ 5.0 V, 20 MHz) 155 mW (@ 5.0 V, 20 MHz) 4.0 to 5.5V 170 mW (@ 5.0 V, 20 MHz) 200 mW (@ 5.0 V, 20 MHz) 100-pin LQFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) -40C to +85C, -40C to +110C -40C to +85C, -40C to +110C Note Number of external interrupts that can be used to release STOP mode 48 aFCAN controller: 4 ch When using main clock: 16 to 20 MHz Pamphlet U15412EJ4V1PF ASSP Lineup (3/3) V850E/SV2 Item PD70F3040/F3040Y V850E1 CPU core 512 KB (mask) Internal ROM 192 KB (mask) 256 KB (mask) 24 KB Bus type Data bus 384 KB (mask) 26 bits 22 bits 8/16 bits 16 bits 8 - SRAM, etc. SRAM, etc. 75 (Y products : 76) 45 (Y products: 46) 12(12)Note 1 32-bit timer/event counter x 1 ch 16-bit timer/event counter x 6 ch 16-bit interval timer x 6 ch 8-bit timer/event counter x 12 ch 9(6)Note1 24-bit timer/event counter x 2 ch 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 8 ch Watchdog timer 1 ch 1 ch Serial interface CSI with automatic transfer function x 2 ch CSI x 3 ch UART/CSI x 1 ch UART x 1 ch I2C x 1 chNote 2 CSI x 1 ch CSI/I2C x 2 chNote 2 CSI/UART x 2ch A/D converter 10-bit x 24 ch - 10-bit x 16 ch - D/A converter DMA controller Ports 4 ch 6 ch (dedicated internal RAMinternal peripheral I/O) I/O 171 135 Input 24 16 - Debug control unit Provided (RUN, break) Other peripheral functions 384 KB (flash) 16 KB Multiplexed Chip select signal Memory controller Interrupt Internal sources External Timer/counter 256 KB (flash) 8 KB Multiplexed/separate Address bus PD70F3038/F3038Y 23 MIPS (@ 20 MHz) 512 KB (flash) Internal RAM PD703038/3038Y V850 55 MIPS (@ 40.5 MHz) CPU performance External bus interface V850/SV1 PD703166/3166Y PD70F3166/F3166Y PD703041/3041Y PD703039/3039Y PD703040/3040Y Part No. Boundary scan function, 12- to 16-bit PWM output : 5 ch, real-time output, ROM correction function : 8 points Watch timer: 1 ch, 12- to 16-bit PWM output : 4 ch, Vsync/Hsync separator, ROM correction function : 4 points Operating frequency 10 to 40.5 MHz When using main clock: 4 to 20 MHz When using subclock: 32.768 kHz Power supply voltage 2.3 to 2.7 V (internal) 2.7 to 3.6 V (external) 3.1 to 3.6 V (@ 20 MHz) 2.7 to 3.6 V (@ 16 MHz) Power consumption (Typ.) 134 mW (@ 2.5 V, 40.5 MHz) 159 mW (@ 2.5 V, 40.5 MHz) 257-pin FBGA (14 x 14 mm) Package Operating ambient temperature 82 mW (@ 3.3 V, 20 MHz) 148 mW (@ 3.3 V, 20 MHz) 82 mW (@ 3.3 V, 20 MHz) 176-pin LQFP (24 x 24 mm) 180-pin FBGA (13 x 13 mm) 176-pin LQFP (24 x 24 mm) -10C to +70C 148 mW (@ 3.3 V, 20 MHz) 180-pin FBGA (13 x 13 mm) -40C to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. V850/SF1 Item PD703075AY Part No. PD703076AY External bus interface PD70F3080 V850ES/PM1 PD703081 PD703228 V850ES 18 MIPS (@ 16 MHz) 18 MIPS (@ 16 MHz) 29 MIPS (@ 20 MHz) 256 KB (mask) 16 KB 256 KB (flash) 128 KB (flash) 128 KB (mask) 6 KB 128 KB (mask)/ROM-less 10 KB Separate Multiplexed - Address bus 22 bits - 19 bits Data bus 16 bits - 8/16 bits - SRAM, etc. - 3 - SRAM, etc. Bus type Chip select signal Memory controller Interrupt sources PD70F3079AY V850 128 KB (mask) 12 KB Internal ROM Internal RAM PD703079AY V850 CPU core CPU performance V850/DB1 PD703078AY Internal 35 38 35 38 8 (6)Note External 16-bit timer/event counter x 8 ch Timer/counter 44 40 28 7 (7)Note 1 7 (7)Note 1 4 (4)Note 1 16-bit timer/event counter (TMG) x 1 ch 16-bit timer/event counter (TM0) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 16-bit timer/event counter (TM1) x 6 ch 8-bit timer/event counter (TM2) x 2 ch Watchdog timer 1 ch 1 ch 1 ch Serial interface CSI x 1 ch CSI/I2C x 1 ch CSI/UART x 2 ch CSI x 3 ch UART x 2 ch CSI x 2 ch UART x 2ch A/D converter 10-bit x 12 ch - 10-bit x 8 ch - 16-bit x 6 ch (12 inputs) - D/A converter 6 ch (dedicated internal RAM internal peripheral I/O) - - I/O 72 99 (Including 16 output-only) Input 12 8 68 - DMA controller Ports - Debug control unit Other peripheral functions Watch timer: 1 ch FCAN controller : 1 ch ROM correction function : 4 points Watch timer: 1 ch FCAN controller : 2 ch ROM correction function : 4 points - - Watch timer: 1 ch FCAN controller : 1 ch ROM correction function : 4 points Watch timer: 1 ch FCAN controller : 2 ch ROM correction function : 4 points Watch timer: 1 ch,16-bit PWM output: 6 ch 8-bit PWM output: 2 ch, meter control PWM: 24 ch DCAN controller: 2 ch Watch timer: 1 ch, 16-bit PWM output: 6 ch 8-bit PWM output: 2 ch, meter control PWM: 24 ch DCAN controller: 1 ch Real-time counter (watch timer) : 1 ch ROM correction function : 4 points 8- to 12-bit PWM output : 4 ch Operating frequency When using main clock: 4 to 16 MHz When using subclock: 32.768 kHz When using main clock: 4 to 16 MHz When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Power supply voltage 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 4.0 to 5.5 V 3.0 to 3.6 V (@ 20 MHz) 2.7 to 3.6 V (@ 10 MHz) 2.2 to 3.6 V (@ 32.768 kHz) Power consumption (Typ.) Package Operating ambient temperature 75 mW (@ 5 V, 16 MHz) 125 mW (@ 5 V, 16 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C 180 mW (@ 5 V, 16 MHz) 120 mW (@ 5 V, 16 MHz) 128-pin QFP (20 x 20 mm) -40C to +85C 81 mW (@ 3.3 V, 20 MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ4V1PF 49 High-End Lineup (1/2) V850E/MA3 V850E/ME2 PD703131A/3131AY PD703132A/3132AY PD703133A/3133AY PD703134A/3134AY PD70F3134A/F3134AY PD703111A Item Part No. CPU core CPU performance Internal ROM V850E1 215 MIPS (@ 150 MHz) 256 KB (mask) Internal RAM External bus interface V850E1 106 MIPS (@ 80 MHz) 16 KB 512 KB (mask) 32 KB Bus type 32 KB Address bus Chip select signal Memory controller ROM-less (instruction cache : 8 KB) Instruction: 128 KB; Data: 16 KB Multiplexed/separate Data bus Interrupt sources 512 KB (flash) 16 KB Separate 26 bits 26 bits 8/16 bits 8/16/32 bits 8 8 SDRAM, SRAM, etc. SDRAM, SRAM, etc. Internal 41 59 External 26(26)Note 1 40(32)Note 1 16-bit interval timer (TMD) x 4 ch 16-bit timer/event counter (TMP) x 3 ch 16-bit timer/event counter (TMQ) x 1 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 1 ch 16-bit timer/event counter (TMC) x 6 ch 16-bit interval timer (TMD) x 4 ch 16-bit encoder counter/timer (TMENC) x 2 ch Timer/counter Watchdog timer 1 ch - Serial interface CSI/UART x 3 ch UART/I2C x 1 chNote 2 CSI (with FIFO) x 1 ch CSI (with FIFO)/UART x 1 ch UART x 1 ch A/D converter 10-bit x 8 ch 10-bit x 8 ch D/A converter 8-bit x 2 ch - DMA controller 4 ch 4 ch I/O 101 77 Input 11 1 Provided (RUN, break) Provided (RUN, break, trace) ROM correction function : 4 points USB (function) x 1 ch, SSCG 16-bit PWM output x 2 ch Operating frequency 5 to 80 MHz 10 to 150 MHz Power supply voltage 2.3 to 2.7 V (internal)/3.0 to 3.6 V (external) 1.35 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 133 MHz) 1.40 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 150 MHz) Ports Debug control unit Other peripheral functions Power consumption (Typ.) T.B.D. Package Operating ambient temperature 575 mW (@2.5 V, 80 MHz) 200 mW (@ 1.5 V, 150 MHz) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) 176-pin LQFP (24 x 24 mm) 240-pin FBGA (16 x 16 mm) -40C to +85C -40C to +85C (@133MHz), -40 toC +70C (@150MHz) Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. Item PD703103A Part No. PD703105A V850E/MA1 PD703106A - CPU performance Internal ROM 128 KB (mask) - 256 KB (mask) 4 KB Address bus Chip select signal Memory controller ROM-less 4 KB Separate Data bus Separate 26 bits 25 bits 8/16 bits 8/16 bits 8 4 SDRAM, SRAM, etc. SDRAM, SRAM, etc. Internal 33 23 External 25 (17)Note 8 (4)Note 16-bit timer/event counter (TMC) x 4 ch 16-bit interval timer (TMD) x 4 ch 16-bit timer/event counter (TMC) x 2 ch 16-bit interval timer (TMD) x 4 ch Timer/counter - Watchdog timer - Serial interface CSI x 1 ch CSI/UART x 2 ch UART x 1 ch A/D converter 10-bit x 8 ch D/A converter - - DMA controller 4 ch 106 4 ch - 74 9 5 - - Ports I/O Input Debug control unit CSI/UART x 2 ch 10-bit x 4 ch 12-bit PWM output x 2ch - Operating frequency 4 to 50 MHz 4 to 40 MHz Power supply voltage 3.0 to 3.6 V 3.0 to 3.6 V Other peripheral functions 528 mW (@ 3.3 V, 50 MHz) Power consumption (Typ.) Package 144-pin LQFP (20 x 20 mm) Operating ambient temperature 627 mW (@ 3.3 V, 50 MHz) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) -40C to +85C Note Number of external interrupts that can be used to release STOP mode 50 256 KB (flash) 10 KB Bus type V850E/MA2 PD703108 V850E1 67 MIPS (@ 50 MHz) ROM-less Internal RAM Interrupt sources PD70F3107A V850E1 CPU core External bus interface PD703107A Pamphlet U15412EJ4V1PF 416 mW (@ 3.3 V, 40 MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C High-End Lineup (2/2) V850E/MS1 Item Part No. External 3.3V External 5V PD703101A-33 PD703102A-33 PD70F3102A-33 PD703100-33/-40 PD703101-33 PD703102-33 PD70F3102-33 - CPU performance 96 KB (mask) 128 KB (mask) Bus type Address bus Data bus ROM-less 4 KB 4 KB Separate 24 bits 24 bits 8/16 bits 8/16 bits Chip select signal Memory controller 128 KB (flash) Separate Internal RAM Interrupt sources - 47 MIPS (@ 33 MHz) ROM-less Internal ROM PD703130 V850E1 V850E1 CPU core External bus interface V850E/MS2 PD703100A-33/-40 8 4 EDO DRAM, SRAM, etc. EDO DRAM, SRAM, etc. Internal 47 35 External 25 (1)Note1 10 (1)Note1 16-bit timer/event counter x 6 ch 16-bit interval timer x 2 ch 16-bit timer/event counter x 4 ch 16-bit interval timer x 2 ch Timer/counter Watchdog timer - - Serial interface CSI x 2 ch CSI/UART x 2 ch CSI/UART x 2ch A/D converter 10-bit x 8 ch 10-bit x 4 ch D/A converter - - DMA controller 4ch 4 ch 122 52 9 5 Debug control unit - - Other peripheral functions - - Operating frequency 2 to 40 MHz (-40 product) 2 to 33 MHz (-33 product) 10 to 33 MHz Power supply voltage 3.0 to 3.6 V (internal, external) (A products) 3.0 to 3.6 V (internal)/4.5 to 5.5 V (external) (Products without A) 3.0 to 3.6 V (internal)/ 4.5 to 5.5 V (external) Ports I/O Input Power consumption (Typ.) 272 mW (@ 3.3 V, 33 MHz) 430 mW (@ 5 V, 33 MHz) Package Operating ambient temperature 294 mW (@ 3.3 V, 33 MHz) 515 mW (@ 5 V, 33 MHz) 218 mW (@ 3.3 V, 33 MHz) 144-pin LQFP (20 x 20 mm) 157-pin FBGA (14 x 14 mm)Note2 100-pin LQFP (14 x 14 mm) -40C to +85CNote3 -40C to +85C Notes 1. Number of external interrupts that can be used to release STOP mode 2. PD703100A-33, 703101A-33, 703102A-33, and 70F3102A-33 only 3. PD703100-40, 703100A-40 : -40C to +70C Others : -40C to +85C V853 Item PD703003A Part No. PD703004A PD703025A 38 MIPS (@ 33 MHz) CPU performance 128 KB (mask) Internal ROM 96 KB (mask) 256 KB (mask) 128 KB (flash) 8 KB 4 KB 8 KB 425 mW (@ 5 V, 33 MHz) 480 mW (@ 5 V, 33 MHz) 4 KB Internal RAM Address bus 20 bits Data bus 16 bits - SRAM, etc. Memory controller Internal 32 External 17(1)Note 16-bit timer/event counter x 4 ch 16-bit interval timer x 1 ch Timer/counter Watchdog timer - Serial interface CSI x 2 ch CSI/UART x 2 ch A/D converter 10 bits x 8 ch D/A converter 2 ch - DMA controller Ports 256 KB (flash) Multiplexed Bus type Chip select signal Interrupt sources PD70F3025A V850 CPU core External bus interface PD70F3003A I/O 67 Input 8 - Debug control unit 12-bit PWM output x 2 ch Other peripheral functions Operating frequency 2 to 33 MHz Power supply voltage 4.5 to 5.5V Power consumption (Typ.) Package Operating ambient temperature 365 mW (@ 5 V, 33 MHz) 450 mW (@ 5 V, 33 MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ4V1PF 51 V850 Series Development Environment The V850 Series development environment consists of tools designed to make the development of application systems using the V850 Series of highperformance microcontrollers made by NEC Electronics more pleasant, faster, and more accurate. Each one of these development tools features functions to fully exploit the performance of the V850 Series. 52 Pamphlet U15412EJ4V1PF Low-Priced Development Environment Lineup Price Emulator and evaluation board available at low prices Low-priced full-function emulator IECUBE * Low prices 1/3 or 1/4 the price of conventional emulators * Connectable to PC via USB * Enhanced real-time RAM monitor and time measuring function * On-chip self-diagnosis function * Debugger and simple programmer provided * Palm size Ultra-low-priced on-chip emulator N-Wire CARD * Ultra low price 1/10 the price of conventional emulators * Connectable to PC via PCMCIA * Writing to the microcontroller on-chip flash memory possible * Debugger provided Starter kit for simple evaluation TK-850 Series * Evaluation kit enabling easy performance testing * Lineup for V850ES/Kx1, V850ES/SA2, and V850ES/SG2 * Debugger, compiler, and circuit diagrams provided as standard Function * For details, refer to V850 Series Development Environment Pamphlet (U15763E) Pamphlet U15412EJ4V1PF 53 Development Flow Product planning PM plus System design Hardware design Software design RX850, RX850 Pro Coding Fabrication Standalone testing Compiling/ assembly CA850 Debugging SM850, SM plus System debugging System evaluation IE, IECUBE +RD850, +RD850 Pro +AZ850, +TW850 ID850, ID850NW, ID850QB Commercialization Software tools Development Tools (1/3) Software tools Product Name Software package SP850 C compiler CA850Note 1 Device file DF703xxxNote 2 Project Manager PM plusNotes 1, 3 Integrated debugger ID850Note 1, ID850NWNote 1, ID850QBNote 4 System simulator SM850Note 1, SM plusNote 5 Real-time OS RX850, RX850 Pro Task debugger RD850, RD850 ProNote 6 System performance analyzer AZ850Note 6 Middleware AP703000-Bxxx, AP703100-Bxxx Performance analysis tool TW850Note 1 Notes 1. Packaged in SP850 2. Download from the NEC Electronics Website. (URL: http://www.necel.com/micro/index_e.html) 3. Included with CA850 4. Included with IECUBE and IE-V850E1-CD-NW. 5. Instruction simulation version: Included with SP850. Instruction + peripheral simulation version: Only the SM plus for the PD70F3261Y is included with SP850. 6. Included with RX850, RX850 Pro Remark For details, refer to the V850 Series Development Environment Pamphlet (U15763E). 54 DF703xxx Hardware tools Pamphlet U15412EJ4V1PF Development Tools (2/3) Hardware tools (when using IECUBE) Target Device In-Circuit Emulator V850ES/SG2, V850ES/SJ2 QB-V850ESSX2-ZZZ V850E/IA3, V850E/IA4, V850ES/IK1 QB-V850EIA4-ZZZ V850ES/KE1, V850ES/KE1+, V850ES/KF1, V850ES/KF1+, V850ES/KG1, V850ES/KG1+, V850ES/KJ1, V850ES/KJ1+ QB-V850ESKX1H-ZZZ V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, PD703229Y, 70F3229Y QB-V850ESFX2-ZZZ Remarks 1. A separate socket is required for each above emulator. 2. A power supply, a USB interface cable, a debugger, and a simple programmer are included. A PC interface board is not required. 3. For details, refer to the V850 Series Development Environment Pamphlet (U15763E). Hardware tools (when using N-Wire CARD) Target Device On-Chip Debug Emulator V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2, V850ES/SJ2, V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, V850ES/KJ1, V850ES/KJ1+, PD70F3229Y IE-V850E1-CD-NW Remarks 1. A target connection cable, a connector conversion board, a target connector, and a debugger are included. A power supply and a PC interface board are not required. 2. For details, refer to the V850 Series Development Environment Pamphlet (U15763E). Hardware tools (using other emulators) In-Circuit Emulator Target Device Emulation Board Main Unit V850ES/SA2, V850ES/SA3 IE-703204-G1-EM1Note 1 V850ES/KF1, V850ES/KG1, V850ES/KJ1 IE-703217-G1-EM1Note 2 V850ES/SG2, V850ES/SJ2 IE-V850ES-G1 V850ES/PM1 IE-703288-G1-EM1Note 2 IE-703228-G1-EM1Note 2 V850ES/FE2, V850/FF2, V850ES/FG2, V850ES/FJ2, PD703229Y, 70F3229Y IE-703239-G1-EM1Note 2 V850ES/ST2 IE-703220-G1-EM1Note 2 V850E/SV2 IE-V850E-MC-A V850E/MA1, V850E/MA2 V850E/IA1 IE-V850E-MC V850E/IA2 V850E/MS1 (5V), V850E/MS2 (5V) IE-703102-MC V850E/MS1 (3.3V) IE-703166-MC-EM1 IE-703107-MC-EM1Note 3 IE-703116-MC-EM1 IE-703114-MC-EM1 IE-703102-MC-EM1Note 3 IE-703102-MC-EM1-A V850/SA1 IE-703017-MC-EM1Note 3 V850/SB1, V850/SB2 IE-703037-MC-EM1Note 3 V850/SV1 IE-703002-MC V850/SF1 IE-703040-MC-EM1Note 3 IE-703079-MC-EM1Note 3 V850/SC1, V850/SC2, V850/SC3 IE-703089-MC-EM1 V853 IE-703003-MC-EM1 Notes 1. A separate socket and probe are required for connection to the target system. The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part. 2. A separate socket is required for connection to the target system. The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part. 3. Depending on the target device package, a separate socket and probe may be required. The following items are required as common items. * PC interface board: IE-70000-PCI-IF-A or IE-70000-CD-IF-A * Power supply: IE-70000-MC-PS-B Remark For details, refer to the V850 Series Development Environment Pamphlet (U15763E). Pamphlet U15412EJ4V1PF 55 Development Tools (3/3) * * IECUBE configuration example N-Wire CARD configuration example In-circuit emulator (IECUBE) AC adapter (provided with ) USB interface cable (provided with ) Extension probe Note Exchange adapter (provided with ) Note Target connector (provided with ) Mount adapter Host machine (with PCMCIA slot) On-chip emulator IE-V850E1-CD-NW In-circuit emulator connection cable Connector conversion board In-circuit emulator connector Note If ordering the in-circuit emulator ( ), if the part number ends in "-ZZZ", the above exchange adapter ( ) and target connector ( ) are not provided. * IE-V850ES-G1 configuration example * IE-V850E-MC, IE-V850E-MC-A, IE-703102-MC, IE-703002-MC configuration example In-circuit emulator (main unit) Emulation board (connected inside main unit) Emulation probe Conversion adapter/conversion socket PC interface cable (provided with ) Power supply cable (provided with ) 56 In-circuit emulator (main unit) Option board Power supply unit Conversion adapter/conversion socket (provided with PC interface cable (provided with ) Pamphlet U15412EJ4V1PF ) V850 Series Development Environment (1/2) Development environment using in-circuit emulator, N-Wire emulator Real-time OS Compiler Task debugger In-circuit emulator N-Wire emulator Debugger Analyzer Integrated development environment RX850 RX850 Pro CA850 RD850 Note RD850 Pro Note ID850 AZ850 Note TW850 ID850 CATS ZIPC850 ATI Nucleus PLUS CCV850 CCV850E Metrowerks Refer to Development Tools Hardware tools (when using N-Wire CARD) (p. 55) QB-V850ESSX2-ZZZ QB-V850EIA4-ZZZ QB-V850ESKX1H-ZZZ QB-V850ESFX2-ZZZ Refer to Development Tools Hardware tools (when using IECUBE) (p. 55) IE-V850E1-CD-NW Refer to Development Tools Hardware tools (when using N-Wire CARD) (p. 55) IE-70000-MC-NW-A Nx85ET Midas Lab ID850NW GHS IE-703002-MC IE-703102-MC IE-V850E-MC IE-V850E-MC-A IE-V850ES-G1 ID850QB AZ850 TW850 GHS MULTI AZ850 RTE-V852-IE RTE-V853-IE RTE-V850/SA1-IE RTE-V850/SB1-IE RTE-V850E/MA1-IE RTE-V850E/IA1-IE RTE-1000-TP RTE-2000-TP KIT-V850E/MA3-IE CodeWarrior Sophia Systems KMC Mispo NORTi Red Hat PARTNER AZ850 GNU Sophia Systems KMC exeGCC GAIO G-OS Native-G GAIO XCC-V XASS-V V852 V853, V853A V850/SA1 V850/SB1, V850/SB2 V850E/MA1 V850E/ IA1 Nx85ET Nx85ET, V850E/ME2, V850E/MA3, NA85E2, AS85EP2 V850E/MA3 WATCHPOINT AZ850 UniSTAC V853 UniSTAC V850/SV1 UniSTAC V850/SA1 UniSTAC V850/SB1 UniSTAC V850E/MS1 UniSTAC V850E/MA1 UniSTAC Nx85ET UniSTAC V850E/IA1 UniSTAC V850ES/Kx1 V853, V853A V850/SV1 V850/SA1 V850/SB1, V850/SB2 V850E/MS1 V850E/MA1 Nx85ET, Nx85E V850E/IA1 V850ES/KF1, V850ES/KG1, V850ES/KJ1 V850E/ME2 V850ES/SG2, V850ES/SJ2, V850ES/Fx2, V850ES/Kx1+, V850ES/Kx1, V850ES/IK1, V850E/IA3, V850E/IA4 UniSTACII/J V850E/ME2 IECUBE YDC micro VIEW-G micro VIEW-PLUS YDC advice advice advice advice advice advice advice advice advice advice advice V853 V850/SA1 V850/SB1 V850E/MS1 V850E/MA1 Nx85ET V850E/IA1 V850E/ME2 V850ES/KF1 V850ES/KG1 V850ES/KJ1 V853 V850/SA1 V850/SB1 V850E/MS1 V850E/MA1 Nx85ET V850E/IA1 V850E/ME2 V850ES/KF1 V850ES/KG1 V850ES/KJ1 KMC PARTNER-ET II PARTNER-J PARTNER-Jet Nx85ET, V850E/ME2 Nx85ET, V850E/ME2 Nx85ET, V850E/ME2 Note The RD850, RD850 Pro, and AZ850 can be used with the ID850, ID850QB, MULTI, PARTNER, and WATCHPOINT. ATI CATS GAIO GHS KMC Metrowerks :Accelerated Technology, Inc. :Communication and Technology Systems, Inc. :Gaio Technology Co., Ltd. :Green Hills Software, Inc. :Kyoto Microcomputer Corporation :Metrowerks Corporation Midas Lab Mispo Red Hat Sophia Systems YDC Unmarked Pamphlet U15412EJ4V1PF :Midas Lab Co., Ltd. :MiSPO, Inc. :Red Hat Corporation :Sophia Systems Co., Ltd. :Yokogawa Digital Computer Corporation :NEC Electronics 57 V850 Series Development Environment (2/2) Development environment using ROM emulator, evaluation board Real-time OS Compiler Debugger ROM emulator Analyzer Task debugger Evaluation board Low-cost evaluation board (limited functions) Evaluation board Cosmo CA850 RX850 RX850 Pro KMC RD850 Note RD850 Pro Note exeGCC CEB-V850/SA1 CEB-V850/SB1 V850/SA1 V850/SB1 CEB-V850E/MS1 CEB-V850E/MA1 V850E/MS1 V850E/MA1 KMC PARTNER AZ850 Note GHS CCV850 CCV850E Midoriya CEB-V850E/MA3 CEB-V850E/IA1 CEB-V850ES/FJ2 CEB-V850ES/SJ2 V850E/MA3 V850E/IA1 V850ES/FJ2 V850ES/SJ2 EMUSE-GII ATI Nucleus PLUS KMC Metrowerks Code Warrior PARTNER-ET II GHS MULTI Midoriya AZ850 Midas Lab RTE-V852-PC RTE-V853-PC V852 V853 EMUSE Mispo NORTi Lightwell Red Hat MDX700 GNU RTE-V850E/MS1-PC RTE-V850E/MA1-CB RTE-V850E/ME2-CB RTE-V850ES/SA3-CB V850E/MS1 V850E/MA1 V850E/ME2 V850ES/SA3 APPLY TK-850/KG1 V850ES/KG1 CA850 GAIO G-OS Native-G GAIO XCC-V XASS-V Monitor version ID850 APPLY GAIO TK-850/SA2 XDEB-V SystemSimulator V850ES/SA2 APPLY TK-850/SG2 SG-703107-1 SG-703111-1 Note RD850, RD850 Pro, and AZ850 can be used with MULTI, PARTNER. APPLY ATI Cosmo Red Hat GAIO GHS KMC Lightwell 58 :Application Corporation :Accelerated Technology, Inc. :Cosmo Co., Ltd. :Red Hat Corporation :Gaio Technology Co., Ltd. :Green Hills Software, Inc. :Kyoto Microcomputer Corporation :Lightwell Co., Ltd. Metrowerks Midas Lab Midoriya Mispo WRS eSOL Unmarked Pamphlet U15412EJ4V1PF :Metrowerks Corporation :Midas Lab, Co., Ltd. :Midoriya Electric Co., Ltd. :MiSPO, Inc. :Wind River Systems, Inc. :eSOL Co., Ltd. :NEC Electronics V850ES/SG2 V850E/MA1 V850E/ME2 Software Product Software package (SP850) C compiler (CA850) Product configuration Features The SP850 software package consists of the following software development tools. *C compiler (CA850) *Project Manager (PM plus) *Integrated debugger (ID850, ID850NW) (to be packaged) *System simulator (SM850, SM plus) (to be packaged) *Performance analysis tuning tool (TW850) *Device file (DF703xxx) System simulator (SM850, SM plus) Features *Complies with ANSI-C, a C language standard. *Supports libraries for embedded systems *Compact code size and faster execution speed can be realized through powerful optimization *Utilities useful for embedded systems (ROMization processor, etc.) *Description of embedded systems in C language (specification of memory allocation and I/O register access) is possible. Project manager (PM plus) Features *Same operability as debugger *Target-less evaluation prior to target completion possible *In addition to the operation of the CPU itself, target system operation including on-chip peripheral unit and interrupt servicing can also be simulated. *Pseudo-target system construction and I/O operation are possible through external parts. *Data generated by 0/1 logic and timing charts can be input to the program being simulated. *Larger number of events than in-circuit emulator *Execution speed estimates can be done on the host machine to accurately simulate pipeline operationNote. *Construction by user target system users is possible through user open interface. *A peripheral I/O register status can be specified and when this status occurs, the system can be made to output an interrupt at the desired timing or transfer data to memory (peripheral I/O register event & action function). *Project management (management of target chip, source, and environment during debugging is possible.) *Supports wizard function during project creation *Automation of series of operations consisting of edit, build, and debug *Integration of Help function Note The pipeline mode is supported by the V853. Target devices V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850/SC1, V850/SC2, V850/SC3, V850E/MS1, V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2, V850ES/SA2, V850ES/SA3, V850ES/KF1, V850ES/ KG1, V850ES/KJ1, V850ES/SG2Note, V850ES/SJ2Note, V850ES/FE2Note, V850ES/FF2Note, V850ES/FG2Note, V850ES/FJ2Note Note Only SM plus is supported N-Wire card (IE-V850E1-CD-NW) Features *Supports V850E and V850ES *Emulator for on-chip debugging *Enables realization of low-cost development environment *Compact PC card type *Function for download to internal flash ROM *Same ease of operation as ID850 Target Devices V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2, V850ES/SJ2, V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, V850ES/KJ1, V850ES/ KJ1+, PD70F3229Y Pamphlet U15412EJ4V1PF 59 Integrated debugger (ID850, ID850NW, ID850QB) Features Task debuggers (RD850, RD850 Pro) Features *Supports object files *Debugging at source level *Debugging using target resources *Real-time execution on target *Event setting according to complex software operation *Online help function *Display detailed information on OS resources such as tasks. *Display source of referenced tasks. *Included with real-time OS (RX850, RX850 Pro) Real-time OSs (RX850, RX850 Pro) Features TCP/IP software library (RX-NET) for V850E products Product configuration *Comply with global standard (ITRON 3.0 specifications). *Support power management function. *Enable embedding of required functions only (selection of system calls to be used). *Support sophisticated task development through task debugger (RD). *Support application operation analysis through system performance analyzer (AZ) *Inherit attributes of real-time OS of 16-bit V Series and 78K Series System performance analyzer (AZ850) *TCP/IP protocol stack *Applications *LAN control driver Features *RFC-compliant *Support of numerous socket interfaces/libraries *Support of applications as option products *Provided device driver *Support of NEC Electronics real-time OS (RX850 Pro) Target devices V850E products Features *Detection of bugs through system timing errors *Detection of bugs due to simultaneous operation of complex tasks *Detection/analysis of real-time system execution performance *Operation linked to various debuggers Performance analysis tuning tool (TW850) Features *Performance analysis changing the internal ROM size, instruction cache size, etc., is possible. *Display of inter-function call relationships, call count information, function execution time information, and cache mishit information *Functions optimally placed to reduce cache mishit count *Functions causing bottlenecks placed into internal ROM or other high-speed access memory In-circuit emulator (IE, IECUBE) Features *Emulator functions loaded in dedicated chip to realize high equivalence *Connectable to variety of computers *Large array of emulation functions *Realization of maximum operating frequency equivalent to that of device 60 Pamphlet U15412EJ4V1PF OSEK/VDX specifications compliant OS (RX-OSEK850) Features * Kernel Compliant with OSEK/VDX OS Ver. 2.0 specifications Supports 4 conformance classes: BCC1, BCC2, ECC1, and ECC2. * Configurator Configurator (OIL850) allowing easy system information creation provided as standard. Configuration files support formats compatible with OIL Ver. 2.0. * Task debugger (RD-OSEK850) Task debugger effective for application debugging using RX-OSEK850 provided as standard RISC microcontroller reference platform (SolutionGearTM) Features General-purpose evaluation boards available as RISC microcontroller software development platform Target CPU: V850E/MA1, V850E/ME2 Industry standard PC-compatible interfaces including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB, provided CPU independent motherboards and CPU boards used combined Bundled real-time OS, middleware, and sample drivers MULTI-PARTNER remote monitor version can be used Reference design information provided Actually tested Circuit diagrams attached H/W S/W Device selection I want to measure Is it possible to realize CPU performance. such a function? I would like to use OS/middleware. First time I use this device, please provide sample circuits. Board design/ development Software design/ development I want to start software development prior to the board. Bundle OS/ middleware This board usable for comparison purposes Various peripheral devices are mounted, so debugging can be started from device-independent parts Not working properly. Is the cause hardware or software? Debug * * * * * * * Time Likely to be a long time until OS/middleware are ready Provide user-own coding block as sample according to this board At such times, RISC microcontroller reference platform Cooperation with third parties By deepening cooperation with third-party companies and forming an array of tools combining NEC Electronics-made tools and third-party-made tools, NEC Electronics offers development environments that support the diverse needs of users. Pamphlet U15412EJ4V1PF 61 V850 Series Website Information about V850 microcontrollers and V850 microcontroller development environment can be viewed at the NEC Electronics Microcomputer website. http://www.necel.com/micro/index_e.html Microcontroller Search Tool * Facility for searching for V850 Series microcontrollers by function Product Lineup * Microcontroller product information Document Download * Microcontroller, development environment, and middleware documents can be downloaded from this area. http://www.necel.com/micro/english/document/index.html Development Tool Download * V850 Series development tools can be downloaded from this area. Customers who are registered users receive upgrade information by email. http://www.necel.com/micro/ods/eng/index.html 62 Pamphlet U15412EJ4V1PF Microcontroller Search Tool Facility for searching V850 Series microcontrollers by function. Specify search condition(s) here. The corresponding NEC Electronics development environment documents can be searched from here with a single link. Development Tool List Document Information List Pamphlet U15412EJ4V1PF 63 Product Lineup 64 Pamphlet U15412EJ4V1PF MEMO Pamphlet U15412EJ4V1PF 65 MEMO 66 Pamphlet U15412EJ4V1PF EEPROM, IEBus, IECUBE, SolutionGear, and VR are trademarks of NEC Electronics Corporation. MIPS is a trademark of MIPS Technologies, Inc. in the United States. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. JAVA and all trademarks and logos related to JAVA are either registered trademarks or trademarks of Sun Microsystems, Inc. in the United States and/or other countries. Ethernet is a trademark of Xerox Corporation. TRON stands for The Real-time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. ITRON is an abbreviation of Micro Industrial TRON. TRON, ITRON, and ITRON do not refer to specific products or product groups. All other marks or trademarks in this document are property of their respective holders. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of September, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 Pamphlet U15412EJ4V1PF 67 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [North America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.necelam.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.ee.nec.de/ NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 Succursale Francaise 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven The Netherlands Tel: 040-2445845 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 Tyskland Filial P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Document No. U15412EJ4V1PF00 (4th edition) Date Published January 2005 N CP(K) C 2002, 2004 G04.1 Printed in Japan