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AMD Geode™ CS5536 Companion Device Data Book

AMD Geode™ CS5536

Companion Device Data Book

May 2007

Publication ID: 33238G

2AMD Geode™ CS5536 Companion Device Data Book

The contents of this document are provided in connection with Advanced Micro

Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with

respect to the accuracy or completeness of the contents of this publication and

reserves the right to make changes to specifications and product descriptions at

any time without notice. No license, whether express, implied, arising by estoppel

or otherwise, to any intellectual property rights is granted by this publication.

Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD

assumes no liability whatsoever, and disclaims any express or implied warranty,

relating to its products including, but not limited to, the implied warranty of mer-

chantability, fitness for a particular purpose, or infringement of any intellectual

property right.

AMD’s products are not designed, intended, authorized or warranted for use as

components in systems intended for surgical implant into the body, or in other

applications intended to support or sustain life, or in any other application in which

the failure of AMD’s product could create a situation where personal injury, death,

or severe property or environmental damage may occur. AMD reserves the right to

discontinue or make changes to its products at any time without notice.

Contacts

www.amd.com

Trademarks

AMD, the AMD Arrow logo, AMD Geode and combinations thereof, and GeodeLink are trademarks of

Advanced Micro Devices, Inc.

Windows is a registered trademark of Microsoft Corporation in the United States and other jurisdiction.

WinBench is a registered trademark of Ziff Davis, Inc.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective

companies.

AMD Geode™ CS5536 Companion Device Data Book 3

Contents 33238G

Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1 GeodeLink™ PCI South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2 GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.3 IDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.4 Universal Serial Bus Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.5 Audio Codec 97 (AC97) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6 Diverse Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.7 GeodeLink™ Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.8 Low Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.9 Processor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.0 Global Concepts and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.1 GeodeLink™ Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4.2 MSR Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.3 Typical GeodeLink™ Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.4 Clock Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.5 Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.6 Memory and I/O Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.7 Standard GeodeLink™ Device MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.9 Component Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4AMD Geode™ CS5536 Companion Device Data Book

Contents

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5.0 Module Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.1 GeodeLink™ Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.2 GeodeLink™ PCI South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.3 AC97 Audio Codec Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 8

5.4 IDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.5 Universal Serial Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

5.6 Diverse Integration Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

5.7 Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

5.8 Programmable Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

5.9 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.10 Keyboard Emulation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

5.11 System Management Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

5.12 UART and IR Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

5.13 Low Pin Count Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

5.14 Real-Time Clock Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

5.15 General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

5.16 Multi-Function General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

5.17 Power Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

5.18 Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

5.19 GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

5.20 Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

6.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.1 GeodeLink™ Interface Unit Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

6.2 GeodeLink™ PCI South Bridge Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

6.3 AC97 Audio Codec Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

6.4 USB Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

6.5 IDE Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

6.6 Diverse Integration Logic Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

6.7 Floppy Port Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

6.8 Programm able Interval Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

6.9 Programmable Interrupt Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

6.10 System Management Bus Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394

6.11 Keyboard Emulati on Logic Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

6.12 UART and IR Port Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

6.13 Direct Memory Access Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447

6.14 Low Pin Count Regist er Descr ipt ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466

6.15 Real-Time Clock Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469

6.16 GPIO Device Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .480

6.17 Multi-Function General Purpose Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .513

6.18 Power Management Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524

6.19 Flash Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549

6.20 GeodeLink™ Control Processor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561

AMD Geode™ CS5536 Companion Device Data Book 5

Contents 33238G

7.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

7.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575

7.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578

7.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580

7.4 Power Supply Sequence Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600

7.5 Low Voltage Detect (LVD) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

7.6 Skip Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605

8.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

A.1 Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609

A.2 Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

6AMD Geode™ CS5536 Companion Device Data Book

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AMD Geode™ CS5536 Companion Device Data Book 7

List of Figures 33238G

List of Figures

Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 2-1. Mobile Computing System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 2-2. Single Board Computing System Block Diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 3-1. Typical Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 3-2. 208-PBGA Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 4-1. Simplified GLIU with Generic GeodeLink™ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 4-2. GeodeLink™ Architecture ASMI and Error Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 4-3. AMD Geode™ CS5536 Companion Device GeodeLink™ Architecture Topology . . . . . . . .58

Figure 4-4. Typical AMD Geode™ CS5536 Companion De vice GeodeLink™ Device . . . . . . . . . . . . . .62

Figure 4-5. Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 4-6. Direct ASMI Behavioral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 4-7. In-Direct ASMI Behavioral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 5-1. Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 5-2. GLPCI_SB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 5-3. ACC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Figure 5-4. AC Link Slot Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Figure 5-5. AC Link Output Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Figure 5-6. AC Link Input Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Figure 5-7. ACC PRD Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 5-8. USB Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Figure 5-9. Diverse Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Figure 5-10. I/O Space LBAR - Fixed Target Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Figure 5-11. I/O Space LBAR - Variable Target Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Figure 5-12. Memory Space LBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Figure 5-13. PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Figure 5-14. PIT Counter Latch Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Figure 5-15. PIT Read-Back Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Figure 5-16. PIT Status Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Figure 5-17. PIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Figure 5-18. Cascading 8259As for LPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Figure 5-19. PIC 8259A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Figure 5-20. DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Figure 5-21. KEL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Figure 5-22. SMB Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Figure 5-23. SMB Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Figure 5-24. SMB START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Figure 5-25. SMB Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Figure 5-26. SMB Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Figure 5-27. SMB Complete Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Figure 5-28. SMB Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 5-29. SMB Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 5-30. SMB Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 5-31. SMB Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 5-32. SMB Sequential Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 5-33. UART/IR Overview Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Figure 5-34. UART Serial Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

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Figure 5-35. Real Dongle Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 5-36. Virtual Dongle Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 5-37. LPC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Figure 5-38. Start of Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 5-39. Abort Mechanism Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 5-40. DMA Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Figure 5-41. Start Frame Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 5-42. IRQ Frame Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 5-43. Stop Frame Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Figure 5-44. FWH Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Figure 5-45. FWH Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Figure 5-46. RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Figure 5-47. Recommended External Comp onent Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Figure 5-48. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Figure 5-49. MFGPT Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Figure 5-50. MFGPT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Figure 5-51. MFGPT Bit Reverse Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Figure 5-52. PMC Power Management Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 5-53. PMC System Sleep Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 5-54. PMC System Wakeup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Figure 5-55. Flash Controller NAND Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Figure 5-56. NOR Flash Basic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Figure 5-57. NOR Flash with Wait States Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 5-58. NAND Flash Command/Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Figure 5-59. NAND Data Timing with No Wait States and No Prefetch (for the first data read) . . . . . . .187

Figure 5-60. NAND Data Timing with Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 5-61. GLCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Figure 5-62. TAP Controller Boundary Scan Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 6-1. UART Register Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413

Figure 6-2. DMA Control Signals Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

Figure 7-1. Clock Reference Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580

Figure 7-2. AC Reference Timing and Test Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580

Figure 7-3. Output Reference Timing and Test Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581

Figure 7-4. Input Reference Timing and Test Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581

Figure 7-5. IDE Data In Timing Non-UltraDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586

Figure 7-6. IDE UltraDMA Data Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587

Figure 7-7. IDE UltraDMA Data In Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588

Figure 7-8. RESET_STAND# Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601

Figure 7-9. VCORE Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602

Figure 7-10. VIO_VSB Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603

Figure 7-11. LVD Electrical Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

Figure 7-12. Debounce Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

Figure 7-13. Skip Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605

Figure 8-1. PBGA 208 Top View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607

Figure 8-2. PBGA 208 Bottom View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608

Figure A-1. AMD Geode™ CS5536 Companion Device OPN Example . . . . . . . . . . . . . . . . . . . . . . . .609

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List of Tables

Table 3-1. Abbreviations/Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 3-2. Ball Assignme nts: Sorted by Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 3-3. Ball Assignments: Sorted Alphabetically by Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 3-4. Buffer Type Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 3-5. Boot Options Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 3-6. DIVIL_BALL_OPT (DIVIL MSR 51400015h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 3-7. IDE and Flash Ball Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 3-8. GPIO Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 3-9. GPIOx Available Functions Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 4-1. MSR Routing Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 4-2. MSR Addresses from AMD Geode™ LX Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 4-3. Clock Sources and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 4-4. AMD Geode™ CS5536 Companion Device Register Space Map Except Diverse Device . .68

Table 4-5. Diverse Device Spac e Ma p Excep t Le gacy I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-6. Legacy I/O: 000h-4FFh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 4-7. GLD_MSR_ CAP Bit Desc rip tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 4-8. Standard GLD_MSR_SMI Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 4-9. GLD_MSR_SMIs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 4-10. MSR Power Management Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 4-11. Sleep Driven PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 4-12. Sleep Driven IDE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-1. GLIU Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 5-2. GLIU Descriptors Reserved for GeodeLink™ Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 5-3. CIS Serial Bits Assignment and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 5-4. Audio Bus Master Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 5-5. SLOTREQ to Output Slot Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 5-6. Physical Region Descriptor (PRD) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 5-7. PCM Data format (Byte and Chan nel Ordering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table 5-8. Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Table 5-9. UDMA Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Table 5-10. Special Cycle Decodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 5-11. 8254 PIT Register Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table 5-12. IRQ Map - Primary and LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 5-13. IRQ Map - Unrestricted Sources Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 5-14. IRQ Map - Unrestricted Sources Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 5-15. 8259A PIC I/O Addresses an d I/O Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table 5-16. DMA Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Table 5-17. KEL Mixed Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 5-18. Comparison of SMB, Industry Standard Two-wire Interface, and ACCESS.bus . . . . . . . . .126

Table 5-19. SMB Native Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Table 5-20. UART/IR Controller Native Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 5-21. Real Dongle Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Table 5-22. Cycle Type s Sup por te d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Table 5-23. Cycle Field Definitions: Target Memory, I/O, and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Table 5-24. Host Initiated Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

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Table 5-25. DMA Initiated Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Table 5-26. IRQ Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 5-27. FWH Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Table 5-28. FWH Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 5-29. External Component Recommended Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Table 5-30. Effect on Feature Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 5-31. 16-Bit GPIO Control Register Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Table 5-32. MFGPT Prescaler Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Table 5-33. MFGPT Pulse Density Modulation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 5-34. Supported ACPI Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 5-35. PM Events and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Table 5-36. ECC Parity/Bit Address Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 5-37. NAND Flash External Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 5-38. TAP Controller Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 6-1. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 6-2. P2D Descriptor MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

Table 6-3. GLIU Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Table 6-4. IOD Descriptor MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Table 6-5. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Table 6-6. GLPCI_SB Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Table 6-7. PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Table 6-8. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Table 6-9. ACC Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

Table 6-10. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

Table 6-11. USB Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

Table 6-12. USB Open Host Controller Inte rface Native Registers Summary . . . . . . . . . . . . . . . . . . . .258

Table 6-13. USB Enhanced Host Controller Interface Native Registers Summary . . . . . . . . . . . . . . . . .259

Table 6-14. USB Device Controller Nat ive Re gist er s Sum mar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

Table 6-15. USB Option Controller Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

Table 6-16. UDC Reaction Durin g the STATUS-OUT Stage of a CONTROL Transfer . . . . . . . . . . . . .323

Table 6-17. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

Table 6-18. IDE Controller Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

Table 6-19. IDE Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332

Table 6-20. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

Table 6-21. DIVIL Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

Table 6-22. Floppy Port Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

Table 6-23. PIT Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

Table 6-24. PIT Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371

Table 6-25. PIC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

Table 6-26. PIC Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

Table 6-27. SMB Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394

Table 6-28. KEL Specific MSRs Summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

Table 6-29. KEL Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

Table 6-30. KEL Legacy Registers Emulated Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

Table 6-31. UART/IR Controller Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

Table 6-32. UART/IR Controller Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

Table 6-33. Secondary ID Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

Table 6-34. Register Bank Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413

Table 6-35. Bank 0 Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414

Table 6-36. EIR Non-Extended Mode Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418

Table 6-37. Bit Settings for Parity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421

Table 6-38. Bank Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

Table 6-39. Bank 1 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428

Table 6-40. Bits Cleared on Fallback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428

Table 6-41. Baud Generator Divisor Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429

AMD Geode™ CS5536 Companion Device Data Book 11

List of Tables 33238G

Table 6-42. Bank 2 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430

Table 6-43. DMA Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432

Table 6-44. Bank 3 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435

Table 6-45. Bank 4 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436

Table 6-46. Bank 5 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

Table 6-47. Bank 6 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438

Table 6-48. Bank 7 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440

Table 6-49. CEIR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in KHz) . . . . . . . . . . . .441

Table 6-50. Consumer IR High Spe ed Demodulator (RXHSC = 1) (Frequency Ranges in KHz) . . . . . .441

Table 6-51. Sharp-IR Demodulator (Frequency Ranges in KHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441

Table 6-52. Modulation Carrier Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442

Table 6-53. CEIR Carrier Frequency Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

Table 6-54. IR Receive Input Selectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446

Table 6-55. DMA Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447

Table 6-56. DMA Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447

Table 6-57. LPC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466

Table 6-58. RTC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469

Table 6-59. RTC Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469

Table 6-60. GPIO Low/High Bank Feature Bit Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .480

Table 6-61. GPIO Input Conditioning Function Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .482

Table 6-62. GPIO Interr up t an d PME Map per Regis te rs Sum m a ry . . . . . . . . . . . . . . . . . . . . . . . . . . . .483

Table 6-63. Low Bank Atomic Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484

Table 6-64. Low Bank Atomic Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484

Table 6-65. High Bank Atomic Register Map Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485

Table 6-66. High Bank Atomic Bit Descript ions Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485

Table 6-67. MFGPT Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513

Table 6-68. MFGPT Native Regist er s Sum m ar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513

Table 6-69. PMC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524

Table 6-70. ACPI Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524

Table 6-71. PM Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525

Table 6-72. Flash Controller Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549

Table 6-73. Flash Controller Native Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550

Table 6-74. Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561

Table 6-75. GLPC Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561

Table 6-76. Clock Mapping / Operational Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566

Table 7-1. Electro Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575

Table 7-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575

Table 7-3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576

Table 7-4. Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577

Table 7-5. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578

Table 7-6. Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582

Table 7-7. Reset and Te st Ti min g Para me te rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583

Table 7-8. PCI, SUSP#, SUSPA#, and RESET_OUT# Timing Parameters . . . . . . . . . . . . . . . . . . . . .584

Table 7-9. IDE Register, PIO, and Multiword DMA Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . .585

Table 7-10. IDE UltraDMA Data Out Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587

Table 7-11. IDE UltraDMA Data In Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588

Table 7-12. Flash Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .589

Table 7-13. USB Power Control Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590

Table 7-14. USB Option and Phy Control Signal Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .590

Table 7-15. SMB Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .591

Table 7-16. AC97 Codec Tim in g Par ame te rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592

Table 7-17. LPC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593

Table 7-18. Power Managemen t an d Proce s sor Control Timing Parameters . . . . . . . . . . . . . . . . . . . . .594

Table 7-19. Miscellaneous Signals Except UART Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .595

12 AMD Geode™ CS5536 Companion Device Data Book

List of Tables

33238G

Table 7-20. UART Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .596

Table 7-21. GPIO Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597

Table 7-22. MFGPT Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598

Table 7-23. JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .599

Table 7-24. RESET_STAND# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601

Table 7-25 . VCORE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602

Table 7-26 . VIO_VSB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603

Table 7-27. LVD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

Table 7-28. Skip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605

Table A-1. Valid OPN Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609

Table A-2. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

Table A-3. Edits to Current Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

AMD Geode™ CS5536 Companion Device Data Book 13

Overview 33238G

1.0Overview

1.1 General Description

The AMD Geode™ CS5536 companion device is designed

to work with an integrated processor North Bridge compo-

nent such as the AMD Geode™ LX processor. Together,

the AMD Geode LX processor and CS5536 companion

device provide a system-level solution well suited for the

high-performance and low-power needs of a host of

embedded devices including digital set-top boxes, mobile

computing devices, thin client applications, and single

board computers.

The internal architecture uses a single, high-performance

modular structure based on GeodeLink™ architecture.

This architecture yields high internal speed (over 4 GB/s)

data movement and extremely versatile internal power

management. The GeodeLink architecture is transparent to

application software. Communication with the processor is

over a 33/66 MHz PCI bus.

The CS5536 incorporates many I/O functions, including

some found in typical superI/O chips, simplifying many sys-

tem designs. Since the graphics subsystem is entirely con-

tained in the AMD Geode LX processor, system

interconnect is simplified. The device contains state-of-the-

art power management that enables systems, especially

battery powered systems, to significantly reduce power

consumption.

Audio is supported by an internal controller, designed to

connect to multiple AC97 compatible codecs. An IR (infra-

red) port supports all popular IR communication protocols.

The IR port is shared with one of two industry-standard

serial ports that can reach speeds of 115.2 kbps. An LPC

(Low Pin Count) port is provided to facilitate connections to

a superI/O should additional expansion, such as a floppy

drive, be necessary, and/or to an LPC ROM for the system

BIOS.

Figure 1-1. Block Diagram

GeodeLink™ Control

Processor (GLCP)

GeodeLink™ PCI

South Bridge

AMD Geode™ LX Processor Interface

PCI

Test/Reset

Interface

AC97 Controller

External

Audio

IDE Controller

USB OHC

USB EHC

33 or 66 MHz

Flash

Interface

82xx PC

Legacy

MFGP

Timers

RTC &

CMOS RAM

UART (2)

& IR (1)

SMB

Controller

LPC

Port

Power

Mgmnt

External I/O

External USB

Ports 1 & 2 & 3

GeodeLink™

Interface

Unit

External

IDE/Flash

GPIO

Diverse Integration Logic (DIVIL)

Diverse

Device (DD)

Low Voltage

Detect (LVD)

System Power

Voltages

Power Good

for Power On

Reset (POR)

(GLPCI_SB)

(GLIU)

(ACC)

(IDE)

External USB

Port 4 USB Device

14 AMD Geode™ CS5536 Companion Device Data Book

Overview

33238G

The hard disk controller is compatible to the ATA-6 specifi-

cation. The bus mastering IDE controller includes support

for two ATA-compliant devices on one channel. The

CS5536 companion device provides four Universal Serial

Bus (USB) 2.0 compliant ports, supporting low speed, full

speed, and high speed connections. All four ports are indi-

vidually automatically associated with either the Open Host

Controller Interface (OHCI) or the Enhanced Host Control-

ler Interface (EHCI) depending on the attached device

type. A battery-backed real-time clock (RTC) keeps track of

time and provides calendar functions.

A suite of 82xx devices provides the legacy PC functional-

ity required by most designs, including two PICs (Program-

mable Interrupt Controllers), one PIT (Programmable

Interval Timer) with three channels, and DMA (Direct Mem-

ory Access) functions. The CS5536 companion device con-

tains eight MFGPTs (Multi-Function General Purpose

Timers) that can be used for a variety of functions. A num-

ber of GPIOs (General Purpose Input/Outputs) are pro-

vided, and are assigned to system functions on power-up

(i.e., LPC port).

State-of-the-art power management features are attained

with the division of the device into two internal power

domains. The GPIOs and MFGPTs are distributed into

each domain allowing them to act as wakeup sources for

the device. The device provides full ACPI (Advanced Con-

figuration Power Interface) compliance and supports indus-

try-standard Wakeup and Sleep modes.

For implementation details and suggestions for this device,

see the supporting documentation (i.e., application notes,

schematics, etc.) on the AMD Embedded Developer Sup-

port Web site (http://www.amd.com/embedded/developer;

NDA required).

1.2 Features

General Features

■Designed for use with the AMD Geode LX processor

■208-Terminal PBGA (plastic ball grid array) package with

internal heatspreader

■3.3V I/O and 1.20V/1.25V/1.40V (nominal) Core opera-

tion

■Working and Standby power domains

■IEEE 1149.1 compliant TAP and boundary scan

■Commercial and industrial temperature ranges support

GeodeLink™ Interface Unit

■64-Bit, 66 MHz operation

■Transparent to applications software and BIOS due to

PCI VSM (virtual system module) implementation

■Non-blocking arbitration and routing of request and data

packets

■Programmable routing descriptors

■Programmable use and activity monitors that generate

optional ASMIs (asynchronous system management

interrupts) for legacy power management purposes

■Programmable SSMI (synchronous system manage-

ment interrupt) generators for selected range of

addresses

■IDE Controller, GLIU (GeodeLink Interface Unit), and

Diverse Device are the only SSMI sources

GeodeLink™ PCI Bridge (South Bridge)

■Provides a PCI interface for GeodeLink Devices:

— PCI specification v2.2 compliant

— 32-Bit, 33/66 MHz operation

— Transaction FIFOs (First In/First Out)

— Bus master or slave

— Converts selected PCI configuration bus cycles to

internal MSR (Model Specific Register) cycles

— Capable of handling in-bound transactions immedi-

ately after reset - no setup

— Mapping of PCI virtual configuration space to MSR

space is done completely in

Virtual System Architecture (VSA) code

— Serialized processor control interface

GeodeLink™ Control Processor

■SUSP#/SUPA# handshake with power management

logic provides Sleep control of all GeodeLink Devices

IDE Controller

■100 MB/s IDE controller in UDMA-5 mode per the ATA-6

specification

■5V interface

■Legacy and Enhanced PIO (Programmable I/O),

MDMA (Multi DMA), and UDMA (Ultra DMA) modes

■One channel with two devices

■Multiplexed with Flash interface

Flash Interface

■Multiplexed with IDE interface

■Connects to array of industry standard NAND Flash

and/or NOR Flash

■NOR optional execute-in-place boot source

■NAND optional file system

■General purpose ISA bus slave-like devices supported

with configurable chip selects

■Hardware support for SmartMedia type ECC (Error

Correcting Code) calculation off loading software inten-

sive algorithm

AMD Geode™ CS5536 Companion Device Data Book 15

Overview 33238G

USB Controller

■Supports four ports

■USB 1.1 supported by one OHCI-based host controller

■USB 2.0 supported by one EHCI-based host controller

■USB port four can be configured as a USB 2.0 compliant

device

■Supports wakeup events

■Overcurrent and power control support

■GeodeLink master burst reads and writes

Audio Codec 97 (AC97) Controller

■AC97 specification v2.3 compliant interface to multiple

audio codecs: Serial In, Serial Out, Sync Out, Bit Clock

■Legacy “PC Beep” support

■Eight-channel buffered GeodeLink mastering interface

■ASMI and IRQ support

■Multiple codec support

■Surround sound support

Diverse Device

■82xx Legacy Devices:

— Two 8259A-equivalent PICs:

– Shadow registers allow reading of internal

registers

— One 8254-equivalent PIT

— Two 8237-equivalent DMA controllers:

– 8-bit DMA supported (only)

— Serial Ports 1 and 2:

– Port 1 is shared with an IR port

– 16550 and 16450 software compatible

– Shadow register support for write-only bit

monitoring

– UART data rates up to 115.2 kbps

■IR (Infrared) Communication Port:

— Shared with Serial Port 1

— 16550 and 16450 software compatible

— Shadow register support for write-only bit monitoring

— Consumer-IR (TV-Remote) mode

— Data rate up to 115.2 kbps (SIR)

— HP-SIR (same as SIR above)

— Selectable internal or external modulation/demodula-

tion (Sharp-IR)

— ASK-IR option of SHARP-IR

— DASK-IR option of SHARP-IR

— Consumer Remote Control supports RC-5, RC-6,

NEC, RCA, and RECS 80

■System Management Bus (SMB) Controller:

— Compatible with Intel System Management Bus,

Industry Standard Two-wire interface, and

ACCESS.bus

— Bus master and slave operation

■LPC (Low Pin Count) Port:

— Based on Intel LPC Interface specification v1.0

— Serial IRQ support

— Serial DMA support (8-bit only)

— Boot source typically off external LPC

— Supports firmware hub protocol

— External bus masters not supported

■General Purpose I/Os (GPIOs):

— Programmable: In, Out, I/O, Open-Drain, Pull-

Up/Down, and Invert

— Parallel bit read and write

— Individual bit access eliminates Read-Modify-Write

cycles

— Input Conditioning Functions (ICF):

– Input debounce/filter

– Input event counter

– Input edge detect

■Multi-Function General Purpose Timers (MFGPTs):

— Eight MFGPTs - two are multiplexed with GPIOs for

external usage

— Two MFGPTs are powered by Standby power and

can be used as wakeups

— Watchdog timer generates reset, IRQ, ASMI, or NMI

— Pulse Width Modulation (PWM)

— Pulse Density Modulation (PDM)

— Blink

■Real-Time Clock (RTC) with CMOS RAM:

— Battery backed-up century calendar in days, day of

the week, date of month, months, years and century,

with automatic leap-year adjustment

— Battery backed-up time of day in seconds, minutes,

and hours that allows a 12 or 24 hour format and

adjustments for daylight savings time

— Binary Coded Decimal (BCD) or binary format for

time keeping

— DS1287, MC146818, and PC87911 compatibility

— Selective lock mechanisms for the RTC RAM

— Real-time alarm

—V

BAT or VSTANDBY power sources with automatic

switching between them

— 242 bytes of battery-backed CMOS RAM in two

banks

16 AMD Geode™ CS5536 Companion Device Data Book

Overview

33238G

■Power Management Controller:

— ACPI (Advanced Configuration Power Interface)

specification v2.0 compliant timer and register set

— Supports APM (Advanced Power Management) and

Legacy PM

— PME (power management event) from GPIOs and/or

on-chip sources

— Working, Sleep, and Standby states

— Wakeup circuits powered by Standby power rails

while rest of component and system powered off

— Automatic clock-off gating reduces power to inactive

blocks

— Flexible power supply controls including On/Off and

Sleep button inputs

— Generic Sleep output controls

— ACPI-compliant four second fail-safe off

— Low-voltage detect function for battery-powered

applications

— Suspend/Acknowledge handshake with AMD Geode

LX processor

— System over-temperature support

— Low Voltage Detect (LVD) provides Power On Reset

(POR) as well as continuous voltage monitoring for

automatic system reset on a low voltage condition

AMD Geode™ CS5536 Companion Device Data Book 17

Architecture Overview 33238G

2.0Architecture Overview

The AMD Geode™ CS5536 companion device provides

interfaces for all the common peripherals of an embedded

device, plus offers expansion for additional needs, if

required. Featuring a 33/66 MHz PCI interface to the

AMD Geode™ LX processor, the AMD Geode CS5536

companion device is internally connected using the

GeodeLink™ packet architecture. This architecture sup-

ports multiple simultaneous transactions and is totally

transparent to all application software. GeodeLink architec-

ture related operations are managed via Model Specific

Registers (MSRs) that are detailed in Section 4.1.6

"Address Spaces and MSRs" on page 59.

As shown in Figure 1-1 on page 13, the CS5536 compan-

ion device is implemented with one GeodeLink Interface

Unit (GLIU) that connects to the:

•GeodeLink PCI South Bridge

•GeodeLink Control Processor

•IDE Controller (IDE Controller multiplexed with Flash

Interface)

•Universal Serial Bus Host Controller with Ports 1 to 4

•Universal Serial Bus Device Controller with Port 4

•Audio Codec 97 (AC97) Controller

•Diverse Device:

— Legacy DMA, Timer, and Interrupt (82xx PC Legacy)

— UARTs (2) and IR (1) Port (shared with UART1)

— System Management Bus (SMB) Controller

— Low Pin Count (LPC) Controller

— General Purpose I/O (GPIO) with Input Conditioning

Functions (ICF)

— Multi-Function General Purpose Timers (MFGPTs)

— Flash Interface (multiplexed with IDE interface)

— Real-Time Clock (RTC) with CMOS RAM

— Power Management Controller (PMC)

The Low Voltage Detect (LVD) circuit is not a GeodeLink

Device, but is connected to the Power Management Con-

troller for voltage monitoring support.

2.1 GeodeLink™ PCI South Bridge

The GeodeLink PCI South Bridge (GLPCI_SB) provides a

PCI interface for the CS5536 companion device. It acts as

a PCI master or slave in providing PCI transactions to and

from the CS5536 and the PCI bus. A special serial inter-

face to the AMD Geode LX processor, the CPU Interface

Serial (CIS), is provided that assists in the transfer of infor-

mation between the CS5536 and the processor.

The interface is compliant to PCI specification v2.2 and

may operate at up to 66 MHz. Optional bus signals PERR#,

SERR#, LOCK#, and CLKRUN are not implemented.

Within a PCI burst, zero wait state operation is achieved.

The PCI interface supports programmable IDSEL selec-

tion, and can handle inbound transactions immediately

after system reset.

2.2 GeodeLink™ Control Processor

The GeodeLink Control Processor (GLCP) is responsible

for debug support and monitors system clocks in support of

PMC operations.

The GLCP interfaces with a JTAG compatible Test Access

Port (TAP) Controller that is IEEE 1149.1 compliant. During

debug, it can be used to pass GeodeLink packets to/from

the GeodeLink Interface Unit (GLIU). It is also used to sup-

port manufacturing test.

18 AMD Geode™ CS5536 Companion Device Data Book

Architecture Overview

33238G

2.3 IDE Controller

The CS5536 companion device is compliant to the ATA-6

specification. The IDE interface supports one channel, that

in turn supports two devices that can operate in PIO modes

0 to 4, MDMA modes 0 to 2, or UDMA modes 0 to 5 (up to

100 MB/s).

This interface is shared with the Flash Interface, using the

same balls. The interface usage, immediately after reset, is

defined by the boot options selected. After reset, the inter-

face may be dynamically altered using DIVIL_BALL_OPT

(DIVIL MSR 51400015h) (see Table 3-7 on page 40 for

details on multiplexing).

The IDE interface provides a variety of features to optimize

system performance, including 32-bit disk access, post

write buffers, bus master, MDMA, look-ahead read buffer,

and prefetch mechanism.

The IDE interface timing is completely programmable. Tim-

ing control covers the command active and recover pulse

widths, and command block register accesses. The IDE

data transfer speed for each device on each channel can

be independently programmed allowing high speed IDE

peripherals to co-exist on the same channel as older, com-

patible devices.

The IDE controller also provides a software accessible

buffered reset signal to the IDE drive. The IDE_RESET#

signal is driven low during reset to the CS5536 companion

device and can be driven low or high as needed for device

power off conditions.

2.4 Universal Serial Bus Controllers

The AMD Geode CS5536 companion device provides four

USB 2.0 compliant ports that support low speed, full speed

and high speed connections. All four ports are individually

automatically associated with either the Open Host Con-

troller Interface or the Enhanced Host Controller Interface

depending on the attached device type.

Port 4 can be configured as a USB 2.0 high speed or full

speed device. This device supports one control endpoint

(EP0) and four further endpoints (EP1-EP4). These end-

points can be configured according to their direction, and

support either control, bulk, or interrupt traffic.

There are two power control lines. Each port can be asso-

ciated individually to one of them.

There is a common overcurrent sense line for all four ports.

The ports can be enabled individually to react on an over-

current event.

2.5 Audio Codec 97 (AC97) Controller

The audio subsection of the CS5536 companion device

consists of three 32-bit stereo-buffered bus masters (two

for output, one for input) and five 16-bit mono-buffered bus

masters (three for output, two for input), whose function is

to transport audio data between system memory and exter-

nal AC97 codecs.

This arrangement is capable of producing multi-channel

5.1 surround sound (left, center, right, left rear, right rear,

and low frequency effects).

The codec interface is AC97 v2.3 compliant and contains

Serial In (x2), Serial Out, Sync Out, and Bit Clock, allowing

support for any AC97 codec with Sample Rate Conversion

(SRC). Additionally, the interface supports the industry-

standard 16-bit pulse code modulated (PCM) format.

2.6 Diverse Device

A suite of 82xx devices provide all the legacy PC function-

ality required by most designs, including two programmable

interrupt controllers (PICs), one Programmable Interval

Timer (PIT) with three channels, and Direct Memory

Access (DMA) functions. The CS5536 companion device

contains eight Multi-Function General Purpose Timers

(MFGPTs) that can be used for a variety of functions. A

number of GPIOs are provided, and are assigned to sys-

tem functions on power-up (i.e., LPC port). Each of these

may be reassigned and given different I/O characteristics

such as debounce, edge-triggering, etc.

The Diverse Integration Logic (DIVIL) holds the devices

together and provides overall control and management via

MSRs.

2.6.1 Legacy DMA Controller

The CS5536 companion device DMA controller consists of

two cascaded 8237-type DMA controllers that together

support four 8-bit channels. The DMA controller is used to

provide high speed transfers between internal chip

sources. It has full 32-bit address range support via high-

page registers. An internal mapper allows routing of any of

seven internal DMA sources to the four 8-bit DMA chan-

nels.

2.6.2 Programmable Interval Timer,

Legacy Timer

The Programmable Interval Timer (PIT) generates pro-

grammable time intervals from the divided clock of an

external clock input. The PIT is an 8254-style timer that

contains three 16-bit independently programmable

counters. A 14.318 MHz external clock signal (from a crys-

tal oscillator or a clock chip) is divided by 12 to generate

1.19 MHz for the clocking reference of all three counters.

AMD Geode™ CS5536 Companion Device Data Book 19

Architecture Overview 33238G

2.6.3 Programmable Interrupt Controller,

Legacy Interrupt

The Programmable Interrupt Controller (PIC) consists of

two 8259A-compatible programmable interrupt controllers

connected in cascade mode through interrupt number two.

Request mask capability and edge-level controls are pro-

vided for each of the 15 channels along with a 15-level pri-

ority controller.

An IRQ mapper takes up to 62 discrete interrupt request

(IRQ) inputs and maps or masks them to the 15 PIC inputs

and to one ASMI (asynchronous system management

interrupt). All 62 inputs are individually maskable and sta-

tus readable.

In addition to the above 8259A features, there are shadow

registers to obtain the values of legacy 8259A registers that

have not been historically readable.

2.6.4 Keyboard Emulation Logic,

Legacy Support Interface

The PS2 Keyboard Emulation Logic (KEL) provides a vir-

tual 8042 keyboard controller interface that may be used to

map non-legacy keyboard and mouse sources to this tradi-

tional interface. Flexible keyboard emulation logic allows

PS2 keyboard emulation traditionally used for USB legacy

keyboard emulation. For example, USB sources may be

‘connected’ to this interface via SMM (System Manage-

ment Mode) software. It also allows mixed environments

with one LPC legacy device and one USB device.

2.6.5 Universal Asynchronous Receiver

Transmitter and IR Port

Two Universal Asynchronous Receiver Transmitters

(UARTs) provide a system interface to the industry stan-

dard serial interface consisting of the basic transmit and

receive signals. One of the UARTs can be coupled with

infrared logic and be connected to an infrared sensor.

The UARTs are both 16550 and 16450 software-compati-

ble and contain shadow register support for write-only bit

monitoring. The ports have data rates up to 115.2 kbps.

Serial Port 1 can be configured as an infrared communica-

tions port that supports Sharp-IR, Consumer-IR, and HP-

SIR as well as many popular consumer remote-control pro-

tocols.

2.6.6 System Management Bus Controller

The System Management Bus (SMB) Controller provides a

system interface to the industry standard SMB. The SMB

allows easy interfacing to a wide range of low-cost memory

and I/O devices, including: EEPROMs, SRAMs, timers,

ADC, DAC, clock chips, and peripheral drivers. These lines

are shared with two GPIOs and must be configured as

SMB ports in order for this interface to be functional.

The SMB is a two-wire synchronous serial interface com-

patible with the System Management Bus physical layer.

The SMB Controller can be configured as a bus master or

slave, and can maintain bidirectional communication with

both multiple master and slave devices. As a slave device,

the SMB Controller may issue a request to become the bus

master.

2.6.7 Low Pin Count Port

This port provides a system interface to the industry stan-

dard Low Pin Count (LPC) bus. The controller can convert

an internal Local bus memory or I/O cycle to an external

LPC cycle. It receives serial IRQs from the LPC and con-

verts them to parallel form so they can be routed to the IRQ

mapper. Lastly, it interacts with Legacy DMA logic to per-

form DMA between on-chip or off-chip DMA devices.

The LPC interface is based on Intel’s Low Pin Count (LPC)

Interface specification v1.0. In addition to the required sig-

nals/pins specified in the Intel specification, it also supports

two optional signals:

•LPC_DRQ# - LPC DMA Request

•LPC_SERIRQ - LPC Serial encoded IRQ

The LPC interface supports memory, I/O, DMA, and Intel’s

firmware hub interfaces.

2.6.8 General Purpose I/Os with Input

Conditioning Functions (ICF)

There are 32 GPIOs in the CS5536 companion device, 28

are externally available, offering a variety of user-selectable

configurations including accessing auxiliary functions

within the chip, and input conditioning such as debounce

and edge detect. Register access is configured in such a

way as to avoid Read-Modify-Write operations; each GPIO

may be directly and independently configured.

Several groups of GPIOs are multiplexed between the LPC

Controller, the SMB Controller, access to the UARTs and

MFGPTs, and power management controls including sys-

tem power and Sleep buttons. Six of the GPIOs are in the

Standby power domain, giving them increased versatility as

wakeup event sources when only Standby power is

applied.

A GPIO interrupt and power management event (PME)

mapper can map any subset of GPIOs to the PICs (eight

interrupts available) or power management controller (eight

events available).

Versatile input filtering is available for each GPIO input.

Each preliminary input is optionally connected to a digital

filter circuit that is optionally followed by an event counter.

Lastly followed by an edge detector that together provide

eight different ICFs (input conditioning functions), plus an

auto-sense feature for determining the initial condition of

the pin.

20 AMD Geode™ CS5536 Companion Device Data Book

Architecture Overview

33238G

2.6.9 Multi-Function General Purpose Timers

This device contains eight Multi-Function General Purpose

Timers (MFGPTs), six are in the normal VDD Working

power domain, while the other two are in the Standby

power domain. The timers are very versatile and can be

configured to provide a Watchdog timer (trigger GPIO out-

put, interrupt or reset), perform Pulse Width Modulation

(PWM) or Pulse Density Modulation (PDM), create Blink

(low frequency pulse for LED), generate GPIO outputs, or

act as general purpose timers.

Each MFGPT operates independently and has the follow-

ing features:

•32 KHz or 14.318 MHz clock selectable by software

(applies to MFGPT0 to MFGPT5, in Working power

domain, only).

•MFGPT6 and MFGPT7, in Standby power domain, use

32 KHz clock.

•Programmable input clock prescaler divisor to divide

input clock by 2i, where i = 0 to 15.

•Provide outputs for generating reset (limited to MFGPT0

to MFGPT5), IRQs, NMI, and ASMIs (indirectly through

PICs).

2.6.10 Flash Interface

The CS5536 companion device has a Flash Interface that

supports popular NOR Flash and inexpensive NAND Flash

devices. This interface is shared with the IDE interface (IDE

Controller), using the same balls. NOR or NAND Flash may

co-exist with IDE devices using PIO (Programmed I/O)

mode. The 8-bit interface supports up to four “lanes” of

byte-wide Flash devices through use of four independent

chip selects, and allows for booting from the array. Hard-

ware support is present for SmartMedia-type ECC (Error

Correction Code) calculations, off-loading software from

having to support this task.

All four independent chip selects may be used as general

purpose chip selects to support other ISA-like slave

devices. Up to 1 KB of address space (without external

latches) may be supported using these signals.

2.6.11 Real-Time Clock with CMOS RAM

The CS5536 companion device maintains a real-time clock

for system use. The clock is powered by an external battery

and so continues to keep accurate time even when system

power is removed. The clock can be set to make automatic

Daylight Savings Time changes in the spring and fall with-

out user intervention. There are separate registers for sec-

onds, minutes, hours, days (both day of the week and day

of the month), months, and years. Alarms can be set for

any time within the range of these registers, which have a

100-year capability. The clock uses an external 32 KHz

oscillator or crystal as the timing element.

The same battery that keeps the clock continuously pow-

ered also provides power to a block of 242 bytes of CMOS

RAM, used for storing non-volatile system parameters.

2.6.12 Power Management Controller

The CS5536 companion device has state-of-the-art power

management capabilities designed into every module.

Independent clock controls automatically turn clocks off to

sections of the chip that are not being used, saving consid-

erable power. In addition, the chip supports full Sleep and

Wakeup states with multiple methods of inducement. A

suite of external signals supports power management of

devices on the system board. Legacy Power Management

(PM), Advanced Power Management (APM), and

Advanced Configuration and Power Interface (ACPI) tech-

niques and requirements are supported. The GPIO device

can be configured to transmit any of several wakeup events

into the system.

The CS5536 companion device is divided into two main

power domains: Working and Standby, plus circuits such as

the real-time clock and CMOS RAM that are battery-

backed. Most of the CS5536 is in the Working power

domain, except for GPIO[31:24] and MFGPT[7:6]. This

allows these signals to be used for wakeup events or out-

put controls.

2.7 GeodeLink™ Interface Unit

The GeodeLink Interface Unit (GLIU) makes up the internal

bus derived from the GeodeLink architecture. It has eight

ports, one of which is dedicated to itself, leaving seven for

use by internal GeodeLink Devices. Figure 1-1 on page 13

shows this device as the central element of the architec-

ture, though its presence is basically transparent to the end

user.

2.8 Low Voltage Detect

The Low Voltage Detect (LVD) circuit monitors Standby I/O

voltage, Standby Core voltage, and Working Core voltage.

Working I/O voltage is not monitored and is assumed to

track with Working Core voltage. The LVD monitors these

voltages to provide Working and Standby power-good sig-

nals (resets) for the respective working and standby power

domains. Additionally, the PMC monitors the working

power-good signal to shut-down and/or re-start the system

as appropriate.

AMD Geode™ CS5536 Companion Device Data Book 21

Architecture Overview 33238G

2.9 Processor Support

As previously stated, the AMD Geode CS5536 companion

device is designed to interface with the AMD Geode LX

processor. Figure 2-1 and Figure 2-2 on page 22 show typ-

ical block diagrams for mobile and single board computing

systems based on the AMD Geode LX processor and

CS5536 companion device.

Figure 2-1. Mobile Computing System Block Diagram

USB

Port 2

USB

Port 0

AMD Geode™

LX Processor

AMD Geode™

CS5536

PCI1211

TPS2211

Cardbus

Socket

PADCar d

Connector

CPLD

SDRAM

SODIMM

Optional

Cardbus Controller

PCI

LPC Bus

LPC

XpressROM

Compact

Flash IDE

LVDS TFT LCD

DSTN LCD

Microcontroller

2-Wire UART I/F

AC97

Audio Amp

Mic In

Internal

Mic Touchscreen

Interface

Headphone

USB Power Switch

USB

Port 1 USB

Port 3

Power Section AC

Cube Charger LiIon

Battery

Two-Phase Sync.

Triple Regulator

Controller

5V/3.3V

AC Adapter or Battery Power

Clock

Generator

for all clocks

Companion

Device

Regulator

Codec

and Overcurrent Protection

EHCI/OHCI

Controller

22 AMD Geode™ CS5536 Companion Device Data Book

Architecture Overview

33238G

Figure 2-2. Single Board Computing System Block Diagram

SDRAM

Ethernet

Compact

Flash

AMD Geode™

LX Processor

AMD Geode™

CS5536 AC97

Clocks

CRT

DSTN or

TFT

Headphones

Server Memory Bus

2-Wire I/F

PCI Bus

RGB Out

Digital RGB

LPC Bus

IDE

USB

4 Ports

DC to DC

VCC3V

VCCCore

VCC5V

Companion

Device Amp

Codec

Regulator

Controller

Flash/ROM

USB Power Switch

and Overcurrent Protection

EHCI/OHCI

Controller

AMD Geode™ CS5536 Companion Device Data Book 23

Signal Definitions 33238G

3.0Signal Definitions

This section defines the signals and describes the external

interface of the AMD Geode™ CS5536 companion device.

Signal multiplexing has been utilized to a high degree. For

example, the IDE and Flash interfaces are multiplexed on

the same balls. Configuration depends on the boot options

selected (see Table 3-5 "Boot Options Selection" on page

34). If Flash is selected, the user has the option of using

NOR and/or NAND Flash devices.

The GPIOs are configurable (e.g., any GPIO input can be

mapped to an interrupt, ASMI, or PME). Figure 3-1 shows

the signals organized in typical functional groups - not all

possible multiplexing is shown.

Where signals are multiplexed, the primary signal name is

listed first and is separated by a plus sign (+). A slash (/) in

a signal name means that the function is always enabled

and available (i.e., time multiplexed).

Figure 3-1. Typical Signal Groups

MHZ66_CLK

RESET_WORK#

RESET_STAND#

MHZ48_CLK

KHZ32_XCI

KHZ32_XCO

MHZ14_CLK

System

Interface

Signals

AD[31:0]

C/BE[3:0]#

PAR

FRAME#

DEVSEL#

IRDY#

TRDY#

STOP#

REQ#

GNT#

PCI

Interface

Signals

USB_PWR_EN1

USB_PWR_EN2

USB_OC_SENS#

USB1_DATPOS

USB1_DATNEG

USB2_DATPOS

USB2_DATNEG

USB3_DATPOS

USB3_DATNEG

USB4_DATPOS

USB4_DATNEG

USB

Interface

AC_S_OUT+BOS1

AC_S_IN

AC_S_SYNC+BOS0

LPC

Interface

Signals

RESET_OUT#

WORKING

SUSP#/CIS

SUSPA#

IRQ13

VBAT

LVD_EN#

PCI_CLK

VSSIO_USB[4:0]

VIO_USB[3:0]

LPC_CLK

LPC_AD[3:0]+GPIO[19:16]

LPC_DRQ#+GPIO20

LPC_SERIRQ+GPIO21+MFGPT2_RS

LPC_FRAME#+GPIO22

Signals

Audio

Codec 97

Interface

Signals

Note: Bold-italicized signal names in parenthesis denote a “recommended” use for a specific GPIO.

See Table 3-8 "GPIO Options" on page 47 for additional details.

AC_CLK

AMD Geode™

CS5536

(Continued on next page)

Companion

Device

MHZ48_XCI

MHZ48_XCO

USB_REXT

VCORE_USB[1:0]

MHZ48_XCEN

USB_VBUS

24 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

Figure 3-1. Typical Signal Groups (Continued)

IDE_CS0#+FLASH_CS0#+CE0#

IDE_CS1#+FLASH_CS1#+CE1#

IDE_IOR0#+FLASH_RE#

IDE_IOW0#+FLASH_WE#

IDE_AD0+FLASH_AD25/AD[0]+CLE

IDE_RDY0+FLASH_IOCHRDY+RDY/BUSY#

IDE_DREQ0+FLASH_CS2#+CE2#

IDE_DACK0#+FLASH_CS3#+CE3#

GPIO2+IDE_IRQ0

IDE/Flash

Signals

IDE_DATA[7:0]+FLASH_AD[17:10]/IO[7:0]

GPIO14+SMB_CLK

GPIO15+SMB_DATA

GPIO1+AC_BEEP_MFGPT0_C2

IDE_AD[2:1]+FLASH_AD[27:26]/AD[2:1]

IDE_DATA[14:8]+FLASH_AD[24:18]/AD[9:3]

IDE_DATA15+FLASH_ALE

Interface

GPIO10+THRM_ALRM#

IDE_RESET#

GPIO11+SLP_CLK_EN#+MFGPT1_C2

GPIO24+WORK_AUX

GPIO25+LOW_BAT#+MFGPT7_C2

GPIO28+PWR_BUT#

GPIO0 (PCI_INTA#)

GPIO3+UART2_RX (DDC_SCL)

GPIO4+UART2_TX (DDC_SDA)

GPIO5+MFGPT1_RS+MFGPT0_C1

GPIO6+MFGPT0_RS+MFGPT1_C1+MFGPT2_C2

GPIO7+MFGPT2_C1+SLEEP_X (PCI_INTB#)

GPIO8+UART1_TX+UART1_IR_TX

GPIO9+UART1_RX+UART1_IR_RX

GPIO26+MFGPT7_RS (PME#)

GPIO27+MFGPT7_C1+32KHZ

GPIOs and

“Recommended”

Usage

TCK

TMS

TDI

TDO

T_DEBUG_IN

T_DEBUG_OUT

LVD_TEST

TEST_MODE

FUNC_TEST

VCORE [Total of 6]

VCORE_VSB [Total of 1]

VIO [Total of 10]

VIO_VSB [Total of 1]

VSS [Total of 13]

NC [Total of 20]

Debug and

Interface Signals

Manufacturing

Power,

Ground,

and

No Connects

GPIO12+AC_S_IN2+SLEEP_Y

GPIO13+SLEEP_BUT

AMD Geode™

CS5536

Companion

Device

USB_PTEST

Note: Bold-italicized signal names in parenthesis denote a “recommended” use for a specific GPIO.

See Table 3-8 "GPIO Options" on page 47 for additional details.

AMD Geode™ CS5536 Companion Device Data Book 25

Signal Definitions 33238G

3.1 Ball Assignments

As illustrated in Figure 3-1 on page 23, the CS5536 com-

panion device is configurable. Boot options and register

programming are used to set various modes of operation

and specific signals on specific balls.

This section describes the ball assignments and interface

options:

•Figure 3-2 "208-PBGA Ball Assignment Diagram" on

page 26:

— Top view looking through package.

•Table 3-2 "Ball Assignments: Sorted by Ball Number" on

page 27:

— Primary signal name is listed first.

— Includes a column labeled Buffer Type. See Section

3.1.1 "Buffer Types" on page 33 for details.

— Includes a column labeled Configuration with refer-

ences to:

– BOS[1:0] - See Section 3.1.2 "Boot Options" on

page 34.

– Ball Opt MSR - See Section 3.1.3 "Ball Options"

on page 34.

– IN_AUX1, OUT_AUX1, and OUT_AUX2 - See

Section 3.2.8 "GPIOs" on page 47.

•Table 3-3 "Ball Assignments: Sorted Alphabetically by

Signal Name" on page 31:

— Quick-reference list, sorted alphabetically with

primary signal listed first.

The tables in this section use several abbreviations. Table

3-1 lists the mnemonics and their meanings.

Table 3-1. Abbreviations/Definitions

Mnemonic Definition

A Analog

GND Ground

I Input

I/O Bidirectional

O Output

OD Open-drain

Ball Opt MSR Model Specific Register Ball Options: A register used to configure balls with multiple functions. Refer

to Section 3.1.3 "Ball Options" on page 34 for further details.

PD Pull-down resistor

PWR Power

PU Pull-up resistor

TS TRI-STATE

VCORE Core Power Working Connection

VCORE_USB USB Core Power Connection

VCORE_VSB Core Power Standby Connection

VIO I/O Power Working Connection

VIO_USB USB I/O Power Connection

VIO_VSB I/O Power Standby Connection

VSS Ground

# The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted

when at a high voltage level.

/ A “/” in a signal name indicates the function is always enabled (i.e., time multiplexed - available when

needed).

+ A “+” in a signal name indicates the function is available on the ball, but that either strapping options or

26 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

Figure 3-2. 208-PBGA Ball Assignment Diagram

1234567891011121314 1615 17

GPIO11 NC VBAT KHZ32I RST# TSTM VCORE_VSB GPIO28 GPIO25 MHZ66 IDE_A0 IDE_A1 IDE_RDY IDE_DQ# NCIDE_D1 IDE_D12

NC NC KHZ32O NC NC VIO_VSB GPIO26 RSTSD# LVDTST IDE_CS0# IDE_A2 GPIO2 IDE_IOR# IDE_D0 IDE_D13IDE_D14 IDE_D4

MHZ14 GPIO7 GPIO10 NC WRKG RSTWRK# LVDEN# GPIO27 GPIO24 IDE_CS1# NC IDE_DK0# IDE_IOW# IDE_D15 IDE_D3IDE_D2 IDE_D11

GPIO9 GPIO6 GPIO5 VIO VSS VIO VSS VCORE VIO VCORE VSS VIO VSS VIO_USB3 IDE_D10IDE_D5 IDE_D9

GPIO3 GPIO4 GPIO8 VSS VSSIO_USB3 IDE_D7IDE_D6 IDE_D8

GPIO15 GPIO13 FTST VIO VIO_USB2 NCIDE_RST# MHZ48_EN

LPC_DQ# LPC_SQ GPIO14 VSS VSSIO_USB2 U4_DNU_PTST U4_DP

LCP_CLK LPC_A0 LPC_FRM# VCORE VCORE_USB0 U3_DNMHZ48_I U3_DP

LPC_A2 LPC_A1 GPIO12 VSS VSSIO_USB1 NCMHZ48_O NC

LPC_A3 IRQ13 GPIO1 VCORE VCORE_USB1 USB1_DPUSB_RXT USB1_DN

AC_SIN AC_SOUT AC_SSYNC VSS VSSIO_USB0 USB2_DPNC USB2_DN

AC_CLK DBUGI DBUGO VIO VIO_USB1 NCUSB_V NC

SUSPA# TCK TMS VSS VSSIO_USB4 USB_PW2USB_OC# MHZ48_C

TDI TDO SUSP# VIO VSS VIO VSS VCORE VIO VCORE VSS VIO VSS VIO_USB0 AD4AD7 USB_PW1

GNT# GPIO0 NC AD28 AD26 C/BE3# AD21 AD18 NC IRDY# DEVSEL# AD15 AD12 AD9 AD2AD6 AD0

REQ# NC AD30 AD27 AD25 AD23 AD20 AD17 C/BE2# TRDY# STOP# AD14 AD11 AD8 AD3AD5 AD1

AD31 NC AD29 PCI_CLK AD24 AD22 AD19 AD16 FRAME# PAR C/BE1# AD13 AD10 C/BE0# NCNC NC

1234567891011121314 1615 17

Note: Signal names have been abbreviated in this figure due to space constraints.

= GND terminal

= PWR terminal

= Multiplexed signal

B = BOS (Boot Option Select)

(Top View - Looking Through Package)

AMD Geode™

CS5536

Companion

Device

AMD Geode™ CS5536 Companion Device Data Book 27

Signal Definitions 33238G

Table 3-2. Ball Assignments: Sorted by Ball Number

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

A1 GPIO11 I/O GP24

SLP_CLK_EN# O OUT_AUX1

MFGPT1_C2 O OUT_AUX2

A2 NC --- ---

A3 VBAT Wire Bare_Wire_

A4 KHZ32_XCI Wire Bare_Wire

A5 RESET_OUT# O GP24

A6 TEST_MODE Wire Bare_Wire

A7 VCORE_VSB PWR ---

A8 GPIO28 I/O GP24

PWR_BUT# I IN_AUX1

A9 GPIO25 I/O GP24

LOW_BAT# I IN_AUX1

MFGPT7_C2 O OUT_AUX2

A10 MHZ66_CLK I GP24

A11 IDE_AD0 O IDE BOS[1:0] = 00

or 11

FLASH_AD25/AD0 O BOS[1:0] = 10

FLASH_CLE O

A12 IDE_AD1 O IDE BOS[1:0] = 00

or 11

FLASH_AD26/AD1 O BOS[1:0] = 10

A13 IDE_RDY0 I IDE BOS[1:0] = 00

or 11

FLASH_IOCHRDY I BOS[1:0] = 10

FLASH_RDY/BUSY# I

A14 IDE_DREQ0 I IDE BOS[1:0] = 00

or 11

FLASH_CS2# O BOS[1:0] = 10

FLASH_CE2# O

A15 IDE_DATA1 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD11/IO1 I/O BOS[1:0] = 10

A16 NC --- ---

A17 IDE_DATA12 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD22/AD7 O BOS[1:0] = 10

B1 NC --- ---

B2 NC --- ---

B3 KHZ32_XCO Wire Bare_Wire

B4 NC --- ---

B5 NC --- ---

B6 VIO_VSB PWR ---

B7 GPIO26 I/O GP24

MFGPT7_RS I IN_AUX1

B8 RESET_STAND# I Bare_Wire

B9 LVD_TEST Wire (O) Bare_Wire

B10 IDE_CS0# O IDE BOS[1:0] = 00

or 11

FLASH_CS0# O BOS[1:0] = 10

FLASH_CE0# O

B11 IDE_AD2 O IDE BOS[1:0] = 00

or 11

FLASH_AD27/AD2 O BOS[1:0] = 10

B12 GPIO2 I/O IDE

IDE_IRQ0 I IN_AUX1

B13 IDE_IOR0# O IDE BOS[1:0] = 00

or 11

FLASH_RE# O BOS[1:0] = 10

B14 IDE_DATA0 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD10/IO0 I/O BOS[1:0] = 10

B15 IDE_DATA14 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD24/AD9 O BOS[1:0] = 10

B16 IDE_DATA13 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD23/AD8 O BOS[1:0] = 10

B17 IDE_DATA4 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD14/IO4 I/O BOS[1:0] = 10

C1 MHZ14_CLK I GP24

C2 GPIO7 I/O PCI

MFGPT2_C1 O OUT_AUX1

SLEEP_X O OUT_AUX2

C3 GPIO10 I/O GP24

THRM_ALRM# I IN_AUX1

C4 NC --- ---

C5 WORKING O SMB

C6 RESET_WORK# I GP24

C7 LVD_EN# Wire Bare_Wire

C8 GPIO27 I/O GP24

MFGPT7_C1 O OUT_AUX1

32KHZ O OUT_AUX2

C9 GPIO24 I/O SMB

WORK_AUX O OUT_AUX1

C10 IDE_CS1# O IDE BOS[1:0] = 00

or 11

FLASH_CS1# O BOS[1:0] = 10

FLASH_CE1# O

C11 NC --- ---

C12 IDE_DACK0# O IDE BOS[1:0] = 00

or 11

FLASH_CS3# O BOS[1:0] = 10

FLASH_CE3# O

C13 IDE_IOW0# O IDE BOS[1:0] = 00

or 11

FLASH_WE# O BOS[1:0] = 10

C14 IDE_DATA15 I/O IDE BOS[1:0] = 00

or 11

FLASH_ALE O BOS[1:0] = 10

C15 IDE_DATA2 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD12/IO2 I/O BOS[1:0] = 10

C16 IDE_DATA3 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD13/IO3 I/O BOS[1:0] = 10

C17 IDE_DATA11 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD21/AD6 O BOS[1:0] = 10

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

28 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

D1 GPIO9 I/O GP24

UART1_RX I IN_AUX1

UART1_IR_RX I

D2 GPIO6 I/O GP24

MFGPT0_RS I IN_AUX1

MFGPT1_C1 O OUT_AUX1

MFGPT2_C2 O OUT_AUX2

D3 GPIO5 I/O GP24

MFGPT1_RS I IN_AUX1

MFGPT0_C1 O OUT_AUX1

D4 VIO PWR ---

D5 VSS GND ---

D6 VIO PWR ---

D7 VSS GND ---

D8 VCORE PWR ---

D9 VIO PWR ---

D10 VCORE PWR ---

D11 VSS GND ---

D12 VIO PWR ---

D13 VSS GND ---

D14 VIO_USB3 PWR ---

D15 IDE_DATA5 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD15/IO5 I/O BOS[1:0] = 10

D16 IDE_DATA10 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD20/AD5 O BOS[1:0] = 10

D17 IDE_DATA9 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD19/AD4 O BOS[1:0] = 10

E1 GPIO3 I/O SMB

UART2_RX I IN_AUX1

E2 GPIO4 I/O SMB

UART2_TX O OUT_AUX1

E3 GPIO8 I/O GP24

UART1_TX O OUT_AUX1

UART1_IR_TX O OUT_AUX2

E4 VSS GND ---

E14 VSSIO_USB3 GND ---

E15 IDE_DATA6 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD16/IO6 I/O BOS[1:0] = 10

E16 IDE_DATA7 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD17/IO7 I/O BOS[1:0] = 10

E17 IDE_DATA8 I/O IDE BOS[1:0] = 00

or 11

FLASH_AD18/AD3 O BOS[1:0] = 10

F1 GPIO15 I/O SMB

SMB_DATA I/O IN_AUX1 and

OUT_AUX1

F2 GPIO13 I/O GP24

SLEEP_BUT I IN_AUX1

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

F3 FUNC_TEST I SMB

F4 VIO PWR ---

F14 VIO_USB2 PWR ---

F15 IDE_RESET# O IDE

F16 NC --- ---

F17 MHZ48_XCEN I GP24

G1 LPC_DRQ# I PCI Ball Opt MSR

[6,4] = 1,1

GPIO20 I/O Ball Opt MSR

[6] = 0

G2 LPC_SERIRQ I/O PCI Ball Opt MSR

[6,5] = 1,1

GPIO21 I/O Ball Opt MSR

[6] = 0

MFGPT2_RS I IN_AUX1

G3 GPIO14 I/O SMB

SMB_CLK I/O IN_AUX1 and

OUT_AUX1

G4 VSS GND ---

G14 VSSIO_USB2 GND ---

G15 USB_PTEST Wire Bare_Wire

G16 USB4_DATNEG I/O USB

G17 USB4_DATPOS I/O USB

H1 LPC_CLK I GP24

H2 LPC_AD0 I/O PCI Ball Opt MSR

[6] = 1

GPIO16 I/O Ball Opt MSR

[6] = 0

H3 LPC_FRAME# O PCI Ball Opt MSR

[6] = 1

GPIO22 I/O Ball Opt MSR

[6] = 0

H4 VCORE PWR ---

H14 VCORE_USB0 PWR ---

H15 MHZ48_XCI Wire Bare_Wire

H16 USB3_DATNEG I/O USB

H17 USB3_DATPOS I/O USB

J1 LPC_AD2 I/O PCI Ball Opt MSR

[6] = 1

GPIO18 I/O Ball Opt MSR

[6] = 0

J2 LPC_AD1 I/O PCI Ball Opt MSR

[6] = 1

GPIO17 I/O Ball Opt MSR

[6] = 0

J3 GPIO12 I/O GP24

AC_S_IN2 I IN_AUX1

SLEEP_Y O OUT_AUX2

J4 VSS GND ---

J14 VSSIO_USB1 GND ---

J15 MHZ48_XCO Wire Bare_Wire

J16 NC --- ---

J17 NC --- ---

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

Table 3-2. Ball Assignments: Sorted by Ball Number (Continued)

AMD Geode™ CS5536 Companion Device Data Book 29

Signal Definitions 33238G

K1 LPC_AD3 I/O PCI Ball Opt MSR

[6] = 1

GPIO19 I/O Ball Opt MSR

[6] = 0

K2 IRQ13 I GP24

K3 GPIO1 I/O GP24 Default

AC_BEEP O OUT_AUX1

MFGPT0_C2 O OUT_AUX2

K4 VCORE PWR ---

K14 VCORE_USB1 PWR ---

K15 USB_REXT Wire Bare_wire

K16 USB1_DATPOS I/O USB

K17 USB1_DATNEG I/O USB

L1 AC_S_IN I GP24

L2 AC_S_OUT O GP24

BOS1 I

L3 AC_S_SYNC O GP24

BOS0 I

L4 VSS GND ---

L14 VSSIO_USB0 GND ---

L15 NC --- ---

L16 USB2_DATPOS I/O USB

L17 USB2_DATNEG I/O USB

M1 AC_CLK I GP24

M2 T_DEBUG_IN I GP24

M3 T_DEBUG_OUT O GP24

M4 VIO PWR ---

M14 VIO_USB1 PWR ---

M15 USB_VBUS Wire Bare_Wire

M16 NC --- ---

M17 NC --- ---

N1 SUSPA# I GP24

N2 TCK I GP24

N3 TMS I GP24

N4 VSS GND ---

N14 VSSIO_USB4 GND ---

N15 USB_OC_SENS# I GP24

N16 USB_PWR_EN2 O GP24

N17 MHZ48_CLK I/O GP24

P1 TDI I GP24

P2 TDO O, TS GP24

P3 SUSP# O GP24

CIS O

P4 VIO PWR ---

P5 VSS GND ---

P6 VIO PWR ---

P7 VSS GND ---

P8 VCORE PWR ---

P9 VIO PWR ---

P10 VCORE PWR ---

P11 VSS GND ---

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

P12 VIO PWR ---

P13 VSS GND ---

P14 VIO_USB0 PWR ---

P15 AD7 I/O PCI

P16 AD4 I/O PCI

P17 USB_PWR_EN1 O GP24

R1 GNT# I PCI

R2 GPIO0 I/O PCI

R3 NC --- ---

R4 AD28 I/O PCI

R5 AD26 I/O PCI

R6 C/BE3# I/O PCI

R7 AD21 I/O PCI

R8 AD18 I/O PCI

R9 NC --- ---

R10 IRDY# I/O PCI

R11 DEVSEL# I/O PCI

R12 AD15 I/O PCI

R13 AD12 I/O PCI

R14 AD9 I/O PCI

R15 AD6 I/O PCI

R16 AD2 I/O PCI

R17 AD0 I/O PCI

T1 REQ# O PCI

T2 NC --- ---

T3 AD30 I/O PCI

T4 AD27 I/O PCI

T5 AD25 I/O PCI

T6 AD23 I/O PCI

T7 AD20 I/O PCI

T8 AD17 I/O PCI

T9 C/BE2# I/O PCI

T10 TRDY# I/O PCI

T11 STOP# I/O PCI

T12 AD14 I/O PCI

T13 AD11 I/O PCI

T14 AD8 I/O PCI

T15 AD5 I/O PCI

T16 AD3 I/O PCI

T17 AD1 I/O PCI

U1 AD31 I/O PCI

U2 NC --- ---

U3 AD29 I/O PCI

U4 PCI_CLK I GP24

U5 AD24 I/O PCI

U6 AD22 I/O PCI

U7 AD19 I/O PCI

U8 AD16 I/O PCI

U9 FRAME# I/O PCI

U10 PAR I/O PCI

U11 C/BE1# I/O PCI

U12 AD13 I/O PCI

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

Table 3-2. Ball Assignments: Sorted by Ball Number (Continued)

30 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

U13 AD10 I/O PCI

U14 C/BE0# I/O PCI

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

U15 NC --- ---

U16 NC --- ---

U17 NC --- ---

Note 1. The primary signal name is listed first.

Note 2. See Table 3-4 "Buffer Type Characteristics" on page 33 for buffer

type definitions.

Ball

No. Signal Name (Note 1) Type

Buffer Type

(Note 2) Configuration

Table 3-2. Ball Assignments: Sorted by Ball Number (Continued)

AMD Geode™ CS5536 Companion Device Data Book 31

Signal Definitions 33238G

Table 3-3. Ball Assignments: Sorted Alphabetically by Signal Name

Signal Name

Ball

No.

32KHZ C8

AC_BEEP K3

AC_CLK M1

AC_S_IN L1

AC_S_IN2 J3

AC_S_OUT L2

AC_S_SYNC L3

AD0 R17

AD1 T17

AD2 R16

AD3 T16

AD4 P16

AD5 T15

AD6 R15

AD7 P15

AD8 T14

AD9 R14

AD10 U13

AD11 T13

AD12 R13

AD13 U12

AD14 T12

AD15 R12

AD16 U8

AD17 T8

AD18 R8

AD19 U7

AD20 T7

AD21 R7

AD22 U6

AD23 T6

AD24 U5

AD25 T5

AD26 R5

AD27 T4

AD28 R4

AD29 U3

AD30 T3

AD31 U1

BOS0 L3

BOS1 L2

C/BE0# U14

C/BE1# U11

C/BE2# T9

C/BE3# R6

CIS P3

DEVSEL# R11

FLASH_AD10/IO0 B14

FLASH_AD11/IO1 A15

FLASH_AD12/IO2 C15

FLASH_AD13/IO3 C16

FLASH_AD14/IO4 B17

FLASH_AD15/IO5 D15

FLASH_AD16/IO6 E15

FLASH_AD17/IO7 E16

FLASH_AD18/AD3 E17

FLASH_AD19/AD4 D17

FLASH_AD20/AD5 D16

FLASH_AD21/AD6 C17

FLASH_AD22/AD7 A17

FLASH_AD23/AD8 B16

FLASH_AD24/AD9 B15

FLASH_AD25/AD0 A11

FLASH_AD26/AD1 A12

FLASH_AD27/AD2 B11

FLASH_ALE C14

FLASH_CE0# B10

FLASH_CE1# C10

FLASH_CE2# A14

FLASH_CE3# C12

FLASH_CLE A11

FLASH_CS0# B10

FLASH_CS1# C10

FLASH_CS2# A14

FLASH_CS3# C12

FLASH_IOCHRDY A13

FLASH_RDY/

BUSY#

A13

FLASH_RE# B13

FLASH_WE# C13

FRAME# U9

FUNC_TEST F3

GNT# R1

GPIO0 R2

GPIO1 K3

GPIO2 B12

GPIO3 E1

GPIO4 E2

GPIO5 D3

GPIO6 D2

GPIO7 C2

GPIO8 E3

GPIO9 D1

GPIO10 C3

GPIO11 A1

GPIO12 J3

GPIO13 F2

GPIO14 G3

GPIO15 F1

GPIO16 H2

GPIO17 J2

GPIO18 J1

GPIO19 K1

GPIO20 G1

GPIO21 G2

GPIO22 H3

Signal Name

Ball

No.

GPIO24 C9

GPIO25 A9

GPIO26 B7

GPIO27 C8

GPIO28 A8

IDE_AD0 A11

IDE_AD1 A12

IDE_AD2 B11

IDE_CS0# B10

IDE_CS1# C10

IDE_DACK0# C12

IDE_DATA0 B14

IDE_DATA1 A15

IDE_DATA2 C15

IDE_DATA3 C16

IDE_DATA4 B17

IDE_DATA5 D15

IDE_DATA6 E15

IDE_DATA7 E16

IDE_DATA8 E17

IDE_DATA9 D17

IDE_DATA10 D16

IDE_DATA11 C17

IDE_DATA12 A17

IDE_DATA13 B16

IDE_DATA14 B15

IDE_DATA15 C14

IDE_DREQ0 A14

IDE_IOR0# B13

IDE_IOW0# C13

IDE_IRQ0 B12

IDE_RDY0 A13

IDE_RESET# F15

IRDY# R10

IRQ13 K2

KHZ32_XCI A4

KHZ32_XCO B3

LOW_BAT# A9

LPC_AD0 H2

LPC_AD1 J2

LPC_AD2 J1

LPC_AD3 K1

LPC_CLK H1

LPC_DRQ# G1

LPC_FRAME# H3

LPC_SERIRQ G2

LVD_EN# C7

LVD_TEST B9

MFGPT0_C1 D3

MFGPT0_C2 K3

MFGPT0_RS D2

MFGPT1_C1 D2

MFGPT1_C2 A1

Signal Name

Ball

No.

MFGPT1_RS D3

MFGPT2_C1 C2

MFGPT2_C2 D2

MFGPT2_RS G2

MFGPT7_C1 C8

MFGPT7_C2 A9

MFGPT7_RS B7

MHZ14_CLK C1

MHZ48_CLK N17

MHZ48_XCEN F17

MHZ48_XCI H15

MHZ48_XCO J15

MHZ66_CLK A10

NC (Total of 21) A2,

A16,

B1,

B2,

B4,

B5,

C4,

C11,

F16,

J16,

J17,

L15,

M16,

M17,

R3,

R9,

T2,

U2,

U15,

U16,

U17

PAR U10

PCI_CLK U4

PWR_BUT# A8

REQ# T1

RESET_OUT# A5

RESET_STAND# B8

RESET_WORK# C6

SLEEP_BUT F2

SLEEP_X C2

SLEEP_Y J3

SLP_CLK_EN# A1

SMB_CLK G3

SMB_DATA F1

STOP# T11

SUSP# P3

SUSPA# N1

T_DEBUG_IN M2

T_DEBUG_OUT M3

TCK N2

TDI P1

TDO P2

TEST_MODE A6

THRM_ALRM# C3

TMS N3

TRDY# T10

UART1_IR_RX D1

Signal Name

Ball

No.

32 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

UART1_IR_TX E3

UART1_RX D1

UART1_TX E3

UART2_RX E1

UART2_TX E2

USB_OC_SENS# N15

USB_PWR_EN1 P17

USB_PWR_EN2 N16

USB1_DATNEG K17

USB1_DATPOS K16

USB2_DATNEG L17

USB2_DATPOS L16

USB3_DATNEG H16

USB3_DATPOS H17

USB4_DATNEG G16

USB4_DATPOS G17

USB_PTEST G15

USB_REXT K15

USB_VBUS M15

Signal Name

Ball

No.

VBAT A3

VCORE (Total of 6) D8,

D10,

H4,

K4,

P8,

P10

VCORE_VSB A7

VCORE_USB0 H14

VCORE_USB1 K14

VIO_USB0 P14

VIO_USB1 M14

VIO_USB2 F14

VIO_USB3 D14

Signal Name

Ball

No.

VIO (Total of 10) D4,

D6,

D9,

D12,

F4,

M4,

P4,

P6,

P9,

P12

VIO_VSB B6

VSS (Total of 13) D5,

D7,

D11,

D13,

E4,

G4,

J4,

L4,

N4,

P5,

P7,

P11,

P13

VSSIO_USB0 L14

VSSIO_USB1 J14

Signal Name

Ball

No.

VSSIO_USB2 G14

VSSIO_USB3 E14

VSSIO_USB4 N14

WORK_AUX C9

WORKING C5

Signal Name

Ball

No.

Table 3-3. Ball Assignments: Sorted Alphabetically by Signal Name (Continued)

AMD Geode™ CS5536 Companion Device Data Book 33

Signal Definitions 33238G

3.1.1 Buffer Types

Table 3-2 "Ball Assignments: Sorted by Ball Number" on

page 27 includes a column labeled “Buffer Type”. The

details of each buffer type listed in this column are given in

Table 3-4. The column headings in Table 3-4 are identified

as follows:

TS: Indicates whether the buffer may be put into the TRI-

STATE mode. Note that some pins having buffer types that

allow TRI-STATE may never actually enter the TRI-STATE

mode in practice, since they may be inputs or provide other

signals that are always driven. To determine if a particular

signal can be put in the TRI-STATE mode, consult the indi-

vidual signal descriptions in Section 3.2 "Signal Descrip-

tions" on page 36.

OD: Indicates if the buffer is open-drain, or not. Open-drain

outputs may be wire ORed together and require a discrete

pull-up resistor to operate properly.

5VT: Indicates if the buffer is 5-volt tolerant, or not. If it is 5-

volt tolerant, then 5 volt TTL signals may be safely applied

to this pin.

Backdrive Protected: Indicates that the buffer may have

active signals applied even when the CS5536 companion

device itself is powered down.

PU/PD: Indicates if an internal, programmable pull-up or

pull-down resistor may be present.

Current High/Low (mA): This column gives the current

source/sink capacities when the voltage at the pin is high,

and low. The high and low values are separated by a “/”

and values given are in milli-amps (mA).

Rise/Fall @ Load: This column indicates the rise and fall

times for the different buffer types at the load capacitance

indicated. These measurements are given in two ways:

rise/fall time between the 20%-80% voltage levels, or, the

rate of change the buffer is capable of, in volts-per-nano-

second (V/ns). See Section 7.3 "AC Characteristics" on

page 580 for details.

Note the presence of several “wire” type buffers in this

table. Signals identified as one of the wire-types are not

driven by a buffer, hence no rise/fall time or other measure-

ments are given; these are marked “NA” in Table 3-4. The

wire-type connection indicates a direct connection to inter-

nal circuits such as power, ground, and analog signals.

Table 3-4. Buffer Type Characteristics

Name TS OD 5VT

Backdrive

Protected PU/PD

Current

High/Low

(mA) Rise/Fall @ Load

GP24 X X 24/24 Max: 4 ns @ 50 pF

PCI (Note 1) X 0.5/1.5 Max: 4 V/ns @ 10 pF

Min: 1 V/ns @ 10 pF

IDE X X 6/6 Max: 1.0 V/ns @ 40 pF

Min: 0.4 V/ns @ 40 pF

SMB X X X Rise Max: 1 µs @ 400 pF

Fall Max: 300 ns @ 400 pF

USB Low-voltage differential-signal I/O buffer (Note 2)

Bare_Wire NA NA NA NA NA

Bare_Wire_BP NA NA X NA NA NA

Note 1. The PCI buffer type does not incorporate a clamping diode to VIO, however, the buffer circuitry provides the elec-

trical device protection as required by the PCI Local Bus Specification, Revision 2.3.

Note 2. For the electrical characteristics of the USB low-voltage differential-signal I/O buffer, see the USB Specification,

Revision 2.0.

34 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.1.2 Boot Options

Two balls on the device, L2 and L3, the Boot Options Select

balls (BOS[1:0]), serve to specify the location of the boot

device as the system undergoes a full reset. Since boot

devices may reside in Flash or on an IDE device, the

IDE/Flash interface is automatically selected as operating

in one of the two modes by the Boot Options. After Reset,

the function of these interfaces may be changed with the

Ball Options MSR (see Section 3.1.3 "Ball Options"). Both

these balls are multiplexed with other functions (as identi-

fied in Section 3.2.7 "Audio Codec 97 Interface" on page

46) and function as BOS[1:0] only when RESET_OUT# is

asserted. Table 3-5 indicates how these two balls should

be configured to select the desired boot device. Both balls

contain an internal pull-up, active only during reset, so if a

ball is required to be high during this time, it may be left

unconnected. If a ball is desired to be low during reset, a

pull-down (i.e., not a hard tie to ground) should be added.

During reset, both balls’ output drivers are in the TRI-

STATE mode.

3.1.3 Ball Options

Table 3-6 shows the Ball Options MSR (DIVIL MSR

51400015h), through which the function of certain groups

of multiplexed balls may be dynamically changed after the

reset period ends. Specifically, the functions LPC/GPIO

and IDE/Flash groups are selected, and certain individual

balls, as specified in the MSR, are controlled.

Table 3-5. Boot Options Selection

BOS1

(Ball L2)

BOS0

(Ball L3) Description

00Boot from Memory Device on the LPC Bus. IDE pins come up connected to IDE Control-

ler (see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6

"DIVIL_BALL_OPT (DIVIL MSR 51400015h)").

01Reserved.

10Boot from NOR Flash on the IDE Bus. IDE pins come up connected to Flash Controller

(see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6

"DIVIL_BALL_OPT (DIVIL MSR 51400015h)").

NOR Flash, ROM, or other random access devices must be connected to “FLASH_CS_3”.

11Boot from Firmware Hub on the LPC Bus. IDE pins come up connected to IDE Control-

ler (see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6

"DIVIL_BALL_OPT (DIVIL MSR 51400015h)").

Table 3-6. DIVIL_BALL_OPT (DIVIL MSR 51400015h)

Bit Name Description

31:12 RSVD Reserved. Reads always return 0. Writes have no effect; by convention, always write 0.

11:10 SEC_BOOT_LOC Secondary Boot Location. Determines which chip select asserts for addresses in the

range F00F0000h to F00F3FFFh. Defaults to the same value as boot option:

00: LPC ROM.

01: Reserved.

10: Flash.

11: FirmWare Hub.

9:8 BOOT_OP_

LATCHED (RO)

Latched Value of Boot Option (Read Only). For values, see Table 3-5 "Boot Options

Selection".

7 RSVD Reserved. Reads return value written. By convention, always write 0. Defaults low.

AMD Geode™ CS5536 Companion Device Data Book 35

Signal Definitions 33238G

6 PIN_OPT_LALL All LPC Pin Option Selection.

0: All LPC pins become GPIOs including LPC_DRQ# and LPC_SERIRQ.

Ball H3 functions as GPIO22

Ball H2 functions as GPIO16

Ball J2 functions as GPIO17

Ball J1 functions as GPIO18

Ball K1 functions as GPIO19

Ball G1 functions as GPIO20

Ball G2 functions as GPIO21

1: All LPC pins are controlled by the LPC controller except LPC_DRQ# and

LPC_SERIRQ. Their use is determined by bits [5:4]. (Default)

Ball H3 functions as LPC_FRAME#

Ball H2 functions as LPC_AD0

Ball J2 functions as LPC_AD1

Ball J1 functions as LPC_AD2

Ball K1 functions as LPC_AD3

When this bit is low, there is an implied high for the LPC_DISABLE_MEM and

LPC_DISABLE_IO bits in DIVIL_LEG_IO (DIVIL MSR 51400014h[25:24]).

5 PIN_OPT_LIRQ LPC_SERIRQ or GPIO21 Pin Option Selection.

0: Ball G2 is GPIO21.

1: Ball G2 functions as LPC_SERIRQ. (Default)

4 PIN_OPT_LDRQ LPC_DRQ# or GPIO20 Pin Option Selection.

0: Ball G1 is GPIO20.

1: Ball G2 functions as LPC_DRQ#. (Default)

3:2 PRI_BOOT_LOC

[1:0]

Primary Boot Location. Determines which chip select asserts for addresses at or

above F0000000h, except those in the range specified by SEC_BOOT_LOC (bits

[11:10]). Defaults to the same value as boot option.

00: LPC ROM.

01: Reserved.

10: Flash.

11: FirmWare Hub.

1 RSVD Reserved. Reads return value written. By convention, always write 0. Defaults low.

0 PIN_OPT_IDE IDE or Flash Controller Pin Function Selection.

0: All IDE pins associated with Flash Controller. Default if BOS[1:0] = 10.

1: All IDE pins associated with IDE Controller. Default if BOS[1:0] = 00 or 11.

IDE_IRQ0 is multiplexed with GPIO2; therefore, this bit has no affect with regards to

programming IDE_IRQ0. See Table 3-5 "Boot Options Selection" for BOS[1:0] pro-

gramming values.

Table 3-6. DIVIL_BALL_OPT (DIVIL MSR 51400015h) (Continued)

Bit Name Description

36 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2 Signal Descriptions

3.2.1 System Interface Signals

Signal Name Ball No. Type Description

MHZ66_CLK A10 I 66 MHz Clock. This is the main system clock. It is also used by the IDE

interface.

MHZ48_CLK N17 I/O USB Clock. The 48 MHz clock for the UARTs and SMB Controller. If

MHZ48_XCEN is high, this pin can be used as output of the 48 MHz

clock generated by the crystal on MHZ48_XCI and MHZ48_XCO.

MHZ14_CLK C1 I 14.31818 MHz Timer Clock. The input clock for power management

functions and the Programmable Interval Timer (PIT).

KHZ32_XCI A4 Wire 32 KHz Input. This input is used for the real-time clock (RTC), GPIOs,

MFGPTs, and power management functions.

This input may come from either an external oscillator or one side of a

32.768 KHz crystal. If an external oscillator is used, it should be pow-

ered by VIO_VSB. This signal takes approximately one second to lock

after power-up.

KHZ32_XCO B3 Wire 32 KHz Input 2. This input is to be connected to the other side of the

crystal oscillator connected to KHZ32_XCI, if used. Leave open (not

connected) if an oscillator (not a crystal) is connected to KHZ32_XCI.

MHZ48_XCI H15 Wire 48 MHz Input. This input is used for USB, the UARTs and SMB con-

troller if MHZ48_XCEN is high. This pin is connected to one side of the

crystal. Tie this signal to ground if MHZ48_XCEN is low. If used for

High Speed Mode, connect these pins to a 48 MHz fundamental fre-

quency crystal.

MHZ48_XCO J15 Wire 48 MHz Input 2. This input is to be connected to the other side of the

crystal oscillator connected to MHZ48_XCI, if used. Leave open (not

connected) if MHZ48_XCEN is low. If used for High Speed Mode, con-

nect these pins to a 48 MHz fundamental frequency crystal.

MHZ48_XCEN F17 Wire 48 MHz Input Control. This input controls if the crystal on

MHZ48_XCI and MHZ48_XCO or MHZ48_CLK is used as clock for the

UARTS, USB and SMB Controller. If high the crystal inputs are used.

RESET_WORK# C6 I Reset Working Power Domain. This signal, when asserted, is the

master reset for all CS5536 interfaces that are in the Working power

domain. See Section 4.8.1 "Power Domains" on page 80 for a descrip-

tion of the Working power domain.

RESET_WORK# must be asserted for at least 10 ns in order to be

properly recognized.

If LVD_EN# is enabled (tied low), use of this input is not required. See

the LVD_EN# discussion in this table.

RESET_STAND# B8 I Reset Standby Power Domain. This signal, when asserted, is the

master reset for all CS5536 interfaces that are in the Standby power

domain. See Section 4.8.1 "Power Domains" on page 80 for a descrip-

tion of the Working power domain.

If LVD_EN# is enabled (tied low), use of this input is not required. See

the LVD_EN# discussion in this table.

Tie directly to VIO_VSB if not used.

AMD Geode™ CS5536 Companion Device Data Book 37

Signal Definitions 33238G

RESET_OUT# A5 O Reset Output. This is the main system reset signal. RESET_OUT# is

de-asserted synchronously with the low-to-high edge of PCI_CLK. The

de-assertion is delayed from internal reset by up to 32 seconds, with

an 8 ms default value, using a programmable counter driven by the 32

KHz clock. Note this counter default is established by

RESET_STAND# and is not affected by RESET_WORK#. Therefore,

the delay value may be changed and the system reset with the new

value.

WORKING C5 O Working State. When high, indicates the chip is in the Working state.

This signal is intended to be used to control power to off-chip devices

in a system. Open-drain. External pull-up required.

SUSP# P3 O Suspend. This signal goes low in response to events as determined by

the power management logic. It requests the AMD Geode™ LX

processor to enter the Suspend state. This is the default state for this

ball at reset. Not used in normal operation.

CIS O CPU Interface Serial. A 20-bit serial status word is output on this ball,

synchronized to PCI_CLK. Data changes on the rising edge and is sta-

ble on the falling edge of PCI_CLK. This WORD is output whenever

one of the internally-monitored signals changes states. See Section

5.2.14 "CPU Interface Serial (CIS)" on page 86 for details. Used in

normal operation.

SUSPA# N1 I Suspend Acknowledge. This input signal is driven low by the

AMD Geode LX processor when it has successfully entered the

Suspend state.

IRQ13 K2 I Interrupt Request Level 13. Floating Point error. Connect directly to

IRQ13 of the AMD Geode LX processor.

VBAT A3 Wire Real-Time Clock Battery Back-Up. Battery voltage on this ball keeps

the real-time clock and CMOS RAM circuits continuously powered.

If not used, tie to ground. This ball incorporates a reverse bias protec-

tion diode on-chip. There is no need for an external diode.

LVD_EN# C7 Wire Low Voltage Detect Enable. LVD_EN# enables/disables the on-chip

low voltage detection circuit. When disabled, the external subsystem

must assert RESET_STAND# as Standby power is applied and must

assert RESET_WORK# as Working power is applied. When LVD is

enabled, use of these two resets is optional. Generally,

RESET_STAND# would be tied high (not used) while RESET_WORK#

would be tied to a reset output that is typically available from the power

supply. However, a system could just have a simple regulator circuit

and also tie RESET_WORK# high.

Tie to VSS to enable. Tie to VIO_VSB to disable.

3.2.1 System Interface Signals (Continued)

Signal Name Ball No. Type Description

38 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2.2 PCI Interface Signals

Signal Name

(Note 1) Ball No. Type Description

PCI_CLK U4 I PCI Clock. 33 or 66 MHz.

AD[31:0] U1, T3, U3,

R4, T4, R5,

T5, U5, T6,

U6, R7, T7,

U7, R8, T8,

U8, R12,

T12, U12,

R13, T13,

U13, R14,

T14, P15,

R15, T15,

P16, T16,

R16, T17,

R17

I/O PCI Address/Data. AD[31:0] is a physical address during the first

clock of a PCI transaction; it is the data during subsequent clocks.

When the CS5536 is a PCI master, AD[31:0] are outputs during the

address and write data phases, and are inputs during the read data

phase of a transaction.

When the CS5536 is a PCI slave, AD[31:0] are inputs during the

address and write data phases, and are outputs during the read data

phase of a transaction.

C/BE[3:0]# R6, T9, U11,

U14

I/O PCI Bus Command and Byte Enables. During the address phase of

a PCI transaction, when FRAME# is active, C/BE[3:0]# define the bus

command. During the data phase of a transaction, C/BE[3:0]# are the

data byte enables.

C/BE[3:0]# are outputs when the CS5536 is a PCI master and inputs

when it is a PCI slave.

PAR U10 I /O PCI Parity. PAR is the parity signal driven to maintain even parity

across AD[31:0] and C/BE[3:0]#.

The CS5536 drives PAR one clock after the address phase and one

clock after each completed data phase of write transactions as a PCI

master. It also drives PAR one clock after each completed data phase

of read transactions as a PCI slave.

FRAME# U9 I/O PCI Cycle Frame. FRAME# is asserted to indicate the start and dura-

tion of a transaction. It is de-asserted on the final data phase.

FRAME# is an input when the CS5536 is a PCI slave.

Normally connected to a 10k to 15k ohm external pull-up. This signal is

in TRI-STATE mode after reset.

DEVSEL# R11 I/O PCI Device Select. DEVSEL# is asserted by a PCI slave to indicate to

a PCI master and subtractive decoder that it is the target of the current

transaction.

As an input, DEVSEL# indicates a PCI slave has responded to the cur-

rent address.

As an output, DEVSEL# is asserted one cycle after the assertion of

FRAME# and remains asserted to the end of a transaction as the

result of a positive decode. DEVSEL# is asserted four cycles after the

assertion of FRAME# if DEVSEL# has not been asserted by another

PCI device when the CS5536 is programmed to be the subtractive

decode agent.

Normally connected to a 10k to 15k ohm external pull-up. This signal is

in TRI-STATE mode after reset.

AMD Geode™ CS5536 Companion Device Data Book 39

Signal Definitions 33238G

IRDY# R10 I/O PCI Initiator Ready. IRDY# is driven by the master to indicate valid

data on a write transaction, or that it is ready to receive data on a read

transaction.

When the CS5536 is a PCI slave, IRDY# is an input that can delay the

beginning of a write transaction or the completion of a read transaction.

Wait cycles are inserted until both IRDY# and TRDY# are asserted

together.

Normally connected to a 10k to 15k ohm external pull-up. This signal is

in TRI-STATE mode after reset.

TRDY# T10 I/O PCI Target Ready. TRDY# is asserted by a PCI slave to indicate it is

ready to complete the current data transfer.

TRDY# is an input that indicates a PCI slave has driven valid data on a

read or a PCI slave is ready to accept data from the CS5536 on a

write.

TRDY# is an output that indicates the CS5536 has placed valid data on

AD[31:0] during a read or is ready to accept the data from a PCI mas-

ter on a write.

Wait cycles are inserted until both IRDY# and TRDY# are asserted

together.

Normally connected to a 10k to 15k ohm external pull-up. This signal is

in TRI-STATE mode after reset.

STOP# T11 I/O PCI Stop. As an input, STOP# indicates that a PCI slave wants to ter-

minate the current transfer. The transfer is either aborted or retried.

STOP# is also used to end a burst.

As an output, STOP# is asserted with TRDY# to indicate a target dis-

connect, or without TRDY# to indicate a target retry. The CS5536

asserts STOP# during any cache line crossings if in single transfer

DMA mode or if busy.

Normally connected to a 10k to 15k ohm external pull-up. This signal is

in TRI-STATE mode after reset.

REQ# T1 O PCI Bus Request. The CS5536 asserts REQ# to gain ownership of

the PCI bus. The REQ# and GNT# signals are used to arbitrate for the

PCI bus.

REQ# should connect to the REQ2# of the AMD Geode LX processor

and function as the highest-priority PCI master.

GNT# R1 I PCI Bus Grant. GNT# is asserted by an arbiter that indicates to the

CS5536 that access to the PCI bus has been granted.

GNT# should connect to GNT2# of the AMD Geode LX processor and

function as the highest-priority PCI master.

Note 1. Use RESET_OUT# for PCI reset.

For SMI, PME, INTA#, and INTB# functions, see Table 3-8 "GPIO Options" on page 47.

3.2.2 PCI Interface Signals (Continued)

Signal Name

(Note 1) Ball No. Type Description

40 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2.3 IDE/Flash Interface Signals

The IDE and Flash interface signals are multiplexed together on the same balls as shown in Table 3-7. Section 3.2.3.1 pro-

vides the names and functions of these signals when the interface is in the IDE mode and Section 3.2.3.2 when in Flash

mode (NOR Flash/GPCS and NAND Flash modes).

Table 3-7. IDE and Flash Ball Multiplexing

Ball No. IDE Mode

NOR Flash/GPCS Mode

NAND Flash ModeAddress Phase Data Phase

B11, A12 IDE_AD[2:1] FLASH_AD[27:26] FLASH_AD[2:1] ---

A11 IDE_AD0 FLASH_AD25 FLASH_AD0 FLASH_CLE

B15, B16, A17, C17,

D16, D17, E17

IDE_DATA[14:8] FLASH_AD[24:18] FLASH_AD[9:3] ---

E16, E15, D15, B17,

C16, C15, A15, B14

IDE_DATA[7:0] FLASH_AD[17:10] FLASH_IO[7:0] FLASH_IO[7:0]

C14 IDE_DATA15 FLASH_ALE FLASH_ALE

B10 IDE_CS0# FLASH_CS0# FLASH_CE0#

C10 IDE_CS1# FLASH_CS1# FLASH_CE1#

B13 IDE_IOR0# FLASH_RE# FLASH_RE#

C13 IDE_IOW0# FLASH_WE# FLASH_WE#

A14 (Note 1)

Note 1. Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash

mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to

keep it high during IDE mode.

IDE_DREQ0 FLASH_CS2# FLASH_CE2#

C12 IDE_DACK0# FLASH_CS3# (Boot Flash Chip Select) FLASH_CE3#

A13 IDE_RDY0 FLASH_IOCHRDY FLASH_RDY/BUSY#

3.2.3.1 IDE Interface Signals

Signal Name Ball No. Type Description

IDE_IRQ0 B12 I IDE Interrupt Request Channel 0. This signal is required for all IDE

applications that use IDE DMA modes. It is available on GPIO2, which

must be configured in the IN_AUX1 mode. If an IDE application will not

use IDE DMA modes, or if the Flash interface will be used instead of

the IDE interface, then this signal may be used as GPIO2.

IDE_RESET# F15 O IDE Reset. IDE port reset signal. This bit can be controlled by Section

6.5.2.6 "IDE Power Management Register (IDE_PM)" on page 340.

IDE_AD[2:0] B11, A12,

A11

OIDE Address Bits. These address bits are used to access a register or

data port in a device on the IDE bus.

IDE_DATA[15:0] C14, B15,

B16, A17,

C17, D16,

D17, E17,

E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O IDE Data Lines. IDE_DATA[15:0] transfers data to/from the IDE

devices.

AMD Geode™ CS5536 Companion Device Data Book 41

Signal Definitions 33238G

IDE_IOR0# B13 O IDE I/O Read. This output is asserted on read accesses to corre-

sponding IDE port addresses.

When in Ultra DMA/33 mode, this signal is redefined:

•IDE_HDMA_RDY. Host DMA Ready for Ultra DMA data-in bursts.

•IDE_HDMA_DS. Host DMA Data Strobe for Ultra DMA data-out

bursts.

IDE_IOW0# C13 O IDE I/O Write. This output is asserted on write accesses to corre-

sponding IDE port addresses.

When in Ultra DMA/33 mode, this signal is redefined:

•IDE_STOP - Stop Ultra DMA data burst.

IDE_CS0# B10 O IDE Chip Select 0. This chip select signal is used to select the Com-

mand Block registers in IDE Device 0.

IDE_CS1# C10 O IDE Chip Select. This chip select signal is used to select the Com-

mand Block registers in IDE Device 1.

IDE_DREQ0 A14 I DMA Request. This input signal is used to request a DMA transfer

from the CS5536. The direction of the transfers are determined by the

IDE_IOR0# and IDE_IOW0# signals.

Note: Ball A14 is the only ball that changes direction from IDE to

Flash (input when in IDE mode, output when in Flash mode). If

this interface is to be switched between IDE and Flash modes,

then ball A14 needs an external pull-up to keep it high during

IDE mode.

IDE_DACK0# C12 O DMA Acknowledge. This output signal acknowledges the

IDE_DREQ0 request to initiate DMA transfers.

IDE_RDY0 A13 I I/O Ready. When de-asserted, this signal extends the transfer cycle of

any host register access when the device is not ready to respond to the

data transfer request.

When in Ultra DMA/33 mode, this signal is redefined:

•STROBE - Device DMA Data Strobe for Ultra DMA data-in bursts.

•DMARDY# - Device DMA Ready for Ultra DMA data-out bursts.

3.2.3.1 IDE Interface Signals (Continued)

Signal Name Ball No. Type Description

42 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2.3.2 Flash Controller Interface

Signal Name Ball No. Type Description

NOR Flash / GPCS Mode

FLASH_CS[3:0]# C12, A14,

C10, B10

OChip Selects. Combine with FLASH_RE#/WE# strobes to access

external NOR Flash devices or some simple devices such as a UART.

CS3# is dedicated to a boot Flash device.

Note: Ball A14 is the only ball that changes direction from IDE to

Flash (input when in IDE mode, output when in Flash mode).

If this interface is to be switched between IDE and Flash

modes, then ball A14 needs an external pull-up to keep it high

during IDE mode.

FLASH_RE# B13 O Read Enable Strobe. This signal is asserted during read operations

from the NOR array.

FLASH_WE# C13 O Write Enable Strobe. This signal is asserted during write operations

to the NOR array.

FLASH_ALE C14 O Address Latch Enable. Controls external latch (e.g., 74x373) for

latching the higher address bits in address phase.

FLASH_AD[27:26]/

AD[2:1],

FLASH_AD25/

AD0,

FLASH_AD[24:18]/

AD[9:3]

B11, A12,

A11, B15,

B16, A17,

C17, D16,

D17, E17

OAddress Bus. During the address phase, address [27:18] is put on

the bus. During the data phase, address [9:0] is put on the bus.

FLASH_AD[17:10]/

IO[7:0]

E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O Multiplexed Address and I/O Bus. During the address phase, NOR

address [17:10] are placed on these lines. During the data phase, it is

the NOR I/O data bus.

FLASH_IOCHRDY A13 I I/O Channel Ready. When a device on the bus wants to extend its

current cycle, it pulls this signal low to insert the wait state.

NAND Flash Mode

FLASH_CE[3:0]# C12, A14,

C10, B10

OChip Enables. These signals remain low during a NAND cycle.

Note: Ball A14 is the only ball that changes direction from IDE to

Flash. Needs external pull-up for Flash use.

FLASH_RE# B13 O Read Enable Strobe. This signal is asserted during read operations

from the NAND array.

FLASH_WE# C13 O Write Enable Strobe. This signal is asserted during write operations

to the NAND array.

FLASH_ALE C14 O Address Latch Enable. Level signal to indicate an address byte is

writing to the NAND Flash device.

FLASH_CLE A11 O Command Latch Enable. Indicates a command byte is being written

to the device.

FLASH_IO[7:0] E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O I/O Bus. I/O bus for NAND Flash devices. Command, address, and

data are sent on this bus. This bus is actively driven to zero with or

without an LPC_CLK from and after reset.

FLASH_RDY/BUSY# A13 I Ready/Busy#. NAND Flash pulls this signal low to indicate it is busy

with an internal operation. No further action is accepted except read

status.

AMD Geode™ CS5536 Companion Device Data Book 43

Signal Definitions 33238G

3.2.4 USB Interface

Signal Name Ball No. Type Description

USB_PWR_EN1 P17 O USB Power Enable 1. This signal is intended to be used to enable an

external USB power source for the USB ports 1, 2, and 3.

USB_PWR_EN1 is an active high signal. If low, it indicates that the

external USB power source for the associated USB ports is turned off.

Defaults off from reset.

USB_PWR_EN2 N16 O USB Power Enable 2. This signal is intended to be used to enable an

external USB power source for USB port 4.

USB_PWR_EN2 is an active high signal. If low, it indicates that the

external USB power source for the associated USB port is turned off.

Defaults off from reset.

USB_OC_SENS# N15 I USB Over Current Sense. This signal is the logical OR or wired-OR

from all external USB power supply devices, and is shared by all four

ports. When pulled low it causes both USB_PWR_EN1 and

USB_PWR_EN2 to de-assert and generate an interrupt. Tie high if not

used.

USB1_DATPOS K16 I/O USB Port 1 Data Positive. This is the positive differential side of the

USB data for port 1.

USB1_DATNEG K17 I/O USB Port 1 Data Negative. This is the negative differential side of the

USB data for port 1.

USB2_DATPOS L16 I/O USB Port 2 Data Positive. This is the positive differential side of the

USB data for port 2.

USB2_DATNEG L17 I/O USB Port 2 Data Negative. This is the negative differential side of the

USB data for port 2.

USB3_DATPOS H17 I/O USB Port 3 Data Positive. This is the positive differential side of the

USB data for port 3.

USB3_DATNEG H16 I/O USB Port 3 Data Negative. This is the negative differential side of the

USB data for port 3.

USB4_DATPOS G17 I/O USB Port 4 Data Positive. This is the positive differential side of the

USB data for port 4.

USB4_DATNEG G16 I/O USB Port 4 Data Negative. This is the negative differential side of the

USB data for port 4.

USB_REXT K15 Wire USB External Resistor Connect. Connect this pin via a 3.4 K W (+/-

1%) resistor to ground.

USB_VBUS M15 A USB Bus Voltage. In device mode, this pin is used to sense the bus

voltage coming over the USB receptacle to generate status signals, in

order to inform the USB device software about the bus power status.

This is also required for self powered devices.

VCORE_USB[1:0] H14, K14 PWR Core Power Working Connection (Total of 2). Balls for the USB

transceivers. Most applications should connect this to VCORE.

VIO_USB[3:0] D14, F14,

M14, P14

PWR I/O Power Connection (Total of 4). Balls for the USB transceivers.

Most applications should connect this to VIO.

VSSIO_USB[4:0] E14, G14,

J14, L14,

N14

GND Ground Connection (Total of 5). Balls for the USB transceivers. Most

applications should connect this to ground.

44 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2.5 System Management Bus (SMB) Interface

Signal Name Ball No. Type Description

SMB_CLK G3 I/O SMB Clock. This is the clock for the System Management Bus. It is ini-

tiated by the master of the current transaction. Data is sampled during

the high state of the clock.

An external pull-up resistor is required.

Shared with GPIO14. Set GPIO14 to IN_AUX1 and OUT_AUX1 modes

simultaneously to use as SMB_CLK. See Table 3-8 "GPIO Options" on

page 47.

This ball is 5V tolerant.

SMB_DATA F1 I/O SMB Data. This is the bidirectional data line for the System Manage-

ment Bus. Data may change during the low state of the SMB clock and

should remain stable during the high state.

An external pull-up resistor is required.

Shared with GPIO15. Set GPIO15 to IN_AUX1 and OUT_AUX1 modes

simultaneously to use as SMB_DATA. See Table 3-8 "GPIO Options"

on page 47.

This ball is 5V tolerant.

3.2.6 Low Pin Count (LPC) Interface

Signal Name

(Note 1) Ball No. Type Description

LPC_CLK H1 I LPC Clock. 33 MHz LPC bus shift clock.

LPC_AD[3:0] K1, J1, J2,

I/O LPC Address/Data Bus. This is the 4-bit LPC bus. Address, control,

and data are transferred on this bus between the AMD Geode CS5536

companion device and LPC devices.

An external pull-up of 100 kW is required on these balls (if used in LPC

mode) to maintain a high level when the signals are in TRI-STATE

mode. From reset, these signals are not driven.

LPC_AD3 is shared with GPIO19.

LPC_AD2 is shared with GPIO18.

LPC_AD1 is shared with GPIO17.

LPC_AD0 is shared with GPIO16.

See Table 3-8 "GPIO Options" on page 47 for further details.

LPC_DRQ# G1 I LPC DMA Request. This is the LPC DMA request signal. Peripherals

requiring service pull it low and then place a serially-encoded

requested channel number on this line to initiate a DMA transfer.

If the device wakes up from Sleep, at least six LPC_CLKs must occur

before this input is asserted.

Shared with GPIO20. See Table 3-8 "GPIO Options" on page 47. Tie

high if selected as LPC_DRQ# but not used.

AMD Geode™ CS5536 Companion Device Data Book 45

Signal Definitions 33238G

LPC_SERIRQ G2 I/O LPC Encoded IRQ. This is the LPC serial interrupt request line, used

to report ISA-style interrupt requests. It may be activated by either the

AMD Geode CS5536 companion device or an LPC peripheral.

An external pull-up of 100 kW is required if this ball is used in LPC

mode to maintain a high level when the signal is in TRI-STATE. From

reset, this signal is not driven.

If the device wakes up from Sleep, at least six LPC_CLKs must occur

before this input is asserted if operating in Quiet mode.

Shared with GPIO21. See Table 3-8 "GPIO Options" on page 47.

LPC_FRAME# H3 O LPC Frame. This signal provides the active-low LPC FRAME signal

used to start and stop transfers on the LPC bus.

Shared with GPIO22. See Table 3-8 "GPIO Options" on page 47.

Note 1. All LPC signals, except LPC_CLK are shared on GPIO balls (see Table 3-8 "GPIO Options" on page 47). The

AMD Geode CS5536 companion device powers up with this group of balls set to the LPC mode; to use them as

GPIOs they must be explicitly reprogrammed. The LPC signals may be switched to GPIOs via MSR 51400015h

(see Section 6.6.2.10 "Ball Options Control (DIVIL_BALL_OPTS)" on page 365).

Use RESET_OUT# for LPC reset.

Use any GPIO assigned as a PME for the LPC PME.

Use any GPIO assigned as an SMI for the LPC SMI.

Use general Sleep and Standby controls (SLEEP_X, ball C2 and SLEEP_Y, ball J3) in place of LPC_PD# for LPC

power-down.

3.2.6 Low Pin Count (LPC) Interface (Continued)

Signal Name

(Note 1) Ball No. Type Description

46 AMD Geode™ CS5536 Companion Device Data Book

Signal Definitions

33238G

3.2.7 Audio Codec 97 Interface

Signal Name

(Note 1) Ball No. Type Description

AC_CLK M1 I Audio Bit Clock. The serial bit clock from the codec. The frequency of

the bit clock is 12.288 MHz and is derived from the 24.576 MHz crystal

input to the external audio codec. Not required if audio not used; tie low.

AC_S_OUT L2 O Audio Controller Serial Data Out. This output transmits audio data to

the codec. This data stream contains both control data and the DAC

audio data. The data is sent on the rising edge of the AC_CLK. Connect

to the audio codec’s serial data input pin.

BOS1 I Boot Options Select Bit 1. During system reset, this ball is the MSB of

the 2-bit boot option (balls L2 and L3) and is used to determine the loca-

tion of the system boot device. It should be pulled low if required by Table

3-5 "Boot Options Selection" on page 34, otherwise, an internal pull-up,

asserted during reset, will pull it high. During reset, the ball output drivers

are held in TRI-STATE mode, and the ball is sampled on the rising edge

of RESET_OUT# (i.e., when external reset is de-asserted). After reset,

this signal defaults low (off).

AC_S_IN L1 I Audio Controller Serial Data Input. This input receives serial data from

the audio codec. This data stream contains both control data and ADC

audio data. This input data is sampled on the falling edge of AC_CLK.

Connect to the audio codec’s serial data output pin.

AC_S_SYNC L3 O Audio Controller Sync. This is a 48 KHz sync pulse that signifies the

beginning of a serial transfer on AC_S_OUT, AC_S_IN, and AC_S_IN2.

AC_S_SYNC is synchronous to the rising edge of AC_CLK. Connect to

the audio codec’s SYNC pin.

BOS0 I Boot Options Select Bit 0. During system reset, this ball is the LSB of

the 2-bit boot option (balls L2 and L3), used to determine the location of

the system boot device. It should be pulled low if required by Table 3-5

"Boot Options Selection" on page 34, otherwise, an internal pull up,

asserted during reset, will pull it high. During reset, the ball drivers are

held in TRI-STATE mode, and the ball is sampled on the rising edge of

RESET_OUT# (i.e., when external reset is de-asserted). After reset, this

signal defaults low (off).

AC_BEEP K3 O Legacy PC/AT Speaker Beep. Connect to codec’s PC_BEEP.

This function is only available when GPIO1 is programmed to

OUT_AUX1. See Table 3-8 "GPIO Options" on page 47.

AC_S_IN2 J3 I Audio Controller Serial Data Input 2. This input receives serial data

from a second codec. This data stream contains both control data and

ADC audio data. This input data is sampled on the falling edge of

AC_CLK. If the codec’s Ready bit is set in this stream (slot 0, bit 15), then

it is functionally ORed with AC_S_IN.

Connect to a second codec’s serial data output.

This function is only available when GPIO12 is programmed to IN_AUX1.

See Table 3-8 "GPIO Options" on page 47.

Note 1. Use RESET_OUT# for AC97 reset.

AMD Geode™ CS5536 Companion Device Data Book 47

Signal Definitions 33238G

3.2.8 GPIOs

Table 3-8 gives the dedicated functions associated with

each GPIO. These functions may be invoked by configuring

the associated GPIO to the IN_AUX1, OUT_AUX1, or

OUT_AUX2 modes. (The functions themselves are

described in Table 3-9 "GPIOx Available Functions

Descriptions" on page 49.) The column “Recommended

Use” is a guideline for system designers to assign GPIO

functionality. Any GPIO input can be mapped to an inter-

rupt, ASMI, or PME. Details of configuring the GPIOs are in

Section 6.16 "GPIO Device Register Descriptions" on page

480. All GPIOs have selectable pull-up and/or pull-down

resistors available on the output, except for those indicated

by Note 1 in the “Weak PU/PD” column of Table 3-8.

Table 3-8. GPIO Options

GPIO

Ball

No.

Power

Domain

Buffer

Type

Post Reset

Recommended

Use

Function Programming Options

Weak

PU/PD I/O Config IN_AUX1 OUT_AUX1 OUT_AUX2

GPIO0 R2 W PCI (Note 1) Disabled PCI_INTA#

(Note 2)

GPIO1 K3 W GP24 PU Disabled --- AC_BEEP MFGPT0_C2

GPIO2 B12 W IDE (Note 1) Disabled --- IDE_IRQ0

GPIO3 E1 W SMB (Note 1) Disabled DDC_SCL

(Note 3)

UART2 RX

GPIO4 E2 W SMB (Note 1) Disabled DDC_SDA

(Note 3)

UART2 TX

GPIO5 D3 W GP24 Auto-

sense

Disabled --- MFGPT1_RS MFGPT0_C1

GPIO6 D2 W GP24 Auto-

sense

Disabled --- MFGPT0_RS MFGPT1_C1 MFGPT2_C2

GPIO7 C2 W PCI (Note 1) Disabled PCI_INTB#

(Note 2)

MFGPT2_C1 SLEEP_X

GPIO8 E3 W GP24 PU Disabled --- UART1_TX UART1_IR_TX

GPIO9 D1 W GP24 PU Disabled --- UART1_RX or

UART1_IR_RX

GPIO10 C3 S

(Note 4)

GP24 PU Disabled --- (Note 5) THRM_ALRM#

GPIO11 A1 W GP24 PU Disabled --- SLP_CLK_EN# MFGPT1_C2

GPIO12 J3 W GP24 PD Disabled --- AC_S_IN2 SLEEP_Y

GPIO13 F2 W GP24 PU Disabled --- (Note 5) SLEEP_BUT

GPIO14 G3 W SMB (Note 1) Disabled --- (Note 6) SMB_CLK_IN SMB_CLK_OUT

GPIO15 F1 W SMB (Note 1) Disabled --- (Note 6) SMB_DATA_IN SMB_DATA_OUT

GPIO16 H2 W PCI (Note 1) LPC (Note 7) LPC_AD0

GPIO17 J2 W PCI (Note 1) LPC (Note 7) LPC_AD1

GPIO18 J1 W PCI (Note 1) LPC (Note 7) LPC_AD2

GPIO19 K1 W PCI (Note 1) LPC (Note 7) LPC_AD3

GPIO20 G1 W PCI (Note 1) LPC (Note 7) LPC_DRQ#

GPIO21 G2 W PCI (Note 1) LPC (Note 7) LPC_SERIRQ MFGPT2_RS

GPIO22 H3 W PCI (Note 1) LPC (Note 7) LPC_FRAME#

GPIO24 C9 S SMB (Note 1) Disabled --- WORK_AUX

Note 8

GPIO25 A9 S GP24 PU/PD Disabled --- LOW_BAT# MFGPT7_C2

GPIO26 B7 S GP24 PU/PD Disabled PME# (Note 9) MFGPT7_RS

GPIO27 C8 S GP24 PU/PD Disabled --- MFGPT7_C1 32KHZ

GPIO28 A8 S GP24 PU/PD Input Enabled

(Note 10)

PWR_BUT#

(Note 11)

PWR_BUT#

(Note 12)

Note 1. No internal pull-up/down available. If not used, tie low.

Note 2. Any GPIO can be used as an interrupt input without restriction. These particular GPIOs have PCI I/O buffer types for complete PCI

bus compatibility. However, such strict compatibility is generally not required.

48 AMD Geode™ CS5536 Companion Device Data Book

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Note 3. Applications incorporating a CRT often require support for the Display Data Channel (DDC) serial interface. These particular

GPIOs have open collector SMB I/O buffer types required by the DDC interface specification. The DDC protocol supplied by AMD

is provided via software implementation and defaults to these GPIOs. However, any design not needing strict DDC electrical sup-

port can use other GPIOs. Lastly, applications not incorporating DDC use at all may use these GPIOs without restriction.

Note 4. The I/O cell of the pin GPIO10/THRM_ALRM# is powered by the Standby power domain. The logic associated with the function

GPIO10 is powered by the Working power domain while the logic associated with the function THRM_ALRM# is powered by the

Standby power domain

Note 5. Internal signal is active high. Use GPIO invert for active low external.

Note 6. When both IN_AUX1 and AUX_OUTx are enabled, I/O direction on this ball is controlled by the SMB Controller.

Note 7. Defaults to LPC use. Use Ball Options MSR (see Table 3-6 on page 34) to switch this ball to GPIO control.

Note 8. When WORK_AUX is used for Save-to-RAM (ACPI S3), initial state is GPIO24 input. This can cause power turn on issues. An

external blocking circuit must be used to prevent WORK_AUX from incorrectly causing power application at initial application of the

standby voltages.

Note 9. Any GPIO can be used as a Power Management Event (PME) wakeup input without restriction. PMEs are supported for both Sleep

and Standby wakeup. However, if Standby wakeup is desired, a GPIO on the Standby power domain must be used. Only

GPIO[24:28] are supplied via the Standby Power Rail and are typically used as follows:

GPIO24 - Auxiliary Working Power Control

GPIO25 - Low Battery Alarm

GPIO26 - PME

GPIO27 - MFGPT setup to provide a blink

GPIO28 - Power Button

Depending on application use, the PME function could be moved to GPIO[24:27]. If only external PME wakeup from Sleep is re-

quired, the PME function could be moved to GPIO[0:23]. Lastly, the PME function could simply not be used, making more GPIOs

available for other uses.

Note 10. GPIOH_IN_EN (GPIO Offset A0h) and GPIOH_IN_AUX1_SEL (GPIO Offset B4h) are enabled.

Note 11. Reset default.

Note 12. If the GPIO28 function is desired, the power button functionality in the PMC must be disabled before the IN_AUX1 function is dis-

abled.

AMD Geode™ CS5536 Companion Device Data Book 49

Signal Definitions 33238G

3.2.8.1 GPIO Functions and Recommended Usage

Functions listed in Table 3-9 are functions that may be

assigned to specific GPIO balls. The “Ball No.” column

gives the ball that must be used if this function is selected,

and the “GPIOx” column gives the GPIO that the function is

associated with.

Table 3-9. GPIOx Available Functions Descriptions

Function Name

Ball

No. GPIO[x] Type Description

32KHZ C8 GPIO27 O 32 KHz Clock. When invoked, this ball produces a buffered output

of the 32 KHz clock provided on KHZ32_XCI and KHZ32_XCO

(balls A4 and B3, respectively).

This option is invoked by selecting the OUT_AUX2 option of

GPIO27. Note that since GPIO27 is in the Standby power domain,

the 32 KHz clock output will continue in Sleep and Standby states.

AC_BEEP K3 GPIO1 O Legacy PC/AT Speaker Beep. Connect to codec’s PC_BEEP.

DDC_SCL E1 GPIO3 I/O DDC Serial Clock. This is a “recommended use” for GPIO3,

because this is one of the few GPIOs that have a high drive capac-

ity, open-drain output. The serial clock function must be imple-

mented in software to support DDC monitors. There is no

dedicated DDC clock function within the CS5536.

DDC_SDA E2 GPIO4 I/O DDC Serial Data. This is a “recommended use” for GPIO4,

because this is one of the few GPIOs that have a high drive capac-

ity, open-drain output. The serial data function must be imple-

mented in software to support DDC monitors. There is no

dedicated DDC data function within the CS5536.

LOW_BAT# A9 GPIO25 I Low Battery Detect. This is a “recommended use” for GPIO25 in

battery-powered systems. It is invoked by setting GPIO25 to the

IN_AUX1 mode. The signal is intended to be driven low by an

external circuit when the battery voltage falls below a preset value

(determined by the external circuit). It could be used to generate a

PME (interrupt) - connected to LowBat function in the Power Man-

agement Controller that would then de-assert WORKING and

WORK_AUX, if no software action is taken within a programmable

time.

MFGPT0_C1 D3 GPIO5 O Multi-Function General Purpose Counter #0 - Compare 1 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 1 registers.

MFGPT0_C2 K3 GPIO1 O Multi-Function General Purpose Counter #0 - Compare 2 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 2 registers.

MFGPT0_RS D2 GPIO6 I Multi-Function General Purpose Counter #0 - Restart. An input

to the counter that causes it to be reset to initial conditions and

then to resume counting.

MFGPT1_C1 D2 GPIO6 O Multi-Function General Purpose Counter #1 - Compare 1 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 1 registers.

MFGPT1_C2 A1 GPIO11 O Multi-Function General Purpose Counter #1 - Compare 2 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 2 registers.

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MFGPT1_RS D3 GPIO5 I Multi-Function General Purpose Counter #1 - Restart. An input

to the counter that causes it to be reset to initial conditions and

then to resume counting.

MFGPT2_C1 C2 GPIO7 O Multi-Function General Purpose Counter #2 - Compare 1 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 1 registers.

MFGPT2_C2 D2 GPIO6 O Multi-Function General Purpose Counter #2 - Compare 2 Out.

Output from the counter that, when asserted, indicates the counter

has reached the conditions set up in the counter’s Compare 2

registers.

MFGPT2_RS G2 GPIO21 I Multi-Function General Purpose Counter #2 - Restart. An input

to the counter that causes it to be reset to initial conditions and

then to resume counting.

MFGPT7_C1 C8 GPIO27 O Multi-Function General Purpose Counter #7 - Compare 1 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 1 registers.

MFGPT7_C2 A9 GPIO25 O Multi-Function General Purpose Counter #7 - Compare 2 Out.

An output from the counter that, when asserted, indicates the

counter has reached the conditions set up in the counter’s

Compare 2 registers.

MFGPT7_RS B7 GPIO26 I Multi-Function General Purpose Counter #7 - Restart. An input

to the counter that causes it to be reset to initial conditions and

then to resume counting.

PCI_INTA# R2 GPIO0 I PCI Interrupt A. This is a “recommended use” for GPIO0,

because this GPIO has a PCI-compatible output type.

PCI_INTB# C2 GPIO7 I PCI Interrupt B. This is a “recommended use” for GPIO7,

because this GPIO has a PCI-compatible output type.

PME# B7 GPIO26 I Power Management Event. This is a “recommended use” for

GPIO26. By mapping this GPIO (or any other) to the PME# func-

tion, the CS5536 may be awakened from a Sleep state when the

mapped ball (in the recommended case, ball B7) is pulled low.

Table 3-9. GPIOx Available Functions Descriptions (Continued)

Function Name

Ball

No. GPIO[x] Type Description

AMD Geode™ CS5536 Companion Device Data Book 51

Signal Definitions 33238G

PWR_BUT# A8 GPIO28 I Power Button. This GPIO can be mapped to the PMC “button-

push” event, that may be used to implement the power ON and the

four-second-delay power OFF functions. Note that GPIO28 comes

up in the IN_AUX1 mode after reset, enabling this feature.

Any power button change on this input must be at least two

KHZ32_XCI edges (approximately 62 µs) in duration to be cor-

rectly detected. If spurious transitions smaller than this are possi-

ble, then use on-chip GPIO input filter function to insure proper

operation. Additionally, the rise or fall time on this input must be

less than 10 µs. If transition times longer than this are possible,

then use the on-chip GPIO input filter function to insure proper

operation.

From the first power-up of the Standby power domain under which

no filter is enabled, spurious transitions on the first high-to-low

power button push are acceptable as long as the input is eventu-

ally low at least two KHZ32_XCI edges. Additionally, transition

times as slow as 1 ms are acceptable for the first push. Note that

these relaxed requirements work because this input is effectively a

“don’t care” at the hardware level after the first power-up until soft-

ware enables use of the power button. Before enabling use, the

software can setup the GPIO filter or other functions as needed.

Skip feature: This input may be tied to ground in order for the sys-

tem to come on immediately when Standby and Working power

are available. Specifically, systems that do not incorporate a power

button should tie this input to ground. See Section 7.6 "Skip

Parameter" on page 605 for more information on the Skip feature.

One side effect of the Skip feature is that the platform design must

insure that this input is not low when Standby power is applied if

the Skip feature is not desired. Specifically, systems that do incor-

porate use of a power button must insure that this input ramps to a

high no more than 1 µs behind VIO_VSB ramp-up. Failure to quickly

establish a high on this input during power-up could result in a

spurious Skip.

AC_S_IN2 J3 GPIO12 I Audio Controller Serial Data Input 2. This input receives serial

data from a second codec. This data stream contains both control

data and ADC audio data. This input data is sampled on the falling

edge of AC_CLK. If the codec’s Ready bit is set in this stream (slot

0, bit 15), then it is functionally ORed with AC_SDATA_IN1. Con-

nect to second codec’s serial data output.

SLP_CLK_EN# A1 GPIO11 O Sleep Clock Enable. This signal is a control that is intended to be

connected to the external system clock generator chip. The

intended use is, when high, the clock generator runs; when low,

the clock generator turns off. From reset, a pull-up makes this

GPIO high. The active state of this signal indicates that the

CS5536 is in the Sleep state.

SLEEP_BUT F2 GPIO13 I Sleep Button. This GPIO can be mapped to a PME “button-push”

type event and used to request the system software to put the sys-

tem to Sleep.

Table 3-9. GPIOx Available Functions Descriptions (Continued)

Function Name

Ball

No. GPIO[x] Type Description

52 AMD Geode™ CS5536 Companion Device Data Book

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33238G

SLEEP_X C2 GPIO7 O Sleep X. This general purpose power control output becomes

active as the CS5536 enters and exits various power management

modes. It may be used by external devices to control their power

states synchronous with power state changes in the CS5536. It

may be configured as active high or active low.

SLEEP_Y J3 GPIO12 O Sleep Y. This general purpose power control output becomes

active as the CS5536 enters and exits various power management

modes. It may be used by external devices to control their power

states synchronous with power state changes in the CS5536. It

may be configured as active high or active low.

SMB_CLK_IN G3 GPIO14 I SMB Clock In / SMB Clock Out. This is the clock for the SMB. In

order to use it properly, the associated GPIO (GPIO14) should be

set to IN_AUX1 and OUT_AUX1 simultaneously. The SMB con-

troller determines the direction (in or out) of the associated ball.

SMB_CLK_OUT O

SMB_DATA_IN F1 GPIO15 I SMB Data In / SMB Data Out. This is the data line for the SMB. In

order to use it properly, the associated GPIO (GPIO15) should be

set to IN_AUX1 and OUT_AUX1 simultaneously. The SMB con-

troller determines the direction (in or out) of the associated ball.

SMB_DATA_OUT O

THRM_ALRM# C3 GPIO10 I Thermal Alarm. When connected to an external thermal monitor,

this input can act as a thermal fail-safe to shut down power by sig-

nalling the power management controller to de-assert WORKING

and WORK_AUX. Set GPIO10 to the IN_AUX1 mode to enable

this feature.

IDE_IRQ0 B12 GPIO2 I IDE Interrupt. Indicates the external IDE device has completed

the DMA operation.

UART1_IR_TX E3 GPIO8 O UART1 Infrared Transmit. This signal is the data output (TX)

from the infrared mode of UART1. It is available when GPIO8 is

switched to the OUT_AUX2 mode.

UART1_RX D1 GPIO9 I UART1 Receive or UART1 Infrared Receive. This signal is the

data input (RX) to the UART1. It acts as the input in both IR and

conventional modes of UART1. It is available when GPIO9 is

switched to the IN_AUX1 mode.

UART1_IR_RX I

UART1_TX E3 GPIO8 O UART1 Transmit. This signal is the data output (TX) from the con-

ventional mode of UART1. It is available when GPIO8 is switched

to the OUT_AUX1 mode.

UART2_RX E1 GPIO3 I UART2 Receive. This signal is the data input (RX) to the UART2.

It acts as the input of UART2. It is available when GPIO3 is

switched to the IN_AUX1 mode.

UART2_TX E2 GPIO4 O UART2 Transmit. This signal is the data output (TX) from the con-

ventional mode of UART2. It is available when GPIO4 is switched

to the OUT_AUX1 mode.

WORK_AUX C9 GPIO24 O Working Au xiliary. When the system supports ACPI S3 (Save-to-

RAM), this output is intended to be used to control external power

sources to all devices except memory (which is intended to be

controlled by WORKING). WORK_AUX de-asserts in synchronism

with WORKING. When WORK_AUX is used for Save-to-RAM

(ACPI S3), initial state is GPIO24 input. This can cause power turn

on issues. An external blocking circuit must be used to prevent

WORK_AUX from incorrectly causing power application at initial

application of the standby voltages.

Table 3-9. GPIOx Available Functions Descriptions (Continued)

Function Name

Ball

No. GPIO[x] Type Description

AMD Geode™ CS5536 Companion Device Data Book 53

Signal Definitions 33238G

3.2.9 Debug and Manufacturing Test Interface

Signal Name Ball No. Type Description

TCK N2 I JTAG Test Clock.

TMS N3 I JTAG Test Mode Select.

TDI P1 I JTAG Test Data In.

TDO P2 O, TS JTAG Test Data Out. From reset, this output is in TRI-STATE mode. It

is only enabled and driven when commanded to output or pass-

through data per JTAG standards.

T_DEBUG_IN M2 I Test Debug Input. Input to the GeodeLink Control Processor (GLCP)

from the AMD Geode LX processor.

T_DEBUG_OUT M3 O Test Debug Out. Output from the GeodeLink Control Processor

(GLCP) to the AMD Geode LX processor.

LVD_TEST B9 O Low Voltage Detect Test. Manufacturing test only. No operational use.

Make no connection.

TEST_MODE A6 I Test Mode. Manufacturing test only. No operational use. Tie low.

FUNC_TEST F3 I Functional Test. Manufacturing test only. No operational use. Tie low.

USB_PTEST G15 I/O USB PHY Test. Manufacturing test only. No operational use. Leave it

open (unconnected).

3.2.10 Power, Ground, and No Connects

Signal Name

(Note 1) Ball No. Type Description

VCORE D8, D10, H4,

K4, P8, P10

PWR Core Power Working Connection (Total of 6).

VCORE_VSB A7 PWR Core Power Standby Connection.

VIO D4, D6, D9,

D12, F4, M4,

P4, P6, P9,

P12

PWR I/O Power Connection (Total of 10).

VIO_VSB B6 PWR I/O Power Standby Connection.

VSS D5, D7, D11,

D13, E4, G4,

J4, L4, N4,

P5, P7, P11,

P13

GND Ground Connection (Total of 13).

NC A2, A16, B1,

B2, B4, B5,

C4, C11,

F16, J16,

J17, L15,

M16, M17,

R3, R9, T2,

U2, U15,

U16, U17

--- No Connection (Total of 21). These lines must be left disconnected.

Connecting any or these lines to a pull-up/down resistor, an active sig-

nal, power, or ground could cause unexpected results and possible

malfunctions.

Note 1. For module specific power and ground signals see:

Section 3.2.1 "System Interface Signals" on page 36.

Section 3.2.4 "USB Interface" on page 43.

54 AMD Geode™ CS5536 Companion Device Data Book

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Global Concepts and Features 33238G

4.0Global Concepts and Features

4.1 GeodeLink™ Architecture Overview

The information in this section provides a basic under-

standing of the architecture used to internally connect

GeodeLink™ devices. The actual existence of architecture

is generally invisible to the user and the system program-

mer. AMD Core BIOS software provides all GeodeLink ini-

tialization and support, including related Model Specific

Registers (MSRs). Additionally, this software provides a

Virtual PCI Configuration Space that abstracts the architec-

ture to industry standard interfaces. From this interface, all

GeodeLink Devices appear in one PCI multi-function con-

figuration space header on the external PCI bus.

4.1.1 Introduction

This component is based on the GeodeLink packet archi-

tecture. It consists of a set of GeodeLink Devices and a

GeodeLink Control Processor (GLCP) connected through

the GeodeLink Interface Unit (GLIU).

A simplified view of a GLIU connected with three generic

GeodeLink Devices is illustrated in Figure 4-1. The follow-

ing points are relevant:

•All outputs from a GeodeLink Device to the GLIU are

registered.

•All outputs from the GLIU to a GeodeLink Device are

registered. Furthermore, there are dedicated output

registers for each GeodeLink Device.

•GeodeLink Device inputs from the GLIU need not be

registered, but they are buffered at the interface.

•All connections between the GeodeLink Devices and

GLIU are dedicated point-to-point connections with one

source and one load. There are no buses in TRI-STATE

mode.

•The GLIU itself is a GeodeLink Device and is always

Port 0.

Figure 4-1. Simplified GLIU with Generic GeodeLink™ Devices

RO RO ROHS HSHS DODODO

GeodeLink™ Device 1 GeodeLink™ Device 2 GeodeLink™ Device 3

P2D ARB Data

Mux GLIU RI RI RI DIDIDI

RO - Request Out

DO - Data Out RI - Request In

DI - Data In HS - Handshake

P2D - Physical to Device Descriptors ARB - Arbiter

56 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

The GLIU implements the “bus”. Transactions between

GeodeLink Devices and the GLIU are conducted with pack-

ets. The GLIU accepts request packets from masters and

routes them to slaves. Similarly, slave response packets

are routed back to the master. The bus is non-blocking.

Several requests can be pending, but order is guaranteed.

Broadcasts are not allowed. All packets have one source

and one destination.

4.1.2 Routing

The Physical to Device (P2D) descriptors control the rout-

ing of the packets. The descriptors are initialized by soft-

ware at system setup. They establish the address map to

be used by the system. They associate a memory or I/O

address range with a GLIU port.

When a request packet arrives from a Request Out (RO)

port, the address and other attributes in the packet are

used to look up the destination port. If the port Request In

(RI) is available, the request is passed. If there are multiple

requests, priorities are used to establish which requestor

and destination port utilize the transfer cycle. A transfer

from an RO to an RI takes one clock edge.

4.1.3 Response Packets

Earlier in this section, it was indicated that an RO can be

used to present a write data packet or a read response

packet. The use and need of a read response packet for a

read request is obvious. However, there is also an optional

write response packet. This tells the requestor that the

write has completed. This is used to hold a processor I/O

write instruction until the response is received, that is, I/O

writes are never posted. Memory writes are always posted.

The response packet is also used to generate Synchro-

nous System Management Interrupts (SSMIs). System

Management Mode (SMM) is used for hardware emulation

and other traps. An SSMI can be generated by a

GeodeLink Device or via special GLIU descriptors. When

the response arrives back at the processor, interface cir-

cuits generate an SMI to invoke the SMM software. Lastly,

all response packets contain an exception flag that can be

set to indicate an error.

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Global Concepts and Features 33238G

4.1.4 ASMI and Error

Two additional signals are needed to complete this

GeodeLink architecture overview: Asynchronous System

Management Interrupt (ASMI) and Error. Each GeodeLink

Device outputs these ASMI and Error signals.

An ASMI is much like a legacy interrupt, except it invokes

the SMM handler. As the name suggests, an ASMI is an

asynchronous event, while an SSMI is synchronous to the

instruction that generated it.

The Error signal simply indicates some type of unexpected

error has occurred. A device asserts this signal. In a nor-

mal operating system, this would not be asserted. For

example, a disk read error or ethernet network error would

be signaled using normal GeodeLink packet mechanisms.

This signal is reserved for the truly unexpected.

Each GeodeLink Device has mechanisms for enabling and

mapping multiple internal sources down to these singular

outputs. The mechanism consists of the logical “OR” of all

enabled sources. The GLIU receives the ASMI and Error

pair from each GeodeLink Device. It has the same “OR”

and enable mechanism that finally results in a single ASMI

and Error pair for the whole component (see Figure 4-2).

The ASMI is routed to the processor, while the Error is

routed to the GLCP. Within the GLCP, the Error signal can

be mapped into an ASMI for routing back into the GLIU.

Figure 4-2. GeodeLink™ Architecture ASMI and Error Routing

ASMI

& Error

ASMI

& Error

ASMI

& Error

ASMI

& Error

ASMI

& Error

ASMI

& Error

ASMI

& Error

GLCP

USB

ACC

IDE

GLPCI_SB

GLIU ASMI & Error AMD Geode™ CS5536 Companion Device Error

to GLCP Debug or conversion to ASM

AMD Geode™ CS5536 Companion Device ASMI

EnableEnable

OROR

to AMD Geode™ LX Processor

58 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

4.1.5 Topology

The connection of the GLIU to the seven GeodeLink

Devices of the AMD Geode™ CS5536 companion device

is illustrated in Figure 4-3. Note the port number of the

GeodeLink Device. By design convention, the GLIU is

always Port 0. Part of the Physical to Device (P2D) descrip-

tor is a port number. When there is a hit on the descriptor

address, the port number indicates which GeodeLink

Device to route the packet to. If there is no hit, then the

packet is routed to the default port. For the CS5536 com-

panion device, the default is always Port 4, that is, the

Diverse Device (DD).

Figure 4-3. AMD Geode™ CS5536 Companion Device GeodeLink™ Architecture Topology

Port 7

Port 3

USB

Req In

Data In

Req Out

Data Out

Diag

GLPCI_SB

Req In

Data In

Req Out

Data Out

Diag

IDE

Req In

Data In

Req Out

Data Out

Diag

Req In

Data In

Req Out

Data Out

Diag

GLCP

Req In

Data In

Req Out

Data Out

Diag

UNUSED

Req In

Data In

Req Out

Data Out

Diag

ACC

Req In

Data In

Req Out

Data Out

Diag

GLIU

Port 4 Port 5

Port 6

Port 0

Port 2

Port 1

AMD Geode™ CS5536 Companion Device Data Book 59

Global Concepts and Features 33238G

4.1.6 Address Spaces and MSRs

The GLIU and GeodeLink Devices support the traditional

memory and I/O spaces. The memory space supports a

traditional 32-bit byte address with associated byte

enables. The I/O space is a 20-bit byte address with byte

enables. I/O registers can be 8, 16, or 32 bits. The GLIU

has both memory and I/O P2Ds for routing.

In addition to the above spaces, there is a Model Specific

ogy. As introduced in the previous section, the GLIU has

eight ports with Port 0 assigned to the GLIU. An MSR

“address” is relative to the device making a request to it

and the topology between the requestor and the MSR.

Thus, for the AMD Geode LX processor to address an

MSR in the CS5536 companion device, it specifies a series

of ports that must be traversed to get there. Once a specific

device port is identified, additional address bits are avail-

able to select a specific MSR within a given device.

MSR space is functionally similar to PCI configuration

space. At boot time system initialization, the Core BIOS

(see Section 4.1 "GeodeLink™ Architecture Overview" on

page 55) traverses the topology of the system to determine

what is present. By convention, the first MSR at each port

is an ID register that indicates a specific device. Once the

Core BIOS knows what is present, it assigns devices to

specific locations in the appropriate memory or I/O address

space using MSRs. Generally, MSRs are used to configure

and set up GeodeLink Devices, but are not used for ongo-

ing operations.

The “assignment” MSRs are located in the GLIUs as

“descriptors”. The “assignment descriptor” basically says:

“route a request packet containing address X to port Y”.

Port Y can be the final device or another GLIU. This second

GLIU must have assignments to route address X to port Z.

This process continues until the final device port is speci-

fied. In addition to the “positive” address decode above,

each GLIU has a subtractive port that takes all addresses

not assigned to a specific port. There is always a default

subtractive port path to the boot ROM to allow the central

processor to start executing code from time zero. Thus,

from system reset, there is a default memory address path

that allows the first processor instruction fetch to:

1) Proceed down through the two GLIUs of the

AMD Geode LX processor;

2) cross the PCI bus to the CS5536 companion device;

3) proceed down through the CS5536 companion device

GLIU to the default port connected to the DD; and

4) access the boot device connected to the DD.

4.1.7 Special Cycles and BIZZARO Flag

The BIZZARO flag is used to indicate special cycles and

exceptions to normal packet operation. All special cycles

traverse the GLIU system as I/O packets with the BIZZARO

flag set. The special cycles are:

1) Interrupt Acknowledge: I/O read from address zero.

2) Shutdown: I/O write to address zero.

3) Halt: I/O write to address one.

60 AMD Geode™ CS5536 Companion Device Data Book

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33238G

4.2 MSR Addressing

An MSR address consists of the fields shown in Table 4-1.

When a GLIU receives an MSR packet, it routes the packet

to the port specified in Field 0 but shifts address bits

[31:14] to the left by three bits and replaces bits [16:14]

with zero. Thus, Field 1 is moved to Field 0, Field 2 is

moved to Field 1, etc. The address field always remains

unchanged and selects one 64-bit MSR per address value,

that is, the address value 0 accesses one 64-bit register,

the address value 1 accesses one 64-bit register, the

address value 2 accesses one 64-bit register, etc. There

are no MSR byte enables. All 64 bits are always written and

read.

Many CS5536 companion device MSRs are only 32 bits in

physical size. In these cases, interface logic discards the

upper 32 bits on write, and pads the upper 32 bits on

reads. Read padding is undefined. Lastly, CS5536

GeodeLink Devices only decode enough bits of the

address to select one of N MSRs, where N is the total num-

ber of MSRs in the device. For example, if a GeodeLink

Device has only 16 MSRs, then the addresses 0x2001,

0x0201, 0x0021, and 0x0x0001 all access MSR number 1,

while the addresses 0x200F, 0x020F, 0x002F, and

0x0x000F all access MSR number 15.

To access a given GeodeLink Device, use Table 4-2. Note

the target device addresses:

GLPCI_SB 5100xxxxh

GLIU 5101xxxxh

USB 5120xxxxh

IDE 5130xxxxh

DD 5140xxxxh

ACC 5150xxxxh

GLCP 5170xxxxh

The xxxx portion refers to the MSR addresses as they

appear within Section 6.0 "Register Descriptions" on page

193. To form a complete MSR address, “OR” an address

provided in a register description section with the appropri-

ate address above.

Table 4-1. MSR Routing Conventions

Routing

Field 0

Routing

Field 1

Routing

Field 2

Routing

Field 3

Routing

Field 4

Routing

Field 5

Address

Field

Bits

[31:29]

Bits

[28:26]

Bits

[25:23]

Bits

[22:20]

Bits

[19:17]

Bits

[16:14]

Bits

[13:0]

Table 4-2. MSR Addresses from AMD Geode™ LX Processor

Routing

Field 0

Routing

Field 1

Routing

Field 2

Routing

Field 3

Routing

Field 4

Routing

Field 5

GeodeLink™

Device

Target Name

& Address Comment

Bits

[31:29]

Bits

[28:26]

Bits

[25:23]

Bits

[22:20]

Bits

[19:17]

Bits

[16:14]

These bits are shifted off to the

left and never enter the CS5536.

These bits are shifted into posi-

tions [31:23] by the time they

reach the CS5536. Bits in posi-

tions [22:14] are always 0 after

shifting.

010 100 010 000 000 000 GLPCI_SB

5100xxxxh

This all-zero convention indi-

cates to the GLPCI_SB that the

MSR packet coming across the

PCI bus is actually for the

GLCPI_SB.

010 100 010 000 Non-zero value GLIU

5101xxxxh

This non-zero convention indi-

cates to the GLPCI_SB that the

MSR packet coming across the

PCI bus should be forwarded to

the GLIU. The GLIU only looks

at [22:20] and hence, keeps the

packet.

AMD Geode™ CS5536 Companion Device Data Book 61

Global Concepts and Features 33238G

010 100 010 001 Any value Illegal The GLIU can not send any

packets back to the port it

came from.

010 100 010 010 Any value USB

5120xxxxh

010 100 010 011 Any value IDE

5130xxxxh

010 100 010 100 Any value DD

5140xxxxh

010 100 010 101 Any value ACC

5150xxxxh

010 100 010 110 Any value Not Used

5160xxxxh

The GLIU port #6 is not con-

nected.

010 100 010 111 Any value GLCP

5170xxxxh

Table 4-2. MSR Addresses from AMD Geode™ LX Processor (Continued)

Routing

Field 0

Routing

Field 1

Routing

Field 2

Routing

Field 3

Routing

Field 4

Routing

Field 5

GeodeLink™

Device

Target Name

& Address Comment

Bits

[31:29]

Bits

[28:26]

Bits

[25:23]

Bits

[22:20]

Bits

[19:17]

Bits

[16:14]

These bits are shifted off to the

left and never enter the CS5536.

These bits are shifted into posi-

tions [31:23] by the time they

reach the CS5536. Bits in posi-

tions [22:14] are always 0 after

shifting.

62 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

4.3 Typical GeodeLink™ Device

A typical or “generic” CS5536 companion device

GeodeLink Device is illustrated in Figure 4-4 along with

internal and external connections. The GeodeLink Device

consists of the Native Block, GeodeLink Adapter, MSRs,

and Clock Control Units (CCU). Each of these is discussed

in the following paragraphs.

Before going into the blocks of the typical device, it should

be noted that the following modules in the CS5536 com-

panion device follow this model very closely:

•AC97 Controller (ACC)

•IDE Controller (IDE)

•Diverse Device (DD)

Specifically, they all use the GeodeLink Adapter.

The Native Block performs the “useful” work for the device.

For example, in a serial port device, the transmit parallel to

serial shift register is located in this block. The Native Block

connects to the outside world, that is, external devices, via

the I/O cells and pads. The Native Block contains registers

that are manipulated by software to perform the “work”.

These are operational registers that are typically manipu-

lated by device drivers. The Native Blocks are covered in

detail in the corresponding module’s register descriptions.

The GeodeLink Adapter sits between the GLIU and the

Local bus. The Local bus is a traditional address/data bus

supporting GeodeLink Adapter to Native Block transactions

(slave transactions) and Native Block to GeodeLink

Adapter transactions (master transactions). However, it is a

single transaction bus in that any given slave or master

transaction runs to completion before another transaction

can start. This is compatible with the Native Blocks listed

above (i.e., ACC, IDE, and DD), which are all single trans-

action devices. As suggested by Figure 4-4, the GeodeLink

Adapter contains no registers and is strictly speaking, just

a bridge.

The MSRs are conceptually separate from the Native Block

and GeodeLink Adapter and generally provide overall

GeodeLink Device configuration and control. In most

designs they are physically separated as shown. There are

six standard MSRs that are detailed in Section 4.7 "Stan-

dard GeodeLink™ Device MSRs" on page 74. All

GeodeLink Devices have these standard MSRs.

GeodeLink Devices may also incorporate additional MSRs

as appropriate.

On the upper right of the figure, the connections between

the GeodeLink Adapter and GLIU are illustrated. All of

these signals were covered previously in Section 4.1

"GeodeLink™ Architecture Overview" on page 55.

The CCUs are a key component in the Active Hardware

Clock Gating (AHCG) infrastructure. They provide the

mechanism for turning off clocks to sections of logic that

are Not Busy. Furthermore, they take an asynchronous glo-

bal reset signal and synchronize it to the applicable clock

domain.

Figure 4-4. Typical AMD Geode™ CS5536 Companion Device GeodeLink™ Device

MSRs

Native

Block

Native

Block

Registers

GeodeLink™

Adapter

GLIU

MSRs

Reg In

Data In

Reg Out

Data Out

Diag

ASMI

ERR

Other Device

CCU

Local

Bus

Interface

Busy Signals

to GLCP

GeodeLink™ Device

Side-band signals to other Native Blocks

External Device Interface

I/O

Cells &

Pads

GeodeLink™ Device Clock

Local Bus Clock

Native Block Clock

Global Internal Reset

Connections

AMD Geode™ CS5536 Companion Device Data Book 63

Global Concepts and Features 33238G

4.4 Clock Considerations

4.4.1 Clock Domain Definitions

Table 4-3 lists the clock sources and domains for the CS5536 companion device.

Table 4-3. Clock Sources and Clock Domains

Component Pin Domain Name Description

MHZ66_CLK ATAC_LB IDE Local bus and IDE controller core

Inverted MHZ66_CLK

(Note 1)

Note 1. The MHZ66_CLK is first inverted and then fed to all these domains.

GLIU_GLD GLIU GeodeLink™ Device interface and related logic

GLIU_STAT GLIU Statistics Counters

GLPCI_GLD GLPCI_SB GeodeLink Device interface and related logic

USB_GLD USB Controller GeodeLink Device interface and related logic

ATAC_GLD IDE GeodeLink Device interface and related logic

DD_GLD DD GeodeLink Device interface and related logic

ACC_GLD ACC GeodeLink Device interface and related logic

GLCP_GLD GLCP GeodeLink Device interface and related logic

OHC_HCLK USB OHC controller 66 MHz GeodeLink clock

EHC_HCLK USB EHC controller 66 MHz GeodeLink clock

UDC_HCLK USB device controller 66 MHz GeodeLink clock

OTC_HCLK USB Option controller clock

MHZ66_CLK divided by

two (Note 2)

Note 2. Each domain receives the referenced clock and performs the divide just before the CCU.

ACC_LB ACC Local bus interface and related logic

PCI_CLK GLPCI_TRNA GLPCI_SBtransaction processing

GLPCI_INTF GLPCI_SB interface to PCI bus

GLCP_PCI GLCP PCI related logic

MHZ48_CLK USB_COR48 USB controller core logic

MHZ48_CLK divided by

two (Note 2)

SMB_COR SMB Controller core logic

UART1_COR UART1 core logic

UART2_COR UART2 core logic

LPC_CLK DD_LB DD Local bus interface and related logic; Includes PIC

LPC_COR LPC Controller core logic

PIT_COR PIT core logic

DMA_COR 8237 DMA core logic

AC_CLK ACC_COR ACC core logic

MHZ14_CLK (Note 3)

Note 3. This clock differs from other clocks in this table in that this clock does not utilize a CCU nor is it subject to GLCP control or power

management control.

MFGPT_COR_14M MFGPT core logic14 MHz clock

PMC_SLP Power Management Controller Sleep logic

PIT_REF Programmable Interval Timer reference clock

KHZ32_XCI (Note 3) RTC_COR RTC core logic

MFGPT_COR_32K MFGPT core logic 32 KHz clock

MFGPT_COR_32K_S MFGPT 32 KHz clock source; Standby power domain

PMC_STB PMC Standby logic; Standby power domain

GPIO_COR GPIO core logic

GPIO_COR_S GPIO core logic; Standby power domain

TCK (Note 3) TAP_CNTRL JTAG TAP Controller clock source

(Note 4)

Note 4. This logic does not have a fixed clock source. During debug it is switched to the clock domain of interest. It does have a CCU.

GLCP_DBG GLCP debug logic

64 AMD Geode™ CS5536 Companion Device Data Book

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33238G

4.4.2 Clock Controls and Setup

Each of the clock domains listed in Table 4-3 on page 63 is

subject to various GLCP controls and status registers

except those with “Note 3”. The following registers, which

control those clocks, and a brief description of each is pro-

vided:

• GLCP Clock Active (GLCP_CLKACTIVE), MSR

51700011h: A 1 indicates the corresponding clock is

active. This is a read only register.

• GLCP Clock Control (GLCP_CLKOFF), MSR

51700010h: A 1 indicates the corresponding clock is to

be disabled immediately and unconditionally. Not

normally used operationally. Debug only.

• GLCP Clock Mask for Debug Clock Stop Action

(GLCP_CLKDISABLE), MSR 51700012h: A 1 indicates

the corresponding clock is to be disabled by debug logic

via a debug event or trigger. Not normally used opera-

tionally. Debug only.

• GLCP Clock Active Mask for Suspend Acknowledge

(GLCP_CLK4ACK), MSR 51700013h: A 1 indicates the

corresponding clock is to be monitored during a power

management Sleep operation. When all the clocks with

associated 1s go inactive, the GLCP sends a Sleep

Acknowledge to the Power Management Controller. This

the CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh[1]) to be 0.

• GLCP Clock Mask for Sleep Request

(GLCP_PMCLKDISABLE), MSR 51700009h: A 1 indi-

cates the corresponding clock is to be disabled uncondi-

tionally during a power management Sleep operation.

Clocks are disabled when the GLCP completes all of its

Sleep Request operations and sends a Sleep Acknowl-

edge to the Power Management Controller.

All of the registers above have the same layout, where

each bit is associated with a clock domain. The layout and

recommended operating values for the registers is pro-

vided in Table 6-76 "Clock Mapping / Operational Settings"

on page 566.

4.4.2.1 Additional Setup Operations

• GLCP Debug Clock Control (GLCP_DBGCLKCTL),

MSR 51700016h: Set all bits to 0. This turns off all

clocks to debug features; not needed during normal

operation.

• GLCP Global Power Management Control

(GLCP_GLB_PM), MSR 5170000Bh: Set all bits to 0.

This disables the use of the fixed delay in

GLCP_CLK_DIS_DELAY and enables the use of

GLCP_CLK4ACK.

• GLCP Clock Disable Delay Value

(GLCP_CLK_DIS_DELAY), MSR 51700008h: Set all

bits to 0. Since use of this register is disabled by setting

all GLCP_DBGCLKCTL bits to 0, the actual value of this

If use of GLCP_CLK_DIS_DELAY is desired, set the

CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh[1] = 1). This will disable the use of

GLCP_CLK4ACK and shut off the clocks in

GLCP_PMCLKDISABLE after the

GLCP_CLK_DIS_DELAY expires. This delay is

measured in PCI clock edges.

4.5 Reset Considerations

The elements that affect “reset” within the CS5536 com-

panion device are illustrated in Figure 4-5 on page 66. The

following points are significant:

•Signals denoted in upper case (i.e., all capitals) are

external pins. Signals denoted in lower case are internal

signals.

•There are separate resets for the Working power domain

(RESET_WORK#) and the Standby power domain

(RESET_STAND#).

•All elements in the figure are within the Standby power

domain and operate off the KHZ32_CLK.

•The TAP Controller is in the Working power domain, but

it may be reset separately from the other Working

domain logic.

•Any time the CS5536 companion device is in the

Standby state, the Working power domain is uncondi-

tionally and immediately driven into reset.

•Any faulted event or external reset input forces the

CS5536 companion device into the Standby state.

•External reset (RESET_OUT#) is always asserted

immediately with internal working domain reset, but is

de-asserted subject to a programmable delay.

RESET_OUT# asserts without any clocks but requires

the KHZ32_CLK for the delay and the PCI_CLK to de-

assert.

•IDE_RESET# is always asserted immediately with

internal working domain reset and de-asserts when the

IDE controller comes out of reset, that is, within a few

MHZ66_CLK edges of internal reset de-assert.

•LVD monitors VCORE and only asserts

power_good_working when VCORE is within normal

operating range.

•LVD monitors VCORE_VSB and VIO_VSB along with

RESET_STAND#. The assertion of power_good_standy

only occurs when the voltages are within normal oper-

ating range and RESET_STAND# is high (de-asserted).

AMD Geode™ CS5536 Companion Device Data Book 65

Global Concepts and Features 33238G

When power is applied to the CS5536 companion device

from a completely cold start, that is, no Standby or Working

power, both RESET_STAND# and RESET_WORK# are

applied. Alternatively, one or both of the reset inputs may

be tied to Standby I/O power (VIO_VSB), and the LVD circuit

will generate internal Power Good Working and internal

Power Good Standby. Assuming the LVD circuit is enabled

(LVD_EN# pin tied low), Power Good Standby will assert

until proper Standby voltages have been achieved and

RESET_STAND# has been de-asserted.

RESET_OUT# is de-asserted synchronous with the low-to-

high edge of PCI_CLK. The de-assertion is delayed from

internal_reset using a counter in the Power Management

Controller. This counter is driven by the 32 KHz clock and

is located in the Standby power domain. The value of the

counter is programmable but defaults to 0x0_0100 (256

edges). 31.25 µs per edge times 256 equals an 8 ms delay.

Note this counter default is established by

RESET_STAND# and is not effected by RESET_WORK#.

Therefore, the delay value may be changed and then the

system can be reset with the new value.

Note the special consideration for TAP Controller reset.

When boundary scan is being performed, internal compo-

nent operation is not possible due to the scanning signals

on the I/Os. Under this condition, it is desirable to hold the

component internals in reset while the boundary scan is

being performed by the TAP Controller. However, under

normal operation, it is desirable to reset the TAP Controller

with the other logic in the Working domain during power

management sequences.

Achieving these dual goals is accomplished as follows:

For boundary scan:

•Assert RESET_STAND#, causing internal

power_good_standby to go low. This causes the

complete component to reset, except for the TAP

Controller. Keep this input held low throughout boundary

scan operations.

•Assert and de-assert RESET_WORK# as needed to

reset the TAP Controller.

For normal operation:

•The internal Power Good Standby will be high, meaning

the TAP Controller reset asserts any time the Standby

state is active or anytime RESET_WORK# is active.

66 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

Figure 4-5. Reset Logic

Faulted

Event

Capture

Power

Manage

Standby

State

Controller

Faulted

Event

Status

& immediately

enter Standby

state

unconditionally

Fail-safe Power Off Alarm

Thermal Alarm

Low Power Alarm

Shutdown Special Cycle

MFGPT Watchdog

DIVIL Bad Packet

GLCP Soft Reset

DIVIL Soft Reset

Working Power Fail

RESET_WORK#

Normal Software Request for Standby state

WORKING

WORK_AUX

Standby State

32kHZ_CLK

De-assert

Delay

PCI_CLK

RESET_OUT#

LVD

(Low

Voltage

Detect)

VCORE

VCORE_VSB

VIO_VSB

RESET_STAND#

IDE

Controller

IDE_RESET#

Internal Reset

to all Working

Domain Logic

except TAP

Controller

Power Good Working

Power Good Standby

(Standby Domain Reset When Low)

TAP Controller Reset

standby_state

AMD Geode™ CS5536 Companion Device Data Book 67

Global Concepts and Features 33238G

4.6 Memory and I/O Map Overview

4.6.1 Introduction

There are several places in the CS5536 companion device

where addresses are decoded and routed:

•Physical PCI Bus. The GLPCI_SB decodes PCI bus

transactions and claims them with a “DEVSEL#” as

appropriate. After claiming a transaction, the GLPCI_SB

converts it to a GLIU request packet. It then passes the

request to the GLIU. It has no routing control or respon-

sibility beyond this point.

•GLIU. The GLIU compares the request addresses

against the descriptor settings. It passes the request to

the port associated with the compare hit. Each port is

connected to a specific GeodeLink Device (see Section

4.1.5 "Topology" on page 58 for port assignment). There

are also specific legacy addresses that receive “special”

routing beyond the standard descriptor routing mecha-

nisms.

•Typical GeodeLink Device. For most GeodeLink

Devices, further decoding is minimal. If a device

contains only MSRs and a single Native Block (register

group) in I/O or memory space, specific bits within the

request packet can be used to easily select between the

two. If a device contains more than one register group, a

Local Base Address Register (LBAR) for each group is

used. Like a PCI Base Address Register (BAR), an

LBAR compare and hit operation is used to select the

desired group.

•Diverse Device. The Diverse Device has the same

decoding responsibilities as a typical GeodeLink Device.

Beyond this programmable LBAR decoding, it has

substantial fixed decoding associated with legacy

addresses.

4.6.2 PCI Bus Decoding

From reset, the GLPCI_SB does not actively decode any

cycle. However, it does subtractively decode all cycles.

From reset, any cycle not positively claimed on the PCI bus

is converted to a GLIU request and passed to the GLIU.

Using appropriate setup registers, the GLPCI_SB can be

programmed to actively decode selected I/O and memory

regions. Other than actively claiming, the “convert” and

“pass” operation is the same.

There are control bits in GLPCI_CTL (MSR 51700010h) to

regulate behavior associated with legacy addresses:

•Bits [12:11]: Legacy I/O Space Active Decode. These

bits control the degree to which the GLPCI_SB actively

claims I/O region 0000h through 03FFh:

— 00: Subtractive – Claim on fourth clock. (Default.)

— 01: Slow – Claim on third clock.

— 10: Medium – Claim on second clock.

•Bit 13: Reject Primary IDE. If this bit is set, the

GLPCI_SB will not actively decode the primary IDE

addresses of 01F0h/01F7h and 03F6h.

•Bit 14: Reject Secondary IDE. If this bit is set, the

GLPCI_SB will not actively decode the secondary IDE

addresses of 0170h/0177h and 0376h.

•Bit 15: Reject DMA High Page Active. If this bit is set, the

GLPCI_SB will not actively decode the I/O range

0480h/048Fh associated with the DMA High Page regis-

ters.

For further details on the GLPCI_CTL register see Section

6.2.2.1 "Global Control (GLPCI_CTRL)" on page 229.

Lastly, there is an “MSR Access Mailbox” located in PCI

Configuration register space. It consists of the following 32-

bit registers:

•MSR Address (PCI Index F4h). Full MSR routing path in

the upper portion plus 14 device address bits in the

lower portion.

•MSR Data Low (PCI Index F8h). Bits [31:0]: When read,

an MSR cycle is generated. The 64-bit read returns the

low 32 bits and saves the upper 32 bits for a read to

“Data High”. A write holds the value written as the

current “Data Low”.

•MSR Data High (PCI Index FCh). Bits [63:32]: Reads

return the upper 32 bits of the last MSR value read.

Writes generate an MSR write cycle using the current

value and the “Data Low” value.

For further details on the MSR Access Mailbox see Section

6.2.3 "PCI Configuration Registers" on page 234.

4.6.3 GLIU Decoding

From reset, the GLIU passes all request packets to the

Diverse Device, except for the legacy primary IDE

addresses (01F0h/01F7h and 03F6h), these are passed to

the IDE device in the IDE controller. There is a GLIU

IOD_SC descriptor to control this primary IDE behavior

and it defaults configured (see Section 6.1.4.2 "IOD Swiss

Cheese Descriptors (GLIU_IOD_SC[x])" on page 220). If

this descriptor is disabled, all requests pass to the Diverse

Device.

Using appropriate MSR setup registers (descriptors), the

GLIU can be programmed to route selected I/O and mem-

ory regions to specific GeodeLink Devices. Any memory or

I/O address that do not hit one of these regions, subtrac-

tively routes to the Diverse Device. Unlike PCI, there is no

performance loss associated with being the subtractive

port.

Operationally, there are four bus masters within the

CS5536 companion device: IDE, ACC, DD, and USB.

These masters only generate requests to access main

memory off the AMD Geode LX processor. Therefore, all

their GLIU requests must be routed to the GLPCI_SB for

presentation to the PCI bus. A set of GLIU P2D_BM

descriptors could be used for this purpose. However, the

CS5536 companion device GLIU is uniquely modified to

68 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

route all requests for the listed masters to the GLPCI_SB

unconditionally. Therefore, GLIU P2D_BM settings do not

affect packet routing from the listed masters. GLIU descrip-

tors are only used to route requests from the GLPCI_SB

and GLCP.

4.6.4 Legacy Keyboard Emulation

In the CS5536 companion device, a USB Controller sup-

ports an Open Host Controller Interface. The USB control

registers are memory mapped. The memory region associ-

ated with these registers is relocatable via standard GLIU

descriptor MSRs starting at an appropriate base address.

The region size is 4 KB (1000h), that is, an offset range of

000h through FFFh. There are four registers called: Hce-

Control, HceInput, HceOutput, and HceStatus. There are

no USB control registers above this region.

Special consideration is given to the legacy keyboard emu-

lation control registers normally associated with the USB

Controller. The keyboard emulation registers are located at

the USB Open Host Controller base address plus 0100h.

The Keyboard Emulation Logic (KEL) hardware is located

in the Diverse Device (DD) module, where it can be closely

coordinated with a possible real keyboard controller in any

of the two locations: in either the USB Controller or on the

LPC bus. This leaves the problem of the control registers

that are physically in the DD, but logically (from the soft-

ware perspective) in the USB Controller.

A descriptor type is incorporated into the CS5536 compan-

ion device to deal with this keyboard issue. It is a variant of

the standard “P2D Base Mask Descriptor” (P2D_BM)

called P2D_BMK (keyboard). A P2D_BMK descriptor does

additional decoding based on Address bit 8. If this bit is

low, the hit directs to the USB port. If this bit is high, the hit

directs to the subtractive port. (see Section 6.1.2.2 "P2D

Base Mask KEL Descriptors (GLIU_P2D_BMK[x])" on

page 204).

4.6.5 GeodeLink™ Device Decoding Except

Diverse Device

Table 4-4 shows the register space map for all CS5536

devices except the Diverse Device. There are no fixed

addresses associated with these devices other than the

MSRs and the legacy IDE I/O addresses as detailed in

Section 4.6.3 "GLIU Decoding" on page 67.

4.6.6 Diverse Device Decoding Except Legacy

I/O

The Diverse Device register space map, except legacy I/O,

is shown in Table 4-5 on page 69.

Table 4-4. AMD Geode™ CS5536 Companion Device Register Space Map Except Diverse Device

Device MSR Space (Note 1) I/O Space Memory Space

GLPCI_SB Standard GeodeLink™ Device MSRs

plus GLPCI_SB setup. All MSRs also

accessible from PCI Configuration space.

None. None.

GLCP Standard GeodeLink™ Device MSRs

plus diagnostic and debug.

None. None.

GLIU Standard GeodeLink™ Device MSRs

plus descriptor setup.

Programmable SSMIs. Programmable SSMIs.

ACC Standard GeodeLink Device MSRs. 16-byte codec interface plus

a 48-byte master interface.

All trap registers removed.

Generates no SSMIs.

The register space can be

here also.

IDE Standard GeodeLink™ Device MSRs

plus timing parameters.

Bus Master LBAR.

Legacy primary addresses.

16-byte master interface.

None.

USB Standard GeodeLink™ Device MSRs

plus base address registers to differential

the Open Host Controller Interface, the

Option Controller, the Enhanced Host

Controller Interface and the Device Con-

troller.

None. 4 KB for each of the four con-

trollers. Keyboard emulation

registers to Diverse Device.

Note 1. See Section 4.7 "Standard GeodeLink™ Device MSRs" on page 74 for register descriptions.

AMD Geode™ CS5536 Companion Device Data Book 69

Global Concepts and Features 33238G

4.6.7 Legacy I/O Decoding

Table 4-6 details the legacy I/O range for 000h through

4FFh. Each I/O location has a read/write (R/W) capability.

Note the following abbreviations:

--- Unknown or can not be determined.

Yes Read and write the register at the indicated

location. No shadow required.

WO Write only. Value written can not be read back.

Reads do not contain any useful information.

RO Read only. Writes have no effect.

Shw The value written to the register can not be read

back via the same I/O location. Read back is

accomplished via a “Shadow” register located

in MSR space.

Shw@ Reads of the location return a constant or

meaningless value.

Shw$ Reads of the location return a status or some

other meaningful information.

Rec Writes to the location are “recorded” and written

to the LPC. Reads to the location return the

recorded value. The LPC is not read.

Table 4-5. Diverse Device Space Map Except Legacy I/O

Device MSR Space (Note 1) I/O Space Memory Space

DD Standard GeodeLink™ Device

MSRs plus:

SMB LBAR, ACPI LBAR,

PM LBAR, GPIO LBAR,

MFGPT LBAR, NAND LBAR,

KEL LBAR, KEL LBAR,

IRQ Mapper LBAR,

Legacy Controls,

DMA Mappers,

Shadow Registers,

LPC Controls, and

Memory Mask.

NOR Flash address control.

Located by associated LBAR.

Defaults disabled.

008 Bytes SMB,

016 Bytes ACPI,

064 Bytes PM Support,

256 Bytes GPIO and ICFs,

064 Bytes MFGPTs,

016 Bytes NAND Flash, and

032 Bytes IRQ Mapper.

All I/O that does not hit one of the

items above and does not hit a

legacy address, is directed to the

LPC bus.

16-Byte KEL Host Controller reg-

ister set at LBAR. Defaults dis-

abled.

NOR Flash per LBAR.

All other memory accesses are

directed to the LPC bus.

Note 1. See Section 4.7 "Standard GeodeLink™ Device MSRs" on page 74 for register descriptions.

Table 4-6. Legacy I/O: 000h-4FFh

I/O Addr. Function Size R/W Comment

000h Slave DMA Address - Channel 0 8-bit Yes 16-bit values in two transfers.

001h Slave DMA Counter - Channel 0 8-bit Yes 16-bit values in two transfers.

002h Slave DMA Address - Channel 1 8-bit Yes 16-bit values in two transfers.

003h Slave DMA Counter - Channel 1 8-bit Yes 16-bit values in two transfers.

004h Slave DMA Address - Channel 2 8-bit Yes 16-bit values in two transfers.

005h Slave DMA Counter - Channel 2 8-bit Yes 16-bit values in two transfers.

006h Slave DMA Address - Channel 3 8-bit Yes 16-bit values in two transfers.

007h Slave DMA Counter - Channel 3 8-bit Yes 16-bit values in two transfers.

008h Slave DMA Command/Status - Channels [3:0] 8-bit Shw$

009h Slave DMA Request - Channels [3:0] 8-bit WO Reads return value B2h.

00Ah Slave DMA Mask - Channels [3:0] 8-bit Shw@ Reads return value B2h.

00Bh Slave DMA Mode - Channels [3:0] 8-bit Shw@ Reads return value B2h.

00Ch Slave DMA Clear Pointer - Channels [3:0] 8-bit WO Reads return value B2h.

00Dh Slave DMA Reset - Channels [3:0] 8-bit WO Reads return value B2h.

70 AMD Geode™ CS5536 Companion Device Data Book

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00Eh Slave DMA Reset Mask - Channels [3:0] 8-bit Shw@ Reads return value B2h.

00Fh Slave DMA General Mask - Channels [3:0] 8-bit Shw@ Reads return value B2h.

010h-

01Fh

No Specific Usage --- ---

020h PIC Master - Command/Status 8-bit Shw$

021h PIC Master - Command/Status 8-bit Shw$

022h-

03Fh

No Specific Usage --- ---

040h PIT – System Timer 8-bit Shw$

041h PIT – Refresh Timer 8-bit Shw$

042h PIT – Speaker Timer 8-bit Shw$

043h PIT – Control 8-bit Shw$

044h-

05Fh

No Specific Usage --- ---

060h Keyboard/Mouse - Data Port 8-bit Yes If KEL Memory Offset 100h[0] = 1

(EmulationEnable bit).

If MSR 5140001Fh[0] = 1 (SNOOP

bit) and KEL Memory Offset 100h[0]

= 0 (EmulationEnable bit).

061h Port B Control 8-bit Yes

062h-

063h

No Specific Usage --- ---

064h Keyboard/Mouse - Command/ Status 8-bit Yes If KEL Memory Offset 100h[0] = 1

(EmulationEnable bit).

If MSR 5140001Fh[0] = 1 (SNOOP

bit) and KEL Memory Offset 100h[0]

= 0 (EmulationEnable bit).

065h-

06Fh

No Specific Usage --- ---

070h-

071h

RTC RAM Address/Data Port 8-bit Yes Options per MSR 51400014h[0].

(Note 1)

072h-

073h

High RTC RAM Address/Data Port 8-bit Yes Options per MSR 51400014h[1].

074h-

077h

No Specific Usage --- ---

078h-

07Fh

No Specific Usage --- ---

080h Post Code Display 8-bit Rec Write LPC and DMA. Read only

DMA.

081h DMA Channel 2 Low Page 8-bit Rec Upper addr bits [23:16]. Write LPC

and DMA. Read only DMA.

082h DMA Channel 3 Low Page

083h DMA Channel 1 Low Page

084h-

086h

No Specific Usage 8-bit Rec Write LPC and DMA. Read only

DMA.

Table 4-6. Legacy I/O: 000h-4FFh (Continued)

I/O Addr. Function Size R/W Comment

AMD Geode™ CS5536 Companion Device Data Book 71

Global Concepts and Features 33238G

087h DMA Channel 0 Low Page 8-bit Rec Upper addr bits [23:16]. Write LPC

and DMA. Read only DMA.

088h No Specific Usage 8-bit Rec Write LPC and DMA. Read only

DMA.

089h DMA Channel 6 Low Page 8-bit Rec Upper addr bits [23:16]. Write LPC

and DMA. Read only DMA.

08Ah DMA Channel 7 Low Page

08B DMA Channel 5 Low Page

08Ch-

08Eh

No Specific Usage 8-bit Rec Write LPC and DMA. Read only

DMA.

08Fh DMA C4 Low Page 8-bit Rec Upper addr bits [23:16]. See com-

ment at 080h.

090h-

091h

No Specific Usage --- ---

092h Port A 8-bit Yes If kel_porta_en is enabled, then

access Port A; else access LPC.

093h-

09Fh

No Specific Usage --- ---

0A0h PIC Slave - Command/Status 8-bit Shw$

0A1h PIC Slave - Command/Status 8-bit Shw$

0A2h-

0BFh

No Specific Usage 8-bit ---

0C0h Master DMA Address - Channel 4 8-bit Yes 16-bit values in two transfers.

0C1h No Specific Usage 8-bit ---

0C2h Master DMA Counter - Channel 4 8-bit Yes 16-bit values in two transfers.

0C3h No Specific Usage 8-bit ---

0C4h Master DMA Address - Channel 5 8-bit Yes 16-bit values in two transfers.

0C6h Master DMA Counter - Channel 5 8-bit Yes 16-bit values in two transfers.

0C7h No Specific Usage 8-bit ---

0C8h Master DMA Address - Channel 6 8-bit Yes 16-bit values in two transfers.

0CAh Master DMA Counter - Channel 6 8-bit Yes 16-bit values in two transfers.

0CBh No Specific Usage 8-bit ---

0CCh Master DMA Address - Channel 7 8-bit Yes 16-bit values in two transfers.

0CDh No Specific Usage 8-bit ---

0CEh Master DMA Counter - Channel 7 8-bit Yes 16-bit values in two transfers.

0CFh No Specific Usage 8-bit ---

0D0h Master DMA Command/Status - Channels

[7:4]

8-bit Shw$

0D1h No Specific Usage 8-bit ---

0D2h Master DMA Request - Channels [7:4] 8-bit WO

0D3h No Specific Usage 8-bit ---

0D4h Master DMA Mask - Channels [7:4] 8-bit Yes

0D5h No Specific Usage 8-bit ---

Table 4-6. Legacy I/O: 000h-4FFh (Continued)

I/O Addr. Function Size R/W Comment

72 AMD Geode™ CS5536 Companion Device Data Book

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33238G

0D6h Master DMA Mode - Channels [7:4] 8-bit Shw@

0D7h No Specific Usage 8-bit ---

0D8h Master DMA Clear Pointer - Channels [7:4] 8-bit WO

0D9h No Specific Usage 8-bit ---

0DAh Master DMA Reset - Channels [7:4] 8-bit WO

0DBh No Specific Usage 8-bit ---

0DCh Master DMA Reset Mask - Channels [7:4] 8-bit WO

0DDh No Specific Usage 8-bit ---

0DEh Master DMA General Mask - Channels [7:4] 8-bit Shw@

0DFh No Specific Usage 8-bit ---

0E0h-

2E7h

No Specific Usage --- ---

2E8h-

2EFh

UART/IR - COM4 8-bit --- MSR bit enables/disables into I/O

space.(UART1 MSR

51400014h[18:16], UART2 MSR

51400014h[22:20]). Defaults to

LPC.

2F0h-

2F7h

No Specific Usage --- ---

2F8h-

2FFh

UART/IR - COM2 8-bit --- MSR bit enables/disables into I/O

space.(UART1 MSR

51400014h[18:16], UART2 MSR

51400014h[22:20]). Defaults to

LPC.

300h-

36Fh

No Specific Usage --- ---

370h Floppy Status R A 8-bit RO Second Floppy.

371h Floppy Status R B 8-bit RO Second Floppy.

372h Floppy Digital Out 8-bit Shw@ Second Floppy.

373h No Specific Usage 8-bit ---

374h Floppy Cntrl Status 8-bit RO Second Floppy.

375h Floppy Data 8-bit Yes Second Floppy.

376h No Specific Usage 8-bit ---

377h Floppy Conf Reg 8-bit Shw$ Second Floppy.

378h-

3E7h

No Specific Usage --- ---

3E8h-

3EFh

UART/IR - COM3 8-bit --- MSR bit enables/disables into I/O

space.(UART1 MSR

51400014h[18:16], UART2 MSR

51400014h[22:20]). Defaults to

LPC.

3F0h Floppy Status R A 8-bit RO First Floppy.

3F1h Floppy Status R B 8-bit RO First Floppy.

3F2h Floppy Digital Out 8-bit Shw@ First Floppy.

Table 4-6. Legacy I/O: 000h-4FFh (Continued)

I/O Addr. Function Size R/W Comment

AMD Geode™ CS5536 Companion Device Data Book 73

Global Concepts and Features 33238G

3F3h No Specific Usage 8-bit ---

3F4h Floppy Cntrl Status 8-bit RO First Floppy.

3F5h Floppy Data 8-bit Yes First Floppy.

3F6h No Specific Usage 8-bit ---

3F7h Floppy Conf Reg 8-bit Shw$ First Floppy.

3F8h-

3FFh

UART/IR - COM1 8-bit --- MSR bit enables/disables into I/O

space.(UART1 MSR

51400014h[18:16], UART2 MSR

51400014h[22:20]). Defaults to

LPC.

400h-

47Fh

No Specific Usage --- ---

480h No Specific Usage 8-bit WO Write LPC and DMA. Read only

DMA.

481h DMA Channel 2 High Page 8-bit Rec Upper addr bits [31:24]. Write LPC

and DMA. Read only DMA.

482h DMA Channel 3 High Page

483h DMA Channel 1 High Page

484h-

486h

No Specific Usage 8-bit WO Write LPC and DMA. Read only

DMA.

487h DMA Channel 0 High Page 8-bit Rec Upper addr bits [31:24]. Write LPC

and DMA. Read only DMA.

488h No Specific Usage 8-bit WO Write LPC and DMA. Read only

DMA.

489h DMA Channel 6 High Page 8-bit Rec Upper addr bits [31:24]. Write LPC

and DMA. Read only DMA.

48Ah DMA Channel 7 High Page

48Bh DMA Channel 5 High Page

48Ch-

48Eh

No Specific Usage 8-bit WO Write LPC and DMA. Read only

DMA.

48Fh DMA Channel 4 High Page 8-bit Rec Upper addr bits [31:24]. Write LPC

and DMA. Read only DMA.

490h-

4CFh

No Specific Usage --- ---

4D0h PIC Level/Edge 8-bit Yes IRQ0-IRQ 7.

4D1h PIC Level/Edge 8-bit Yes IRQ8-IRQ15.

4D2h-

4FFh

No Specific Usage --- ---

Note 1. The Diverse Device snoops writes to this port and maintains the MSB as NMI enable. When low, NMI is enabled.

When high, NMI is disabled. This bit defaults high. Reads of this port return bits [6:0] from the on-chip or off-chip

target, while bit 7 is returned from the “maintained” value.

Table 4-6. Legacy I/O: 000h-4FFh (Continued)

I/O Addr. Function Size R/W Comment

74 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

4.7 Standard GeodeLink™ Device MSRs

All GeodeLink™ Devices have the following Standard

MSRs and are always located at the addresses indicated

below from the base address given in Table 4-2 "MSR

Addresses from AMD Geode™ LX Processor" on page 60:

•MSR Address 0: GeodeLink Device Capabilities

(GLD_MSR_CAP)

•MSR Address 1: GeodeLink Device Master Configura-

tion (and GLA Prefetch) (GLD_MSR_CONFIG)

•MSR Address 2: GeodeLink Device System Manage-

ment Interrupt Control (GLD_MSR_SMI)

•MSR Address 3: GeodeLink Device Error Control

(GLD_MSR_ERROR)

•MSR Address 4: GeodeLink Device Power Management

(GLD_MSR_PM)

•MSR Address 5: GeodeLink Device Diagnostic MSR

(GLD_MSR_DIAG) (This register is reserved for internal

use by AMD and should not be written to.)

4.7.1 MSR Address 0: Capabilities

The Capabilities MSR (GLD_MSR_CAP) is read only and

provides identification information as illustrated Table 4-7.

4.7.2 MSR Address 1: Master Configuration

The defined fields in the GeodeLink Device Master Config-

uration MSR (GLD_MSR_CONF) vary depending upon the

device. Refer to the appropriate GeodeLink Device register

chapter starting in Section 6.0 "Register Descriptions" on

page 193 for descriptions.

4.7.3 MSR Address 2: SMI Control

Each GeodeLink Device within the CS5536 companion

device incorporates System Management Interrupts

(SMIs). These SMIs are controlled via the Standard

GLD_MSR_SMI located at MSR Address 2 within each

GeodeLink Device (see Table 4-8). The lower 32 bits of this

contain Flag (FLAG) bits. The EN and FLAG bits are orga-

nized in pairs of (n, n+32). For example: (0,32); (1,33);

(2,34); etc. The GLD_MSR_SMI is used to control and

report events.

An event is any action or occurrence within the GeodeLink

Device requiring processor attention. The FLAG bits are

status bits that record events. The EN bits enable events to

be recorded. An EN bit must be 1 for an event to be

recorded (with the exception of the GLUI and the GLCP -

the EN bit must be 0 for an event to be recorded). When an

event is recorded, the associated FLAG bit is set to a 1.

SMI events are of two types: Asynchronous SMI (ASMI)

and Synchronous SMI (SSMI).

Table 4-7. GLD_MSR_CAP Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Reads as 0.

23:8 DEV_ID Device ID. Identifies the module.

7:0 REV_ID Revision ID. Identifies the module revision.

Table 4-8. Standard GLD_MSR_SMI Format

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

SMI_FLAG

313029282726252423222120191817161514131211109876543210

SMI_EN

AMD Geode™ CS5536 Companion Device Data Book 75

Global Concepts and Features 33238G

4.7.3.1 ASMI

ASMIs fall into two classes: direct and in-direct.

A behavioral model for a direct class ASMI is illustrated in

Figure 4-6. In the model, an event is represented as a short

duration (much less than 1 µs) positive pulse that is associ-

ated with a given Enable/Event pair n. The Enable/Event

pair is represented by a pair of simple “D” flip/flops that can

be set (write 1 to Q) or cleared (write 0 to Q) by software.

The EN bit can be written high or low, but the FLAG bit can

only be cleared. By GeodeLink architecture convention,

writing 1 to a FLAG bit clears it; writing 0 has no effect. If

the EN bit is 1, then the 0-to-1 transition of the event pulse

clocks a 1 into the SMI FLAG flip/flop.

All of the ASMI bits are ORed together to form the

GeodeLink Device ASMI. The GeodeLink Device ASMI is

routed through the GLIU where it is ORed with all other

device ASMIs to form the CS5536 companion device

ASMI.

Figure 4-6. Direct ASMI Behavioral Model

A behavioral model for an in-direct class ASMI is illustrated

in Figure 4-7 on page 76. An event is represented as

before, but it is first applied to some type of Native Event

kind that records multiple IRQ sources. Alternatively, there

might be multiple independent Native Event registers that

are at some point ORed together to form a single Native

Event Summary Signal (NESS). In general, a NESS can

also be an IRQ signal routed to the PIC device. Hence,

depending on operational needs, a NESS can be an IRQ or

ASMI.

The important point is that the NESS 0-to-1 transition

clocks a 1 into the SMI FLAG flip/flop. The event only in-

directly causes the SMI FLAG bit to be set. Further note

that the Event[X] and ASMI[n+1] are independently clear-

able. ASMI[n+1] can be cleared, while leaving NESS at a 1

state. After such clearing action with NESS high,

ASMI[n+1] will not set again. Alternatively, Event[X] could

be cleared without effecting the state of ASMI[n+1].

Lastly, it is possible to clear and set ASMI[n+1] while NESS

remains at a constant high state. Consider the following

sequence:

1) Assume EN[n] is high.

2) Event[X] occurs and NESS makes a 0-to-1 transition

that sets ASMI[n+1].

3) Software clears ASMI[n+1] by writing a 1 to it.

4) NESS remains high because Event[X] has not been

cleared.

5) EN[n] is cleared to 0.

6) EN[n] is set to a 1 and causes ASMI[n+1] to be set

again.

Note: Step 5 could also be performed between steps 2

and 3 instead, yielding the same result. The

sequence of setting EN[n] to 0 followed by setting

EN[n] to 1 is called an Enable Toggle.

The previous sequence is used when multiple events X, Y,

Z, etc. all OR to form a single NESS. The events are shar-

ing a single NESS. Under this arrangement, the following

Virtual System Architecture™ (VSA) software sequence

would be typical:

1) Assume EN[n] is high.

2) Event[X] fires and causes a CS5536 companion

device ASMI.

3) VSA searches the AMD Geode LX processor/CS5536

system looking for the ASMI source and finds

ASMI[n+1].

4) VSA clears EN[n] to 0 and begins to perform the

actions associated with Event[X].

5) While the “actions” are being taken, Event[Y] fires.

6) VSA “actions” include clearing Event[X] and

ASMI[n+1].

SMI MSR

FLAG Bit[n+1]

ASMI

[n+1]

GeodeLink™

Clear_By_Software

Set_By_Software

Clear_By_Software

Event

[X]

Bit[n]

Other ASMI

FLAG Bits

Device ASMI

76 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

7) NESS remains high because Event[Y] has fired.

8) VSA sets EN[n] high. This action sets ASMI[n+1] high

again and causes another CS5536 companion device

ASMI.

9) VSA begins to return to the process interrupted by the

original ASMI, but notes SMI into the processor is still

asserted and returns to step 3.

10) If there was no Event[Y] at any point above, return to

the interrupted process.

Note: Step 5 above could occur at any time between step

2 and step 9, or the Event[Y] could come after step

10. Regardless, the same VSA approach is used in

order not to miss any events.

4.7.3.2 Apparent SSMI

An SSMI event is associated with an I/O space access to a

specific address or range of addresses. If SSMIs are

enabled for the given address, then the hardware traps or

blocks access to the target register. The actual register

write and/or read operation is not performed. Generally,

only write operations are trapped, but there are cases of

trapping writes and reads. The CS5536 companion device

does not support SSMIs, however, it supports a mecha-

nism called “Apparent SSMI” using ASMIs. (Hereafter

“Apparent SSMI” is referred to as “SSMI”.)

The CS5536 companion device insures that the ASMI is

taken on the I/O instruction boundary. The ASMI reaches

the CPU before a target ready is signaled on the PCI bus.

This action creates an SSMI because the I/O instruction

will not complete before ASMI reaches the CPU. VSA soft-

ware then examines the GLPCI_SB GLD_SMI_MSR to

determine if an SSMI has occurred from an I/O trap.

Figure 4-7. In-Direct ASMI Behavioral Model

Native Event

FLAG Bit[x]

Clear_By_Software

Set_By_Software

Clear_By_Software

Event

[X]

Bit[m]

Other

FLAG Bits

SMI MSR

FLAG Bit[n+1]

ASMI

[n+1]

GeodeLink™

Clear_By_Software

Set_By_Software

Clear_By_Software

Bit[n]

Other ASMI

FLAG Bits

Native Event

Summary Signal

(NESS)

Event

[X]

ALL OR

ALL Device ASMI

AMD Geode™ CS5536 Companion Device Data Book 77

Global Concepts and Features 33238G

SSMIs are primarily used for hardware emulation and

extension. From the perspective of the code on which the

trap occurred, everything is normal and done in hardware.

However, VSA code generally performs a number of opera-

tions to achieve the desired result. This can include return-

ing an appropriate read value to the trapped software. The

GLIU is often used to implement SSMI traps. Any I/O

descriptor can be used for this purpose by setting the Des-

tination ID to 0. On a descriptor hit, the GLIU traps the

access and sets the SSMI bit in the response packet.

4.7.3.3 ASMI/SSMI Summary

Table 4-9 provides a register summary for the Standard

GLD_SMI_MSRs.

Table 4-9. GLD_MSR_SMIs Summary

Port #, Device FLAG Bit EN Bit SMI Type Description

Port 0, GLIU (Note 1) 35 3 ASMI Statistics Counter 2 Event

34 2 ASMI Statistics Counter 1 Event

33 1 ASMI Statistics Counter 0 Event

32 0 SSMI Descriptor Trap and Illegal Accesses

Port 1, GLPCI_SB 22 6 ASMI Target Abort Signaled

21 5 ASMI Parity Error

20 4 ASMI System Error

19 3 ASMI EXECP Received

18 2 ASMI SSMI Received

17 1 ASMI Target Abort Received

16 0 ASMI Master Abort Received

35 3 ASMI INT by the USB Option Controller (see PIC for actual source)

Port 4, DD (DIVIL) 47 15 SSMI PMC PM1_CNT

46 14 SSMI PMC PM2_CNT

45 13 ASMI KEL A20 Keyboard

44 12 SSMI 8237 DMA Controller access during legacy DMA

43 11 SSMI LPC access during legacy DMA

41 9 SSMI UART 2 access during legacy DMA

40 8 SSMI UART 1 access during legacy DMA

39 7 ASMI KEL INIT Port A

38 6 ASMI KEL A20 Port A

37 5 ASMI KEL INIT Keyboard

36 4 ASMI PMC Event (see PMC for actual source)

35 3 ASMI Extended PIC Mapper (see PIC for actual source)

34 2 ASMI KEL Emulation Event

33 1 ASMI Shutdown Special Cycle

32 0 ASMI Halt Special Cycle

Port 5, ACC 32 0 SSMI IRQ from ACC

Port 7, GLCP

(Note 1)

17 1 ASMI Debug event

16 0 ASMI Convert CS5536 Global GLIU_Error to ASMI

Note 1. For this device, the listed events are enabled when the EN bit is low. For all other devices, events are enabled when the associated

EN bit is high.

78 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

4.7.4 MSR Address 3: Error Control

Each GeodeLink Device within the CS5536 companion

device can generate errors. Furthermore, these errors are

controlled via the Standard GeodeLink Device Error MSR

(GLD_MSR_ERROR) located at MSR Address 3 within

each GeodeLink Device. The register is organized just like

GLD_MSR_SMI, that is, the lower 32 bits contain Enable

(EN) bits, while the upper 32 bits contain Flag (FLAG) bits

(see Table 4-8 on page 74). The EN and FLAG bits are

organized in pairs of (n, n+32). For example: (0,32); (1,33);

(2,34); etc. The Error MSR is used to control and report

errors.

The SMI concepts of direct asynchronous and synchro-

nous carry over into similar error concepts. However, there

is no concept of an in-direct error. At each GeodeLink

Device, all of the Error FLAG bits are ORed together to

form the Error signal. The Error is routed through the GLIU

where it is ORed with all other device Errors to form the

CS5536 companion device Error signal. This signal is

routed to the GLCP for debug purposes.

Only the GLIU is capable of generating synchronous errors

that utilize the Exception (EXCEP) bit of the associated

response packet. All other CS5536 GeodeLink Devices

only generate asynchronous errors.

4.7.5 MSR Address 4: Power Management

All the power management MSRs (GLD_MSR_PM) con-

form to the model illustrated in Table 4-10. The power and

I/O mode functions are completely independent other than

sharing the same MSR. The GLD_MSR_PM fields have

the following definitions:

•Power Mode for Clock Domains:

— 00: Disable clock gating. Clocks are always on.

— 01: Enable active hardware clock gating. Clock goes

off whenever this module’s circuits are not busy.

—10: Reserved.

— 11: Reserved.

•I/O Mode (Applies only to GLPCI_SB and IDE controller

modules, see Table 4-11 and Table 4-12 for a list of

controlled signals):

— 00: No gating of I/O cells during a Sleep sequence

(Default).

— 01: During a power management Sleep sequence,

force inputs to their non-asserted state when

PM_IN_SLPCTL (PMS I/O Offset 20h) is enabled.

— 10: During a power management Sleep sequence,

force inputs to their non-asserted state when

PM_IN_SLPCTL is enabled, and park (force) outputs

low when PM_OUT_SLPCTL (PMS I/O Offset 0Ch)

is enabled.

— 11: Immediately and unconditionally, force inputs to

their not asserted state, and park (force) outputs low.

The PMC controls when the PCI/IDE inputs and outputs

(listed in Table 4-11 and Table 4-12) are asserted and de-

asserted. The PM_OUT_SLPCTL (PMS I/O Offset 0Ch)

and PM_IN_SLPCTL (PMS I/O Offset 20h) registers pro-

vide the global control of the PCI/IDE I/Os. The IO_MODE

bits individually control PCI (GLPCI_SB GLD_MSR_PM

(MSR 51000004h[49:48]) and IDE (IDE GLD_MSR_PM

(MSR 51300004h[49:48]) I/Os.

Table 4-10. MSR Power Management Model

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

IO MODE H

IO MODE G

IO MODE F

IO MODE E

IO MODE D

IO MODE C

IO MODE B

IO MODE A

RSVD

313029282726252423222120191817161514131211109876543210

PMODE15

PMODE14

PMODE13

PMODE12

PMODE11

PMODE10

PMODE9

PMODE8

PMODE7

PMODE6

PMODE5

PMODE4

PMODE3

PMODE2

PMODE1

PMODE0

AMD Geode™ CS5536 Companion Device Data Book 79

Global Concepts and Features 33238G

4.8 Power Management

Typically the three greatest power consumers in a comput-

ing device are the display, hard drive (if it has one) and sys-

tem electronics. The CPU usually consumes the most

power of all the system electronic components. Managing

power for the first two is relatively straightforward in the

sense that they are simply turned on or off. Managing CPU

power is more difficult since effective use clock control

technology requires effective detection of inactivity, both at

a system level and at a code processing level.

Power consumption in an AMD Geode LX processor or

other AMD Geode processor based system is managed

with the use of both hardware and software. The complete

hardware solution is provided for only when the

AMD Geode LX processor is combined with the CS5536

companion device.

The processor power consumption is managed primarily

through a sophisticated clock stop management technol-

ogy. The processor also provides the hardware enablers

from which the complete power management solution

depends on.

Basically two methods are supported to manage power

during periods of inactivity. The first method, called activity

based power management allows the hardware in the

CS5536 companion device to monitor activity to certain

devices in the system and if a period of inactivity occurs

take some form of power conservation action. This method

does not require OS support because this support is han-

dled by SMM software. Simple monitoring of external activ-

ity is imperfect as well as inefficient. The second method,

called passive power management, requires the OS to take

an active role in managing power. AMD supports two appli-

cation programming interfaces (APIs) to enable power

management by the OS: Advanced Power Management

(APM) and Advanced Configuration and Power Interface

(ACPI). These two methods can be used independent of

one another or they can be used together. The extent to

which these resources are employed depends on the appli-

cation and the discretion of the system designer.

The AMD Geode LX processor and CS5536 companion

device contain advanced power management features for

reducing the power consumption of the processor, com-

panion device and other devices in the system.

Table 4-11. Sleep Driven PCI Signals

Signal Ball No. Direction

C/BE[3:0]# R6, T9, U11,

U14

Pad driven to 0. Internal

logic sees logic 1.

DEVSEL# R11 Pad driven to 0. Internal

logic sees logic 1.

FRAME# U9 Pad driven to 0. Internal

logic sees logic 1.

TRDY# T10 Pad driven to 0. Internal

logic sees logic 1.

IRDY# R10 Pad driven to 0. Internal

logic sees logic 1.

STOP# T11 Pad driven to 0. Internal

logic sees logic 1.

PAR U10 Pad driven to 0. Internal

logic sees logic 1.

REQ# T1 Pad driven to 0.

GNT# R1 Pad TRI-STATE. Internal

logic sees logic 0.

AD[31:0] U1, T3, U3,

R4, T4, R5,

T5, U5, T6,

U6, R7, T7,

U7, R8, T8,

U8, R12, T12,

U12, R13,

T13, U13,

R14, T14,

P15, R15,

T15, P16, T16,

R16, T17, R17

Pad driven to 0.

Table 4-12. Sleep Driven IDE Signals

Signal Ball No. Direction

IDE_CS[1:0]# C10, B10 Pad driven to 0.

IDE_IOR0# B13 Pad driven to 0.

IDE_IOW0# C13 Pad driven to 0.

IDE_AD[2:0] B11, A12, A11 Pad driven to 0.

IDE_RESET# F15 Pad driven to 0.

IDE_RDY0 A13 Pad TRI-STATE. Internal

logic sees logic 0.

IDE_DREQ0 A14 Pad TRI-STATE. Internal

logic sees logic 0.

IDE_DACK0# C12 Pad driven to 0.

IDE_DATA[15:0] C14, B15,

B16, A17,

C17, D16,

D17, E17,

E16, E15,

D15, B17,

C16, C15,

A15, B14

Pad driven to 0.

80 AMD Geode™ CS5536 Companion Device Data Book

Global Concepts and Features

33238G

4.8.1 Power Domains

In order to support power management in periods of inac-

tivity as well as “off” conditions, the CS5536 companion

device is divided into three power domains:

•Working Domain - Consists of VCORE and VIO

•Standby Domain - Consists of VCORE_VSB and VIO_VSB

•RTC Domain - Consists of VBAT

When the system is in an operational mode, all three of the

domains are on. In general the power management tech-

niques used while operating produce power savings with-

out user awareness. The performance and usability of the

system is unaffected.

When the system is “off” only the Standby domain is pow-

ered. If desired, the operational design can allow returning

the system to the operational point when the system was

last “on”. This “instant on” feature is a requirement for many

battery powered systems.

If the system has been removed from all power sources,

the Real-Time Clock (RTC) can be kept operating with a

small button battery.

All sections of the CS5536 companion device use the

Working domain except:

Standby Domain

•GPIO[31:24] and associated registers.

•GPIO Input Conditioning Functions 6 and 7.

•GPIO Power Management Events (PMEs) 6 and 7.

•MFGPT[7:6].

•Power Management Controller (PMC) Standby

Controller and associated I/O consisting of: WORKING,

WORK_AUX, and RESET_OUT.

•PMC Standby registers starting at PMS I/O Offset 30h.

See Table 6-71 "PM Support Registers Summary" on

page 525.

RTC Domain

•Real-Time Clock

4.8.2 ACPI Power Management

ACPI power management is a standardized method to

manage power. An overview of the standard is presented

here. See Section 5.17 "Power Management Control" on

page 169 for a more complete discussion of ACPI support

in the CS5536 companion device. See ACPI specification

v2.0 for complete details on ACPI. An AMD Geode LX pro-

cessor/CS5536 system solution can fully support all the

requirements in the ACPI specification.

ACPI defines power states from a system perspective

down to a device perspective. There are four global system

states: G0 through G3. As a subset of the Global system

states G0-G2, there are six Sleep states: S0 through S5.

Within the sleep states S0-S1, there are five CPU states:

C0-C3 and CT, and three Device states: D0-D2. In an

AMD Geode LX processor/CS5536 system design, the

optional Sleep state S2, and the CPU states C3 and CT

(CPU Throttling) are not supported. See Table 5-34 "Sup-

ported ACPI Power Management States" on page 169“.

Table 5-34 shows how the ACPI power states relate to

each other. The table also shows the condition of the power

domains and the logic within those domains with respect to

the ACPI power states.

4.8.3 APM Power Management

Some systems rely solely on an APM (Advanced Power

Management) driver for enabling the operating system to

power-manage the CPU. APM provides several services

that enhance the system power management. It is a rea-

sonable approach to power management but APM has

some limitations:

•APM is an OS-specific driver, and may not be available

for some operating systems.

•Application support is inconsistent. Some applications in

foreground may prevent Idle calls.

•APM does not help with Suspend determination or

peripheral power management.

4.9 Component Revision ID

The revision ID number of the CS5536 companion device

may be read in any of the following places. All return the

same value:

1) GLCP_CHIP_REV_ID register: MSR 51700017h[7:0].

2) PCI Configuration Space Device Revision ID:

PCI Index 08h[15:0].

3) TAP Controller Revision register:

Instruction 8FFFFAh[7:0].

The revision is an 8-bit value. For example:

0x01 A0 Value assigned to first manufactured

silicon of any new product.

For listing of updates, refer to the AMD Geode™ CS5536

Companion Device Specification Update document.

AMD Geode™ CS5536 Companion Device Data Book 81

Module Functional Descriptions 33238G

5.0Module Functional Descriptions

The modules that make up the AMD Geode™ CS5536

companion device (shown in gray in Figure 5-1) are:

•GeodeLink™ Interface Unit

•GeodeLink PCI South Bridge

•GeodeLink Control Processor

•IDE Controller (IDE Controller multiplexed with Flash

Interface)

•Universal Serial Bus Host Controller

•Universal Serial Bus Device Controller

•Audio Codec 97 (AC97) Controller

•Diverse Device

The Low Voltage Detect (LVD) circuit is not a GeodeLink

Device, but is connected to the Power Management Con-

troller (PMC) for voltage monitoring support.

This section provides a functional description of each mod-

ule.

Figure 5-1. Module Block Diagram

GeodeLink™ PCI

South Bridge

AMD Geode™ LX Processor Interface

PCI

Test/Reset

Interface

AC97 Controller

External

Audio

IDE Controller

USB Host Controller

33 or 66 MHz

Flash

Interface

82xx PC

Legacy

MFGP

Timers

RTC &

CMOS RAM

UART (2)

& IR (1)

SMB

Controller

LPC

Port

Power

Mgmnt

External I/O

External USB

Ports 1,2 & 3

External USB

Port 4

GeodeLink™

Interface

Unit

External

IDE/Flash

GPIO

Diverse Integration Logic (DIVIL)

Diverse

Device (DD)

Low Voltage

Detect (LVD)

System Power

Voltages Power Good

for Power On

Reset (POR)

(GLPCI_SB)

(GLIU)

(USB)

(ACC)

(IDE)

GeodeLink™ Control

Processor (GLCP)

USB Device

(UDC)

82 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ Interface Unit

33238G

5.1 GeodeLink™ Interface Unit

Many traditional architectures use buses to connect mod-

ules together, usually requiring unique addressing for each

house-keeping be done as new modules are designed and

new devices are created from the module set. Module

select signals can be used to create the unique addresses,

but that can get cumbersome and it requires that the mod-

ule selects be sourced from some centralized location.

To alleviate this issue, AMD developed an internal bus

architecture based on GeodeLink™ technology. The

GeodeLink architecture connects the internal modules of a

device using the data channels provided by GeodeLink

Interface Units (GLIUs). Using GLIUs, all internal module

port addresses are derived from the distinct port that the

module is connected to. In this way, a module’s Model Spe-

cific Registers (MSRs) do not have unique addresses until

a device is defined. Also, as defined by the GeodeLink

architecture, a module’s port address depends on the loca-

tion of the module sourcing the cycle, or source module.

The AMD Geode CS5536 companion device incorporates

one GLIU into its device architecture. Except for the config-

uration registers that are required for x86 compatibility, all

internal registers are accessed through a Model Specific

and a 64-bit data space. The full 64-bit data space is

always read or written when accessed.

5.1.1 GLIU Port Connections

Table 5-1 shows the GeodeLink Devices connected to each

of the seven GLIU ports on CS5536 companion device.

5.1.2 Descriptor Summary

Table 5-2 shows the descriptors reserved for each

GeodeLink Device.

Table 5-1. GLIU Port Connections

Port # GeodeLink™ Device

1GeodeLink PCI South Bridge (GLPCI_SB)

2USB Controller (USB)

3IDE Controller (IDE)

4Diverse Device (DD)

5AC97 Audio Controller (ACC)

6Not Used

7GeodeLink Control Processor (GLCP)

Table 5-2. GLIU Descriptors Reserved for GeodeLink™ Devices

GeodeLink™

Device

Descriptor

Type

# of

Descriptors Usage

USB P2D_BM(K) 4 Do not hit on keyboard emulation registers.

IDE IOD_BM 1 For IDE master registers.

IOD_BM 1 Defaults to 1Fxh.

IOD_SC 1 Defaults to 3F6h.

DD IOD_BM 3 COM ports legacy power management.

IOD_BM 1 For secondary IDE trapping to 17xh.

IOD_SC 1 For secondary IDE trapping to 376h.

IOD_SC 1 Keyboard legacy power management.

IOD_SC 3 LPC ports legacy power management.

IOD_SC 1 Floppy legacy power management.

ACC P2D_BM 1 For memory space registers.

IOD_BM 1 For I/O space registers.

GLPCI_SB P2D_BM 1 For master requests to AMD Geode™ LX processor’s GLPCI.

Spares IOD_BM 3

IOD_SC 1

P2D_BM 1

AMD Geode™ CS5536 Companion Device Data Book 83

GeodeLink™ PCI South Bridge 33238G

5.2 GeodeLink™ PCI South Bridge

The GeodeLink™ PCI Bus South Bridge (GLPCI_SB) pro-

vides a PCI interface for GeodeLink Device based designs.

Its three major functions are:

1) Acting as a PCI slave and transforming PCI transac-

tions to GLIU transactions as a GLIU master.

2) Acting as a GLIU slave and transforming GLIU trans-

actions to PCI bus transactions as a PCI master.

3) Providing a CPU serial interface that conveys system

information such as interrupts, SSMI, ASMI, etc.

Features include:

•PCI v2.2 compliance. Optional signals PERR#, SERR#,

LOCK#, and CLKRUN are not implemented.

•32-bit, 66 MHz PCI bus operation and 64-bit, 66 MHz

GeodeLink Device operation.

•Target support for fast back-to-back transactions.

•Zero wait state operation within a PCI burst.

•MSR access mailbox in PCI configuration space.

•Capable of handling in-bound transactions after

RESET_OUT# + 2 clock cycles.

•Dynamic clock stop/start support for GeodeLink and PCI

clock domains via power management features.

•Programmable IDSEL selection.

•Support active decoding for Legacy I/O space 000h to

3FFh and DMA High Page 480h to 48Fh.

•Support subtractive decode for memory and I/O space.

•Special performance enhancements for fast IDE PIO

data transfers.

•The GeodeLink PCI interface does not support peer-to-

peer transactions on the PCI bus from devices other

than the CPU.

The GLPCI_SB module is composed of the following major

blocks:

•GeodeLink Interface

•FIFO/Synchronization

•Transaction Forwarding

•PCI Bus Interface

•CPU Interface Serial (CIS)

The GLIU and PCI bus interfaces provide adaptation to the

respective buses. The Transaction Forwarding block pro-

vides bridging logic. The CIS block provides serial output to

the CPU for any change in SSMI and the selected side-

band signals. Little endian byte ordering is used on all sig-

nal buses.

Figure 5-2 is a block diagram of the GLPCI_SB module.

Figure 5-2. GLPCI_SB Block Diagram

GeodeLink™ Interface

PCI Bus Interface

PCI Bus

Request

Request Data

REQ# / GNT#

MSR Transaction Forwarding

FIFOs/Synchronization CIS Side-band signals

CIS

AMD Geode™ LX Processor

84 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ PCI South Bridge

33238G

5.2.1 GeodeLink Interface

The GeodeLink Interface block provides a thin protocol

conversion layer between the transaction forwarding mod-

ule and the GLIU. It is responsible for multiplexing in-bound

write request data with out-bound read response data on

the single GLIU data out bus.

5.2.2 FIFOs/Synchronization

The FIFO block consists of a collection of in-bound and

out-bound FIFOs. Each FIFO provides simple, synchro-

nous interfaces to the reader and to the writer.

The FIFO block also includes synchronization logic for a

few non-FIFO related signals and clock gating logic.

5.2.3 Transaction Forwarding

The Transaction Forwarding block receives, processes, and

forwards transaction requests and responses between the

GeodeLink Interface and PCI Bus Interface blocks. It imple-

ments the transaction ordering rules. It performs write/read

prefetching as needed. It also performs the necessary

translation between GLIU and PCI commands. The Trans-

action Forwarding block also handles the conversion

between 64-bit GLIU data paths and 32-bit PCI data paths.

Out-bound transactions are handled in a strongly ordered

fashion. All out-bound memory writes are posted. The

SEND_RESPONSE flag is never expected to be set in a

memory write and is ignored. Any queued out-bound

requests are flushed prior to handling an in-bound read

request.

All in-bound memory writes are posted. South bridge mas-

ter out-bound read request data can pass in-bound writes.

Thus, a pending out-bound read request need not be

deferred while posted in-bound write data is waiting to be

flushed or is in the process of being flushed. The out-bound

read request may be performed on the PCI bus at the

same time that the in-bound write data is flowing through

the GLIU.

When handling an in-bound read request, the intended size

of the transfer is unknown. In-bound read requests for non-

prefetchable addresses only fetch the data explicitly indi-

cated in the PCI transaction. Thus, all in-bound read

requests made to non-prefetchable addresses return at

most a single 32-bit WORD. In-bound read requests made

to prefetchable memory may cause more than a 32-bit

WORD to be prefetched. The amount of data prefetched is

configurable via the read threshold fields of the Global

Control (GLPCI_CTRL) register, MSR 51000010h. Multiple

read requests may be generated to satisfy the read thresh-

old value.

In-bound read requests may pass posted in-bound write

data when there is no address collision between the read

request and the address range of the posted write data (dif-

ferent cache lines) and the read address is marked as

being prefetchable.

Support IDE data port Read Prefetch when MSR Control

performance enhancement. I/O reads to address 1F0h can

follow a prefetching behavior. When enabled, the

GLPCI_SB issues GLIU Read Request Packets for this

specific address before receiving a request on the PCI bus

for it.

5.2.4 PCI Bus Interface

The PCI Bus Interface block provides a protocol conversion

layer between the transaction forwarding module and the

PCI bus. The master and target portions of this module

operate independently. Thus, out-bound write requests and

in-bound read responses are effectively multiplexed onto

the PCI bus. The PCI Bus Interface block includes address

decoding logic to recognize distinct address regions for

slave operation. Each address region is defined by a start-

ing address, an address mask, and some attached

attributes (i.e., memory and/or I/O space indicator,

prefetchable, retry/hold, postable memory write, region

enable).

The PCI Bus Interface block is responsible for retrying out-

bound requests when a slave termination without data is

seen on the PCI bus. It also must restart transactions on

the PCI that are prematurely ended with a slave termina-

tion. This module also always slave terminates in-bound

read transactions issued to non-prefetchable regions after

a single WORD has been transferred.

5.2.5 CPU Interface Serial

The CPU Interface Serial block provides a serial interface

to the CPU for side-band signals. From reset, the

GLPCI_SB connects only the SUSP# signal to the serial

output. All other signals must be added by programming

the CIS mode (MSR 51000010h[4:3]). Any change of the

signals selected from the 16 side-band signals will start

shifting to the CPU all 20 bits of the CIS register including

two START bits (00) and two padding STOP bits (11).

Three different modes control the selection of the side-

band signals to the CIS shift register.

5.2.6 Programmable ID Selection

An ID select register, IDSEL[31:0], is used for programma-

ble ID selection. Only one bit in IDSEL[31:12] is set and

used as a chip select (i.e., compared with AD[31:12]) dur-

ing a PCI configuration write/read. The reset value of the

IDSEL register is 02000000h. After reset, the first 32-bit I/O

write PCI command (i.e., BE# = 0h) with address

00000000h and one bit set in AD[31:0] is assumed to ini-

tialize the IDSEL register. Only data with one bit set in

AD[31:0] is considered valid. All other values are ignored

and will not change the contents of IDSEL.

AMD Geode™ CS5536 Companion Device Data Book 85

GeodeLink™ PCI South Bridge 33238G

5.2.7 SSMI and EXCEP Support in GLIU

Read/Write Response Packets

If the Hold for CIS Transfer Disable bit in

GLPCI_MSR_CTRL (MSR 51000010h[9]) is set, any in-

bound memory, I/O, or external MSR read/write response

packet is checked for SSMI and EXCEP bits. If the

response packet has the EXCEP bit and/or SSMI bit set,

then the GLPCI_SB will not complete the transaction (it

either issues a Retry or Hold PCI bus) until the CIS transfer

completes.

During an out-bound transaction, when the GLPCI_SB

issues a Master Abort, the EXCEP bit in the GLIU

response packet is set.

5.2.8 Subtractive Decoding

If the SDOFF (Subtractive Decode Off) bit in the

GLPCI_MSR_CTRL (MSR 51000010h[10]) is cleared

(reset value), any PCI transaction, other than Configuration

Read/Write, Interrupt Acknowledge, and Special Cycle

transactions, not claimed by any device (i.e., not asserting

DEVSEL#) within the default active decode cycles (three

cycles immediately after FRAME# being asserted) will be

accepted by GLPCI_SB at the fourth clock edge. The Retry

condition is issued for Memory Read, Memory Read Line,

Memory Read Multiple (after Initial Latency Timeout), and

I/O Read/Write (immediately) and all the required informa-

tion (command, address and byte enable bits) is stored for

the following Delayed Transactions. During Delayed Trans-

actions, the active decode scheme is used. Any address

accessed through a subtractive decoding is assumed to be

non-prefetchable.

5.2.9 Byte Enable Checking in I/O Address

Decoding

In any in-bound I/O transaction, the byte enables BE[3:0]#

are checked against address bits PCI_AD[1:0] for valid

combinations. If an illegal byte enable pattern is asserted,

the GLPCI_SB issues a Target Abort. The only exception is

when subtractive decode is used. During a subtractive

decode, PCI_AD[1:0] and BE# are passed to the GLIU as

is. The I/O Addressing Error Checking Disable bit in

GLPCI_MSR_CTRL (MSR 51000010h[8]) can be set to

disable the I/O addressing error checking, where AD[1:0] is

ignored and the byte enables are passed to the GLIU.

5.2.10 IDE Data Port Read Prefetch

This algorithm issues multiple four byte reads to the IDE

data register (1F0h) at the “beginning” of an IDE “read

operation”. The hardware continues to read ahead of soft-

ware read requests until a sector boundary is about to be

crossed. The hardware does not read ahead over a sector

boundary. Once a software read crosses a sector bound-

ary, the hardware proceeds to read ahead again. Further-

more, the algorithm does not prefetch the last read of a

sector because there is the potential that the last sector

read will be the last read of the overall read operation. On

the last read, the status changes to indicate the operation

is complete. By not prefetching the last sector read, the

data and status never get out of sync with each other.

5.2.11 IDE Data Port Write Posting

The PPIDE (Post Primary IDE) bit in GLPCI_MSR_CTRL

(MSR 51000010h[17]) controls post/write on confirmation

for I/O writes of address 1F0h (part of primary IDE

address). If bit 17 is set, a write is completed immediately

on the PCI bus as soon as it is accepted by the GLPCI_SB.

If bit 17 is cleared, an I/O write is completed only after com-

pleting the write in the primary IDE space. Default behavior

is write on confirmation.

5.2.12 Other Typical Slave Write Posting

For each GLPCI_SB Region Configuration register (0

through 15), if the SPACE bit (bit 32) is programmed for I/O

and bit 3 (PF, Prefetchable) is high, post all I/O writes to

this region. (See Section 6.2.2.2 "Region 0-15 Configura-

tion MSRs (GLPCI_R[x])" on page 232 for further details.)

Use of this feature is most appropriate for GPIO “bit bang-

ing” in the Diverse Device module. Posting writes on the

North Bridge side will not increase performance.

5.2.13 Memory Writes with Send Response

Normally memory writes are posted independent of region

and independent of decode and legacy/non-legacy

address. The USB registers are in memory space and can

not be moved to I/O space due to driver compatibility

issues. In an AMD Geode LX processor/CS5536 compan-

ion device system, a memory write is posted and a possi-

bility exists that a subsequent I/O write will complete before

the posted memory write completes. In order to prevent out

of order execution, when a memory write is issued to the

GLIU in the CS5536 companion device, the request packet

is issued with the send response bit set to serialize the

request. I/O writes are not an issue, since the requests

packet always has the send response bit set.

86 AMD Geode™ CS5536 Companion Device Data Book

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5.2.14 CPU Interface Serial (CIS)

The CIS provides the system interface between the

CS5536 companion device and AMD Geode LX processor.

The interface supports several modes to send different

combinations of 16-bit side-band signals through the CIS

signal (ball P3). The sideband signals are synchronized to

the PCI clock through 2-stage latching. Whenever at least

one of 16 signals is changed, the serial transfer (using the

PCI clock) immediately starts to send the information from

the companion device to the processor. But, if any bit

changes within 20 clocks of any previous change, the later

change is not transmitted during the transfer. Another

transfer starts immediately after the conclusion of the

transfer due to the subsequent change.

There are three modes of operation for the CIS signal (ball

P3). Note that the transmitted polarity may be different than

the “generally defined” polarity state:

•Mode A - Non-serialized mode with CIS equivalent to

SUSP# (reset mode). Not used in normal operation.

•Mode B - Serialized mode with signals SUSP#, NMI#,

Sleep#, and Delayed Sleep#. Not used in normal opera-

tion.

•Mode C - Serialized mode with Mode B signals plus

SMI#, and INTR#. Used in normal operation.

If the HCD bit (MSR 51000010h[9]) is set, any in-bound

transaction, except in-bound memory writes, is held for any

CIS transfer to complete before claiming completion.

Mode selection is programmed in the GLPCI_MSR_CTRL

(MSR 51000010h[4:3]).

Table 5-3 lists the serial data with corresponding side-band

signals. The serial shift register takes the selected side-

band signals as inputs. The signal SMI is the ORed result

of the SSMI_ASMI_FLAG (SSMI Received Event) bit

(GLPCI MSR 51000002h[18]) and the side-band signal

ASMI. It also serves as a direct output to the processor.

Table 5-3. CIS Serial Bits Assignment and Descriptions

Bit Position Mode B Mode C Comment

start_0 0 0 Start Bit 0

start_1 0 0 Start Bit 1

data 00 1 1 Reserved

data 01 1 1 Reserved

data 02 SUSP# SUSP# Sleep Request

data 03 NMI# NMI# Non-Maskable Interrupt

data 04 Sleep# Sleep# Power Management Input Disable

data 05 Delayed Sleep# Delayed Sleep# Power Management Output Disable

data 06 1 SMI# Asynchronous SMI or Synchronous SMI

data 07 1 INTR# Maskable Interrupt out

data 08 1 1 Reserved

data 09 1 1 Reserved

data 10 1 1 Reserved

data 11 1 1 Reserved

data 12 1 1 Reserved

data 13 1 1 Reserved

data 14 1 1 Reserved

data 15 1 1 Reserved

stop_0 1 1 Stop Bit 0

stop_1 1 1 Stop Bit 1

Note: Mode A is not listed since it is a non-serialized mode with CIS equivalent to SUSP# (reset mode).

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5.2.15 Exception Handling

This section describes how various errors are handled by

the PCI Bus Interface block.

Since PERR# is not implemented on the CS5536 compan-

ion device or on the AMD Geode LX processor, error

reporting via this signal is not supported. In an AMD Geode

LX/CS5536 system, other PCI devices that do have the

PERR# pin must have a pull-up.

5.2.16 Out-Bound Write Exceptions

When performing an out-bound write on PCI, three errors

may occur: master abort, target abort, and parity error.

When a master or target abort occurs, the PCI Bus Inter-

face block flushes any stored write data. If enabled, an

ASMI is generated. ASMI generation is enabled and

reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h).

Parity errors are detected and handled by the processor.

The failed transaction is not retried.

5.2.17 Out-Bound Read Exceptions

When performing an out-bound read on PCI, three errors

may occur: master abort, target abort, and detected parity

error. When a master or target abort occurs, the PCI Bus

Interface block returns the expected amount of data. If

enabled, an ASMI is generated. ASMI generation is

enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR

51000002h). Parity errors are detected and handled by the

processor. The failed transaction is not retried.

5.2.18 In-Bound Write Exceptions

When performing an in-bound write from PCI, two errors

may occur: a detected parity error and a GLIU exception. A

GLIU exception cannot be relayed back to the originating

PCI bus master, because in-bound PCI writes are always

posted. When a parity error is detected, an ASMI is gener-

ated if it is enabled. ASMI generation is enabled and

reported in the GLPCI_SB GLD_MSR_SMI register (MSR

51000002h). However, the corrupted write data is passed

along to the GLIU.

5.2.19 In-Bound Read Exceptions

When performing an in-bound read from the GLIU, the

EXCEP flag may be set on any received bus-WORD of

data. This may be due to an address configuration error

caused by software or by an error reported by the source of

data. The asynchronous ERR and/or SMI bit is set by the

PCI Bus Interface block and the read data, valid or not, is

passed to the PCI Bus Interface block along with the asso-

ciated exceptions. The PCI Bus Interface block should sim-

ply pass the read response data along to the PCI bus.

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5.3 AC97 Audio Codec Controller

The primary purpose of the AC97 Audio Codec Controller

(ACC) is to stream data between system memory and an

AC97 codec (or codecs) using direct memory access

(DMA). The AC97 codec supports several channels of digi-

tal audio input and output. Hence, the ACC contains sev-

eral bus mastering DMA engines to support these

channels. This method off-loads the CPU, improving sys-

tem performance. The ACC is connected to the system

through the GLIU and all accesses to and from system

memory go through the GLIU. The AC97 codec is con-

nected with a serial interface, and all communication with

the codec occurs via that interface (see Figure 5-3).

Features include:

•AC97 version 2.3 compliant interface to codecs: serial in

(x2), serial out, sync out, and bit clock in.

•Eight-channel buffered GLIU mastering interface.

•Support for industry standard 16-bit pulse code modu-

lated (PCM) audio format.

•Support for any AC97 codec with Sample Rate Conver-

sion (SRC).

•Transport for audio data to and from the system memory

and AC97 codec.

•Capable of outputting multi-channel 5.1 surround sound

(Left, Center, Right, Left Rear, Right Rear, and

Low Frequency Effects).

Hardware Includes:

•GeodeLink™ Adapter.

•Three 32-bit stereo-buffered bus masters (two for output,

one for input).

•Five 16-bit mono-buffered bus masters (three for output,

two for input).

•AC Link Control block for interfacing with external AC97

codec(s).

The ACC logic controls the traffic to and from the AC97

codec. For input channels, serial data from the codec is

buffered and written to system memory using DMA. For

output channels, software-processed data is read from sys-

tem memory and streamed out serially to the codec.

Figure 5-3. ACC Block Diagram

GLIU Data In GLIU Data Out

GeodeLink™ Adaptor (GLA)

Output

Data

Mux

Registers / Control

To/From Codec

Control Signals to Bus Masters

GLCP I/F

Bus Master 0

Bus Master 1

Bus Master 2

Bus Master 3

Bus Master 4

Bus Master 5

Bus Master 6

Bus Master 7

CCUGL Clock

CCULBus Clock

CCU

AC Link

Bit Clock

Link

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5.3.1 Audio Bus Masters

The ACC includes eight bus mastering units (three for

input, five for output). Each bus master corresponds to one

or two slots in the AC Link transfer protocol (see Section

5.3.4.1 "AC Link Serial Interface Protocol" on page 90).

Table 5-4 lists the details for each bus master.

5.3.2 Bus Master Audio Configuration

Registers

The bus masters must be programmed by software to con-

figure how they transfer data. This is done using their con-

figuration registers. These registers determine whether the

bus master is active and what parts of memory they have

been assigned to transfer. Status registers allow software

to read back information on the state of the bus masters.

(See Section 6.3.2 "ACC Native Registers" on page 246 for

further details on the Bus Master Audio Configuration reg-

isters.)

5.3.3 AC Link Overview

The AC Link is the interface between the AC97 codec and

the ACC. The interface is AC97 v2.3 compliant. Any AC97

codec that supports Sample Rate Conversion (SRC) can

be used with the ACC. See Intel Corporation’s “Audio

Codec 97” Revision 2.3 component specification for more

details.

The AC Link protocol defines an input and output frame

consisting of 12 “slots” of data. Each slot contains 20 bits,

except slot 0, which contains 16 bits. The SYNC signal is

generated by the ACC and defines the beginning of an

input and an output frame. The serial clock is generated by

the AC97 codec. The AC Link is covered in depth in Sec-

tion 5.3.4.1 "AC Link Serial Interface Protocol" on page 90.

It is important to note that the AC97 codec has its own set

of configuration registers that are separate from the ACC.

These registers are accessible over the serial link. There

are registers in the ACC that provide software with an inter-

face to the AC97 codec registers. (See Section 6.3.2 "ACC

Native Registers" on page 246 for register descriptions.)

Table 5-4. Audio Bus Master Descriptions

Bus

Master Size Direction AC Link Slot(s) Channel Description

BM0 32-bit

(16 bits/channel)

Output to codec 3 (left) and 4 (right) Left and Right Stereo Main Playback

BM1 32-bit

(16 bits/channel)

Input from codec 3 (left) and 4 (right) Left and Right Stereo Recording

BM2 16-bit Output to codec 5 Modem Line 1 DAC Output

BM3 16-bit Input from codec 5 Modem Line 1 ADC Input

BM4 16-bit Output to codec 6 or 11 (configurable) Center Channel Playback (slot 6) or

Headset Playback (slot 11)

BM5 16-bit Input from codec 6 or 11 (configurable) Microphone Record (slot 6) or

Headset Record (slot 11)

BM6 32-bit

(16 bits/channel)

Output to codec 7 (left) and 8 (right) Left and Right Surround Playback

BM7 16-bit Output to codec 9 Low Frequency Effects Playback (LFE)

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5.3.4 Codec Interface

5.3.4.1 AC Link Serial Interface Protocol

The following figures outline the slot definitions and timing scheme of the AC Link serial protocol.

Figure 5-4. AC Link Slot Scheme

Figure 5-5. AC Link Output Frame

Figure 5-6. AC Link Input Frame

TAG CMD PCM PCM LINE1 PCM PCM PCM PCM RSVD HSET GPIO

AC_S_SYNC

AC_S_OUT

(Outgoing Stream)

AC_S_IN

Data Phase

TAG

ADDR CMD

DATA LEFT RIGHT DAC CEN L SUR R SUR LFE DAC CNTL

TAG

STATUS

PCM PCM LINE1 MIC RSVD HSET GPIO

ADDR

STATUS

DATA LEFT RIGHT ADC ADC ACD

STATUS

or AC_S_IN2

(Incoming Stream)

RSVD RSVD RSVD

0123456789101112

Slot #

Phase

Valid

Frame Slot 1 Slot 2 Slot 12

End of

AC_CLK

AC_S_SYNC

Time slot “valid” bits

(“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12

Tag Phase Data Phase

48 KHz (20.8 µs)

12.288 MHz (81.4 ns)

AC_S_OUT

“0” “0” “0” 19 0 19 1901900

Slot 3

Previous Frame

Codec

Ready Slot 1 Slot 2

Slot 12

End of

Time slot “valid” bits

(“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12

AC_S_IN or AC_S_IN2

“0”

“0” “0” “19” 0 19 0 19 0 19 0

AC_CLK

AC_S_SYNC

Tag Phase Data Phase

48 KHz (20.8 µs)

12.288 MHz (81.4 ns)

Previous Frame

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5.3.4.2 AC Link Output Frame (AC_S_OUT)

The audio output frame data stream corresponds to the

time division multiplexed bundles of all digital output data

targeting the AC97 codec’s DAC inputs and control regis-

ters. Each audio output frame contains 13, 20-bit outgoing

data slots, except for slot 0, which contains 16 bits. Slot 0 is

a dedicated slot used for the AC Link protocol.

An audio output frame begins with a low-to-high transition

of the AC_S_SYNC signal. AC_S_SYNC is synchronous to

the rising edge of AC_CLK. The AC97 codec samples the

AC_S_SYNC on the immediately following falling edge of

AC_CLK. AC_S_SYNC is held high for 16-bit clocks. The

ACC transmits data on each rising edge of the bit clock,

whereas the AC97 codec samples the data on the falling

edge of AC_CLK.

The serial output stream is MSB justified (MSB first) within

each slot, and all non-valid bit positions are stuffed with 0s

by the AC Link interface.

Slot 0: TAG

This slot is used for AC Link protocol information. The first

bit (bit 15) flags the validity of the entire audio frame as a

whole. If this bit is 0, all of the remaining bits in the frame

should be 0. The next 12 bits indicate the validity of the 12

following slots. The last two bits contain the codec ID for

accessing registers of several codecs. When the codec ID

is 01, 10, or 11, bits 13 and 14 must always be 0, even if

slots 1 and 2 are valid. Slots that are marked invalid by slot

0 should be padded with all 0s (except for slots 1 and 2

while accessing registers of a secondary codec).

bit 15 Frame Valid

bit 14 Slot 1 Valid

(primary codec only)

bit 13 Slot 2 Valid

(primary codec only)

bits [12:3] Slot 3-12 Valid bits

(bit[12] -> slot 3, bit[11] -> slot 4,

bit[10] -> slot 5, ... , bit[3] -> slot 12)

bit 2 Reserved

bits [1:0] Codec ID field

Slot 1: Command Address

The command address is used to access registers within

the AC97 codec. The AC97 registers control features and

monitor status for AC97 codec functions, including mixer

settings and power management as indicated in the AC97

Codec specifications.

The control interface architecture supports up to 64 16-bit

read/write registers, addressable on even byte boundaries,

and reserves support for 64 odd addresses. Audio output

frame slot 1 communicates control register address, and

write/read command information to the AC97 codec.

bit 19 Read/Write Command

(1 = Read, 0 = Write)

bits [18:12] Control Register Index

(64 16-bit locations, addressed on

even byte boundaries)

bits [11:0] Reserved

(Stuffed with 0s)

The first bit (MSB) indicates whether the current control

transaction is a read or write operation. The following 7 bit

positions communicate the targeted control register

address.

Slot 2: Command Data

The command data slot carries 16-bit control register write

data if the current command port operation is a write cycle

as indicated by slot 1, bit 19.

bits [19:4] Control Register Write Data

(Stuffed with 0s if current operation

is a read)

bits [3:0] Reserved

(Stuffed with 0s)

If the current command port operation is a read, then the

entire slot is stuffed with 0s.

Slot 3: PCM Playback Left Channel

Outputs the front left audio DAC data (main output) (16-bit

resolution, MSB first, unused LSBs = 0).

Slot 4: PCM Playback Right Channel

Outputs the front right audio DAC data (main output) (16-bit

resolution, MSB first, unused LSBs = 0).

Slot 5: Modem Line 1 DAC

Outputs the modem line 1 DAC data (16-bit resolution,

MSB first, unused LSBs = 0).

Slot 6: PCM Playback Center Channel

Outputs the center channel DAC data (16-bit resolution,

MSB first, unused LSBs = 0).

Slot 7: PCM Playback Left Surround Channel

Outputs the left surround channel DAC data (16-bit resolu-

tion, MSB first, unused LSBs = 0).

Slot 8: PCM Playback Right Surround Channel

Outputs the right surround channel DAC data (16-bit reso-

lution, MSB first, unused LSBs = 0).

Slot 9: PCM Playback LFE Channel

Outputs the low frequency effects channel DAC data (16-bit

resolution, MSB first, unused LSBs = 0).

Slot 10: Not used

Slots 10 is not used by the ACC.

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Slot 11: Modem Headset DAC

Outputs the headset DAC data (16-bit resolution, MSB first,

unused LSBs = 0).

Slot 12: GPIO Control

This slot allows the ACC to set the value of the AC97

codec’s GPIO output pins.

bits [19:4] Value of the GPIO pins

(Up to 16 can be implemented)

bits [3:0] Reserved

5.3.4.3 AC Link Input Frame (AC_S_IN, AC_S_IN2)

The audio input frame data streams correspond to the time

division multiplexed bundles of all digital input data coming

from the AC97 codec. Each input frame contains 13, 20-bit

incoming data slots, except for slot 0, which contains 16

bits. Slot 0 is a dedicated slot used for the AC Link protocol.

An audio input frame begins with a low-to-high transition of

the AC_S_SYNC signal. AC_S_SYNC is synchronous to

the rising edge of AC_CLK. The AC97 codec samples the

AC_S_SYNC signal on the immediately following falling

edge of the bit clock. The AC97 codec transmits data on

each following rising edge of AC_CLK. The ACC samples

the data on the falling edges of AC_CLK.

The serial input stream is MSB justified (MSB first) within

each slot, and all non-valid bit positions stuffed with zeroes

by the AC97 codec.

Slot 0: TAG

The first bit of the TAG slot (bit 15) is the Codec_Ready bit.

The next 12 bits indicate the validity of the next 12 data

slots.

Slot 1: Status Address / SLOTREQ Bits

The status address is the echo of the register address

(index) that was sent to the codec on output slot 1 of the

previous output frame. It indicates the address (index) of

the register whose data is being returned in slot 2 of the

input frame.

bit 19 Reserved

(Stuffed with 0s)

bits [18:12] Control Register Index

(Echo of register index for which data

is being returned)

bits [11:2] SLOTREQ bits

(For variable sampling rate)

bits [1:0] Reserved

(Stuffed with 0s)

The SLOTREQ bits support the variable sample rate sig-

naling protocol. With normal 48 KHz operation, these bits

are always zero. When the AC97 codec is configured for a

lower sample rate, some output frames will not contain

samples because the AC Link always outputs frames at 48

KHz. The SLOTREQ bits serve as the codec’s instrument

to tell the ACC whether it needs a sample for a given slot

on the next output frame. For each bit: 0 = Send data; 1 =

Do NOT send data. If the codec does not request data for a

given slot, the ACC should tag that slot invalid and not send

PCM data. The mapping between SLOTREQ bits and out-

put slots is given in Table 5-5. The SLOTREQ bits are inde-

pendent of the validity of slot 1, and slot 1 is only tagged

valid by the codec if it contains a register index.

Slot 2: Status Data

The status data slot delivers 16-bit control register read

data.

bits [19:4] Control Register Read Data

(Stuffed with 0s if slot 2 is tagged

“invalid” by slot 0)

bits [3:0] Reserved

(Stuffed with 0s)

Slot 3: PCM Record Left Channel

Contains the left channel ADC input data (16-bit resolution,

MSB first, unused LSBs = 0).

Slot 4: PCM Record Right Channel

Contains the right channel ADC input data (16-bit resolu-

tion, MSB first, unused LSBs = 0).

Slot 5: Modem Line 1 ADC

Contains the modem line 1 ADC input data (16-bit resolu-

tion, MSB first, unused LSBs = 0).

Slot 6: Optional Microphone Record Data

Contains the microphone ADC input data (16-bit resolution,

MSB first, unused LSBs = 0).

Slots 7-10: Not Used

Slots 7-10 are reserved.

Table 5-5. SLOTREQ to Output Slot Mapping

Bit

Slot

Request Notes

11 Slot 3 Left Channel Out (BM0)

10 Slot 4 Right Channel Out (BM0)

9 Slot 5 Modem Line 1 Out (BM2)

8 Slot 6 Center Out (BM4 if selected)

7 Slot 7 Left Surround Out (BM6)

6 Slot 8 Right Surround Out (BM6)

5 Slot 9 LFE Out (BM7)

4 Slot 10 Not Supported

3 Slot 11 Handset Out (BM4 if selected)

2 Slot 12 Not Supported

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Slot 11: Modem Headset ADC

Contains the modem headset ADC input data (16-bit reso-

lution, MSB first, unused LSBs = 0).

Slot 12: GPIO Status

This slot returns the pin status of the AC97 codec’s GPIO

pins (if implemented).

bits [19:4] Value of the GPIO pins

(Up to 16 can be implemented)

bits [3:1] Reserved

bit 0 GPIO_INT input pin event interrupt

(1 = Event; 0 = No Event)

Bit 0 indicates that there was a transition on one of the

unmasked codec GPIO pins (see AC97 Codec Specifica-

tion v2.3 for details). If the Codec GPIO Interrupt Enable bit

is set, then slot 12, bit 0 = 1 triggers an IRQ and sets the

Codec GPIO Interrupt Flag bit.

5.3.5 AC Link Power Management

5.3.5.1 AC Link Power-down

The AC Link interface signals can be placed in a low power

mode by programming the AC97 codec’s Power-down Con-

trol/Status register. When this is performed, both the

AC_CLK and AC_S_IN are brought to a low voltage level

by the AC97 codec. This happens immediately following

the write to the AC97 codec’s Power-down Control/Status

frame signaling power-down. After powering down the AC

Link, the ACC must keep AC_S_SYNC and AC_S_OUT

low; hence, all the AC Link signals (input and output) are

driven low.

AC_CLK is de-asserted at the same time that bit 4 of slot 2

is being transmitted on the AC Link. This is necessary

because the precise time when the codec stops, AC_CLK

is not known.

5.3.5.2 AC Link Wakeup (Warm Reset)

A warm reset re-activates the AC Link without altering the

registers in the AC97 codec. The ACC signals the warm

reset by driving AC_S_SYNC high for a minimum of 1 µs in

the absence of the AC_CLK. This must not occur for a min-

imum of four audio frame periods following power-down

(note that no bit clock is available during this time).

AC_S_SYNC is normally a synchronous signal to AC_CLK,

but when the AC97 codec is powered down, it is treated as

an asynchronous wakeup signal. During wakeup, the AC97

codec does not re-activate the bit clock until AC_S_SYNC

is driven high (for 1 µs minimum) and then low again by the

ACC. Once AC_S_SYNC is driven low, AC_CLK is re-

asserted.

See "Audio Driver Power-up/down Programming Model" on

page 97 for additional power management information and

programming details.

5.3.6 Bus Mastering Buffer Scheme

Because the bus masters must feed data to the codec with-

out interruption, they require a certain amount of data buff-

ering.

The 32-bit bus masters (stereo) use 24 bytes of buffer

space, and the 16-bit bus masters (mono) use 20 bytes of

buffer space. A bus master always does buffer fill/empty

requests whenever it can transfer 16 bytes of data. It

attempt to do transfers of 16 bytes on a 16-byte boundary,

whenever possible. A bus master may do a transfer of more

(if it is just starting, and sufficient buffer space is available)

or less than 16 bytes (to bring itself onto a 16-byte bound-

ary). It may also do a transfer of less than 16 bytes if the

size of the physical memory region causes it to end on a

non-16 byte boundary.

Some important details on how a bus master behaves:

•When an outgoing bus master is enabled, it begins

sending data over the AC Link as soon as data is avail-

able in its buffer. The slot valid tag for its slot is asserted

beginning with the first audio sample.

•When a bus master is disabled while operating, any data

in its buffer is lost. Re-enabling the bus master begins by

fetching a Physical Region Descriptor (PRD).

•If the bus master is paused during recording or play-

back, the data in its buffer remains there in a frozen

state. Once resumed, it continues as if nothing has

occurred. If the bus master is playing back data, the

output slots corresponding to the bus master are tagged

invalid while it is in the paused state.

•If a buffer underrun occurs on an outgoing bus master,

the output slots corresponding to the bus master are

tagged invalid until data becomes available.

•If a buffer overrun occurs on an incoming bus master,

samples coming in on the serial link are tossed away

until space becomes available in the bus master’s buffer.

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5.3.7 ACC Software Programming

5.3.7.1 Physical Region Descriptor Table Address

Before a bus master starts a transfer, it must be pro-

grammed with a pointer to a PRD table. This is done by

writing to the bus master’s PRD Table Address register.

This pointer sets the starting memory location of the PRD

table. The PRDs in the PRD table describe the areas of

memory that are used in the data transfer. The table must

be aligned on a 4-byte boundary (DWORD aligned).

5.3.7.2 Physical Region Descriptor Format

Each physical memory region to be transferred is

described by a PRD as illustrated in Table 5-6. The PRD

table must be created in memory by software before the

bus master can be activated. When the bus master is

enabled by setting its Bus Master Enable bit, data transfer

begins, with the PRD table serving as the bus master’s

“guide” for what to do. The bus master does not cache

PRDs.

A PRD entry in the PRD table consists of two DWORDs.

The first DWORD contains a 32-bit pointer to a buffer to be

transferred (Memory Region Base Address). The second

DWORD contains control flags and a 16-bit buffer size

value. The maximum amount of audio data that can be

transferred for a given PRD is 65534 bytes for mono

streams and 65532 bytes for stereo streams.

For stereo streams (bus masters 0, 1, and 6):

Memory Region Base Address and Size should be a

multiple of four (DWORD aligned). This ensures an

equal number of left and right samples.

For mono streams (bus masters 2, 3, 4, 5, and 7):

Memory Region Base Address and Size should be a

multiple of two (WORD aligned).

Descriptions of the control flags are:

• End of Transfer (EOT) - If set in a PRD, this bit indi-

cates the last entry in the PRD table. The last entry in a

PRD table must have either the EOT bit or the JMP bit

set. A PRD can not have both the JMP and EOT bits set.

When the bus master reaches an EOT, it stops and

clears its Bus Master Enable bit. If software desires an

IRQ to be generated with the EOT, it must set the EOP

bit and the EOT bit on the last PRD entry.

• End of Page (EOP) - If set in a PRD and the bus master

has completed the PRD’s transfer, the End of Page bit is

set (in the IRQ status register) and an IRQ is generated.

If a second EOP is reached due to the completion of

another PRD before the End of Page bit is cleared, the

Bus Master Error bit is set (in the IRQ status register)

and the bus master pauses. In this paused condition,

reading the IRQ status register clears both the Bus

Master Error and the End of Page bits, and the bus

master continues.

• Jump (JMP) - This PRD is special. If set, the Memory

Region Base Address is now the target address of the

JMP. The target address of the JMP must point to

another PRD. There is no audio data transfer with this

PRD. This PRD allows the creation of a looping mecha-

nism. If a PRD table is created with the JMP bit set in the

last PRD, the PRD table does not need a PRD with the

EOT bit set. A PRD can not have both the JMP and EOT

bits set.

Table 5-6. Physical Region Descriptor (PRD) Format

DWORD

Byte 3 Byte 2 Byte 1 Byte 0

09876543210

0 Memory Region Base Address [31:0] (Address of Audio Data Buffer)

EOT

EOP

JMP

Reserved Size [15:0]

AMD Geode™ CS5536 Companion Device Data Book 95

AC97 Audio Codec Controller 33238G

5.3.7.3 PCM Data Format and Byte Order

Table 5-7 shows an example of how PCM audio data is

stored in memory (byte order and channel order). Each row

represents a byte in memory, in order of increasing

addresses. The byte order can be configured via the Bus

Master Command Register for Intel (little endian) or Motor-

ola (big endian) byte ordering. Changing the byte order

only affects how PCM data is interpreted. PRD entries and

format applies to the 32-bit bus masters handling left and

right input and output. The single channel format applies to

the 16-bit bus masters. The 32-bit bus masters always

operate on stereo data, and the 16-bit bus masters always

operate on mono data. Since there is no special mode for

playing monaural sound through the main channels (left

and right), it is the responsibility of the software to create

stereo PCM data with identical samples for the left and

right channels to effectively output monaural sound.

5.3.7.4 Programming Model

Audio Playback/Record

The following discussion explains, in steps, how to initiate

and maintain a bus master transfer between memory and

an audio slave device. In the steps, the reference to Exam-

ple refers to Figure 5-7:

1) Software creates a PRD table in system memory. The

last PRD entry in a PRD table must have the EOT or

JMP bit set.

Example - Assume the data is outbound. There are

three PRDs in the example PRD table. The first two

PRDs (PRD_1, PRD_2) have only the EOP bit set.

The last PRD (PRD_3) has only the JMP bit set. This

example creates a PRD loop.

Figure 5-7. ACC PRD Table Example

Table 5-7. PCM Data format (Byte and Channel Ordering)

2 Channel,

Little Endian

1 Channel,

Little Endian

2 Channel,

Big Endian

1 Channel,

Big Endian

Sample Channel Byte Sample Byte Sample Channel Byte Sample Byte

0 Left Low 0 Low 0 Left High 0 High

0 Left High 0 High 0 Left Low 0 Low

0 Right Low 1 Low 0 Right High 1 High

0 Right High 1 High 0 Right Low 1 Low

1 Left Low 2 Low 1 Left High 2 High

1 Left High 2 High 1 Left Low 2 Low

1 Right Low 3 Low 1 Right High 3 High

1 Right High 3 High 1 Right Low 3 Low

Address_1

Size_1

EOT = 0 Audio

Buffer_1

Audio

Buffer_2

Size_1

Size_2

Address_1

EOP = 1

JMP = 0

Address_2

Size_2

EOT = 0

EOP = 1

JMP = 0

Address_3

Don’t Care

EOT = 0

EOP = 0

JMP = 1

PRD_1

PRD_2

PRD_3

Address_2

Address_3

96 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller

33238G

2) Software loads the starting address of the PRD table

by programming the PRD Table Address register.

Example - Program the PRD Table Address register

with Address_3.

3) Software must fill the buffers pointed to by the PRDs

with audio data. It is not absolutely necessary to fill the

buffers; however, the buffer filling process must stay

ahead of the buffer emptying. The simplest way to do

this is by using the EOP flags to generate an interrupt

when an audio buffer is empty.

Example - Fill Audio Buffer_1 and Audio Buffer_2.

Ensure than an interrupt service routine is assigned to

the audio interrupt.

4) Read the IRQ Status register to clear the Bus Master

Error and End of Page flags (if set).

Program the AC97 codec properly to receive audio

data (mixer settings, etc.).

Engage the bus master by setting the Bus Master

Enable bit.

The bus master reads the PRD entry pointed to by the

PRD Table Address register. Using the address from

the PRD, it begins the audio transfer. The PRD Table

Address register is incremented by eight.

Example - The bus master is now properly pro-

grammed to transfer Audio Buffer_1 to a specific

slot(s) in the AC97 interface.

5) The bus master transfers data from memory and

sends it to the AC97 codec. At the completion of each

PRD, the bus master’s next response depends on the

settings of the flags in the PRD.

Example - After transferring the data described by

PRD_1, an interrupt is generated because the EOP bit

is set, and the bus master continues on to PRD_2. The

interrupt service routine reads the Second Level Audio

IRQ Status register to determine which bus master to

service. It refills Audio Buffer_1 and then reads the bus

master’s IRQ Status register to clear the End of Page

flag and the interrupt.

After transferring the data described by PRD_2,

another interrupt is generated because the EOP bit is

set, and the bus master continues on to PRD_3. The

interrupt service routine reads the Second Level Audio

IRQ Status register to determine which bus master to

service. It refills Audio Buffer_2 and then reads the bus

master’s IRQ Status register to clear the End of Page

flag and the interrupt.

PRD_3 has the JMP bit set. This means the bus mas-

ter uses the address stored in PRD_3 (Address_3) to

locate the next PRD. It does not use the address in the

PRD Table Address register to get the next PRD. Since

Address_3 is the location of PRD_1, the bus master

has looped the PRD table. No interrupt is generated

for PRD_3.

Pausing the bus master can be accomplished by set-

ting the Bus Master Pause bit in its control register.

The bus master stops immediately on the current sam-

ple being processed. Upon resuming, the bus master

(clearing the Bus Master Pause bit), resumes on the

exact sample where it left off.

The bus master can be stopped in the middle of a

transfer by clearing the Bus Master Enable bit in its

control register. In this case, the bus master will not

remember what sample it left off on. If it is re-enabled,

it begins by reading the PRD entry pointed to by its

PRD Table Address register. If software does not re-

initialize this pointer, it point to the PRD entry immedi-

ately following the PRD entry that was being pro-

cessed. This may be an invalid condition if the bus

master was disabled while processing the last PRD in

a PRD table (PRD Table Address register pointing to

memory beyond the table).

Note that if the Bus Master Error bit is set, the interrupt

service routine should refill two buffers instead of one,

because a previous interrupt was missed (unless it

was intentionally missed). For this to work correctly,

the service routine should read the Second Level

Audio IRQ Status register, fill the buffer of the bus

master needing service, read the bus master’s IRQ

Status register, and then fill the next buffer if the Bus

Master Error bit was set. Failing to fill the first buffer

before reading the IRQ Status register would possibly

resume the bus master too early and result in sound

being played twice or data being overwritten (if record-

ing).

Codec Register Access

The ACC provides a set of registers that serve as an inter-

face to the AC97 codec’s registers. The Codec Command

codec register. The Codec Status register allows software

to read back the data from the codec after a read operation

has completed. Since the AC Link runs very slow relative to

core CPU speed (and therefore software speed), it is nec-

essary for software to wait between issuing commands to

the codec.

For register reads, software specifies a command address

and sets both the read/write flag and the Codec Command

New flag in the Codec Control register. Software must then

wait for the Codec Status New bit to be set before using the

returned status data in the Codec Status register. Before

issuing another read command, software must wait for the

Codec Command New flag to be cleared by hardware.

(Note: Codec Command New will clear before Codec Sta-

tus New is set; therefore, a second read can be issued

before the result of the current read is returned).

For register writes, software specifies a command address

and command data using the Codec Control register. At

the same time it must set the Codec Command New flag.

Before issuing another read or write, software must wait for

the Codec Command New flag to clear. See Section 6.3

"AC97 Audio Codec Controller Register Descriptions" for

details on the Codec register interface.

AMD Geode™ CS5536 Companion Device Data Book 97

AC97 Audio Codec Controller 33238G

Audio Driver Power-up/down Programming Model

The ACC contains Model Specific Registers (MSRs) that

relate to a very low level power management scheme, but

are discrete from the power management features of the

codec and the device driver programming model. This sec-

tion covers the power management features for the device

driver.

See Section 5.3.5 "AC Link Power Management" on page

93 for power management hardware details.

The following sections outline how the device driver should

perform power management.

Power-down Procedure

1) Disable or pause all bus masters using their bus mas-

ter command register.

2) It may be necessary to determine if a second codec is

being used, and if so, verify that the power-down

Semaphore for Secondary Codec bit is set before pro-

ceeding (to insure that the modem driver has prepared

the second codec for power-down, if necessary).

3) Using the Codec Control register, access the primary

codec’s registers and program the codec to power-

down. Also, simultaneously write to the AC Link Shut-

down bit in the Codec Control register (ACC I/O Offset

0Ch[18]).

4) The ACC and codec power-down once the command

is received by the codec. All contents of the ACC and

codec registers are preserved during the power-down

state.

5) To enable the GPIO wakeup interrupt, wait for an addi-

tional two audio frame periods (42 µs) before setting

the GPIO Wakeup Interrupt Enable bit (ACC I/O Offset

00h[29]). Failure to wait causes false interrupt events

to occur.

Power-up Procedure

1) If GPIO Wakeup Interrupt Enable (ACC I/O Offset

00h[29]) was set in the power-down procedure, it is

automatically disabled upon power-up.

2) Set the AC Link Warm Reset bit in the Codec Control

warm reset sequence.

3) Wait for the Codec Ready bit(s) in the Codec Status

before accessing any codec features or enabling any

bus masters.

Notes:

1) If the GPIO Wakeup Interrupt Enable (ACC I/O Offset

00h[29]) is set, and an interrupt occurs, it is detected

and fired, but the interrupt does not wakeup the codec

and ACC. The hardware will only wakeup if the soft-

ware responds to the interrupt and performs the

power-up procedure.

2) Once software has issued a power-down, it must not

perform the power-up procedure for at least six audio

frame periods (about 0.125 ms or 125 µs). Doing so

could lock up the codec or ACC.

3) If the system has cut off power to the codec and

restarted it, it is not necessary to initiate a warm reset.

The AC Link Shutdown should be cleared manually to

restart the operation of the AC Link.

98 AMD Geode™ CS5536 Companion Device Data Book

IDE Controller

33238G

5.4 IDE Controller

The hard disk controller is an ATA-6 compatible IDE con-

troller. This controller supports UDMA (up to UDMA mode

5), MDMA, and PIO modes. The controller can support one

channel (two devices).

The IDE interface provides a variety of features to optimize

system performance, including 32-bit disk access, post

write buffers, bus master, MDMA, look-ahead read buffer,

and prefetch mechanism.

The IDE interface timing is completely programmable. Tim-

ing control covers the command active and recover pulse

widths, and command block register accesses. The IDE

data-transfer speed for each device on each channel can

be independently programmed allowing high speed IDE

peripherals to coexist on the same channel as older, com-

patible devices. Faster devices must be ATA-6 compatible.

The IDE controller also provides a software-accessible

buffered reset signal to the IDE drive. The IDE_RESET#

signal is driven low during system reset and can be driven

low or high as needed for device power off conditions.

Features include:

•ATA-6 compliant IDE controller

•Supports PIO (mode 0 to 4), MDMA (mode 0 to 2), and

UDMA (mode 0 to 5).

•Supports one channel, two devices

•Allows independent timing programming for each device

5.4.1 PIO Modes

The IDE data port transaction latency consists of address

latency, asserted latency, and recovery latency. Address

latency occurs when a PCI master cycle targeting the IDE

data port is decoded, and the IDE_ADDR[2:0] and

IDE_CS# lines are not set up. Address latency provides the

setup time for the IDE_AD[2:0] and IDE_CS# lines prior to

IDE_IOR# and IDE_IOW#.

Asserted latency consists of the I/O command strobe

assertion length and recovery time. Recovery time is pro-

vided so that transactions may occur back-to-back on the

IDE interface without violating minimum cycle periods for

the IDE interface.

If IDE_RDY0 is asserted when the initial sample point is

reached, no wait states are added to the command strobe

assertion length. If IDE_RDY0 is negated when the initial

sample point is reached, additional wait states are added.

Recovery latency occurs after the IDE data port transac-

tions have completed. It provides hold time on the

IDE_AD[2:0] and IDE_CS# lines with respect to the read

and write strobes (IDE_IOR# and IDE_IOW#).

The PIO portion of the IDE registers is enabled through the

IDE Controller Drive Timing Control register (IDE_DTC)

(MSR 51300012h)

The IDE channel and devices can be individually pro-

grammed to select the proper address setup time, asserted

time, and recovery time.

The bit formats for these registers are shown in Section

6.5.3 "IDE Controller Native Registers" on page 341.

5.4.2 Bus Master Mode

An IDE bus master is provided to perform the data trans-

fers for the IDE channel. The IDE controller off-loads the

CPU and improves system performance.

The bus master mode programming interface is an exten-

sion of the standard IDE programming model. This means

that devices can always be dealt with using the standard

IDE programming model, with the master mode functional-

ity used when the appropriate driver and devices are

present. Master operation is designed to work with any IDE

device that supports DMA transfers on the IDE bus.

Devices that work in PIO mode can only use the standard

IDE programming model.

The IDE bus master uses a simple scatter/gather mecha-

nism, allowing large transfer blocks to be scattered to or

gathered from memory. This cuts down on the number of

interrupts to and interactions with the CPU.

5.4.2.1 Physical Region Descriptor Table Address

Before the controller starts a master transfer it is given a

pointer to a Physical Region Descriptor Table. This pointer

sets the starting memory location of the Physical Region

Descriptors (PRDs). The PRDs describe the areas of mem-

ory that are used in the data transfer. The PRDs must be

aligned on a 4-byte boundary and the table cannot cross a

64 KB boundary in memory.

5.4.2.2 IDE Bus Master Registers

The IDE Bus Master registers have an IDE Bus Master

Command register and Bus Master Status register (IDE I/O

Address 00h and 02h respectively). These registers can be

accessed by byte, WORD, or DWORD.

AMD Geode™ CS5536 Companion Device Data Book 99

IDE Controller 33238G

5.4.2.3 Physical Region Descriptor Format

Each physical memory region to be transferred is

described by a Physical Region Descriptor (PRD) as illus-

trated in Table 5-8. When the bus master is enabled (Com-

mand register bit 0 = 1), data transfer proceeds until each

PRD in the PRD table has been transferred. The bus mas-

ter does not cache PRDs.

The PRD table consists of two DWORDs. The first DWORD

contains a 32-bit pointer to a buffer to be transferred. This

pointer must be 2-byte aligned. The second DWORD con-

tains the size in bytes of the buffer and the EOT (End Of

Table) flag. The size must be in multiples of 1 WORD (2

bytes) or zero (which means a 64 KB transfer). The EOT bit

(bit 31) must be set to indicate the last PRD in the PRD

table.

5.4.2.4 Programming Model

The following steps explain how to initiate and maintain a

bus master transfer between memory and an IDE device:

1) Software creates a PRD table in system memory.

Each PRD entry is 8 bytes long, consisting of a base

address pointer and buffer size. The maximum data

that can be transferred from a PRD entry is 64 KB. A

PRD table must be aligned on a 4-byte boundary. The

last PRD in a PRD table must have the EOT bit set.

2) Software loads the starting address of the PRD table

by programming the PRD Table Address register.

3) Software must fill the buffers pointed to by the PRDs

with IDE data.

4) Write 1 to the Bus Master Interrupt bit and Bus Master

Error (IDE I/O address 02h[2,1]) to clear the bits.

5) Set the correct direction to the Read or Write Control

bit (IDE I/O address 00h[3]).

Engage the bus master by writing a 1 to the Bus Mas-

ter Control bit (IDE I/O address 00h[0]).

The bus master reads the PRD entry pointed to by the

PRD Table Address register and increments the

address by 08h to point to the next PRD. The transfer

begins.

6) The bus master transfers data to/from memory

responding to bus master requests from the IDE

device until all PRD entries are serviced.

7) The IDE device signals an interrupt once its pro-

grammed data count has been transferred.

8) In response to the interrupt, software resets the Bus

Master Control bit (IDE I/O address 00h[0]). It then

reads the status of the controller and IDE device to

determine if the transfer is successful.

Table 5-8. Physical Region Descriptor Format

DWORD

Byte 3 Byte 2 Byte 1 Byte 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Memory Region Physical Base Address [31:1] (IDE Data Buffer) 0

EOT

Reserved Size [15:1] 0

100 AMD Geode™ CS5536 Companion Device Data Book

IDE Controller

33238G

5.4.2.5 UDMA Mode

The IDE controller supports UDMA modes 0 to 5. It utilizes

the standard IDE bus master functionality to interface, ini-

tiate, and control the transfer. The ATA specification also

incorporates a Cyclic Redundancy Checking (CRC) error

checking protocol to detect errors.

The UDMA protocol requires no extra signal pins on the

IDE connector. The IDE controller redefines three standard

IDE control signals when in UDMA mode. These definitions

are shown in Table 5-9.

All other signals on the IDE connector retain their func-

tional definitions during the UDMA operation.

IDE_IOW# is defined as STOP for both read and write

transfers to request to stop a transaction.

IDE_IOR# is redefined as DMARDY# for transferring data

from the IDE device to the IDE controller. It is used by the

IDE controller to signal when it is ready to transfer data and

to add wait states to the current transaction. The IDE_IOR#

signal is defined as STROBE for transferring data from the

IDE controller to the IDE device. It is the data strobe signal

driven by the IDE controller on which data is transferred

during each rising and falling edge transition.

IDE_IORDY is redefined as STROBE for transferring data

from the IDE device to the IDE controller during a read

cycle. It is the data strobe signal driven by the IDE device

on which data is transferred during each rising and falling

edge transition. IDE_IORDY is defined as DMARDY# dur-

ing a write cycle for transferring data from the IDE control-

ler to the IDE device. It is used by the IDE device to signal

when it is ready to transfer data and to add wait states to

the current transaction.

UDMA data transfer consists of three phases: a startup

phase, a data transfer phase, and a burst termination

phase.

The IDE device begins the startup phase by asserting

IDE_DREQ. When ready to begin the transfer, the IDE con-

troller asserts IDE_DACK#. When IDE_DACK# is asserted,

the IDE controller drives IDE_CS0# and IDE_CS1#

asserted, and IDE_ADDR[2:0] low. For write cycles, the

IDE controller negates STOP, waits for the IDE device to

assert DMARDY#, and then drives the first data WORD

and STROBE signal. For read cycles, the IDE controller

negates STOP and asserts DMARDY#. The IDE device

then sends the first data WORD and asserts STROBE.

The data transfer phase continues the burst transfers with

the IDE controller and the IDE device via providing data,

toggling STROBE and DMARDY#. IDE_DATA[15:0] is

latched by the receiver on each rising and falling edge of

STROBE. The transmitter can pause the burst cycle by

holding STROBE high or low, and resume the burst cycle

by again toggling STROBE. The receiver can pause the

burst cycle by negating DMARDY# and resumes the burst

cycle by asserting DMARDY#.

The current burst cycle can be terminated by either the

transmitter or receiver. A burst cycle must first be paused,

as described above, before it can be terminated. The IDE

controller can then stop the burst cycle by asserting STOP,

with the IDE device acknowledging by negating

IDE_DREQ0. The transmitter then drives the STROBE sig-

nal to a high level. The IDE controller then puts the result of

the CRC calculation onto IDE_DATA[15:0] while de-assert-

ing IDE_DACK0#. The IDE device latches the CRC value

on the rising edge of IDE_DACK0#.

The CRC value is used for error checking on UDMA trans-

fers. The CRC value is calculated for all data by both the

IDE controller and the IDE device during the UDMA burst

transfer cycles. This result of the CRC calculation is

defined as all data transferred with a valid STROBE edge

while IDE_DACK0# is asserted. At the end of the burst

transfer, the IDE controller drives the result of the CRC cal-

culation onto IDE_DATA[15:0], which is then strobed by the

de-assertion of IDE_DACK0#. The IDE device compares

the CRC result of the IDE controller to its own and reports

an error if there is a mismatch.

The timings for UDMA are programmed in the DMA control

•IDE Controller UDMA Extended Timing Control Register

(IDE_ETC) (MSR 51300014h)

The bit formats for these registers are given in Section

6.5.3 "IDE Controller Native Registers" on page 341.

Table 5-9. UDMA Signal Definitions

IDE Channel

Signal

UDMA

Read Cycle

UDMA

Write Cycle

IDE_IOW# STOP STOP

IDE_IOR# DMARDY# STROBE

IDE_RDY0 STROBE DMARDY#

AMD Geode™ CS5536 Companion Device Data Book 101

Universal Serial Bus Controller 33238G

5.5 Universal Serial Bus Controller

The Universal Serial Bus (USB) Controller module (Figure

5-8) consists of a USB 2.0 Enhanced Host Controller Inter-

face (EHCI) compliant host controller, with a USB 1.1 Open

Host Controller Interface (OHCI) compliant companion con-

troller, and a USB 2.0 device controller. The USB module is

connected via the GeodeLink™ Adapter (GLA) to the pro-

cessor and other modules.

There are four USB 2.0 ports. The ports are dependent on

the type of attached device, either associated with the EHC

or OHC interface.

Furthermore Port 4 can be configured as a device. The

functional descriptions of the blocks in Figure 5-8 are

described in the following subsections.

5.5.1 GeodeLink™ Adapter

The GeodeLink™ Adapter (GLA) translates GeodeLink

transactions to/from local bus transactions. The GLA inter-

faces to a 64-bit GLIU (GeodeLink Interface Unit) and a 32-

bit local bus. The GLA supports in-bound memory that tar-

gets the USB module. It also supports in-bound MSR

transactions to the MSRs, which are located in the GLA.

The GLA supports out-bound memory requests only. I/O

and MSR transactions from the USB never occur. The GLA

contains an arbiter that arbitrates the bus master requests

of the OHC, the EHC, and the device controller. A prefetch

logic is implemented for bus master read performance

improvement to cover memory read latencies.

Figure 5-8. USB Controller Block Diagram

USB Port 1

Port 1

USB Module

64-bit GeodeLink™ Interface Unit

GeodeLink™

Adapter

Prefetch Logic

MSRs

Port Router

Target Interface

Bus Master Arbiter

Host Controller

Device Controller

USB Port 2

Port 2

USB Port 3

Port 3

USB Port 4

Port 4

USB PHY

UTMI-MUX

EHCOHC Device

Local Bus

UTMI Interface

MHZ48_XCI MHZ48_XCO

Oscillator

MHZ48_CLK

MHZ48_XCEN

Controller Option

Controller

USB_VBUS

102 AMD Geode™ CS5536 Companion Device Data Book

Universal Serial Bus Controller

33238G

5.5.2 Host Controller

The host controller is responsible for:

•Detecting the attachment and removal of USB devices.

•Managing control flow between the host and USB

devices.

•Managing data flow between the host and USB devices.

•Collecting status and activity statistics.

•Controlling power supply to attached USB devices.

•Controlling the association to either the OHCI or the

EHCI via the port router

•Root Hub functionality to support up to four ports

The USB system software on the host manages interac-

tions between USB devices and host-based device soft-

ware. There are five areas of interactions between the USB

system software and device software:

1) Device enumeration and configuration.

2) Isochronous data transfers.

3) Asynchronous data transfers.

4) Power management.

5) Device and bus management information.

Whenever possible, the USB system software uses existing

host system interfaces to manage the above interactions.

Attached devices are recognized by the USB PHY as either

USB 1.1 compliant (full speed and low speed) or USB 2.0

compliant (high speed) devices. Low or full speed devices

attached to USB ports are associated with the OHC and

high speed devices are associated with the EHC.

The interface combines responsibility for executing bus

transactions requested by the host controller as well as the

hub and port management specified by USB.

5.5.3 Device Controller

USB Port 4 can be configured alternatively as a device

port. The device supports four bidirectional endpoints (ep1

... ep4) plus the default endpoint ep0. Endpoint ep0 only

supports control traffic. The enpoints ep1...ep4 can be pro-

grammed to support either control, bulk or interrupt traffic.

The maximum packet size is only restricted by the sum of

all IN endpoints. Maximum packet size is less than 1.5 KB.

USB Port 4 can be configured as a device by programming

the PMUX bit (UOC Memory Offset 04h[1:0]).

5.5.4 USB Option Controller

The basic functionality is to allow the software to assign the

shared USB Port 4 to either the host controller or the

device controller, and to provide additional information

about the status of the USB device port.

5.5.4.1 Port Multiplexing

The PMUX bit and its alias (UOC Memory Offset 0Ch[1:0])

are used to control the assignment of USB Port 4

(USB4_DATPOS (ball G17)/USB4_DATNEG (ball G16)) to

either the host or the device controller or to inactivate that

port.

Software must take precautions not to change port assign-

ment while USB traffic occurs on the USB Port 4, and must

first ensure that the currently associated controller has

ceased any USB traffic before changing the port assign-

ment. This may imply reading the appropriate controller

status registers or interacting with higher levels of the con-

troller software drivers.

PUEN (UOC Memory Offset 04h[2]) is only valid when the

Port 4 is assigned to the device controller.

AMD Geode™ CS5536 Companion Device Data Book 103

Diverse Integration Logic 33238G

5.6 Diverse Integration Logic

The Diverse Integration Logic (DIVIL) connects a series of

Local bus devices to the GeodeLink™ architecture. Figure

5-9 illustrates how the DIVIL (within the dashed lines) inter-

faces with the other devices of the Diverse Device. The

main blocks of the DIVIL are: Address Decode, Standard

MSRs, Local BARs, and Data Out Mux (DOM).

Figure 5-9. Diverse Logic Block Diagram

GLIU Interface

RI DI DO RO

8254 & Port B

(2) 8259A &

Kybd Emu &

System Mgmt

(2) UART & IR

IRQ Map

Port A

Bus Control

(2) 8237 &

LPC Bus

RTC & CMOS

DMA Map

Control

RAM

GPIO & ICF

MFGP Timers

Local Bus Interface

Pwr Mgmnt

NOR & NAND

Data Out

Data In

Flash Interfaces

and Control

External

I/O

Req/Ack

External

I/O

Address

External

I/O

External

I/O

External

I/O

Slave Addr

& Byte

Enables

RO Packet

Arguments

from MSR

Master Addr

& Byte

Enables

Local Bus

Handshake

Chip

Selects

Address Decode

and

Legacy Decode MSRs

Standard

MSRs

Local BARs,

Compares,

Address

Hits

GeodeLink™ Adapter (GLA)

DIVIL

*Data Out Mux not shown.

and

Miscellaneous

104 AMD Geode™ CS5536 Companion Device Data Book

Diverse Integration Logic

33238G

• Address Decode - Decodes the upper Local bus

address bits to select a target slave. Most of the legacy

devices have fixed addresses or are selectable between

a small number of selectable I/O addresses. However,

many of the functions are relocatable via a Local Base

Address Register (LBAR) established via an MSR.

Address Decode also detects special GLIU cycles, such

as Shutdown, and takes appropriate action.

•Standard MSRs - Includes the Standard GeodeLink

Device MSRs found in all GeodeLink Devices: Capabili-

ties, Master Configuration, SMI Control, Error Control,

Power Management, and Diagnostics.

• Local BARs - Local Base Address Registers (LBARs)

establish the location of non-legacy functions within the

Diverse Device. The module also includes logic to

compare the current bus cycle address to the LBAR to

detect a hit. For the I/O LBARs, the I/O address space

000h-4FFh is off limits. No I/O LBAR is allowed to point

to this space.

• Data Out Mux (DOM) - This mux is not explicitly illus-

trated. Each function above produces a single output to

the DIVIL. The DIVIL DOM has a port for each of the

functions and is responsible for selecting between them.

5.6.1 LBARs and Comparators

The LBARs are used to establish the address and hence,

chip select location of all functions that do not have fixed

legacy addresses. This block also has comparators to

establish when a current bus cycle address hits an LBAR.

A hit is passed to the address decode block and results in a

chip select to the target device if there are no conflicts. The

mask and base address values are established via an

MSR.

5.6.1.1 Fixed Target Size I/O LBARs

This discussion applies to the following LBARs:

•MSR 51400008h: IRQ Mapper (DIVIL_LBAR_IRQ)

•MSR 5140000Bh: SMB (DIVIL_LBAR_SMB)

•MSR 5140000Ch: GPIO and ICFs (DIVIL_LBAR_GPIO)

•MSR 5140000Dh: MFGPTs (DIVIL_LBAR_MFGPT)

•MSR 5140000Eh: ACPI (DIVIL_LBAR_ACPI)

•MSR 5140000Fh: Power Management Support

(DIVIL_LBAR_PMS)

The IO_MASK only applies to the upper bits [15:12] (see

Figure 5-10). Normally, one would set all the mask bits (i.e.,

no mask on upper bits). Mask or clear bits only if address

wrapping or aliasing is desired.

•Rule. When a mask bit is cleared, the associated bit in

the base address must also be cleared. Otherwise, the

compare is not equal on these bits. This rule applies to

both memory and I/O LBARs.

The base size is fixed based on the target. For example,

the GPIO takes 256 bytes of address space. Therefore, the

base only applies to bits [15:8]. Base bits [7:0] are always

cleared by the hardware. Therefore, the base is always

forced by hardware to be on a boundary the size of the tar-

get.

Figure 5-10. I/O Space LBAR - Fixed Target Size

ADDR[15:12] I/O_MASK Compare BASE_ADDR

Hit

[15:n]

[15:12]

Notes:

1) The I/O mask is always 4 bits.

2) The I/O base address is variable ([15:n]).

The value of “n” depends on the I/O space requirements of the target. For example, a device needing 4, 8, 16, 32,

64, 128, or 256 bytes of I/O space has “n” = 2, 3, 4, 5, 6, 7, 8, respectively. The value “n” for various functions is:

MSR_LBAR_IRQ n = 5 MSR_LBAR_SMB n = 3

MSR_LBAR_GPIO n = 8 MSR_LBAR_MFGPT n = 6

MSR_LBAR_ACPI n = 5 MSR_LBAR_PMS n = 7

MSR_LBAR_FLASH_IO n = 4

AMD Geode™ CS5536 Companion Device Data Book 105

Diverse Integration Logic 33238G

5.6.1.2 Variable Target Size I/O LBARs

This discussion applies to the following LBARs:

•MSR 51400010h: Flash Chip Select 0

(DIVIL_LBAR_FLSH0) with bit 34 = 0 (I/O mapped)

•MSR 51400011h: Flash Chip Select 1

(DIVIL_LBAR_FLSH1) with bit 34 = 0 (I/O mapped)

•MSR 51400012h: Flash Chip Select 2

(DIVIL_LBAR_FLSH2) with bit 34 = 0 (I/O mapped)

•MSR 51400013h: Flash Chip Select 3

(DIVIL_LBAR_FLSH3) with bit 34 = 0 (I/O mapped)

Note: Flash Chip Selects [3:0] can be programmed for

I/O or a memory space. See Section 5.6.1.3

"Memory LBARs".

The I/O LBAR works just like the Fixed style, except the

size of the IO_MASK has been expanded to cover the

entire address range (see Figure 5-11). In the Fixed style,

the IO_MASK applies to bits [15:12] but for Variable style,

the IO_MASK applies to bits [15:4]. If all bits are set, then

the target size is 16 bytes and base address bits [15:4]

determine the base. Base bits [3:0] are a “don't care” and

are effectively forced to zero by the hardware. Thus, the

smallest I/O target is 16 bytes. As the LSBs of IO_MASK

are cleared, the “target space” expands. For example,

assume a 64-byte device is desired in I/O space. The

IO_MASK = FFCh, base address bits [15:6] are pro-

grammed to the desired base, and base address bits [5:4]

are cleared (see Section 5.6.1.1, Rule on page 104).

5.6.1.3 Memory LBARs

This discussion applies to the following LBARs:

•MSR 51400009h: KEL from USB OHC

(DIVIL_LBAR_KEL)

•MSR 51400010h: Flash Chip Select 0

(DIVIL_LBAR_FLSH0) with bit 34 = 1 (memory mapped)

•MSR 51400011h: Flash Chip Select 1

(DIVIL_LBAR_FLSH1) with bit 34 = 1 (memory mapped)

•MSR 51400012h: Flash Chip Select 2

(DIVIL_LBAR_FLSH2) with bit 34 = 1 (memory mapped)

•MSR 51400013h: Flash Chip Select 3

(DIVIL_LBAR_FLSH3) with bit 34 = 1 (memory mapped)

Note: The Flash Chip Selects [3:0] can be programmed

for an I/O space or a memory space.

For memory space, the LBAR works exactly like the Vari-

able style (see Figure 5-12), except that clearing the LSBs

of the MEM_MASK begins to make sense. For example,

assume there is a 64 KB external ROM that will be con-

nected to Flash Chip Select 0. Such a device needs

address bits [15:0]. The MEM_MASK would normally be

programmed to FFFF0h and base address bits [31:16]

would be programmed to the desired base. The values in

base address [15:12] would be cleared because the asso-

ciated mask bits are cleared (see Section 5.6.1.1, Rule on

page 104). Lastly, the memory target cannot be smaller

than 4 KB.

Figure 5-11. I/O Space LBAR - Variable Target Size

Figure 5-12. Memory Space LBAR

ADDR[15:4] I/O_MASK Compare BASE_ADDR

Hit

[15:4]

ADDR[31:12] MEM_MASK Compare BASE_ADDR

Hit

[31:12]

Note: The memory mask is always 20 bits, which is equal to the number of memory base address bits.

106 AMD Geode™ CS5536 Companion Device Data Book

Diverse Integration Logic

33238G

5.6.1.4 Miscellaneous Block

Special cycles are sent to the Miscellaneous block. They

are decoded as given in Table 5-10. Note that the Halt spe-

cial cycle depends on the value of the SPEC_CYC_MD bit

(DIVIL MSR 51400014h[28]).

Soft IRQ and Soft Reset MSRs are decoded within the Mis-

cellaneous block.

Each block in the Diverse Device generates an output to

the DIVIL. The DIVIL DOM has a port for each of the func-

tions and is responsible for selecting between them.

5.6.2 Standard MSRs

This block contains the Standard GeodeLink Device MSRs

and their associated logic: Capabilities, Master Configura-

tion, SMI Control, Error Control, Power Management, and

Diagnostics. The Capabilities, Master Configuration, and

Diagnostic MSRs are “passive” in that they contain values

that have an effect elsewhere. The other MSRs have vari-

ous “active” bits that are set and cleared via hardware/soft-

ware interactions.

Table 5-10. Special Cycle Decodes

Cycle Type Address Function Action

Write 00h Shutdown Send shutdown pulse to MSR_ERROR.

Send shutdown pulse to MSR_SMI.

If RESET_SHUT_EN (MSR 51400014h[31]) is high, send reset

pulse to power management indicating shutdown reset.

SPEC_CYC_MD (MSR 51400014h[28]) = 0

Write 01h Halt Send halt pulse to MSR_SMI.

SPEC_CYC_MD (MSR 51400014h[28]) = 1

Write 02h Halt Send halt pulse to MSR_SMI.

All other values x86 Special Discard with no side effects.

All other values Not Defined Discard with no side effects.

Read 00h Interrupt ACK Send cycle to PIC.

GeodeLink Adapter generates back-to-back bus cycles.

All other values Not Defined Return zero with no side effects.

AMD Geode™ CS5536 Companion Device Data Book 107

Programmable Interval Timer 33238G

5.7 Programmable Interval Timer

The Programmable Interval Timer (PIT) generates pro-

grammable time intervals from the divided clock of an

external clock signal of a crystal oscillator. The PIT (8254)

has six modes of operation. Figure 5-13 shows the block

diagram of the PIT and its connectivity to the Local bus.

The 8254 is comprised of three independently programma-

ble counters. Each counter is 16 bits wide. A 14.318 MHz

external clock signal (from a crystal oscillator or an external

clock chip) is divided by 12 to generate 1.19 MHz, which is

used as a clocking reference for these three counters.

Each counter is enabled or triggered with its GATE signal.

Based on the counting mode, the counter concerned is

activated by a high level or a low-to-high transition of its

GATE signal.

Each counter has its output signal, whose shape is depen-

dent upon the counter’s operational mode. The Control reg-

ister loads the counters and controls the various modes of

operation. This Control register controls the operation

mode of the control logic (counter state machine), which in

turn controls the counter, the high-order and low-order out-

put latches. A status latch is also present in the 8254 and is

used to output status information.

Features include:

•Comprised of three 16-bit wide counters.

•Supports read-back and counter latch commands.

•Supports six modes of counting.

•Allows several counter latch commands in parallel with

the read-back command.

Figure 5-13. PIT Block Diagram

CPU

Local Bus

PIT Shadow Divide By 12

Timer 0 Timer 1 Timer 2

GeodeLink™ Adapter (GLA)

Control

14 MHz

RegisterRegister

108 AMD Geode™ CS5536 Companion Device Data Book

Programmable Interval Timer

33238G

5.7.1 Programming the 8254 PIT

Programming of the 8254 PIT is initiated by first writing one

control WORD via I/O Address 43h into the PIT Mode Con-

trol Word register (PIT I/O Address 43h). It is followed by

writing one or two data bytes via the I/O address of the

intended counter. If the Control register is loaded once, the

counters may be overwritten with different values without

accessing the Control register again. Table 5-11 lists the

I/O addresses of the various registers.

The Control register in the 8254 PIT is write-only, but cer-

tain control information can be determined by the read-

back (read-status) command.

5.7.1.1 Write to the Counters

To load a counter with new values, a control WORD must

output what defines the intended counter, number, and

type of bytes to write, the counting mode and the counting

format. I/O Address 43h[5:4] indicate whether low-order or

high-order or both are going to be written. If low-order or

high-order counter byte only is specified to be written, then

only that byte can be read during a read access. According

to bits I/O Address 43h[5:4], either write the low-order or

the high-order or both into the counter after passing the

control WORD. If bits [5:4] are 11, then a low-order byte

must be written first, followed by a high-order byte. For

small counting values or counting values that are multiples

of 256, it is sufficient to pass the low-order or high-order

counter byte. I/O Address 43h[3:1] define the counting

mode of the counter selected by bits [5:4]. I/O Address

43h[0] defines the binary or BCD counting format. The

maximum loadable count value is not FFFFh (binary count-

ing) or 9999 (BCD counting), but 0. On the next CLK pulse,

the counter concerned jumps to FFFFh or 9999. Once the

value is decreased to 0 again, it outputs a signal according

to the programmed mode. Therefore, the value 0 corre-

sponds to 2^16 for binary counting and 10^4 for BCD

counting.

Read from the Counters

There are three options for reading a counter in the 8254

PIT:

1) Counter Latch command

2) Read-back (read-status) command

3) Direct Read

To read a counter, the third option (Direct Read) should not

be used. The Counter Latch command or Read-back com-

mand should be used to transfer the current state of the

counter into its output latches. One or two successive read

counter instructions for the port address of the counter con-

cerned reads these latches. If only the low-order or high-

order byte was written when the counter was loaded with

the initial counting value, then read the current counting

value of the initially written byte by a single read counter

instruction. If both the low-order and high-order counter

bytes are written previously, then to read the current

counter value, two read counter instructions are needed.

The 8254 PIT returns the low-order byte of the 16-bit

counter with the first read counter instruction, and then the

high-order byte with the second read counter instruction. If

the content of the counter has been transferred once by a

counter latch command into the output latches, then this

value is held there until the CPU executes one or two

counter read instructions, or until the corresponding

counter is reprogrammed. Successive counter latch com-

mands are ignored if the output latches have not been read

before. Figure 5-14 shows the format of the control WORD

for the counter latch command.

Figure 5-14. PIT Counter Latch Command Format

Table 5-11. 8254 PIT Register Ports

I/O Address Register Access Type

040h Counter 0 Read/ Write

041h Counter 1 Read / Write

042h Counter 2 Read / Write

043h Control Word Write

Bits [7:6] = Select counter to latch

76543210

00xxxx

AMD Geode™ CS5536 Companion Device Data Book 109

Programmable Interval Timer 33238G

The Read-back command present in the 8254 PIT is used

to determine the current counter value and its status-like

counting format, the counting mode, the low-order or high-

order byte or both, being read or written, and the status of

its output. Figure 5-15 shows the format of the Read-back

command. The two most significant bits define the Read-

back command with their value 11. CT and ST indicate that

the value and the status of the counter are to be deter-

mined respectively. The C0-C2 bits define the counter

whose value or status is to be determined. With the Read-

back command, several counter latch commands can be

issued in parallel by indicating several counters simulta-

neously with the C0-C2 bits. The 8254 then behaves as if

several counter latch commands have been issued individ-

ually, and transfers the individual count values into the out-

put latches of each counter. All successive counter latch

commands, whether issued by its own counter or a next

Read-back command, are ignored if the counter concerned

has not been read by counter read instructions. To deter-

mine the programmed mode of a particular counter, set

CT = 1 and ST = 0.

The Read-back command latches the current mode and

provides a status byte (see Figure 5-16) at the port address

of the counter concerned. This status byte is fetched by a

counter read instruction. The PIN bit indicates the current

status of the concerned counter’s output pin. If PIN = 1,

then the counter output is at logic 1, else at logic 0. Bit 0

shows whether the last written counter value has already

been transferred to the counter. Not before zero = 0 is it

meaningful to read back the counter value.

Figure 5-15. PIT Read-Back Command Format

Figure 5-16. PIT Status Byte Format

CT: Determine count value of selected counter.

0 = Determine count value.

1 = Do not determine count value.

ST: Determine status of selected counter.

0 = Determine count status.

1 = Do not determine count status.

C2, C1, C0: Counter selection.

0 = Counter not selected.

1 = Counter selected.

76543210

CT ST C2 C1 C0 x11

PIN: Status of counter output pin:

0 = Output pin low.

1 = Output pin high.

LOAD: Is counter loaded with a start value?

0 = Counter loaded, count value can be read.

1 = Counter not yet loaded, count value cannot be read.

LH: Corresponds to bits [5:4] of the Control Word register.

MODE: Corresponds to bits [3:1] of the Control Word register.

BCD: Corresponds to bit 0 of the Control Word register.

76543210

LH MODE BCDLOADPIN

110 AMD Geode™ CS5536 Companion Device Data Book

Programmable Interrupt Control

33238G

5.8 Programmable Interrupt Control

The Programmable Interrupt Control (PIC) is illustrated in

Figure 5-17. The major blocks are the Mapper and Masks

(MM), Extended PIC (XPIC), and Legacy 8259A PICs

(LPIC).

Features

•Two x86 compatible 8259A controllers

•15-Level priority controller

•Programmable interrupt modes

•Individual request mask capability

•Individual edge/level controls

•Complete 8259A state read back via shadow registers

•Mapper routes 62 inputs to 15 legacy interrupts and one

Asynchronous System Management Interrupt (ASMI)

•All 62 inputs individually maskable and status readable

(MSRs 51400020h-51400027h or PIC I/O Offsets 00h-

1Ch)

5.8.1 Mapper and Masks

This block maps and masks up to 62 interrupt sources to

60 discrete Extended PIC (XPIC) inputs. The sources are

organized into four groups:

1) 15 Primary pre-defined inputs (see Table 5-12)

2) 15 LPC inputs pre-defined (see Table 5-12)

3) 16 Unrestricted Y inputs (see Table 5-13)

4) 16 Unrestricted Z inputs (see Table 5-14)

The outputs are organized into 16 groups of four signals

each, except groups 0 and 2; they have two signals each.

Each group is called an Interrupt Group (IG). Each pre-

defined input is mapped to a specific IG. Each unrestricted

input can be mapped to any IG except IG0. Regardless of

mapping, any interrupt source can be masked to prevent

participation in the interrupt process. Once the input to out-

put map is established along with the mask values, signal

flow from input to output is always completely combina-

tional.

Figure 5-17. PIC Block Diagram

Primary Input 0

Primary Input 1

Primary Input 3

Primary Input 4

Primary Input 15

LPC Input 0

LPC Input 1

LPC Input 3

LPC Input 4

LPC Input 15

Unrestricted Y Input 0

Unrestricted Y Input 1

Unrestricted Y Input 2

Unrestricted Y Input 3

Unrestricted Y Input 15

Unrestricted Z Input 0

Unrestricted Z Input 1

Unrestricted Z Input 2

Unrestricted Z Input 3

Unrestricted Z Input 15

Mapper

and

Masks

(MM)

IG0 (Note)

IG1

IG2 (Note)

IG3

IG4

IG5

IG6

IG7

IG8

IG9

IG10

IG11

IG12

IG13

IG14

IG15

IRQ0

IRQ1

(IRQ2)

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Extended

PIC

(XPIC)

Legacy

8259A

PICs

(LPIC)

ASMI

INTR

Note: The outputs are organized into 16 groups of four signals each, except IG0 and IG2; they have two signals each.

AMD Geode™ CS5536 Companion Device Data Book 111

Programmable Interrupt Control 33238G

Table 5-12. IRQ Map - Primary and LPC

Input # Primary Sources LPC Sources Legacy IRQ

Input 0 8254 Timer IRQ LPC IRQ0 8254 Timer

Input 1 KEL IRQ1 LPC IRQ1 Keyboard

N/A None (Slave Controller) None None

Input 3 Reserved - Grounded LPC IRQ3 UART

Input 4 Reserved - Grounded LPC IRQ4 UART

Input 5 Reserved - Grounded LPC IRQ5 Parallel Port 2

Input 6 Reserved - Grounded LPC IRQ6 Floppy

Input 7 Reserved - Grounded LPC IRQ7 Parallel Port 1

Input 8 RTC Periodic IRQ LPC IRQ8 RTC

Input 9 Reserved - Grounded LPC IRQ9 Undefined

Input 10 Reserved - Grounded LPC IRQ10 Undefined

Input 11 Reserved - Grounded LPC IRQ11 Undefined

Input 12 KEL IRQ12 LPC IRQ12 Mouse

Input 13 Float Point Error IRQ LPC IRQ13 FPU

Input 14 Primary IDE Channel IRQ LPC IRQ14 Primary IDE

Input 15 Reserved - Grounded LPC IRQ15 Secondary IDE

Table 5-13. IRQ Map - Unrestricted Sources Y

Unrestricted Y Source Comment

Input 0 Software Generated IRQ

Input 1 Reserved - Grounded

Input 2 USB IRQ

Input 3 RTC Alarm This is a pulse from the RTC. Must use edge triggered inter-

rupt, that is, level interrupt will not work.

Input 4 Audio IRQ OR of all audio codec interrupts and master interrupts.

Input 5 Power Management SCI OR of all possible power management System Control Inter-

rupts (SCIs).

Input 6 NAND Flash Ready Ready to perform NAND write or read.

Input 7 NAND Flash Distraction NOR access occurred during NAND operation causing a

NAND abort or distraction.

Input 8 Reserved, Grounded

Input 9 Reserved, Grounded

Input 10 Reserved, Grounded

Input 11 Reserved, Grounded

Input 12 SMB Controller IRQ

Input 13 KEL Emulation IRQ

Input 14 UART 1 IRQ

Input 15 UART 2 IRQ

112 AMD Geode™ CS5536 Companion Device Data Book

Programmable Interrupt Control

33238G

5.8.2 Extended PIC (XPIC)

For each of 16 input IGs of four signals each (except IG0

and IG2 with two signals each), XPIC provides a four input

“OR”. Thus, 16 outputs are formed. A software readable

XPIC Input Request register is available to read the status

of the 64 inputs. Outputs [0:1] and [3:15] are connected

directly to the corresponding inputs on LPIC. Output 2 can

be used as an ASMI.

5.8.3 Legacy PIC (LPIC)

The LPIC consists of two 8259A compatible Programmable

Interrupt Controllers (PICs) connected in Cascade mode

through interrupt signal two (see Figure 5-18). LPIC con-

tains mechanisms to:

1) Mask any of the 15 inputs via an Interrupt Mask Regis-

ter (IMR).

2) Determine the input request status via an Interrupt

Request Register (IRR).

3) Generate an interrupt request (INTR) to the processor

when any of the unmasked requests are asserted.

4) Provide an interrupt vector to the processor as part of

an interrupt acknowledge operation based on request

priorities.

5) Determine which requests are acknowledged but not

yet fully serviced, via an In-Service (ISR) register.

In addition to the above 8259A features, there are two reg-

isters to control edge/level mode for each of the interrupt

inputs (PIC I/O Address 4D0h and 4D1h) as well as a

shadow register to obtain the values of legacy 8259A regis-

ters that have not been historically readable (MSR

51400034h).

Figure 5-18. Cascading 8259As for LPIC

Table 5-14. IRQ Map - Unrestricted Sources Z

Unrestricted Z Source Comment

Input 0 MFGPT_Comp_1A OR of MFGPT_Comp_1 0 and 4.

Input 1 MFGPT_Comp_1B OR of MFGPT_Comp_1 1 and 5.

Input 2 MFGPT_Comp_1C OR of MFGPT_Comp_1 2 and 6.

Input 3 MFGPT_Comp_1D OR of MFGPT_Comp_1 3 and 7.

Input 4 MFGPT_Comp_2A OR of MFGPT_Comp_2 0 and 4.

Input 5 MFGPT_Comp_2B OR of MFGPT_Comp_2 1 and 5.

Input 6 MFGPT_Comp_2C OR of MFGPT_Comp_2 2 and 6.

Input 7 MFGPT_Comp_2D OR of MFGPT_Comp_2 3 and 7.

Input 8 GPIO Interrupt 0 From GPIO Interrupt/PME Mapper.

Input 9 GPIO Interrupt 1 From GPIO Interrupt/PME Mapper.

Input 10 GPIO Interrupt 2 From GPIO Interrupt/PME Mapper.

Input 11 GPIO Interrupt 3 From GPIO Interrupt/PME Mapper.

Input 12 GPIO Interrupt 4 From GPIO Interrupt/PME Mapper.

Input 13 GPIO Interrupt 5 From GPIO Interrupt/PME Mapper.

Input 14 GPIO Interrupt 6 From GPIO Interrupt/PME Mapper.

Input 15 GPIO Interrupt 7 From GPIO Interrupt/PME Mapper.

8259A Slave 8259A Master

INTA INT

INTINTA D0-D7D0-D7

IRQ0IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

Note: Cascading the 8259A PICs. The INT output of the slave is connected to the IRQ2 input of the master.

AMD Geode™ CS5536 Companion Device Data Book 113

Programmable Interrupt Control 33238G

As illustrated in Figure 5-19, the blocks that make up the

8259A PIC are:

•Read/Write Logic

•Interrupt Request Register (IRR)

•In-Service Register (ISR)

•Interrupt Mask Register (IMR)

•Priority Resolver

•Control Logic

•Data Bus Buffer

•Cascade Buffer/Comparator

Read/Write Logic

The function of this block is to accept commands from the

processor. It contains the four Initialization Command Word

registers, PIC_ICW1-PIC_ICW4, and three Operation

Command Word registers, PIC_OCW1-PIC_OCW3, that

can be programmed to operate in various modes.

IRR, ISR, and IMR

Three registers are available to handle interrupts in the

PIC. Each of the three registers is eight bits wide, where

every bit corresponds to one of the IR0-IR7 input lines.

Priority Resolver

The priority resolver block manages the hardware requests

according to their priority. As several bits may be set in the

IRR simultaneously, the priority encoder passes only the

highest priority bit; ordered in priority 0 through 7 (0 being

the highest).

Control Logic

The INT output goes directly to the CPU interrupt input.

When an INT signal is activated, the CPU responds with an

Interrupt Acknowledge access that is translated to two

pulses on the INTA input of the PIC. At the first INTA pulse,

the highest priority IRR bit is loaded into the corresponding

ISR bit, and that IRR bit is reset. The second INTA pulse

instructs the PIC to present the 8-bit vector of the interrupt

handler onto the data bus.

Data Bus Buffer

Control WORDs and status information are transferred

through the data bus buffer.

Cascade Buffer/Comparator

This functional block stores and compares the IDs of the

PICs.

Figure 5-19. PIC 8259A Block Diagram

Internal Bus

Interrupt Mask Register

(IMR)

In-Service

(ISR)

Priority

Resolver

Interrupt

Request

(IRR)

Control Logic

Data

Bus

Buffer

Read/

Write

Logic

Cascade

Buffer/

Comparator

INTA INT

D7-D0

CAS0

CAS1

CAS2

SP/EN

IR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

114 AMD Geode™ CS5536 Companion Device Data Book

Programmable Interrupt Control

33238G

5.8.3.1 Interrupt Sequence

Three registers in the PIC control interrupt requests and

eight interrupt lines (IR0-IR7) are connected to the IRR.

The peripheral that requests an interrupt raises the signal

at the corresponding IR0-IR7 inputs, which sets the corre-

sponding bit in the IRR. Several peripheral devices can

issue interrupt requests at the same time. The PIC gates

these requests under the IMR and under the priority of any

interrupt service routine already entered (using the ISR),

and activates the PIC’s output INTR to the processor. The

processor acknowledges the INTR, generating two INTA

pulses. On the first, the priority encoder transfers (clears)

the highest-priority enabled bit in the IRR to the corre-

sponding bit in the ISR (sets). Also, the two PICs use their

Cascade connections to decide which one will be selected

to respond further. On the second INTA pulse, the selected

PIC presents the 8-bit pointer (called as vector data) onto

the data bus. The processor reads this pointer as the num-

ber of the interrupt handler to call.

Software writes a command (EOI) at the end of the inter-

rupt subroutine, which clears the appropriate ISR bit.

Initialization and Programming

Two types of command words are generated by the proces-

sor to program the PIC:

1) Initialization Command Word (ICW): The PIC is first

initialized by four ICWs (ICW1-ICW4) before any nor-

mal operation begins. The sequence is started by writ-

ing Initialization Command Word 1 (ICW1). After ICW1

has been written, the controller expects the next writes

to follow in the sequence ICW2, ICW3, and ICW4 if it

is needed.

2) Operation Command Word (OCW): Using these

three OCWs (OCW1-OCW3), the PIC is instructed to

operate in various interrupt modes. These registers

can be written after the initialization above.

ICWs and OCWs must be programmed before operation

begins.

Since both the PICs are cascaded, ICW3 of the PIC master

should be programmed with the value 04h (PIC I/O Port

021h[7:0]), indicating that the IRQ2 input of the master PIC

is connected to the INT output of the slave PIC, rather than

the I/O device. This is part of the system initialization code.

Also, ICW3 of the slave PIC should be programmed with

the value 02h (I/O Port 0A1h[7:0]) as that corresponds to

the input on the master PIC.

For accessing the PIC’s registers, two ports are available

for the master and slave. Table 5-15 lists the addresses

and read/write data for these registers.

5.8.3.2 Interrupt Modes

Fully Nested Mode

The interrupt requests are ordered in priority from 0

through 7.

The highest priority request is processed and its vector

data placed on the bus.

The corresponding ISR bit is set until the trailing edge of

the last INTA. While the ISR bit is set, all other interrupts of

the same or lower priority are inhibited, while higher levels

are acknowledged only if the processor internal interrupt

enable flip-flop has been re-enabled through software.

End of Interrupt (EOI) Mode

The ISR bit can be reset by a command word that must be

issued to the PIC before returning from a service routine.

EOI must be issued twice if in cascade mode, once for the

master and once for the slave.

There are two forms of EOI: Specific and Non-Specific.

When a non-specific EOI is issued, the PIC automatically

resets the ISR bit corresponding to the highest priority level

in service. A non-specific EOI can be issued with OCW2

(EOI = 1, SL = 0, R = 0).

A specific EOI is issued when a mode is used that may dis-

turb the fully nested structure and the PIC might not be

able to determine the last interrupt level acknowledged. A

specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R

= 0, and L0-L2 is the binary level of the ISR bit to be reset).

Automatic End of Interrupt (AEOI) Mode

The PIC automatically performs a non-specific EOI at the

trailing edge of the last INTA pulse. This mode is not sup-

ported in the CS5536 companion device.

Table 5-15. 8259A PIC I/O Addresses and I/O Data

I/O Address

IRQ0-IRQ7

(Master)

I/O Address

IRQ8-IRQ15

(Slave)

Read

Data

Write

Data

020h 0A0h IRR

ISR

ICW1

OCW2

OCW3

021h 0A1h IMR ICW2

ICW3

ICW4

OCW1 (IMR)

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Programmable Interrupt Control 33238G

Automatic Rotation Mode

In cases where a number of IRQs have equal priority, the

device that has been serviced receives the lowest priority.

That device, if requesting another interrupt, must wait until

the other seven devices have been serviced.

There are two ways to accomplish automatic rotation using

OCW2:

•Rotation on the non-specific EOI command (R = 1, SL =

0, EOI = 1).

•Rotation in automatic EOI mode, which is set by (R = 1,

SL = 0, EOI = 0) and cleared by (R = 0, SL = 0, EOI = 0).

Specific Rotation Mode

Priorities can be changed by programming the bottom pri-

ority, which fixes all other priorities. For example, if IRQ5 is

programmed as the bottom priority device, then IRQ6 has

the highest priority. The command is issued to OCW2 (R =

1, SL = 1, and L0-L2 is the binary priority level code of the

bottom priority device).

Special Mask Mode

In this mode, when a mask bit is set in OCW1, it inhibits fur-

ther interrupts at that level and enables interrupts from all

other levels (lower as well as higher) that are not masked.

The special mask mode is set (SSMM = 1, SMM = 1) and

cleared (SSMM = 1, SMM = 0) by OCW3.

5.8.4 PIC Operation

From reset, the PIC device comes up in legacy mode. The

“Primary” mapper and mask inputs connect directly to LPIC

and all other interrupt sources are masked off.

While there are a number of different ways to use the PIC,

the discussions that follow assume a mix of level and edge

interrupt inputs. The first discussion assumes the operating

system schedules the work of the interrupt service after a

brief interrupt service routine. The second discussion

assumes the operating system performs the work real-time

in the interrupt service routine.

Assume the mapper and masks have been established as

desired. Level interrupts can be shared, but edge interrupts

cannot. This means an XPIC level output can be driven by

up to four mapper and mask inputs. Further, this means an

XPIC edge output can only be driven by one mapper and

mask input.

Assume all edge interrupts generate a low-to-high edge to

indicate an interrupt. Assume active low interrupts are

inverted outside the PIC device as needed; that is, all MM

inputs are active high. An external PCI bus uses active low

interrupts that can be shared in an open-collector wired

“OR” fashion. This is OK. On-chip, the interrupt sense is

inverted. Lastly, note that for the edge interrupts, the edge

must remain high until the interrupt acknowledge action.

Assume LPIC is initialized as follows:

;Set Initialization Command Words (ICWs)

;All values are in hex

;PIC #1 (Master)

out 20, 11 ; ICW1 - Edge, Master, ICW4 needed

out 21, 8 ; ICW2 - Interrupt vector table offset is 8

out 21, 4 ; ICW3 - Master level 2

out 21, 1 ; ICW4 - Master, 8086 mode

out 21, ff ; mask all IRQs

;PIC #2 (Slave)

out a0, 11 ; ICW1 - Edge, Slave ICW4 needed

out a1, 70 ; ICW2 - Interrupt vector table offset 70

out a1, 2 ; ICW3 - Slave Level 2

out a1, 1 ; ICW4 - Slave, 8086 mode

out a1, ff ; mask all IRQs

;Use Operation Control Words (OCWs) during interrupt

service

Thus, the LPIC 8259As all start in edge mode. This is fol-

lowed by writes to the individual edge level registers at

4D0h (interrupts 0-7) and 4D1h (interrupts 8-15) to estab-

lish level mode for all level inputs. Note that IRQ0 and IRQ2

can not be put in level mode. Writing 0FFh to 4D0h reads

back 0FAh.

Scheduled Interrupts Approach

The following set of events is typical. Assume the proces-

sor has maskable interrupts enabled:

1) One or more interrupts are generated in the system.

These set the associated bits in the LPIC Interrupt

Request register.

2) The maskable interrupt signal (INTR) is asserted by

the LPIC and interrupts the processor. INTR is an

active high level.

3) The processor generates an interrupt acknowledge

bus cycle that flows through the GeodeLink™ system

as a single BIZZARO packet. When it reaches the

Diverse Logic, it is converted to the two cycle interrupt

acknowledge sequence expected by the LPIC.

4) The acknowledge operation returns an interrupt vector

to the processor that is used to call the appropriate

interrupt service routine. Processor interrupts are now

disabled at the processor.

5) The acknowledge operation also selects the highest

priority interrupt from the IRR and uses it to set one bit

in the LPIC ISR. Each acknowledge operation always

sets a single ISR bit.

116 AMD Geode™ CS5536 Companion Device Data Book

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6) The acknowledge operation generally de-asserts INTR

if there are no higher priority interrupts. However, it is

possible that another interrupt is generated in the sys-

tem anytime after the acknowledge. Any new inter-

rupts will appear in the IRR. If they are higher priority

than the current interrupt, then the INTR is re-

asserted. Since interrupts are disabled at the proces-

sor, INTR remaining high or going high during the

interrupt service routine has no effect until interrupts

are explicitly enabled again at the processor by the

interrupt service routine or implicitly enabled when a

return-from-interrupt is executed.

7) The interrupt service routine masks off the interrupt in

the LPIC IMR. The interrupt service routine interacts

with the operating system to schedule calls to the driv-

ers associated with the interrupt. If level, one or more

drivers could be associated. If edge, only one driver

could be associated. The service executes a return-

from-interrupt.

8) The operating system calls the drivers associated with

the interrupt as scheduled. Each driver checks its

associated device to determine service needs. If no

“need”, the driver returns to the operating system with-

out any action. If “need”, the driver performs the inter-

rupt action, clears the interrupt source, and returns to

the operating system. When all the scheduled drivers

have been called, the operating system un-masks the

interrupt at LPIC. Note that the individual drivers do

not directly interact with LPIC.

Note in the above procedure that there is no need to han-

dle level and edge types separately as long as edge types

are not shared.

Real-Time Interrupts Approach

The following discussion assumes the work associated

with the interrupt is performed in the interrupt service rou-

tine. The setup and steps 1 through 6 are the same:

1) If there is only one driver associated with the interrupt,

it is called at this point. If more than one driver

(shared), then they could be called in order to deter-

mine “need”. Alternately, the XPIC Input Request reg-

ister could be read to directly identify the source.

2) Depending on the event being serviced and the oper-

ating system policies, the processor will enable inter-

rupts again at some point. Potentially, this will generate

another higher priority interrupt causing the current

service routine to nest with another interrupt acknowl-

edge cycle. For a nest operation, an additional bit will

be set in the ISR.

3) Eventually, the highest priority service routine is run-

ning and INTR is de-asserted. The service calls the

driver(s) associated with the interrupt. The driver com-

pletes the interrupt “work”, clears the interrupt at its

system source, and returns to the interrupt service

routine.

4) The interrupt service routine disables interrupts at the

processor and prepares to return to a lower priority

service routine or the initially interrupted process. It

writes an end-of-interrupt (EOI) command (020h) to

the PIC_OCW2 register. This clears the highest prior-

ity ISR bit. One EOI always clears one ISR bit. The

service routine executes a return-from-interrupt that

enables interrupts again at the processor.

5) It is possible for INTR to assert from the same interrupt

as soon as EOI is written. The initial interrupt acknowl-

edge action copies the bit to the ISR. For edge mode,

the initial interrupt acknowledge action also clears the

bit in the IRR. For level, the IRR always reflects the

level of the signal on the interrupt port. After the inter-

rupt acknowledge for edge mode, another edge could

set the bit in the IRR before the EOI. If in level mode,

another shared interrupt could be keeping the input

high or potentially the initial interrupt has occurred

again, since the driver cleared the source but before

the EOI. At any rate, if the IRR is high at EOI, INTR will

immediately assert again. Hence, the need to disable

interrupts at the processor before writing the EOI.

6) Eventually, all system events are serviced and control

returns to the originally interrupted program.

Note that the above procedure did not use the IMR, but

variations on the above could have. Lastly note, as in the

first discussion, drivers do not directly interact with the

LPIC.

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5.9 Direct Memory Access Controller

The Direct Memory Access (DMA) controller supports

industry standard DMA architecture using two 8237-com-

patible DMA controllers in cascaded configuration. Figure

5-20 shows the DMA controller partitioning. It consists of

two standard 8237 DMA controllers, a bus interface,

address mapper, and source mapper.

Features

•32-bit address range support via high page registers.

•Supports the standard 7-channel DMA configuration, out

of which the four 8-bit channels are used.

•DMA mapper to route DMA sources to the four 8-bit

DMA channels.

•DMA sources from the LPC bus, and from transmit and

receive buffers from the two on-chip UARTs are

supported.

•Allows the data bus to be released in between DMA

transfers during demand or bulk mode to allow transfers

to the DMA controller or the module doing DMA trans-

fers.

5.9.1 DMA Controllers

The Core Logic supports seven DMA channels using two

standard 8237-equivalent controllers. DMA Controller 1

contains Channels 0 through 3 and supports 8-bit I/O

adapters. These channels are used to transfer data

between 8-bit peripherals and system memory. Using the

high and low page address registers, a full 32-bit address

is output for each channel so they can all transfer data

throughout the entire 4 GB system address space. Each

channel can transfer data in 64 KB pages.

DMA Controller 2 is unused.

Figure 5-20. DMA Controller Block Diagram

8237

Data LBus I/F

LPC I/F

DMA R/W Controls

DMA Requests

DMA Acks

Bus Interface

and Registers

LPC and DMA

Interfaces with

DMA mapper

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5.9.2 DMA Transfer Modes

Each DMA channel can be programmed for single, block,

demand, or cascade transfer modes. In the most commonly

used mode, single transfer mode, one DMA cycle occurs

per DMA Request (DRQ) and the PCI bus is released after

every cycle. This allows the Core Logic to timeshare the

PCI bus with the AMD Geode LX processor. This is impera-

tive, especially in cases involving large data transfers,

because the AMD Geode LX processor gets locked out for

too long.

In block transfer mode, the DMA controller executes all of

its transfers consecutively without releasing the PCI bus.

In demand transfer mode, DMA transfer cycles continue to

occur as long as DRQ is high or terminal count is not

reached. In this mode, the DMA controller continues to exe-

cute transfer cycles until the I/O device drops DRQ to indi-

cate its inability to continue providing data. For this case,

the PCI bus is held by the Core Logic until a break in the

transfers occurs.

In the CS5536 companion device design, block and

demand transfers behave much like single transfer mode to

avoid the lockout problem.

In cascade mode, the channel is connected to another

DMA controller or to an ISA bus master, rather than to an

I/O device. In the Core Logic, one of the 8237 controllers is

designated as the master and the other as the slave. The

HOLD output of the slave is tied to the DRQ0 input of the

master (Channel 4), and the master’s DACK0# output is

tied to the slave’s HLDA input.

In each of these modes, the DMA controller can be pro-

grammed for read, write, or verify transfers.

Both DMA controllers are reset at power-on reset (POR) to

fixed priority. Since master Channel 0 is actually connected

to the slave DMA controller, the slave’s four DMA channels

have the highest priority, with Channel 0 as highest and

Channel 3 as the lowest. Immediately following slave

Channel 3, master Channel 1 (Channel 5) is the next high-

est, followed by Channels 6 and 7.

5.9.3 DMA Controller Registers

The DMA controller can be programmed with standard I/O

cycles to the standard register space for DMA.

When writing to a channel's address or WORD Count reg-

ister, the data is written into both the base register and the

current register simultaneously. When reading a channel

address or WORD Count register, only the current address

or WORD Count can be read. The base address and base

WORD Count are not accessible for reading.

5.9.4 DMA Transfer Types

Each of the seven DMA channels may be programmed to

perform one of three types of transfers: read, write, or ver-

ify. The transfer type selected defines the method used to

transfer a byte or WORD during one DMA bus cycle.

For read transfer types, the DMA controller reads data from

memory and writes it to the I/O device associated with the

DMA channel.

For write transfer types, the DMA controller reads data from

the I/O device associated with the DMA channel and writes

to the memory.

The verify transfer type causes the DMA controller to exe-

cute DMA transfer bus cycles, including generation of

memory addresses, but neither the READ nor WRITE com-

mand lines are activated. This transfer type was used by

DMA Channel 0 to implement DRAM refresh in the original

IBM PC and XT.

5.9.5 DMA Priority

The DMA controller may be programmed for two types of

priority schemes: fixed and rotate.

In fixed priority, the channels are fixed in priority order

based on the descending values of their numbers. Thus,

Channel 0 has the highest priority. In rotate priority, the last

channel to get service becomes the lowest-priority channel

with the priority of the others rotating accordingly. This pre-

vents a channel from dominating the system.

The address and WORD Count registers for each channel

are 16-bit registers. The value on the data bus is written

into the upper byte or lower byte, depending on the state of

the internal addressing byte pointer. This pointer can be

cleared by the Clear Byte Pointer command. After this com-

mand, the first read/write to an address or WORD-count

and the byte pointer points to the high byte. The next

read/write to an address or WORD-count register reads or

writes to the high byte of the 16-bit register and the byte

pointer points back to the low byte.

The DMA controller allows the user to program the active

level (low or high) of the DRQ and DACK# signals. Since

the two controllers are cascaded together internally on the

chip, these signals should always be programmed with the

DRQ signal active high and the DACK# signal active low.

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5.9.6 DMA Shadow Registers

The DMA controller contains shadow registers (see Sec-

tion 6.13 on page 447) for reading the configuration of the

DMA controllers.

5.9.7 DMA Addressing Capability

DMA transfers occur over the entire 32-bit address range of

the PCI bus. This is accomplished by using the DMA con-

troller’s 16-bit memory address registers in conjunction

with an 8-bit DMA Low Page register and an 8-bit DMA

High Page register. These registers, associated with each

channel, provide the 32-bit memory address capability. A

write to the Low Page register clears the High Page regis-

ter, for backward compatibility with the PC/AT standard.

The starting address for the DMA transfer must be pro-

grammed into the DMA controller registers and the chan-

nel’s respective Low and High Page registers prior to

beginning the DMA transfer.

DMA Page Registers and Extended Addressing

The DMA Page registers provide the upper address bits

during DMA cycles. DMA addresses do not increment or

decrement across page boundaries. Page boundaries for

the 8-bit channels (Channels 0 through 3) are every 64 KB

and page boundaries for the 16-bit channels (Channels 5,

6, and 7) are every 128 KB.

Before any DMA operations are performed, the Page regis-

ters must be written at the I/O Port addresses in the DMA

controller registers to select the correct page for each DMA

channel. The other address locations between 080h and

08Fh, and 480h and 48Fh are not used by the DMA chan-

nels, but can be read or written by a PCI bus master. These

registers are reset to zero at POR. A write to the Low Page

patibility with the PC/AT standard.

For most DMA transfers, the High Page register is set to

zeros and is driven onto PCI address bits AD[31:24] during

DMA cycles. This mode is backward compatible with the

PC/AT standard. For DMA extended transfers, the High

Page register is programmed, and the values are driven

onto the PCI addresses AD[31:24] during DMA cycles to

allow access to the full 4 GB PCI address space.

5.9.8 DMA Address Generation

The DMA addresses are formed such that there is an

upper address, a middle address, and a lower address por-

tion.

The upper address portion, which selects a specific page,

is generated by the Page registers. The Page registers for

each channel must be set up by the system before a DMA

operation. The DMA Page register values are driven on

PCI address bits AD[31:16] for 8-bit channels and

AD[31:17] for 16-bit channels.

The middle address portion, which selects a block within

the page, is generated by the DMA controller at the begin-

ning of a DMA operation and any time the DMA address

increments or decrements through a block boundary. Block

sizes are 256 bytes for 8-bit channels (Channels 0 through

3) and 512 bytes for 16-bit channels (Channels 5, 6, and

7). The middle address bits are driven on PCI address bits

AD[15:8] for 8-bit channels and AD[16:9] for 16-bit chan-

nels.

The lower address portion is generated directly by the DMA

controller during DMA operations. The lower address bits

are output on PCI address bits AD[7:0] for 8-bit channels

and AD[8:1] for 16-bit channels.

5.9.9 DMA Mapper Source Selection

For each 8-bit DMA channel, the DMA mapper allows the

DMA request to come from a number of sources. Table 5-

16 shows how the DMA mapper register select field selects

the appropriate DMA source.

When LPC is selected as the DMA source for DMA Chan-

nel 0, the source is LPC DMA Channel 0. Similarly, when

LPC is selected as the source for DMA Channel 1, 2, or 3,

then the DMA sources for those three DMA channels are

respectively LPC DMA Channels 1, 2, and 3. Therefore,

LPC DMA Channel 0 can only be mapped to DMA Channel

0, LPC DMA Channel 1 can only be mapped to DMA Chan-

nel 1, etc.

Table 5-16. DMA Source Selection

Source Selector

Value from DMA

Mapper DMA Source

0 None (DMA channel off)

1UART1 Transmit

2 UART1 Receive

3UART2 Transmit

4 UART2 Receive

5 Reserved (not active)

6 Reserved (not active)

7LPC

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5.10 Keyboard Emulation Logic

The Keyboard Emulation Logic (KEL) provides a virtual

8042 keyboard controller interface that is used to map non-

legacy keyboard and mouse sources to this traditional

interface. For example, Universal Serial Bus (USB) sources

are “connected” to this interface via System Management

Mode (SMM) software. It also allows mixed environments

with one LPC legacy device and multiple new (USB)

devices. It produces IRQ and ASMI outputs.

Features

•Provides a virtual 8042 keyboard controller interface.

•Allows mixed environments.

•Produces IRQ and ASMI outputs.

•Employs a clock control logic for power management

purposes.

•No USB controller required for KEL to operate.

5.10.1 Keyboard Emulation and Port A

The Keyboard Emulation Logic (KEL) with Port A is illus-

trated in Figure 5-21. Strictly speaking, these are separate

functions. However, since they both affect the FA20#

(Force processor Address bit 20 to zero when low), the two

functions are implemented together. The Keyboard Emula-

tion Logic is the most complex and is discussed first.

Figure 5-21. KEL Block Diagram

Port A Write

& Read

KEL X

Control

32 32 88

Local Bus Clock

Reset

IN OUT OUT IN

Local Bus DataLocal Bus Data

* Read-Back Multiplexer is not shown

USB_SOF

1 KHz Clock

Keyboard

Emulator

Logic (KEL)

LPC_IRQ1

LPC_IRQ12

ASMI

EmulationEnable

SnoopEnable

FA20#

INIT Keyboard

IRQ 1 (to PIC)

IRQ 12 (to PIC)

EmulationInterrupt

Port A Enable

A20 Keyboard

INIT Port A

A20 Port A

Port 060h and

Port 064h Write

Port 060h

Read

Port 064h

Read

HCE

Control

HCE

Input

HCE

Output

HCE

Status

14 MHz

1 KHz

14 MHz

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5.10.2 Keyboard Emulation Overview

The purpose of the KEL is to model the legacy 8042 key-

board/mouse controller interfaced via legacy I/O Addresses

060h and 064h (also known as Ports 60 and 64). This hard-

ware and supporting processor System Management

Mode (SMM) software are designed to support systems

that do not have a true PS/2-compatible keyboard and/or

mouse interface, but those that have alternative devices

performing the equivalent function. Generally, the alterna-

tive device is a keyboard or mouse off a USB (Universal

Serial Bus) port, but it need not be. Due to the origins of the

hardware to be explained shortly, this discussion generally

assumes a USB alternative device, but this is not a require-

ment from a hardware perspective.

The KEL closely models the keyboard emulation hardware

detailed in the USB OHCI specification. It is specifically

designed to be software compatible with this model. In the

USB model, it is part of the USB “Host Controller”, but is

logically separate from it. The discussion and description

that follows is taken from the OHCI specification, but with

modifications to reflect the CS5536 companion device spe-

cific implementation.

To support applications and drivers in non-USB-aware

environments (e.g., DOS), a peripheral subsystem needs

to provide some hardware support for the emulation of a

PS/2 keyboard and/or mouse by their USB equivalents

(alternative devices). For OHCI, this emulation support is

provided by a set of registers that are controlled by code

running in SMM. Working in conjunction, this hardware and

software produces approximately the same behavior-to-

application code as would be produced by a PS/2-compati-

ble keyboard and/or mouse interface.

When data is received from the alternative device, the

emulation code is notified and becomes responsible for

translating the alternative device keyboard/mouse data into

a data sequence that is equivalent to what would be pro-

duced by a PS/2-compatible keyboard/mouse interface.

The translated data is made available to the system

through the legacy keyboard interface I/O Addresses 060h

and 064h. Likewise, when data/control is to be sent to the

alternative device (as indicated by the system writing to the

legacy keyboard interface), the emulation code is notified

and becomes responsible for translating the information

into appropriate data to be sent to the alternative device.

On the PS/2 keyboard/mouse interface, a read of I/O

Address 060h returns the current contents of the keyboard

output buffer; a read of I/O Address 064h returns the con-

tents of the keyboard status register. An I/O write to I/O

Addresses 060h and 064h puts data into the keyboard

input buffer (data is being input into the keyboard sub-

system). When emulation is enabled, reads and writes of

I/O Addresses 060h and 064h are captured in the KEL

HCE Output, Status, and/or Input operational registers.

The KEL described here supports a mixed environment in

which either the keyboard or mouse is implemented as an

alternative device and the other device is attached to a

standard PS/2 interface.

The following subsections use the term “alternate device

interrupt”. This is an ASMI or IRQ as appropriate for the

device; for example the USB can generate either an ASMI

or IRQ. The KEL generates a separate ASMI or IRQ.

5.10.3 Theory - Keyboard / Mouse Input

When data is received from the alternative device, the

emulation code is notified with an alternate device interrupt

and translates the keyboard/mouse data into an equivalent

PS/2-compatible sequence for presentation to the applica-

tion software. For each byte of PS/2-compatible data that is

to be presented to the applications software, the emulation

code writes to KEL_HCE_OUT (KEL Memory Offset 108h).

The emulation code then sets the appropriate bits in

KEL_HCE_STS (KEL Memory Offset 10Ch) (normally,

OutputFull (bit 0) is set for keyboard data and OutputFull

plus AuxOutputFull (bit 5) for mouse data). If key-

board/mouse interrupts are enabled, setting the

KEL_HCE_STS bits causes the generation of an IRQ1 for

keyboard data and IRQ12 for mouse data. The emulation

code then exits and waits for the next alternate device inter-

rupt.

When the host CPU exits from SMM, it can service the

pending IRQ1/IRQ12. This normally results in a read from

I/O Address 060h. When I/O Address 060h is read, the

KEL intercepts the access and returns the current contents

of KEL_HCE_OUT. The KEL also clears the OutputFull bit

in KEL_HCE_STS (KEL Memory Offset 10Ch[0]) and de-

asserts IRQ1/IRQ12.

If the emulation software has multiple characters to send to

the application software, it sets the CharacterPending bit in

KEL_HCE_CTRL (KEL Memory Offset 100h[2]). This

causes the KEL to generate an ASMI at the beginning of

the next frame, a time after the application read from I/O

Port 060h (KEL_HCE_OUT).

5.10.4 Theory - Keyboard Output

Keyboard output is indicated by application software writing

data to either I/O Address 060h or 064h. Upon a write to

either address, the KEL captures the data in KEL_HCE_IN

(KEL Memory Offset 104h) and, except in the case of a

FA20# (Force processor Address bit 20 to zero when low)

sequence, updates the InputFull and CmdData bits (KEL

Memory Offset 10Ch[1,3]). When the InputFull bit is set, a

KEL ASMI is generated at the beginning of the next frame.

Upon receipt of the KEL ASMI, the emulation software

reads KEL_HCE_CTRL and KEL_HCE_STS to determine

the cause of the emulation interrupt and performs the oper-

ation indicated by the data. Generally, this means putting

out data to the alternate device.

5.10.5 Emulation Events

Emulation Events (EEs) are caused by reads and writes of

the emulation registers. EEs generated by the emulation

hardware are steered by the KEL to either an ASMI or an

Emulation Interrupt. Steering is determined by the Emula-

tion Event Routing bit (MSR 5140001Fh[1]).

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Historically, EEs for data coming from the keyboard/mouse

are generated on USB frame boundaries. The KEL is inde-

pendent of the USB logic, but uses USB frame boundaries

for backward compatibility. Alternately, an independent 1

ms counter can be used (MSR 5140001Fh[3:2]). At the

beginning of each frame, the conditions that define asyn-

chronous EEs are checked and, if an EE condition exists,

the EE is signaled to the host. This has the effect of reduc-

ing the number of EEs that are generated for legacy input

to no more than 1,000 per second. The number of emula-

tion interrupts is limited because the maximum rate of data

delivery to an application cannot be more than 1,000 bytes

per second. A benefit of this rule is that, for normal key-

board and mouse operations, only one EE is required for

each data byte sent to the application. Additionally, delay of

the EE until the next Start Of Frame (SOF) causes data

persistence for keyboard input data that is equivalent to

that provided by an 8042 device.

5.10.6 Theory - KEL EEs

There are three EEs that produce the signal KEL ASMI.

These three EEs are: Character Pending, Input Full, and

External IRQ. An A20 sequence is a possible Input Full EE.

The A20Sequence bit (KEL Memory Offset 100h[5]) is set

in this case. The signal KEL ASMI is an active high pulse,

one Local bus clock in width, and sent to the Diverse Inte-

gration Logic (DIVIL). This signal is only asserted when the

EmulationEnable bit is enabled (KEL Memory Offset

100h[0] = 1). For an EE, KEL also optionally produces an

Emulation IRQ (KEL_EMU_IRQ). This signal is a level and

is only asserted when the EER bit (MSR 5140001Fh[1]) is

low. De-asserting KEL_EMU_IRQ requires clearing the

appropriate bit in KEL_HCE_CTRL or KEL_HCE_STS

(KEL Memory Offset 100h and 10Ch).

For the keyboard A20Sequence, KEL sets the

KEL_A20_ASMI_FLAG if enabled in the DIVIL.

Keyboard INIT and A20 are generated as appropriate when

emulation is enabled or SNOOP is enabled in KELX_CTL

(MSR 5140001Fh[0]). KEL ASMI is generated as appropri-

ate when emulation is enabled. KEL ASMI is not generated

when emulation is disabled and snoop is enabled. Key-

board A20 under snoop does not require service beyond

the DIVIL GLD_MSR_SMI (MSR 51400002h); that is, KEL

does not need to be manipulated. The InputFull bit (KEL

Memory Offset 10Ch[1]) will set, but does not require ser-

vice. Each new keyboard A20Sequence will set the

KEL_INIT_ASMI_FLAG if enabled.

If a write to Port A changes the value of bit 1, the KEL sets

the PORTA_A20_ASMI_FLAG (DIVIL MSR

51400002h[38]) if enabled in the DIVIL. If bit 0 of Port A is

written to a 1, KEL sets the PORTA_INIT_ASMI_FLAG

(DIVIL MSR 51400002h[39]) if enabled in the DIVIL. It also

sets Port A to the value 2; that is, only bit 1 is high. The

A20State bit in KEL_HCE_CTRL (KEL Memory Offset

100h[8]) is not effected.

The rate of application software reading of I/O Address

060h is dependent on the alternate device interrupt rate or

SOFEVENT (MSR 5140001Fh[3:2]) when the Character-

Pending bit is used (KEL Memory Offset 100h[2]). There is

one KEL EE per application software read of I/O Address

060h when the CharacterPending is set.

The rate of application software writing of I/O Addresses

060h and 064h is no greater than SOFEVENT. Generally,

there is one KEL EE per application write to I/O Address

060h.

SOFEVENT is used to emulate normal delays associated

with a real 8042 controller and PS/2 device. Its source is

established via MSR 5140001Fh[3:2]. Its value is 1 ms

frame interval.

5.10.7 Theory - Mixed Environment

A mixed environment is one in which an alternate device

and a PS/2 device are supported simultaneously (e.g., a

USB keyboard and a PS/2 mouse). The mixed environment

is supported by allowing the emulation software to control

the PS/2 interface. Control of this interface includes captur-

ing I/O accesses to I/O Addresses 060h and 064h and also

includes capture of interrupts from the PS/2 keyboard con-

troller off the LPC. IRQ1 and IRQ12 from the LPC keyboard

controller are routed through the KEL. When Externa-

lIRQEn (KEL Memory Offset 100h[4]) is set, IRQ1 and

IRQ12 from the legacy keyboard controller are blocked at

the KEL and an ASMI is generated instead. This allows the

emulation software to capture data coming from the legacy

controller and presents it to the application through the

emulated interface. The behavior of IRQ1 and IRQ12 with

respect to the ExternalIRQEn and IRQEn bits is summa-

rized in Table 5-17.

Table 5-17. KEL Mixed Environment

Emulation

Enable

External

IRQEn IRQEn LPC_IRQ1

LPC_

IRQ12

Output

Full

Output

FullAux

IRQ1

Active

IRQ12

Active Action

101001000IRQ1

101000100IRQ12

x10010001EE

x10100010EE

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5.10.8 Theory - Force A20 Low Sequence

The FA20 sequence occurs frequently in DOS applications.

Mostly, the sequence is to set FA20 high; that is, do not

force address bit 20 to a 0. High is the default state of this

signal. To reduce the number of ASMIs caused by the A20

sequence, KEL generates an ASMI only if the GateA20

sequence would change the state of A20.

The A20 sequence is initiated with a write of D1h to I/O

Address 064h. On detecting this write, the KEL sets the

A20Sequence bit (KEL Memory Offset 100h[5]). It captures

the data byte (KEL Memory Offset 104h[7:0]), but does not

set the InputFull bit (KEL Memory Offset 10Ch[1]). When

the A20Sequence is set, a write of a value to I/O Address

060h, that has bit 1 set to a value different than A20State

(KEL Memory Offset 100h[8]), causes InputFull to be set

and causes an ASMI. An ASMI with both InputFull and

A20Sequence set, indicates that the application is trying to

change the setting of FA20 on the keyboard controller.

However, when A20Sequence is set, and a write of a value

to I/O Address 060h that has bit 1 set to the same value as

A20State is detected, then no ASMI will occur.

As mentioned above, a write to I/O Address 064h of any

value other than D1h causes A20Sequence to be cleared.

If A20Sequence is active and a value of FFh is written to

I/O Address 064h, A20Sequence is cleared but InputFull is

not set. A write of any value other than D1h or FFh causes

InputFull to be set, which then causes an ASMI. A write of

FFh to I/O Address 064h when A20Sequence is not set

causes InputFull to be set. The current value of the

A20_Mask is maintained in two unconnected places: the

A20State bit (KEL Memory Offset 100h[8]) in Port A and

the value of A20State is only changed via a software write

to KEL_HCE_CTRL. It is set to 0 at reset. The value of bit 1

in Port A changes on any write to Port A. From reset,

PortA[1] is 1.

5.10.9 Theory - Processor Initialize Sequence

The processor initialization sequence is possible if either of

the following cases is true:

•A write of a value fed to I/O Address 064h indicates

processor initialization (INIT) or warm reset. This sets

KEL_INIT_ASMI_FLAG if enabled in the DIVIL. All HCE

registers and Port A are not effected.

•Port A initialization, INIT will respond to: Write 01h to I/O

Address 092h. (Refer to Section 5.10.10 "Port A".)

5.10.10 Port A

This register is at I/O Address 092h. It can also be used to

change the state of A20 or to cause an INIT. When 8-bit

data that has its bit 0 set to 1 is written, it causes an INIT.

However, if bit 1 of the 8-bit data is set to 1, it causes a

change in the state of A20 (A20 gets asserted). As above,

an ASMI is only generated on an INIT or A20 event. The

INIT operation always forces A20 high. Writes to bits 2 and

higher are a “don’t care”. Reads to Port A always return

00h or 02h depending on the state of Port A[1].

Note that A20 can be changed with Port A or the GateA20

sequence. Another important point is that A20State (bit 8)

in KEL_HCE_CTRL and bit 1 in Port A are independent

from each other. Writing a 1 to Port A[1] does not effect the

A20State bit. Changing the state of the A20State bit does

not effect Port A[1].

Note that when A20 has a value of 0, it means that the sec-

ond MB wraps to the first MB. However, a value of 1 means

that A20 is not modified.

The following statements summarize the above INIT and

A20 sequences :

INIT responds to: Write 01h to I/O Address 092h or FEh to

I/O Address 064h.

A20 toggle responds to: Write 02h to Address 092h or

Write 00h to Address 092h (bit 1 toggles, bit 0 held at 0),

and Write D1h to I/O Address 064h then write a value to

I/O Address 060h that has bit 1 set to a value different than

the A20State in the KEL_HCE_CTRL register. Trapping will

insure the SMI is taken on the instruction boundary.

A keyboard INIT does not respond to: Write D1h to I/O

Address 064h followed by a write 02h to I/O Address 060h

(set bit 0 to 0).

5.10.11 Keyboard Emulation Logic MSRs

In addition to KEL_HCE_CTRL (KEL Memory Offset 100h),

there is a KEL Extended Control MSR, KELX_CTL (MSR

5140001Fh), to provide additional features.

A “snoop” feature is used when an external LPC based

keyboard controller is used (while the KEL is not enabled).

All I/O accesses to I/O Addresses 060h and 064h proceed

to the LPC, but the KEL snoops or watches for the A20 and

INIT sequences. If these occur, KEL sets the

KEL_A20_ASMI_FLAG or KEL_INIT_ASMI_FLAG in the

DIVIL if enabled.

EEs may be routed such that they generate an IRQ or

ASMI. In the case of Emulation IRQ, the clearing is done by

an operation on the appropriate KEL_HCE_CTRL or

KEL_HCE_STS registers. Reading the EE routing bit is not

required for emulation processing via IRQ. This bit does

not effect ASMIs associated with A20 and INIT operations.

All ASMI signals are a single clock pulse wide.

SOFEVENT (Start Of Frame Event) is established with

MSR 5140001Fh[3:2]. These bits provide alternative

sources for SOFEVENT. The SOFEVENT can be sourced

from USB1, USB2, or the PIT. A 00 value selects the test

mode.

The Port A enable bit is a mask bit for Port A and its default

state is high.

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5.10.12 Related Diverse Device Functions

FA20# and INIT are not passed directly to the processor.

SSM code manipulates equivalent functions in the proces-

sor.

The HCE registers are considered part of the USB opera-

tional register set for some software, and hence, share the

same memory mapped register space. The GLIU descrip-

tor for the USBs, MSR_LBAR_KEL1, and

MSR_LBAR_KEL2 must all be set to the same base. The

GLIU routes accesses at Memory Offset 100h and above

to the Diverse Device and accesses below 100h to the

USB.

The address decoder in the DIVIL routes accesses to I/O

Addresses 060h and 064h to the KEL or LPC based on the

value of EmulationEnable (KEL Memory Offset 100h[0]). If

snoop mode is enabled and the EmulationEnable bit is not

set, writes are made directly to both the KEL and LPC.

The LPC IRQ1 and IRQ12 outputs are connected to both

KEL and the PIC. Masking logic in the PIC allows the LPC

interrupts to be used directly or the KEL set can be used.

The KEL ASMI is routed through the Diverse Device’s

Standard GLD_MSR_SMI register (MSR 51400002h). It

may be masked off there, but it is only cleared via

KELX_CTL (MSR 5140001Fh).

5.10.13 Emulation Event Decode

Emulation Events are of two types: frame synchronous and

asynchronous. The conditions for a frame synchronous

interrupt are sampled by the KEL at each SOF interval and,

if an event condition exists, it is signaled at that time. For

asynchronous events, the event is signaled as soon as the

condition exists.

The equation for the synchronous Emulation Event condi-

tion is:

synchronousEvent =

HCE_Control.EmulationEnable

(KEL Memory Offset 100h[0])

and

HCE_Control.CharacterPending

(KEL Memory Offset 100h[2])

and not

HCE_Status.OutputFull

(KEL Memory Offset 10Ch[0]).

When this decode is true, an Emulation Event is generated

at the next SOF. The Event condition is latched until the

decode becomes false.

The equation for the asynchronous Emulation Event condi-

tion is:

asynchronousEvent =

HCE_Control.EmulationEnable

(KEL Memory Offset 100h[0])

and

HCE_Status.InputFull

(KEL Memory Offset 10Ch[1]),

HCE_Control.ExternlIRQEn

(KEL Memory Offset 100h[4])

and

HCE_Control.IRQ1Active

(KEL Memory Offset 100h[6])

HCE_Control.IRQ12Active

(KEL Memory Offset 100h[7]).

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5.11 System Management Bus Controller

The System Management Bus (SMB) Controller is a two-

wire synchronous serial interface, compatible with the Sys-

tem Management Bus physical layer. The SMB Controller

is also compatible with Intel's SMBus, and other industry

standard two-wire interfaces. The SMB Controller can be

configured as a bus master or slave, and can maintain bidi-

rectional communication with both multiple master and

slave devices. As a slave device, the SMB Controller may

issue a request to become the bus master.

The SMB Controller allows easy interfacing to a wide range

of low-cost memory and I/O devices, including: EEPROMs,

SRAMs, timers, ADC, DAC, clock chips, and peripheral

drivers.

This chapter describes the general SMB Controller func-

tional block. A device may include a different implementa-

tion.

A block diagram of the System Management Bus (SMB)

Controller is shown Figure 5-22.

The SMB Controller is upward compatible with previous

industry standard two-wire interfaces as detailed in Table 5-

18 on page 126.

The SMB Controller’s protocol uses a two-wire interface for

bidirectional communication between the ICs connected to

the bus. The two interface lines are the Serial Data Line

(SDA) and the Serial Clock Line (SCL). These lines should

be connected to a positive supply via an internal or external

pull-up resistor, and remain high even when the bus is idle.

Each IC has a unique address and can operate as a trans-

mitter or a receiver (though some peripherals are only

receivers).

During data transactions, the master device initiates the

transaction, generates the clock signal, and terminates the

transaction. For example, when the SMB Controller ini-

tiates a data transaction with an attached SMB compliant

peripheral, the SMB Controller becomes the master. When

the peripheral responds and transmits data to the SMB

Controller, their master/slave (data transaction initiator and

clock generator) relationship is unchanged, even though

their transmitter/receiver functions are reversed.

Figure 5-22. SMB Controller Block Diagram

Data In

Local Bus Interface

CCU PIC

Busy

IRQ

Clock

I/O Enable

Data Out

Clock Out

SMB Controller

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Table 5-18. Comparison of SMB, Industry Standard Two-wire Interface, and ACCESS.bus

Symbol Parameter

SMB

Industry Standard

Two-wire Interface ACCESS.bus

Min Max Min Max Min Max

F Operating frequency 10 KHz 100 KHz 0 KHz 100 KHz 10 KHz 100 KHz

TBUF Bus free time between STOP

and START condition

4.7 µs 4.7 µs 4.7 µs

THD:STA Hold time after (repeated)

START condition. After this

period the first clock is generated

4.0 µs 4.0 µs 4.0 µs

TSU:STA Repeated START condition setup

time

4.7 µs 4.7 µs 4.7 µs

TSU:STO STOP condition setup time 4.0 µs 4.0 µs 4.0 µs

THD:DAT Data hold time 300 ns 0 µs 3.45 µs 300 ns

TSU:DAT Data setup time 250 ns 250 ns 250 ns

TTimeout Detect clock low time-out 25 ms 35 ms 25 ms 35 ms

TLOW Clock low period 4.7 µs 4.7 µs 4.7 µs

THIGH Clock high period 4.0 µs 50 µs 4.0 µs 4.0 µs 50 µs

TLOW:SEXT Cumulative clock low extend

period (slave)

25 ms 25 ms

TLOW:MEXT Cumulative clock low extend

period (master)

10 ms 10 ms

TFClock/data fall time 300 ns 300 ns 300 ns

TRClock/data rise time 1000 ns 1000 ns 1000 ns

TPOR Time that device must be opera-

tional after power-on reset

500 ms

VIL SMBus signal input low voltage 0.8V -0.5V 1.5V -0.5V 0.6V

VIH SMBus signal input high voltage 2.1V VDD 3.0V 1.4V 5.5V

VOL SMBus signal output low voltage 0.4V 0V 0.4V 0V 0.4V

ILEAK_BUS Input leakage per bus segment -200 µA ±200 µA

ILEAK_PIN Input leakage per device pin -10 µA ±10 µA -10 µA +10 µA 10 µA

VDD Nominal bus voltage 2.7V 5.5V 2.0V 5.0V

IPULLUP Current sinking, VOL = 0.4V

(SMBus)

4.0 mA 100 µA 350 µA

CBUS Capacitive load per bus segment 400 pF

CICapacitance for SMBDAT or

SMBCLK pin

10 pF 10 pF

VNOISE Signal noise immunity from 10 to

100 MHz

300 mV

p-p

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5.11.1 Data Transactions

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock (SCL).

Consequently, throughout the clock’s high period, the data

should remain stable (see Figure 5-23). Any changes on

the SDA line during the high state of SCL and in the middle

of a transaction aborts the current transaction. New data

should be sent during the low SCL state. This protocol per-

mits a single data line to transfer both command/control

information and data, using the synchronous serial clock.

Each data transaction is composed of a START condition,

a number of byte transfers (set by the software), and a

STOP condition to terminate the transaction. Each byte is

transferred with the most significant bit first, and after each

byte (8 bits), an Acknowledge signal must follow. The fol-

lowing subsections provide further details of this process.

During each clock cycle, the slave can stall the master

while it handles the previous data or prepares new data.

This can be done for each bit transferred, or on a byte

boundary, by the slave holding SCL low to extend the clock-

low period. Typically, slaves extend the first clock cycle of a

transfer if a byte read has not yet been stored, or if the next

byte to be transmitted is not yet ready. Some microcontrol-

lers, with limited hardware support for SMB, extend the

SMB after each bit, thus allowing the software to handle

this bit.

Figure 5-23. SMB Bit Transfer

5.11.1.1 START and STOP Conditions

The SMB master generates START and STOP conditions

(control codes). After a START condition is generated, the

bus is considered busy and retains this status for a certain

time after a STOP condition is generated. A high-to-low

transition of the data line while the clock is high indicates a

START condition. A low-to-high transition of the data line

while the clock is high indicates a STOP condition (see Fig-

ure 5-24).

In addition to the first START condition, a repeated START

condition can be generated in the middle of a transaction.

This allows another device to arbitrate the bus, or a change

in the direction of data transfer.

Figure 5-24. SMB START and STOP Conditions

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

SDA

SCL SP

START

Condition STOP

Condition

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5.11.1.2 Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock pulse

sent by the master with each byte transferred, and the ACK

signal sent by the receiving device (see Figure 5-25).

The master generates the ACK clock pulse on the ninth

clock pulse of the byte transfer. The transmitter releases

the data line (permits it to go high) to allow the receiver to

send the ACK signal. The receiver must pull down the data

line during the ACK clock pulse, signalling that it has cor-

rectly received the last data byte and is ready to receive the

next byte. Figure 5-26 illustrates the ACK cycle.

Figure 5-25. SMB Data Transaction

Figure 5-26. SMB Acknowledge Cycle

SDA

SCL

MSB

ACK ACK

3 - 6 789123 - 89

Acknowledge

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

START

Condition STOP

Condition

START

Condition

SCL 12

3 - 6 789

Transmitter Stays Off Bus

During Acknowledge Clock

Acknowledge

Signal From Receiver

Data Output

by Transmitter

Data Output

by Receiver

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5.11.1.3 Acknowledge After Every Byte Rule

According to this rule, the master generates an acknowl-

edge clock pulse after each byte transfer, and the receiver

sends an acknowledge signal after every byte received.

There are two exceptions to this rule:

•When the master is the receiver, it must indicate to the

transmitter the end of data by not acknowledging (nega-

tive acknowledge) the last byte clocked out of the slave.

This negative acknowledge still includes the acknowl-

edge clock pulse (generated by the master), but the SDA

line is not pulled down.

•When the receiver is full, otherwise occupied, or a

problem has occurred, it sends a negative acknowledge

to indicate that it cannot accept additional data bytes.

5.11.1.4 Addressing Transfer Formats

Each device on the bus has a unique address. Before any

data is transmitted, the master transmits the address of the

slave being addressed. The slave device should send an

acknowledge signal on the SDA, once it recognizes its

address.

The address consists of the first seven bits after a START

condition. The direction of the data transfer (R/W) depends

on the bit sent after the address, the eighth bit. A low-to-

high transition during an SCL high period indicates the

STOP condition, and ends the transaction of SDA (see Fig-

ure 5-27).

When the address is sent, each device in the system com-

pares this address with its own. If there is a match, the

device considers itself addressed and sends an acknowl-

edge signal. Depending on the state of the R/W bit (1 =

Read, 0 = Write), the device acts either as a transmitter or

a receiver.

The SMB protocol allows a general call address to be sent

to all slaves connected to the bus. The first byte sent speci-

fies the general call address (00h) and the second byte

specifies the meaning of the general call (for example, write

slave address by software only). Those slaves that require

data acknowledge the call, and become slave receivers;

other slaves ignore the call.

Figure 5-27. SMB Complete Data Transaction

START

Condition STOP

Condition

SDA

SCL 1 - 7 891 - 7 891 - 7 89

Address R/W ACK Data ACK Data ACK

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5.11.1.5 Arbitration on the Bus

Multiple master devices on the bus require arbitration

between their conflicting bus SMB demands. Control of the

bus is initially determined according to address bits and

clock cycle. If the masters are trying to address the same

slave, data comparisons determine the outcome of this

arbitration. In master mode, the device immediately aborts

a transaction if the value sampled on the SDA line differs

from the value driven by the device. (An exception to this

rule is SDA while receiving data. The lines may be driven

low by the slave without causing an abort.)

The SCL signal is monitored for clock synchronization and

to allow the slave to stall the bus. The actual clock period is

set by the master with the longest clock period, or by the

slave stall period. The clock high period is determined by

the master with the shortest clock high period.

When an abort occurs during the address transmission, a

master that identifies the conflict should give up the bus,

switch to slave mode, and continue to sample SDA to

check if it is being addressed by the winning master on the

bus.

5.11.1.6 Master Mode

This discussion and Section 5.11.1.7 on page 132 refer-

ence several bits in the SMB Native register set (e.g., SMB

I/O Offset 03h[7], SMB I/O Offset 01h[1], etc.). Table 5-19

provides the bit map for the SMB Native registers for the

reader’s convenience. For full bit descriptions, refer to Sec-

tion 6.10.1 "SMB Native Registers" on page 395.

Requesting Bus Mastership

An SMB transaction starts with a master device requesting

bus mastership. It asserts a START condition, followed by

the address of the device that wants the bus. If this transac-

tion is successfully completed, the software may assume

that the device has become the bus master.

For the device to become the bus master, the software

should perform the following steps:

1) Configure SMB I/O Offset 03h[2] to the desired opera-

tion mode (Polling = 0 or Interrupt = 1) and set SMB

I/O Offset 03h[0]. This causes the SMB Controller to

issue a START condition on the bus when the bus

becomes free (SMB I/O Offset 02h[1] is cleared, or

other conditions that can delay START). It then stalls

the bus by holding SCL low.

2) If a bus conflict is detected (i.e., another device pulls

down the SCL signal), SMB I/O Offset 01h[5] is set.

3) If there is no bus conflict, SMB I/O Offset 01h[6] and

SMB I/O Offset 01h[1] are set.

4) If SMB I/O Offset 03h[2] is set and either SMB I/O Off-

set 01h[5] or SMB I/O Offset 01h[6] is set, an interrupt

is issued.

Sending the Address Byte

When the device is the active master of the bus (SMB I/O

Offset 01h[1] is set), it can send the address on the bus.

The address sent should not be the device’s own address,

as defined by the ADDR bits of the SMB_ADDR register if

the SMB I/O Offset 04h[7] is set, nor should it be the global

call address if the SMB I/O Offset 02h[3] is set.

To send the address byte, use the following sequence:

1) For a receive transaction, where the software wants

only one byte of data, it should set SMB I/O Offset

03h[4]. If only an address needs to be sent or if the

device requires STALL for some other reason, set the

SMB I/O Offset 03h[7].

2) Write the address byte (7-bit target device address)

and the direction bit to SMB_SDA (SMB I/O Offset

00h). This causes the SMB Controller to generate a

transaction. At the end of this transaction, the acknowl-

edge bit received is copied to SMB I/O Offset 01h[4].

During the transaction, the SDA and SCL lines are

continuously checked for conflict with other devices. If

a conflict is detected, the transaction is aborted, SMB

I/O Offset 01h[5] is set, and SMB I/O Offset 01h[1] is

cleared.

Table 5-19. SMB Native Registers Map

SMB I/O

OffsetName 76543210

00h SMB_STA SMBSDA

01h SMB_STS SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT

02h SMB_CTRL_

STS

RSVD TGSCL TSDA GCMTCH MATCH BB BUSY

03h SMB_CTRL1 STASTRE NMINTE GCMEN ACK RSVD INTEN STOP START

04h SMB_ADDR SAEN SMBADDR

05h SMB_CTRL2 SCLFRQ[6:0] EN

06h SMB_CTRL3 SCLFRQ[14:7]

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3) If SMB I/O Offset 03h[7] is set and the transaction was

successfully completed (i.e., both SMB I/O Offset

01h[5] and SMB I/O Offset 01h[4] are cleared), the

STASTR (SMB I/O Offset 01h[3]) bit is set. In this

case, the SMB Controller stalls any further bus opera-

tions (i.e., holds SCL low). If SMB I/O Offset 03h[2] is

set, it also sends an interrupt request to the host.

4) If the requested direction is transmit and the START

transaction was completed successfully (i.e., neither

SMB I/O Offset 01h[4] nor SMB I/O Offset 01h[5] is

set, and no other master has arbitrated the bus), SMB

I/O Offset 01h[6] is set to indicate that the SMB Con-

troller awaits attention.

5) If the requested direction is receive, the START trans-

action was completed successfully and SMB I/O Offset

01h[3] is cleared, the SMB Controller starts receiving

the first byte automatically.

6) Check that both SMB I/O Offset 01h[5] and SMB I/O

Offset 03h[7] are cleared. If set and SMB I/O Offset

03h[2] is set, an interrupt is generated.

Master Transmit

After becoming the bus master, the device can start trans-

mitting data on the bus.

To transmit a byte in an interrupt or polling controlled oper-

ation, the software should:

1) Check that both SMB I/O Offset 01h[5] and SMB I/O

Offset 01h[4] are cleared, and that SMB I/O Offset

01h[6] is set. If SMB I/O Offset 03h[7] is set, also

check that the SMB I/O Offset 01h[3] is cleared (and

clear it if required).

2) Write the data byte to be transmitted to SMB_SDA.

When either SMB I/O Offset 01h[4] or SMB I/O Offset

01h[5] is set, an interrupt is generated. When the slave

responds with a negative acknowledge, SMB I/O Offset

01h[4] is set and SMB I/O Offset 01h[6] remains cleared. In

this case, if SMB I/O Offset 03h[2] is set, an interrupt is

issued.

Master Receive

After becoming the bus master, the device can start receiv-

ing data on the bus.

To receive a byte in an interrupt or polling operation, the

software should:

1) Check that SMB I/O Offset 01h[6] is set and that SMB

I/O Offset 01h[5] is cleared. If SMB I/O Offset 03h[7] is

set, also check that SMB I/O Offset 01h[3] is cleared

(and clear it if required).

2) Set SMB I/O Offset 03h[4] if the next byte is the last

byte that should be read. This causes a negative

acknowledge to be sent.

3) Read the data byte from SMB_DATA.

4) If last byte, issue STOP or repeated START before one

byte time (nine clocks) otherwise another byte will be

latched into the SMB_DATA and SMB I/O Offset 01h[6]

will be set. Before generating a STOP condition or

generating a repeated START condition, it is neces-

sary to perform an SDA read and clear SMB I/O Offset

01h[6].

Master STOP

To end a transaction, set SMB I/O Offset 03h[1] before

clearing the current STALL flag (i.e., the SDAST, NEGACK,

or STASTR bit of SMB I/O Offset 01h). This causes the

SMB to send a STOP condition immediately, and to clear

SMB I/O Offset 03h[1]. A STOP condition may be issued

only when the device is the active bus master (SMB I/O

Offset 01h[1] is set).

Master Bus Stall

The SMB Controller can stall the bus between transfers

while waiting for the host response. The bus is stalled by

holding the SCL signal low after the acknowledge cycle.

Note that this is interpreted as the beginning of the follow-

ing bus operation. The user must make sure that the next

operation is prepared before the flag that causes the bus

STALL is cleared.

The flags that can cause a bus STALL in master mode are:

•Negative acknowledge after sending a byte

(SMB I/O Offset 01h[4] = 1).

•SMB I/O Offset 01h[6] is set.

•SMB I/O Offset 03h[7] = 1, after a successful START

(SMB I/O Offset 01h[3] = 1).

Repeated START

A repeated START is performed when the device is already

the bus master (SMB I/O Offset 01h[1] is set). In this case,

the bus is stalled and the SMB Controller awaits host han-

dling due to: negative acknowledge (SMB I/O Offset 01h[4]

= 1), empty buffer (SMB I/O Offset 01h[6] = 1), and/or a

STALL after START (SMB I/O Offset 01h[3] = 1).

For a repeated START:

1) Set SMB I/O Offset 03h[0] = 1.

2) In master receive mode, read the last data item from

SMB_SDA.

3) Follow the address send sequence, as described in

“Write the address byte (7-bit target device address)

and the direction bit to SMB_SDA (SMB I/O Offset

00h). This causes the SMB Controller to generate a

transaction. At the end of this transaction, the acknowl-

edge bit received is copied to SMB I/O Offset 01h[4].

During the transaction, the SDA and SCL lines are

continuously checked for conflict with other devices. If

a conflict is detected, the transaction is aborted, SMB

I/O Offset 01h[5] is set, and SMB I/O Offset 01h[1] is

cleared.

132 AMD Geode™ CS5536 Companion Device Data Book

System Management Bus Controller

33238G

4) If the SMB Controller was awaiting handling due to

SMB I/O Offset 01h[3] = 1, clear it only after writing the

requested address and direction to SMB_DATA.

Master Error Detection

The SMB Controller detects illegal START or STOP condi-

tions (i.e., a START or STOP condition within the data

transfer, or the acknowledge cycle) and a conflict on the

data lines of the bus. If an illegal condition is detected,

SMB I/O Offset 01h[5] is set and master mode is exited

(SMB I/O Offset 01h[1] is cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a

restart operation fails, SMB I/O Offset 01h[5] is set to indi-

cate the error. In some cases, both the device and the

other device may identify the failure and leave the bus idle.

In this case, the START sequence may be incomplete and

the bus may remain deadlocked.

To recover from deadlock, use the following sequence:

1) Clear SMB I/O Offset 01h[5] and SMB I/O Offset

02h[1].

2) Wait for a time-out period to check that there is no

other active master on the bus (i.e., SMB I/O Offset

02h[1] remains cleared).

3) Disable, and re-enable the SMB Controller to put it in

the non-addressed slave mode. This completely resets

the functional block.

At this point, some of the slaves may not identify the bus

error. To recover, the SMB Controller becomes the bus

master: it asserts a START condition, sends an address

byte, then asserts a STOP condition that synchronizes all

the slaves.

5.11.1.7 Slave Mode

A slave device waits in Idle mode for a master to initiate a

bus transaction. Whenever the SMB Controller is enabled

and it is not acting as a master (i.e., SMB I/O Offset 01h[1]

is cleared), it acts as a slave device.

Once a START condition on the bus is detected, the device

checks whether the address sent by the current master

matches either:

•The SMB I/O Offset 04h[6:0] value if SMB I/O Offset

04h[7] = 1, or

•The general call address if SMB I/O Offset 03h[5] = 1.

This match is checked even when SMB I/O Offset 01h[1] is

set. If a bus conflict (on SDA or SCL) is detected, SMB I/O

Offset 01h[5] is set, SMB I/O Offset 01h[1] is cleared and

the device continues to search the received message for a

match.

If an address match or a global match is detected:

1) The device asserts its SDA line during the acknowl-

edge cycle.

2) SMB I/O Offset 02h[2] and SMB I/O Offset 01h[2] are

set. If SMB I/O Offset 01h[0] = 1 (i.e., slave transmit

mode) SMB I/O Offset 01h[6] is set to indicate that the

buffer is empty.

3) If SMB I/O Offset 03h[2] is set, an interrupt is gener-

ated if both SMB I/O Offset 03h[2] and SMB I/O Offset

03h[6] are set.

4) The software then reads SMB I/O Offset 01h[0] to

identify the direction requested by the master device. It

clears SMB I/O Offset 01h[2] so future byte transfers

are identified as data bytes.

Slave Receive and Transmit

Slave receive and transmit are performed after a match is

detected and the data transfer direction is identified. After a

byte transfer, the SMB Controller extends the acknowledge

clock until the software reads or writes the SMB_SDA reg-

ister. The receive and transmit sequences are identical to

those used in the master routine.

Slave Bus Stall

When operating as a slave, the device stalls the bus by

extending the first clock cycle of a transaction in the follow-

ing cases:

•SMB I/O Offset 01h[6] is set.

•SMB I/O Offset 01h[2] and SMB I/O Offset 03h[6] are

set.

Slave Error Detection

The SMB Controller detects an illegal START and STOP

condition on the bus (i.e., a START or STOP condition

within the data transfer or the acknowledge cycle). When

this occurs, SMB I/O Offset 01h[5] is set and SMB I/O Off-

set 02h[2] and SMB I/O Offset 02h[3] are cleared, setting

the SMB Controller as an unaddressed slave.

5.11.1.8 Configuration

SDA and SCL Signals

The SDA and SCL are open-drain signals. The device per-

mits the user to define whether to enable or disable the

internal pull-up of each of these signals.

SMB Clock Frequency

The SMB permits the user to set the clock frequency for the

System Management Bus clock. The clock is set by the

SMB I/O Offset 05h[7:1] field and the SMB_CTRL3 regis-

ter, which determines the SCL clock period used by the

device. This clock low period may be extended by stall peri-

ods initiated by the SMB or by another System Manage-

ment Bus device. In case of a conflict with another bus

master, a shorter clock high period may be forced by the

other bus master until the conflict is resolved.

AMD Geode™ CS5536 Companion Device Data Book 133

System Management Bus Controller 33238G

5.11.1.9 Transaction Types

Byte Write

Sequence of events (see Figure 5-28):

1) START

2) Address phase

3) Acknowledge

4) Word address

5) Acknowledge

6) Data

7) Acknowledge

8) STOP

Page Write

Sequence of Events (see Figure 5-29):

1) START

2) Address

3) Acknowledge

4) Word Address

5) Acknowledge

6) Data1

7) Acknowledge

8) Data(n)

9) Acknowledge

10) Data(n+1)

11) Acknowledge

12) Data(n+x)

13) Acknowledge

14) STOP

Current Address Read

Sequence of Events (see Figure 5-30):

1) START

2) Device Address - 8 bit

3) Acknowledge

4) Data

5) No Acknowledge

6) STOP

Figure 5-28. SMB Byte Write

Figure 5-29. SMB Page Write

Figure 5-30. SMB Current Address Read

START

MSB

LSB WriteR/W

ACK

Device

Word Address

MSB

LSB

ACK

Data

STOP

Address

SDA

ACK

Line

START

MSB

LSB WriteR/W

ACK

Device

Word Address (n)

MSB

LSB

ACK

Data (n)

STOP

Address

SDA

ACK

Line

Data (n + 1) Data (n + x)

ACK

START

MSB

LSB ReadR/W

ACK

Device

Data

No ACK

STOP

Address

SDA

Line

134 AMD Geode™ CS5536 Companion Device Data Book

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33238G

Random Read

Sequence of Events (see Figure 5-31):

1) START

2) Device Address

3) Acknowledge

4) Word Address(n)

5) Acknowledge

6) START

7) Device Address

8) Acknowledge

9) Data(n)

10) No Acknowledge

11) STOP

Sequential Reads

Sequence of Events (see Figure 5-32):

1) START

2) Device Address

3) Acknowledge

4) Data(n)

5) Acknowledge

6) Data(n+1)

7) Acknowledge

8) Data(n+2)

9) Acknowledge

10) Data(n+x)

11) No Acknowledge

12) STOP

Figure 5-31. SMB Random Read

Figure 5-32. SMB Sequential Reads

START

MSB

LSB WriteR/W

ACK

Device

Word Address (n)

ACK

START

Address

SDA

Line

MSB

LSB

MSB

LSB Read

Device

Address

ACK

Data (n)

No ACK STOP

Dummy Write

START

MSB

LSB ReadR/W

ACK

Device

Data (n)

ACK

Address

SDA

Line

ACK

Data (n + x)

No ACK STOP

Data (n+1) Data (n+2)

ACK

AMD Geode™ CS5536 Companion Device Data Book 135

UART and IR Port 33238G

5.12 UART and IR Port

The UART and IR Port (UART/IR Controller) is an

enhanced serial port with fast IR (infrared). The UART/IR

Controller provides advanced, versatile serial communica-

tions features with IR capabilities and supports:

•UART (Section 5.12.1.1 "UART Mode" on page 138)

•Sharp-IR (Section 5.12.1.2 "Sharp-IR Mode" on page

138)

•IrDA 1.0 SIR (Section 5.12.1.3 "SIR Mode" on page 138)

•Consumer Electronic IR (CEIR); also called TV Remote

or Consumer remote control (Section 5.12.1.4 "CEIR

Mode" on page 139)

In UART mode, the functional block can act as a standard

16450 or 16550, or in extended mode.

Existing 16550-based legacy software is completely and

transparently supported. Organization and specific fall-

back mechanisms switch the functional block to 16550

compatibility mode upon reset, or when initialized by 16550

software.

This functional block has two DMA channels, of which the

device can use one or both. One channel is required for IR-

based applications, since IR communication works in half-

duplex fashion. Two channels are normally needed to han-

dle high speed, full duplex, UART-based applications.

Figure 5-33 shows the serial port connections to the

peripheral devices and host, as well as the device configu-

ration.

Features

•Fully compatible with 16550 and 16450 devices (except

modem)

•Extended UART mode

•Sharp-IR

•IrDA 1.0 SIR with up to 115.2 kbps data rate

•Consumer-IR mode

•UART mode data rates up to 1.5 Mbps

•Full duplex infrared frame transmission and reception

•Transmit deferral

•Automatic fallback to 16550 compatibility mode

•Selectable 16 and 32 level FIFOs

•12-bit timer for infrared protocol support

•DMA handshake signal routing for either 1 or 2 channels

•Support for power management

•Virtual dongle interface

Figure 5-33. UART/IR Overview Diagram

Microprocessor

Master Bus

Local Bus Interface

DMA Controller

Virtual Dongle

Interface Super I/O Bus and

Tx and Rx UART/IR Logic

UART InterfaceIR Interface

MSR_DON

MSR_CONFIG

MSR_RSVD

MSR_MOD

Local Bus to Super I/O Bus Converter and Control Logic

ID[3:0]

IRSL0_DS

IRSL[2:0]

Modem/Control Signals

UART/IR Controller

SOUT SINIRTX IRRX1

IRQ

Interrupt Controller

BUSY

CCU

MHZ48_CLK

DMA Interface

MHZ48_XCO,

MHZ48_XCI

MHZ48_XCEN

136 AMD Geode™ CS5536 Companion Device Data Book

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33238G

5.12.1 Operational Modes

This section describes the operation modes of the

UART/IR Controller. Although each mode is unique, certain

system resources and features are common.

This discussion references several bits in the UART/IR

Controller Native register set. Table 5-20 provides the bit

map for the UART/IR Controller Native registers for the

reader’s convenience. For full bit descriptions, refer to Sec-

tion 6.12.2 on page 413.

Table 5-20. UART/IR Controller Native Register Bit Map

I/O

OffsetName76543210

Bank 0

00h RXD RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0

00h TXD TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0

01h IER

(Note 1)

RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE

IER

(Note 2)

RSVD TXEMP_IE DMA_IE MS_IE LS_IE TXLDL_IE RXHDL_IE

02h EIR

(Note 1)

FEN[1:0] RSVD RXFT IPR[1:0] IPF

EIR

(Note 2) RSVD TXEMP_EV DMA_EV MS_EV LS_EV/

TXHLT_EV

TXLDL_EV RXHDL_IE

FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN

03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0]

BSR BKSE BSR[6:0]

04h MCR

(Note 1)

RSVD LOOP ISEN or

DCDLP

RILP RTS DTR

MCR

(Note 2)

MDSL[2:0] IR_PLS TX_DFR DMA_EN RTS DTR

05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA

06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS

07h SPR

(Note 1)

Scratch Data

ASCR

(Note 2)

CTE TXUR RXACT RXWDG RSVD S_OET RSVD RXF_TOUT

Bank 1

00h LBGD_L LBGD[7:0]

01h LBGD_H LBGD[15:8]

02h RSVD RSVD

03h LCR BKSE SBRK STKP EPS PEN STB WLS1 WLS0

BSR BKSE BSR[6:0]

04-07h RSVD RSVD

Bank 2

00h BGD_L BGD[7:0]

01h BGD_H BGD[15:8]

02h EXCR1 RSVD EDTLBK LOOP DMASWP DMATH DMANF EXT_SL

03h BSR BKSE BSR[6:0]

04h EXCR2 LOCK RSVD PRESL[1:0] RF_SIZ[1:0] TF_SIZ1[1:0]

05h RSVD RSVD

06h TXFLV RSVD TFL[5:0]

07h RXFLV RSVD RFL[5:0]

AMD Geode™ CS5536 Companion Device Data Book 137

UART and IR Port 33238G

Bank 3

00h MRID MID[3:0] RID[3:0]

01h SH_LCR RSVD SBRK STKP EPS PEN STB WLS1 WLS0

02h SH_FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN

03h BSR BKSE BSR[6:0]

04h-

07h

RSVD RSVD

Bank 4

00h-

01h

RSVD RSVD

02h IRCR1 RSVD IR_SL[1:0] RSVD

03h BSR BKSE BSR[6:0]

04h-

07h

RSVD RSVD

Bank 5

00h-

02h

RSVD RSVD

03h BSR BKSE BSR[6:0]

04h IRCR2 RSVD RSVD RSVD AUX_IRRX RSVD RSVD IRMSSL IR_FDPLX

05h-

07h

RSVD RSVD

Bank 6

00h IRCR3 SHDM_DS SHMD_DS RSVD

01h RSVD RSVD

02h SIR_PW RSVD SPW3 SPW2 SPW1 SPW0

03h BSR BKSE BSR[6:0]

04h-

07h

RSVD RSVD

Bank 7

00h IRRXDC DBW[2:0] DFR[4:0]

01h IRTXMC MCPW[2:0] MCFR[4:0]

02h RCCFG R_LEN T_OV RXHSC RCDM_DS RSVD TXHSC RC_MMD[1:0]

03h BSR BKSE BSR[6:0]

04h IRCFG1 STRV_MS RSVD SET_IRTX IRRX1_LV RSVD IRIC[2:0]

05h-

06h

RSVD RSVD

07h IRCFG4 RSVD IRSL0_DS RXINV IRSL21_DS RSVD

Note 1. Non- Extended Mode.

Note 2. Extended Mode.

Table 5-20. UART/IR Controller Native Register Bit Map (Continued)

I/O

OffsetName76543210

138 AMD Geode™ CS5536 Companion Device Data Book

UART and IR Port

33238G

5.12.1.1 UART Mode

UART mode supports serial data communication with a

remote peripheral device using a wired interface. This func-

tional block provides receive and transmit channels that

can operate concurrently in full-duplex mode. This func-

tional block performs all functions required to conduct par-

allel data interchange with the system and composite serial

data exchange with the external data channel.

It performs parallel-to-serial conversion on data characters

received from the processor or a DMA controller, and

serial-to-parallel conversion on data characters received

from the serial interface. Figure 5-34 shows the serial data

stream. A data character contains five to eight data bits. It

is preceded by a START bit and is followed by an optional

PARITY bit and a STOP bit. Data is transferred in Little

Endian order (LSB first).

UART mode can be implemented in standard 16450 and

16550 compatibility (non-extended) and extended mode.

UART 16450 compatibility mode is the default after power-

up or reset. When extended mode is selected, the func-

tional block architecture changes slightly and a variety of

additional features are made available. The interrupt

sources are no longer prioritized, and an Auxiliary Status

and Control Register (ASCR) replaces the Scratch Pad

tures include: transmitter FIFO (TX_FIFO) thresholding,

DMA capability, and interrupts on transmitter empty states

and DMA events.

The clock for both transmit and receive channels is pro-

vided by an internal baud generator that divides its input

clock by any divisor value from 1 to 216-1. The output clock

frequency of the baud generator must be programmed to

be 16 times the baud rate value. The baud generator input

clock is derived from a 24 MHz clock through a program-

mable prescaler. The prescaler value is determined by the

PRESL bits in the EXCR2 register (Bank 3 I/O Offset

04h[5:4]). Its default value is 13. This allows all the stan-

dard baud rates, up to 115.2 Kbaud, to be obtained.

Smaller prescaler values allow baud rates up to 921.6

Kbaud (standard) and 1.5 Kbaud (non-standard).

Before operation can begin, both the communication for-

mat and baud rate must be programmed by the software.

The communication format is programmed by loading a

control byte into the LCR (Link Control Register) (Bank 1

I/O Offset 03h), while the baud rate is selected by loading

an appropriate value into the Baud Generator Divisor regis-

ter. The software can read the status of the functional block

at any time during operation. The status information

includes Full/Empty states for both transmit and receive

channels, and any other condition detected on the received

data stream, such as a parity error, framing error, data

overrun, or break event.

5.12.1.2 Sharp-IR Mode

This mode supports bidirectional data communication with

a remote device, using IR radiation as the transmission

medium. Sharp-IR uses Digital Amplitude Shift Keying

(DASK) and allows serial communication at baud rates up

to 38.4 Kbaud. The format of the serial data is similar to

that of the UART data format. Each data WORD is sent

serially, beginning with a 0 value START bit, followed by up

to eight data bits (LSB first), an optional parity bit, and end-

ing with at least one STOP bit, with a binary value of 1. A

logical 0 is signalled by sending a 500 KHz continuous

pulse train of IR radiation. A logical 1 is signalled by the

absence of an IR signal. This functional block can perform

the modulation and demodulation operations internally, or

can rely on the external optical module to perform them.

Sharp-IR device operation is similar to operation in UART

mode. The difference being that data transfer operations

are normally performed in half-duplex fashion, and the

modem control and status signals are not used. Selection

of the Sharp-IR mode is controlled by the Mode Select bits

in the MCR (Bank 0 I/O Offset 04h[7:5]) when the func-

tional block is in extended mode, or by the IR_SL bits in the

IRCR1 (Bank 4 I/O Offset 02h[3:2]) when the functional

block is in non-extended mode.) This prevents legacy soft-

ware, running in non-extended mode, from spuriously

switching the functional block to UART mode when the soft-

ware writes to the MCR.

5.12.1.3 SIR Mode

SIR mode supports bidirectional data communication with

a remote device, using IR radiation as the transmit

medium. SIR allows serial communication at baud rates up

to 115.2 Kbaud. The serial data format is similar to that of

the UART data format. Each data WORD is sent serially,

beginning with a 0 value START bit, followed by eight data

bits (LSB first), an optional PARITY bit, and ending with at

least one STOP bit, with a binary value of 1. A 0 value is

signalled by sending a single IR pulse. A 1 value is sig-

nalled by the absence of a pulse. The width of each pulse

can be either 1.6 μs or 3/16 of the time required to transmit

a single bit (1.6 μs equals 3/16 the time required to transmit

a single bit at 115.2 kbps). This way, each WORD begins

with a pulse at the START bit.

Operation in SIR is similar to that of the UART mode. The

difference being that data transfer operations are normally

performed in half-duplex fashion. Selection of the IrDA 1.0

SIR mode is controlled by the Mode Select bits in the MCR

(Bank 0 I/O Offset 04h[7:5]) when the UART is in extended

mode, or by the IR_SL bits in the IRCR1 register (Bank 4

I/O Offset 02h[3:2]) when the UART is in non-extended

mode. This prevents legacy software, running in non-

extended mode, from spuriously switching the functional

block to UART mode when the software writes to the MCR.

Figure 5-34. UART Serial Data Stream Format

START -LSB- DATA[5:8] -MSB- PARITY STOP

AMD Geode™ CS5536 Companion Device Data Book 139

UART and IR Port 33238G

5.12.1.4 CEIR Mode

The Consumer Electronics IR circuitry is designed to opti-

mally support all major protocols presently used in the fol-

lowing remote-controlled home entertainment equipment:

RC-5, RC-6, RECS 80, NEC, and RCA. This device, in

conjunction with an external optical device, provides the

physical layer functions necessary to support these proto-

cols. Such functions include: modulation, demodulation,

serialization, de-serialization, data buffering, status report-

ing, interrupt generation, etc. The software is responsible

for the generation of IR code transmitted, and the interpre-

tation of received code.

CEIR Transmit Operation

The transmitted code consists of a sequence of bytes that

represents either a bit string or a set of run-length codes.

The number of bits or run-length codes needed to repre-

sent each IR code bit depends on the IR protocol used.

The RC-5 protocol, for example, needs two bits or between

one and two run-length codes to represent each IR code

bit.

Transmission is initiated when the processor or DMA con-

troller writes code bytes into the empty TX_FIFO. Trans-

mission is completed when the processor sets the S_EOT

bit (Bank 0 I/ O Offset 07h[2]), before writing the last byte,

or when the DMA controller activates the terminal count

(TC). Transmission also terminates if the processor simply

stops transferring data and the transmitter becomes empty.

In this case, however, a transmitter-underrun condition is

generated that must be cleared in order to begin the next

transmission.

The transmission bytes are either de-serialized or run-

length encoded, and the resulting bit-string modulates a

carrier signal that is sent to the transmitter LED. The trans-

fer rate of this bit-string, like in UART mode, is determined

by the value programmed in the Baud Generator Divisor

PARITY bits are not included in the transmitted data

stream. A logic 1 in the bit-string keeps the LED off, so no

IR signal is transmitted. A logic 0 generates a sequence of

modulating pulses that turn on the transmitter LED. Fre-

quency and pulse width of the modulating pulses are pro-

grammed by the MCFR and MCPW fields in the IRTXMC

TXHSC bit of the RCCFG register (Bank 7 I/O Offset

02h[2]).

The RC_MMD field (Bank 7 I/O Offset 02h[1:0]) selects the

transmitter modulation mode. If C_PLS mode is selected,

modulating pulses are generated continuously for the

entire logic 0 bit time. If 6_PLS or 8_PLS mode is selected,

six or eight pulses are generated each time a logic 0 bit is

transmitted following a logic 1 bit.

C_PLS modulation mode is used for RC-5, RC-6, NEC,

and RCA protocols. 8_PLS or 6_PLS modulation mode is

used for the RECS 80 protocol. The 8_PLS or 6_PLS

mode allows minimization of the number of bits needed to

represent the RECS 80 IR code sequence. The current

transmitter implementation supports only the modulated

modes of the RECS 80 protocol; it does not support the

Flash mode.

Note: The total transmission time for the logic 0 bits must

be equal to or greater than six or eight times the

period of the modulation subcarrier, otherwise

fewer pulses are transmitted.

CEIR Receive Operation

The CEIR receiver is significantly different from a UART

receiver. The incoming IR signals are DASK modulated;

therefore, demodulation may be necessary. Also, there are

no START bits in the incoming data stream.

The operations performed by the receiver, whenever an IR

signal is detected, are slightly different, depending on

whether or not receiver demodulation is enabled. If demod-

ulation is disabled, the receiver immediately becomes

active. If demodulation is enabled, the receiver checks the

carrier frequency of the incoming signal and becomes

active only if the frequency is within the programmed

range. Otherwise, the signal is ignored and no other action

is taken.

When the receiver enters the Active state, the RXACT bit

(Bank 0 I/O Offset 07h[5]) is set to 1. Once in the Active

state, the receiver keeps sampling the IR input signal and

generates a bit-string, where a logic 1 indicates an Idle

condition and a logic 0 indicates the presence of IR energy.

The IR input is sampled regardless of the presence of IR

pulses at a rate determined by the value loaded into the

Baud Generator Divisor Registers. The received bit-string

is either de-serialized and assembled into 8-bit characters,

or is converted to run-length encoded values. The resulting

data bytes are then transferred into the receiver FIFO

(RX_FIFO).

The receiver also sets the RXWDG bit (Bank 0 I/O Offset

07h[4]) each time an IR pulse signal is detected. This bit is

automatically cleared when the ASCR is read. It is

intended to assist the software in determining when the IR

link has been Idle for a period of time. The software can

then stop data from being received by writing a 1 into the

RXACT bit to clear it, and return the receiver to the inactive

state.

The frequency bandwidth for the incoming modulated IR

signal is selected by the DFR and DBW fields in the

IRRXDC register (Bank 7 I/O Offset 00h). There are two

CEIR receive data modes: Oversampled and Programmed

T Period. For either mode, the sampling rate is determined

by the setting of the Baud Generator Divisor Registers.

140 AMD Geode™ CS5536 Companion Device Data Book

UART and IR Port

33238G

Oversampled mode can be used with the receiver demodu-

lator either enabled or disabled. It should be used with the

demodulator disabled when a detailed snapshot of the

incoming signal is needed; for example, to determine the

period of the carrier signal. If the demodulator is enabled,

the stream of samples can be used to reconstruct the

incoming bit-string. To obtain good resolution, a fairly high

sampling rate should be selected.

Programmed T Period mode should be used with the

receiver demodulator enabled. The T Period represents

one-half bit time for protocols using biphase encoding or

the basic unit of pulse distance for protocols using pulse

distance encoding. The baud is usually programmed to

match the T Period. For long periods of logic low or high,

the receiver samples the demodulated signal at the pro-

grammed sampling rate.

When a new IR energy pulse is detected, the receiver syn-

chronizes the sampling process to the incoming signal tim-

ing. This reduces timing-related errors and eliminates the

possibility of missing short IR pulse sequences, especially

with the RECS 80 protocol. In addition, the Programmed T

Period sampling minimizes the amount of data used to rep-

resent the incoming IR signal, therefore reducing the pro-

cessing overhead in the host CPU.

5.12.1.5 FIFO Timeouts

Timeout mechanisms are provided to prevent received

data from remaining in the RX_FIFO indefinitely, in case

the programmed interrupt or DMA thresholds are not

reached.

An RX_FIFO timeout generates a Receiver Data Ready

interrupt and/or a receiver DMA request if bit 0 of the IER

respectively. An RX_FIFO timeout also sets bit 0 of the

ASCR register (I/O Offset 07h[0]) to 1 if the RX_FIFO is

below the threshold. When a Receiver Data Ready inter-

rupt occurs, this bit is tested by the software to determine

whether a number of bytes indicated by the RX_FIFO

threshold can be read without checking bit 0 of the LSR

The conditions that must exist for a timeout to occur in the

modes of operation are described below. When a timeout

has occurred, it can only be reset when the FIFO is read by

the processor or DMA controller.

Timeout Conditions for UART, SIR, and Sharp-IR

Modes

RX_FIFO timeout conditions:

•At least one byte is in the RX_FIFO.

•More than four character times have elapsed since the

last byte was loaded into the RX_FIFO from the receiver

logic.

•More than four character times have elapsed since the

last byte was read from the RX_FIFO by the processor

or DMA controller.

Timeout Conditions for CEIR Mode

The RX_FIFO timeout in CEIR mode is disabled while the

receiver is active. The conditions for this timeout to occur

are as follows:

•At least one byte has been in the RX_FIFO for 64 µs or

more.

•The receiver has been inactive (RXACT = 0) for 64 µs or

more.

•More than 64 µs have elapsed since the last byte was

read from the RX_FIFO by the processor or DMA

controller.

5.12.1.6 Transmit Deferral

This feature allows software to send short, high speed data

frames in PIO mode without the risk of generating a trans-

mitter underrun.

Transmit deferral is available only in extended mode and

when the TX_FIFO is enabled. When transmit deferral is

enabled (I/O Offset 04h[3] = 1) and the transmitter

becomes empty, an internal flag is set and locks the trans-

mitter. If the processor now writes data into the TX_FIFO,

the transmitter does not start sending the data until the

TX_FIFO level reaches either 14 for a 16-level TX_FIFO or

30 for a 32-level TX_FIFO, at which time the internal flag is

cleared. The internal flag is also cleared and the transmit-

ter starts transmitting when a timeout condition is reached.

This prevents some bytes from being in the TX_FIFO indef-

initely if the threshold is not reached.

The timeout mechanism is implemented by a timer that is

enabled when the internal flag is set and there is at least

one byte in the TX_FIFO. Whenever a byte is loaded into

the TX_FIFO, the timer is reloaded with the initial value. If

no byte is loaded for a 64 µs time, the timer times out and

the internal flag is cleared, thus enabling the transmitter.

AMD Geode™ CS5536 Companion Device Data Book 141

UART and IR Port 33238G

5.12.1.7 Automatic Fallback to 16550 Compatibility

Mode

This feature is designed to support existing legacy software

packages, using the 16550 serial port. For proper opera-

tion, many of these software packages require that the

device look identical to a plain 16550, since they access

the serial port registers directly. Because several extended

features and new operational modes are provided, make

sure the device is in the proper state before executing a

legacy program.

The fallback mechanism eliminates the need to change the

state when a legacy program is executed following comple-

tion of a program that used extended features. It automati-

cally switches the device to 16550 compatibility mode and

turns off any extended features whenever the Baud Gener-

ator Divisor Register is accessed through the LBGD_L or

LBGD_H ports in register Bank 1.

In order to avoid spurious fallbacks, baud generator divisor

ports are provided in Bank 2. Baud generator divisor

access through these ports changes the baud rate setting

but does not cause fallback.

New programs designed to take advantage of the extended

features should not use LBGD_L and LBGD_H to change

the baud rate. Instead, they should use BGD_L and

BGD_H.

A fallback can occur in either extended or non-extended

modes. If extended mode is selected, fallback is always

enabled. In this case, when a fallback occurs, the following

happens:

•TX_FIFO and RX_FIFO switch to 16 levels.

•A value of 13 is selected for the baud generator pre-

scaler.

•ETDLBK and LOOP of the EXCR1 register are cleared

(Bank 2 I/O Offset 02h[5:4]).

•UART mode is selected.

•The functional block switches to non-extended mode.

When fallback occurs from non-extended mode, only the

first three of the above actions occur. If either Sharp-IR or

SIR infrared modes were selected, no switching to UART

mode occurs. This prevents spurious switching to UART

mode when a legacy program, running in Infrared mode,

accesses the Baud Generator Divisor Register from Bank

Fallback from non-extended mode can be disabled by set-

ting LOCK in the EXCR2 register to 1 (I/O Offset 04h[7] =

1). When LOCK is set and the functional block is in non-

extended mode, two scratch pad registers overlaid with

LBGD_L and LBGD_H are enabled. Any attempted proces-

sor access of the Baud Generator Divisor Register through

LBGD_L and LBGD_H accesses the scratch pad registers,

without affecting the baud rate setting. This feature allows

existing legacy programs to run faster than 115.2 Kbaud,

without realizing they are running at this speed.

5.12.2 Modem Support

An MSR (MSR_UART[x]_MOD) (UART1 MSR 51400038h

and UART2 MSR 5140003Ch) mimics modem input sig-

nals for making it compatible with the software having

modem support. The hardware of this device has all the

required functionality for modem compatibility.

142 AMD Geode™ CS5536 Companion Device Data Book

UART and IR Port

33238G

5.12.3 Dongle Interface

The dongle interface on the CS5536 companion device is

not a fully hardware compatible interface. The real dongle

interface requires six external interface signals and the

CS5536 companion device only supports three. With only

three signals, the dongle interface supports a subset of the

real dongle interface through virtualization.

5.12.3.1 Real Dongle

The real dongle interface uses six multiplexed pins for don-

gle identification, data transfer, and transceiver configura-

tion. Figure 5-35 on page 142 illustrates the real dongle

interface and Table 5-21 provides the interface signals and

their descriptions.

Only three signals (IRTX, IRRX, and ID0/IRSL0/IRRX2) are

used for the IR interface. It has three phases:

Phase 1:

Change the ID0-ID3 bits to input mode, and read the

status to complete primary identification of the dongle.

Phase 2:

Change ID1 and ID2 as output and read the status of

ID0 and ID3 to complete the secondary dongle identifi-

cation phase. This phase provides information about

the connected dongle.

Phase 3:

Configure mode: Change IRSL[2:0] to an output and

configure the transceiver for the required mode. If two

infrared inputs are required, change IRSL0 to an input

to give the second receiver channel IRRX2. The IRSL2

and IRSL1 are configured as outputs to keep the

transceiver in the required mode.

Figure 5-35. Real Dongle Interface

Table 5-21. Real Dongle Interface Signals

Signal Name Type Description

IRTX O Infrared transmit data

IRRX I Infrared receive data

ID0/IRSL0/IRRX2 I/O Identification signal 0

Infrared mode select 0

Infrared receive data for

transceivers with two RX

channels

ID1/IRSL1 I/O Identification signal 1

Infrared mode select 1

ID2/IRSL2 I/O Identification signal 2

Infrared mode select 2

ID3 I/O Identification signal 2

Shielded

Cable

IrDA-Data Transceiver with Receive Channels

TXRX-ARX-B

Controller

Transceiver Select Logic

Resistance

Pull-up

IRTX

IRRXI

ID0/IRSL0/IRRX2

ID1/IRSL1

ID2/IRSL2

ID3

ASIC Boundary

AMD Geode™ CS5536 Companion Device Data Book 143

UART and IR Port 33238G

5.12.3.2 Virtual Dongle

The virtual dongle interface is used due to the unavailability

of pins for dongle identification and configuration (see Fig-

ure 5-36).

The virtual dongle interface is a method used to run legacy

software on the UART/IR Controller. The virtual dongle

interface uses dedicated UART/IR MSRs. (See Section

6.12.1 "UART/IR Controller Specific MSRs" on page 410

for complete register and bit formats.) The virtual dongle

imitates the real dongle as far as legacy software is con-

cerned, and there are no plug-and-play requirements for IR

transceivers.

•The software inputs the dongle's ID to the ID[0:3] bits of

UART[x]_MOD (UART1 MSR 51400038h and UART2

MSR 5140003Ch) as the primary ID encoding.

•For dongles that use a non-serial transceiver, it identifies

the Consumer IR capabilities. The software should

switch ID1 and ID2 to output mode (so they become

IRSL1 and IRSL2). IRSL1 and IRSL2 will or will not

behave differently (i.e., INV [invert] or NCH [no change])

from the previous step and the software should respond

by driving the appropriate level on ID0 and ID3 in the

UART[x]_DONG register.

The operational mode of an infrared dongle that uses a

non-serial transceiver is selected by driving the IRSL[2:0]

signals.

Features

•Uses only three pins to connect to IR transceiver.

•Fully supports legacy software written for real dongle,

with some manual intervention.

•All real dongle modes can be supported by changing the

MSR.

Limitations

•No Plug-and-Play features available.

•IRSL1 and IRSL2 pins must be tied in the IR transceiver

for the required mode.

•MSR contents must be changed when changing the

transceiver mode. If BIOS is used to change the MSR

contents, it must be a factory setting.

•If the legacy software supports IR transceiver configura-

tion, the contents of IRSL[2:0] are to be read from the

MSR and the required bit tieing must be done in the

transceiver board.

Figure 5-36. Virtual Dongle Interface

Mux

IR Controller

ID1 ID2 ID0 ID3

UART/IR Controller

MSR_UART[x]_MOD MSR_UART[x]_DONG

IRSL0 IRSL1 IRSL2

IRTXIRRX1 ASIC Boundary

IR Transceiver Tie IRSL1

and IRSL2

IRSL1

IRSL2

ID1 ID2 ID0 ID3

ID0_SEC ID3_SEC

144 AMD Geode™ CS5536 Companion Device Data Book

Low Pin Count Port

33238G

5.13 Low Pin Count Port

The Low Pin Count port is based on Intel’s Low Pin Count

(LPC) Interface Specification v1.0. In addition to the

required pins, the CS5536 companion device also supports

two optional pins: LDRQ# and SERIRQ. The LPC interface

supports memory, I/O, DMA, and Intel’s Firmware Hub

Interface. Figure 5-37 shows the block diagram of the LPC

port.

Features

•Based on Intel’s Low Pin Count (LPC) Specification

v1.0.

•Serial IRQ support.

•Supports memory, I/O, and DMA cycle types.

•Bus master cycles not supported.

•CLKRUN# and LPCPD# not supported. SMI# and PME#

supported via GPIOs.

•On-chip DMA transfers through LPC.

•Supports Intel’s FirmWare Hub (FWH) Interface:

— 5 Signal communication interface supporting byte-at-

a-time reads and writes.

— LAD[3:0] called as FWH0-FWH3 and LFRAME# as

FWH4.

Figure 5-37. LPC Block Diagram

GeodeLink™ Adapter (GLA)

Local Bus

Local Bus Slave Local Bus Master

LPC Master

DRQ

LDRQSIRQ

LPC Reg

To PI C

LFRAME# LDRQ#LAD[3:0]SERIRQ

To DMA

From DMA

LPC to/from Local Bus

Busy

LPC Master Initiates all transactions on LPC bus, takes/issues requests from Local bus.

Local Bus Master Takes request from LPC master and DMA.

Local Bus Slave Issues request to LPC master from Local bus.

SIRQ Decodes SERIRQ into IRQ to be passed on to PIC.

LDRQ Decodes LDRQ# into DRQ sets and clears.

DRQ Combines multiple LDRQ# outputs and passes results to DMA.

LPC Reg Contains all the LPC I/O registers.

LPC to/from Local Bus LPC to Local bus interface block.

Busy Generates busy signal for clock controls.

AMD Geode™ CS5536 Companion Device Data Book 145

Low Pin Count Port 33238G

5.13.1 LPC Protocol

The LPC port supports memory read/write, I/O read/write,

DMA read/write, and Firmware Hub Interface (see Table 5-

22). Data transfers on the LPC bus are serialized over a 4-

bit bus.

LFRAME# is used by the host to start or stop transfers. No

peripherals drive this signal. A cycle is started by the host

when it drives LFRAME# active and puts information

related to the cycle on the LAD[3:0] signals. The host

drives information such as address or DMA channel num-

ber. For DMA and target cycles, the host drives cycle type

(memory or I/O), read/write direction, and size of the trans-

fer. The host optionally drives data, and turns around to

monitor peripherals for completion of the cycle. The periph-

eral indicates the completion of the cycle by driving appro-

priate values on the LAD[3:0] signals.

The LAD[3:0] signals communicate address, control, and

data information over the LPC bus between the host and

the peripheral. The information carried on the LAD signals

are: start, stop (abort a cycle), transfer type (memory, I/O,

DMA), transfer direction (read/write), address, data, wait

states, and DMA channel number. The following sections

give an overview of fields used. Detailed field descriptions

are provided in Table 5-23 on page 146.

START: This field indicates the start or stop of a transac-

tion. The START field is valid on the last clock that

LFRAME# is active. It is used to indicate a device number,

or start/stop indication.

CYCTYP: The Cycle Type field is driven by the host when it

is performing DMA or target accesses. Bits [3:2] are used

for cycle type and bit 1 is used for direction. Bit 0 is

reserved.

SIZE: This field is one clock. It is driven by the host on

memory and DMA transfers to determine how many bytes

are to be transferred. Bits [1:0] are used to determine size

and bits [3:2] are reserved.

TAR: The Turn Around field is two clocks, and is driven by

the host when it is turning control over to a peripheral and

vice versa. In the first clock a host or a peripheral drives the

LAD[3:0] lines to 1111, on the second cycle the host or

peripheral TRI-STATES the LAD[3:0] lines. These lines

have weak pull-ups so they will remain at a logical high

state.

ADDR: The Address field is four clocks for I/O cycles and

eight clocks for memory cycles. It is driven by the host on

target accesses. This field is not driven on DMA cycles.

The most significant nibble is driven first.

CHANNEL/Terminal Count: The Channel field is one

clock and driven by the host on DMA cycles to indicate the

DMA channel. Only 8-bit channels are supported (0, 1, 2,

3). DMA channel is communicated on LAD[2:0] and Termi-

nal Count (TC) is communicated through LAD3. TC indi-

cates the last byte of transfer, based upon the size of the

transfer. If an 8-bit transfer and TC is set, then this is the

last byte.

DATA: This field is two clocks, representing one byte data.

It is driven by the host on target and DMA cycles when data

is flowing to the peripheral, and by the peripheral when

data is flowing to the host. The lower nibble is driven first.

SYNC: This field can be several clocks in length and is

used to add wait states. Driven by the peripheral on target

or DMA cycles.

SYNC Timeout:

1) The host starts a cycle, but no device ever drives

SYNC valid. If the host observes three consecutive

clocks without a valid SYNC, it can abort the cycle.

2) The host starts a cycle, a device drives a SYNC valid

to insert wait states (LAD[3:0] = 0101 or 0110), but

never completes it. This could happen if the peripheral

locks up for some reason. The peripheral should be

designed to prevent this case:

– If the SYNC pattern is 0101, then the maximum

number of SYNC clocks is eight. If the host sees

more than eight, it may abort the cycle.

– If the SYNC pattern is 0110, then no maximum

number of SYNC clocks took place, the peripheral

must have protection mechanisms to complete the

cycle.

Table 5-22. Cycle Types Supported

Cycle Type Size

Size

Supported

Intel FWH Read 1 Byte Yes

Intel FWH Write 1 Byte Yes

Memory Read 1 Byte Yes

Memory Write 1 Byte Yes

I/O Read 1 Byte Yes

I/O Write 1 Byte Yes

DMA Read 1, 2, 4 Bytes 1 Byte Only

DMA Write 1, 2, 4 Bytes 1 Byte Only

Bus Master Mem Read 1, 2, 4 Bytes No

Bus Master Mem Write 1, 2, 4 Bytes No

Bus Master I/O Read 1, 2, 4 Bytes No

Bus Master I/O Write 1, 2, 4 Bytes No

146 AMD Geode™ CS5536 Companion Device Data Book

Low Pin Count Port

33238G

When the host is driving SYNC, it may insert a very large

number of wait-states depending on PCI latencies. The

peripheral must not assume any timeouts.

SYNC Error Indication: A peripheral can report an error via

the LAD[3:0] = 1010 encoding. If the host was reading data

from a peripheral, the data is still transferred in the next two

nibbles, even though this data is invalid, the peripheral

must transfer it. If the host was writing, data had already

been transferred.

In DMA, if it was a multiple byte cycle, an error SYNC ter-

minates the cycle.

For more info on SYNC timeout and SYNC error details,

refer to the LPC Specification.

Table 5-23. Cycle Field Definitions: Target Memory, I/O, and DMA

Field # Clocks Comment

START 1 Start of Cycle. 0000 indicates a start of a cycle.

CYCTYP 1 Cycle Type. Indicates the type of cycle.

Bits [3:0] Definition

000x I/O Read

001x I/O Write

010x Memory Read

011x Memory Write

100x DMA Read

101x DMA Write

1100 Reserved

1101 FWH Read

1110 FWH Write

1111 Reserved

CHANNEL 1 Channel #. Used only for DMA cycles to indicate channel number being granted. The LAD[2:0]

bits indicate the channel number being granted, and LAD[3] indicates the TC bit. The encoding

on LAD[2:0] for channel number is as follows:

LAD[2:0] Definition

000 I/O Read

001 I/O Write

010 Memory Read

011 Memory Write

100-111 Reserved

Only 8-bit channels are supported.

TAR 2 Turn-Around. The last component driving LAD[3:0] will drive it high during the first clock and

TRI-STATE during the second clock.

SIZE 1 Size of Transfer. Used only for DMA cycles. Bits [3:0] are reserved and must be ignored by the

peripheral.

LAD[1:0] Definition

00 8-Bit

01-11 Reserved

Only 8-bit is supported for all transfers.

DATA 1 Byte

DMA: 1 Byte

Data Phase. The data byte is transferred with the least significant nibble first (D[3:0] on

LAD[3:0], then D[7:4] on LAD[3:0]).

DMA. The data byte is transferred with the least significant nibble first (D[3:0] on LAD[3:0], then

D[7:4] on LAD[3:0]). Only one byte data transfer is supported.

ADDR 8 for Memory,

4 for I/O

Address Phase. Address is 32-bit for memory, 16-bit for I/O. It is transferred most significant

nibble first.

DMA cycles do not use the ADDR field.

AMD Geode™ CS5536 Companion Device Data Book 147

Low Pin Count Port 33238G

5.13.2 Cycle Protocol

Start of Cycle (see Figure 5-38): The host asserts

LFRAME# for one or more clocks and drives a START

value on LAD[3:0], all peripherals stop driving the LAD[3:0]

signals even if in the middle of a transfer. The peripheral

must always use the last START value when LFRAME#

was active. On the clock after the START value, the host

de-asserts LFRAME#.

Abort Mechanism (see Figure 5-39): The host can cause

an abort on the LPC interface by driving LFRAME# active

with a START value of 1111. The host must keep

LFRAME# active for at least four consecutive clocks and

drive LAD[3:0] to 1111 no later than the fourth clock after

LFRAME# goes active. The host must drive LFRAME#

inactive for at least one clock after an abort.

An abort typically occurs on SYNC timeouts.

Figure 5-38. Start of Cycle Timing Diagram

Figure 5-39. Abort Mechanism Timing Diagram

SYNC 1-N Sync: Allows peripheral or host to synchronize (add wait-states). Generally, the peripheral or

host drives 0101 or 0110 until no more wait-states are needed. At that point it will drive 0000. All

other combinations are reserved.

0000 Sync achieved with no error.

DMA. Sync achieved with no error. Also indicates no more transfer desired for that chan-

nel, and DMA request is de-asserted.

0101 Indicates that Sync not achieved yet, but the part is driving the bus.

DMA. Part indicating wait states.

0110 Indicates that Sync not achieved yet, but the part is driving the bus, and expect long

Sync.

DMA. Part indicating wait states, and many wait states will be added.

1010 Special case. Peripheral indicating errors, see sync section in protocol overview.

DMA. Sync achieved with error. Also indicates no more transfers desired for that channel,

and DMA request is de-asserted.

1001 DMA (only). Sync achieved with no error and more DMA transfer desired to continue

after this transfer.

Table 5-23. Cycle Field Definitions: Target Memory, I/O, and DMA (Continued)

Field # Clocks Comment

START CYCTYP

LCLK

LAD[3:0]#

LFRAME#

ADDR TAR SYNC DATA START

TAR

1 1 - 8 2 1 - n 2 2 1

START CYCTYP

LCLK

LAD[3:0]#

LFRAME#

ADDR TAR SYNC

11 - 8

Too many

Peripheral must

Stop driving

Chip set will

drive high

Syncs cause

Timeout

148 AMD Geode™ CS5536 Companion Device Data Book

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33238G

5.13.2.1 Host Initiated Cycles

Memory Cycles: Memory read or write cycles are

intended for memory-mapped devices. The ADDR field is a

full 32 bits, and transmitted with most significant nibble first.

Typically a memory device supports much less addressing

and ignores address bits above which it is capable of

decoding.

I/O Cycles: I/O read or write cycles are intended for

peripherals. These cycles are generally used for register or

FIFO accesses and have minimal Sync times. Data trans-

fers are assumed to be exactly 1 byte. The host is respon-

sible for breaking up larger data transfers into 8-bit cycles.

The minimum number of wait states between bytes is 1.

The host initiated cycles are shown in Table 5-24.

5.13.2.2 DMA Initiated Cycles

DMA on LPC is handled through the LDRQ# line from

peripherals and special encoding on LAD[3:0] for the host.

Single, demand, verify, and increment mode are supported

on the LPC interface. Block, decrement, and cascade are

not supported. Channels 0 through 3 are 8-bit channels.

Only 8-bit channels are supported.

Asserting DMA Requests: Peripherals need the DMA

service to encode their request channel number on the

LDRQ# signal. LDRQ# is synchronous with LCLK. Periph-

erals start the sequence by asserting LDRQ# low. The next

3 bits contain the encoded DMA channel number with the

MSB first. And the next bit (ACT) indicates whether the

requested channel is active or not. The case where ACT is

low (inactive) will be rare, and is only used to indicate that a

previous request for that channel is being abandoned. After

indication, LDRQ# should go high for at least one clock.

After that one clock, LDRQ# can be brought low for the

next encoding sequence (see Figure 5-40.)

DMA Transfer: Arbitration for DMA channels is performed

through the 8237 within the host. Once the host won the

arbitration, it asserts LFRAME# on the LPC bus. The host

starts a transfer by asserting 0000 on LAD[3:0] with

LFRAME# asserted. The host’s assert “cycle type” and

direction is based on the DMA transfer. In the next cycle it

asserts channel number and in the following cycle it indi-

cates the size of the transfer.

DMA Reads: The host drives 8 bits of data and turns the

bus around, then the peripheral acknowledges the data

with a valid SYNC.

DMA Writes: The host turns the bus around and waits for

data, then the peripheral indicates data is ready through

valid SYNC and transfer of the data.

The DMA initiated cycles are shown in Table 5-25.

Figure 5-40. DMA Cycle Timing Diagram

Table 5-24. Host Initiated Cycles

Memory or I/O

Driven By

Read Cycle Write Cycle

START Host Host

CYCTYP + DIR Host Host

ADDR Host Host

TAR Host Host

SYNC Peripheral Peripheral

DATA Peripheral Host

TAR Peripheral Peripheral

Table 5-25. DMA Initiated Cycles

DMA

Driven By

Read Cycle

(Host to

Peripheral)

Write Cycle

(Peripheral to

Host)

START Host Host

CYCTYP Host Host

CHANNEL Host Host

SIZE Host Host

DATA Host Host

TAR Host Peripheral

SYNC Peripheral Peripheral

TAR Peripheral Peripheral

START MSB LSB ACT START

LCLK

LDRQ#

AMD Geode™ CS5536 Companion Device Data Book 149

Low Pin Count Port 33238G

5.13.3 Serial IRQ

The LPC supports a serial IRQ scheme. This allows a sin-

gle signal to be used to report ISA-style interrupt requests.

Because more than one device may need to share the sin-

gle serial IRQ signal, an Open Collector signaling scheme

is used.

Serial interrupt information is transferred using three types

of frames: a Start frame, one or more IRQ Data frames,

and one Stop frame (see Figure Figure 5-41, Figure 5-42,

and Figure 5-43 on page 150). There are also two modes

of operation. Quiet mode, initiated by the peripheral, and

Continuous mode, initiated by the host:

1) Quiet (Active) Mode: To indicate an interrupt, the

peripheral brings the SERIRQ signal active for one

clock, and then places the signal in TRI-STATE mode.

This brings all the state machines from the Idle state to

the Active state.

The host then takes control of the SERIRQ signal by

driving it low on the next clock, and continues driving it

low for 3-7 clocks more (programmable). Thus, the

total number of clocks low will be 4-8. After those

clocks, the host drives SERIRQ high for one clock and

then places SERIRQ into TRI-STATE mode.

2) Continuous (Idle) Mode: In this mode, the host ini-

tiates the Start frame, rather than the peripherals. Typ-

ically, this is done to update IRQ status

(acknowledges). The host drives SERIRQ low for 4-8

clocks. This is the default mode after reset; it can be

used to enter the Quiet Mode.

Data Frame

Once the Start frame has been initiated, all of the serial

interrupt peripherals must start counting frames based on

the rising edge of the SERIRQ. Each of the IRQ/DATA

frames has exactly three phases of one clock each: a Sam-

ple phase, a Recovery phase, and a Turn Around phase.

During the sample phase, the device drives SERIRQ low if

the corresponding interrupt signals should be active. If the

corresponding interrupt is inactive, then the devices should

not drive the SERIRQ signal. It will remain high due to pull-

up registers. During the other two phases (Turn Around

and Recovery), no device should drive the SERIRQ signal.

The IRQ/DATA frames have a specific order and usage as

shown in Table 5-26.

Stop Frame

After all of the Data frames, a Stop frame is performed by

the host. This is accomplished by driving SERIRQ low for

two to three clocks. The number of clocks determines the

next mode:

•If the SERIRQ is low for two clocks, the next mode is the

Quiet mode. Any device may initiate a Start frame in the

second clock (or more) after the rising edge of the Stop

frame.

•If SERIRQ is low for three clocks, the next cycle is the

Continuous mode. Only the host may initiate a Start

frame in the second clock (or more) after the rising edge

of the Stop frame.

Table 5-26. IRQ Data Frames

Date Frame Number Usage

0IRQ0

1IRQ1

2 SMI# (Not Supported)

3IRQ3

4IRQ4

5IRQ5

6IRQ6

7IRQ7

8IRQ8

9IRQ9

10 IRQ10

11 IRQ11

12 IRQ12

13 IRQ13

14 IRQ14

15 IRQ15

31-16 Unassigned

150 AMD Geode™ CS5536 Companion Device Data Book

Low Pin Count Port

33238G

Figure 5-41. Start Frame Waveform

Figure 5-42. IRQ Frame Waveform

Figure 5-43. Stop Frame Waveform

START REC TAR

Drivers Host

Slave

Host Controller None

LCLK

SERIRQ

START: Start pulse width can be from 4-8 cycles, the width is determined by the value of START width.

REC: Recover, host actively drives SERIRQ high.

TAR: Turn Around Cycle. Dead cycle to prevent bus contention.

IRQ Set:

IRQ Clear:

SERIRQ

LCLK

SAMP REC TAR

None

IRQX

SERIRQ SAMP REC TAR

Driver

NoneDriver

SAMP: Sample, slave drives low or leaves high.

REC: Recover, slave actively drives SERIRQ high if driven low during sample.

TAR: Turn Around Cycle. Dead cycle to prevent bus contention.

STOP REC TAR

Host Controller

None

Drivers

SERIRQ

LCLK

Quiet Mode:

Continues Mode:

STOP REC TAR

SERIRQ

Host Controller

None

Drivers

REC: Recover, host actively drives SERIRQ high.

TAR: Turn Around Cycle. Dead cycle to prevent bus contention.

AMD Geode™ CS5536 Companion Device Data Book 151

Low Pin Count Port 33238G

5.13.4 Firmware Hub Interface

The Firmware Hub (FWH) relies on the Intel Firmware Hub

interface to communicate with the outside world. This inter-

face consists of four bidirectional signals and one “control”

input. The timing and the electrical parameters of the FWH

interface are similar to those of the LPC interface. The Intel

FWH interface is designed to use an LPC-compatible Start

cycle, with a reserved cycle type code. This ensures that all

LPC devices present on the shared interface will ignore

cycles destined for the FWH, without becoming “confused”

by the different protocols.

When the FWH interface is active, information is trans-

ferred to and from the FWH by a series of “fields” where

each field contains four bits of data. Many fields are one

clock cycle in length but can be of variable length, depend-

ing on the nature of the field. Field sequences and contents

are strictly defined for read and write operations.

5.13.4.1 FWH Cycles

A cycle is started on the rising edge of LCLK when

LFRAME# is asserted and a valid cycle type is driven on

LAD[3:0] by the host. Valid cycle types for the FWH are

1101 (read) and 1110 (write).

FWH Read Cycles: A read cycle is initiated by asserting

1101 on LAD[3:0] with LFRAME# low. All data transfers are

valid on the rising edge of the LCLK. The cycle is illustrated

in Figure 5-44 on page 152 and described in Table 5-27 on

page 152.

FWH Write Cycles: A write cycle is initiated by asserting

1110 on LAD[3:0] with LFRAME# low. All data transfers are

valid on the rising edge of the LCLK. The cycle is illustrated

in Figure 5-45 on page 153 and described in Table 5-28 on

page 153.

Abort Operation: LFRAME# (FWH4) active (low) indi-

cates either that a Start cycle will eventually occur or that

an abort is in progress. In either case, if LFRAME# (FWH4)

is asserted, the Intel FWH will “immediately” TRI-STATE its

outputs and the FWH state machine is reset.

During a write cycle, there is a possibility that an internal

Flash write or erase operation is in progress (or has just

been initiated). If LFRAME# (FWH4) is asserted during this

frame, the internal operation will not abort. The software

must send an explicit Flash command to terminate or Sus-

pend the operation.

The internal FWH state machine will not initiate a Flash

write or erase operation until it has received the last data

nibble from the chip set. This means that LFRAME#

(FWH4) can be asserted as late as this cycle (“cycle 12")

and no internal Flash operation will be attempted. However,

since the Intel FWH will start “processing” incoming data

before it generates its SYNC field, it should be considered

a non-buffered peripheral device.

152 AMD Geode™ CS5536 Companion Device Data Book

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33238G

Figure 5-44. FWH Read Cycle

Table 5-27. FWH Read Cycle

Signal

Clock

Cycle LAD[3:0]

Peripheral

I/O Description

START 1 1101 I On the rising edge of CLK with LFRAME# low, the contents of

LAD[3:0] indicate the start of an FWH cycle.

IDSEL 1 0000 I Indicates which FWH peripheral is selected. The value on the

LAD[3:0] is compared to the IDSEL strapping on the FWH device

pins to select which device is being addressed.

Note: From Intel 82802 Specification - the boot device must have

an ID (determined by ID strapping pins ID[3:0]) of 0. It is advisable

that subsequent devices use incremental numbering.

ADDR 7 xxxx I A 28-bit address phase is transferred starting with the most signifi-

cant nibble first.

MSIZE 1 0000 I Always 0000 (single byte transfer).

TAR 1 1111 I The LPC host drives LAD[3:0] to 1111 to indicate a turnaround

cycle.

TAR 1 1111

(float)

O The FWH device takes control of LAD[3:0] during this cycle.

WSYNC 2 0101 O The FWH device drives LAD[3:0] to 0101 (short wait-sync) for two

clock cycles, indicating that the data is not yet available.

RSYNC 1 0000 O The FWH device drives LAD[3:0] to 0000, indicating that data will

be available during the next clock cycle.

DATA 2 xxxx O Data transfer is two cycles, starting with least significant nibble.

TAR 1 1111 O The FWH device drives LAD[3:0] to 1111, to indicate a turnaround

cycle.

TAR 1 1111

(float)

N/A The FWH device floats its output and the LPC host takes control of

LAD[3:0].

LCLK

LFRAME#

LAD[3:0]

(FWH3-FWH0)

Number of Clock Cycles

START IDSEL ADDR MSIZE TARSYNC DATATAR

172311 22

(FWH4)

AMD Geode™ CS5536 Companion Device Data Book 153

Low Pin Count Port 33238G

Figure 5-45. FWH Write Cycle

Table 5-28. FWH Write Cycle

Signal

Clock

Cycle LAD[3:0]

Peripheral

I/O Description

START 1 1110 I On the rising edge of CLK with LFRAME# Low, the contents of

LAD[3:0] indicate the start of an FWH cycle.

IDSEL 1 0000 I Indicates which FWH peripheral is selected. The value on the

LAD[3:0] is compared to the IDSEL strapping on the FWH device

pins to select which device is being addressed.

Note: From Intel(R) 82802 spec - the boot device must have an ID

(determined by ID strapping Pins ID[3:0]) of 0. It is advisable that

subsequent devices use incremental numbering.

ADDR 7 xxxx I A 28-bit address phase is transferred starting with the most signifi-

cant nibble first.

MSIZE 1 0000 I Always 0000 (single byte transfer).

DATA 2 xxxx I Data transfer is two cycles, starting with least significant nibble.

TAR 1 1111 I The LPC host drives LAD[3:0] to 1111 to indicate a turnaround

cycle.

TAR 1 1111

(float)

O The FWH device takes control of LAD[3:0] during this cycle.

SYNC 1 0000 O The FWH device drives LAD[3:0] to 0000 to indicate it has received

data or a command.

TAR 1 1111 O The FWH device drives LAD[3:0] to 1111, indicating a turnaround

cycle.

TAR 1 1111

(float)

N/A The FWH device floats its output and the LPC host takes control of

LAD[3:0].

LCLK

LFRAME#

LAD[3:0]

(FWH0-FWH3)

Number of Clock Cycles

START IDSEL ADDR MSIZE TAR

SYNCDATA TAR

172211 21

(FWH4)

154 AMD Geode™ CS5536 Companion Device Data Book

Real-Time Clock Features

33238G

5.14 Real-Time Clock Features

The Real-Time Clock (RTC) consists of three main blocks:

digital, analog, and level shifter (see Figure 5-46). The digi-

tal block contains the bus interface, RAM, voltage control,

time generator, and the time keeper. The analog block con-

tains the voltage switch and low power crystal oscillator.

Finally, the level shifter block provides the appropriate volt-

age level translation of signals to and from the RTC block.

Level shifters are needed because the RTC is powered by

the VPP (output of the analog section), which is different

from the VCORE and VCORE_VSB power domains.

Features

•Accurate timekeeping and calendar management

•Alarm at a predetermined time and/or date

•Three programmable interrupt sources

•Valid timekeeping during power-down, by utilizing

external battery backup

•242 bytes of battery-backed RAM

•RAM lock schemes to protect its content

•Internal oscillator circuit (the crystal itself is off-chip), or

external clock supply for the 32.768 KHz clock

•A century counter

•Additional low-power features such as:

— Automatic switching from battery to VSB

— Internal power monitoring on the VRT bit

— Oscillator disabling to save battery during storage

•Software compatible with the DS1287 and MC146818

Figure 5-46. RTC Block Diagram

rtc_seconds

rtc_minutes

rtc_hours

rtc_monthday

rtc_months

rtc_years

Time Keeper

Index_Reg

Ctrl_Reg A, B, C, D

RAM I/F

Gated Clocks

Bus Interface

q q q

Time Generator

Update

242x8 Bit RAM

Voltage Control

Voltage Switch

Low Power Osc. 32 KHz Clock

VPP

VIO_VSB

VBAT

KHZ32_XCI

Write

Index Read

Local Bus

Data & Ctrls

#0 #1 #14

KHZ32_XCO

Level Shifter

rtc_weekday

DataData

Clock

Voltage

Sense

Voltage

Select

AMD Geode™ CS5536 Companion Device Data Book 155

Real-Time Clock Features 33238G

5.14.1 External Use Recommendations

It is recommended that the external components for the

oscillator be connected as illustrated in Figure 5-47. The

recommended specifications for those external compo-

nents are listed in Table 5-29.

Capacitors C1, C2, and C3 should be chosen to match the

crystal’s load capacitance. The load capacitance CL “seen”

by the crystal Y is comprised of C1, C2, and C3 in parallel

with the parasitic capacitance of the circuit. The parasitic

capacitance is caused by the chip package, board layout,

and socket (if any). The rule of thumb in choosing these

capacitors is:

CL = (C1 * C2)/(C1 + C2) + C3 + CPARASITIC

To achieve high time accuracy, use crystal and capacitors

with low tolerance and temperature coefficients.

Figure 5-47. Recommended External Component Connections

Table 5-29. External Component Recommended Specifications

Component Parameters Values Tolerance

Crystal Resonance 32.768 KHz Parallel Mode User-defined

Type N-Cut or XY-bar

Serial Resistance 35 kΩMax

Q Factor 90K Typ

Shunt Capacitance 1.6 pF Max

Load Capacitance, CL12.5 pF

Capacitance Ratio 460 Typ

Drive Level 1 μWMax

Temperature Coefficient User-defined

Resistor, R1 Resistor 10 MΩ5%

Resistor, R2 Resistor 1 MΩ5%

Capacitor, C1 Capacitor 22 pF 5%

Capacitor, C2 Capacitor 22 pF 5%

Capacitor, C3 Capacitor 1 pF 5%

To other modules

C1 C2

Internal

External

KHZ32_XCI KHZ32_XCO

156 AMD Geode™ CS5536 Companion Device Data Book

General Purpose Input/Output

33238G

5.15 General Purpose Input/Output

Proper use and understanding of the General Purpose

Input/Output (GPIO) subsystem is the key to applying the

AMD Geode™ CS5536 companion device in a custom sys-

tem design. By totalizing the optional features of the

CS5536 companion device GPIOs, system functions such

as soft buttons, DDC monitoring, timers, system interrupts,

etc. may be implemented. The system designer should pay

careful attention to the suite of features available through

the GPIO subsystem and, because the GPIOs are multi-

plexed with other on-chip functions, must make careful

trade-offs to obtain the features desired in the system.

The register space for control of the GPIO subsystem con-

tains space for control of 32 GPIOs. Since only 28 GPIOs

are realized, the control bits for the non-existent

GPIO[31:29], and GPIO[23] are marked “Reserved”.

GPIO[22:16] are multiplexed with the LPC bus; therefore, if

the system requires an LPC bus, GPIO[22:16] are not

available as GPIOs. Likewise, GPIO[15:14] are multiplexed

with the SMB (System Management Bus); if the system

requires the SMB, GPIO[15:14] are dedicated to this func-

tion and not available as GPIOs. Other GPIOs are multi-

plexed with individual functions as indicated in Table 3-8

"GPIO Options" on page 47.

Features

•Input Features:

— Each of the available GPIOs may be configured as

an input. A block of eight Input Conditioning Func-

tions, providing edge detection, event counting, and

input filtering, may be configured for use by any eight

of the 28 GPIOs, though all 28 may have edge detec-

tion. The optionally-conditioned input may then be

fed to steering logic that can connect it to an inter-

rupt, or power-management input event (PME).

•Output Features:

— Each of the available 28 GPIOs has a configurable

output cell. The output cell for each GPIO may be

independently configured to provide a variety of inter-

face options. The cell may be enabled or disabled,

configured as a totem-pole or open-drain type, have

internal pull-up or pull-down resistors applied, or be

inverted.

— As indicated in Table 3-8 "GPIO Options" on page 47,

the GPIOs have differing output driver types and

reset defaults. When choosing a GPIO for a given

function, choose one with a compatible output driver

type, and one that the use of, does not make another

desired function inaccessible. Careful study of this

table will assist the system designer in making proper

selections of the desired functionality of the suite of

GPIOs.

•Auxiliary Functions

— Most of the 28 GPIOs have additional hard-wired

internally-connected functions that may be selected

by choosing either the AUX_1 or AUX_2 outputs. Use

of these allows internal functions to be accessed at

the device pins. Table 3-8 "GPIO Options" on page

47 identifies these auxiliary functions, including

access to the UARTS and multi-function timers, as

well as certain power-management controls.

•Output Mapping:

— After passing through the optional input conditioning

circuits, any GPIO may be mapped (connected) to

one of eight PIC-level interrupts, or to one of eight

Power Management Event (PME) inputs. A given

GPIO may not be simultaneously mapped to both an

interrupt and a PME. The PIC interrupt inputs may be

configured to cause the generation of an ASMI-type

interrupt from any or all of the mapped GPIO signals.

•Power Domains:

— The GPIO circuits are distributed into the Working

and Standby power domains. Those circuits in the

Standby power domain may be used for system

wakeup events, since they remain powered when the

Working power is removed. As indicated in Table 3-8

"GPIO Options" on page 47, GPIO[28:24] are located

in the Standby power domain; all others are in the

Working power domain. Event/Filter pairs 6 and 7 are

located in the Standby domain; pairs [5:0] are in the

Working power domain.

•Auto-sense:

—GPIO5 and GPIO6 have a feature called Auto-sense.

When reset is applied to the system, a weak internal

pull-up is applied to the pad. When reset is de-

asserted, the Auto-sense value is used to establish

the pull-up/down state on the de-assertion edge. If

nothing pulls down the pad, then the weak pull-up

continues to be applied. If the pad is pulled down,

then pull-up is set to “no” and pull-down is set to

“yes”. The output driver does not actively drive the

pad, that is, it remains in TRI-STATE mode. If an

auto-sensed pull-down is desired, a diode between

the reset signal and the GPIO pin pulls it down during

the Auto-sense operation but has no effect during

normal operation.

•Recommended Functions:

— System designers at AMD have created a list of

recommended uses for selected GPIOs, see Table 3-

8 "GPIO Options" on page 47. The desired functions

were matched up with GPIOs by selecting appro-

priate buffer types and multiplexing options to create

an optimal list of recommended uses for the GPIOs.

Designers may use these recommended functions as

a starting point and make modifications to the list as

needed to fit the particulars of their system.

AMD Geode™ CS5536 Companion Device Data Book 157

General Purpose Input/Output 33238G

5.15.1 Programming for Recommended Functions

Table 3-8 "GPIO Options" on page 47 includes an “Recommended Use” column. Shown below are the register settings to

achieve the example.

Example Use Getting Example Use Note

---------------------------------------------------------------------------------------

PCI_INTA_L INPUT_ENABLE = 1

Setup GPIO Interrupt Mapper

AC_BEEP OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

IDE_IRQ0 INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

DDC_SCL OUT_ENABLE = 1 Software write OUT_VALUE

DDC_SDA OUT_ENABLE = 1 Software write OUT_VALUE

MFGPT0 OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

MFGPT1 OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

PCI_INTB_L INPUT_ENABLE = 1

Setup GPIO Interrupt Mapper

UART1_TX OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

UART1_RX INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

THRM_ALRM_L INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

INPUT_INVERT = 1

SLP_CLK_L OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

GPIO IN INPUT_ENABLE = 1 Software read READ_BACK

SMB_CLK INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

OUT_AUX1_SELECT = 1

SMB_DATA INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

OUT_AUX1_SELECT = 1

LPC_AD0 Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_AD1 Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_AD2 Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_AD3 Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_DRQ_L Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_SERIRQ Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

LPC_FRAME_L Hardware default Table 3-6 "DIVIL_BALL_OPT (DIVIL MSR 51400015h)" on page 34

WORK_AUX OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

LOW_BAT_L INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

PME# INPUT_ENABLE = 1

Setup GPIO PME Mapper

MFGPT7 OUT_ENABLE = 1

OUT_AUX1_SELECT = 1

PWR_BUT_L INPUT_ENABLE = 1

IN_AUX1_SELECT = 1

158 AMD Geode™ CS5536 Companion Device Data Book

General Purpose Input/Output

33238G

5.15.2 Register Strategy

The register set for the GPIO subsystem has been

arranged in such a way as to eliminate the need for read-

modify-write operations. Individual GPIO control bits may

be directly and immediately altered without requiring

knowledge of any other GPIO states or bit settings. Previ-

ous systems required the current settings for all GPIOs to

be read, selected pins changed, and the result written

back. If this read-modify-write operation was interrupted by

another process that also used the GPIOs, then erroneous

operation could result.

To avoid the read-modify-write operation, two data bits are

used to control each GPIO feature bit, wherein a feature is

enabled or disabled. One register bit is used to establish a

logic 1, while a second register bit is used to establish a

logic 0. A 1 in a register bit changes the feature bit’s value,

while a 0 does nothing. Since there are two register bits for

each GPIO feature bit, there are four combinations of regis-

ter bits possible. The two control bits operate in an exclu-

sive-OR pattern, as illustrated in Table 5-30.

An example 16-bit register controlling a feature bit for eight

GPIOs is illustrated in Table 5-31. Note that the real regis-

ters are 32 bits; 16 bits are used here as an illustrative

example.

Assume that the register in Table 5-31 allows setting and

clearing of an unspecified “feature bit” for GPIO[7:0].

Assume that the 16-bit value given in the example has just

been written into the register. In this example, all four possi-

ble bit combinations fromTable 5-30 are examined.

GPIO5 has a 0 in the logic 0 bit position (register bit 13),

and a 1 in the logic 1 bit position (register bit 5), so the

GPIO5 feature bit would become a 1.

GPIO4 has a 1 in the logic 0 bit position (register bit 12),

and a 0 in the logic 1 bit position (register bit 4), so the

GPIO4 feature bit would become a 0.

GPIO7 has a 1 in both bit positions (register bits 15 and 7).

Writing a 1 to both the logic 1 and logic 0 bit positions

causes no change to the GPIO7 feature bit.

GPIO6 has a 0 in both bit positions (register bits 14 and 6).

Writing a 0 to both the logic 1 and logic 0 bit positions

causes no change to the GPIO6 control bit. GPIO[3:0], also

have 0s in both bit positions, so they experience no

change.

Reads produce a normal and an inverted value. For exam-

ple, assume the Output Enable is set only for GPIO4 in the

above register. A read would return the value EF10h.

Actual GPIO registers associated with feature bit settings

are 32 bits wide and each handle 16 GPIOs. They are

organized into low and high banks. The low bank deals with

GPIO[15:0], while the high bank deals with GPIO[28:24]

and GPIO[22:16].

In addition to these “bit registers”, there are value registers

for the Input Conditioning Functions.

5.15.3 Lock Bits

Many GPIO registers are protected against accidental

changes by Lock Enable registers that prevent further

changes. Once a LOCK bit is set, the associated register

can not be changed until the corresponding LOCK bit is

cleared. There are two Lock Bit registers, one for the high

bank (GPIOH_LOCK_EN, GPIO I/O Offset BCh) and one

for the low bank (GPIOH_LOCK_EN, GPIO I/O Offset

3Ch). All GPIO registers are protected by LOCK bits except

the High and Low Bank Read Back registers,

(GPIO[x]_READ_BACK), High and Low Bank Positive

Edge Status registers (GPIO[x]POSEDGE_STS), the High

Low Bank Negative Edge Status registers

(GPIO[x]NEGEDGE_STS), and of course the Lock Enable

registers themselves.

Table 5-30. Effect on Feature Bit

Logic 0

Bit

Position

Logic 1 Bit

Position Effect on Feature Bit

0 0 No change

1 0 Feature bit is cleared to 0

0 1 Feature bit is set to 1

1 1 No change

Table 5-31. 16-Bit GPIO Control Register Example

Bit No.

“1” Sets Control Bit to 0 “1” Sets Control Bit to 1

1514131211109876543210

Value 1001000010100000

GPIO # 7654321076543210

AMD Geode™ CS5536 Companion Device Data Book 159

General Purpose Input/Output 33238G

5.15.4 GPIO Basic I/O Configuration

The General Purpose Input and Output (GPIO) Interface is

illustrated in Figure 5-48. The figure represents one of

twenty-eight GPIOs potentially available. Note the GPIOs

[31:29] and [23] are non-existent. Table 3-8 "GPIO Options"

on page 47 provides a complete list of features for each

GPIO and should be consulted when configuring a system.

Each GPIO has basic configuration options used to set up

the characteristics of the GPIO for either input or output.

Each of the functions in the list below follows the GPIO reg-

ister strategy outlined inSection 5.15.2 "Register Strategy"

on page 158 unless otherwise noted. This strategy allows

individual GPIOs to be modified without accidentally

changing the characteristics of unrelated GPIOs, and with-

out requiring ‘read-modify-write’ cycles. All values are

active high.

•OUT_EN. When high, enables this GPIO/OUT_AUX for

output. A pad may be configured for output, input, or

both.

•IN_EN. Enables this GPIO/IN_AUX for input. A pad may

be configured for input, output, or both.

•OUT_VAL. This will establish the value driven to the pad

when it is selected as an Output, unless either

OUT_AUX1 or OUT_AUX2 are selected. The value

driven to the GPIO pad is subject to an optional inver-

sion.

•OUT_INVRT_EN. When high, inverts the

GPIO/OUT_AUX Output Value.

•IN_INVRT_EN. Inverts the signal applied to the ball, and

presents the inverted value to all follow-up circuitry (i.e.,

input conditioning functions). Affects both GPIO and

IN_AUX.

•OUT_OD_EN. Configures this GPIO/OUT_AUX for

open-drain operation. When the output pad is to be

driven low, the pad is driven low. When the output pad is

to be driven high, the pad is allowed to float and is not

driven.

•OUT_AUX1_SEL and OUT_AUX2_SEL. Selects an

internal auxiliary source for the Output Value. Table 3-8

"GPIO Options" on page 47 identifies all the possible

internal connections for these two auxiliary sources.

•IN_AUX1_SEL. Selects an internal destination other

than the GPIO for the ball. Table 3-8 "GPIO Options" on

page 47 lists all the functions that may be connected in

this manner.

•Selecting both IN_AUX1 and OUT_AUX1 is only

supported for GPIO14 and GPIO15. For all other GPIOs,

this setting may result in undefined behavior.

•PU_EN. Applies a weak pull-up to the pad. The effect of

this control is independent of all other settings except

PD_EN. If PU_EN is set by software, PD_EN is auto-

matically cleared. Affects both GPIO and IN_AUX.

•PD_EN. Applies a weak pull-down to the pad. The effect

of this control is independent of all other settings except

PU_EN. If PD_EN is set by software, PU_EN is auto-

matically cleared. Affects both GPIO and IN_AUX.

Figure 5-48. GPIO Configuration

Event

Ball

Open-Drain

Pull-Up

Enable

Event Counter

AUX1

AUX2

Output

Value

AUX1 Counter

Read

Back

Enable

Count Compare

Filter

Enable

Filter

Filter Amount

AUX Select

Invert Enable

Output Enable

GPIO_INTS [7:0]

GPIO_PME [7:0]

Invert Enable

Input Enable

Pull-Down

Enable

1+ Edge Detect

- Edge Detect

Edge

Detects

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5.15.5 Input Conditioning Functions

GPIOs in the CS5536 companion device may have their

inputs conditioned by configurable circuitry as illustrated in

Figure 5-48 on page 159. Any GPIO may be connected to

one of eight Input Conditioning functions, each consisting

of a Digital Filter and an Event Counter (known as an

Event/Filter pair). Each GPIO is followed by an edge detec-

tion function that may be set for either positive or negative

going edges. As shown in Figure 5-48, the edge detection

function may be used to monitor the output of the Event/Fil-

ter pair that has been associated with that particular GPIO,

or it may be used independently of the Event /Filter pair.

These functions are enabled as follows:

•IN_FLTR_EN. Enables the input filter function of the

associated GPIO.

•EVNTCNT_EN. Enables the event counter function of

the associated GPIO.

•IN_POSEDGE_EN and IN_NEGEDGE_EN. Enables

the edge detection function and mode.

The final input value may be read back by a software

accessible register (GPIO[x]_READ_BACK). It may also be

used as an Interrupt or a Power Management Event.

There are a total of eight Digital Filter/Event Counter pairs

that are shared by 28 GPIOs. There is a selection function

to associate a given Filter/Counter pair with a given GPIO.

All GPIOs incorporate edge detection.

5.15.5.1 Input Filter Conditioning Function

The digital filter is one-half of a Filter/Event conditioning cir-

cuit. (The other half is the Event Counter.) The filter is used

to produce a stable output from an unstable input. Mechan-

ical switch de-bounce is a typical use.

To use one of the eight digital filters, it must first be

assigned to one of the GPIO inputs using one of the

GPIO_FE[x]_SEL registers (GPIO I/O Offsets F0h-F7h);

where “x” is the number of the Filter/Event pair, 0 to 7.

Then the filter function must be enabled through either the

GPIOL_IN_FLTR_EN (GPIO I/O Offset 28h) or the

GPIOH_IN_FLTR_EN (GPIO I/O Offset A8h) registers,

depending on whether the selected GPIO is in the high

[28:16] or low [15:0] bank. Finally, a GPIO_FLTR[x]_AMNT

(GPIO I/O Offsets 50h, 58h, 60h, 68h, 70h, 78h, D0h, and

D8h) must be determined and then programmed to estab-

lish the filter’s stability period.

The associated GPIO input must ultimately remain stable

for a FLTR_AMNT number of 32 KHz clock edges in order

for the output to change. A FLTR_AMNT of 0 effectively dis-

ables the filtering function, because the counter will not roll

over from 0 to all 1s. The maximum FLTR_AMNT is FFFFh.

The digital filter is based on a 16-bit programmable down-

counter. An initial count is loaded into the counter via the

GPIO_FLTR[x]_AMNT register. When the associated GPIO

input changes, the counter begins counting down from

FLTR[x]_AMNT towards 0. If the associated GPIO input

remains stable for the length of the count-down period,

then the counter reaches 0 and produces an output pulse

to whatever the GPIO is internally connected to. If the

associated GPIO input changes during the count-down

period, then the counter reloads the initial count from the

GPIO_FLTR[x]_AMNT register and begins counting down

towards 0 again.

Direct access to the counter’s state is provided by the R/W

time to determine the current value of the counter. The

GPIO_FLTR[x]_CNT register may also be written to at any

time, thereby jamming the counter state forward or back-

ward from the current count.

Reads and writes of the GPIO_FLTR[x]_CNT register are

internally synchronized to avoid false read values and cor-

rupted writes, that is, reads and writes may occur to a filter

circuit without concern of the phasing or timing of the 32

KHz clock edges. When GPIO[x]_IN_FLTR_EN is low, the

filter circuit is not clocked.

The filter circuit is used to produce a stable output from an

unstable input. Mechanical switch de-bounce is a typical

use. The default value for all flip-flops, the Down Counter,

and the Filter Amount Register is zero. Software estab-

lishes the filter amount. As long as the preliminary input on

the left matches the filtered input on the right, the circuit is

stable and the counter continuously loads the filter amount

value. When the preliminary input changes, the counter

begins to count. If the input remains steady, then the

counter reaches zero and enables loading the value flip-

flop. This brings the circuit back to the stable point. If the

input does not remain steady, then the counter reloads.

The preliminary input on the left must remain steady for the

“filter amount” number of clock edges for the final input on

the right to change. A filter amount of zero effectively dis-

ables the filtering function because the Down Counter will

not roll over backwards to all ones. The maximum filter

amount is FFFFh

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5.15.5.2 Input Event Counter Conditioning Function

The event counter is one half of a filter/event conditioning

circuit, and is in series with its associated filter. (The other

half is the digital filter.) It counts events and can produce an

output when a predefined count is reached. The event

counter may be down-counted by writing to a particular

address. It may be used as a rate counter that may be peri-

odically read, and that produces no output at all.

To use one of the eight event counters, it must first be

assigned to one of the GPIO inputs using one of the

GPIO_FE[x]_SEL registers (GPIO I/O Offset F0h-F7h)

(where X is the number of the Filter/Event pair, 0 to 7).

Then the associated digital filter must be enabled, through

either the GPIOL_IN_FLTR_EN or GPIOH_IN_FLTR_EN

registers (I/O Offset 28h and A8h), depending on whether

the selected GPIO is in the high [28:16] or low [15:0] bank.

If digital filtering is not required, program the associated

GPIO_FLTR[x]_AMNT registers to 0000h. Finally, the

desired “compare value” (GPIO_EVNTCNT[x]

_COMPARE) must be determined and then programmed to

establish the number of events that will produce an output

when that count has been reached.

The event counter is based on a 16-bit programmable

up/down counter. The up-down counter counts positive

edges of the selected GPIO input and produces a constant

or level output when the GPIO_EVNTCNT[x] (counter

value) exceeds the GPIO_EVNTCNT[x]_COMPARE (com-

pare value). The output can be read as the GPIO and/or

used to drive an auxiliary input.

The counter may be counted down one count by writing to

one of two addresses, depending on which bank (High or

Low) the associated GPIO resides in. Knowledge of which

GPIO is associated with the event counter is required,

since these two decrementer registers have a dedicated bit

for each GPIO. When counted down, this counter, unlike

the counter in the digital filter, rolls over from 0000h to

FFFFh. Typically, decrementing is used to clear an interrupt

or power management event as part of the associated ser-

vice routine.

5.15.5.3 Uses of the Event Counter

Such an auxiliary input could be used to drive an ASMI or

maskable interrupt. Assume the compare value is set to 0.

The service routine clears the ASMI by decrementing the

counter via the mechanism illustrated. If additional events

have occurred, the count does not decrement to 0 and the

ASMI remains asserted. The count up and down inputs are

synchronized such that false values are not created if up

and down pulses occur at or near the same instant in time.

The counter will not decrement through 0.

Alternatively, the compare value could be set to a higher

value to trigger an ASMI or interrupt when a certain num-

ber of events has occurred. In this case, the ASMI or inter-

rupt is cleared by writing the counter to 0.

Lastly, the input value may be ignored and the event

counter used as a rate indicator. If software reads the

counter at a fixed periodic interval, an input pulse rate may

be measured. Such an approach may be used to imple-

ment a tachometer function. The counter will increment

past all Fs back to 0.

As suggested above, the counter may be read or written

under software control. The read and write operations are

synchronized such that false values are not created if count

up pulses occur at or near the same instant in time.

5.15.5.4 Input Edge Conditioning Function

The Edge Detection function is illustrated as part of Figure

5-48 on page 159. It is normally used to generate an ASMI

or maskable interrupt on each positive and/or negative

edge of an input signal. Use of this function simultaneously

with the event counter function is somewhat logically mutu-

ally exclusive, but is not prevented in hardware.

Each GPIO has the optional edge detection function.

The reset default for the detection circuit establishes a 0

level on GPIO[x]_POSEDGE_EN and

GPIO[x]_NEGEDGE_EN (GPIO I/O Offset C0h and C4h).

When both are set to 0, the edge detection function is dis-

abled. If either a positive or negative edge detection is

enabled, an active high output is produced when the appro-

priate edge occurs. This level must be cleared by writing to

either the GPIO[x]_POSEDGE_STS or the

GPIO[x]NEGEDGE_STS registers (GPIO I/O Offset C8h

and CCh), whichever is appropriate. If another edge occurs

before clearing, the active high output is not affected. If the

clear action occurs at the “same time” as another edge, the

result is not defined.

Each edge detection function is controlled by four registers

as follows:

•Positive Edge Enable (GPIO[x]_POSEDGE_EN).

Enabled if feature bit is high.

•Negative Edge Enable (GPIO[x]_NEGEDGE_EN).

Enabled if feature bit is high.

•Positive Edge Status (GPIO[x]_POSEDGE_STS). Set

indicates edge. Write 1 to clear.

•Negative Edge Status (GPIO[x]_POSEDGE_STS). Set

indicates edge. Write 1 to clear.

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5.15.5.5 Output Steering (Mapping)

Outputs from the internal GPIO circuits, driven by inputs to

the CS5536 companion device from the system, may be

steered (or ‘mapped’) to either interrupts, or power man-

agement events (PME). Sufficient steering logic exists in

the CS5536 companion device to provide for eight inde-

pendent interrupts and simultaneously for eight indepen-

dent PMEs.

The eight GPIO interrupts are all in the Working power

domain; of the eight PMEs, [7:6] are in Standby power

domain and [5:0] are in Working domain. Those in the

Standby power domain are intended to be used to awaken

the system when the Working power domain is off, how-

ever, they may also be used when the Working power

domain is on. The interrupts are connected to the PIC, and

the PMEs are connected to the PMC.

Four 32-bit steering registers control the routing of the

GPIOs’ internal output (that produced by an input to the

chip from an external source, or from one of the internally-

connected AUX inputs) to either an interrupt or PME. The

set of four registers taken together, contain a nibble for

each GPIO. The upper bit of each nibble selects either a

PME (if high) or an interrupt (if low). The remaining three

bits of each nibble select which of the eight possible inter-

rupts or PMEs the GPIO will be steered to.

The four registers are identified as GPIO Mapper X, Y, Z,

and W. Their GPIO associations are as follows:

•GPIO_MAP_X = GPIO[7:0]

•GPIO_MAP_Y = GPIO[15:8]

•GPIO_MAP_Z = GPIO[23:16]

•GPIO_MAP_W = GPIO[31:24]

The steering logic does not prohibit mapping of two or

more GPIOs to the same output, but it is impossible to cre-

ate a single GPIO that functions simultaneously as both an

interrupt and a PME. Registers X, Y, Z, and W default to all

0s, as do both the High and Low EVNT_EN registers.

Thus, all GPIOs are mapped to INT[0] after a reset, but

none are enabled.

5.15.5.6 Auto-sense

Two GPIOs (GPIO5 and GPIO6) have a function called

“Auto-sense”. Auto-sense is a method of automatically

determining whether or not to apply a pull-up or pull-down

to the corresponding GPIO input.

Auto-sensed inputs behave as follows. When reset is

applied to the system, a weak pull-up is applied to the pad.

When reset is de-asserted, the sensed value is used to

establish the pull-up/down state on the de-assertion edge.

If nothing pulls down the pad, then the pull-up continues to

be applied. If the pad is pulled down, then the pull-up is

cleared to 0 and the pull-down is set to 1. If a pull-down is

desired, a diode between the reset signal and the GPIO pin

will pull it down during the Auto-sense operation but have

no effect during normal operation.

Disabling the auto-sensed pull-up or pull-down requires

more program operation than just disabling the pull-up or

pull-down through the GPIOL_PU_EN or GPIOL_PD_EN.

If the pull-up was enabled through auto-sense, the proce-

dure to disable is:

1) Enable the pull-down in GPIOL_PD_EN.

2) Disable the pull-down in GPIOL_PD_EN.

If the pull-down was enabled through auto-sense, the pro-

cedure to disable is:

1) Enable the pull-up in GPIOL_PU_EN.

2) Disable the pull-up in GPIOL_PU_EN.

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5.16 Multi-Function General Purpose Timer

The Multi-Function General Purpose Timer contains eight

multi-function general purpose timers (MFGPTs). Six of the

eight MFGPTs are in the Working power domain running

off a 32 KHz clock or a 14.318 MHz clock, while the other

two are in the Standby power domain running off a 32 KHz

clock.

The Working power domain contains the following blocks:

•Six MFGPTs each split into three blocks, one containing

I/O registers, one containing the clock switch, and one

containing the timer logic.

•15-bit prescaler to divide down the 14.318 MHz clock

and generate 15 carry-out signals.

•15-bit prescaler to divide down the 32 KHz clock and

generate 15 carry-out signals.

•Logic to implement Local Bus Interface, Control Logic,

MSR Registers, and NMI, IRQ, and Reset Output

Events.

•Two blocks containing I/O registers to write into the two

MFGPTs in the Standby power domain.

The Standby power domain contains the following blocks:

•Two MFG PTs.

•15-bit prescaler to divide down the 32 KHz clock and

generate 15 carry-out signals.

•Interface for signals going between Standby and

Working power domains.

Figure 5-49 shows the top level block diagram of the Multi-

Function General Purpose Timer.

Features

Each MFGPT operates independently and can have the

following features:

•32 KHz or 14.318 MHz clock selectable by software

(MFGPT0 to MFGPT5 only; MFGPT6 and MFGPT7 use

32 KHz clock).

•Programmable input clock prescaler divisor to divide

input clock by 2i, where i = 0 to 15.

•Watchdog timer (trigger GPIO output, interrupt, or

reset).

•Pulse Width Modulation (PWM).

•Pulse Density Modulation (PDM).

•Blink (low frequency pulse for LED).

•General Purpose Timer.

•Generate GPIO outputs.

•Provide outputs for generating reset (limited to MFGPT0

to MFGPT5), IRQs, NMI, and ASMI (indirectly through

PIC).

Figure 5-49. MFGPT Top Level Block Diagram

Working Domain

Control and MSR Registers

MFGPT0

MFGPT6

Bus Interface

Reset and Interrupt Generation

Power Domain Crossing I/F

Standby Domain

14.318 MHz

32 KHz

Prescaler

32 KHz

Prescaler

I/O Reg Clock

Switch Timer

MFGPT1

I/O Reg Clock

Switch Timer

MFGPT2

I/O Reg Clock

Switch Timer

MFGPT3

I/O Reg Clock

Switch Timer

MFGPT4

I/O Reg Clock

Switch Timer

MFGPT5

I/O Reg Clock

Switch Timer

I/O Reg I/F MFGPT7

I/O Reg I/F

MFGPT6

Timer MFGPT7

Timer

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5.16.1 Prescaler

The 15-bit prescaler is a binary down counter, dividing

down the incoming clock, and provides 15 outputs for the

MFGPTs. The frequency of these outputs ranges from 2-1

to 2-15 of the input frequency and each pulse is one incom-

ing clock high, so these outputs function as increment

enables for the MFGPTs. The prescaler resets to 000016

and starts decrementing after reset. The prescaler output

vector, psclr_out[14:0], is based on prescaler counter

psclr_cnt[14:0], where psclr_out[i] = &(~psclr_cnt[i:0]) (i.e.,

prescaler output bit i is asserted if the prescaler counter

from bit i down to bit 0 are all low). When the prescaler

reaches 000016, all prescaler outputs are asserted at that

time.

The external clock for the prescaler is activated if there is

one or more MFGPTs activated using it as the clock

source. It is also activated for MFGPT I/O register writes

and synchronous counter reads (only for 14.318 MHz)

when the MFGPT being written has already selected the

14.318 MHz clock as its clock source. Whenever the exter-

nal clock is activated, the prescaler counts. Therefore, mul-

tiple MFGPTs and register access can affect the prescaler

counting. From the point of view of the MFGPT, once the

MFGPT is disabled and then re-enabled, it cannot be

determined exactly when the prescaler carry-out occurs as

it does not know how long the prescaler has been stopped,

if at all.

5.16.2 I/O Register Block

The I/O register write data is first stored in I/O register sub-

modules before being transferred over to the MFGPTs.

There are two types of I/O register submodules, one for the

Working power domain and one for the Standby power

domain. The main difference is that for the Working power

domain, except for the counter register, the register values

here and the register values in the timer are the same. For

the Standby power domain, the register values in the I/O

write, as this logic could have been powered down in

Standby mode and the register data is therefore invalid. For

the Standby power domain, the read always comes from

the timer directly.

5.16.2.1 MFGPT Register Set

There are four software accessible I/O registers per

MFGPT: Up Counter, Comparator 1 Value, Comparator 2

Value, and Setup registers. (See Section 6.17 "Multi-Func-

tion General Purpose Timer Register Descriptions" on

page 513 for register details.) Writes to these registers are

first stored here and then transferred to a separate copy of

the register in the timer. For MFGPT0 to MFGPT5, reads of

these registers, except for the counter, comes from the reg-

isters here, while reads of the counter register comes from

the timer. For MFGPT6 and MFGPT7, reads of these regis-

ters comes from the copy inside the timer.

5.16.2.2 Setup Register

The Setup Register contains the following control fields that

control the MFGPT operation:

• Counter Enable. Enables the Up Counter to count (it

does not enable/disable other MFGPT functions).

• Clock Select. Instructs the clock switch logic to use the

32 KHz clock as the MFGPT clock if low or the 14.318

MHz clock if high, once this register has been written

(only for MFGPT0 to MFGPT5).

• Scale Factor. Selects the prescaler divide scale factor

for the Up Counter to increment.

•Stop Enable. Enables the Up Counter to stop counting

during a system power management Sleep mode (for

MFGPT0 to MFGPT5) or Standby mode (for MFGPT6

and MFGPT7).

• External Enable. Enables the Up Counter to be cleared

and restarted rather than performing the next increment

each time there is a low to high transition detected on

the GPIO input associated with the timer. An asynchro-

nous edge-detector catches the transition; the signal is

then synchronized and sent to clear the counter

synchronously. Therefore, the clear does not occur

immediately on the transition.

• Reverse Enable. Flips the order of the Up Counter

outputs going to the Compare 1 circuit so that bit 0

becomes bit 15, bit 1 becomes bit 14, etc. This allows

the timer logic to generate a PDM signal instead of a

PWM signal. To properly generate a PDM signal, the

Compare 2 Value should be set to FFFF16 to allow the

Compare 1 Value to establish the density.

• Compare 1 Mode. Controls the Compare 1 output.

There are four cases:

00: Disabled. Output is low.

01: Compare on Equal. The compare output goes high

when the Up Counter value, after going through Bit

Reverse logic, is the same value as the Compare 1

Value.

10: Compare on GE. The compare output goes high

when the Up Counter value, after going through Bit

Reverse logic, is greater than or equal to the Compare

1 Value.

11: Event. Same as “Compare on GE”, but an event is

also created. This event can be read and cleared via

the MFGPT Setup Register and is used to generate

interrupt and reset.

• Compare 2 Mode. Same as Compare 1 Mode, except

this controls the Compare 2 output. The Up Counter is

directly compared against the Compare 2 Value (i.e.,

without going through Bit Reverse logic).

All of the above fields, except Count Enable, are write once

only.

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Compare Status/Event Bits

The Setup register also contains two status bits: one from

Compare 1 and one from Compare 2. If Event mode is

selected, then these two status bits represent the events

from the two Compare circuits, and writing a 1 to one of the

bits clears that particular event. If Event mode is not

selected, then the status bits read back the compare out-

puts, and writing to those bits has no effect. Note that since

this logic is in the Working power domain, MFGPT6 and

MFGPT7 loses these events when VCORE is powered off.

In order for events to be captured again, the chip must have

VCORE powered up out of Standby mode and then come

out of reset.

The Compare 1 and Compare 2 outputs may change

simultaneously on the same MFGPT clock edge. However,

when checking the outputs through the two status bits after

this occurred, on rare occasions, the read may find only

one of the two outputs changed to the new value. This

could occur when the two outputs change at about the

same time they are synchronized by separate synchroniz-

ers to the local bus clock domain, and one synchronizer

captured the new value in time, while the other one does

not. A subsequent read can show that both outputs did

change states.

5.16.2.3 Register Initialization Sequence for Event

Mode

If the Setup register is written before the other three I/O

registers, and if Event mode is selected for Compare 1

mode or Compare 2 mode, then events are triggered

immediately. This is because the compare outputs look for

a Compare register value greater than or equal to the

counter, and the result will be true as those registers are all

0. To avoid triggering these events on Setup register initial-

ization, first initialize the Compare 1 Value and Compare 2

Value registers before initializing the Setup register.

5.16.2.4 Register Data Transfer to/from MFGPT

Only WORD writes and DWORD writes are accepted for

I/O register accesses; BYTE writes to I/O registers are

ignored. The DWORD write causes the two I/O registers

located within the DWORD boundaries to be written in par-

allel. If Up Counter, Compare 1 Value, or Compare 2 Value

registers are written while the MFGPT is running, it could

cause the compare outputs to change in the middle of a

prescaler period (i.e., not at a clock cycle where the pres-

caler signals a counter increment). For MFGPT0 to

MFGPT5, the clock switch circuitry disables all clocks to

the MFGPT until the Setup register has been written.

Therefore, even if the Up Counter, Compare 1 Value,

and/or Compare 2 Value registers are written before the

Setup register, these register values are transferred to the

timer at the same time as the Setup register values.

All reads and writes to MFGPT registers can be done by

software at any time, and are completed without requiring

any additional software operation, and without affecting the

proper operation of the MFGPT as long as a clock to the

MFGPT has been selected by writing to the Setup register.

On a write, the write transfer on the bus is considered com-

plete when the write to the register in the I/O register sub-

module is complete. This occurs before the register data is

transferred to the timer. However, a subsequent read or

write to the same register will be held up until that first write

transfer to the timer is complete.

The Setup register, except for bits 13 and 14, are handled

in the same way as the Compare 1 Value and Compare 2

Value registers. Bits 13 and 14 write and read were dis-

cussed earlier, where the entire logic is in the Working

power domain.

5.16.2.5 Register Re-initialization

If it is necessary to re-initialize the Up Counter, Compare 1

Value, or Compare 2 Value, the following sequence should

be followed to prevent any spurious reset, interrupt, or out-

put pulses from being created:

1) Clear Counter Enable bit to 0.

2) Clear Interrupt Enable, NMI Enable, and Reset Enable

bits in MSRs; disable GPIO inputs and outputs.

3) Update Up Counter, Compare 1 Value, and Compare

2 Value registers as desired.

4) When updates are completed, clear any event bits that

are set.

5) Set up Interrupt Enable, NMI Enable, and Reset

Enable bits in MSRs; enable desired GPIO inputs and

outputs.

6) Set Counter Enable bit to 1.

5.16.3 Clock Switch

The clock switch output is disabled at reset and selection

can only be done one time after reset, at the first write to

the Setup register.

Restriction on Register Read/Write Sequence Due to

Clock Switch

Note that because the timer clock is stopped until the first

write to the Setup register, a write to one of the other three

I/O registers during this time could not complete its transfer

to the timer. As a result, a second access, read or write, to

the same register causes the bus interface to hang, as the

second access waits for the first access (the initial write) to

complete before completing its own operation. But since

the first access cannot complete without a clock, the sec-

ond access is in limbo. This means no more accesses can

occur, so there is no way to write to the Setup register to

enable the timer clock. Care should be taken to see that

this situation does not occur.

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5.16.4 Single MFGPT

Figure 5-50 shows the functionality of one of these timers. There are two types of timers, one for the Working power domain

and one for the Standby power domain.

Figure 5-50. MFGPT Block Diagram

Standby State/

32 KHz/14 MHz

Count_Enable

External Enable

GPIO GPIO Input Value

Little Endian

Big Endian

Bit Reverse

Compare 1

Compare 1 Value

Compare 2

Compare 2 Value

Clear

Clear & Re-start

Reverse Enable

Compare 1 Output

Compare 1 Mode

Compare 2 Mode

Sleep State

Compare 2 Output

16 Bit Sync

Up Counter

Stop Enable

Count

14 MHz/32 KHz Prescaler_Carry_Outs

Compare 1 Event

Compare 2 Event

VCORE

Scale Factor

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5.16.4.1 Clock Selection and Counter Increment

The MFGPT can use either the 32 KHz clock or 14.318

MHz clock as the clock source (MFGPT6 and MFGPT7 in

Standby power domain are limited to the 32 KHz clock).

When the Counter Enable bit is high, the MFGPT is acti-

vated and capable of counting. An actual increment is per-

formed when the selected prescaler divide-by signals the

increment; this is done through the Scale Factor selecting

one of 16 signals. Table 5-32 shows how the Scale Factor

effectively divides down the incoming clock.

5.16.4.2 Compare 1 and Compare 2 Outputs

When the Up Counter reaches the Compare 1 Value, the

Compare 1 Output is asserted. When the Compare 2 Value

is reached, the Compare 2 Output is asserted, and the Up

Counter then synchronously clears and restarts. The

MFGPT outputs coming from Compare 1 and Compare 2

are all glitch-free outputs.

The compare outputs and events may change in the middle

of a prescaler period if new values are written to the Up

Counter, Compare 1 Value, or Compare 2 Value registers.

These compare outputs can be used to trigger their

respective events and drive GPIO outputs. The events are

used to trigger interrupts, NMI, and reset.

5.16.4.3 GPIO Input

The Up Counter could also be software selected to have a

GPIO input positive edge as another source for the counter

to clear and restart. The GPIO input signal is asynchronous

to the timer and the timer uses a flip-flop to capture the

GPIO rising edge. It takes up to one prescaler clock period

plus two MFGPT clock periods from the GPIO rising edge

for the clear to take effect. Once the counter is cleared, this

edge detect circuit can then accept a new GPIO edge.

Each individual pulse can be as short as a few nanosec-

onds wide for the rising edge to be captured. If this feature

is not selected or the counter is disabled, the clear counter

output and the edge detector are kept de-asserted.

5.16.4.4 Bit Reverse and Pulse Density Modulation

Figure 5-51 shows how the Little Endian/Big Endian Bit

Reverse functions.

Table 5-33 on page 168 shows a 3-bit example of pulse

density modulation; note that the MFGPT has a 16-bit

implementation. If the desired pulse train is of the opposite

polarity, this can be inverted in the GPIO or generated with

a different Compare 1 value.

Figure 5-51. MFGPT Bit Reverse Logic

Table 5-32. MFGPT Prescaler Clock Divider

Scale Factor Input Clock Divide-By

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1010 1024

1011 2048

1100 4096

1101 8192

1110 16384

1111 32768

123456789101112131415 0

Input Word from Up Counter

Output Word to Compare Circuit

168 AMD Geode™ CS5536 Companion Device Data Book

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5.16.5 Working Power Domain Logic

The Working power domain logic consists of the Local Bus

Interface, Control Logic, MSRs, and NMI, IRQ, and Reset

Output Events.

When Event mode is enabled, the NMI, IRQ, and Reset

Output Events logic gathers the event outputs of all eight

MFGPTs and then generates the interrupt and resets out-

puts based on MSR settings. The interrupt outputs go to

the PIC that can then trigger an IRQ or ASMI. Note that

MFGPT6 and MFGPT7 cannot trigger reset. These outputs

are controlled by MSR bits, and the NMI output can be fur-

ther controlled by the MSB of I/O Address 070h.

5.16.6 Power Domain Crossing Interface Logic

The asynchronous internal Standby State signal dis-

ables/enables the Working power domain interface immedi-

ately. Therefore, any bus operation active at that time has

an indeterminate result.

Table 5-33. MFGPT Pulse Density Modulation Example

Up Counter Output Bit Reverse Output

Pulse Train Output for Given Compare 1 Value (Note 1)

12456

000 000 0 0 0 0 0

001 100 1 1 1 0 0

010 010 1 1 0 0 0

011 110 1 1 1 1 1

100 001 1 0 0 0 0

101 101 1 1 1 1 0

110 011 1 1 0 0 0

111 111 1 1 1 1 1

Note 1. Compare 2 Value must be set to all 1s for pulse density modulation.

AMD Geode™ CS5536 Companion Device Data Book 169

Power Management Control 33238G

5.17 Power Management Control

The Power Management Control (PMC) controls all

aspects of power management. Power management is

event driven, meaning that in general, any action that the

PMC performs is predicated on some event. These events

can come from other GeodeLink Devices, including the

CPU inside the AMD Geode LX processor for example, or

events coming from other off-chip sources.

The PMC is compatible with the industry standard power

management capabilities as defined in the Advanced Con-

figuration and Power Interface (ACPI) v2.0 specification. An

operating system that conforms to ACPI can take advan-

tage of the CS5536 companion device ACPI support hard-

ware.

Advanced Power Management (APM) is another power

management approach that the PMC supports. APM is a

subset of ACPI and therefore is not directly discussed.

Components in a GeodeLink architecture based system

have hardware and software means of performing power

management, which the PMC controls. A high performance

computing system consumes multiple watts of power when

fully on. However, with GeodeLink architecture, system

power consumption is significantly lower on average

through the use of power states that reduce power needs

when the system is idle.

5.17.1 Power Domains

The PMC consists of three blocks: Working, Standby and

RTC.

•The Working block contains all circuits and functions

associated with the Working power domain. It includes

the Working state machine, Local bus interface, ACPI

power management registers, and power management

supporting logic (i.e., counters, timer, CCU, etc.). The

main function of the Working block is to put the system

into Sleep, that is, turn off clocks to the system and

disable I/Os to reduce power consumption.

•The Standby block contains all circuits and functions

associated with the Standby power domain. It includes

the Standby state machine, ACPI registers, and power

management supporting logic (i.e., counters, reset,

CCU, etc.). The function of the Standby logic is to

control power to the Working power domain. The PMC

disables all interfaces between the Standby and Working

domains while the Working power is off.

•The RTC block contains the timing circuits for keeping

real time. These circuits are powered by VBAT (ball A3).

It is not a device requirement that the RTC block be

powered during Mechanical Off. If a system design does

not require that real time be kept, then VBAT should be

tied to ground.

5.17.2 Power States

Table 5-34 shows the supported ACPI power states and

how they relate to the AMD Geode LX/CS55336 system.

ACPI power states not described are not supported.

Table 5-34. Supported ACPI Power Management States

ACPI States Hardware States

Global System

State Sleep State C State

AMD Geode™

LX Processor

State

System

Main

Memory

AMD Geode™ CS5536

Companion Device

Working

Logic

Standby

Logic

G0: Working S0 C0 FO FO FO On

AHCG AHCG AHCG

C1 Suspend on

Halt

AHCG AHCG

G1: Idle S1: Sleeping C2 Sleep Auto-refresh Sleep On (Sleep)

S3: Save-to-RAM Off Off Auto-refresh Off Standby

S4: Save-to-Disk Off Off Off Off

G2: Soft Off S5 Off Off Off Off Standby

G3: Mechanical Off Off Off Off Off Off Off

170 AMD Geode™ CS5536 Companion Device Data Book

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5.17.2.1 ACPI System Power States

•G0/S0: Not Sleeping. Software is executing code or

could be halted waiting for a system event.

•G1/S1: Requires explicit software action to enter this

state. All AMD Geode LX processor, CS5536

companion device, and main memory states maintained.

All system clocks may be turned off except 32 KHz or

selected additional clocks may be left on as required.

The PMC provides generic controls, SLEEP_X and

SLEEP_Y, that may be used to control the “D” states of

external system devices (not described in this data

book, see ACPI specification for details). Two additional

internal signals control PCI and IDE input and outputs. A

wakeup event brings the system back to the opcode

following the one that initiated entry into S1. Context

restore operation is not required on the AMD Geode LX

processor, CS5536 companion device, or main memory.

•G1/S3: Save-to-RAM state. Requires explicit software

action to enter this state. The CS5536 companion

device and other system context are lost. System state

is saved in the main memory. To properly support this

state, main memory power must be controlled by

WORKING power while the AMD Geode LX processor,

CS5536 companion device, and all other system compo-

nents power must be controlled by WORK_AUX power.

Note that this applies only to the Working domain of the

CS5536 companion device. The Standby domain must

be continuously supplied from Standby power.

•G1/S4: Suspend-to-Disk state. Requires explicit soft-

ware action to enter this state. Same as S3 state, but the

system state is “saved” on the hard drive or other mass

storage device. Only Standby power is on while in this

state.

•G2/S5: Requires explicit software action to enter this

state. All system context is lost and not saved. Operating

system re-boot is required. The 32 KHz clock is kept

running for Standby PMC and selected GPIO and

MFGPT circuits.

•G3: Software action is not required to enter this state.

Working power and Standby power are removed. The

only domain that may be powered is the RTC. It is not a

requirement that the RTC be powered.

5.17.2.2 CPU Power States

• G0/S0/C0: Processor actively executing instructions and

clock running. Cache snoops supported.

• G0/S0/C1: HLT instruction executed. Usually occurs in

the Operating System’s idle loop. Operating System

waiting for Power Management Event (PME), interrupt,

or ASMI. Cache snoops are supported while in this

state, so bus mastering activity can safely occur.

• G1/S1/C2: Processor is in the lowest power state that

maintains context in a software invisible fashion. Entered

as part of the S1 sequence. The SUSP#/SUSPA#

signaling protocol indicates entry. SUSP# is not an

explicit external signal, it is part of the CIS packet. (See

Section 5.2.14 "CPU Interface Serial (CIS)" on page 86

for further details.) No explicit software action required.

However, this state can be entered by explicit software

action by reading the ACPI P_VL2 register provided by

the AMD Geode LX processor’s GLCP.

5.17.2.3 Hardware Power States

• FO (Full On): From a hardware reset, all clocks come

up Full On or always running. Generally, the system

should not be left in this state. The AHCG state should

be used.

• AHCG (Active Hardware Clock Gating): This is the

desired mode of operation; it utilizes automatic hardware

clock gating. Latency to turn on a clock is near 0. This

hardware state should be established at system initial-

ization by BIOS code; after initialization it needs no addi-

tional support. AHCG is invisible to the Operating

System, ACPI, or other software based power manage-

ment facilities.

• Suspend on Halt: See CPU power state G0/S0/C1.

• Sleep: See CPU power state G1/S1/C2.

• Auto-refresh: The memory controller issues an auto-

refresh command to the DRAMs. In this state, the

DRAMs perform refresh cycles on their own without any

additional commands or activity from the memory

controller or the interface. As long as power to the

DRAMs is maintained, the memory contents are

retained.

5.17.2.4 PMC Control

Under S3, S4, and S5 power management states, all Work-

ing domain circuits, as well as the AMD Geode LX proces-

sor, are turned off to conserve power. Under S3, the

system memory is powered by VIO_VSB in Standby Auto-

refresh mode but otherwise, all other system components

are also turned off.

The PMC is used to establish overall system power states.

Normally, the Standby domain voltages are present any-

time the system is plugged into the wall; if portable, any-

time the battery is plugged in. Generally, G3 Mechanical

Off (see Table 5-34 on page 169) only applies during stor-

age or maintenance. Therefore, operationally speaking, the

PMC Standby controller is always available to manage

power. There is a class of system designs that do not

require G1 and G2 global power states. These systems

usually power-up WORKING and STANDBY power

domains simultaneously when power is applied.

For supporting Save-to-RAM (G1/S3) the WORKING out-

put is used to switch off/on the Working domain sources for

system memory while the WORK_AUX output is used to

switch off/on the Working domain sources for everything

else. Thus, the PMC can completely control the system

power states via these outputs.

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5.17.3 Software Power Management Actions

The hardware comes up from hardware system reset in the

Full On (FO) state. As part of system initialization, the

power management MSRs (see Section 6.18.1 on page

526) are written to establish the Active Hardware Clock

Gating (AHCG) state. The AHCG state is the nominal oper-

ational state.

5.17.3.1 Sleep/Standby Sequence

Entering the states under G1 and G2 requires explicit soft-

ware action. That action starts a hardware chain of events

in which some of the chain is determined by registers that

must be programmed previous to the start of the sequence.

The block diagram of the hardware involved in this

sequence is illustrated in Figure 5-52. Figure 5-53 and Fig-

ure 5-54 graphically show the Sleep/Standby sequence.

The sequence is as follows:

1) The “explicit software action” begins with a write to

PM1_CNT (ACPI I/O Offset 08h) starting the

Sleep/Standby sequence.

2) The PMC issues a Sleep Request to the CS5536 com-

panion device’s GLCP and it passes the request as

SUSP# to the AMD Geode LX processor’s GLCP.

3) The AMD Geode LX processor’s GLCP issues a sus-

pend request to the processor. After the processor has

shutdown operation, it provides a suspend acknowl-

edge back to the Geode LX processor’s GLCP.

4) The AMD Geode LX processor’s GLCP processes a

sleep sequence similar to that described in step 5,

while issuing a SUSPA# to the CS5536 companion

device’s GLCP.

Figure 5-52. PMC Power Management Elements

GLIU

Activity Counters

GeodeLink™ Device

(1 of n)

PM MSR

GLCP

DSMI, SMI, NMI, IRQ

SUSP# SUSPA#

Processor

Clock Control

Turn Off PCI/IDE Inputs

Turn Off PCI/IDE Outputs

External I/O

Sleep Request

Sleep Acknowledge

Internal Wakeup Events

External Wakeup and Thermal

Events including Buttons

SLEEP_X, SLEEP_Y,

SLP_CLK_EN#, WORKING,

and WORK_AUX

System Reset if

Wakeup from Standby

Power Low Indicator

PMC & Reset

(with Standby power)

Notes: *At least one per GeodeLink™ Device.

#Global signal, one per system.

(CIS packet)

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5) The CS5536 companion device’s GLCP processes a

Sleep sequence. This is done in one of the three ways:

a) If the CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh[1]) is 0 and the CLK_DELAY value in the

GLCP_CLK_DIS_DELAY (MSR 51700008h[23:0]) is

0, then wait until the CLK_ACTIVE flags specified in

GLCP_CLK4ACK (MSR 51700013h[43:0]) have gone

to 0.

b) If the CLK_DLY_EN bit is 1 and the CLK_DELAY

value is non-zero, then wait the amount of time of the

CLK_DELAY value.

c) If the CLK_DLY_EN is 0 and the CLK_DELAY value

is non-zero, then wait as in (a) but no longer than (b).

6) At the completion of the wait above, de-assert the

CLK_DIS bits specified in GLCP_PMCLKDISABLE

(MSR 51700009h[45:0]) and assert Sleep Acknowl-

edge to the PMC.

7) When the Sleep Acknowledge is received, the PMC

can optionally issue additional external generic con-

trols SLEEP_X and SLEEP_Y as well as SLP_CLK#

to turn off external clocks. The completion of this step

takes the system to S1. The system is now in Sleep.

8) If the Sleep Request was to enter S3 (Save-to-RAM)

then the PMC moves beyond S1 and removes main

power by de-asserting WORK_AUX and leaving

WORKING asserted. WORKING is used to power

main memory, while WORK_AUX is used for every-

thing else in the system.

9) If the Sleep Request was to enter S4 (Save-to-Disk) or

S5 (Soft Off), then the PMC moves beyond S1 and

removes main power by de-asserting both

WORK_AUX and WORKING.

10) An external or internal wakeup event reverses the

events above to bring the system back to the S0 state.

Figure 5-53. PMC System Sleep Sequence

Sleep Request

SUSP#

SUSPA#

GL Device Clock Control

Sleep Acknowledge

PCI/IDE Input Control

SLEEP_X/SLEEP_Y

PCI/IDE Output Control

SLP_CLK_EN#

Indicates a variable delay.

Note: External signals are not necessarily active high. Shown as active high for clarity.

SLP_CLK_EN# signal must be the last control to assert because it turns off all system clocks.

AMD Geode™ CS5536 Companion Device Data Book 173

Power Management Control 33238G

Figure 5-54. PMC System Wakeup Sequence

5.17.3.2 Sleep Controls

The Sleep Request/Sleep Acknowledge handshake (see

Figure 5-52 on page 171) between the GLCP and PMC

controls the transitions into and out of the Sleep and

Standby states. The PMC starts the Sleep sequence by

asserting Sleep Request to the GLCP. The GLCP requests

the processor to enter C2 by asserting the SUSP# signal.

When SUSPA# from the processor is received, the GLCP

informs the internal GeodeLink Devices of a pending shut-

down and waits until the GeodeLink Devices’ clock control

indicates that they are ready. The length of time it takes for

each device to respond is programmable (GLCP MSR

51700008h, 51700013h, and 5170000Bh). After all desig-

nated GeodeLink Devices have responded, the GLCP

asserts Sleep Acknowledge to the PMC.

The PM_IN_SLPCTL (PMS I/O Offset 20h) register and the

PM_OUT_SLPCTL (PMS I/O Offset 0Ch) are used to dis-

able PCI/IDE inputs and outputs respectively during Sleep.

Generally, they are asserted at the end of a Sleep

sequence and de-asserted at the beginning of a Wakeup

sequence. When “disabled”, some of the outputs are forced

to TRI-STATE with an active internal pull-down resistor

while the rest are simply pulled low. See Section 4.7.5

"MSR Address 4: Power Management" on page 78 for spe-

cific details on PCI/IDE I/O controls during Sleep.

5.17.3.3 Power Controls

In response to Sleep Acknowledge from the GLCP, the

PMC can assert five controls/enables: SLEEP_X,

SLEEP_Y, SLP_CLK_EN#, WORKING, and WORK_AUX.

These can control external electronic power switches and

enables. Each control’s assertion and de-assertion is sub-

ject to an enable and a programmable delay (PMS I/O Off-

set 04h to 3Ch).

Controls SLEEP_X and SLEEP_Y are generic and have no

specific use. Asserting control SLP_CLK_EN# is assumed

to turn off the system (board) clocks. It is always de-

asserted by the wakeup event. The following conditions

apply to the timing of selected output control (see Section

5.17.3.2 "Sleep Controls"), SLEEP_X, SLEEP_Y and

SLP_CLK_EN#.

When going to sleep:

a) If not enabled, SLEEP_X and SLEEP_Y do not assert at

all. If they are enabled, the delay should be set to occur

between the delays programmed in the PM_IN_SLPCTL

and PM_OUT_SLPCTL registers (PMS I/O Offset 20h and

0Ch respectively).

b) If SLP_CLK_EN# is enabled, any delays associated with

the PM_OUT_SLPCTL, SLEEP_X, and SLEEP_Y regis-

ters must be less than the SLP_CLK_EN# delay.

Sleep Request

SUSP#

SUSPA#

GL Device Clock Control

Sleep Acknowledge

PCI/IDE Input Control

SLEEP_X/SLEEP_Y

PCI/IDE Output Control

SLP_CLK_EN#

SLEEP_X/SLEEP_Y Controls should de-assert between PCI/IDE input and output controls.

Indicates a variable delay.

Note: External signals are not necessarily active high. Shown as active high for clarity.

SLP_CLK_EN# de-asserts at wakeup event and turns on system clocks.

Wakeup sequence begins with a Sleep wakeup event.

174 AMD Geode™ CS5536 Companion Device Data Book

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c) If SLP_CLK_EN# is enabled, then Sleep wakeup is pos-

sible only after SLP_CLK_EN# asserts.

d) If SLP_CLK_EN# is not enabled, and if at least one of

the following PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y

registers is enabled, then Sleep wakeup is possible only

after the longest delay of the three. The delays could be

zero.

e) If SLP_CLK_EN# is not enabled, and the

PM_OUT_SLPCTL, SLEEP_X, or SLEEP_Y registers are

not enabled, then Sleep wakeup is possible immediately.

f) If SLP_CLK_EN# is enabled and the delay associated

with the PM_OUT_SLPCTL register is longer than or equal

to the delay associated with SLP_CLK_EN#, then the

PCI/IDE outputs are not disabled.

If enabled, the de-assertion of WORKING is assumed to

remove Working power and all clock sources except 32

KHz; that is, the Standby state is entered. In this state, the

PMC disables its interface to all circuits connected to Work-

ing power and asserts RESET_OUT# before de-assertion

of WORKING. RESET_OUT# remains asserted throughout

Standby.

WORK_AUX is an auxiliary control for the Standby state

with no specific use. It can be de-asserted any time before

or after WORKING.

WORKING and WORK_AUX are independent controls, but

the use of either implies that the Standby state is to be

entered. In both cases, the PMC disables all circuits con-

nected to Working power and asserts reset. However,

since they are independent, one may be left on while the

other is de-asserted.

5.17.3.4 Wakeup Events

If the system has been put to Sleep, only preprogrammed

wakeup events can get the system running again. The

PMC contains the controls that allow the system to respond

to the selected wakeup events.

On wakeup from Sleep (not Standby, but Sleep Wakeup)

(see Figure 5-52 on page 171), the PMC immediately de-

asserts SLP_CLK_EN# to turn system clocks back on. It

also re-enables PCI/IDE outputs to allow output drivers to

return to their operational levels. Next it de-asserts

SLEEP_X and SLEEP_Y based on programmable delays.

Alternate SLEEP_X and SLEEP_Y interactions are shown

as dotted lines. Lastly, the PMC, re-enables PCI/IDE inputs

after a programmable delay and de-asserts Sleep Request.

The GLCP starts any on-chip PLLs and waits for them to

become stable. Then the GLCP de-asserts SUSP# to the

processor. When the processor de-asserts SUSPA#, the

GLCP de-asserts Sleep Acknowledge. The PMC allows the

wakeup event to assert a System Control Interrupt (SCI).

After a wakeup event:

a) PCI/IDE outputs are re-enabled after SLP_CLK_EN# is

de-asserted.

b) PCI/IDE inputs are re-enabled at Sleep wakeup or after

a programmable delay. Generally, PCI/IDE inputs are nor-

mally used with a delay and that delay is longer than any

de-assertion delay associated with SLEEP_X and/or

SLEEP_Y. Re-enabling PCI/IDE inputs is generally not

useful at the beginning of a wakeup sequence.

c) Sleep Request is de-asserted at Sleep wakeup or after a

programmable delay. Sleep Request is kept de-asserted

until the PCI/IDE inputs are re-enabled. Generally, the

enable and delay values in PM_SED (PMS I/O Offset 14h)

and PM_IN_SLPCTL (PMS I/O Offset 20h) should always

be the same.

d) If used, SLEEP_X/SLEEP_Y delay should be set to

occur between the delays programmed in

PM_OUT_SLPCTL and PM_IN_SLPCTL (PMS I/O Offset

0Ch and 20h respectively). If the delays for

SLEEP_X/SLEEP_Y are longer than the PM_IN_SLPCTL

delay, then SLEEP_X/SLEEP_Y de-assert at the same

time as the PCI/IDE inputs are re-enabled.

On wakeup from Standby (not Sleep, but Standby Wakeup)

the PMC asserts WORKING and performs a system reset.

RESET_OUT# is de-asserted after a programmable delay

and the normal software start-up sequence begins. How-

ever, early in the sequence, the software checks the PMC

state to determine if waking from Standby (PMS I/O Offset

54h[0]). If yes, then the system state is potentially restored

from non-volatile storage.

If enabled, WORK_AUX may be asserted before or after

RESET_OUT# is de-asserted.

5.17.3.5 Fail-Safe Power Off

The PMC provides the support logic to implement an ACPI

compliant fail-safe power off button. This logic uncondition-

ally de-asserts the WORKING and WORK_AUX signals if

the On/Off button is held down for a programmable delay.

For ACPI compliance, this delay should be set to four sec-

onds.

5.17.3.6 Wake Events Status and SCI

When enabled, a wake event from the general wake events

isters" on page 509) sets its status bit and the WAK_STS

bit and causes a system control interrupt (SCI). The Sleep

button, RTC alarm, and power button when asserted,

always set their status bit. They set the WAK_STS bit and

generate an SCI only when their enable bit is set. When

overflowed, the PM timer sets its status bit. This overflow

condition does not cause a wakeup event but if enabled, it

generates an SCI. The event’s status is cleared by writing a

one to it.

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5.17.4 PMC Power Management States

The PMC state machines support the fundamental hard-

ware states: Power Off, Reset Standby, Working, Sleep,

and Controlled Standby.

• Reset Standby State: From Power Off, reset is applied

to the Standby domain by the external input pin

RESET_STAND#. Once reset, the Reset Standby state

de-asserts WORKING and WORK_AUX outputs and

waits for a Reset Standby wakeup event.

• Working State: The Working state can be entered from

Reset Standby, Sleep, or Controlled Standby states.

Working state is established when Working power is

applied and all system clocks are enabled. Once in this

state, registers and functions in the PMC can be initial-

ized, programmed, enabled/disabled, and the potential

exists for the system to proceed to the Sleep state or

Standby state.

• Sleep State: The system initiates the entry to the Sleep

state with a Sleep sequence. Under the Sleep state,

Working and Standby power are maintained. PCI/IDE

inputs are disabled when Sleep Acknowledge asserts.

PCI/IDE outputs are disabled when Sleep Acknowledge

asserts or after a programmable delay. SLEEP_X,

SLEEP_Y, and SLP_CLK_EN# may be asserted if

enabled. A Sleep wakeup event returns the system to

Working state.

• Controlled Standby State: Can be entered “normally”,

“fault condition”, or by a “restart”.

A normal entry is by way of a system initiated sequence as

in the Sleep case. This method of entry requires the

Standby state machine to monitor SLP_CLK_EN# and look

for an enable of the “Working De-assert Delay and Enable”

Work_aux De-assert Delay and Enable register

(PM_WKXD, PMS I/O Offset 34h[30]). This signals the

Controlled Standby state normal entry. A Standby wakeup

event returns the system to Working state after a program-

mable delay (PM_NWKD, PMS I/O Offset 4Ch).

If enabled, a faulted entry can be initiated by a low power

off, thermal off, or fail-safe off. It can also be initiated by

Working power fail asserted. A default wakeup event

returns the system to the Working state after a programma-

ble delay (PM_AWKD, PMS I/O Offset 50h).

A re-start can be initiated by any of these resets: GLCP

soft reset, soft reset, shutdown reset, watchdog reset, or

bad packet type reset. The system returns to the Working

state when reset is de-asserted and the abnormal work

delay (PM_AWKD) expired. WORKING and WORK_AUX

are not de-asserted.

When a Controlled Standby state is entered by a faulted

condition or restart event, software control is assumed lost

and the software established state is assumed to be poten-

tially wrong. Therefore, the Standby domain returns to the

state associated with “Standby State Entry from Power

Off”; that is, Standby domain reset defaults are used. The

only exceptions are registers from the following list; these

are locked and not subject to change by software:

PM_RD De-assert Reset Delay from Standby

(PMS I/O Offset 38h)

PM_WKXA WORK_AUX Assert Delay from Standby

(PMS I/O Offset 3Ch)

PM_FSD Fail-Safe Delay and Enable

(PMS I/O Offset 40h)

PM_TSD Thermal Safe Delay and Enable

(PMS I/O Offset 44h)

PM_PSD Power Safe Delay and Enable

(PMS I/O Offset 48h)

PM_NWKD Normal to Work Delay and Enable

(PMS I/O Offset 4Ch)

PM_AWKD Abnormal Work Delay and Enable

(PMS I/O Offset 50h)

The Abnormal Work Delay and Enable (PM_AWKD) regis-

ter is the only one of the above registers that potentially

applies during a re-start entry.

Lastly, note that any normal entry operation in process is

aborted.

Wakeup from faulted entry is the same as that associated

with Standby State Entry from Power Off; that is, it acts as

if the power button has been pushed. Other possible

wakeup events such as RTC Alarm and PMEs are ignored.

However, the system can be held in the Standby state for

the following reasons:

1) If enabled and locked, LOW_BAT# is still asserted.

2) If LVD_EN# is tied to ground and VCORE is not at a

valid voltage, or if RESET_WORK # is asserted.

Note: If enabled and locked, the thermal alarm does not

keep the system in the Standby state if it is

asserted. The thermal alarm circuitry resides in the

Working domain, and its state is ignored by the

Standby state. Once out of Standby, the thermal

alarm again comes into play. If it is still asserted, its

timer would start again.

The Power Management Control (PMC) has two state

machines:

• Working State Machine: Operates under Working

power and runs on a 14 MHz clock from the CCU. Its

function is to generate control signals used to turn off/on

systems clocks and I/Os based on events coming from

on or off the chip.

• Standby State Machine: Operates under Standby

power and runs on the 32 KHz clock. Its function is to

power-up and down the Working power to the Working

domain based on events coming from on or off the chip.

176 AMD Geode™ CS5536 Companion Device Data Book

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5.17.5 PMC Power Management Events

A large number of inputs to the PMC are used to monitor

and create system power managements events. Some of

these inputs apply the Working state machine while the

remainder apply to the Standby state machine.

5.17.5.1 PM Sleep Events

•Sleep:

— Sleep sequence initiated by software

•Wakeup:

— Assertion of the Sleep Button (SLEEP_BUT)

— Assertion of the Power Button (PWR_BUT#)

—RTC alarm

— Working power domain PMEs

— Standby power domain PMEs

5.17.5.2 PM Standby Events

•Standby:

— Sleep sequence initiated by software

— LVD detection of low voltage on VCORE (system fault)

— Assertion of the Power Button for 4 seconds

(PWR_BUT#, system fault)

— Thermal Alarm (THRM_ALRM#, system fault)

— Low battery (LOW_BAT#, system fault)

— Hardware reset (system restart)

— Software initiated reset (system restart)

— Shutdown initiated reset, CPU triple fault (system

restart)

— Watchdog initiated reset (system restart)

— GLCP software initiated reset (system restart)

— Bad packet type reset (system restart)

— Reset Standby state machine RESET_STAND#

(Standby)

•Wakeup:

— Assertion of the Power Button (PWR_BUT#)

—RTC Alarm

— Standby power domain PMEs

Note: While the system is in the Standby state and

THRM_ALRM# or LOW_BAT# are asserted, wakeup

events (e.g., assertion of PWR_BTN#) are recognized (i.e.,

the associated status flags are set (e.g., PWRBTN_FLAG

in PM1_STS)), but do not cause the system to exit from the

Standby state due to THRM_ALRM# or LOW_BAT# being

asserted. When THRM_ALRM# and LOW_BAT# are de-

asserted wakeup event flags can cause the system to exit

the Standby state when accordingly enabled.

Table 5-35 provides a complete list of the power manage-

ment inputs and describes their function. The system can

only be in one of three states: Working, Sleep, or Standby.

The activity of the inputs is to move the system from one

state to another.

Table 5-35. PM Events and Functions

Event

Current

State Function

The following events are Sleep and/or Standby wakeup events (except for ACPI Timer).

PWR_BTN#

(also serves as a

Standby event)

Working Sets the status bit (PWRBTN_FLAG) in PM1_STS (ACPI I/O Offset 00h[8] = 1).

If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), an SCI is generated.

Sleep Sets the status bit (PWRBTN_FLAG) in PM1_STS (ACPI I/O Offset 00h[8] = 1).

If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), SCI generation and wakeup

from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1).

Standby Sets the status bit (PWRBTN_FLAG) in PM1_STS (ACPI I/O Offset 00h[8] = 1).

If PWRBTN_EN is enabled (ACPI I/O Offset 02h[8] = 1), SCI generation and wakeup

from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1).

SLP_BTN Working Sets the status bit (SLPBTN_FLAG) in PM1_STS (ACPI I/O Offset 00h[9] = 1).

If SLPBTN_EN is enabled (ACPI I/O Offset 02h[9] = 1), an SCI is generated.

Sleep Sets the status bit (SLPBTN_FLAG) in PM1_STS (ACPI I/O Offset 00h[9] = 1).

If SLPBTN_EN is enabled (ACPI I/O Offset 02h[9] = 1), SCI generation and wakeup

from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1).

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Power Management Control 33238G

RTC Alarm Working Sets the status bit (RTC_FLAG) in PM1_STS (ACPI I/O Offset 00h[10] = 1).

If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), an SCI is generated.

Sleep Sets the status bit (RTC_FLAG) in PM1_STS (ACPI I/O Offset 00h[10] = 1).

If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), SCI generation and wakeup

from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1).

Standby Sets the status bit (RTC_FLAG) in PM1_STS (ACPI I/O Offset 00h[10] = 1).

If RTC_EN is enabled (ACPI I/O Offset 02h[10] = 1), SCI generation and wakeup

from this event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset 00h[15] = 1).

ACPI Timer

(internal timer)

Working Sets the status bit (TMR_FLAG) in PM1_STS (ACPI I/O Offset 00h[0] = 1).

If TMR_EN is enabled (ACPI I/O Offset 02h[0] = 1), an SCI is generated.

GPE[23:0]

(General Purpose

Power Manage-

ment Events in

Working Domain)

Working If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), the corresponding

status bit (GPE_STS[23:0]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an

SCI is generated.

Sleep If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and

wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset

00h[15] = 1).

GPE[31:24]

(General Purpose

Power Manage-

ment Events in

Standby Domain)

Working If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding

status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an

SCI is generated.

Sleep If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and

wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset

00h[15] = 1).

Standby If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding

status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set, and

SCI generation and wakeup from the event is enabled (i.e., sets the WAK_STS bit,

ACPI I/O Offset 00h[15] = 1).

The following events caused a Standby state entry.

RESET_STAND# Working If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset

54h[0]) is set and causes a Reset Standby state entry. No Working or Standby

power.

Sleep If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset

54h[0]) is set and causes a Reset Standby state entry. No Working or Standby

power.

Standby If asserted in Restart, or Normal or Faulted Standby state, the corresponding status

bit (OFF_FLAG) in PM_SSC (PMS I/O Offset 54h[0]) is set and causes a Reset

Standby state entry.

LVD circuit detects

low voltage on

VCORE

Working If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set

and causes an Faulted Standby state entry. Working power is turned-off.

Sleep If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set

and causes an Faulted Standby state entry. Working power is turned-off.

Standby If de-asserted in Restart state, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Off-

set 54h[2]) is set and causes an Faulted Standby state entry.

Table 5-35. PM Events and Functions (Continued)

Event

Current

State Function

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PWR_BTN# Working If enabled and asserted for four seconds (fail-safe), the status bit (PWRBTN_FLAG)

in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state

entry. Working power is turned-off.

Sleep If enabled and asserted for four seconds (fail-safe), the status bit (PWRBTN_FLAG)

in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state

entry. Working power is turned-off.

Standby If enabled and asserted for four seconds (fail-safe) while in Normal or Restart state,

the status bit (PWRBTN_FLAG) in PM_SSC (PMS I/O Offset 54h[3]) is set and

causes a Faulted Standby state entry.

THRM_ALRM# Working If enabled and asserted for a programmable amount of time, the status bit

(THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted

Standby state entry. Working power is turned-off.

Sleep If enabled and asserted for a programmable amount of time, the status bit

(THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted

Standby state entry. Working power is turned-off.

Standby Ignored.

LOW_BAT# Working If enabled and asserted for a programmable amount of time, the status bit

(LOWBAT_FLAG) in PM_SSC (PMS I/O Offset 54h[5]) is set and causes an Faulted

Standby state entry. Working power is turned-off.

Sleep If enabled and asserted for a programmable amount of time, the status bit

(LOWBAT_FLAG) in PM_SSC (PMS I/O Offset 54h[5]) is set and causes an Faulted

Standby state entry. Working power is turned-off.

Standby If asserted in Normal or Re-start state, the status bit (LOWBAT_FLAG) in PM_SSC

(PMS I/O Offset 54h[5]) is set and causes a Faulted state entry.

RESET_WORK# Working If asserted, the status bit (HRD_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[6]) is

set and causes a Restart state entry. Working power is not turned-off.

Sleep If asserted, the status bit (HRD_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[6]) is

set and causes a Restart state entry. Working power is not turned-off.

Software initiated

reset

Working If asserted, the status bit (SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[8]) is

set and causes a Restart state entry. Working power is not turned-off.

Sleep If asserted, the status bit (SFT_RST_FLAG) in PM_SSC (PMS I/O Offset 54h[8]) is

set and causes a Restart state entry. Working power is not turned-off.

Shutdown initiated

reset (CPU triple

fault)

Working If asserted, the status bit (SHTDWN_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[9]) is set and causes a Re-start state entry. Working power is not turned-off.

Sleep If asserted, the status bit (SHTDWN_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[9]) is set and causes a Restart state entry. Working power is not turned-off.

Watchdog initiated

reset

Working If asserted, the status bit (WATCHDOG_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[10]) is set and causes a Restart state entry. Working power is not turned-off.

Sleep If asserted, the status bit (WATCHDOG_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[10]) is set and causes a Restart state entry. Working power is not turned-off.

GLCP Soft Reset Working If asserted, the status bit (GLCP_SFT_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[11]) is set and causes a Restart state entry. Working power is not turned-off.

Sleep If asserted, the status bit (GLCP_SFT_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[11]) is set and causes a Restart state entry. Working power is not turned-off.

Table 5-35. PM Events and Functions (Continued)

Event

Current

State Function

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Power Management Control 33238G

Bad packet type

reset

Working If asserted, the status bit (BADPACK_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[12]) is set and causes a Restart state entry. Working power is not turned-off.

Sleep If asserted, the status bit (BADPACK_RST_FLAG) in PM_SSC (PMS I/O Offset

54h[12]) is set and causes a Restart state entry. Working power is not turned-off.

Table 5-35. PM Events and Functions (Continued)

Event

Current

State Function

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5.18 Flash Controller

The AMD Geode™ CS5536 companion device has a Flash

interface that supports popular NOR Flash and inexpensive

NAND Flash devices. This interface is shared with the IDE

interface, using the same balls. NOR or NAND Flash may

co-exist with IDE devices using PIO (Programmed I/O)

mode. The 8-bit interface supports up to four “lanes” of

byte-wide Flash devices through use of four independent

chip selects, and allows for booting from the array. Hard-

ware support is present for SmartMedia-type ECC (Error

Correction Code) calculations, off-loading software from

having to support this task. If Flash and IDE are both oper-

ational, an external pullup (10K) to IDE_DREQ0 (A14) and

IDE_DREQ0 must not be connected to the IDE device. To

switch modes, explicit software actions must occur to dis-

able one and enable the other.

Features

•Supports popular NOR Flash and inexpensive NAND

Flash devices on IDE interface. No extra pins needed.

•NOR Flash and NAND Flash co-exist with IDE devices

with PIO (Programmed I/O) only mode.

•General purpose chip select pins support on-board ISA-

like slave devices.

•Programmable timing supports a variety of Flash

devices.

•Supports up to four byte-wide NOR Flash devices.

— Address up to 256 KB boot ROMs using an external

octal latch.

— Address up to 256 MB linear Flash memory arrays

using external latches.

— Boot ROM capability.

— Burst mode capability (DWORD read/write on PCI

bus).

•Supports up to four byte-wide NAND Flash devices.

— Hardware support for SmartMedia-type ECC (Error

Correction Code) calculation off-loading software

effort.

•Supports four programmable chip select pins with

memory or I/O addressable.

— Up to 1 KB of address space without external latch.

5.18.1 NAND Flash Controller

To understand the functioning of the NAND Flash Control-

ler, an initialization sequence and a read sequence is pro-

vided in the following subsections. The NAND Flash

Controller’s registers can be mapped to memory or I/O

space. The following example is based on memory

mapped registers.

5.18.1.1 Initialization

1) Program DIVIL_LBAR_FLSH0 (MSR 51400010h) to

establish a base address (NAND_START) and

whether in memory or I/O space. The NAND Controller

is memory mapped in this example and always occu-

pies 4 KB of memory space.

2) Set the NAND timing MSRs to the appropriate values

(MSRs 5140001Bh and 5140001Ch).

5.18.1.2 Read

1) Allocate a memory buffer. Start at address BAh in sys-

tem memory.

2) Fill the buffer with the following values:

– BA: 02h (Assert CE#, CLE)

– BA + 1: 00h (Command: Read mode)

– BA + 2: 04h (Assert CE#, ALE, De-assert CLE)

– BA + 3: CA (Start column address)

– BA + 4: 04h

– BA + 5: PA0 (Page address byte 0)

– BA + 6: 04h

– BA + 7: PA1 (Page address byte 1)

– BA + 8: 04h

– BA + 9: PA2 (Page address byte 2)

– BA + 10: 08h (Assert CE#, De-assert ALE, Enable

Interrupt)

3) For (i = 0; i < 11; i++), write the data in buffer [BA+i] to

memory location [NAND_START + 800h + i]. Generate

the command and address phase on the NAND Flash

interface.

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Flash Controller 33238G

4) NAND Flash device may pull down the RDY/BUSY#

signal at this point. Software sets the EN_INT bit and

waits for the interrupt.

5) Memory byte writes 03h to memory location

[NAND_START + 815h] to clear ECC parity and

Enable ECC engine.

6) For (i = 0; i < 256; i++), read data from [NAND_START

+ i] to buffer [BA + i] (read data from NAND Flash to

memory buffer. Can use DWORD read to save time).

7) Memory DWORD Reads [NAND_START + 810h] to

get ECC parity [ECC0] of first 256 byte data.

8) Memory byte writes 03h to memory location

[NAND_START + 815h] to clear ECC parity and

enable ECC engine.

9) For (i = 256; i < 512; i++), read data from

[NAND_START + i] to buffer [BA + i] (read data from

NAND Flash to memory buffer. Can use DWORD read

to save time).

10) Memory DWORD reads [NAND_START + 810h] to get

ECC parity [ECC1] of second 256 byte data.

11) For (i = 512; i < 528; i++), read data from

[NAND_START + i] to buffer [BA + i] (read data from

NAND Flash redundant data to memory buffer. Can

use DWORD read to save time).

12) Write 01h to memory location [NAND_START + 800h]

(de-assert CE#, NAND Flash enters to Idle state).

13) Retrieve ECC parity data from redundant data area

and compare them to ECC0 and ECC1.

14) Correct data if data error is detected and can be fixed.

Figure 5-55 on page 181 shows a basic NAND read cycle.

Figure 5-55. Flash Controller NAND Read Cycle

CLE

CE#

WE#

ALE

RE#

I/O

R/B#

D0 D1 D2 D

(n-1)

PA2PA1PA0CA00h

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5.18.1.3 NAND ECC Control Device

The NAND ECC Control device is part of the NAND Flash

Controller. It calculates 22-bit ECC parity for each of the

256 bytes of the NAND Flash’s data transferred on the

Local bus. The ECC calculation algorithm follows the

SmartMedia Physical Format Specification. The ECC algo-

rithm is capable of single-bit correction and 2-bit random-

error detection. ECCs are generated only for data areas

and no ECC is generated for page-data redundant areas

containing ECCs as the page-data redundant area is dupli-

cated for reliability. For ECC calculations, 256 bytes are

handled as a stream of 2048-bit serial data. In the event of

an error, the error-correction feature can detect the bit loca-

tion of the error based on the results of a parity check and

correct the data.

Hardware Operation

The ECC engine treats 256-byte data as a block. Each byte

has an 8-bit address called a Line Address (LA). Each bit in

a byte has a 3-bit address called a Column Address (CA).

Combining these two address fields forms an 11-bit unique

address for every single bit in the 256-byte data block. The

address uses the notation: LLLL_LLLL, CCC. This device

contains an 8-bit counter to keep track of the LA of each

byte. Each ECC parity bit calculation in the ECC engine

produces even parity of half of the data bits in the block.

Different parity bits use different sets of the bits. For exam-

ple, CP0 is the even parity bit of the bits with Column

Address bit 0 equals 0. CP1 is the even parity bit of the bits

with Column Address bit 0 equals 1. Both odd and even

parity are supported for ECC. The ECC parity available in

the NAND ECC column, LSB line, and MSB line parity reg-

isters is the inverted output of the ECC parity from the ECC

engine in the case of odd ECC parity and the non-inverted

output in the case of even parity. Table 5-36 lists the rela-

tionship between the parity bits and the corresponding bit

addresses. The hardware ECC engine calculates 22-bit

ECC parity whenever there is a data write or data read

to/from the NAND Flash device. On power-up, the ECC

engine is configured to be odd parity. Even or odd ECC

parity is controlled by bit 2 of NAND ECC Control register

(Flash Memory Offset 815h[2]). For more information on

the Flash Controller, see the NAND Flash Device Specifi-

cation.

Table 5-36. ECC Parity/Bit Address Relationship

Parity Bit Address

CP0 xxxx_xxxx, xx0

CP1 xxxx_xxxx, xx1

CP2 xxxx_xxxx, x0x

CP3 xxxx_xxxx, x1x

CP4 xxxx_xxxx, 0xx

CP5 xxxx_xxxx, 1xx

LP00 xxxx_xxx0, xxx

LP01 xxxx_xxx1, xxx

LP02 xxxx_xx0x, xxx

LP03 xxxx_xx1x, xxx

LP04 xxxx_x0xx, xxx

LP05 xxxx_x1xx, xxx

LP06 xxxx_0xxx, xxx

LP07 xxxx_1xxx, xxx

LP08 xxx0_xxxx, xxx

LP09 xxx1_xxxx, xxx

LP10 xx0x_xxxx, xxx

LP11 xx1x_xxxx, xxx

LP12 x0xx_xxxx, xxx

LP13 x1xx_xxxx, xxx

LP14 0xxx_xxxx, xxx

LP15 1xxx_xxxx, xxx

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Software Operation

The NAND Flash contains a redundant data area contain-

ing ECC fields. While writing to the NAND Flash, the hard-

ware ECC engine calculates ECC parity, if it is enabled

properly. Software can write the ECC parity bits to the ECC

field after writing the data area. When software reads the

data from NAND Flash, the hardware ECC engine calcu-

lates ECC parity. After the data is read from the NAND

Flash, software can compare the ECC parity in the hard-

ware ECC engine and the ECC parity in the ECC field of

the NAND Flash to determine if the data block is correct.

Each data bit has 11 corresponding parity bits, which can

be determined by the bit address. If one data bit is different

from its original value, 11 ECC parity bits are changed from

the original ECC parity bits. Take the ECC parity from the

hardware ECC engine and perform bit-wise exclusive OR

with it and the ECC parity field in NAND Flash. The result

can be as follows.

1) All bits are 0. The data is correct.

2) Eleven bits are 1. One bit error has been detected.

Use the eleven bits to identify the error bit position.

3) One bit is 1. One bit in ECC field is corrupt. Data area

should be OK.

4) Otherwise, two or more data bits are corrupt. Cannot

be corrected.

5.18.2 NOR Flash Controller/General Purpose

Chip Select

The NOR Flash Controller supports up to four independent

chip selects that can be used for NOR Flash devices or

General Purpose Chip Selects (GPCS). Up to 28 bits of

address is supported for each chip select, allowing byte-

wide linear arrays up to 256 MB in memory space. Chips

selects may also be located in I/O space, but the usable

address bits are limited by the over all limits of I/O space.

Each chip select is independently programmable:

•Address Setup: Defaults to seven Local bus clocks

•Read/Write Strobe Width: Defaults to seven Local bus

clocks

•Address Hold: Defaults to seven Local bus clocks cycles

•Optional Wait State Insertion: Defaults off, driven by an

external input (FLASH_IOCHRDY) to be used by

General Purpose devices.

•Optional Write Protect: Defaults protected

These settings are located in MSR space and on hard

reset default to the settings listed above. Hence, virtually

any NOR device can be used immediately out of reset for

first instruction fetch. After booting, delays can be pro-

grammed as appropriate.

Special considerations must be made for NOR Flash write

operations. Depending on the manufacturer and write

mode, each write can take from a few microseconds to a

few hundred microseconds. Specifically, the software per-

forming the write must observe the following procedure:

1) Write to device.

2) Wait an amount of time dependent on manufacturer’s

specifications.

3) Repeat from #1 until all writes are completed.

The “wait” in step two is implemented using an appropriate

time base reference. There is no reference within the Flash

Controller device.

Some NOR devices provide a ready line that de-asserts

during the “wait” in step two. Direct use of this signal is not

supported by the Flash Controller. The NOR write software

should use an appropriate time base reference to deter-

mine when the device is ready, that is, determine how long

to wait for the current write to complete before starting

another write. Alternatively, the NOR device internal status

may be read to determine when the write operation is com-

plete. Refer to NOR Flash manufacturer’s data sheets for

additional write operation details.

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5.18.3 Flash Controller Interface Timing Diagrams

5.18.3.1 NOR/GPCS

The NOR/GPCS timing has two phases: address phase

and data phase.

In the address phase, the address bus and data bus

present a higher address, ADD[27:10]. Board designers

can use external latches, such as 74x373, to latch the

address bits.

In the data phase, the address bus presents ADD[9:0], and

the data bus is for data read or write.

The Flash Controller is running off the internal Local bus

clock (maximum frequency 33 MHz). The address phase is

always two clock periods. The ALE signal asserts high in

the first-half clock period and de-asserts in the second

clock period. A 74LCX373 only needs 4 ns setup time and

2 ns hold time (worst case). This timing provides a lot of

flexibility for the designing of the board. In the data phase,

the address bus and write data bus are available in the first

clock period. In the second clock period of the data phase,

chip select goes low. After the required hold time, chip

select goes high, and write data bus change. After one

Local bus clock from chip select change (going high),

address bus changes. The setup time, strobe pulse width,

and hold time are programmable through the NOR timing

registers. See Section 6.19.1.2 "NOR Flash Timing MSRs"

on page 552.

Figure 5-56 and Figure 5-57 provides some NOR Flash

timing examples.

Figure 5-56. NOR Flash Basic Timing

ADD[9:0]

ALE

CS#

WE#, RE#

DATA (write)

DATA (read)

01234XYY+1Y+2ZZ+1Z+2

Address

Phase Data Phase

tS tH

DataHigher Address

Higher Address Data

»»

Higher Address Lower Address

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Figure 5-57. NOR Flash with Wait States Timing

ADD[9:0]

ALE

CS#

WE#, RE#

DATA (write)

DATA (read)

01234XYY+1Y+2ZZ+1Z+2

Address

Phase Data Phase

tS tH

DataHigher Address

Higher Address Data

»»

Wait States

»Don’t Care

Don’t Care

IOCHRDY

»»»

Higher Address Lower Address

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5.18.3.2 NAND

The NAND Flash interface has three external timings that are controlled by nine timing registers. The timing parameters are

described in Table 5-37 and illustrated in Figures 5-58 through 5-60.

Figure 5-58. NAND Flash Command/Address Timing

Table 5-37. NAND Flash External Timing Parameters

Symbol Description

tCS Control Setup Time. The setup time from the toggle of the control signals to the falling edge of WE#.

tCP Control Pulse Width. The WE# active pulse width in the Command/Address phase.

Note that the command/address byte is put on the I/O bus at the same time that the WE# is asserted.

tCH Control Hold Time. The hold time from the rising edge of WE# to the toggle of the control signals.

Note that the I/O bus is turned off when the tCH expires.

tWS Data Write Setup Time. This timing is just for the internal state machine; no external reference point.

Can be set to 0 if the setup time is not needed.

tWP Data Write Pulse Width. The WE# active pulse width in the data write phase.

Note that the data byte is put on the I/O bus at the same time that WE# is asserted; no external reference

point. Can be set to 0 if the hold time is not needed.

tRP Data Read Pulse Width. The RE# active pulse width in the data read phase.

tRH Data Read Hold Time. This timing is just for the internal state machine; no external reference point.

Can be set to 0 if the hold time is not needed.

tRS Data Read Setup Time. This timing is just for the internal state machine; no external reference point.

Can be set to 0 if the setup time is not needed.

tCS tCH

tCP tCH

Command / Address

012 XX+1YZZ+1

»»

WE#

34Z+2

CTLR_BUSY

I/O[7:0] »»»

Note: CTLR_BUSY is bit 2 of the NAND Status register (Flash Memory Offset 810h or Flash I/O Offset 06h).

AMD Geode™ CS5536 Companion Device Data Book 187

Flash Controller 33238G

Figure 5-59. NAND Data Timing with No Wait States and No Prefetch (for the first data read)

Figure 5-60. NAND Data Timing with Wait States

tWS / tRS tWP / tRP tWH / tRP

0123XYY+1ZZ+1Z+2

WE# / RE#

I/O [7:0] (write)

I/O [7:0] (read)

tWS / tRS tWP / tRP tWH / tRH

0123XYY+1ZZ+1Z+2

WE# / RE#

I/O [7:0] (write)

I/O [7:0] (read)

»»

Wait State

FLASH_RDY/BUSY#

188 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ Control Processor

33238G

5.19 GeodeLink™ Control Processor

The GeodeLink™ Control Processor (GLCP) functionality

is illustrated in Figure 5-61 and is summarized as:

•Serial to GeodeLink conversion to facilitate JTAG

accesses to GeodeLink Devices

•Power management support (reset and clock control)

•MSRs

Together with a JTAG controller, the GLCP provides com-

plete visibility of the register state that the chip is in. All reg-

isters are accessible via the JTAG interface.

How the JTAG controller interfaces with the GLCP is

beyond the scope of this document and is not explained

here.

The GLCP also works with the CCU (Clock Control Unit)

blocks of other GeodeLink Devices to provide clock control

via its relevant MSRs. The GLCP supplies the clock enable

signals to all the CCUs, which allows clocks to be shut off if

the power management logic generates a Sleep request or

if a debug event triggers a clock disable situation.

Figure 5-61. GLCP Block Diagram

5.19.1 GeodeLink Power Management Support

The main power management functions are performed by

the Power Management Logic, with the GLCP playing a

supporting role. (See Section 5.17 "Power Management

Control" on page 169 for a complete understanding of

power management.)

5.19.1.1 Soft Reset

This is one of the active high soft reset sources going to the

Power Management Logic. It resides in the

GLCP_SYS_RST register (MSR 51700014h). When

active, all circuitry in the CS5536 companion device is

reset (including the GLCP_SYS_RST register itself).

5.19.1.2 Clock Control

The GLCP provides a mechanism to shut off clocks. The

busy signal from a module can control the clock gating in

its CCU, however, clocks can also be enabled or disabled

by the functional clock enable signals coming from the

GLCP. These enable signals are asynchronous to the mod-

ules and need to be synchronized in the CCU blocks before

being used to enable or disable the functional clocks.

The clocks can be disabled in one or a combination of the

three ways below. All the MSRs mentioned can be found in

Section 6.18 "Power Management Controller Register

Descriptions" on page 524 and Section 6.20 "GeodeLink™

Control Processor Register Descriptions" on page 561.

1) The power management circuitry disables the clocks

when going into Sleep. The Sleep sequence is started

by the assertion of Sleep Request from the Power

Management Logic. The GLCP asserts Sleep Request

and waits for the assertion of Sleep Acknowledge,

which indicates that the clocks should be disabled.

There are two ways to do this:

A) If Sleep Acknowledge is asserted and the clock dis-

able delay period has expired, disable the clocks spec-

ified in GLCP_PMCLKDISABLE (MSR 51700009h).

Each bit in GLCP_PMCLKDISABLE corresponds to a

CCU, and when set, indicates that the clock going to

that CCU should be disabled during a Sleep

sequence. The clock disable delay period is specified

by the CLK_DELAY bits in GLCP_CLK_DIS_DELAY

(MSR 51700008h), and is enabled by the

CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh). It is clocked by the PCI functional clock.

Serial to GL

Conversion

MSR Registers

Power

Management

Support

PCI Interface

Req Req Data Data

TAP Controller

PCI Clock

GeodeLink™ Interface

Out In Out In

AMD Geode™ CS5536 Companion Device Data Book 189

GeodeLink™ Control Processor 33238G

B) If Sleep Acknowledge is asserted and the clock dis-

able delay period is not enabled, check to see if all

clocks specified by GLCP_CLK4ACK (MSR

51700013h) have become inactive. If

GLCP_CLKACTIVE (MSR 51700011h) shows that

those clocks are indeed inactive, disable the clocks

specified in GLCP_PMCLKDISABLE (MSR

51700009h).

Sleep Acknowledge is asserted after the clocks have

been disabled. The wakeup sequence is triggered by

the de-assertion of the Sleep Request, which turns on

all the clocks.

2) If a debug event in the debug circuitry triggers a clock

disable, disable all the clocks specified in

GLCP_CLKDISABLE. Each GLCP_CLKDISABLE bit

corresponds to a CCU, and when set, indicates that

the clock going to that CCU should be disabled.

3) Each bit in GLCP_CLKOFF (MSR 51700010h) corre-

sponds to a CCU. When set, the bit indicates that the

clock going to that CCU should be disabled. This is the

simplest case.

5.19.2 GLCP Clocks

The GLCP has multiple clock domains, namely the

GeodeLink clock and PCI clock. The GeodeLink clock is

the clock source for the MSRs, the serial interface, and the

GeodeLink interface. The PCI clock is used in the power

management support for the clock disable delay timer. Both

the GeodeLink and PCI functional clocks come from pri-

mary inputs. All these clocks are handled by a CCU. Even

though the PCI clock is always running in functional mode,

a CCU is needed to be able to perform reset synchroniza-

tion and to turn off the internal clock to support TAPSCAN.

The CCUs used by the GLCP are the asynchronous ver-

sions, since the GLCP outputs asynchronous busy signals.

190 AMD Geode™ CS5536 Companion Device Data Book

Test Controller

33238G

5.20 Test Controller

The TAP controller is IEEE 1149.1 specification compliant.

A block diagram of the TAP controller and the boundary

scan implementation are shown in Figure 5-62. The TAP is

programmable by means of TAP control instructions,

shown in Table 5-38 on page 191. All data registers shift in

and out data, LSB first. The instruction register and all data

registers are shift registers, so if more bits are shifted in

than the register can hold, only the last bits shifted in, the

MSBs, are used. This can be useful on systems that

always shift in a multiple of 8 bits to the data or instruction

registers.

The TAP controller can be initialized synchronously or

asynchronously. For a synchronous reset, holding TMS

high and clocking TCK_C a minimum of five times puts the

TAP state machine into the Test-Logic-Reset state. Asyn-

chronous reset is available by asserting TRST_N (Tap

Controller Reset). From TRST_N, the TAP state machine

immediately enters the Test-Logic-Reset state. On this

device TRST_N is connected to RESET_WORK#.

Figure 5-62. TAP Controller Boundary Scan Block Diagram

PAD

PADPAD PAD PAD

PAD

TDO

TDI

Instruction Shift Register

Instruction Register IR

captureIR updateIR

Data Shift Register

captureDR

IR[0]

MBIST Register ID Register

TAP

TRST

TMS

TCK

TDI

scan_update_outputs_clk

scan_clk

scan_shiftdr

scan_enable

Scan Chains in Debug Mode

Bypass Mode Flipflop

USB PHY Test Register

captureDR updateDR

AMD Geode™ CS5536 Companion Device Data Book 191

Test Controller 33238G

5.20.1 Instruction Register

The TAP controller has specific pre-assigned meanings to

the bits in the 24-bit IR register. Note that the bits only

affect the processor once the Update-IR JTAG state occurs

in the JTAG controller. Shifting through these bits will not

change the state of internal signals (for example

test_mode). The details on JTAG controller states are cov-

ered in the IEEE 1149.1 standard.

Table 5-38. TAP Controller Instructions

Instruction IR Name Brief Description

000000h and

FFFFE8h

EXTEST[241:0] Boundary Scan Register. IEEE 1149.1 specification compliant.

(Mapped twice in IR address space.)

01EFFAh,

03EFFAh,...,

45EFFAh

TAPSCAN0,

TAPSCAN1,..,

TAPSCAN34

TAP Scan Chain 0 Through 34. These are parts of the internal scan chain

subdivided according to a common CCU clock. TAP scan chains 5-9 are

unused.

01EFFFh,

03EFFFh,...,

45EFFFh

TAPFUNC0,

TAPFUNC1,..,

TAPFUNC34

TAP Function Chain 0 Through 34. One capture cycle applied to the indi-

vidual CCU scan chain clocked by the functional clock. TAP scan chains 5-9

are unused.

81FFFAh GL_ADDR[69:0] GeodeLink™ Address. Access GeodeLink request packet and data packet

control bits.

83FFFAh GL_DATA[65:0] GeodeLink Data. Access GeodeLink data.

85FFFAh PADACC[3:0] N/A.

87FFFAh PROGMISR[23:0] N/A.

8BFFFAh GL_ADDR_ACT[69:0] GeodeLink Address Action. Same data register as MB_ADDR, but no

GeodeLink transactions are triggered by the access - only by GLCP debug

action.

8DFFFAh TST_IDDQ Test IDDQ. Put the device in a mode for running IDDQ tests.

8FFFFAh REVID[7:0] Revision ID. Access device revision code.

FFFFDFh TRISTATE[0] TRI-STATE. Put device I/Os in TRI-STATE mode.

FFEFFDh BISTDR[20:0] Parallel RAM BIST. Internal one hot coded BIST Data register.

FFFFFEh IDCODE[31:0] ID Code. Boundary scan ID code - IEEE 1149.1 specification compliant.

ID code = 0x1E001003 for CS5536 companion device revision A0

ID code = 0x2E001003 for CS5536 companion device revision B0

ID code = 0x3E001003 for CS5536 companion device revision B1

ID31...ID28, ID27...ID12, ID11...ID1, ID0

Version, Part Number, Manuf. ID, 1

FFFFFFh BYPASS[0] Bypass. Boundary scan Bypass - IEEE 1149.1 spec compliant.

192 AMD Geode™ CS5536 Companion Device Data Book

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33238G

EXTEST

The EXTEST instruction accesses the boundary scan

chain around the processor and controls the pad logic such

that the boundary scan data will control the data and

enable signals for the pads. IEEE 1149.1 requires that an

all-zero instructions access the boundary scan chain. The

TAP controller catches the all-zero condition during the

Update-IR state and loads 0xFFFFE8 into the internal

instruction register.

GL_ADDR

This register contains 53 bits for a GeodeLink control

packet and the 17 bits for a GeodeLink data packet. The 17

bits for the data packet are updated if a GeodeLink read is

requested and is available for shifting out. The GL_DATA

description discusses the various conditions under which a

valid request packet is posted to the internal GeodeLink.

Note that since only one GL_ADDR request packet can be

sequenced in with JTAG, the special “read with byte

enable” 2-packet requests that GeodeLink supports cannot

be triggered. 8, 16, 32, and 64-bit reads can still be per-

formed and reads of less than 64-bit sizes generate the

appropriate byte enables at the device. As with GeodeLink

traffic, reads of less than 64 bits must be to an aligned

address, but the data will return in the GL_DATA adjusted

to 64-bit alignment (i.e., a 16-bit read to address 102h

should have address bit 1 set and data will return in bits

[31:16] of the 64-bit response). Writes of less than 64 bits

must always have 64-bit aligned addresses and should use

the byte enables in the data packet (part of the GL_ADDR

data register) to identify which specific bytes are to be writ-

ten.

GL_DATA

The data transfer rate in and out of the JTAG port is limited

to about 90% of the TCK frequency by the GLCP design.

The GLCP is designed for up to 50 MHz TCKs, but typical

TCK rates for industry interfaces are about 15 MHz. As

such, the GLCP JTAG data rate is 14 Mbits/sec or 1.6

Mbytes/sec. However, industry interface boxes will limit this

rate to about 500 kbytes/sec.

GeodeLink requests packets are triggered at these specific

moments:

•If GL_ADDR has been accessed more recently than

GL_ADDR_ACT and:

— The TYPE of the request is a read and the Update-

DR JTAG state is entered after loading the

GL_ADDR register.

— The TYPE of the request is a write and the Update-

DR JTAG state is entered after loading the GL_DATA

— The TYPE of the request is a read, the second TCK

in the Shift-DR state for shifting out the GL_DATA

(GL_DATA DR bits 1 and 0) are non-zero and the first

bit shifted out was non-zero.

•If the GL_ADDR_ACT register has been accessed more

recently than GL_ADDR and:

— The GLCP debug logic triggers the

GeodeLink_action due to a debug event occurring.

Note that if both MSR accesses from the GLIU and JTAG

are interfacing to these registers, the results will be non-

deterministic.

GL_ADDR_ACT

This is the same data register as GL_ADDR, but it disables

any GeodeLink transaction from occurring either on this

access or a following access to the GL_DATA register. Only

the GLCP debug action that triggers a GeodeLink cycle will

cause these bits to be used.

TST_IDDQ

TST_IDDQ places the chip in a mode for running IDDQ

tests (i.e., generates an internal signal to disable pull-ups

and pull downs). Also the USB transceiver is powered off.

REVID

REVID is the TAP instruction used to access the current 8-

bit revision code of the chip.

TRI-STATE

This instruction will TRI-STATE all of the tri-statable pri-

mary outputs. The DR accessed is the BYPASS register.

IDCODE

This instruction accesses the 32-bit IDCODE register dur-

ing DR access.

BYPASS

In the IEEE 1149.1 specification, shifting all 1s into the IR

must connect the 1-bit BYPASS register. The register has

no function except as a storage flip-flop. This instruction

can also allow relatively easy connection of multiple GLCP

JTAG interface chips. On a board with two GLCP chips,

TMS and TCK of each chip should be wired together and

TDO of one chip should connect to TDI of the other chip.

Note: In parallel scan mode, “input” pads provide data

into the boundary scan cells (the boundary scan

cells provide data into the core). “Cowrie” pads will

behave as dictated by the internal core flops that

normally control the pad; the output data and

enable state will be latched into the boundary scan

cells. “Cheroot” pads will drive out data as dictated

by the internal core flop associated with the pad.

AMD Geode™ CS5536 Companion Device Data Book 193

6.0Register Descriptions

This chapter provides detailed information regarding the

registers of the AMD Geode™ CS5536 companion device.

The register descriptions are documented at the module-

level and briefly summarized below.

GeodeLink™ Interface Unit (GLIU)

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

•P2D Descriptor MSRs: Accessed via RDMSR and

WRMSR instructions. (Memory base descriptor.)

•GLIU Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• IOD Descriptor MSRs: Accessed via RDMSR and

WRMSR instructions. (I/O base descriptor.)

GeodeLink PCI South Bridge (GLPCI_SB)

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

•GLPCI_SB Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• PCI Configuration Registers: Index accessed via PCI

configuration cycle.

Audio Codec 97 Controller (ACC)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions.

• ACC Native Registers: Accessed as I/O offsets from a

GLIU IOD descriptor.

IDE Controller (IDE)

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

•IDE Controller Specific MSRs: Accessed via RDMSR

and WRMSR instructions.

• IDE Controller Native Registers: Accessed as I/O offsets

from a GLIU IOD descriptor.

Universal Serial Bus Controllers

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

•This register is reserved for internal use by AMD and

should not be written to. USB Specific MSRs: Accessed

via RDMSR and WRMSR instructions.

• USB OHC Native Registers: Accessed via base

address register MSR51200008, as memory offsets.

•USB EHC Native Registers via base address register

MSR51200009, as memory offsets.

•USB Device Controller Native Registers via base

address register MSR5120000A, as memory offsets.

• USB Option Controller Native Registers via base

address register MSR5120000B, as memory offsets.

Diverse Integration Logic (DIVIL)

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

• DIVIL Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

Floppy Port

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

• Floppy Port Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

Programmable Interval Timer (PIT)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•PIT Specific MSRs: Accessed via RDMSR and WRMSR

instructions.

• PIT Native Registers: Accessed as I/O addresses.

Programmable Interrupt Controller (PIC)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•PIC Specific MSRs: Accessed via RDMSR and WRMSR

instructions.

• PIC Native Registers: Accessed as I/O addresses.

System Management Bus (SMB)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

• SMB Native Registers: Accessed via a base address

offsets.

194 AMD Geode™ CS5536 Companion Device Data Book

33238G

Keyboard Emulation Logic (KEL)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•KEL Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• KEL Native Registers: Accessed via a base address

memory offsets.

Universal Asynchronous Receiver-Transmitter (UART)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•UART/IR Controller Specific MSRs: Accessed via

RDMSR and WRMSR instructions.

• UART/IR Controller Native Registers: Accessed via

Banks 0 through 7 as I/O offsets. See MSR_LEG_IO

(MSR 51400014h) bits [22:20] and bits [18:16] for

setting base address.

Direct Memory Access (DMA)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•DMA Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• DMA Native Registers: Accessed as I/O Addresses.

Low Pin Count (LPC)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

• LPC Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

Real-Time Clock (RTC)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•RTC Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• RTC Native Registers: Accessed as I/O addresses.

General Purpose Input Output (GPIO)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•GPIO Native Registers: Accessed via a base address

offsets.

— GPIO Low/High Bank Feature Bit Registers

— GPIO Input Conditioning Function Registers

— GPIO Interrupt and PME Registers

Multi-Function General Purpose Timer (MFGPT)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•MFGPT Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

• MFGPT Native Registers: Accessed via a base address

I/O offsets.

Power Management Controller (PMC)

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•PMC Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

•ACPI Registers: Accessed via a base address register,

MSR_LBAR_ACPI (MSR 5140000Eh), as I/O offsets.

• PM Support Registers: Accessed via a base address

offsets.

Flash Controller

•Standard GeodeLink Device (GLD) MSRs: Accessed via

RDMSR and WRMSR instructions. (Shared with DIVIL.)

•Flash Controller Specific MSRs: Accessed via RDMSR

and WRMSR instructions.

•Flash Controller Native Registers: Accessed via a base

address register as either memory or I/O offsets:

— MSR_LBAR_FLSH0 (MSR 51400010h) for use with

FLASH_CS0#.

— MSR_LBAR_FLSH1 (MSR 51400011h) for use with

FLASH_CS1#.

— MSR_LBAR_FLSH2 (MSR 51400012h) for use with

FLASH_CS2#.

— MSR_LBAR_FLSH3 (MSR 51400013h) for use with

FLASH_CS3#.

GeodeLink Control Processor (GLCP)

•Standard GeodeLink™ Device (GLD) MSRs: Accessed

via RDMSR and WRMSR instructions.

• GLCP Specific MSRs: Accessed via RDMSR and

WRMSR instructions.

Note that MSRs for the Floppy Port, PIT, PIC, KEL, SMB,

UART, DMA, LPC, RTC, GPIO, MFGPT, and Flash Control-

ler devices are part of the DIVIL module (i.e., MSR

51400000h-514000FFh). Hence, the Standard GeodeLink

Device MSRs (MSR 51400000h-51400007h) are docu-

mented in the DIVIL register description and the device

Specific MSRs are documented in their appropriate regis-

ter description chapter.

The tables in this chapter use the following abbreviations:

Type Description

R/W Read/Write.

R Read from a specific address returns the

value of a specific register.

Write to the same address is to a different

WWrite.

RO Read Only.

WO Write Only.

R/W1C Read/Write 1 to clear. Writing 1 to a bit

clears it to 0. Writing 0 has no effect.

AMD Geode™ CS5536 Companion Device Data Book 195

GeodeLink™ Interface Unit Register Descriptions 33238G

6.1 GeodeLink™ Interface Unit Register Descriptions

The GeodeLink™ Interface Unit (GLIU) registers are Model

Specific Registers (MSRs) and are accessed through the

RDMSR and WRMSR instructions. The MSR address is

derived from the perspective of the CPU Core. See Section

4.2 "MSR Addressing" on page 60 for details.

The GLIU MSRs are split into the following groups:

•Standard GeodeLink Device (GLD) MSRs

•P2D Descriptor MSRs

•GLIU Specific MSRs

•IOD Descriptor MSRs

Tables 6-1 through 6-4 are GLIU register summary tables

that include reset values and page references where the bit

descriptions are provided.

Reserved (RSVD) fields do not have any meaningful stor-

age elements. They always return 0.

Table 6-1. Standard GeodeLink™ Device MSRs Summary

MSR Address Type Register Name Reset Value Reference

51010000h RO GLD Capabilities MSR

(GLIU_GLD_MSR_CAP)

00000000_005015xxh Page 198

51010001h R/W GLD Master Configuration MSR

(GLIU_GLD_MSR_CONFIG)

0000000_00000004h Page 198

51010002h R/W GLD SMI MSR (GLIU_GLD_MSR_SMI) 00000000_00000001h Page 199

51010003h R/W GLD Error MSR

(GLIU_GLD_MSR_ERROR)

00000000_00000001h Page 200

51010004h R/W GLD Power Management MSR

(GLIU_GLD_MSR_PM)

00000000_00000000h Page 202

51010005h R/W GLD Diagnostic MSR

(GLIU_GLD_MSR_DIAG)

00000000_00000000h Page 202

51010006h-

5101000Fh

R/W GLIU Reserved MSRs (GLD_MSRs_RSVD) 00000000_00000000h ---

Table 6-2. P2D Descriptor MSRs Summary

MSR Address Type Register Name Reset Value Reference

51010020h R/W P2D Base Mask Descriptor 0

(GLIU_P2D_BM0)

000000FF_FFF00000h Page 203

51010021h R/W P2D Base Mask Descriptor 1

(GLIU_P2D_BM1)

000000FF_FFF00000h Page 203

51010022h R/W P2D Base Mask Descriptor 2

(GLIU_P2D_BM2)

000000FF_FFF00000h Page 203

51010023h R/W P2D Base Mask KEL Descriptor 0

(GLIU_P2D_BMK0)

000000FF_FFF00000h Page 204

51010024h R/W P2D Base Mask KEL Descriptor 1

(GLIU_P2D_BMK1)

000000FF_FFF00000h Page 204

51010025h R/W P2D Base Mask Descriptor 3

(GLIU_P2D_BM3)

000000FF_FFF00000h Page 203

51010026h R/W P2D Base Mask Descriptor 4

(GLIU_P2D_BM4)

000000FF_FFF00000h Page 203

51010027h-

5101003Fh

R/W P2D Reserved Descriptors (P2D_RSVD) 00000000_00000000h ---

196 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ Interface Unit Register Descriptions

33238G

Table 6-3. GLIU Specific MSRs Summary

MSR Address Type Register Name Reset Value Reference

51010080h R/W Coherency (GLIU_COH) 00000000_00000000h Page 205

51010081h R/W Port Active Enable (GLIU_PAE) 00000000_0000FFFFh Page 205

51010082h R/W Arbitration (GLIU_ARB) 00000000_00000000h Page 206

51010083h R/W Asynchronous SMI (GLIU_ASMI) 00000000_00000000h Page 207

51010084h R/W Asynchronous Error (GLIU_AERR) 00000000_00000000h Page 208

51010085h R/W Debug (GLIU_DEBUG) 00000000_00000004h Page 209

51010086h RO Physical Capabilities (GLIU_PHY_CAP) 327920A0_80000005h Page 209

51010087h RO N Outstanding Response

(GLIU_NOUT_RESP)

00000000_00000000h () Page 210

51010088h RO Number of Outstanding Write Data

(GLIU_NOUT_WDATA)

00000000_00000000h Page 211

51010089h-

5101008Ah

R/W Reserved (RSVD) 00000000_00000000h ---

5101008Bh RO WHO AM I (GLIU_WHOAMI) Configuration Dependent Page 211

5101008Ch R/W Slave Disable (GLIU_SLV_DIS) 00000000_00000040h Page 211

5101008Dh-

5101008Fh

R/W Reserved (RSVD) 00000000_00000000h ---

510100A0h WO Descriptor Statistic Counter 0

(GLIU_STATISTIC_CNT0)

00000000_00000000h Page 212

510100A1h R/W Descriptor Statistic Mask 0

(GLIU_STATISTIC_MASK0)

00000000_00000000h Page 213

510100A2h R/W Descriptor Statistic Action 0

(GLIU_STATISTIC_ACTION0)

00000000_00000000h Page 214

510100A3h R/W Reserved (RSVD) 00000000_00000000h ---

510100A4h WO Descriptor Statistic Counter 1

(GLIU_STATISTIC_CNT1)

00000000_00000000h Page 212

510100A5h R/W Descriptor Statistic Mask 1

(GLIU_STATISTIC_MASK1)

00000000_00000000h Page 213

510100A6h R/W Descriptor Statistic Action 1

(GLIU_STATISTIC_ACTION1)

00000000_00000000h Page 214

510100A7h R/W Reserved (RSVD) 00000000_00000000h ---

510100A8h WO Descriptor Statistic Counter 2

(GLIU_STATISTIC_CNT2)

00000000_00000000h Page 212

510100A9h R/W Descriptor Statistic Mask 2

(GLIU_STATISTIC_MASK2)

00000000_00000000h Page 213

510100AAh R/W Descriptor Statistic Action 2

(GLIU_STATISTIC_ACTION2)

00000000_00000000h Page 214

510100ABh-

510100BFh

R/W Reserved (RSVD) 00000000_00000000h ---

510100C0h R/W Request Compare Value

(GLIU_RQ_COMP_VAL)

001FFFFF_FFFFFFFFh Page 215

510100C1h R/W Request Compare Mask

(GLIU_RQ_COMP_MASK)

00000000_00000000h Page 216

AMD Geode™ CS5536 Companion Device Data Book 197

GeodeLink™ Interface Unit Register Descriptions 33238G

510100C2h-

510100CFh

R/W Reserved (RSVD) 00000000_00000000h ---

510100D0h R/W Data Compare Value Low

(GLIU_DA_COMP_VAL_LO)

00001FFF_FFFFFFFFh Page 216

510100D1h R/W Data Compare Value High

(GLIU_DA_COMP_VAL_HI)

0000000F_FFFFFFFFh Page 217

510100D2h R/W Data Compare Mask Low

(GLIU_DA_COMP_MASK_LO)

00000000_00000000h Page 218

510100D3h R/W Data Compare Mask High

(GLIU_DA_COMP_MASK_HI)

00000000_00000000h Page 218

510100D4h-

510100DFh

R/W Reserved (RSVD) 00000000_00000000h ---

Table 6-3. GLIU Specific MSRs Summary (Continued)

MSR Address Type Register Name Reset Value Reference

Table 6-4. IOD Descriptor MSRs Summary

MSR Address Type Register Name Reset Value Reference

510100E0h R/W IOD Base Mask 0 (GLIU_IOD_BM0);

Reserved for ATA; Defaults to 1Fx16.

60000000_1F0FFFF0h Page 219

510100E1h R/W IOD Base Mask 1 (GLIU_IOD_BM1) 000000FF_FFF00000h Page 219

510100E2h R/W IOD Base Mask 2 (GLIU_IOD_BM2) 000000FF_FFF00000h Page 219

510100E3h R/W IOD Base Mask 3 (GLIU_IOD_BM3) 000000FF_FFF00000h Page 219

510100E4h R/W IOD Base Mask 4 (GLIU_IOD_BM4) 000000FF_FFF00000h Page 219

510100E5h R/W IOD Base Mask 5 (GLIU_IOD_BM5) 000000FF_FFF00000h Page 219

510100E6h R/W IOD Base Mask 6 (GLIU_IOD_BM6) 000000FF_FFF00000h Page 219

510100E7h R/W IOD Base Mask 7 (GLIU_IOD_BM7) 000000FF_FFF00000h Page 219

510100E8h R/W IOD Base Mask 8 (GLIU_IOD_BM8) 000000FF_FFF00000h Page 219

510100E9h R/W IOD Base Mask 9 (GLIU_IOD_BM9) 000000FF_FFF00000h Page 219

510100EAh R/W IOD Swiss Cheese 0 (GLIU_IOD_SC0) 60000000_403003F0h Page 220

510100EBh R/W IOD Swiss Cheese 1 (GLIU_IOD_SC1) 00000000_00000000h Page 220

510100ECh R/W IOD Swiss Cheese 2 (GLIU_IOD_SC2) 00000000_00000000h Page 220

510100EDh R/W IOD Swiss Cheese 3 (GLIU_IOD_SC3) 00000000_00000000h Page 220

510100EEh R/W IOD Swiss Cheese 4 (GLIU_IOD_SC4) 00000000_00000000h Page 220

510100EFh R/W IOD Swiss Cheese 5 (GLIU_IOD_SC5) 00000000_00000000h Page 220

510100F0h R/W IOD Swiss Cheese 6 (GLIU_IOD_SC6) 00000000_00000000h Page 220

510100F1h R/W IOD Swiss Cheese 7 (GLIU_IOD_SC7) 00000000_00000000h Page 220

510100F2h-

510100FFh

R/W Reserved (RSVD) 00000000_00000000h ---

198 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.1.1 Standard GeodeLink™ Device (GLD) MSRs

6.1.1.1 GLD Capabilities MSR (GLIU_GLD_MSR_CAP)

6.1.1.2 GLD Master Configuration MSR (GLIU_GLD_MSR_CONFIG)

MSR Address 51010000h

Type RO

Reset Value 00000000_005015xxh

GLIU_GLD_MSR_CAP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD DEV_ID REV_ID

GLIU_GLD_MSR_CAP Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Reads return 0.

23:8 DEV_ID Device ID. Identifies module.

7:0 REV_ID Revision ID. Identifies module revision. See AMD Geode™ CS5536 Companion Device

Specification Update for value.

MSR Address 51010001h

Type R /W

Reset Value 0000000_00000004h

GLIU_GLD_MSR_CONFIG Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD SUBP

GLD_MSR_CONFIG Bit Descriptions

Bit Name Description

63:3 RSVD Reserved. Write as read.

2:0 SUBP Subtractive Port. For all negative decode requests.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

Note: The reset value of this register should not be changed.

AMD Geode™ CS5536 Companion Device Data Book 199

GeodeLink™ Interface Unit Register Descriptions 33238G

6.1.1.3 GLD SMI MSR (GLIU_GLD_MSR_SMI)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 0. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.3 "MSR Address 2: SMI Control" on page 74 for

further SMI and ASMI generation details.)

MSR Address 51010002h

Type R /W

Reset Value 00000000_00000001h

GLIU_GLD_MSR_SMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

STATCNT2_ASMI_FLAG

STATCNT1_ASMI_FLAG

STATCNT0_ASMI_FLAG

SSMI_FLAG

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD

STATCNT2_ASMI_EN

STATCNT1_ASMI_EN

STATCNT0_ASMI_EN

SSMI_EN

GLIU_GLD_MSR_SMI Bit Descriptions

Bit Name Description

63:36 RSVD Reserved. Write as read.

35 STATCNT2_

ASMI_FLAG

Statistic Counter 2 ASMI Flag. If high, records that an ASMI was generated due to a

Statistic Counter 2 (MSR 510100A8h) event. Write 1 to clear; writing 0 has no effect.

STATCNT2_ASMI_EN (bit 3) must be low to generate ASMI and set flag.

34 STATCNT1_

ASMI_FLAG

Statistic Counter 1 ASMI Flag. If high, records that an ASMI was generated due to a

Statistic Counter 1 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect.

STATCNT1_ASMI_EN (bit 2) must be low to generate ASMI and set flag.

33 STATCNT0_

ASMI_FLAG

Statistic Counter 0 SMI Flag. If high, records that an ASMI was generated due to a Sta-

tistic Counter 0 (MSR 510100A0h) event. Write 1 to clear; writing 0 has no effect.

STATCNT0_ASMI_EN (bit 1) must be low to generate ASMI and set flag.

32 SSMI_FLAG SSMI Flag. If high, records that an SSMI was generated due to a received event. Event

sources are:

•Illegal request type to GLIU (Port 0), meaning anything other than MSR read/write,

debug request, and null.

•A self-referencing packet (i.e., a packet sent to the GLIU that finds its destination port

is the source port).

•The destination of the packet is to a port where the GLIU slave for that port has been

disabled.

•Trap on a descriptor with device port set to 0. This is the typical operational use of this

bit. The data returned with such a trap is the value 0.

Write 1 to clear; writing 0 has no effect. SSMI_EN (bit 0) must be low to generate SSMI

and set flag.

200 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ Interface Unit Register Descriptions

33238G

6.1.1.4 GLD Error MSR (GLIU_GLD_MSR_ERROR)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 0. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.4 "MSR Address 3: Error Control" on page 78

for further details.)

31:4 RSVD Reserved. Write as read.

3 STATCNT2_

ASMI_EN

Statistic Counter 2 ASMI Enable. Write 0 to enable STATCNT2_ASMI_FLAG (bit 35)

and to allow a Statistic Counter 2 (MSR 510100A8h) event to generate an ASMI.

2 STATCNT1_

ASMI_EN

Statistic Counter 1 ASMI Enable. Write 0 to enable STATCNT1_ASMI_FLAG (bit 34)

and to allow a Statistic Counter 1 (MSR 510100A4h) event to generate an ASMI.

1 STATCNT0_

ASMI_EN

Statistic Counter 0 ASMI Enable. Write 0 to enable STATCNT0_ASMI_FLAG (bit 33)

and to allow a Statistic Counter 0 (MSR 510100A0h) event to generate an ASMI.

0 SSMI_EN SSMI Enable. Write 0 to enable SSMI_FLAG (bit 32) and to allow a received SSMI event

to generate an SSMI. (See bit 32 description for SSMI event sources.)

GLIU_GLD_MSR_SMI Bit Descriptions (Continued)

Bit Name Description

MSR Address 51010003h

Type R /W

Reset Value 00000000_00000001h

GLIU_GLD_MSR_ERROR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

DACMP_ERR_FLAG

RSVD

RQCOMP_ERR_FLAG

RSVD

STATCNT2_ERR_FLAG

STATCNT1_ERR_FLAG

STATCNT0_ERR_FLAG

SSMI_ERR_FLAG

UNEXP_ADD_ERR_FLAG

UNEXP_TYPE_ERR_FLAG

313029282726252423222120191817161514131211109876543210

RSVD

DACMP_ERR_EN

RSVD

RQCOMP_ERR_EN

RSVD

STATCNT2_ERR_EN

STATCNT1_ERR_EN

STATCNT0_ERR_EN

SSMI_ERR_EN

UNEXP_ADD_ERR_EN

UNEXP_TYPE_ERR_EN

GLIU_GLD_MSR_ERROR Bit Descriptions

Bit Name Description

63:44 RSVD Reserved. Write as read.

43 DACOMP_

ERR_FLAG

Data Comparator Error Flag. If high, records that an ERR was generated due to a Data

Comparator (DA_COMP_VAL_LO / DA_COMP_VAL_HI, MSR 510100D0h / 510100D1h)

event. Write 1 to clear; writing 0 has no effect. DACOMP_ERR_EN (bit 11) must be low to

generate ERR and set flag.

42:40 RSVD Reserved. Write as read.

AMD Geode™ CS5536 Companion Device Data Book 201

GeodeLink™ Interface Unit Register Descriptions 33238G

39 RQCOMP_

ERR_FLAG

Request Comparator Error Flag. If high, records that an ERR was generated due to a

Request Comparator 0 (RQ_COMP_VAL, MSR 510100C0h) event. Write 1 to clear; writing

0 has no effect. RQCOMP_ERR_EN (bit 7) must be low to generate ERR and set flag.

38 RSVD Reserved. Write as read.

37 STATCNT2_

ERR_FLAG

Statistic Counter 2 Error Flag. If high, records that an ERR was generated due to a Sta-

tistic Counter 2 (MSR 510100A8h) event. Write 1 to clear; writing 0 has no effect.

STATCNT2_ERR_EN (bit 5) must be low to generate ERR and set flag.

36 STATCNT1_

ERR_FLAG

Statistic Counter 1 Error Flag. If high, records that an ERR was generated due to a Sta-

tistic Counter 1 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect.

STATCNT2_ERR_EN (bit 4) must be low to generate ERR and set flag.

35 STATCNT0_

ERR_FLAG

Statistic Counter 0 Error Flag. If high, records that an ERR was generated due to a Sta-

tistic Counter 0 (MSR 510100A4h) event. Write 1 to clear; writing 0 has no effect.

STATCNT0_ERR_EN (bit 3) must be low to generate ERR and set flag.

34 SSMI_ERR_

FLAG

SSMI Error Flag. If high, records that an ERR was generated due an unhandled SSMI

(synchronous error). Write 1 to clear; writing 0 has no effect. SSMI_ERR_EN (bit 2) must

be low to generate ERR and set flag. (Note 1)

33 UNEXP_ADD_

ERR_FLAG

Unexpected Address Error Flag. If high, records that an ERR was generated due an

unexpected address (synchronous error). Write 1 to clear; writing 0 has no effect.

UNEXP_ADD_ERR_EN (bit 1) must be low to generate ERR and set flag. (Note 1)

32 UNEXP_TYPE

_ERR_FLAG

Unexpected Type Error Flag. If high, records that an ERR was generated due an unex-

pected type (synchronous error). Write 1 to clear; writing 0 has no effect.

UNEXP_TYPE_ERR_EN (bit 0) must be low to generate ERR and set flag. (Note 1)

31:12 RSVD Reserved. Write as read.

11 DACOMP_

ERR_EN

Data Comparator Error Enable. Write 0 to enable DACOMP_ERR_FLAG (bit 43) and to

allow a Data Comparator (DA_COMP_VAL_LO / DA_COMP_VAL_HI, MSR 510100D0h /

510100D1h) event to generate an ERR and set flag.

10:8 RSVD Reserved. Write as read.

7RQCOMP_

ERR_EN

Request Comparator Error Enable. Write 0 to enable RQCOMP_ERR_FLAG (bit 39) and

to allow a Request Comparator (RQ_COMP_VAL, MSR 510100C0h) event to generate an

ERR.

6 RSVD Reserved. Write as read.

5 STATCNT2_

ERR_EN

Statistic Counter 2 Error Enable. Write 0 to enable STATCNT2_ERR_FLAG (bit 37) and

to allow a Statistic Counter 2 (MSR 510100A8h) event to generate an ERR.

4 STATCNT1_

ERR_EN

Statistic Counter 1 Error Enable. Write 0 to enable STATCNT1_ERR_FLAG (bit 36) and

to allow a Statistic Counter 1 (MSR 510100A4h) event to generate an ERR.

3 STATCNT0_

ERR_EN

Statistic Counter 0 Error Enable. Write 0 to enable STATCNT0_ERR_FLAG (bit 35) and

to allow a Statistic Counter 0 (MSR 510100A0h) event to generate an ERR.

2 SSMI_ERR_

SSMI Error Enable. Write 0 to enable SSMI_ERR_FLAG (bit 34) and to allow the unhan-

dled SSMI (synchronous error) event to generate an ERR.

1 UNEXP_ADD_

ERR_EN

Unexpected Address Error Enable. Write 0 to enable UNEXP_ADD_ERR_FLAG (bit 33)

and to allow the unexpected address (synchronous error) event to generate an ERR.

0 UNEXP_TYPE

_ERR_EN

Unexpected Type Error Enable. Write 0 to enable UNEXP_TYPE_ERR_FLAG (bit 32)

and to allow the unexpected type (synchronous error) event to generate an ERR.

Note 1. These are synchronous errors, that is, they do not result in the assertion of the GeodeLink ERR signal but instead

set the Exception bit in the response packet.

GLIU_GLD_MSR_ERROR Bit Descriptions (Continued)

Bit Name Description

202 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.1.1.5 GLD Power Management MSR (GLIU_GLD_MSR_PM)

6.1.1.6 GLD Diagnostic MSR (GLIU_GLD_MSR_DIAG)

This register is reserved for internal use by AMD and should not be written to.

MSR Address 51010004h

Type R /W

Reset Value 00000000_00000000h

GLIU_GLD_MSR_PM Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

PMODE1

PMODE0

GLIU_GLD_MSR_PM Bit Descriptions

Bit Name Description

63:4 RSVD Reserved. Write as read.

3:2 PMODE1 Power Mode 1. Statistics and Time Slice Counters.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

1:0 PMODE0 Power Mode 0. Online GLIU logic.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

MSR Address 51010005h

Type R /W

Reset Value 00000000_00000000h

AMD Geode™ CS5536 Companion Device Data Book 203

GeodeLink™ Interface Unit Register Descriptions 33238G

6.1.2 P2D Descriptor MSRs

6.1.2.1 P2D Base Mask Descriptors (GLIU_P2D_BM[x])

P2D Base Mask Descriptor 0 (GLIU_P2D_BM0)

P2D Base Mask Descriptor 1 (GLIU_P2D_BM1)

P2D Base Mask Descriptor 2 (GLIU_P2D_BM2)

P2D Base Mask Descriptor 3 (GLIU_P2D_BM3)

P2D Base Mask Descriptor 4 (GLIU_P2D_BM4)

These registers set up the Physical To Device Base Mask descriptors for determining an address hit.

MSR Address 51010020h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 51010021h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 51010022h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 51010025h

Type R/W

Reset Value 000000FF_FFF00000h

MSR Address 51010026h

Type R/W

Reset Value 000000FF_FFF00000h

GLIU_P2D_BM[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

PDID1_BM

PCMP_BIZ_BM

RSVD PBASE_BM

313029282726252423222120191817161514131211109876543210

PBASE_BM PMASK_BM

GLIU_P2D_BM[x] Bit Descriptions

Bit Name Description

63:61 PDID_BM Physical Descriptor Destination ID. These bits define which port to route the request to

if it is a hit based on the other settings in this register.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

60 PCMP_BIZ_BM Physical Compare BIZZARO Flag.

0: Consider only transactions whose BIZZARO flag is low as a potentially valid address

hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or

I/O.

1: Consider only transactions whose BIZZARO flag is high as a potentially valid address

hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or

Halt cycle

59:40 RSVD Reserved. Write as read.

39:20 PBASE_BM Physical Memory Address Base. These bits form the matching value against which the

masked value of the physical address bits [31:12] are directly compared. If a match is

found, then a hit is declared, depending on the setting of the BIZZARO flag comparator.

19:0 PMASK_BM Physical Memory Address Mask. These bits are used to mask physical address bits

[31:12] for the purposes of this hit detection.

204 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ Interface Unit Register Descriptions

33238G

6.1.2.2 P2D Base Mask KEL Descriptors (GLIU_P2D_BMK[x])

P2D Base Mask KEL Descriptor 0 (GLIU_P2D_BMK0) P2D Base Mask KEL Descriptor 1 (GLIU_P2D_BMK1)

This is a special version of a P2D_BM descriptor to support routing the USB Keyboard Emulation Logic (KEL) native regis-

ters to the default port. The default port device on the CS5536 companion device contains the KEL.

MSR Address 51010023h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 51010024h

Type R/W

Reset Value 000000FF_FFF00000h

GLIU_P2D_BMK[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

PDID1_BMK

PCMP_BIZ_BMK

RSVD PBASE_BMK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBASE_BMK PMASK_BMK

GLIU_P2D_BMK[x] Bit Descriptions

Bit Name Description

63:61 PDID1_BMK Physical Descriptor Destination ID. Descriptor Destination ID. These bits define

which port to route the request to if it is a hit based on the other settings in this register.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

60 PCMP_BIZ_BMK Physical Compare BIZZARO Flag. If set, bit 8 of the address must be low for a hit on

this descriptor.

59:40 RSVD Reserved. Write as read.

39:20 PBASE_BMK Physical Memory Address Base.These bits form the matching value against which

the masked value of the physical address bits [31:12] are directly compared. If a match

is found, then a hit is declared, depending on the setting of the BIZZARO flag compara-

tor.

19:0 PMASK_BMK Physical Memory Address Mask.These bits are used to mask physical address bits

[31:12] for the purposes of this hit detection.

AMD Geode™ CS5536 Companion Device Data Book 205

GeodeLink™ Interface Unit Register Descriptions 33238G

6.1.3 GLIU Specific MSRs

6.1.3.1 Coherency (GLIU_COH)

6.1.3.2 Port Active Enable (GLIU_PAE)

MSR Address 51010080h

Type R /W

Reset Value 00000000_00000000h

GLIU_COH Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD COHP

GLIU_COH Bit Descriptions

Bit Name Description

63:3 RSVD Reserved. Write as read.

2:0 COHP Coherent Device Port. The port that coherent snoops are routed to. If the coherent device

is on the other side of a bridge, the COHP points to the bridge.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

MSR Address 51010081h

Type R /W

Reset Value 00000000_0000FFFFh

GLIU_PAE Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD PAE0 PAE7 PAE6 PAE5 PAE4 PAE3 PAE2 PAE1

GLIU_PAE Bit Descriptions

Bit Name Description

63:16 RSVD Reserved. Write as read.

15:14 PAE0 Port Active Enable for Port 0 (GLIU).

00: OFF - Master transactions are disabled.

01: LOW - Master transactions limited to one outstanding transaction.

10: Reserved.

11: ON - Master transactions enabled with no limitations.

13:12 PAE7 Port Active Enable for Port 7 (GLCP). See bits [15:14] for decode.

11:10 PAE6 Reserved. Write as read.

9:8 PAE5 Port Active Enable for Port 5 (ACC). See bits [15:14] for decode.

7:6 PAE4 Port Active Enable for Port 4 (DD). See bits [15:14] for decode.

206 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.1.3.3 Arbitration (GLIU_ARB)

5:4 PAE3 Port Active Enable for Port 3 (IDE). See bits [15:14] for decode.

3:2 PAE2 Port Active Enable for Port 2 (USB). See bits [15:14] for decode.

1:0 PAE1 Port Active Enable for Port 1 (GLPCI_SB).

GLIU_PAE Bit Descriptions (Continued)

Bit Name Description

MSR Address 51010082h

Type R /W

Reset Value 00000000_00000000h

GLIU_ARB Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

PIPE_DIS

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

GLIU_ARB Bit Descriptions

Bit Name Description

63 RSVD Reserved. Write as read.

62 PIPE_DIS Pipelined Arbitration Disabled.

0: Pipelined arbitration enabled and the GLIU is not limited to one outstanding transaction.

1: Limit the entire GLIU to one outstanding transaction.

61:0 RSVD Reserved. Write as read.

AMD Geode™ CS5536 Companion Device Data Book 207

GeodeLink™ Interface Unit Register Descriptions 33238G

6.1.3.4 Asynchronous SMI (GLIU_ASMI)

ASMI is a condensed version of the Port ASMI signals. The EN bits ([15:8]) can be used to prevent a device from issuing an

ASMI. A write of 1 to the EN bit disables the device’s ASMI. The FLAG bits ([7:0]) are status bits. If high, an ASMI was gen-

erated due to the associated device. (See Section 4.1.4 "ASMI and Error" on page 57 for further details.)

MSR Address 51010083h

Type R /W

Reset Value 00000000_00000000h

GLIU_ASMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

P7_ASMI_EN

RSVD

P5_ASMI_EN

P4_ASMI_EN

P3_ASMI_EN

P2_ASMI_EN

P1_ASMI_EN

P0_ASMI_EN

P7_ASMI_FLAG

RSVD

P5_ASMI_FLAG

P4_ASMI_FLAG

P3_ASMI_FLAG

P2_ASMI_FLAG

P1_ASMI_FLAG

P0_ASMI_FLAG

GLIU_ASMI Bit Descriptions

Bit Name Description

63:16 RSVD Reserved.

15 P7_ASMI_EN Port 7 (GLCP) Asynchronous SMI Enable.

14 RSVD Reserved.

13 P5_ASMI_EN Port 5 (ACC) Asynchronous SMI Enable.

12 P4_ASMI_EN Port 4 (DD) Asynchronous SMI Enable.

11 P3_ASMI_EN Port 3 (IDE) Asynchronous SMI Enable.

10 P2_ASMI_EN Port 2 (USB) Asynchronous SMI Enable.

9 P1_ASMI_EN Port 1 (GLPCI_SB) Asynchronous SMI Enable.

8 P0_ASMI_EN Port 0 (GLIU) Asynchronous SMI Enable.

7 P7_ASMI_FLAG (RO) Port 7 (GLCP) Asynchronous SMI Flag (Read Only).

6 RSVD Reserved.

5 P5_ASMI_FLAG (RO) Port 5 (ACC) Asynchronous SMI Flag (Read Only).

4 P4_ASMI_FLAG (RO) Port 4 (DD) Asynchronous SMI Flag (Read Only).

3 P3_ASMI_FLAG (RO) Port 3 (IDE) Asynchronous SMI Flag (Read Only).

2 P2_ASMI_FLAG (RO) Port 2 (USB) Asynchronous SMI Flag (Read Only).

1 P1_ASMI_FLAG (RO) Port 1 (GLPCI_SB) Asynchronous SMI Flag (Read Only).

0 P0_ASMI_FLAG (RO) Port 0 (GLIU) Asynchronous SMI Flag (Read Only).

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6.1.3.5 Asynchronous Error (GLIU_AERR)

ERR is a condensed version of the port (asynchronous) ERR signals. The EN bits ([15:8]) can be used to prevent a device

from issuing an ERR. A write of 1 to the EN bit disables the device’s ERR. The FLAG bits ([7:0]) are status bits. If high, an

ERR was generated due to the associated device. (See Section 4.1.4 "ASMI and Error" on page 57 for further details.)

MSR Address 51010084h

Type R /W

Reset Value 00000000_00000000h

GLIU_AERR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

P7_AERR_EN

RSVD

P5_AERR_EN

P4_AERR_EN

P3_AERR_EN

P2_AERR_EN

P1_AERR_EN

P0_AERR_EN

P7_AERR_FLAG

RSVD

P5_AERR_FLAG

P4_AERR_FLAG

P3_AERR_FLAG

P2_AERR_FLAG

P1_AERR_FLAG

P0_AERR_FLAG

GLIU_AERR Bit Descriptions

Bit Name Description

63:16 RSVD Reserved.

15 P7_AERR_EN Port 7 (GLCP) Asynchronous Error Enable.

14 RSVD Reserved.

13 P5_AERR_EN Port 5 (ACC) Asynchronous Error Enable.

12 P4_AERR_EN Port 4 (DD) Asynchronous Error Enable.

11 P3_AERR_EN Port 3 (IDE) Asynchronous Error Enable.

10 P2_AERR_EN Port 2 (USB) Asynchronous Error Enable.

9 P1_AERR_EN Port 1 (GLPCI_SB) Asynchronous Error Enable.

8 P0_AERR_EN Port 0 (GLIU) Asynchronous Error Enable.

7 P7_AERR_FLAG (RO) Port 7 (GLCP) Asynchronous Error Flag (Read Only).

6 RSVD Reserved.

5 P5_AERR_FLAG (RO) Port 5 (ACC) Asynchronous Error Flag (Read Only).

4 P4_AERR_FLAG (RO) Port 4 (DD) Asynchronous Error Flag (Read Only).

3 P3_AERR_FLAG (RO) Port 3 (IDE) Asynchronous Error Flag (Read Only).

2 P2_AERR_FLAG (RO) Port 2 (USB) Asynchronous Error Flag (Read Only).

1 P1_AERR_FLAG (RO) Port 1 (GLPCI_SB) Asynchronous Error Flag (Read Only).

0 P0_AERR_FLAG (RO) Port 0 (GLIU) Asynchronous Error Flag (Read Only).

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6.1.3.6 Debug (GLIU_DEBUG)

6.1.3.7 Physical Capabilities (GLIU_PHY_CAP)

This register provides the resources available in the CS5536 companion device.

MSR Address 51010085h

Type R /W

Reset Value 00000000_00000004h

GLIU_DEBUG Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

GLIU_DEBUG Bit Descriptions

Bit Name Description

63:0 RSVD Reserved. Write as read.

MSR Address 51010086h

Type RO

Reset Value 327920A0_80000005h

GLIU_PHY_CAP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

NSTAT_CNT

NDBG_DA_CMP

NDBG_RQ_CMP

NPORTS NCOH NIOD_SC NIOD_BM NP2D_BMK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NP2D_BMK

NP2D_SC NP2D_RO NP2D_R NP2D_BMO NP2D_BM

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6.1.3.8 N Outstanding Response (GLIU_NOUT_RESP)

GLIU_PHY_CAP Bit Descriptions

Bit Name Description

63 RSVD Reserved. Returns 0.

62:60 NSTAT_CNT Number Of Statistic Counters. Provides the number of available Statistic Counters.

59:57 NDBG_DA_CMP Number Of Data Comparators. Provides the number of available Data Compara-

tors.

56:54 NDBG_RQ_CMP Number Of Request Comparators. Provides the number of available Request Com-

parators.

53:51 NPORTS Number of Ports on the GLIU. Provides the number of available ports on the GLIU.

50:48 NCOH Number of Coherent Devices. Provides the number of available Coherent Devices.

47:42 NIOD_SC Number of IOD_SC Descriptors. Provides the number of available IOD_SC

Descriptors.

41:36 NIOD_BM Number of IOD_BM Descriptors. Provides the number of available IOD_BM

Descriptors.

35:30 NP2D_BMK Number of P2D_BMK Descriptors. Provides the number of available P2D_BMK

Descriptors.

29:24 NP2D_SC Number of P2D_SC Descriptors. Provides the number of available P2D_SC

Descriptors

23:18 NP2D_RO Number of P2D_RO Descriptors. Provides the number of available P2D_RO

Descriptors.

17:12 NP2D_R Number of P2D_R Descriptors. Provides the number of available P2D_R ‘Descrip-

tors.

11:6 NP2D_BMO Number of P2D_BMO Descriptors. Provides the number of available P2D_BMO

Descriptors.

5:0 NP2D_BM Number of P2D_BM Descriptors. Provides the number of available P2D_BM

Descriptors.

MSR Address 51010087h

Type RO

Reset Value 00000000_00000000h (Note 1)

Note 1. Even if the reset value of this register is 0, read it back 00000000_00000100h.

GLIU_NOUT_RESP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD

GLIU_NOUT_RESP Bit Descriptions

Bit Name Description

63:0 RSVD Reserved. Returns 0.

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6.1.3.9 Number of Outstanding Write Data (GLIU_NOUT_WDATA)

6.1.3.10 WHO AM I (GLIU_WHOAMI)

6.1.3.11 Slave Disable (GLIU_SLV_DIS)

MSR Address 51010088h

Type RO

Reset Value 00000000_00000000h

GLIU_NOUT_WDATA Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

GLIU_NOUT_WDATA Bit Descriptions

Bit Name Description

63:0 RSVD Reserved. Returns 0.

MSR Address 5101008Bh

Type RO

Reset Value Configuration Dependent

GLIU_WHOAMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD

GLIU_WHOAMI Bit Descriptions

Bit Name Description

63:0 RSVD Reserved. Returns 0.

MSR Address 5101008Ch

Type R /W

Reset Value 00000000_00000040h

GLIU_SLV_DIS Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD

GLIU_SLV_DIS Bit Descriptions

Bit Name Description

63:0 RSVD Reserved. Write as read.

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6.1.3.12 Descriptor Statistic Counters (GLIU_STATISTIC_CNT[x])

Descriptor Statistic Counter 0

(GLIU_STATISTIC_CNT0)

Descriptor Statistic Counter 1

(GLIU_STATISTIC_CNT1)

Descriptor Statistic Counter 2

(GLIU_STATISTIC_CNT2)

These registers work in conjunction with the GLIU_STATISTIC_MASK[x] and the GLIU_STATISTIC_ACTION[x] registers.

The counters count ‘hits’ on the P2D and IOD descriptors. The counter behaves as setup in the

GLIU_STATISTIC_ACTION[x] register.

MSR Address 510100A0h

Type WO

Reset Value 00000000_00000000h

MSR Address 510100A4h

Type WO

Reset Value 00000000_00000000h

MSR Address 510100A8h

Type WO

Reset Value 00000000_00000000h

GLIU_STATISTIC_CNT[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

LOAD_VAL

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT

GLIU_STATISTIC_CNT[x] Bit Descriptions

Bit Name Description

63:32 LOAD_VAL Counter Load Value. A value loaded here is used as the initial Statistics Counter value

when a LOAD action occurs or is commanded.

31:0 CNT Counter Value. These bits provide the current counter value when read.

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6.1.3.13 Descriptor Statistic Mask (GLIU_STATISTIC_MASK[x])

Descriptor Statistic Mask 0 (GLIU_STATISTIC_MASK0)

Descriptor Statistic Mask 1 (GLIU_STATISTIC_MASK1)

Descriptor Statistic Mask 2 (GLIU_STATISTIC_MASK2)

MSR Address 510100A1h

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100A5h

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100A9h

Type R /W

Reset Value 00000000_00000000h

GLIU_STATISTIC_MASK[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

IOD_MASK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P2D_MASK

GLIU_STATISTIC_MASK[x] Bit Descriptions

Bit Name Description

63:32 IOD_MASK Mask for Hits to each IOD. Hits are determined after the request is arbitrated. A hit is

determined by the following logical equation:

hit = |(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] &

RQ_DESC_HIT[n-1:0] && is_mem)

31:0 P2D_MASK Mask for Hits to each P2D. A hit is determined by the following logical equation:

hit = |(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] &

RQ_DESC_HIT[n-1:0] && is_mem)

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6.1.3.14 Descriptor Statistic Action (GLIU_STATISTIC_ACTION[x])

Descriptor Statistic Action 0 (GLIU_STATISTIC_ACTION0)

Descriptor Statistic Action 1 (GLIU_STATISTIC_ACTION1)

Descriptor Statistic Action 2 (GLIU_STATISTIC_ACTION2)

MSR Address 510100A2h

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100A6h

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100AAh

Type R /W

Reset Value 00000000_00000000h

GLIU_STATISTIC_ACTION[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD PREDIV

WRAP

ZERO_ERR

ZERO_SMI

ALWAYS_DEC

HIT_ERR

HIT_SMI

HIT_DEC

HIT_LDEN

GLIU_STATISTIC_ACTION[x] Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Write as read.

23:8 PREDIV Pre-divider used for ALWAYS_DEC. The pre-divider is free running and extends the

depth of the counter.

7WRAP Decrement Counter Beyond Zero and Wrap.

0: Disable wrap; counter stops when it reaches zero.

1: Enable wrap; counter decrements through 0 to all ones.

6 ZERO_ERR Assert AERR on Cnt = 0. Assert AERR when STATISTIC_CNT[x] = 0.

0: Disable.

1: Enable.

5 ZERO_SMI Assert ASMI on Cnt = 0. Assert ASMI when STATISTIC_CNT[x] = 0.

0: Disable.

1: Enable.

4 ALWAYS_DEC Always Decrement Counter. If enabled, the counter decrements on every memory

clock subject to the prescaler value PREDIV (bits [23:8]). Decrementing continues unless

loading is occurring due to another action, or if the counter reaches zero and WRAP (bit

7) is disabled.

0: Disable.

1: Enable.

3HIT_ERR Assert AERR on Descriptor Hit. This bit causes an asynchronous error to be generated

when a matching descriptor hit occurs, or not. The descriptor hits are ANDed with the

masks and then all ORed together.

0: Disable.

1: Enable.

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6.1.3.15 Request Compare Value (GLIU_RQ_COMP_VAL)

The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is

determined by hit = (RQ_IN & RQ_COMP_MASK) == RQ_COMP_VAL). A hit can trigger the RQ_COMP error sources

when they are enabled. The value is compared only after the packet is arbitrated.

2HIT_SMI Assert ASMI on Descriptor Hit. This bit causes an ASMI to be generated when a

matching descriptor hit occurs, or not. The descriptor hits are ANDed with the masks and

then all ORed together.

0: Disable.

1: Enable.

1HIT_DEC Decrement Counter on Descriptor Hit. This bit causes the associated counter to dec-

rement when a matching descriptor hit occurs, or not.The descriptor hits are ANDed with

the masks and then all ORed together.

0: Disable.

1: Enable.

0HIT_LDEN Load Counter on Descriptor Hit. This bit causes the associated counter to reload its

LOAD_VAL when a matching descriptor hit occurs, or not.The descriptor hits are ANDed

with the masks and then all ORed together.

0: Disable.

1: Enable.

MSR Address 510100C0h

Type R /W

Reset Value 001FFFFF_FFFFFFFFh

GLIU_STATISTIC_ACTION[x] Bit Descriptions (Continued)

Bit Name Description

GLIU_RQ_COMP_VAL Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD RQ_COMPVAL

313029282726252423222120191817161514131211109876543210

RQ_COMPVAL

GLIU_RQ_COMP_VAL Bit Descriptions

Bit Name Description

63:53 RSVD Reserved. Write as read.

52:0 RQ_COMPVAL Request Packet Value. This is the value compared against the logical bit-wise AND of

the incoming request packet and the RQ_COMP_MASK in order to determine a hit.

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6.1.3.16 Request Compare Mask (GLIU_RQ_COMP_MASK)

The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is

determined by hit = (RQ_IN & RQ_COMP_MASK) == RQ_COMP_VAL). A hit can trigger the RQ_COMP error sources

when they are enabled. The value is compared only after the packet is arbitrated.

6.1.3.17 Data Compare Value Low (GLIU_DA_COMP_VAL_LO)

The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-

mined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_CMP error sources when they

are enabled. The value is compared only after the packet is arbitrated.

MSR Address 510100C1h

Type R /W

Reset Value 00000000_00000000h

GLIU_RQ_COMP_MASK Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD RQ_COMPMASK

313029282726252423222120191817161514131211109876543210

RQ_COMPMASK

GLIU_RQ_COMP_MASK Bit Descriptions

Bit Name Description

63:53 RSVD Reserved. Write as read.

52:0 RQ_COMPMASK Request Packet Mask. This field is bit-wise logically ANDed with the incoming

Request Packet before it is compared to the RQ_COMPVAL.

MSR Address 510100D0h

Type R /W

Reset Value 00001FFF_FFFFFFFFh

GLIU_DA_COMP_VAL_LO Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD DALO_COMPVAL

313029282726252423222120191817161514131211109876543210

DALO_COMPVAL

GLIU_DA_COMP_VAL_LO Bit Descriptions

Bit Name Description

63:45 RSVD Reserved. Write as read.

44:0 DALO_COMPVAL Data Packet Compare Value [44:0]. This field forms the lower portion of the data

value that is compared to the logical bit-wise AND of the incoming data value and the

data value compare mask in order to determine a hit. The “HI” and “LO” portions of the

incoming data, the compare value, and the compare mask, are assembled into com-

plete bit patterns before these operations occur.

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6.1.3.18 Data Compare Value High (GLIU_DA_COMP_VAL_HI)

The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-

mined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_CMP error sources when they

are enabled. The value is compared only after the packet is arbitrated.

MSR Address 510100D1h

Type R /W

Reset Value 0000000F_FFFFFFFFh

GLIU_DA_COMP_VAL_HI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

DAHI_COMPVAL

313029282726252423222120191817161514131211109876543210

DAHI_COMPVAL

GLIU_DA_COMP_VAL_HI Bit Descriptions

Bit Name Description

63:36 RSVD Reserved. Write as read.

35:0 DAHI_

COMPVAL

DA Packet Compare Value [80:45]. This field forms the upper portion of the data

value that is compared to the logical bit-wise AND of the incoming data value and the

data value compare mask in order to determine a hit. The “HI” and “LO” portions of the

incoming data, the compare value, and the compare mask, are assembled into com-

plete bit patterns before these operations occur.

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6.1.3.19 Data Compare Mask Low (GLIU_DA_COMP_MASK_LO)

The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-

mined by hit = (DA_IN & DA_COMP_MASK) == DA_COMP_VAL). A hit can trigger the DA_COMP error sources when they

are enabled. The value is compared only after the packet is arbitrated.

6.1.3.20 Data Compare Mask High (GLIU_DA_COMP_MASK_HI)

MSR Address 510100D2h

Type R /W

Reset Value 00000000_00000000h

GLIU_DA_COMP_MASK_LO Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD DALO_COMPMASK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DALO_COMPMASK

GLIU_DA_COMP_MASK_LO Bit Descriptions

Bit Name Description

63:45 RSVD Reserved. Write as read.

44:0 DALO_COMPMASK Data Packet Compare Mask [44:0]. This field forms the lower portion of the data

COMPMASK value, that is then bit-wise logically ANDed with the incoming data value

before it is compared to the DA_COMPVAL. The “HI” and “LO” portions of the incom-

ing data, the compare value, and the compare mask, are assembled into complete bit

patterns before these operations occur.

MSR Address 510100D3h

Type R /W

Reset Value 00000000_00000000h

GLIU_DA_COMP_MASK_HI Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

DAHI_COMPMASK

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAHI_COMPMASK

GLIU_DA_COMP_MASK_HI Bit Descriptions

Bit Name Description

63:36 RSVD Reserved. Write as read.

35:0 DAHI_COMPMASK DA Packet Compare Mask [80:45]. This field forms the upper portion of the data

COMPMASK value that is then bit-wise logically ANDed with the incoming data value

before it is compared to the DA_COMP_VAL. The “HI” and “LO” portions of the

incoming data (the compare value and compare mask) are assembled into complete

bit patterns before these operations occur.

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6.1.4 IOD Descriptor MSRs

6.1.4.1 IOD Base Mask Descriptors (GLIU_IOD_BM[x])

IOD Base Mask 0 (GLIU_IOD_BM0)

IOD Base Mask 1 (GLIU_IOD_BM1)

IOD Base Mask 2 (GLIU_IOD_BM2)

IOD Base Mask 3 (GLIU_IOD_BM3)

IOD Base Mask 4 (GLIU_IOD_BM4)

IOD Base Mask 5 (GLIU_IOD_BM5)

IOD Base Mask 6 (GLIU_IOD_BM6)

IOD Base Mask 7 (GLIU_IOD_BM7)

IOD Base Mask 8 (GLIU_IOD_BM8)

IOD Base Mask 9 (GLIU_IOD_BM9)

MSR Address 510100E0h

Type R /W

Reset Value 60000000_1F0FFFF0h

MSR Address 510100E1h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 510100E2h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 510100E3h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 510100E4h

Type R /W

Reset Value 000000FF_FFF00000h

MSR Address 510100E5h

Type R/W

Reset Value 000000FF_FFF00000h

MSR Address 510100E6h

Type R/W

Reset Value 000000FF_FFF00000h

MSR Address 510100E7h

Type R/W

Reset Value 000000FF_FFF00000h

MSR Address 510100E8h

Type R/W

Reset Value 000000FF_FFF00000h

MSR Address 510100E9h

Type R/W

Reset Value 000000FF_FFF00000h

GLIU_IOD_BM[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

IDID_BM

ICMP_BIZ_BM

RSVD IBASE_BM

313029282726252423222120191817161514131211109876543210

IBASE_BM IMASK_BM

GLIU_IOD_BM[x] Bit Descriptions

Bit Name Description

63:61 IDID_BM I/O Descriptor Destination ID. These bits define which port to route the request to if it is

a hit based on the other settings in this register.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

60 ICMP_BIZ_BM Compare BIZZARO Flag.

0: Consider only transactions whose BIZZARO flag is low as a potentially valid address

hit. A low BIZZARO flag indicates a normal transaction cycle such as a memory or

I/O.

1: Consider only transactions whose BIZZARO flag is high as a potentially valid address

hit. A high BIZZARO flag indicates a ‘special’ transaction, such as a PCI Shutdown or

Halt cycle.

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6.1.4.2 IOD Swiss Cheese Descriptors (GLIU_IOD_SC[x])

IOD Swiss Cheese 0 (GLIU_IOD_SC0)

IOD Swiss Cheese 1 (GLIU_IOD_SC1)

IOD Swiss Cheese 2 (GLIU_IOD_SC2)

IOD Swiss Cheese 3 (GLIU_IOD_SC3)

IOD Swiss Cheese 4 (GLIU_IOD_SC4)

IOD Swiss Cheese 5 (GLIU_IOD_SC5)

IOD Swiss Cheese 6 (GLIU_IOD_SC6)

IOD Swiss Cheese 7 (GLIU_IOD_SC7)

Each of these eight descriptors checks that the physical address supplied by the device’s request on the address bits is

equal to the IBASE_SC field of descriptor register bits and that the enable write or read conditions given by the descriptor

the device’s request. If the above matches, then the descriptor has a hit condition and routes the received address to the

programmed destination ID, IDID1_SC field of the descriptor register bits.

59:40 RSVD Reserved. Write as read.

39:20 IBASE_BM Physical I/O Address Base.These bits form the matching value against which the

masked value of the physical address, bits [19:0] are directly compared. If a match is

found, then a hit is declared, depending on the setting of the BIZZARO flag comparator.

19:0 IMASK_BM Physical I/O Address Mask. These bits are used to mask address bits [39:20] for the

purposes of this hit detection.

GLIU_IOD_BM[x] Bit Descriptions (Continued)

Bit Name Description

MSR Address 510100EAh

Type R /W

Reset Value 60000000_403003F0h

MSR Address 510100EBh

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100ECh

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100EDh

Type R /W

Reset Value 00000000_00000000h

MSR Address 510100EEh

Type R/W

Reset Value 00000000_00000000h

MSR Address 510100EFh

Type R/W

Reset Value 00000000_00000000h

MSR Address 510100F0h

Type R/W

Reset Value 00000000_00000000h

MSR Address 510100F1h

Type R/W

Reset Value 00000000_00000000h

GLIU_IOD_SC[x] Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

IDID_SC

ICMP_BIZ_SC

RSVD

313029282726252423222120191817161514131211109876543210

EN_SC RSVD

WEN_SC

REN_SC

IBASE_SC RSVD

AMD Geode™ CS5536 Companion Device Data Book 221

GeodeLink™ Interface Unit Register Descriptions 33238G

GLIU_IOD_SC Bit Descriptions

Bit Name Description

63:61 IDID_SC I/O Descriptor Destination ID. Encoded port number of the destination of addresses

that produce a hit based on the other fields in this descriptor.

000: Port 0 (GLIU) 100: Port 4 (DD)

001: Port 1 (GLPCI_SB) 101: Port 5 (ACC)

010: Port 2 (USB) 110: Port 6 (Not Used)

011: Port 3 (IDE) 111: Port 7 (GLCP)

60 ICMP_BIZ_SC Compare BIZZARO Flag. Used to check that the BIZZARO flag of the request is equal

to the ICMP_BIZ_SC bit. If a match does not occur, then the incoming request cannot

generate a hit. The BIZZARO flag, if set in the incoming request, signifies a “special’

cycle such as a PCI Shutdown or Halt.

59:32 RSVD Reserved. Write as read.

31:24 EN_SC Enable for Hits to IDID_SC else SUBP.

bit 0, if set, hit on I/O Address Base plus 0.

bit 1, if set, hit on I/O Address Base plus 1.

bit 7, if set, hit on I/O Address Base plus 7.

23:22 RSVD Reserved.

21 WEN_SC Descriptor Hits IDID_SC on Write Request Types else SUBP. If set, causes the

incoming request to be routed to the port specified in IDID_SC (bits [63:61]) if the incom-

ing request is a WRITE type.

20 REN_SC Descriptors Hit IDID_SC on Read Request Types else SUBP. If set, causes the

incoming request to be routed to the port specified in IDID_SC (bits [63:61]) if the incom-

ing request is a READ type.

19:0 IBASE_SC I/O Address Base. This field forms the basis of comparison with the incoming checks

that the physical address supplied by the device’s request on address bits [31:18] are

equal to the PBASE field of descriptor register bits [13:0]

2:0 RSVD Reserved. Write as read.

222 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ PCI South Bridge Register Descriptions

33238G

6.2 GeodeLink™ PCI South Bridge Register Descriptions

The GeodeLink™ PCI South Bridge (GLPCI_SB) register

set consists of:

•Standard GeodeLink™ Device (GLD) MSRs

•GLPCI_SB Specific MSRs

•PCI Configuration Registers

The MSRs (both Standard and GLPCI_SB Specific) are

accessed via the RDMSR and WRMSR processor instruc-

tions. The MSR address is derived from the perspective of

the CPU Core. See Section 4.2 "MSR Addressing" on page

60 for more details on MSR addressing.

Additionally, all GLPCI_SB Specific MSRs can be

accessed through both the PCI and GLIU interfaces. See

Section 6.2.3 "PCI Configuration Registers" on page 234

for details.

The PCI configuration registers can only be accessed

through the PCI interface and include:

•The first 16 bytes of standard PCI configuration regis-

ters.

•MSR access registers:

—PMCTRL

— PMADDR

—PMDATA0

—PMDATA1

Tables 6-5 through 6-7 are register summary tables that

include reset values and page references where the bit

descriptions are provided.

Table 6-5. Standard GeodeLink™ Device MSRs Summary

MSR Address Type Register Reset Value Reference

51000000h RO GLD Capabilities MSR

(GLPCI_GLD_MSR_CAP)

00000000_005055xxh Page 224

51000001h R/W GLD Master Configuration MSR

(GLPCI_GLD_MSR_CONFIG)

00000000_00000000h Page 224

51000002h R/W GLD SMI MSR (GLPCI_GLD_MSR_SMI) 00000000_00000000h Page 225

51000003h R/W GLD Error MSR (GLPCI_GLD_MSR_ERROR) 00000000_00000000h Page 226

51000004h R/W GLD Power Management MSR

(GLPCI_GLD_MSR_PM)

00000000_00000000h Page 227

51000005h R/W GLD Diagnostic MSR

(GLPCI_GLD_MSR_DIAG)

00000000_00000000h Page 228

Table 6-6. GLPCI_SB Specific MSRs Summary

MSR Address Type Register Reset Value Reference

51000010h R/W Global Control (GLPCI_CTRL) 44000030_00000003h Page 229

51000020h R/W Region 0 Configuration (GLPCI_R0) 00000000_00000000h Page 232

51000021h R/W Region 1 Configuration (GLPCI_R1) 00000000_00000000h Page 232

51000022h R/W Region 2 Configuration (GLPCI_R2) 00000000_00000000h Page 232

51000023h R/W Region 3 Configuration (GLPCI_R3) 00000000_00000000h Page 232

51000024h R/W Region 4 Configuration (GLPCI_R4) 00000000_00000000h Page 232

51000025h R/W Region 5 Configuration (GLPCI_R5) 00000000_00000000h Page 232

51000026h R/W Region 6 Configuration (GLPCI_R6) 00000000_00000000h Page 232

51000027h R/W Region 7 Configuration (GLPCI_R7) 00000000_00000000h Page 232

51000028h R/W Region 8 Configuration (GLPCI_R8) 00000000_00000000h Page 232

51000029h R/W Region 9 Configuration (GLPCI_R9) 00000000_00000000h Page 232

5100002Ah R/W Region 10 Configuration (GLPCI_R10) 00000000_00000000h Page 232

5100002Bh R/W Region 11 Configuration (GLPCI_R11) 00000000_00000000h Page 232

AMD Geode™ CS5536 Companion Device Data Book 223

GeodeLink™ PCI South Bridge Register Descriptions 33238G

5100002Ch R/W Region 12 Configuration (GLPCI_R12) 00000000_00000000h Page 232

5100002Dh R/W Region 13 Configuration (GLPCI_R13) 00000000_00000000h Page 232

5100002Eh R/W Region 14 Configuration (GLPCI_R14) 00000000_00000000h Page 232

5100002Fh R/W Region 15 Configuration (GLPCI_R15) 00000000_00000000h Page 232

51000030h RO PCI Configuration Space Header Byte 0-3

(GLPCI_PCIHEAD_BYTE0-3)

00000000_208F1022h Page 233

51000031h RO PCI Configuration Space Header Byte 4-7

(GLPCI_PCIHEAD_BYTE4-7)

00000000_00000000h Page 233

51000032h RO PCI Configuration Space Header Byte 8-B

(GLPCI_PCIHEAD_BYTE8-B)

00000000_FF0000xxh Page 233

51000033h RO PCI Configuration Space Header Byte C-F

(GLPCI_PCIHEAD_BYTEC-F)

00000000_00000000h Page 234

Table 6-6. GLPCI_SB Specific MSRs Summary

MSR Address Type Register Reset Value Reference

Table 6-7. PCI Configuration Registers

Index Type

Width

(Bits) Name Reset Value Reference

00h RO 32

(Note 1)

PCI Configuration Space Header Byte 0-3

(GLPCI_PCI_HEAD_BYTE0-3)

208F1022h Page 234

04h RO 32

(Note 1)

PCI Configuration Space Header Byte 4-7

(GLPCI_PCI_HEAD_BYTE4-7)

00000000h Page 235

08h RO 32

(Note 1)

PCI Configuration Space Header Byte 8-B

(GLPCI_PCI_HEAD_BYTE8-B)

FF0000xxh Page 235

0Ch RO 32

(Note 1)

PCI Configuration Space Header Byte C-F

(GLPCI_PCI_HEAD_BYTEC-F)

00000000h Page 236

F0h R/W 32 PCI MSR Control (GLPCI_PMCTRL) 00000001h Page 236

F4h R/W 32 PCI MSR Address (GLPCI_PMADDR) 00000000h Page 237

F8h R/W 32 PCI MSR Data 0 (GLPCI_PMDATA0) 00000000h Page 237

FCh R/W 32 PCI MSR Data 1 (GLPCI_PMDATA1) 00000000h Page 238

Note 1. Read address bits [1:0] are ignored and taken as 00.

224 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.2.1 Standard GeodeLink™ Device (GLD) MSRs

6.2.1.1 GLD Capabilities MSR (GLPCI_GLD_MSR_CAP)

6.2.1.2 GLD Master Configuration MSR (GLPCI_GLD_MSR_CONFIG)

MSR Address 51000000h

Type RO

Reset Value 00000000_005055xxh

GLPCI_GLD_MSR_CAP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD DEV_ID REV_ID

GLPCI_GLD_MSR_CAP Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Reads as 0.

23:8 DEV_ID Device ID. Identifies module (2051h).

7:0 REV_ID Revision ID. Identifies module revision. See AMD Geode™ CS5536 Companion Device

Specification Update document for value.

MSR Address 51000001h

Type R /W

Reset Value 00000000_00000000h

GLCPI_GLD_MSR_CONFIG Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD PRI

RSVD

PID

GLPCI_GLD_MSR_CONFIG Bit Descriptions

Bit Name Description

63:7 RSVD (RO) Reserved (Read Only). Returns 0.

6:4 PRI Priority Level. Always write 0.

3 RSVD (RO) Reserved (Read Only). Returns 0.

2:0 PID Priority ID. Always write 0.

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6.2.1.3 GLD SMI MSR (GLPCI_GLD_MSR_SMI)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.3 "MSR Address 2: SMI Control" on page 74 for

further SMI/ASMI generation details.)

MSR Address 51000002h

Type R /W

Reset Value 00000000_00000000h

GLPCI_GLD_MSR_SMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

TAS_ASMI_FLAG

PAR_ASMI_FLAG

SYSE_ASMI_FLAG

EXCEP_ASMI_FLAG

SSMI_ASMI_FLAG

TAR_ASMI_FLAG

MAR_ASMI_FLAG

RSVD

TAS_ASMI_EN

PAR_ASMI_EN

SYSE_ASMI_EN

EXCEP_ASMI_EN

SSMI_ASMI_EN

TAR_ASMI_EN

MAR_ASMI_EN

GLPCI_GLD_MSR_SMI Bit Descriptions

Bit Name Description

63:23 RSVD (RO) Reserved (Read Only). Returns 0.

22 TAS_ASMI_

FLAG

Target Abort Signaled ASMI Flag. If high, records that an ASMI was generated due to

the signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

TA_ASMI_EN (bit 6) must be high to generate ASMI and set flag.

21 PAR_ASMI_

FLAG

Parity Error ASMI Flag. If high, records that an ASMI was generated due to the detec-

tion of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PAR_ASMI_EN (bit

5) must be high to generate ASMI and set flag.

20 SYSE_ASMI_

FLAG

System Error ASMI Flag. If high, records that an ASMI was generated due to the detec-

tion of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ASMI_EN

(bit 4) must be high to generate ASMI and set flag.

19 EXCEP_ASMI_

FLAG

Exception Bit Flag. If high, records that an ASMI was generated due to the EXCEP bit

being set in the received GLIU read response packet. Write 1 to clear; writing 0 has no

effect. EXCEP_ASMI_EN (bit 3) must be set to enable this flag.

18 SSMI_ASMI_

FLAG

SSMI ASMI Flag. If high, records that an ASMI was generated due to the SSMI bit being

set in the received GLIU read or write response packet. Write 1 to clear; writing 0 has no

effect. SSMI_ASMI_EN (bit 2) must be set to enable this flag.

17 TAR_ASMI_

FLAG

Target Abort Received ASMI Flag. If high, records that an ASMI was generated due to

the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

TAR_ASMI_EN (bit 1) must be high to generate ASMI and set flag.

16 MAR_ASMI_

FLAG

Master Abort Received ASMI Flag. If high, records that an ASMI was generated due to

the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

MAR_ASMI_EN (bit 0) be high to generate ASMI and set flag.

15:7 RSVD (RO) Reserved (Read Only). Returns 0.

6 TAS_ASMI_EN Target Abort Signaled ASMI Enable. Write 1 to enable TAS_ASMI_FLAG (bit 22) and

to allow the event to generate an ASMI.

5 PAR_ASMI_EN Parity Error ASMI Enable. Write 1 to enable PAR_ASMI_FLAG (bit 21) and to allow the

event to generate an ASMI.

4 SYSE_ASMI_

System Error SMI Enable. Write 1 to enable SYSE_ASMI_FLAG (bit 20) and to allow

the event to generate an ASMI.

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33238G

6.2.1.4 GLD Error MSR (GLPCI_GLD_MSR_ERROR)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.4 "MSR Address 3: Error Control" on page 78

for further details.)

3 EXCEP_ASMI_

Exception Bit Enable. Write 1 to enable EXCEP_ASMI_FLAG (bit 19) and to allow the

event.

2 SSMI_EN SSMI Enable. Write 1 to enable SSMI_ASMI_FLAG bit (bit 18) and to allow the event.

1 TAR_ASMI_EN Target Abort Received ASMI Enable. Write 1 to enable TAR_ASMI_FLAG (bit 17) and

to allow the event to generate an ASMI.

0 MAR_ASMI_EN Master Abort Received ASMI Enable. Write 1 to enable MAR_ASMI_FLAG (bit 16) and

to allow the event to generate an ASMI.

MSR Address 51000003h

Type R /W

Reset Value 00000000_00000000h

GLPCI_GLD_MSR_SMI Bit Descriptions (Continued)

Bit Name Description

GLPCI_GLD_MSR_ERROR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

TAS_ERR_FLAG

PARE_ERR_FLAG

SYSE_ERR_FLAG

EXCEP_ERR_FLAG

RSVD

TAR_ERR_FLAG

MAR_ERR_FLAG

RSVD

TAS_ERR_EN

PARE_ERR_EN

SYSE_ERR_EN

EXCEP_ERR_EN

RSVD

TAR_ERR_EN

MAR_ERR_EN

GLPCI_GLD_MSR_ERROR Bit Descriptions

Bit Name Description

63:23 RSVD (RO) Reserved (Read Only). Returns 0.

22 TAS_ERR_

FLAG

Target Abort Signaled Error Flag. If high, records that an ERR was generated due to

signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

TAS_ERR_EN (bit 6) must be set to enable this event and set flag.

21 PARE_ERR_

FLAG

Parity Error Flag. If high, records that an ERR was generated due to the detection of a

PCI bus parity error. Write 1 to clear; writing 0 has no effect. PARE_ERR_EN (bit 5) must

be set to enable this event and set flag.

20 SYSE_ERR_

FLAG

System Error Flag. If high, records that an ERR was generated due to the detection of a

PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ERR_EN (bit 4)

must be set to enable this event and set flag.

19 EXCEP_ERR_

FLAG

Exception Bit Error Flag. If high, records that the EXCP bit in the received GLIU read or

write response packet is set. Write 1 to clear. EXCEP_ERR_EN (bit 3) must be set to

enable this event and set flag.

18 RSVD (RO) Reserved (Read Only). Returns 0.

17 TAR_ERR_

FLAG

Target Abort Received Error Flag. If high, records that an ERR was generated due to

the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

TAR_ERR_EN (bit 1) must be set to enable this event and set flag.

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GeodeLink™ PCI South Bridge Register Descriptions 33238G

6.2.1.5 GLD Power Management MSR (GLPCI_GLD_MSR_PM)

16 MAR_ERR_

FLAG

Master Abort Received Error Flag. If high, records that an ERR was generated due to

the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.

MAR_ERR_EN (bit 0) must be set to enable this event and set flag.

15:7 RSVD (RO) Reserved (Read Only). Returns 0.

6 TAS_ERR_EN Target Abort Signaled Error Enable. Write 1 to enable TAS_ERR_FLAG (bit 22) and to

allow the event to generate an ERR.

5 PARE_ERR_EN Parity Error Enable. Write 1 to enable PAR_ERR_FLAG (bit 21) and to allow the event

to generate an ERR.

4 SYSE_ERR_EN System Error Enable. Write 1 to enable SYSE_ERR_FLAG (bit 20) and to allow the

event to generate an ERR.

3 EXCEP_ERR_

Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 19) and to allow

the event to generate an ERR.

2 RSVD (RO) Reserved (Read Only). Returns 0.

1 TAR_ERR_EN Target Abort Received Error Enable. Write 1 to enable TAR_ERR_FLAG (bit 17) and to

allow the event to generate an ERR.

0 MAR_ERR_EN Master Abort Received Enable. Write 1 to enable MAR_ERR_FLAG (bit 16) and to

allow the event to generate an ERR.

MSR Address 51000004h

Type R /W

Reset Value 00000000_00000000h

GLPCI_GLD_MSR_ERROR Bit Descriptions (Continued)

Bit Name Description

CLPCI_GLD_MSR_PM Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD IO

MODEA

RSVD

313029282726252423222120191817161514131211109876543210

RSVD P

MODE2

MODE1

MODE0

GLPCI_GLD_MSR_PM Bit Descriptions

Bit Name Description

63:50 RSVD (RO) Reserved (Read Only). Returns 0.

49:48 IOMODEA I/O Mode A Control. These bits determine how the associated PCI inputs and outputs

will behave when the PMC asserts two internal signals that are controlled by PMS I/O

Offset 20h and 0Ch. The list of affected signals is given in Table 4-11 "Sleep Driven PCI

Signals" on page 79.

00: No gating of I/O cells during a Sleep sequence. (Default)

01: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled.

10: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled, and park (force) outputs low when

PM_OUT_SLPCTL is enabled.

11: Immediately and unconditionally, force inputs to their not asserted state, and park

(force) outputs low.

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33238G

6.2.1.6 GLD Diagnostic MSR (GLPCI_GLD_MSR_DIAG)

This register is reserved for internal use by AMD and should not be written to.

47:35 RSVD (RO) Reserved (Read Only). Returns 0.

34:32 RSVD Reserved. Write as read.

31:6 RSVD (RO) Reserved (Read Only). Returns 0.

5:4 PMODE2 Power Mode 2. Power mode for PCI-fast clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

3:2 PMODE1 Power Mode 1. Power mode for PCI clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

1:0 PMODE0 Power Mode 0. Power mode for GLIU clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

MSR Address 51000005h

Type R /W

Reset Value 00000000_00000000h

GLPCI_GLD_MSR_PM Bit Descriptions (Continued)

Bit Name Description

AMD Geode™ CS5536 Companion Device Data Book 229

GeodeLink™ PCI South Bridge Register Descriptions 33238G

6.2.2 GLPCI_SB Specific MSRs

6.2.2.1 Global Control (GLPCI_CTRL)

MSR Address 51000010h

Type R /W

Reset Value 44000030_00000003h

GLPCI_CTRL Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

FTH RTH RSVD RTL RSVD

SLTO

ILTO LAT 000

313029282726252423222120191817161514131211109876543210

SECSIZE SUS

RSVD

FPIDE

PPIDE

LRH

RDHP

RSIDE

RPIDE

LEGACT

SDOFF

HCD

IOED

RSVD CISM

GLPCI_CTRL Bit Descriptions

Bit Name IB/OB Description

63:60 FTH IB In-Bound Flush Threshold. Controls the timing for requesting new read data while

concurrently flushing previously prefetched stale read data. While flushing stale data,

if the number of prefetched 64-bit WORDs reaches this level, then a new read request

is made.

59:56 RTH IB In-Bound Read Threshold. Controls the timing for prefetching read data. If the num-

ber of prefetched 32-bit WORDs is decremented and reaches this threshold, a subse-

quent GLIU request is generated to fetch the next cache-line of read data.

55:52 RSVD (RO) --- Reserved (Read Only). Returns 0.

51:49 RTL OB Retry Transaction Limit. Limits the number of out-bound retries. If a target signals

retry indefinitely the PCI interface may be configured to abort the failing out-bound

request.

000: No limit. 100: 64 retries.

001: 8 retries. 101: 128 retries.

010: 16 retries. 110: 256 retries.

011: 32 retries. 111: 512 retries.

48:43 RSVD (RO) --- Reserved (Read Only). Returns 0.

42 SLTO IB Subsequent Latency Time-Out Select. Specifies the subsequent target latency

time-out limit. If within a burst, the GLPCI_SB module does not respond with the con-

figured number of clock edges, the PCI interface terminates the PCI bus cycle.

0: 8 PCI clock edges.

1: 4 PCI clock edges.

41:40 ILTO IB Initial Latency Time-Out Select. Specifies the initial target latency time-out limit for

the PCI interface. If the GLPCI_SB module does not respond with the first data phase

within the configured number of clock edges, the PCI interface terminates the PCI bus

cycle.

00: 32 PCI clock edges. 10: 8 PCI clock edges.

01: 16 PCI clock edges. 11: 4 PCI clock edges.

39:35 LAT IB/OB PCI Usage Timer. Usage time-out value for limiting bus tenure.

34:32 0 (RO) IB/OB Constant 0 (Read Only). The three least significant bits of the PCI latency timer field

are fixed as zeros. These bits are not used as part of the PCI latency timer compari-

son.

230 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ PCI South Bridge Register Descriptions

33238G

31:24 SECSIZE --- Sectorsize. The Primary IDE prefetch is stopped one DWORD before the end of the

sector to prevent interrupt assertion because of prefetch. After starting read from the

next sector, prefetch is automatically continued. The value represents the sector size

divided by 16.

Programming examples:

Value Sector Size

128: 8 KB

64: 4 KB

32: 2 KB

16: 1 KB

8: 512 Byte

4: 256 Byte

2: 128 Byte

1: 64 Byte

0: No Prefetch

23:21 SUS IB/OB Busy Sustain. Controls the sustain time for keeping the clocks running after the inter-

nal busy signals indicate that the clocks may be gated.

000: No sustain. 100: 32 clock cycles.

001: 4 clock cycles. 101: 64 clock cycles.

010: 8 clock cycles. 110: 128 clock cycles.

011: 16 clock cycles. 111: 256 clock cycles.

20 RSVD (RO) --- Reserved (Read Only). Returns 0.

19:18 FPIDE IB Prefetch Primary IDE. If these bits are set, I/O reads to address 1F0h conform to a

prefetching behavior. Under this mode, the GLPCI_SB issues GLIU Read Request

Packets for this specific address before receiving a request on the PCI bus for it.

00: Off. (Default)

01: At “beginning” initialize pipeline with two read requests.

10: At “beginning” initialize pipeline with three read requests.

11: Reserved.

The prefetch only applies if the current command is “read”. The current command is

assumed from the last write to the IDE Command Register at 1F7h. The following

commands are considered “reads”:

Read sectors - 20h

Read multiple - C4h

Read buffer - E4h

All reads from the same sector must be of the same size (16 or 32 bits) - software

must not mix 16-bit and 32-bit reads.

Prefetch does not cross sector boundaries that are programmed in the SECSIZE field

(bit [31:24]). Prefetch is stopped before the boundary and automatically restarted after

the boundary is crossed. Any prefetched data is discarded on any write to 1F7h.

17 PPIDE IB Post Primary IDE. Defaults to 0. If this bit is set, I/O writes to address 1F0h are

posted; that is, the “send response” flag is not set in the GLIU Write Request Packet.

Effectively, an I/O write to this specific address is posted just like memory writes are

posted. When IDE posting is enabled, single and DWORD writes may be mixed with-

out restriction.

16 LRH IB Legacy I/O Retry/Hold.

0: Legacy I/O retry.

1: Legacy I/O hold.

Regardless of the above settings, an I/O read or write to 1F0h always causes a retry if

data can not be immediately transferred.

GLPCI_CTRL Bit Descriptions (Continued)

Bit Name IB/OB Description

AMD Geode™ CS5536 Companion Device Data Book 231

GeodeLink™ PCI South Bridge Register Descriptions 33238G

15 RDHP IB Reject DMA High Page. Controls the decoding of I/O range associated with the DMA

High Page registers (480h-48Fh).

0: Considered part of legacy I/O.

1: Subtractive decode.

14 RSIDE IB Reject Secondary IDE. Controls the decoding of I/O range associated with Second-

ary IDE address of 170h-177h and 376h.

0: Considered part of legacy I/O.

1: Subtractive decode.

13 RPIDE IB Reject Primary IDE. Controls the decoding of I/O range associated with Primary IDE

address of 1F0h-1F7h and 3F6h.

0: Considered part of legacy I/O.

1: Subtractive decode.

12:11 LEGACT IB Legacy I/O Space Active Decode.

00: Subtractive decode (claim on fourth clock).

01: Slow decode (claim on third clock).

10: Medium decode (Claim on second clock).

11: Reserved (implemented as medium decode and returned 10 when read).

10 SDOFF OB Non Legacy Subtractive Decode Off.

0: Subtractive decode enabled.

1: Subtractive decode disabled.

9 HCD IB Hold for CIS Transfer Disable.

0: Hold for CIS transfer enabled.

1: Hold for CIS transfer disabled.

8IOED IBI/O Addressing Error Checking Disable.

0: I/O addressing error checking enabled.

1: I/O addressing error checking disabled.

7:5 RSVD (RO) --- Reserved (Read Only). Returns 0.

4:3 CISM IB/OB CIS Mode.

00: Mode A. Not used in normal operation. (Default)

01: Mode B. Not used in normal operation.

10: Mode C. Used in normal operation.

11: Reserved.

See Section 5.2.14 "CPU Interface Serial (CIS)" on page 86 for details regarding

operation modes.

2OD OBOut-Bound Request Disable.

0: Out-bound request enabled.

1: Out-bound request disabled.

When an out-bound request is disabled, all outstanding out-bound requests are ser-

viced before a read response packet with SSMI bit and all data bits cleared and

EXCEP bit set is returned.

1IE IBI/O Enable. Enable handling of in-bound I/O transactions from PCI. When set to 1 the

PCI interface accepts all in-bound I/O transactions from PCI. This mode is only

intended for design verification purposes. When cleared to 0 no in-bound I/O transac-

tions are accepted.

0ME IBMemory Enable. Enable handling of in-bound memory access transaction from PCI.

When cleared to 0, the PCI interface does not accept any in-bound memory transac-

tions from the PCI bus.

GLPCI_CTRL Bit Descriptions (Continued)

Bit Name IB/OB Description

232 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.2.2.2 Region 0-15 Configuration MSRs (GLPCI_R[x])

Region 0 Configuration (GLPCI_R0)

Region 1 Configuration (GLPCI_R1)

Region 2 Configuration (GLPCI_R2)

Region 3 Configuration (GLPCI_R3)

Region 4 Configuration (GLPCI_R4)

Region 5 Configuration (GLPCI_R5)

Region 6 Configuration (GLPCI_R6)

Region 7 Configuration (GLPCI_R7)

Region 8 Configuration (GLPCI_R8)

Region 9 Configuration (GLPCI_R9)

Region 10 Configuration (GLPCI_R10)

Region 11 Configuration (GLPCI_R11)

Region 12 Configuration (GLPCI_R12)

Region 13 Configuration (GLPCI_R13)

Region 14 Configuration (GLPCI_R14)

Region 15 Configuration (GLPCI_R15)

MSR Address 51000020h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000021h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000022h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000023h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000024h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000025h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000026h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000027h

Type R /W

Reset Value 00000000_00000000h

MSR Address 51000028h

Type R/W

Reset Value 00000000_00000000h

MSR Address 51000029h

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Ah

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Bh

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Ch

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Dh

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Eh

Type R/W

Reset Value 00000000_00000000h

MSR Address 5100002Fh

Type R/W

Reset Value 00000000_00000000h

GLPCI_R[x] Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

TOP RSVD

SPACE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BASE RSVD

RSVD

AMD Geode™ CS5536 Companion Device Data Book 233

GeodeLink™ PCI South Bridge Register Descriptions 33238G

6.2.2.3 PCI Configuration Space Header Byte 0-3 (GLPCI_PCIHEAD_BYTE0-3)

Reads back the value of PCI Configuration Space Header Byte 0-3 (GLPCI_PCI_HEAD_BYTE0-3). See Section 6.2.3.1 on

page 234 for register map and bit definitions.

6.2.2.4 PCI Configuration Space Header Byte 4-7 (GLPCI_PCIHEAD_BYTE4-7)

Reads back the value of PCI Configuration Space Header Byte 4-7 (GLPCI_PCI_HEAD_BYTE4-7). See Section 6.2.3.2 on

page 235 for register map and bit definitions.

6.2.2.5 PCI Configuration Space Header Byte 8-B (GLPCI_PCIHEAD_BYTE8-B)

Reads back the value of PCI Configuration Space Header Byte 8-B (GLPCI_PCI_HEAD_BYTE8-B). See Section 6.2.3.3

on page 235 for register map and bit definitions.

GLPCI_REGCONF[x] Bit Descriptions

Bit Name Description

63:44 TOP Top of Region. For memory use [63:44] as top of address bits [31:12]. For I/O use

[63:46] as top of address bits [19:2]. (Note 1)

43:33 RSVD (RO) Reserved (Read Only): Returns 0.

32 SPACE Region Space Indicator.

0: Memory space.

1: I/O space.

31:12 BASE Base of Region. For memory use [31:12] as base of address bits [31:12]. For I/O use

[31:14] as base of address bits [19:2]. (Note 1)

11:4 RSVD (RO) Reserved (Read Only). Returns 0.

3PF Prefetchable. If region is memory and this bit is set, it indicates a prefetechable memory

region. Reads to this region have no side-effects. If region is I/O and this bit is set, post all

I/O writes to this region.

2 RSVD (RO) Reserved (Read Only). Returns 0.

1RH Retry/Hold. Defines whether GLPCI_SB PCI slave generates a retry condition or holds

the PCI bus until cycle completion. Note that even if hold is selected, the cycle is termi-

nated if initial latency time-out is reached.

0: Retry.

1: Hold.

0EN Region Enable. Set to 1 to enable access to this region.

Note 1. For memory, 4 KB granularity, inclusive: [63:44] <= address[31:12] <= [31:12].

For I/O, 4B granularity, inclusive: [63:46] <= address[19:2] <= [31:14].

MSR Address 51000030h

Type RO

Reset Value 00000000_208F1022h

MSR Address 51000031h

Type RO

Reset Value 00000000_00000000h

MSR Address 51000032h

Type RO

Reset Value 00000000_FF0000xxh

234 AMD Geode™ CS5536 Companion Device Data Book

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6.2.2.6 PCI Configuration Space Header Byte C-F (GLPCI_PCIHEAD_BYTEC-F)

Reads back the value of PCI Configuration Space Header Byte C-F (GLPCI_PCI_HEAD_BYTEC-F). See Section 6.2.3.4

on page 236 for register map and bit definitions.

6.2.3 PCI Configuration Registers

The first 16 bytes of the PCI configuration register space

consist of standard PCI header registers. An additional 32

bytes are used to implement a mailbox for giving access

from the PCI bus to the internal MSRs of the CS5536 com-

panion device.

MSR Access Mailbox

Upon reset, MSR access is enabled. That is, the PMC-

TRL.EN bit is set. A PCI configuration (config) write to reg-

ister F0h clearing the EN bit is required to disable MSR

access.

An MSR read is accomplished by:

•A PCI configuration write to register F4h (PMADDR)

with the appropriate address value. If the appropriate

address value was previously written to register F4h,

then this step is unnecessary.

•A PCI configuration read of register F8h (PMDATA0).

This starts the GLIU MSR read. The PCI bus is held

(i.e., no retry unless time-out) until the transaction

completes.

•A PCI configuration read of register FCh (PMDATA1).

The PCI bus is held (i.e., no retry unless time-out) until

the transaction completes.

An MSR write is accomplished by:

•A PCI configuration write to register F4h (PMADDR)

with the appropriate address value. If the appropriate

address value was previously written to register F4h,

then this step is unnecessary.

•A PCI configuration write to register F8h (PMDATA0).

•A PCI configuration write to register FCh (PMDATA1).

This starts the GLIU MSR write. The PCI bus is held

(i.e., no retry unless time-out) until the transaction

completes.

Any PCI transaction interrupting an MSR read/write trans-

action is retried until the MSR transaction is complete.

The external MSR write request always has the

SEND_RESPONSE bit set. The returned MSR read or

write response packet is checked for the SSMI and EXCEP

bits.

6.2.3.1 PCI Configuration Space Header Byte 0-3 (GLPCI_PCI_HEAD_BYTE0-3)

MSR Address 51000033h

Type RO

Reset Value 00000000_00000000h

PCI Index 00h

Type RO

Reset Value 208F1022h

GLPCI_PCI_HEAD_BYTE0-3 Register Map

313029282726252423222120191817161514131211109876543210

DEV_ID VEN_ID

GLPCI_PCI_HEAD_BYTE0-3 Bit Descriptions

Bit Name Description

31:16 DEV_ID (RO) Device Identification Register (Read Only). Identifies AMD Geode™ CS5536 compan-

ion device as the device. Reads as 208Fh.

15:0 VEN_ID (RO) Vendor Identification Register (Read Only). Identifies AMD as the vendor. Reads as

1022h.

AMD Geode™ CS5536 Companion Device Data Book 235

GeodeLink™ PCI South Bridge Register Descriptions 33238G

6.2.3.2 PCI Configuration Space Header Byte 4-7 (GLPCI_PCI_HEAD_BYTE4-7)

6.2.3.3 PCI Configuration Space Header Byte 8-B (GLPCI_PCI_HEAD_BYTE8-B)

PCI Index 04h

Type RO

Reset Value 00000000h

GLPCI_PCI_HEAD_BYTE4-7 Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI_STS PCI_CMD

GLPCI_PCI_HEAD_BYTE4-7 Bit Descriptions

Bit Name Description

31:16 PCI_STS (RO) PCI Status Register (Read Only). Not implemented.

15:0 PCI_CMD (RO) PCI Command Register (Read Only). Not implemented.

PCI Index 08h

Type RO

Reset Value FF0000xxh

GLPCI_PCI_HEAD_BYTE8-B Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI_CLASS DEV_REV_ID

GLPCI_PCI_HEAD_BYTE8-B Bit Descriptions

Bit Name Description

31:16 PCI_CLASS

(RO)

PCI Class Code (Read Only).

15:0 DEV_REV_ID

(RO)

Device Revision ID (Read Only). Identifies the major and minor silicon revision of the

CS5536 companion device. Can also be read at MSR 51700017h[7:0]. See Section

6.20.2.12 "Chip Revision ID (GLCP_CHIP_REV_ID)" on page 574.

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33238G

6.2.3.4 PCI Configuration Space Header Byte C-F (GLPCI_PCI_HEAD_BYTEC-F)

6.2.3.5 PCI MSR Control (GLPCI_PMCTRL)

PCI Index 0Ch

Type RO

Reset Value 00000000h

GLPCI_PCI_HEAD_BYTC-F Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PCI_BIST PCI_HEADER PCI_LTNCY_TMR PCI_CACHE

GLPCI_PCI_HEAD_BYTEC-F Bit Descriptions

Bit Name Description

31:24 PCI_BIST (RO) PCI BIST Register (Read Only). Not implemented.

23:16 PCI_HEADER

(RO)

PCI Header Type Byte (Read Only). This register defines the format of this header.

This header is of type format 0, that is, this byte contains all zeroes.

16:8 PCI_LTNCY_TMR

(RO)

PCI Latency Timer Register (Read Only). Not implemented. Writing these bits has no

effect.

7:0 PCI_CACHE (RO) PCI Cache Line Size Register (Read Only). Not implemented. Writing these bits has

no effect.

PCI Index F0h

Type R /W

Reset Value 00000001h

GLPCI_PMCTRL Register Map

313029282726252423222120191817161514131211109876543210

RSVD

MSR_EN

GLPCI_PMCTRL Bit Descriptions

Bit Name Description

31:1 RSVD (RO) Reserved (Read Only). Returns 0.

0MSR_EN MSR Enable. Set to 1 to enable access to Model Specific Registers (MSRs).

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GeodeLink™ PCI South Bridge Register Descriptions 33238G

6.2.3.6 PCI MSR Address (GLPCI_PMADDR)

6.2.3.7 PCI MSR Data 0 (GLPCI_PMDATA0)

PCI Index F4h

Type R /W

Reset Value 00000000h

GLPCI_PMADDR Register Map

313029282726252423222120191817161514131211109876543210

ADDRESS

GLPCI_PMADDR Bit Descriptions

Bit Name Description

31:0 ADDRESS MSR Address. Address field to use in GLIU MSR accessing. Addresses with the most

significant 18 bits set to zero address the model specific registers of the GLPCI_SB mod-

ule itself. If any of the 18 most significant bits are set to one, the GLPCI_SB forwards the

MSR access to the GLIU without performing any address translation.

PCI Index F8h

Type R /W

Reset Value 00000000h

GLPCI_PMDATA0 Register Map

313029282726252423222120191817161514131211109876543210

DATA0

GLPCI_PMDATA0 Bit Descriptions

Bit Name Description

31:0 DATA0 MSR Data 0. Least significant 32-bits of MSR data. DATA0 and DATA1 (PCI Index

FCh[31:0]) are atomic in nature (i.e., if DATA0 access is made in GLPCI_SB then it must

followed by DATA1 access). Until the DATA1 access, the GLPCI_SB retries all other

transactions on the PCI bus for 215 cycles. After the timeout expires, atomic nature of

DATA0 and DATA1 expires and other transactions are accepted.

238 AMD Geode™ CS5536 Companion Device Data Book

GeodeLink™ PCI South Bridge Register Descriptions

33238G

6.2.3.8 PCI MSR Data 1 (GLPCI_PMDATA1)

PCI Index FCh

Type R /W

Reset Value 00000000h

GLPCI_PMDATA1 Register Map

313029282726252423222120191817161514131211109876543210

DATA1

GLPCI_PMDATA1 Bit Descriptions

Bit Name Description

31:0 DATA1 MSR Data 1. Most significant 32-bits of MSR data. DATA0 and DATA1 R/W are atomic in

nature (i.e., if DATA0 access is made in GLPCI_SB then it must followed by DATA1

access). Until the DATA1 access, GLPCI_SB retries all other transactions on PCI bus for

215 cycles. After this timeout, atomic nature for DATA0 and DATA1 expires and other

transactions are accepted.

AMD Geode™ CS5536 Companion Device Data Book 239

AC97 Audio Codec Controller Register Descriptions 33238G

6.3 AC97 Audio Codec Controller Register Descriptions

The control registers for the AC97 Audio Codec Controller

(ACC) are divided into two register sets:

•Standard GeodeLink™ Device (GLD) MSRs

•ACC Native Registers

The MSRs are accessed via the RDMSR and WRMSR pro-

cessor instructions. The MSR address is derived from the

perspective of the CPU Core. See Section 4.2 "MSR

Addressing" on page 60 for more details on MSR address-

ing.

The ACC Native registers begin at ACC Offset 00h. The

system automatically maps the ACC registers to a location

in memory space or I/O space, but this is hidden from the

module’s point of view. At the audio block level, it does not

matter if these registers are in memory or I/O space but at

the system level, there are significant operational differ-

ences (see Section "Eliminating Race Conditions"). Here-

after, the ACC Addresses are called out as I/O Offsets,

since I/O mapping is recommended.

For Native register access, only the lower seven bits of the

address are decoded, so the register space is aliased.

Accesses beyond 7Fh alias below 7Fh. Accesses to

addresses that are not implemented or reserved are “don’t

cares” (i.e., writes do nothing, reads return 0s).

Tables 6-8 and 6-9 are ACC register summary tables that

include reset values and page references where the bit

descriptions are provided.

Eliminating Race Conditions

All I/O writes are sequence locked, that is, completion of

the write at the target is confirmed before the executing

processor proceeds to the next instruction. All memory

writes are posted, that is, the executing processor pro-

ceeds to the next instruction immediately after the write

whether or not the write has completed. Write posting can

lead to out of order execution. Reading the register to

which a write has been posted forces any pending posted

write to execute if it has not already done so.

Consider this example. Assume an audio master is per-

forming an access to system memory and register access

is temporarily blocked. If the processor was servicing an

interrupt, a write to clear the interrupt posts to a memory

mapped register but not execute immediately, that is, the

interrupt would not immediately clear. If the processor then

enabled the Programmable Interrupt Controller (PIC) for

new interrupts, then the “not immediately cleared” interrupt

causes a false new interrupt, a form of a race condition.

This type of race condition can be eliminated by placing the

audio registers in I/O space, or, by performing a register

read to any register having a pending posted write that is

capable of creating a race condition.

Table 6-8. Standard GeodeLink™ Device MSRs Summary

MSR Address Type Register Name Reset Value Reference

51500000h RO GLD Capabilities MSR (ACC_GLD_MSR_CAP) 00000000_005335xxh Page 242

51500001h R/W GLD Master Configuration MSR

(ACC_GLD_MSR_CONFIG)

00000000_0000F000h Page 242

51500002h R/W GLD SMI MSR (ACC_GLD_MSR_SMI) 00000000_00000000h Page 243

51500003h R/W GLD Error MSR (ACC_GLD_MSR_ERROR) 00000000_00000000h Page 244

51500004h R/W GLD Power Management MSR

(ACC_GLD_MSR_PM)

00000000_00000000h Page 245

51500005h R/W GLD Diagnostic MSR (ACC_GLD_MSR_DIAG) 00000000_00000000h Page 245

240 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

Table 6-9. ACC Native Registers Summary

ACC I/O Offset Type Name Reset Value Reference

00h R/W Codec GPIO Status Register

(ACC_GPIO_STATUS)

00000000h Page 246

04h R/W Codec GPIO Control Register

(ACC_GPIO_CNTL)

00000000h Page 247

08h R/W Codec Status Register

(ACC_CODEC_STATUS)

00000000h Page 247

0Ch R/W Codec Control Register

(ACC_CODEC_CNTL)

00000000h Page 249

10h-11h --- Not Used --- ---

12h RO Second Level Audio IRQ Status Register

(ACC_IRQ_STATUS)

00000000h Page 251

14h R/W Bus Master Engine Control Register

(ACC_ENGINE_CNTL)

00000000h Page 252

18h-1Fh --- Not Used --- ---

20h R/W Bus Master 0 Command (ACC_BM0_CMD) 00h Page 253

21h RC Bus Master 0 IRQ Status

(ACC_BM0_STATUS)

00h Page 254

22h-23h --- Not Used --- ---

24h R/W Bus Master 0 PRD Table Address

(ACC_BM0_PRD)

00000000h Page 255

28h R/W Bus Master 1 Command (ACC_BM1_CMD) 08h Page 253

29h RC Bus Master 1 IRQ Status

(ACC_BM1_STATUS)

00h Page 254

2Ah-2Bh --- Not Used --- ---

2Ch R/W Bus Master 1 PRD Table Address

(ACC_BM1_PRD)

00000000h Page 255

30h R/W Bus Master 2 Command (ACC_BM2_CMD) 00h Page 253

31h RC Bus Master 2 IRQ Status

(ACC_BM2_STATUS)

00h Page 254

32h-33h --- Not Used --- ---

34h R/W Bus Master 2 PRD Table Address

(ACC_BM2_PRD)

00000000h Page 255

38h R/W Bus Master 3 Command (ACC_BM3_CMD) 08h Page 253

39h RC Bus Master 3 IRQ Status

(ACC_BM3_STATUS)

00h Page 254

3Ah-3Bh --- Not Used --- ---

3Ch R/W Bus Master 3 PRD Table Address

(ACC_BM3_PRD)

00000000h Page 255

40h R/W Bus Master 4 Command (ACC_BM4_CMD) 00h Page 253

41h RC Bus Master 4 IRQ Status

(ACC_BM4_STATUS)

00h Page 254

42h-43h --- Not Used --- ---

44h R/W Bus Master 4 PRD Table Address

(ACC_BM4_PRD)

00000000h Page 255

AMD Geode™ CS5536 Companion Device Data Book 241

AC97 Audio Codec Controller Register Descriptions 33238G

48h R/W Bus Master 5 Command (ACC_BM5_CMD) 08h Page 253

49h RC Bus Master 5 IRQ Status

(ACC_BM5_STATUS)

00h Page 254

4Ah-4Bh --- Not Used --- ---

4Ch R/W Bus Master 5 PRD Table Address

(ACC_BM5_PRD)

00000000h Page 255

50h R/W Bus Master 6 Command (ACC_BM6_CMD) 00h Page 253

51h RC Bus Master 6 IRQ Status

(ACC_BM6_STATUS)

00h Page 254

52h-53h --- Not Used --- ---

54h R/W Bus Master 6 PRD Table Address

(ACC_BM6_PRD)

00000000h Page 255

58h R/W Bus Master 7 Command (ACC_BM7_CMD) 00h Page 253

59h RC Bus Master 7 IRQ Status

(ACC_BM7_STATUS)

00h Page 254

5Ah-5Bh --- Not Used --- ---

5Ch R/W Bus Master 7 PRD Table Address

(ACC_BM7_PRD)

00000000h Page 255

60h RO Bus Master 0 DMA Pointer

(ACC_BM0_PNTR)

00000000h Page 256

64h RO Bus Master 1 DMA Pointer

(ACC_BM1_PNTR)

00000000h Page 256

68h RO Bus Master 2 DMA Pointer

(ACC_BM2_PNTR)

00000000h Page 256

6Ch RO Bus Master 3 DMA Pointer

(ACC_BM3_PNTR)

00000000h Page 256

70h RO Bus Master 4 DMA Pointer

(ACC_BM4_PNTR)

00000000h Page 256

74h RO Bus Master 5 DMA Pointer

(ACC_BM5_PNTR)

00000000h Page 256

78h RO Bus Master 6 DMA Pointer

(ACC_BM6_PNTR)

00000000h Page 256

7Ch RO Bus Master 7 DMA Pointer

(ACC_BM7_PNTR)

00000000h Page 256

Table 6-9. ACC Native Registers Summary

ACC I/O Offset Type Name Reset Value Reference

242 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

6.3.1 Standard GeodeLink Device (GLD) MSRs

6.3.1.1 GLD Capabilities MSR (ACC_GLD_MSR_CAP)

6.3.1.2 GLD Master Configuration MSR (ACC_GLD_MSR_CONFIG)

MSR Address 51500000h

Type RO

Reset Value 00000000_005335xxh

ACC_GLD_MSR_CAP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD DEV_ID REV_ID

ACC_GLD_MSR_CAP Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Reads return 0.

23:8 DEV_ID Device ID. Identifies module.

7:0 REV_ID Revision ID. Identifies module revision. See AMD Geode™ CS5536 Companion

Device Specification Update document for value.

MSR Address 51500001h

Type R /W

Reset Value 00000000_0000F000h

ACC_GLD_MSR_CONFIG Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD

PREFETCH_SEL

FIX_PREFETCH

DISCARD

NON_COH_WR

NON_COH_RD

RSVD PRI

RSVD

PID

ACC_GLD_MSR_CONFIG Bit Descriptions

Bit Name Description

63:20 RSVD Reserved. Reads return 0.

19 PREFETCH_SEL Select Flexible Prefetch Policy.

0: Fixed read prefetch policy is selected. (Default)

1: The ACC establishes prefetch policy.

18:16 FIX_PREFETCH Fixed Read Prefetch Policy.

000: None. Each read takes a complete trip to memory.

001: Initial read 08 bytes. Read next 8 only when requested.

010: Initial read 16 bytes. Read next 16 only when requested.

011: Initial read 32 bytes. Read next 32 only when requested.

100: Initial read 32 bytes. Read next 32 when 16 bytes left.

101, 110, and 111: Reserved.

AMD Geode™ CS5536 Companion Device Data Book 243

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.1.3 GLD SMI MSR (ACC_GLD_MSR_SMI)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.3 "MSR Address 2: SMI Control" on page 74 for

further SMI/ASMI generation details.)

15:14 DISCARD Read Prefetch Discard Policy.

00: Reserved.

01: Discard all data not taken under current local bus grant.

10: Discard all data on any local bus transaction.

11: Discard all data on any local bus write transaction. Always use this value.

13 NON_COH_WR Non-Coherent Write.

0: Write requests are coherent.

1: Write requests are non-coherent. Always use this value.

12 NON_COH_RD Non-Coherent Read.

0: Read requests are coherent.

1: Read requests are non-coherent. Always use this value.

11:7 RSVD Reserved. Reads as 0.

6:4 PRI Priority Level. Always write 0.

3 RSVD (RO) Reserved (Read Only). Returns 0.

2:0 PID Priority ID. Always write 0.

ACC_GLD_MSR_CONFIG Bit Descriptions (Continued)

Bit Name Description

MSR Address 51500002h

Type R /W

Reset Value 00000000_00000000h

ACC_GLD_MSR_SMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

IRQ_SSMI_FLAG

313029282726252423222120191817161514131211109876543210

RSVD

IRQ_SSMI_EN

244 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.3.1.4 GLD Error MSR (ACC_GLD_MSR_ERROR)

The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns

the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.7.3 "MSR Address 2: SMI Control" on page 74 for

further details.)

ACC_GLD_MSR_SMI Bit Descriptions

Bit Name Description

63:33 RSVD Reserved. Reads return 0.

32 IRQ_SSMI_FLAG IRQ SSMI Flag. If high, records that an SSMI was generated because the ACC inter-

rupt signal transitioned from 0 to 1. This bit is unaffected when the interrupt transitions

from 1 to 0. Write 1 to clear; writing 0 has no effect. IRQ_SSMI_EN (bit 1) must be set

to enable this event and set flag.

31:1 RSVD Reserved. Reads return 0.

0 IRQ_SSMI_EN IRQ SSMI Enable. Write 1 to enable IRQ_SSMI_FLAG (bit 32) and to allow the event

to generate an SSMI.

MSR Address 51500003h

Type R /W

Reset Value 00000000_00000000h

ACC_GLD_MSR_ERROR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

UNEXP_TYPE_ERR_FLAG

313029282726252423222120191817161514131211109876543210

RSVD

UNEXP_TYPE_ERR_EN

AMD Geode™ CS5536 Companion Device Data Book 245

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.1.5 GLD Power Management MSR (ACC_GLD_MSR_PM)

6.3.1.6 GLD Diagnostic MSR (ACC_GLD_MSR_DIAG)

This register is reserved for internal use by AMD and should not be written to.

ACC_GLD_MSR_ERROR Bit Descriptions

Bit Name Description

63:33 RSVD Reserved. Reads return 0.

32 UNEXP_TYPE_

ERR_FLAG

Unexpected Type Error Flag. If high, records that an ERR was generated due to

either an unexpected type event or a master response packet with the EXCEP bit set

has been received. Write 1 to clear; writing 0 has no effect. UNEXP_TYPE_ERR_EN

(bit 1) must be set to enable this event and set flag.

31:1 RSVD Reserved. Reads return 0.

0 UNEXP_TYPE_

ERR_EN

Unexpected Type Error Enable. Write 1 to enable UNEXP_TYPE_ERR_FLAG (bit

32) and to allow the event to generate an ERR.

MSR Address 51500004h

Type R /W

Reset Value 00000000_00000000h

ACC_GLD_MSR_PM Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD

PMODE1

PMODE0

ACC_GLD_MSR_PM Bit Descriptions

Bit Name Description

63:62 RSVD Reserved. Reads return value written.

61:4 RSVD Reserved. Reads return 0.

3:2 PMODE1 Power Mode 1. Power mode for LBus clock.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever the LBus circuits

are not busy.

10: Reserved. 11: Reserved.

1:0 PMODE0 Power Mode 0. Power mode for GLIU clock

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever the GLIU circuits

are not busy.

10: Reserved. 11: Reserved.

MSR Address 51500005h

Type R /W

Reset Value 00000000_00000000h

246 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

6.3.2 ACC Native Registers

6.3.2.1 Codec GPIO Status Register (ACC_GPIO_STATUS)

ACC I/O Offset 00h

Type R /W

Reset Value 00000000h

ACC_GPIO_STATUS Register Map

313029282726252423222120191817161514131211109876543210

GPIO_EN

INT_EN

WU_INT_EN

RSVD

INT_FLAG

WU_INT_FLAG

PIN_STS

ACC_GPIO_STATUS Bit Descriptions

Bit Name Description

31 GPIO_EN GPIO Enable. This bit determines if the codec GPIO pin data is sent out in slot 12 of

the serial output stream.

0: Send 0s and tag slot 12 as invalid.

1: Send GPIO pin data and tag slot valid.

30 INT_EN Codec GPIO Interrupt Enable. Allow a codec GPIO interrupt to set the codec GPIO

interrupt flag and generate an IRQ.

0: Disable.

1: Enable.

A GPIO interrupt is defined by serial data in slot 12, bit 0

29 WU_INT_EN Codec GPIO Wakeup Interrupt Enable. Allow a codec GPIO wakeup interrupt to set

the codec GPIO wakeup interrupt flag and generate an IRQ.

0: Disable.

1: Enable.

A codec GPIO wakeup interrupt is defined as a 0-to-1 transition of AC_S_IN or

AC_S_IN2 while the codec is powered down. This bit can only be set after the codec(s)

are powered down (See Audio Driver Power-up/down Programming Model on

page 97).

28:22 RSVD Reserved. Reads return 0.

21 INT_FLAG Codec GPIO Interrupt Flag (Read to Clear). If the GPIO interrupt is enabled (bit 30 =

1) then this flag is set upon a codec GPIO interrupt event (serial data in slot 12, bit 0 =

1), and an IRQ is generated.

20 WU_INT_FLAG Codec GPIO Wakeup Interrupt Flag (Read to Clear). If the GPIO wakeup interrupt is

enabled (bit 29 = 1), then this flag is set when a GPIO wakeup interrupt occurs, and an

IRQ is generated.

19:0 PIN_STS (RO) Codec GPIO Pin Status (Read Only). This is the GPIO pin status that is received from

the codec in slot 12 of the serial input stream. This is updated every time slot 12 of the

input stream is tagged valid.

Note: All 20 bits of input slot 12 are visible in this register, including reserved bits

within slot 12.

AMD Geode™ CS5536 Companion Device Data Book 247

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.2.2 Codec GPIO Control Register (ACC_GPIO_CNTL)

6.3.2.3 Codec Status Register (ACC_CODEC_STATUS)

ACC I/O Offset 04h

Type R /W

Reset Value 00000000h

ACC_GPIO_CNTL Register Map

313029282726252423222120191817161514131211109876543210

RSVD PIN_DATA

ACC_GPIO_CNTL Bit Descriptions

Bit Name Description

31:20 RSVD Reserved. Reads return 0.

19:0 PIN_DATA Codec GPIO Pin Data. This is the GPIO pin data that is sent to the codec in slot 12 of

the serial output stream.

Note: All 20 bits of the output slot 12 are controllable through this register, even

though some are reserved per the AC97 spec and should be set to zero.

ACC I/O Offset 08h

Type R /W

Reset Value 00000000h

ACC_CODEC_STATUS Register Map

313029282726252423222120191817161514131211109876543210

STS_ADD

PRM_RDY_STS

SEC_RDY_STS

SDATAIN2_EN

BM5_SEL

BM4_SEL

RSVD

STS_NEW

RSVD

STS_DATA

ACC_CODEC_STATUS Bit Descriptions

Bit Name Description

31:24 STS_ADD (RO) Codec Status Address (Read Only). Address of the register for which status is being

returned. This address comes from slot 1 bits [19:12] of the serial input stream.

Note: Bit 19 of slot 1 is reserved, but still observable by software.

23 PRM_RDY_STS

(RO)

Primary Codec Ready (Read Only). Indicates the ready status of the primary codec

(slot 0, bit 15). Software should not access the codec or enable any bus masters until

this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec

Control register (ACC I/O Offset 0Ch[18]).

22 SEC_RDY_STS

(RO)

Secondary Codec Ready (Read Only). Indicates the ready status of the secondary

codec (slot 0, bit 15). Software should not access the codec or enable any bus masters

until this bit is set. This bit is cleared when the AC Link Shutdown bit is set in the Codec

Control register (ACC I/O Offset 0Ch[18]).

248 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

21 SDATAIN2_EN Enable Second Serial Data Input (AC_S_IN2).

0: Disable.

1: Enable.

For the second serial input to function, this bit must be set. This is functionally ANDed

with the AC_S_IN2 port of the ACC. Often, it may be necessary to configure a corre-

sponding I/O pin as an input on the chip containing the ACC.

20 BM5_SEL Audio Bus Master 5 AC97 Slot Select. Selects the serial input slot for Audio Bus Mas-

ter 5 to receive data.

0: Slot 6.

1: Slot 11.

19 BM4_SEL Audio Bus Master 4 AC97 Slot Select. Selects slot for Audio Bus Master 4 to transmit

data.

0: Slot 6.

1: Slot 11.

18 RSVD Reserved. Reads return 0

17 STS_NEW Codec Status New (Read to Clear). Indicates if the status data in bits [15:0] is new:

0: Not new.

1: New.

This bit is set by hardware after receiving valid codec status data in slot 2 of the input

stream. Upon issuing a read to the codec registers, software should wait for this flag to

indicate that the corresponding data has been returned.

16 RSVD Reserved. Reads return 0.

15:0 STS_DATA (RO) Codec Status Data (Read Only). This is the codec status data that is received from

the codec in slot 2, bits [19:4] of the serial input stream. This is used for reading the

contents of registers inside the AC97 codec.

ACC_CODEC_STATUS Bit Descriptions (Continued)

Bit Name Description

AMD Geode™ CS5536 Companion Device Data Book 249

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.2.4 Codec Control Register (ACC_CODEC_CNTL)

Since this register could potentially be accessed by both an audio driver and a modem driver running at the same time, it is

expected that all writes occur as atomic read-modify-write accesses.

ACC I/O Offset 0Ch

Type R /W

Reset Value 00000000h

ACC_CODEC_CNTL Register Map

313029282726252423222120191817161514131211109876543210

RW_CMD

CMD_ADD

COMM_SEL

PD_PRIM

PD_SEC

RSVD

LNK_SHTDWN

LNK_WRM_RST

CMD_NEW

CMD_DATA

ACC_CODEC_CNTL Bit Descriptions

Bit Name Description

31 RW_CMD Codec Read/Write Command. This bit specifies a read or write operation targeting the

AC97 codec’s registers.

0: Write.

1: Read.

This bit determines whether slot 1, bit 19 of the serial output stream will be high or low.

30:24 CMD_ADD Codec Command Address. Address of the codec control register for which the com-

mand is being sent. This address goes in slot 1, bits [18:12] of the serial output stream.

This is used for specifying the address of a register in the AC97 codec (for reading or

writing).

23:22 COMM_SEL Audio Codec Communication. Selects which codec to communicate with (for register

reads/writes):

00: Codec 1 (Primary)

01: Codec 2 (Secondary)

10: Codec 3

11: Codec 4

These bits determine output slot 0, bits [1:0]. When these bits are non-zero, bits [14:13]

of output slot 0 must be set to zeros regardless of the validity of slot 1 and slot 2.

21 PD_PRIM Power-down Semaphore for Primary Codec. This bit is used by software in conjunc-

tion with bit 20 to coordinate the power-down of the two codecs. This bit is intended to

be set by the audio driver to indicate to the modem driver that the audio codec has

been prepared for power-down. Internally it does not control anything, and is simply a

memory bit.

20 PD_SEC Power-down Semaphore for Secondary Codec. This bit is used by software in con-

junction with bit 21 to coordinate the power-down of the two codecs. This bit is intended

to be set by the modem driver to indicate to the audio driver that the modem codec has

been prepared for power-down. Internally it does not control anything, and is simply a

memory bit.

19 RSVD Reserved. Reads return 0.

250 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

18 LNK_SHTDWN AC Link Shutdown. Informs the Controller that the AC Link is being shutdown.

This bit should be set at the same time that the codec power-down command is issued

to the codec.

Setting this bit also clears both Codec Ready bits in the Codec Status register (ACC I/O

Offset 08h[23:22]).

Issuing a warm reset via bit 17 clears this bit.

If the codec has been powered off and back on, a warm reset is unnecessary, this bit

should be cleared manually.

17 LNK_WRM_RST AC Link Warm Reset. Setting this bit initiates the AC Link/codec warm reset process.

It is automatically cleared by hardware once the serial bit clock resumes. This should

only be set when the codec(s) are powered down. Once set, software should then wait

for "Codec Ready" before accessing the codec.

16 CMD_NEW Codec Command New. Indicates if the codec command in bits [31:22] (and [15:0] for

writes) is new.

0: Not new.

1: New.

This bit is to be set by software when a new command is loaded. It is cleared by hard-

ware when the command is sent to the codec. Software must wait for this bit to clear

before loading another command.

This bit can not be cleared by software. When the CODEC_CNTL register is written by

software with bit 16 cleared, then bits [31:22] and [15:0] are unaffected. Thus, bit 16 is

an "enable" allowing bits [31:22] and [15:0] to be changed.

15:0 CMD_DATA Codec Command Data. This is the command data being sent to the codec in slot 2,

bits [19:12] of the serial output stream. This is used for writing data into one of the reg-

isters in the AC97 codec. The contents are only sent to the codec for write commands

(bit [31] = 0). For reads slot 2, bits[19:12] are stuffed with 0s.

ACC_CODEC_CNTL Bit Descriptions (Continued)

Bit Name Description

AMD Geode™ CS5536 Companion Device Data Book 251

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.2.5 Second Level Audio IRQ Status Register (ACC_IRQ_STATUS)

ACC I/O Offset 12h

Type RO

Reset Value 00000000h

ACC_IRQ_STATUS Register Map

1514131211109876543210

RSVD

BM7_IRQ_STS

BM6_IRQ_STS

BM5_IRQ_STS

BM4_IRQ_STS

BM3_IRQ_STS

BM2_IRQ_STS

BM1_IRQ_STS

BM0_IRQ_STS

WU_IRQ_STS

IRQ_STS

ACC_IRQ_STATUS Bit Descriptions

Bit Name Description

15:10 RSVD Reserved. Reads return 0.

9 BM7_IRQ_STS Audio Bus Master 7 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 7. Reading the Bus Master 7 IRQ Status

8 BM6_IRQ_STS Audio Bus Master 6 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 6. Reading the Bus Master 6 IRQ Status

7 BM5_IRQ_STS Audio Bus Master 5 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 5. Reading the Bus Master 5 IRQ Status

6 BM4_IRQ_STS Audio Bus Master 4 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 4. Reading the Bus Master 4 IRQ Status

5 BM3_IRQ_STS Audio Bus Master 3 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 3. Reading the Bus Master 3 IRQ Status

4 BM2_IRQ_STS Audio Bus Master 2 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 2. Reading the Bus Master 2 IRQ Status

3 BM1_IRQ_STS Audio Bus Master 1 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 1. Reading the Bus Master 1 IRQ Status

2 BM0_IRQ_STS Audio Bus Master 0 IRQ Status. If this bit is set, it indicates that an IRQ was caused

by an event occurring on Audio Bus Master 0. Reading the Bus Master 0 IRQ Status

1WU_IRQ_STS Codec GPIO Wakeup IRQ Status. If this bit is set, it indicates that an IRQ was caused

by a GPIO Wakeup Interrupt event (serial data in going high during power-down).

Reading the Codec GPIO Status Register clears this bit.

0IRQ_STS Codec GPIO IRQ Status. If this bit is set, it indicates that an IRQ was caused by a

GPIO event in the AC97 Codec (slot 12, bit 0). Reading the Codec GPIO Status Regis-

ter clears this bit.

252 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

6.3.2.6 Bus Master Engine Control Register (ACC_ENGINE_CNTL)

ACC I/O Offset 14h

Type R /W

Reset Value 00000000h

ACC_ENGINE_CNTL Register Map

313029282726252423222120191817161514131211109876543210

RSVD

SSND_MODE

ACC_ENGINE_CNTL Bit Descriptions

Bit Name Description

31:1 RSVD Reserved. Reads return 0.

0 SSND_MODE Surround Sound (5.1) Synchronization Mode. Enables synchronization of Bus Mas-

ters 0, 4, 6, and 7. This bit should be set whenever playing back multi-channel surround

sound. It ensures that the four bus masters stay synchronized and do not introduce any

temporal skew between the separate channels.

AMD Geode™ CS5536 Companion Device Data Book 253

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.2.7 Audio Bus Master 0-7 Command Registers (ACC_BM[x]_CMD)

Bus Master 0 Command (ACC_BM0_CMD)

Bus Master 1 Command (ACC_BM1_CMD)

Bus Master 2 Command (ACC_BM2_CMD)

Bus Master 3 Command (ACC_BM3_CMD)

Bus Master 4 Command (ACC_BM4_CMD)

Bus Master 5 Command (ACC_BM5_CMD)

Bus Master 6 Command (ACC_BM6_CMD)

Bus Master 7 Command (ACC_BM7_CMD)

ACC I/O Offset 20h

Type R /W

Reset Value 00h

ACC I/O Offset 28h

Type R /W

Reset Value 08h

ACC I/O Offset 30h

Type R /W

Reset Value 00h

ACC I/O Offset 38h

Type R /W

Reset Value 08h

ACC I/O Offset 40h

Type R/W

Reset Value 00h

ACC I/O Offset 48h

Type R/W

Reset Value 08h

ACC I/O Offset 50h

Type R/W

Reset Value 00h

ACC I/O Offset 58h

Type R/W

Reset Value 00h

ACC_BM[x]_CMD Register Map

76543210

RSVD RW BYTE_ORD BM_CTL

ACC_BM[x]_CMD Bit Descriptions

Bit Name Description

7:4 RSVD Reserved. Reads return 0

3RW (RO) Read or Write (Read Only). Indicates the transfer direction of the audio bus master.

This bit always reads 0 for BM [0,2,4,6,7].

This bit always reads 1 for BM[1,3,5].

0: Memory to codec.

1: Codec to memory.

2 BYTE_ORD Byte-Order. Sets the byte order for 16-bit samples that this bus master uses.

0: Little Endian (Intel) byte-order (LSBs at lower address).

1: Big Endian (Motorola) byte-order (MSBs at lower address).

1:0 BM_CTL Bus Master Pause/Enable Control. Enables, disables, or pauses the bus master.

00: Disable bus master.

01: Enable bus master.

10: Reserved.

11: Pause bus master (if currently enabled) or do nothing (if currently disabled).

When the bus master is enabled by writing 01, the bus master starts up by using the

address in its associated PRD Table Address Register. Writing 00 while the bus master

is enabled causes the bus master to stop immediately. Upon resuming, the bus master

uses the address in its PRD Table Address Register. The PRD Table Address Register

must be re-initialized by software before enabling the bus master, or there is a risk that

the bus master may overstep the bounds of the PRD Table.

Note: When the bus master reaches a PRD with the EOT bit set, these bits are set to

00.

254 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.3.2.8 Audio Bus Master 0-7 IRQ Status Registers (ACC_BM[x]_STATUS)

Bus Master 0 IRQ Status (ACC_BM0_STATUS)

Bus Master 1 IRQ Status (ACC_BM1_STATUS)

Bus Master 2 IRQ Status (ACC_BM2_STATUS)

Bus Master 3 IRQ Status (ACC_BM3_STATUS)

Bus Master 4 IRQ Status (ACC_BM4_STATUS)

Bus Master 5 IRQ Status (ACC_BM5_STATUS)

Bus Master 6 IRQ Status (ACC_BM6_STATUS)

Bus Master 7 IRQ Status (ACC_BM7_STATUS)

ACC I/O Offset 21h

Type R C

Reset Value 00h

ACC I/O Offset 29h

Type R C

Reset Value 00h

ACC I/O Offset 31h

Type R C

Reset Value 00h

ACC I/O Offset 39h

Type R C

Reset Value 00h

ACC I/O Offset 41h

Type RC

Reset Value 00h

ACC I/O Offset 49h

Type RC

Reset Value 00h

ACC I/O Offset 51h

Type RC

Reset Value 00h

ACC I/O Offset 59h

Type RC

Reset Value 00h

ACC_BM[x]_STATUS Register Map

76543210

RSVD BM_EOP_ERR EOP

ACC_BM[x]_STATUS Bit Descriptions

Bit Name Description

7:2 RSVD Reserved. Reads return 0

1 BM_EOP_ERR Bus Master Error. If this bit is set, it indicates that hardware encountered a second

EOP before software cleared the first EOP.

If hardware encounters a second EOP (end of page) before software clears the first

EOP, it causes the bus master to pause until this register is read to clear the error. Read

to clear.

0EOP End of Page. If this bit is set, it indicates the bus master transferred data that is marked

by the EOP bit in the PRD table (bit 30). Read to clear.

AMD Geode™ CS5536 Companion Device Data Book 255

AC97 Audio Codec Controller Register Descriptions 33238G

6.3.2.9 Audio Bus Master 7-0 PRD Table Address Registers (ACC_BM[x]_PRD)

Bus Master 0 PRD Table Address (ACC_BM0_PRD)

Bus Master 1 PRD Table Address (ACC_BM1_PRD)

Bus Master 2 PRD Table Address (ACC_BM2_PRD)

Bus Master 3 PRD Table Address (ACC_BM3_PRD)

Bus Master 4 PRD Table Address (ACC_BM4_PRD)

Bus Master 5 PRD Table Address (ACC_BM5_PRD)

Bus Master 6 PRD Table Address (ACC_BM6_PRD)

Bus Master 7 PRD Table Address (ACC_BM7_PRD)

ACC I/O Offset 24h

Type R /W

Reset Value 00000000h

ACC I/O Offset 2Ch

Type R /W

Reset Value 00000000h

ACC I/O Offset 34h

Type R /W

Reset Value 00000000h

ACC I/O Offset 3Ch

Type R /W

Reset Value 00000000h

ACC I/O Offset 44h

Type R/W

Reset Value 00000000h

ACC I/O Offset 4Ch

Type R/W

Reset Value 00000000h

ACC I/O Offset 54h

Type R/W

Reset Value 00000000h

ACC I/O Offset 5Ch

Type R/W

Reset Value 00000000h

ACC_BM[x]_PRD Register Map

313029282726252423222120191817161514131211109876543210

PRD_PNTR RSVD

ACC_BM[x]_PRD Bit Descriptions

Bit Name Description

31:2 PRD_PNTR Pointer to the Physical Region Descriptor Table. This register is a PRD table pointer

for Audio Bus Master [x].

When written, this register points to the first entry in a PRD table. Once Audio Bus Mas-

ter [x] is enabled (Command Register bit 0 = 1), it loads the pointer and updates this

When read, this register points to the next PRD.

1:0 RSVD Reserved. Reads return 0.

256 AMD Geode™ CS5536 Companion Device Data Book

AC97 Audio Codec Controller Register Descriptions

33238G

6.3.2.10 Bus Master 0-7 DMA Pointer Registers (ACC_BM[x]_PNTR)

Bus Master 0 DMA Pointer (ACC_BM0_PNTR)

Bus Master 1 DMA Pointer (ACC_BM1_PNTR)

Bus Master 2 DMA Pointer (ACC_BM2_PNTR)

Bus Master 3 DMA Pointer (ACC_BM3_PNTR)

Bus Master 4 DMA Pointer (ACC_BM4_PNTR)

Bus Master 5 DMA Pointer (ACC_BM5_PNTR)

Bus Master 6 DMA Pointer (ACC_BM6_PNTR)

Bus Master 7 DMA Pointer (ACC_BM7_PNTR)

ACC I/O Offset 60h

Type RO

Reset Value 00000000h

ACC I/O Offset 64h

Type RO

Reset Value 00000000h

ACC I/O Offset 68h

Type RO

Reset Value 00000000h

ACC I/O Offset 6Ch

Type RO

Reset Value 00000000h

ACC I/O Offset 70h

Type RO

Reset Value 00000000h

ACC I/O Offset 74h

Type RO

Reset Value 00000000h

ACC I/O Offset 78h

Type RO

Reset Value 00000000h

ACC I/O Offset 7Ch

Type RO

Reset Value 00000000h

ACC_BM[x]_PNTR Register Map

313029282726252423222120191817161514131211109876543210

DMA_PNTR

ACC_BM[x]_PNTR Bit Descriptions

Bit Name Description

31:0 DMA_PNTR DMA Buffer Pointer. Address of current sample being fetched (BM [0,2,4,6,7]) or writ-

ten (BM [1,3,5]) by the DMA Bus Master [x].

AMD Geode™ CS5536 Companion Device Data Book 257

USB Controller Register Descriptions 33238G

6.4 USB Controller Register Descriptions

The control registers allow software to communicate with

the USB Controller. These control registers are broadly

divided into six register sets:

•Standard GeodeLink™ Device (GLD) MSRs

•This register is reserved for internal use by AMD and

should not be written to. USB Specific MSRs

•USB Open Host Controller Interface Native Registers

•USB Enhanced Host Controller Native Registers

•This register is for AMD internal debug purposes. Soft-

ware should never write this register. USB Device

Controller Native Registers

•USB Option Controller Native Registers

The MSRs (both Standard and Specific) are accessed via

the RDMSR and WRMSR processor instructions. The MSR

address is derived from the perspective of the CPU Core.

See Section 4.2 "MSR Addressing" on page 60 for more

details on MSR addressing. The USB Transceiver PLL can

be disabled by software for power management purposes

with the GLCP_CLKOFF register (MSR 51700010h[46:0]).

Tables 6-10 through 6-12 are register summary tables that

include reset values and page references where the regis-

ter maps and bit descriptions are provided.

Table 6-10. Standard GeodeLink™ Device MSRs Summary

MSR Address Type Register Name Reset Value Reference

51200000h RO GLD Capabilities MSR

(USB_GLD_MSR_CAP)

00000000_005435xxh Page 262

51200001h R/W GLD Master Configuration MSR

(USB_GLD_MSR_CONFIG)

00000000_000BF000h Page 262

51200002h R/W GLD SMI MSR (USB_GLD_MSR_SMI) 00000000_0000002Fh Page 263

51200003h R/W GLD Error MSR (USB_GLD_MSR_ERROR) 00000000_00000000h Page 265

51200005h R/W GLD Diagnostic MSR

(USB_GLD_MSR_DIAG)

00000000_00000000h Page 265

Table 6-11. USB Specific MSRs Summary

MSR Address Type Register Name Reset Value Reference

51200008h R/W USB OHC Base Address (USBMSROHCB) 00000000_00000000h Page 266

51200009h R/W USB EHC Base Address (USBMSREHCB) 00000000_00000000h Page 266

5120000Ah R/W USB Device Controller Base Address

(USBMSRUDCB)

00000000_00000000h Page 268

5120000Bh R/W USB Option Controller Base Address

(USBMSRUOCB)

00000000_00000000h Page 268

258 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

Table 6-12. USB Open Host Controller Interface Native Registers Summary

OHC Memory

Offset Type Register Name Reset Value Reference

00h RO Host Controller Interface Revision (USB_HcRevision) 00000110h Page 269

04h R/W Host Controller Control (USB_HcControl) 00001414h Page 270

08h R/W Host Controller Command Status

(USB_HcCommandStatus)

00000000h Page 271

0Ch R/W Host Controller Interrupt Status (USB_HcInterruptStatus) 00000000h Page 273

10h R/W Host Controller Interrupt Enable (USB_HcInterruptEnable) 00000000h Page 274

14h R/W Host Controller Interrupt Disable (USB_HcInterruptDisable) 00000000h Page 275

18h R/W Host Controller HCCA (USB_HcHCCA) 00000000h Page 276

1Ch RO Host Controller Current Period List ED

(USB_HcPeriodCurrentED)

00000000h Page 276

20h R/W Host Controller Control List Head ED

(USB_HcControlHeadED)

00000000h Page 276

24h R/W Host Controller Current Control List ED

(USB_HcControlCurrentED)

00000000h Page 277

28h R/W Host Controller Bulk List Head ED (USB_HcBulkHeadED) 00000000h Page 277

2Ch R/W Host Controller Current Bulk List ED

(USB_HcBulkCurrentED)

00000000h Page 278

30h RO Host Controller Current Done List Head ED

(USB_HcDoneHead)

00000000h Page 278

34h R/W Host Controller Frame Interval (USB_HcFmInterval) 00002EDFh Page 279

38h RW Host Controller Frame Remaining

(USB_HcFrameRemaining)

00000000h Page 279

3Ch R/W Host Controller Frame Number (USB_HcFmNumber) 00000000h Page 280

40h R/W Host Controller Periodic Start (USB_HcPeriodicStart) 00000000h Page 280

44h R/W Host Controller Low Speed Threshold

(USB_HcLSThreshold)

00000628h Page 281

48h R/W Host Controller Root Hub Descriptor A

(USB_HcRhDescriptorA)

10000904h Page 281

4Ch R/W Host Controller Root Hub Descriptor B

(USB_HcRhDescriptorB)

00000000h Page 282

50h R/W Host Controller Root Hub Status (USB_HcRhStatus) 00000000h Page 283

54h R/W Host Controller Root Hub Port Status 1

(USB_HcRhPortStatus[1])

00000000h Page 284

58h R/W Host Controller Root Hub Port Status 2

(USB_HcRhPortStatus[2])

00000000h Page 289

5Ch R/W Host Controller Root Hub Port Status 3

(USB_HcRhPortStatus[3])

00000000h Page 289

60h R/W Host Controller Root Hub Port Status 4

(USB_HcRhPortStatus[4])

00000000h Page 292

AMD Geode™ CS5536 Companion Device Data Book 259

USB Controller Register Descriptions 33238G

Table 6-13. USB Enhanced Host Controller Interface Native Registers Summary

EHC Memory

Offset Type Register Name Reset Value Reference

00h RO Host Controller Capability Register (USB_HCCAPBASE) 01000010h Page 295

04h RO Structural Parameters Register (USB_HCSPARAMS) 00001414h Page 295

08h RO Capability Parameters Register (USB_HCCPARAMS) 00000012h Page 296

10h R/W Command Register (USBCMD) 00008000h Page 297

14h R/W Status Register (USBSTS) 00001000h Page 298

18h R/W Interrupt Enable Register (USBINTR) 00000000h Page 299

1Ch R/W Frame Index Register (FRINDEX) 00000000h Page 300

20h RO Control Data Structure Segment Register (CTRLDSSEG-

MEN)

00000000h Page 301

24h R/W Periodic Frame List Base Address Register (PERIODI-

CLISTBASE)

00000000h Page 301

28h R/W Current Asynchronous List Address Register (ASYNCLIS-

TADDR)

00000000h Page 302

50h R/W Configure Flag Register (CONFIGFLAG) 00000000h Page 302

54h R/W Port 1 Status and Control Register (PORTSC_1) 00000000h Page 302

58h R/W Port 2 Status and Control Register (PORTSC_2) 00000000h Page 305

5Ch R/W Port 3 Status and Control Register (PORTSC_3) 00000000h Page 307

60h R/W Port 4 Status and Control Register (PORTSC_4) 00000000h Page 309

90h R/W Vendor Specific Register 0 (IPREG00) 00000000h Page 312

94h R/W Vendor Specific Register 1 (IPREG01) 00F80010h Page 312

98h R/W Vendor Specific Register 2 (IPREG02)Vendor Specific Reg-

ister 2 (IPREG02)

00000020h Page 312

9Ch R/W Vendor Specific Register 3 (IPREG03) 00000001h Page 312

A0h R/W Vendor Specific Register 4 (IPREG04) 00000000h Page 312

A4h R/W Vendor Specific Register 5 (IPREG05) 00000000h Page 312

Table 6-14. USB Device Controller Native Registers Summary

UDC Memory Offset Type Register Name Reset Value Reference

EPINCTRL_0: 0000h

EPINCTRL_1: 0020h

EPINCTRL_2: 0040h

EPINCTRL_3: 0060h

EPINCTRL_4: 0080h

R/W Endpoint In Control Register (EPINCTRL) 00000000h Page 313

EPINSTS_0: 0004h

EPINSTS_1: 0024h

EPINSTS_2: 0044h

EPINSTS_3: 0064h

EPINSTS_4: 0084h

R/WC Endpoint In Status Register (EPINSTS) 00000000h Page 314

260 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

EPINBS_0: 0008h

EPINBS_1: 0028h

EPINBS_2: 0048h

EPINBS_3: 0068h

EPINBS_4: 0088h

R/W Endpoint In Buffer Size Register (EPINBS) 00000000h Page 315

EPINMAXP_0: 000Ch

EPINMAXP_1: 002Ch

EPINMAXP_2: 004Ch

EPINMAXP_3: 006Ch

EPINMAXP_4: 008Ch

R/W Endpoint In Max Packet Size Register (EPIN-

MAXP)

00000000h Page 315

EPINDDP_0: 0014h

EPINDDP_1: 0034h

EPINDDP_2: 0054h

EPINDDP_3: 0074h

EPINDDP_4: 0094h

R/W Endpoint In Data Descriptor Register (EPINDDP) 00000000h Page 316

EPINWRC_0: 001Ch

EPINWRC_1: 003Ch

EPINWRC_2: 005Ch

EPINWRC_3: 007Ch

EPINWRC_4: 009Ch

W Endpoint In Write Confirmation Register (EPIN-

WRC)

00000000h Page 316

EPOUTCTRL_0: 0200h

EPOUTCTRL_1: 0220h

EPOUTCTRL_2: 0240h

EPOUTCTRL_3: 0260h

EPOUTCTRL_4: 0280h

R/W Endpoint Out Control Register (EPOUTCTRL) 00000000h Page 317

EPOUTSTS_0: 0204h

EPOUTSTS_1: 0224h

EPOUTSTS_2: 0244h

EPOUTSTS_3: 0264h

EPOUTSTS_4: 0284h

R/W Endpoint Out Status Register (EPOUTSTS) 00000000h Page 318

EPOUTFRN_0: 0208h

EPOUTFRN_1: 0228h

EPOUTFRN_2: 0248h

EPOUTFRN_3: 0268h

EPOUTFRN_4: 0288h

RO Endpoint Out Frame Number Register (EPOUT-

FRN)

00000000h Page 319

EPOUTMAXP_0: 020Ch

EPOUTMAXP_1: 022Ch

EPOUTMAXP_2: 024Ch

EPOUTMAXP_3: 026Ch

EPOUTMAXP_4: 028Ch

R/W Endpoint Out Max Packet Size Register (EPOUT-

MAXP)

00000000h Page 319

EPOUTSUBP_0: 0210h

EPOUTSUBP_1: 0230h

EPOUTSUBP_2: 0250h

EPOUTSUBP_3: 0270h

EPOUTSUBP_4: 0290h

R/W Endpoint Out Setup Register (EPOUTSUBP) 00000000h Page 320

EPOUTDDP_0: 0214h

EPOUTDDP_1: 0234h

EPOUTDDP_2: 0254h

EPOUTDDP_3: 0274h

EPOUTDDP_4: 0294h

R/W Endpoint Out Data Descriptor Register (EPOUT-

DDP)

00000000h Page 320

Table 6-14. USB Device Controller Native Registers Summary

UDC Memory Offset Type Register Name Reset Value Reference

AMD Geode™ CS5536 Companion Device Data Book 261

USB Controller Register Descriptions 33238G

EPOUTRDC_0: 021Ch

EPOUTRDC_1: 023Ch

EPOUTRDC_2: 025Ch

EPOUTRDC_3: 027Ch

EPOUTRDC_4: 029Ch

WC Endpoint Out Read Confirmation Register

(EPOUTRDC)

00000000h Page 321

0400h R/W Device Configuration Register (DEVCFG) 00000020h Page 321

0404h R/W Device Control Register (DEVCTRL) 00000000h Page 323

0408h RO Device Status Register (DEVSTS) 000x0000h Page 324

040Ch R/WC Device Interrupt Register (DEVINTR) 00000000h Page 325

0410h R/W Device Interrupt Mask Register (DEVINTRMSK) 0000003Eh Page 325

0414h R/WC Endpoint Interrupt Register (EPINTR) 00000000h Page 326

0418h R/W Endpoint Interrupt Mask Register (EPINTRMSK) 001F001Fh Page 326

EP0REG: 0504h

EP1REG: 0508h

EP2REG: 050Ch

EP3REG: 0510h

EP4REG: 0514h

EP5REG: 0518h

EP6REG: 051Ch

EP7REG: 0520h

EP8REG: 0524h

R/W Endpoint Register (EPREG) 00000000h Page 327

0800h-BFCh R/W Receive FIFO (RXFIFOMEM) xxxxxxxxh Page 328

0C00h-11FCh R/W Transmit FIFO (TXFIFOMEM) xxxxxxxxh Page 328

Table 6-14. USB Device Controller Native Registers Summary

UDC Memory Offset Type Register Name Reset Value Reference

Table 6-15. USB Option Controller Native Registers Summary

UOC Memory Offset Type Register Name Reset Value Reference

00h R/W USB Option Capability Register (UOCCAP) 000003EAh Page 328

04h R/W USB Option Multiplex Register (UOCMUX) 00000000h Page 329

08h RO USB Reserved 0 (USB_RSVD0) 000008xxh Page 330

0Ch R/W USB Option Control Register (UOCCTL) 00000200h Page 330

10h R/W USB Reserved 1 (USB_RSVD1) 00000000h Page 330

14h R/WC USB Reserved 2 (USB_RSVD2) 00000000h Page 330

18h R/W USB Reserved 3 (USB_RSVD3) 00000000h Page 330

262 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.1 Standard GeodeLink™ Device (GLD) MSRs

6.4.1.1 GLD Capabilities MSR (USB_GLD_MSR_CAP)

6.4.1.2 GLD Master Configuration MSR (USB_GLD_MSR_CONFIG)

MSR Address 51200000h

Type RO

Reset Value 00000000_005435xxh

USB_GLD_MSR_CAP Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

313029282726252423222120191817161514131211109876543210

RSVD DEV_ID REV_ID

USB_GLD_MSR_CAP Bit Descriptions

Bit Name Description

63:24 RSVD Reserved. Reads as 0.

23:8 DEV_ID Device ID. Identifies module.

7:0 REV_ID Revision ID. Identifies module revision. See AMD Geode™ CS5536 Companion

Device Specification Update document for value.

MSR Address 51200001h

Type R /W

Reset Value 00000000_000BF000h

USB_GLD_MSR_CONFIG Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

SSDEN

ENPW

OHCPD

PFEN

313029282726252423222120191817161514131211109876543210

RSVD SPARE

RSVD

PRIO0

RSVD

PID

AMD Geode™ CS5536 Companion Device Data Book 263

USB Controller Register Descriptions 33238G

6.4.1.3 GLD SMI MSR (USB_GLD_MSR_SMI)

USB_GLD_MSR_CONFIG Bit Descriptions

Bit Name Description

63:36 RSVD Reserved. Reads return 0.

35 SSDEN Serial Short Detect Enable. When set, this bit enables the short detection circuit for

the serial PHY interface.

34 ENPW Emulate Non-Posted Writes. When set, this bit enforces strict ordering by finishing

every GeodeLink™ write burst with a read request on the burst’s start address, thus

ensuring that data has reached the memory before downstream read requests are

accepted.

33 OHCPD OHC Prefetch Disable. When set, the GLIU to AHB bridge does not use prefetching

for OHC bus master accesses.

32 PFEN Prefetch enable. When set, bus master read performance is improved.

31:11 RSVD Reserved. Reads return 0.

10:8 SPARE Reserved. These bits are R/W but control no hardware.

7 RSVD Reserved. Reads return 0.

6:4 PRIO0 Primary Priority Level.

3 RSVD Reserved. Reads return 0.

2:0 PID Priority Domain.

MSR Address 51200002h

Type R /W

Reset Value 00000000_0000002Fh

USB_GLD_MSR_SMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

EHCSSTAT

OHCSSTAT

UOCISTAT

UDCISTAT

EHCISTAT

OHCISTAT

313029282726252423222120191817161514131211109876543210

RSVD

EHCSMIIMSK

OHCSMIMSK

UOCI2SMIMSK

UDCI2SMIMSK

EHCI2SMIMSK

OHCI2SMIMSK

264 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

USB_GLD_MSR_SMI Bit Descriptions

Bit Name Description

63:38 RSVD Reserved. Reads return 0.

37 EHCSSTAT EHC Controller SMI Status Register. This register is set when the controller gener-

ates an SMI. The interrupt condition is cleared inside the controller. Writing a 1 clears

this bit. Writing 0 has no effect.

36 OHCSSTAT

(Note 1)

OHC Controller SMI Status Register. This register is set when the controller gener-

ates an SMI. The interrupt condition is cleared inside the controller. Writing a 1 clears

this bit. Writing 0 has no effect.

35 UOCISTAT USB Option Controller Interrupt Status Register. This register is set when the con-

troller generates an interrupt. The interrupt condition is cleared inside the controller.

Writing a 1 clears this bit. Writing 0 has no effect.

34 UDCISTAT UDC Interrupt Status Register. This register is set when the controller generates an

interrupt. The interrupt condition is cleared inside the controller. Writing a 1 clears this

bit. Writing 0 has no effect.

33 EHCISTAT EHC Interrupt Status Register. This register is set when the controller generates an

interrupt. The interrupt condition is cleared inside the controller. Writing a 1 clears this

bit. Writing 0 has no effect.

32 OHCISTAT OHC Interrupt Status Register. This register is set when the controller generates an

interrupt. The interrupt condition is cleared inside the controller. Writing a 1 clears this

bit. Writing 0 has no effect.

31:6 RSVD Reserved. Reads return 0.

5 EHCSMIMSK EHC SMI to ASMI Mask.

4 OHCSMIMSK OHC SMI to ASMI Mask.

3 UOCI2SMIMSK USB Option Controller Interrupt to ASMI Route Mask.

2 UDCI2SMIMSK UDC Interrupt to ASMI Route Mask.

1 EHCI2SMIMSK EHC Interrupt to ASMI Route Mask.

0 OHCI2SMIMSK OHC Interrupt to ASMI Route Mask.

Note 1. The status bits [36:32] are set with the rising edge of an event. This happens under two conditions:

1. When the corresponding mask bit is already set, then the status bit gets set with the rising edge of the interrupt

event.

2. When the corresponding mask bit is reset and an interrupt event is pending, then the status bit gets set when the

mask bit is set (set on mask toggle).

AMD Geode™ CS5536 Companion Device Data Book 265

USB Controller Register Descriptions 33238G

6.4.1.4 GLD Error MSR (USB_GLD_MSR_ERROR)

6.4.1.5 GLD Diagnostic MSR (USB_GLD_MSR_DIAG)

MSR Address 51200003h

Type R /W

Reset Value 00000000_00000000h

USB_GLD_MSR_ERROR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

UADDRSTS

UTYPESTS

313029282726252423222120191817161514131211109876543210

RSVD

UADDRMSK

UTYPEMSK

USB_GLD_MSR_ERROR Bit Descriptions

Bit Name Description

63:34 RSVD Reserved. Reads return 0.

33 UADDRSTS Unexpected Address. This bit is set by hardware when an unexpected type is

received on a GeodeLink™ request. Software must write a 1 to clear.

32 UTYPESTS Unexpected Type. This bit is set by hardware when an unexpected type is received on

a GeodeLink request. Software must write a 1 to clear.

31:2 RSVD Reserved. Reads return 0.

1 UADDRMSK Unexpected Address Mask. When this bit is set, an unexpected address received

with a GeodeLink request asserts the GeodeLink error flag.

0 UTYPEMSK Unexpected Type Mask. When this bit is set, an unexpected type received with a

GeodeLink request asserts the GeodeLink error flag.

MSR Address 51200005h

Type R /W

Reset Value 00000000_00000000h

266 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.2 This register is reserved for internal use by AMD

and should not be written to. USB Specific

MSRs

6.4.2.1 USB OHC Base Address (USBMSROHCB)

6.4.2.2 USB EHC Base Address (USBMSREHCB)

MSR Address 51200008h

Type R /W

Reset Value 00000000_00000000h

USBMSROHCB Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

PMESTS

PMEEN

BMEN

MEMEN

SPARE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OHCB RSVD

USBMSROHCB Bit Descriptions

Bit Name Description

63:37 RSVD Reserved. Read as 0.

36 PMESTS PME Status. This bit is set when the controller asserts PME independent of the state of

PMEEN (bit 35).

35 PMEEN PME Enable. If set, the controller is allowed to generate PMEs.

34 BMEN OHC Bus Master Enable. If set, the arbiter is allowed to arbitrate the OHC bus master.

33 MEMEN OHC Memory Enable. If set, memory space is enabled. If cleared, accesses to the

memory space are blocked.

32 SPARE Reserved. This bit does not control any hardware.

31:8 OHCB OHC Base Address. Base address providing for a memory space of 256 bytes.

7:0 RSVD Reserved. Read as 0.

MSR Address 51200009h

Type R /W

Reset Value 00000000_00000000h

USBMSREHCB Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD LEGSMISTS RSVD LECSMIEN RSVD FLADJ RSVD

PMESTS

PMEEN

BMEN

MEMEN

SPARE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EHCB RSVD

AMD Geode™ CS5536 Companion Device Data Book 267

USB Controller Register Descriptions 33238G

USBMSROHCB Bit Descriptions

Bit Name Description

63:62 RSVD Reserved. Read as 0.

61:56 LEGSMISTS Legacy SMI Status. Shadow bits from USBSTS (EHC Memory Offset 14h[5:0]) are

used for legacy SMI support.

61: Async Advance

60: Host System Error

59: Frame List Rollover

58: Port Change Detect

57: USD Error

56: USB Complete

55:54 RSVD Reserved. Read as 0.

53:48 LECSMIEN Legacy SMI Enable. These bits control whether the corresponding status bit in

LEGSMISTS (bit [61:56]) can cause an SMI.

53: SMI on Async Advance

52: SMI on Host System Error

51: SMI on Frame List Rollover

50: SMI on Port Change Detect

49: SMI on USD Error

48: SMI on USB Complete

47:46 RSVD Reserved. Read as 0.

45:40 FLADJ Frame Length Adjustment. The Start of Frame (SOF) cycle time is equal to 59488 +

(16*this value). The default of 20h gives a SOF cycle time of 60000.

FrameLength (HS bit times) FLADJ value

59488 00h

59504 01h

59520 02h

……

59984 1Fh

60000 20h

……

60480 3Eh

60496 3Fh

39:37 RSVD Reserved. Read as 0.

36 PMESTS PME Status. This bit is set when the controller asserts PME independent of the state of

PMEEN (bit 35).

35 PMEEN PME Enable. If set, the controller is allowed to generate PMEs.

34 BMEN EHC Bus Master Enable. If set, the arbiter is allowed to arbitrate the EHC bus master.

33 MEMEN EHC Memory Enable. If set, memory space is enabled. If cleared, accesses to the

memory space are blocked.

32 SPARE Reserved. This bit does not control any hardware.

31:8 EHCB EHC Base Address. Base address providing for a memory space of 256 bytes.

7:0 RSVD Reserved. Read as 0.

268 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.2.3 USB Device Controller Base Address (USBMSRUDCB)

6.4.2.4 USB Option Controller Base Address (USBMSRUOCB)

MSR Address 5120000Ah

Type R /W

Reset Value 00000000_00000000h

USBMSRUDCB Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

PMESTS

PMEEN

BMEN

MEMEN

SPARE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UDCB RSVD

USBMSRUDCB Bit Descriptions

Bit Name Description

63:37 RSVD Reserved. Read as 0.

36 PMESTS PME Status. This bit is set when the controller asserts PME independent of the state of

PMEEN (bit 35).

35 PMEEN PME Enable. If set, the controller is allowed to generate PMEs.

34 BMEN USB Device Controller Bus Master Enable. If set, the arbiter is allowed to arbitrate

the OHC bus master.

33 MEMEN USB Device Controller Memory Enable. If set, memory space is enabled. If cleared,

accesses to the memory space are blocked.

32 SPARE Reserved. This bit does not control any hardware.

31:13 UDCB USB Device Controller Base Address. Base address providing for a memory space

of 8 KB.

12:0 RSVD Reserved. Read as 0.

MSR Address 5120000Bh

Type R /W

Reset Value 00000000_00000000h

USBMSRUOCB Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

PMESTS

PMEEN

RSVD

MEMEN

SPARE

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UOCB RSVD

AMD Geode™ CS5536 Companion Device Data Book 269

USB Controller Register Descriptions 33238G

6.4.3 USB Open Host Controller Interface Native Registers

6.4.3.1 Host Controller Interface Revision (USB_HcRevision)

USBMSRUOCB Bit Descriptions

Bit Name Description

63:37 RSVD Reserved. Read as 0.

36 PMESTS PME Status. This bit is set when the controller asserts PME independent of the state of

PMEEN (bit 35).

35 PMEEN PME Enable. If set, the controller is allowed to generate PMEs.

34 RSVD Reserved.

33 MEMEN USB Option Controller Memory Enable. If set, memory space is enabled. If cleared,

accesses to the memory space are blocked.

32 SPARE Reserved. This bit does not control any hardware

31:8 UOCB USB Option Controller Base Address. Base address providing for a memory space

of 256 bytes.

7:0 RSVD Reserved. Read as 0.

OHC Memory Offset 00h

Type RO

Reset Value 00000110h

USB_HcRevision Register Map

313029282726252423222120191817161514131211109876543210

RSVD

LGCYSUP

REV

USB_HcRevision Bit Descriptions

Bit Name Description

31:8 RSVD Reserved. Read as 0.

8 LGCYSUP Legacy Support. This field is set to 1 to indicate that the legacy support registers are

present in this host controller (HC).

7:0 REV Revision. Indicates the Open HCI Specification revision number implemented by the

hardware.

270 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.3.2 Host Controller Control (USB_HcControl)

OHC Memory Offset 04h

Type R /W

Reset Value 00000000h

USB_HcControl Register Map

313029282726252423222120191817161514131211109876543210

RSVD

RWE

RWC

HCFS

BLE

CLE

PLE

CSBR

USB_HcControl Bit Descriptions

Bit Name Description

31:11 RSVD Reserved. Read as 0.

10 RWE Remote Wakeup Connected Enable. This bit is used by the host controller driver

(HCD) to enable or disable the remote wakeup feature upon the detection of upstream

resume signaling. When this bit is set, and the ResumeDetected bit (Memory Offset

0Ch[3]) is set, a remote wakeup is signaled to the host system. Setting this bit has no

impact on the generation of hardware interrupts.

9RWC Remote Wakeup Connected. This bit indicates whether the HC supports remote

wakeup signaling. If remote wakeup is supported and used by the system, it is the

responsibility of system firmware to set this bit during POST. The HC clears the bit upon

a hardware reset but does not alter it upon a software reset. Remote wakeup signaling

of the host system is host-bus specific and is not described in this specification.

8IR Interrupt Routing. This bit is used for interrupt routing.

0: Interrupts routed to normal interrupt mechanism (INT).

1: Interrupts routed to SMI.

7:6 HCFS Host Controller Functional State. A transition to UsbOperational from another state

causes SOF generation to begin 1 ms later. The HCD may determine whether the HC

has begun sending SOFs by reading the SOF field (OHC Memory Offset 0Ch[2]). This

field may be changed by the HC only when in the UsbSuspend state. The HC may move

from the UsbSuspend state to the UsbResume state after detecting the resume signal-

ing from a downstream port. The HC enters UsbSuspend after a software reset,

whereas it enters UsbReset after a hardware reset. The latter also resets the Root Hub

and asserts subsequent reset signaling to downstream ports.

00: UsbReset.

01: UsbResume.

10: UsbOperational.

11: UsbSuspend.

5BLE Bulk List Enable. This bit is set to enable the processing of the Bulk List in the next

frame. If cleared by the HCD, processing of the Bulk List does not occur after the next

SOF. The HC checks this bit whenever it determines to process the list. When disabled,

the HCD may modify the list. If USB_HcBulkCurrentED (Memory Offset 2Ch) is pointing

to an endpoint direction to be removed, the HCD must advance the pointer by updating

USB_HcBulkCurrentED before re-enabling processing of the list.

4CLE Control List Enable. This bit is set to enable the processing of the Control List in the

next frame. If cleared by the HCD, processing of the Control List does not occur after the

next SOF. The HC must check this bit whenever it determines to process the list. When

disabled, the HCD may modify the list. If USB_HcControlCurrentED (Memory Offset

24h) is pointing to an endpoint direction to be removed, the HCD must advance the

pointer by updating USB_HcControlCurrentED before re-enabling processing of the list.

AMD Geode™ CS5536 Companion Device Data Book 271

USB Controller Register Descriptions 33238G

6.4.3.3 Host Controller Command Status (USB_HcCommandStatus)

3IE Isochronous Enable. This bit is used by the HCD to enable/disable processing of iso-

chronous endpoint directions. While processing the Periodic List in a frame, the HC

checks the status of this bit when it finds an Isochronous endpoint direction (F=1). If set

(enabled), the HC continues processing the endpoint directions. If cleared (disabled),

the HC halts processing of the Periodic List (which now contains only isochronous end-

point directions) and begins processing the Bulk/Control lists. Setting this bit is guaran-

teed to take effect in the next frame (not the current frame).

2PLE Periodic List Enable. This bit is set to enable the processing of the Periodic List in the

next frame. If cleared by the HCD, processing of the Periodic List does not occur after

the next SOF. The HC must check this bit before it starts processing the list.

1:0 CBSR Control Bulk Service Ratio. This specifies the service ratio between control and bulk

endpoint directions. Before processing any of the Nonperiodic Lists, the HC must com-

pare the ratio specified with its internal count of how many nonempty control endpoint

directions have been processed, in determining whether to continue serving another

control endpoint direction or switching to bulk endpoint directions. The internal count is

retained when crossing the frame boundary. In case of reset, the HCD is responsible for

restoring this value.

CBSR No. of Control EDs Over Bulk EDs Served

00 1: 1

01 2: 1

10 3: 1

00 4: 1

OHC Memory Offset 08h

Type R /W

Reset Value 00000000h

USB_HcControl Bit Descriptions (Continued)

Bit Name Description

USB_HcCommandStatus Register Map

313029282726252423222120191817161514131211109876543210

RSVD SOC RSVD

OCR

BLF

CLF

HCR

272 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

USB_HcCommandStatus Bit Descriptions

Bit Name Description

31:18 RSVD Reserved. Read as 0.

17:16 SOC Schedule Overrun Count. These bits are incremented on each scheduling overrun

error. They are initialized to 00 and wrap around at 11. They are incremented when a

scheduling overrun is detected even if SchedulingOverrun (OHC Memory Offset 0Ch[0])

has already been set. This is used by the HCD to monitor any persistent scheduling

problems.

15:4 RSVD Reserved. Read as 0.

3OCR Ownership Change Request. This bit is set by an OS HCD to request a change of con-

trol of the HC. When set, the HC sets the OwnershipChange field (OHC Memory Offset

0Ch[30]). After the changeover, this bit is cleared and remains so until the next request

from the OS HCD.

2BLF Bulk List Filled. This bit is used to indicate whether there are any transfer descriptors

on the Bulk List. It is set by the HCD whenever it adds a transfer descriptor to an end-

point direction in the Bulk List. When the HC begins to process the head of the Bulk List,

it checks BLF. As long as BLF is 0, the HC does not start processing the Bulk List. If BLF

is 1, the HC starts processing the Bulk List and sets BLF to 0. If the HC finds a transfer

descriptor on the list, then the HC sets BLF to 1 causing the Bulk List processing to con-

tinue. If no transfer descriptor is found on the Bulk List, and if the HCD does not set BLF,

then BLF is still 0 when the HC completes processing the Bulk List and Bulk List pro-

cessing stops.

1CLF Control List Filled. This bit is used to indicate whether there are any transfer descrip-

tors on the Control List. It is set by the HCD whenever it adds a transfer descriptor to an

endpoint direction in the Control List. When the HC begins to process the head of the

Control List, it checks CLF. As long as CLF is 0, the HC does not start processing the

Control List. If CLF is 1, the HC starts processing the Control List and sets CLF to 0. If

the HC finds a transfer descriptor on the list, then the HC sets CLF to 1 causing the

Control List processing to continue. If no transfer descriptor is found on the Control List,

and if the HCD does not set CLF, then CLF is still 0 when the HC completes processing

the Control List and Control List processing stops.

0 HCR Host Controller Reset. This bit is set by the HCD to initiate a software reset of the HC.

Regardless of the functional state of the HC, it moves to the UsbSUSPEND state in

which most of the operational registers are reset except those stated otherwise (e.g.,

the InterruptRouting field of USB_HcControl (Memory Offset 04h[8])) and no Host bus

accesses are allowed. This bit is cleared by the HC upon completion of the reset opera-

tion. The reset operation must be completed within 10 ms. This bit, when set, should not

cause a reset to the Root Hub and no subsequent reset signaling should be asserted to

its downstream ports.

AMD Geode™ CS5536 Companion Device Data Book 273

USB Controller Register Descriptions 33238G

6.4.3.4 Host Controller Interrupt Status (USB_HcInterruptStatus)

All bits are set by the hardware and cleared by software.

OHC Memory Offset 0Ch

Type R /W

Reset Value 00000000h

USB_HcInterruptStatus Register Map

313029282726252423222120191817161514131211109876543210

RSVD

RHSC

FNO

SOF

WDH

USB_HcInterruptStatus Bit Descriptions

Bit Name Description

31 RSVD Reserved. Read as 0.

30 OC Ownership Change. This bit is set when the OwnershipChangeRequest bit (OHC

Memory Offet 08h[3]) is set.

29:7 RSVD Reserved. Read as 0.

6 RHSC Root Hub Status Change. This bit is set when the content of HcRhStatus (Memory

Offset 50h) or the content of any USBHcRhPortStatus[x] (OHC Memory Offset 54h,

58h, 5Ch, 60h) register has changed.

5FNO Frame Number Overflow. This bit is set when bit 15 of FrameNumber changes value

(OHC Memory Offset 3Ch[15]).

4UE (RO) Unrecoverable Error (Read Only). This event is not implemented and is hard coded to

0. HCD clears this bit.

3RD Resume Detected. This bit is set when the HC detects resume signaling on a down-

stream port.

2SOF Start Of Frame. This bit is set when the Frame Management block signals a Start Of

Frame event.

1WDH Writeback Done Head. This bit is set after the HC has written HcDoneHead (OHC

Memory Offset 30h[31:4]).

0SO Scheduling Overrun. This bit is set when the List Processor determines a Schedule

Overrun has occurred.

274 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.4.3.5 Host Controller Interrupt Enable (USB_HcInterruptEnable)

Each enable bit corresponds to an associated interrupt bit in USB_HcInterruptStatus (OHC Memory Offset 0Ch). This reg-

ister is used to control which events generate a hardware interrupt. When a bit is set in USB_HcInterruptStatus and the cor-

responding bit in the USB_HcInterruptEnable is set and the MasterInterruptEnable bit (bit 31) is set, then a hardware

interrupt is requested on the host bus. Writing a 1 to a bit in this register sets the corresponding bit, while writing 0 leaves

the bit unchanged.

OHC Memory Offset 10h

Type R /W

Reset Value 00000000h

USB_HcInterruptEnable Register Map

313029282726252423222120191817161514131211109876543210

MIE

RSVD

RHSC

FNO

WDH

USB_HcInterruptEnable Bit Descriptions

Bit Name Description

31 MIE Master Interrupt Enable. This bit is a global interrupt enable. Writing a 1 allows inter-

rupts to be enabled.

30 OC Ownership Change Enable.

0: Ignore.

1: Enable interrupt generation due to Ownership Change.

29:7 RSVD Reserved. Read as 0.

6 RHSC RootHub Status Change Enable.

0: Ignore.

1: Enable interrupt generation due to Root Hub Status Change.

5FNO Frame Number Overflow Enable.

0: Ignore.

1: Enable interrupt generation due to Frame Number Overflow.

4UE Unrecoverable Error Enable. This event is not implemented. All writes to this bit are

ignored.

3RD Resume Detected Enable.

0: Ignore.

1: Enable interrupt generation due to Resume Detected.

2SF Start Of Frame Enable.

0: Ignore.

1: Enable interrupt generation due to Start Of Frame.

1WDH Writeback Done Head Enable.

0: Ignore.

1: Enable interrupt generation due to Writeback Done Head.

0SO Scheduling Overrun Enable.

0: Ignore.

1: Enable interrupt generation due to Scheduling Overrun.

AMD Geode™ CS5536 Companion Device Data Book 275

USB Controller Register Descriptions 33238G

6.4.3.6 Host Controller Interrupt Disable (USB_HcInterruptDisable)

Each disable bit corresponds to an associated interrupt bit in USB_HcInterruptStatus (OHC Memory Offset 0Ch). This reg-

ister is coupled with USB_HcInterruptEnable (OHC Memory Offset 10h). Thus, writing a 1 to a bit in this register clears the

corresponding bit in the USB_HcInterruptEnable register, whereas writing 0 to a bit in this register leaves the corresponding

bit in the USB_HcInterruptEnable register unchanged.

OHC Memory Offset 14h

Type R /W

Reset Value 00000000h

USB_HcInterruptDisable Register Map

313029282726252423222120191817161514131211109876543210

MIE

RSVD

RHSC

FNO

WDH

USB_HcInterruptDisable Bit Descriptions

Bit Name Description

31 MIE Master Interrupt Disable. Global interrupt disable. A write of 1 disables all interrupts.

30 OC Ownership Change Disable.

0: Ignore.

1: Disable interrupt generation due to Ownership Change.

29:7 RSVD Reserved. Read as 0.

6 RHSC Root Hub Status Change Disable.

0: Ignore.

1: Disable interrupt generation due to Root Hub Status Change.

5FNO Frame Number Overflow Disable.

0: Ignore.

1: Disable interrupt generation due to Frame Number Overflow.

4UE Unrecoverable Error Disable. This event is not implemented. All writes to this bit will

be ignored.

3RD Resume Detected Disable.

0: Ignore.

1: Disable interrupt generation due to Resume Detected.

2SF Start Of Frame Disable.

0: Ignore.

1: Disable interrupt generation due to Start of Frame.

1WDH Writeback Done Head Disable.

0: Ignore.

1: Disable interrupt generation due to Writeback Done Head.

0SO Scheduling Overrun Disable.

0: Ignore.

1: Disable interrupt generation due to Scheduling Overrun.

276 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.3.7 Host Controller HCCA (USB_HcHCCA)

6.4.3.8 Host Controller Current Period List ED (USB_HcPeriodCurrentED)

6.4.3.9 Host Controller Control List Head ED (USB_HcControlHeadED)

OHC Memory Offset 18h

Type R /W

Reset Value 00000000h

USB_HcHCCA Register Map

313029282726252423222120191817161514131211109876543210

HCCA RSVD

USB_HcHCCA Bit Descriptions

Bit Name Description

31:8 HCCA HCCA. This is the base address of the HC communication area.

7:0 RSVD Reserved. Read as 0.

OHC Memory Offset 1Ch

Type RO

Reset Value 00000000h

USB_HcPeriodCurrentED Register Map

313029282726252423222120191817161514131211109876543210

PCED RSVD

USB_HcPeriodCurrentED Bit Descriptions

Bit Name Description

31:4 PCED Period Current ED. This is used by the HC to point to the head of one of the Periodic

Lists, which will be processed in the current frame. The content of this register is

updated by the HC after a periodic endpoint direction has been processed.The HCD

may read the content in determining which endpoint direction is currently being pro-

cessed at the time of reading.

3:0 RSVD Reserved. Read as 0.

OHC Memory Offset 20h

Type R /W

Reset Value 00000000h

USB_HcControlHeadED Register Map

313029282726252423222120191817161514131211109876543210

CHED RSVD

AMD Geode™ CS5536 Companion Device Data Book 277

USB Controller Register Descriptions 33238G

6.4.3.10 Host Controller Current Control List ED (USB_HcControlCurrentED)

6.4.3.11 Host Controller Bulk List Head ED (USB_HcBulkHeadED)

USB_HcControlHeadED Bit Descriptions

Bit Name Description

31:4 CHED Control Head ED. The HC traverses the Control List starting with the Control Head ED

pointer. The content is loaded from HCCA (OHC Memory Offset 18h) during the initial-

ization of the HC.

3:0 RSVD Reserved. Read as 0.

OHC Memory Offset 24h

Type R /W

Reset Value 00000000h

USB_HcControlCurrentED Register Map

313029282726252423222120191817161514131211109876543210

CCED RSVD

USB_HcControlCurrentED Bit Descriptions

Bit Name Description

31:4 CCED Control Current ED. This pointer is advanced to the next endpoint direction after serv-

ing the present one. The HC continues processing the list from where it left off in the

last frame. When it reaches the end of the Control List, the HC checks OHC Memory

Offset 08h[1]. If set, it copies the content of USB_HcControlHeadED (OHC Memory

Offset 20h) to USB_HcControlCurrentED and clears the bit. If not set, it does nothing.

The HCD is allowed to modify this register only when OHC Memory Offset 04h[4] is

cleared. When set, the HCD only reads the instantaneous value of this register. Initially,

this is set to zero to indicate the end of the Control List.

3:0 RSVD Reserved. Read as 0.

OHC Memory Offset 28h

Type R /W

Reset Value 00000000h

USB_HcBulkHeadED Register Map

313029282726252423222120191817161514131211109876543210

BHED RSVD

USB_HcBulkHeadED Bit Descriptions

Bit Name Description

31:4 BHED Bulk Head ED. The HC traverses the Bulk List starting with the USB_HcBulkHeadED

pointer. The content is loaded from HCCA (OHC Memory Offset 18h[31:8]) during the

initialization of the HC.

3:0 RSVD Reserved. Read as 0.

278 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.4.3.12 Host Controller Current Bulk List ED (USB_HcBulkCurrentED)

6.4.3.13 Host Controller Current Done List Head ED (USB_HcDoneHead)

OHC Memory Offset 2Ch

Type R /W

Reset Value 00000000h

USB_HcBulkCurrentED Register Map

313029282726252423222120191817161514131211109876543210

BCED RSVD

USB_HcBulkCurrentED Bit Descriptions

Bit Name Description

31:4 BCED Bulk Current ED. This is advanced to the next endpoint direction after the HC has

served the present one. The HC continues processing the list from where it left off in

the last frame. When it reaches the end of the Bulk List, the HC checks OHC Memory

Offset 08h[1]. If set, it copies the content of USB_HcBulkHeadED (OHC Memory Offset

28h) to USB_HcBulkCurrentED and clears the bit. If not set, it does nothing. The HCD

is only allowed to modify this register when OHC Memory Offset 04h[5] is cleared.

When set, the HCD only reads the instantaneous value of this register. This is initially

set to zero to indicate the end of the Bulk List.

3:0 RSVD Reserved. Read as 0.

OHC Memory Offset 30h

Type RO

Reset Value 00000000h

USB_HcDoneHead Register Map

313029282726252423222120191817161514131211109876543210

DH RSVD

USB_HcDoneHead Bit Descriptions

Bit Name Description

31:4 DH Done Head. When a transfer descriptor is completed, the HC writes the content of

USB_HcDoneHead to the NextTD field of the transfer descriptor. The HC then over-

writes the content of USB_HcDoneHead with the address of this transfer descriptor.

This is set to zero whenever the HC writes the content of this register to HCCA (OHC

Memory Offset 18h[31:8]). It also sets WDH (OHC Memory Offset 0Ch[1]).

3:0 RSVD Reserved. Read as 0.

AMD Geode™ CS5536 Companion Device Data Book 279

USB Controller Register Descriptions 33238G

6.4.3.14 Host Controller Frame Interval (USB_HcFmInterval)

6.4.3.15 Host Controller Frame Remaining (USB_HcFrameRemaining)

OHC Memory Offset 34h

Type R /W

Reset Value 00002EDFh

USB_HcFmInterval Register Map

313029282726252423222120191817161514131211109876543210

FIT

FSMPS RSVD FI

USB_HcFmInterval Bit Descriptions

Bit Name Description

31 FIT Frame Interval Toggle. The HCD toggles this bit whenever it loads a new value to

Frame Interval (bit [13:0]).

30:16 FSMPS FS Largest Data Packet. This field specifies a value that is loaded into the Largest

Data Packet Counter at the beginning of each frame. The counter value represents the

largest amount of data in bits that can be sent or received by the HC in a single transac-

tion at any given time without causing scheduling overrun. The field value is calculated

by the HCD.

15:14 RSVD Reserved. Read as 0.

13:0 FI Frame Interval. This specifies the interval between two consecutive SOFs in bit times.

The nominal value is set to be 11,999. The HCD should store the current value of this

field before resetting the HC by setting the Host Controller Reset field (OHC Memory

Offset 08h[0]) as this causes the HC to reset this field to its nominal value. The HCD

may choose to restore the stored value upon the completion of the Reset sequence.

OHC Memory Offset 38h

Type RW

Reset Value 00000000h

USB_HcFrameRemaining Register Map

313029282726252423222120191817161514131211109876543210

FRT

RSVD FR

USB_HcFrameRemaining Bit Descriptions

Bit Name Description

31 FRT Frame Remaining Toggle. This bit is loaded from the Frame Interval Toggle field

(OHC Memory Offset 34h[31]) whenever Frame Remaining (bits [13:0]) reaches 0. This

bit is used by the HCD for the synchronization between Frame Interval (OHC Memory

Offset 34h[13:0]) and Frame Remaining (bits [13:0]).

30:14 RSVD Reserved. Read as 0.

13:0 FR Frame Remaining. This counter is decremented at each bit time. When it reaches

zero, it is reset by loading the Frame Interval (OHC Memory Offset 34h[13:0]) value at

the next bit time boundary. When entering the UsbOperational state, the HC reloads

the content with the Frame Interval (OHC Memory Offset 34h[13:0]) and uses the

updated value from the next SOF.

280 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

6.4.3.16 Host Controller Frame Number (USB_HcFmNumber)

6.4.3.17 Host Controller Periodic Start (USB_HcPeriodicStart)

OHC Memory Offset 3Ch

Type R /W

Reset Value 00000000h

USB_HcFmNumber Register Map

313029282726252423222120191817161514131211109876543210

RSVD FN

USB_HcFmNumber Bit Descriptions

Bit Name Description

31:16 RSVD Reserved. Read as 0.

15:0 FN Frame Number. This bit is incremented when USB_HcFmRemaining (OHC Memory

Offset 38h) is reloaded. It is rolled over to 0h after FFFFh. When entering the UsbOper-

ational state, this is incremented automatically. The content is written to HCCA (OHC

Memory Offset 18h[31:8]) after the HC has incremented the Frame Number at each

frame boundary and sent a SOF, but before the HC reads the first endpoint direction in

that frame. After writing to HCCA, the HC sets the SOF bit (OHC Memory Offset

0Ch[2]).

OHC Memory Offset 40h

Type R /W

Reset Value 00000000h

USB_HcPeriodicStart Register Map

313029282726252423222120191817161514131211109876543210

RSVD PS

USB_HcPeriodicStart Bit Descriptions

Bit Name Description

31:14 RSVD Reserved. Read as 0.

13:0 PS Periodic Start. After a hardware reset, this field is cleared. Periodic Start is then set by

the HCD during the HC initialization. The value is calculated roughly as 10% off from

USB_HcFmInterval (Memory Offset 34h). A typical value is 3E67h. When

USB_HcFmRemaining (Memory Offset 38h) reaches the value specified, processing of

the Periodic Lists has priority over Control/Bulk processing. The HC therefore starts

processing the Interrupt list after completing the current control or bulk transaction that

is in progress.

AMD Geode™ CS5536 Companion Device Data Book 281

USB Controller Register Descriptions 33238G

6.4.3.18 Host Controller Low Speed Threshold (USB_HcLSThreshold)

6.4.3.19 Host Controller Root Hub Descriptor A (USB_HcRhDescriptorA)

OHC Memory Offset 44h

Type R /W

Reset Value 00000628h

USB_HcLSThreshold Register Map

313029282726252423222120191817161514131211109876543210

RSVD LST

USB_HcLSThreshold Bit Descriptions

Bit Name Description

31:12 RSVD Reserved. Read as 0.

11:0 LST LS Threshold. This field contains a value that is compared to the Frame Remaining

field (OHC Memory Offset 38h[13:0])prior to initiating a low speed transaction. The

transaction is started only if Frame Remaining is greater or equal to this field. The value

is calculated by the HCD with the consideration of transmission and setup overhead.

OHC Memory Offset 48h

Type R /W

Reset Value 10000904h

USB_HcRhDescriptorA Register Map

313029282726252423222120191817161514131211109876543210

POTPGT RSVD

NOCP

OCPM

NPS

PSM

NDP

USB_HcRhDescriptorA Bit Descriptions

Bit Name Description

31:24 POTPGT PowerOn To PowerGood Time. This byte specifies the duration the HCD waits before

accessing a powered-on port of the Root Hub.The unit of time is 2 ms. The duration is

calculated as POTPGT * 2 ms.

23:13 RSVD Reserved. Read as 0.

12 NOCP No Over Current Protection. This bit describes how the over current status for the

Root Hub ports are reported. When this bit is cleared, the Over Current Protection

Mode field (bit 11) specifies global or per-port reporting.

0: Over current status is reported collectively for all downstream ports.

1: No over current protection supported.

11 OCPM Over Current Protection Mode. This bit describes how the over current status for the

Root Hub ports are reported. This field is valid only if the NoOverCurrent Protection

field (bit 12) is cleared.

0: Over current status is reported collectively for all downstream ports.

1: Over current status is reported on a per-port basis.

10 DT Device Type (Read Only). This bit specifies that the Root Hub is not a compound

device. The Root Hub is not permitted to be a compound device.

282 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.4.3.20 Host Controller Root Hub Descriptor B (USB_HcRhDescriptorB)

This register is only reset by a power-on reset. It is written during system initialization to configure the Root Hub. These bits

should not be written during normal operation.

9NPS No Power Switching. These bits are used to specify whether power switching is sup-

ported or ports are always powered. When this bit is cleared, Power Switching Mode

(bit 8) specifies global or per-port switching.

0: Ports are power switched.

1: Ports are always powered on when the HC is powered on.

8 PSM Power Switching Mode. This bit is used to specify how the power switching of the

Root Hub ports is controlled.This field is only valid if No Power Switching (bit 9) is

cleared.

0: All ports are powered at the same time.

1: Each port is powered individually.This mode allows port power to be controlled by

either the global switch or per-port switching. If Port Power Control Mask (OHC Memory

Offset 4Ch[20:17]) is set, the port responds only to port power commands (Set/Clear-

PortPower). If the port mask is cleared, then the port is controlled only by the global

power switch (Set/ClearGlobalPower).

7:0 NDP (RO) Number Downstream Ports (Read Only). These bits specify the number of down-

stream ports supported by the Root Hub.

OHC Memory Offset 4Ch

Type R /W

Reset Value 00000000h

USB_HcRhDescriptorA Bit Descriptions (Continued)

Bit Name Description

USB_HcRhDescriptorB Register Map

313029282726252423222120191817161514131211109876543210

RSVD PPCM RSVD DR

RSVD

USB_HcRhDescriptorB Bit Descriptions

Bit Name Description

31:21 RSVD Reserved. Read as 0.

20:17 PPCM Port Power Control Mask. Each bit indicates if a port is affected by a global power

control command when Power Switching Mode is set (OHC Memory Offset 48h[8] = 1).

When set, the port’s power state is only affected by per-port power control (Set/Clear-

PortPower). When cleared, the port is controlled by the global power switch (Set/Clear-

GlobalPower). If the device is configured to global switching mode

(PowerSwitchingMode = 0), this field is not valid.

Bit 17: Ganged-power mask on Port #1

Bit 18: Ganged-power mask on Port #2

Bit 19: Ganged-power mask on Port #3

Bit 20: Ganged-power mask on Port #4

16:5 RSVD Reserved. Read as 0.

AMD Geode™ CS5536 Companion Device Data Book 283

USB Controller Register Descriptions 33238G

6.4.3.21 Host Controller Root Hub Status (USB_HcRhStatus)

This register is reset by the UsbReset state.

Note: Read back are 0s.

4:1 DR Device Removeable. Each bit is dedicated to a port of the Root Hub. When cleared,

the attached device is removable. When set, the attached device is not removable.

Bit 1: Device attached to Port #1

Bit 2: Device attached to Port #2

Bit 3: Device attached to Port #3

Bit 4: Device attached to Port #4

0 RSVD Reserved. Read as 0.

OHC Memory Offset 50h

Type R /W

Reset Value 00000000h

USB_HcRhDescriptorB Bit Descriptions (Continued)

Bit Name Description

USB_HcRhStatus Register Map

313029282726252423222120191817161514131211109876543210

CRWE

RSVD

CCIC

LPSC

DRWE

RSVD

OCI

LPS

USB_HcRhStatus Bit Descriptions

Bit Name Description

31 CRWE Clear Remote Wakeup Enable. Writing a 1 to this bit clears Device Remote Wakeup

Enable (bit 15). Writing 0 has no effect.

30:18 RSVD Reserved. Read as 0.

17 CCIC Over Current Indicator Change. This bit is set by hardware when a change has

occurred to the OCI field (bit 1). The HCD clears this bit by writing a 1. Writing 0 has no

effect.

16 LPSC Read: Local Power Status Change. The Root Hub does not support the local power

status feature; thus, this bit is always read as 0.

Write: Set Global Power. In global power mode (Power Switching Mode = 0) (OHC

Memory Offset 48h[8] = 0), this bit is written to 1 to turn on power to all ports (clear

PortPowerStatus). In per-port power mode, it sets Port Power Status (OHC Memory

Offset 58h[8]) only on ports whose PortPowerControlMask bit (OHC Memory Offset

4Ch[20:17]) is not set. Writing 0 has no effect.

15 DRWE Read: Device Remote Wakeup Enable. This bit enables a Connect Status Change bit

(OHC Memory Offset 54h[16]) as a resume event, causing a UsbSuspend to UsbRe-

sume state transition and setting the Resume Detected interrupt.

0: ConnectStatusChange is not a remote wakeup event.

1: ConnectStatusChange is a remote wakeup event.

Write: Set Remote Wakeup Enable. Writing a 1 sets Device Remote Wakeup Enable.

Writing 0 has no effect.

14:2 RSVD Reserved. Read as 0.

1OCI Over Current Indicator. This bit reports over current conditions when the global

reporting is implemented. When set, an over current condition exists. When cleared, all

power operations are normal. If per-port over current protection is implemented this bit

is always 0.

284 AMD Geode™ CS5536 Companion Device Data Book

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33238G

6.4.3.22 Host Controller Root Hub Port Status 1 (USB_HcRhPortStatus[1])

0LPS Read: Local Power Status. The Root Hub does not support the local power status fea-

ture; thus, this bit is always read as 0.

Write: Clear Global Power. In global power mode (Power Switching Mode = 0) (OHC

Memory Offset 48h[8] = 0), this bit is written to 1 to turn off power to all ports (clear Port

Power Status (Memory Offset 54h[8])). In per-port power mode, it clears Port Power

Status only on ports whose Port Power Control Mask (Memory Offset 4Ch[20:17] bit is

not set. Writing 0 has no effect.

OHC Memory Offset 54h

Type R /W

Reset Value 00000000h

USB_HcRhStatus Bit Descriptions (Continued)

Bit Name Description

USB_HcRhPortStatus[1] Register Map

313029282726252423222120191817161514131211109876543210

RSVD

PRSC

OCIC

PSSC

PESC

CSC

RSVD

LSDA

PPS

RSVD

PRS

POCI

PSS

PES

CCS

USB_HcRhPortStatus[1] Bit Descriptions

Bit Name Description

31:21 RSVD Reserved. Read as 0.

20 PRSC Port Reset Status Change. This bit is set at the end of the 10 ms port reset signal.

The HCD writes a 1 to clear this bit. Writing 0 has no effect.

0: Port reset is not complete.

1: Port reset is complete.

19 OCIC Port Over Current Indicator Change. This bit is valid only if over current conditions

are reported on a per-port basis. This bit is set when Root Hub changes the Port Over

Current Indicator bit (bit 3). The HCD writes a 1 to clear this bit. Writing 0 has no effect.

0: No change in Port Over Current Indicator.

1: Port Over Current Indicator has changed.

18 PSSC Port Suspend Status Change. This bit is set when the full resume sequence has been

completed. This sequence includes the 20 ms resume pulse, LS EOP, and 3 ms resy-

chronization delay. The HCD writes a 1 to clear this bit. Writing 0 has no effect. This bit

is also cleared when Port Reset Status Change (bit 20) is set.

0: Port is not resumed.

1: Port resume is complete.

17 PESC Port Enable Status Change. This bit is set when hardware events cause the Port

Enable Status bit (bit 1) to be cleared. Changes from the HCD writes do not set this bit.

The HCD writes a 1 to clear this bit. Writing 0 has no effect.

0: No change in Port Enable Status.

1: Change in Port Enable Status.

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USB Controller Register Descriptions 33238G

16 CSC Connect Status Change. This bit is set whenever a connect or disconnect event

occurs. The HCD writes a 1 to clear this bit. Writing 0 has no effect. If Current Connect

Status (bit 0) is cleared when a Set Port Reset, Set Port Enable, or Set Port Suspend

(bits [4, 1, 2]) write occurs, this bit is set to force the driver to re-evaluate the connection

status since these writes should not occur if the port is disconnected.

0: No change in Current Connect Status.

1: Change in Current Connect Status.

15:10 RSVD Reserved. Read as 0.

9LSDA Read: Low Speed Device Attached. This bit indicates the speed of the device

attached to this port. When set, a low speed device is attached to this port. When clear,

a full speed device is attached to this port. This field is valid only when the Current Con-

nect Status (bit 0) is set.

0: Full speed device attached.

1: Low speed device attached.

Write: Clear Port Power. The HCD clears the Port Power Status bit (bit 8) by writing a

1 to this bit. Writing 0 has no effect.

8 PPS Read: Port Power Status. This bit reflects the ports power status, regardless of the

type of power switching implemented. This bit is cleared if an over current condition is

detected. The HCD sets this bit by writing Set Port Power (bit 8) or Set Global Power

(OHC Memory Offset 50h[16]). The HCD clears this bit by writing Clear Port Power (bit

9) or ClearGlobalPower (OHC Memory Offset 50h[0]). Which power control switches

are enabled is determined by Power Switching Mode and Port Control Mask (OHC

Memory Offset 48h[8] and OHC Memory Offset [20:17]). In global switching mode

(Power Switching Mode = 0), only Set/ClearGlobalPower controls this bit. In per-port

power switching (Power Switching Mode = 1), if the Port Power Control Mask bit for the

port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only

Set/ClearGlobalPower commands are enabled. When port power is disabled, Current

Connect Status, Port Enable Status, Port Suspend Status, and Port Reset Status (bits

[0,1,2,4]) should be reset.

0: Port power is off.

1: Port power is on.

Write: Set Port Power. The HCD writes a 1 to set the Port Power Status bit. Writing 0

has no effect.

7:5 RSVD Reserved. Read as 0.

4PRS Read: Port Reset Status. When this bit is set by a write to Set Port Reset (bit 4), port

reset signaling is asserted. When reset is completed, this bit is cleared when Port

Reset Status Change (bit 20) is set. This bit cannot be set if Current Connect Status (bit

0) is cleared.

0: Port reset signal is not active.

1: Port reset signal is active.

Write: Set Port Reset. The HCD sets the port reset signaling by writing a 1 to this bit.

Writing 0 has no effect. If Current Connect Status (bit 0) is cleared, this write does not

set Port Reset Status (bit 4), but instead sets Connect Status Change (bit 16). This

informs the driver that it attempted to reset a disconnected port.

USB_HcRhPortStatus[1] Bit Descriptions (Continued)

Bit Name Description

286 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

3POCI Read: Port Over Current Indicator. This bit is only valid when the Root Hub is config-

ured in such a way that over current conditions are reported on a per-port basis. If per-

port over current reporting is not supported, this bit is set to 0. If cleared, all power

operations are normal for this port. If set, an over current condition exists on this port.

This bit always reflects the over current input signal.

0: No over current condition.

1: Over current condition detected.

Write: Clear Port Suspend. The HCD writes a 1 to initiate a resume. Writing 0 has no

effect. A resume is initiated only if Port Suspend Status (bit 2) is set.

2 PSS Read: Port Suspend Status. This bit indicates that the port is suspended or in the

resume sequence. It is set by a Set Port Suspend (bit 3) write and cleared when Port

Suspend Status Change (bit 18) is set at the end of the resume interval. This bit cannot

be set if Current Connect Status (bit 0) is cleared. This bit is also cleared when Port

Reset Status Change (bit 20) is set at the end of the port reset or when the HC is

placed in the UsbResume state. If an upstream resume is in progress, it should propa-

gate to the HC.

0: Port is not suspended.

1: Port is suspended.

Write: Set Port Suspend. The HCD sets Port Suspend Status (bit 2) by writing a 1 to

this bit. Writing 0 has no effect. If Current Connect Status (bit 0) is cleared, this write

does not set Port Suspend Status; instead it sets Connect Status Change (bit 16). This

informs the driver that it attempted to suspend a disconnected port.

1 PES Read: Port Enable Status. This bit indicates whether the port is enabled or disabled.

The Root Hub may clear this bit when an over current condition, disconnect event,

switched-off power, or operational bus error such as babble is detected. This change

also causes Port Enabled Status Change (bit 17) to be set. HCD sets this bit by writing

Set Port Enable (bit 1) and clears it by writing Clear Port Enable (bit 0). This bit cannot

be set when Current Connect Status (bit 0) is cleared. This bit is also set, if not already,

at the completion of a port reset when Port Reset Status Change (bit 20) is set or port

suspend when Port Suspend Status Change (bit 18) is set.

0: Port is disabled.

1: Port is enabled.

Write: Set PortEnable. The HCD sets Port Enable Status (bit 1) by writing a 1. Writing

0 has no effect. If Current Connect Status (bit 0) is cleared, this write does not set Port

Enable Status (bit 1), but instead sets Connect Status Change (bit 16). This informs the

driver that it attempted to enable a disconnected port.

0 CCS Read: Current Connect Status. This bit reflects the current state of the downstream

port.

0: No device connected.

1: Device connected.

Write: Clear Port Enable. The HCD writes a 1 to this bit to clear Port Enable Status

(bit 1). Writing 0 has no effect. The Current Connect Status (bit 0) is not affected by any

write.

USB_HcRhPortStatus[1] Bit Descriptions (Continued)

Bit Name Description

AMD Geode™ CS5536 Companion Device Data Book 287

USB Controller Register Descriptions 33238G

6.4.3.23 Host Controller Root Hub Port Status 2 (USB_HcRhPortStatus[2])

OHC Memory Offset 58h

Type R /W

Reset Value 00000000h

USB_HcRhPortStatus[2] Register Map

313029282726252423222120191817161514131211109876543210

RSVD

PRSC

OCIC

PSSC

PESC

CSC

RSVD

LSDA

PPS

RSVD

PRS

POCI

PSS

PES

CCS

USB_HcRhPortStatus[2] Bit Descriptions

Bit Name Description

31:21 RSVD Reserved. Read as 0.

20 PRSC Port Reset Status Change. This bit is set at the end of the 10 ms port reset signal.

The HCD writes a 1 to clear this bit. Writing 0 has no effect.

0: Port reset is not complete.

1: Port reset is complete.

19 OCIC Port Over Current Indicator Change. This bit is valid only if over current conditions

are reported on a per-port basis. This bit is set when Root Hub changes the Port Over

Current Indicator bit (bit 3). The HCD writes a 1 to clear this bit. Writing 0 has no effect.

0: No change in Port Over Current Indicator.

1: Port Over Current Indicator has changed.

18 PSSC Port Suspend Status Change. This bit is set when the full resume sequence has been

completed. This sequence includes the 20 ms resume pulse, LS EOP, and 3 ms resy-

chronization delay. The HCD writes a 1 to clear this bit. Writing 0 has no effect. This bit

is also cleared when Port Reset Status Change (bit 20) is set.

0: Port is not resumed.

1: Port resume is complete.

17 PESC Port Enable Status Change. This bit is set when hardware events cause Port Enable

Status (bit 1) to be cleared. Changes from the HCD writes do not set this bit. The HCD

writes a 1 to clear this bit. Writing 0 has no effect.

0: No change in Port Enable Status.

1: Change in Port Enable Status.

16 CSC Connect Status Change. This bit is set whenever a connect or disconnect event

occurs. The HCD writes a 1 to clear this bit. Writing 0 has no effect. If Current Connect

Status (bit 0) is cleared when a Set Port Enable, Set Port Suspend, or Set Port Reset

(bits [1,2,4]) write occurs, this bit is set to force the driver to re-evaluate the connection

status since these writes should not occur if the port is disconnected.

0: No change in Current Connect Status.

1: Change in Current Connect Status.

15:10 RSVD Reserved. Read as 0.

9LSDA Read: Low Speed Device Attached. This bit indicates the speed of the device

attached to this port. When set, a low speed device is attached to this port. When clear,

a full speed device is attached to this port. This field is valid only when Current Connect

Status (bit 0) is set.

0: Full speed device attached.

1: Low speed device attached.

Write: Clear Port Power. The HCD clears the Port Power Status bit (bit 8) by writing a

1 to this bit. Writing 0 has no effect.

288 AMD Geode™ CS5536 Companion Device Data Book

USB Controller Register Descriptions

33238G

8 PPS Read: Port Power Status. This bit reflects the ports power status, regardless of the

type of power switching implemented. This bit is cleared if an over current condition is

detected. HCD sets this bit by writing Set Port Power (bit 8) or Set Global Power (OHC

Memory Offset 50h[16]). HCD clears this bit by writing Clear Port Power (bit 9) or Clear

Global Power (OHC Memory Offset 50h[0]). Which power control switches are enabled

is determined by Power Switching Mode (OHC Memory Offset 48h[8]) and Port Power

Control Mask (OHC Memory Offset 4Ch[20:17]). In global switching mode (Power

Switching Mode = 0), only Set/ClearGlobalPower controls this bit. In per-port power

switching (Power Switching Mode = 1), if the Port Power Control Mask bit for the port is

set, only Set/ClearPortPower commands are enabled. If the mask is not set, only

Set/ClearGlobalPower commands are enabled. When port power is disabled, Current

Connect Status, Port Enable Status, Port Suspend Status, and Port Reset Status (bits

[0,1,2,4]) should be reset.

0: Port power is off.

1: Port power is on.

Write: Set Port Power. The HCD writes a 1 to set Port Power Status (bit 8). Writing 0