DRAM MODULE KMM53632000BK/BKG
KMM53632000BK/BKG Fast Page Mode
32M x 36 DRAM SIMM Using 16Mx4 & 16Mx1, 4K Refresh, 5V
The Samsung KMM53632000B is a 32Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53632000B consists of sixteen CMOS 16Mx4bits and
eight CMOS 16Mx1bit DRAMs in SOJ packages mounted on
a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling
capacitor is mounted on the printed circuit board for each
DRAM. The KMM53632000B is a Single In-line Memory Mod-
ule with edge connections and is intended for mounting into
72 pin edge connector sockets.
• Part Identification
- KMM53632000BK(4K cycles/64ms Ref, SOJ, Solder)
- KMM53632000BKG(4K cycles/64ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDpin & pinout
• PCB : Height(1420mil), double sided component
GENERAL DESCRIPTION FEATURES
PERFORMANCE RANGE
Speed tRAC tCAC tRC tPC
-5 50ns 13ns 90ns 35ns
-6 60ns 15ns 110ns 40ns
PIN NAMES
Pin Name Function
A0 - A11 Address Inputs
DQ0 - 35 Data In/Out
WRead/Write Enable
RAS0 - RAS3 Row Address Strobe
CAS0 - CAS3 Column Address Strobe
PD1 -PD4 Presence Detect
Vcc Power(+5V)
Vss Ground
NC No Connection
PRESENCE DETECT PINS (Optional)
Pin 50NS 60NS
PD1
PD2
PD3
PD4
NC
Vss
Vss
Vss
NC
Vss
NC
NC
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS3
RAS2
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE KMM53632000BK/BKG
FUNCTIONAL BLOCK DIAGRAM
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
CAS0
RAS0 U0
Vcc
Vss
0.1 or 0.22uF Capacitor
for each DRAM
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U1
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U3
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U4
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U6
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U7
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U9
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
WA0-A11
U10
To all DRAMs
CAS1
CAS2
RAS2
CAS3
W
A0-A11
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
CAS0
RAS1
U12
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U13
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U15
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U16
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U18
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U19
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U21
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4 WA0-A11
U22
CAS1
CAS2
RAS3
CAS3
DQ0~DQ3
DQ4~DQ7
DQ9~DQ12
DQ13~DQ16
DQ18~DQ21
DQ22~DQ25
DQ27~DQ30
DQ31~DQ34
CAS
RAS
DQ8
D
Q
WA0-A11
U2 CAS
RAS
D
QWA0-A11
U14
CAS
RAS
DQ17
D
Q
WA0-A11
U5 CAS
RAS
D
QWA0-A11
U17
CAS
RAS
DQ26
D
Q
WA0-A11
U8 CAS
RAS
D
QWA0-A11
U20
CAS
RAS
DQ35
D
Q
WA0-A11
U11 CAS
RAS
D
QWA0-A11
U23
DRAM MODULE KMM53632000BK/BKG
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Fast page mode cycle time, tPC.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item Symbol Rating Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
Pd
IOS
-1 to +7.0
-1 to +7.0
-55 to +125
24
50
V
V
°C
W
mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
*1 : VCC+2.0V at pulse width≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width≤20ns, which is measured at VSS.
Item Symbol Min Typ Max Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
4.5
0
2.4
-1.0*2
5.0
0
-
-
5.5
0
VCC*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
I(IL)
I(OL)
VOH
VOL
Symbol Speed KMM53632000BK/BKG Unit
Min Max
ICC1 -5
-6 -
-1344
1224 mA
mA
ICC2 Don′t care -48 mA
ICC3 -5
-6 -
-1344
1224 mA
mA
ICC4 -5
-6 -
-904
784 mA
mA
ICC5 Don′t care -24 mA
ICC6 -5
-6 -
-1344
1224 mA
mA
II(L)
IO(L) Don′t care -10
-10 10
10 uA
uA
VOH
VOL Don′t care 2.4
--
0.4 V
V
: Operating Current * ( RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @ tRC=min)
: Input Leakage Current (Any input 0≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc)
: Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (I OL = 4.2mA)
DRAM MODULE KMM53632000BK/BKG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item Symbol Min Max Unit
Input capacitance[A0-A11]
Input capacitance[W]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
CIN1
CIN2
CIN3
CIN4
CDQ
-
-
-
-
-
130
178
52
52
17
pF
pF
pF
pF
pF
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter Symbol -5 -6 Unit Note
Min Max Min Max
Random read or write cycle time tRC 90 110 ns
Access time from RAS tRAC 50 60 ns 3,4,10
Access time from CAS tCAC 13 15 ns 3,4,5
Access time from column address tAA 25 30 ns 3,10
CAS to output in Low-Z tCLZ 0 0 ns 3
Output buffer turn-off delay tOFF 013 0 15 ns 6
Transition time(rise and fall) tT150 1 50 ns 2
RAS precharge time tRP 30 40 ns
RAS pulse width tRAS 50 10K 60 10K ns
RAS hold time tRSH 13 15 ns
CAS hold time tCSH 50 60 ns
CAS pulse width tCAS 13 10K 15 10K ns
RAS to CAS delay time tRCD 20 37 20 45 ns 4
RAS to column address delay time tRAD 15 25 15 30 ns 10
CAS to RAS precharge time tCRP 5 5 ns
Row address set-up time tASR 0 0 ns
Row address hold time tRAH 10 10 ns
Column address set-up time tASC 0 0 ns
Column address hold time tCAH 10 10 ns
Column address to RAS lead time tRAL 25 30 ns
Read command set-up time tRCS 0 0 ns
Read command hold referenced to CAS tRCH 0 0 ns 8
Read command hold referenced to RAS tRRH 0 0 ns 8
Write command hold time tWCH 10 10 ns
Write command pulse width tWP 10 10 ns
Write command to RAS lead time tRWL 15 15 ns
Write command to CAS lead time tCWL 13 15 ns
Data set-up time tDS 0 0 ns 9
Data hold time tDH 10 10 ns 9
Refresh period tREF 64 64 ms
Write command set-up time tWCS 0 0 ns 7
CAS setup time(CAS-before-RAS refresh) tCSR 5 5 ns
CAS hold time(CAS-before-RAS refresh) tCHR 10 10 ns
RAS to CAS precharge time tRPC 5 5 ns
Access time from CAS precharge tCPA 30 35 ns 3
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
DRAM MODULE KMM53632000BK/BKG
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V ih/Vil. VIH(min) and V IL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter Symbol -5 -6 Unit Note
Min Max Min Max
Fast page mode cycle time tPC 35 40 ns
CAS precharge time(Fast page cycle) tCP 10 10 ns
RAS pulse width(Fast page cycle) tRASP 50 200K 60 200K ns
W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns
W to RAS hold time(C-B-R refresh) tWRH 10 10 ns
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
DRAM MODULE KMM53632000BK/BKG
tCRP
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tRRH tRCH
Don′t care
Undefined
tRCS
tOFF
DRAM MODULE KMM53632000BK/BKG
tWCS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
tWP
tDS tDH
tWCH
tCWL
tRWL
Don′t care
DATA-IN
Undefined
DRAM MODULE KMM53632000BK/BKG
tOED
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
DATA-IN
tWP
Don′t care
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tCWL
tRWL
tDS tDH
tOEH
Undefined
DRAM MODULE KMM53632000BK/BKG
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ
ROW
ADDR
tRAS tRWC tRP
tRSHtRCD tCAS
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
VALID
tWP
Don′t care
READ - MODIFY - WRTIE CYCLE
tRWL
tCWL
tOEZ
tOEA
tOED
tAWD
tCWD
tRWD
DATA-OUT
Undefined
VALID
DATA-IN
tRAC
tAA tCAC
tCLZ
tDS tDH
COLUMN
ADDRESS
DRAM MODULE KMM53632000BK/BKG
tRCH
tOEZ
tCLZ
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tASC
tRAD
tASR tRAH
tASC
tCAH
tCRP
VALID
Don′t care
FAST PAGE READ CYCLE
tOEZ
tRRH
DATA-OUT
Undefined
VALID
DATA-OUT
NOTE : D OUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tRCH
¡ó
tRCS tRCStRCS
tOEA
tCAC tOEA
tCAC tOEA
tCAC
VALID
DATA-OUT
tCLZ
tOFF
tAA tOFF
tAA
tCLZ tOFF
tOEZ
tRAC
tAA
¡ó
¡ó
tCP
tCAS
tRP
tCP
DRAM MODULE KMM53632000BK/BKG
tASC
tCAH
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tRAD
tASR tRAH
tASC
tCRP
VALID
Don′t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
tDS
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tWCS tWCH
tWCS
VALID
DATA-IN
¡ó
¡ó
tWP
tCWL
tWP
tWCH
tWP
tWCS tWCH
tCWL
tRWL
tCWL
tDH tDS tDH tDS tDH
¡ó
¡ó
¡ó
tRP
tCP
tCP
tCAS
tPC
DRAM MODULE KMM53632000BK/BKG
tCAC
tASCtASC
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ
ROW
ADDR
tCSH tRASP
tASR
VALID
Don′t care
FAST PAGE READ - MODIFY - WRITE CYCLE
DATA-OUT
Undefined
tRCD tCP
tRAD
tCAH
tWP
tDH
COL.
ADDR COL.
ADDR
tCAS tCAS
tCRP
tCAH tRAL
tPRWC
tRCS tCWL
tCWD
tAWD
tRWD
tWP
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
VALID
DATA-IN VALID
DATA-OUT VALID
DATA-IN
tCLZ
tDS
tOEA
tAA tDH
tDS
tOEZ
tOED
tRWL
tRP
tRSH
tRAH
DRAM MODULE KMM53632000BK/BKG
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - ROW
ADDR
tRAS tRC tRP
tASR tRAH
tCRP
Don′t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRPC tCRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tWRP
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
VOH -
VOL -
DQ OPEN
DRAM MODULE KMM53632000BK/BKG
tWRH
tOFF
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHRtRCD
tRAD
tASR tRAH tASC tCAH
tCRP
tRCS
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
tRRH
Don′t care
tRSH
tOEZ
tWRP
Undefined
tRC
DATA-OUT
tRP tRP
tRAS
DRAM MODULE KMM53632000BK/BKG
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHR
tRCD
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
tRSH
DATA-IN
tWRP
tWRH
Undefined
tRC
NOTE : DOUT = OPEN
tWCH
tWP
tDH
tRPtRP tRAS
tDS
tWCS
DRAM MODULE KMM53632000BK/BKG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - COLUMN
ADDRESS
tRAS
tRSH
tCHR
tRAL
tCSR tCPT
tRP
tCAS
tASC tCAH
READ CYCLE
VOH -
VOL - DATA-OUT
DQ
tOFF
tCLZ
WRITE CYCLE
VIH -
VIL - DATA-IN
DQ
tDH
tDS
WVIH -
VIL - tWP
tCWD
tCWL
tRWL
READ-MODIFY-WRITE tAWD
VIH -
VIL -
OE
tOEA
tAA
tCAC
tDS
tDH
VALID
DATA-OUT
VI/OH -
VI/OL -
DQ
Don′t care
Undefined
VIH -
VIL -
OE
tOEA tOEZ
OE VIH -
VIL -
tRCS
tCLZ tOEZ
tOED
tWRP tWRH tRRH
tRCH
tRCS tCAC
tAA
VIH -
VIL -
W
tWRP tWRH
tWCS tWCH
tCWL
VIH -
VIL -
W
tWP
tRWL
tWRP tWRH
VALID
DATA-IN
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
DRAM MODULE KMM53632000BK/BKG
Don′t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRASS tRPS
tRPC
tWRP
tCHS
tRP
tCP
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
OPEN
VOH -
VOL -
DQ
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tRPC
tWTS
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWTH
tOFF
OPEN
VOH -
VOL -
DQ
DRAM MODULE KMM53632000BK/BKG
PACKAGE DIMENSIONS
.133(3.38)
4.250(107.95)
3.984(101.19)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
.250(6.35)
Units : Inches (millimeters)
Gold/Solder Plating Lead
.010(.25)MAX
.050(1.27) .041±.004(1.04±.10)
.100(2.54)
MIN
.350(8.89)
MAX
.054(1.37)
Tolerances : ±.005(.13) unless otherwise specified
1.420(36.07)
.400(10.16)
.125 DIA±.002(3.18±.051)R.062(1.57)
.250(6.35)
.080(2.03)
.047(1.19)
( Back view )
( Front view )
NOTE : The used device is 16Mx4 DRAM & 16Mx1 DRAM, SOJ
DRAM Part No. : KMM53632000BK/BKG -- KM44C16100BK
KM41C16000CK
