Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 5 1Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D–type flip–flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is locked out and
information present will not be transferred to the outputs until the
next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
•Outputs Source/Sink 24 mA
•′ACT74 Has TTL Compatible Inputs
CP1CD2
CP2
1314 12 11 10 9 8
21 34567
VCC
CD1 D1CP1SD1 Q1Q1
CD2 D2CP2SD2 Q2Q2
CD1
SD1
Q1
D1
SD2Q2
Q2
D2
GND
Q1
Figure 1. Pinout: 14–Lead Packages Conductors
(Top V iew)
PIN ASSIGNMENT
PIN FUNCTION
D1, D2Data Inputs
CP1, CP2Clock Pulse Inputs
CD1, CD2 Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q 1, Q2, Q2Outputs
TSSOP–14
DT SUFFIX
CASE 948G
1
14
EIAJ–14
M SUFFIX
CASE 965
1
14
SO–14
D SUFFIX
CASE 751A
http://onsemi.com
1
14
1
14
PDIP–14
N SUFFIX
CASE 646
Device Package Shipping
ORDERING INFORMATION
MC74AC74DT TSSOP–14 96 Units/Rail
MC74AC74DTR2 TSSOP–14 2500 Tape & Reel
MC74ACT74DT TSSOP–14 96 Units/Rail
MC74ACT74DTR2 TSSOP–14 2500 Tape & Reel
MC74AC74N PDIP–14 25 Units/Rail
MC74AC74D SOIC–14 55 Units/Rail
MC74ACT74N PDIP–14 25 Units/Rail
MC74AC74DR2 SOIC–14 2500 Tape & Reel
MC74ACT74D SOIC–14 55 Units/Rail
MC74ACT74DR2 SOIC–14 2500 Tape & Reel
MC74AC74M EIAJ–14 50 Units/Rail
MC74AC74MEL EIAJ–14 2000 Tape & Reel
MC74ACT74M EIAJ–14 50 Units/Rail
MC74ACT74MEL EIAJ–14 2000 Tape & Reel
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
MC74AC74, MC74ACT74
http://onsemi.com
2
TRUTH TABLE (Each Half)
Inputs Outputs
SDCDCP D Q Q
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q0Q0
NOTE: H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH
T ransition of Clock Figure 2. Logic Symbol
SD1
Q1
CP1
Q1
CD1
SD2
Q2
D2CP2
Q2
CD2
D1
SD
D
CP
CD
Q
Q
Figure 3. Logic Diagram
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Sink/Source Current, per Pin ±50 mA
ICC DC VCC or GND Current per Output Pin ±50 mA
Tstg Storage Temperature –65 to +150 °C
*Maximum Ratings are those values beyond which damage to the device may occur . Functional operation should be restricted to the Recom-
mended Operating Conditions.
MC74AC74, MC74ACT74
http://onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
Supply Voltage
′AC 2.0 5.0 6.0
V
VCC Supply Voltage ′ACT 4.5 5.0 5.5 V
Vin, Vout DC Input V oltage, Output Voltage (Ref. to GND) 0 – VCC V
VCC @ 3.0 V – 150 –
tr, tfInput Rise and Fall Time (Note )
′
AC Devices exce
p
t Schmitt In
p
uts
VCC @ 4.5 V – 40 – ns/V
r,f
′AC
Devices
except
Schmitt
Inputs
VCC @ 5.5 V – 25 –
tt
f
Input Rise and Fall Time (Note ) VCC @ 4.5 V – 10 –
ns/V
tr, tf
In ut
Rise
and
Fall
Time
(Note
)
′ACT Devices except Schmitt Inputs VCC @ 5.5 V – 8.0 – ns/V
TJJunction Temperature (PDIP) – – 140 °C
TAOperating Ambient Temperature Range –40 25 85 °C
IOH Output Current – High – – –24 mA
IOL Output Current – Low – – 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that dif fer from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC 74AC
Symbol Parameter VCC
(V) TA = +25°CTA =
–40°C to
+85°CUnit Conditions
Typ Guaranteed Limits
VIH Minimum High Level 3.0 1.5 2.1 2.1 VOUT = 0.1 V
g
Input Voltage 4.5 2.25 3.15 3.15 V or VCC – 0.1 V
5.5 2.75 3.85 3.85
VIL Maximum Low Level 3.0 1.5 0.9 0.9 VOUT = 0.1 V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC – 0.1 V
5.5 2.75 1.65 1.65
VOH Minimum High Level 3.0 2.99 2.9 2.9 IOUT = –50 µA
g
Output Voltage 4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
*VIN = VIL or VIH
3.0 – 2.56 2.46
V
–12 mA
4.5 – 3.86 3.76
V
IOH –24 mA
5.5 – 4.86 4.76 –24 mA
VOL Maximum Low Level 3.0 0.002 0.1 0.1 IOUT = 50 µA
Output Voltage 4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
*VIN = VIL or VIH
3.0 – 0.36 0.44
V
12 mA
4.5 – 0.36 0.44
V
IOL 24 mA
5.5 – 0.36 0.44 24 mA
IIN Maximum Input
55
–
±01
±10
µA
VI=V
CC GND
Leakage Current 5.5 – ±
0
.
1
±
1
.
0
µ
A
V
I =
V
CC,
GND
IOLD †Minimum Dynamic
Ot tC t
5.5 – – 75 mA VOLD = 1.65 V Max
IOHD Output Current 5.5 – – –75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
55
–
40
40
µA
VIN =V
CC or GND
Q
Supply Current 5.5 –
4
.
0
40
µ
A
V
IN =
V
CC or
GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
MC74AC74, MC74ACT74
http://onsemi.com
4
AC CHARACTERISTICS (For Figures and W aveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC 74AC
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Min Typ Max Min Max
fmax
Maximum Clock 3.3 100 125 – 95 –
MHz
3
–
3
f
max Frequency 5.0 140 160 – 125 –
MH
z
3
–
3
tPLH
Propagation Delay 3.3 5.0 8.0 12.5 4.0 13.0
ns
3
–
6
tPLH
gy
CDn or SDn to Qn or Qn5.0 3.5 6.0 9.0 3.0 10.0 ns
3
–
6
tPHL
Propagation Delay 3.3 4.0 10.5 12.0 3.5 13.5
ns
3
–
6
tPHL
gy
CDn or SDn to Qn or Qn5.0 3.0 8.0 9.5 2.5 10.5 ns
3
–
6
tPLH
Propagation Delay 3.3 4.5 8.0 13.5 4.0 16.0
ns
3
–
6
tPLH
gy
CPn to Qn or Qn5.0 3.5 6.0 10.0 3.0 10.5 ns
3
–
6
tPHL
Propagation Delay 3.3 3.5 8.0 14.0 3.5 14.5
ns
3
–
6
tPHL
gy
CPn to Qn or Qn5.0 2.5 6.0 10.0 2.5 10.5 ns
3
–
6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74AC 74AC
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Typ Guaranteed Minimum
ts
Set-up Time, HIGH or LOW 3.3 1.5 4.0 4.5
ns
3–9
tsDn to CPn5.0 1.0 3.0 3.0 ns
3
–
9
th
Hold T ime, HIGH or LOW 3.3 –2.0 0.5 0.5
ns
3–9
thDn to CPn5.0 –1.5 0.5 0.5 ns
3
–
9
tw
CPn or CDn or SDn 3.3 3.0 5.5 7.0
ns
3–6
twPulse Width 5.0 2.5 4.5 5.0 ns
3
–
6
trec
Recovery TIme 3.3 –2.5 0 0
ns
3–9
trec CDn or SDn to CP 5.0 –2.0 0 0 ns
3
–
9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC74, MC74ACT74
http://onsemi.com
5
DC CHARACTERISTICS
74ACT 74ACT
Symbol Parameter VCC
(V) TA = +25°CTA =
–40°C to
+85°CUnit Conditions
Typ Guaranteed Limits
VIH Minimum High Level 4.5 1.5 2.0 2.0
V
VOUT = 0.1 V
g
Input Voltage 5.5 1.5 2.0 2.0
V
or VCC – 0.1 V
VIL Maximum Low Level 4.5 1.5 0.8 0.8
V
VOUT = 0.1 V
Input Voltage 5.5 1.5 0.8 0.8
V
or VCC – 0.1 V
VOH Minimum High Level 4.5 4.49 4.4 4.4
V
IOUT = –50 µA
g
Output Voltage 5.5 5.49 5.4 5.4
V
*VIN = VIL or VIH
4.5 – 3.86 3.76 V
–24 mA
5.5 – 4.86 4.76
OH –24 mA
VOL Maximum Low Level 4.5 0.001 0.1 0.1
V
IOUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
*VIN = VIL or VIH
4.5 – 0.36 0.44 V
24 mA
5.5 – 0.36 0.44
OL 24 mA
IIN Maximum Input
55
–
±01
±10
µA
VI=V
CC GND
Leakage Current 5.5 – ±
0
.
1
±
1
.
0
µ
A
V
I =
V
CC,
GND
∆ICCT Additional Max. ICC/Input 5.5 0.6 – 1.5 mA VI = VCC – 2.1 V
IOLD †Minimum Dynamic
Ot tC t
5.5 – – 75 mA VOLD = 1.65 V Max
IOHD Output Current 5.5 – – –75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
55
–
40
40
µA
VIN =V
CC or GND
Q
Supply Current 5.5 –
4
.
0
40
µ
A
V
IN =
V
CC or
GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and W aveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT 74ACT
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Min Typ Max Min Max
fmax
Maximum Clock
50
145
210
–
125
–
MHz
3–3
f
max
Maximum
Clock
Frequency 5.
0
14
5
210
–
12
5 –
MH
z
3
–
3
tPLH
Propagation Delay
50
30
55
95
25
10 5
ns
3–6
tPLH
Pro agation
Delay
CDn or SDn to Qn or Qn5.
0
3
.
0
5.5
9
.5
2
.5
10
.5 ns
3
–
6
tPHL
Propagation Delay
50
30
60
10 0
30
11 5
ns
3–6
tPHL
Pro agation
Delay
CDn or SDn to Qn or Qn5.
0
3
.
0
6
.
0
10
.
0
3
.
0
11
.5 ns
3
–
6
tPLH
Propagation Delay
50
40
75
11 0
40
13 0
ns
3–6
tPLH
Pro agation
Delay
CPn to Qn or Qn5.
0
4
.
0
7.5
11
.
0
4
.
0
13
.
0
ns
3
–
6
tPHL
Propagation Delay
50
35
60
10 0
30
11 5
ns
3–6
tPHL
Pro agation
Delay
CPn to Qn or Qn5.
0
3
.5
6
.
0
10
.
0
3
.
0
11
.5 ns
3
–
6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC74, MC74ACT74
http://onsemi.com
6
AC OPERATING REQUIREMENTS
74ACT 74ACT
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Typ Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
50
10
30
35
ns
3
–
9
tsDn to CPn5.
0
1
.
0
3
.
0
3
.5 ns
3
–
9
th
Hold T ime, HIGH or LOW
50
–
05
10
10
ns
3
–
9
thDn to CPn5.
0
–
0
.5
1
.
0
1
.
0
ns
3
–
9
tw
CPn or CDn or SDn
50
30
50
60
ns
3
–
6
twPulse Width 5.
0
3
.
0
5.
0
6
.
0
ns
3
–
6
trec
Recovery TIme
50
–
25
0
0
ns
3
–
9
trec CDn or SDn to CP 5.
0
–
2
.5
0
0
ns
3
–
9
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol Parameter Value
Typ Unit Test Conditions
CIN Input Capacitance 4.5 pF VCC = 5.0 V
CPD Power Dissipation Capacitance 35 pF VCC = 5.0 V
MC74AC74, MC74ACT74
http://onsemi.com
7
MARKING DIAGRAMS
A = Assembly Location
WL, L = W afer Lot
YY, Y = Year
WW, W = W ork Week
PDIP–14 SO–14 TSSOP–14
MC74AC74N
AWLYYWW AC74
AWLYWW AC
74
ALYW
ACT
74
ALYW
ACT74
AWLYWW
MC74ACT74N
AWLYYWW
74AC74
ALYW
EIAJ–14
74ACT74
ALYW
MC74AC74, MC74ACT74
http://onsemi.com
8
PACKAGE DIMENSIONS
PDIP–14
N SUFFIX
14 PIN PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
SO–14
D SUFFIX
14 PIN PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
MC74AC74, MC74ACT74
http://onsemi.com
9
PACKAGE DIMENSIONS
TSSOP–14
DT SUFFIX
14 PIN PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C--- 1.20 --- 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.

S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L–U–
SEATING
PLANE
0.10 (0.004)
–T–
ÇÇÇ
ÇÇÇ
SECTION N–N
DETAIL E
JJ1
K
K1
ÉÉ
ÉÉ
DETAIL E
F
M
–W–
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
–V–
14X REFK
N
N
EIAJ–14
M SUFFIX
14 PIN PLASTIC EIAJ PACKAGE
CASE 965–01
ISSUE O
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
MC74AC74, MC74ACT74
http://onsemi.com
10
Notes
MC74AC74, MC74ACT74
http://onsemi.com
11
Notes
MC74AC74, MC74ACT74
http://onsemi.com
12
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur . Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
MC74AC74/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada