General Description
The MAX6953 is a compact cathode-row display driver
that interfaces microprocessors to 5 ✕7 dot-matrix LED
displays through an I2C™-compatible serial interface.
The MAX6953 drives up to four digits (140 LEDs).
Included on-chip are an ASCII 104-character font, mul-
tiplex scan circuitry, column and row drivers, and static
RAM that stores each digit, as well as font data for 24
user-definable characters. The segment current for the
LEDs is set by an internal digit-by-digit digital bright-
ness control.
The device includes a low-power shutdown mode, seg-
ment blinking (synchronized across multiple drivers, if
desired), and a test mode that forces all LEDs on. The
LED drivers are slew-rate limited to reduce EMI.
For an SPI™-compatible version, refer to the MAX6952
data sheet. An EV kit is available for the MAX6952.
Applications
Message Boards
Medical Equipment
Industrial Displays
Audio/Video Equipment
Gaming Machines
Features
♦400kbps 2-Wire Interface Compatible with I2C
♦2.7V to 5.5V Operation
♦Drives 4 Monocolor or 2 Bicolor Cathode-Row
5 ✕7 Matrix Displays
♦Built-In ASCII 104-Character Font
♦24 User-Definable Characters Available
♦Automatic Blinking Control for Each Segment
♦70µA Low-Power Shutdown (Data Retained)
♦16-Step Digital Brightness Control
♦Display Blanked on Power-Up
♦Slew-Rate-Limited Segment Drivers for Lower EMI
♦36-Pin SSOP and 40-Pin DIP Packages
♦Extended Temperature Range as Standard
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
DIGIT 1
R1
R6
R7
C1
R4
R3
R2
R5
C2
C3
C5
C4
DIGIT 0
O0
O1
O2
O3
O4
O5
O6
O14
O15
O16
O17
O18
R1
R6
R7
C1
R4
R3
R2
R5
C2
C3
C5
C4
O0
O1
O2
O3
O4
O5
O6
O19
O20
O21
O22
O23
R1
R6
R7
C1
R4
R3
R2
R5
C2
C3
C5
C4
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
R1
R6
R7
C1
R4
R3
R2
R5
C2
C3
C5
C4
DIGIT 3
O7
O8
O9
O10
O11
O12
O13
O19
O20
O21
O22
O23
DIGIT 2
3.3V
100nF
47µF
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
ISET
OSC
V+
V+
GND
GND
BLINK
V+
GND
SDA
SCL
AD1
26pF
CSET
53.6kΩ
RSET
MAX6953
AD0
3.3V
4.7kΩ
4.7kΩ4.7kΩ
Typical Application Circuit
19-2312; Rev 3; 3/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX6953EAX -40°C to +85°C 36 SSOP
MAX6953EPL -40°C to +85°C 40 PDIP
I2C is a trademark of Philips Corp.
SPI is a trademark of Motorola, Inc.
Pin Configurations appear at end of data sheet.
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = 3.0V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with Respect to GND)
V+.............................................................................-0.3V to +6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
O0–O13 Sink Current....................................................... 500mA
O14–O23 Source Current .................................................. 50mA
Continuous Power Dissipation (TA= +70°C)
36-Pin SSOP (derate 11.8mW/°C above +70°C) .....941.2mW
40-Pin PDIP (derate 16.7mW/°C above +70°C)........1333mW
Operating Temperature Range
MAX6953E......................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Operating Supply Voltage V+ 2.7 5.5 V
TA = TMIN to TMAX
130
Shutdown Supply Current ISHDN Shutdown mode, all
digital inputs at V+
or GND TA = +25°C 70 100 µA
Operating Supply Current I+ All segments on, intensity set to full,
internal oscillator, no display load
connected, BLINK open circuit 12 15 mA
Master Clock Frequency
(OSC Internal Oscillator) fOSC OSC = RC oscillator, RSET = 53.6kΩ,
CSET = 26pF 4
MHz
Master Clock Frequency
(OSC External Clock) fOSC OSC overdriven externally 1 8
MHz
Dead Clock Protection
Frequency fOSC 90 kHz
OSC Internal/External Detection
Threshold VOSC
1.7
V
OSC High Time tCH 50 ns
OSC Low Time tCL 50 ns
Slow Segment Blink Period
(OSC Internal Oscillator)
fSLOWBLINK
OSC = RC oscillator, RSET = 53.6kΩ,
CSET = 26pF 1s
Fast Segment Blink Period
(OSC Internal Oscillator)
fFASTBLINK
OSC = RC oscillator, RSET = 53.6kΩ,
CSET = 26pF
0.5
s
Fast or Slow Segment Blink
Duty Cycle (Note 2)
49.5 50.5
%
Column Drive Source Current
ICOLUMN
VLED = 2.4V, V+ = 3.0V, TA = +25oC -32 -58 mA
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical operating circuit, V+ = 3.0V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Segment Current Slew Rate ∆ISEG/∆tT
A = +25oC
12.5
mA/µs
Segment Drive Current
Matching (Within IC) ∆ISEG TA = +25°C 4 %
LOGIC INPUTS
Input High Voltage
SDA, SCL, AD0, AD1 VIH 0.7 x
V+ V
Input Low Voltage
SDA, SCL, AD0, AD1 VIL 0.3 ✕
V+ V
Input Hysteresis
SDA, SCL, AD0, AD1 VHYST
0.05 ✕
V+ V
Input Leakage Current IIL, IIH -2 2 µA
Input Capacitance CI10 pF
DIGITAL OUTPUT
SDA Output Low Voltage VOLSDA ISINK = 4mA 0.4 V
BLINK Output Low Voltage VOLBK ISINK = 1.6mA 0.4 V
MAX6953 TIMING CHARACTERISTICS
(V+ = 2.7V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Serial Clock Frequency fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 µs
Hold Time (Repeated) START
Condition
tHD, STA
0.6 µs
Repeated START Condition
Setup Time
tSU, STA
0.6 µs
STOP Condition Setup Time
tSU
,
STO
0.6 µs
Data Hold Time
tHD
,
DAT
(Note 3) 0.9 µs
Data Setup Time
tSU
,
DAT 100
ns
SCL Clock Low Period tLOW 1.3 µs
SCL Clock High Period tHIGH 0.6 µs
Rise Time of Both SDA and SCL
Signals, Receiving tR(Notes 2, 4) 20 +
0.1CB300
ns
Fall Time of Both SDA and SCL
Signals, Receiving tF(Notes 2, 4) 20 +
0.1CB300
ns
Typical Operating Characteristics
(Typical application circuit, V+ = 3.3V, LED forward voltage = 2.4V, scan limit set to 4 digits, TA= +25°C, unless otherwise noted.)
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
4_______________________________________________________________________________________
MAX6953 TIMING CHARACTERISTICS (continued)
(V+ = 2.7V to 5.5V, TA= TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fall Time of SDA Transmitting tF(Notes 2, 5) 20 +
0.1CB250
ns
Pulse Width of Spike Suppressed
tSP (Note 6) 0 50 ns
Capacitive Load for Each
Bus Line CB(Note 2)
400
pF
Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤6mA. CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
3.80
3.90
4.10
4.00
4.20
4.30
-40 0-20 20 40 60 80
INTERNAL OSCILLATOR
FREQUENCY vs. TEMPERATURE
MAX6953 toc01
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (MHz)
V+ = 3.3V
V+ = 2.7V
V+ = 5V
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX6953 toc02
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (MHz)
4.53.5
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
3.6 2.5 5.5
0
0.5
1.5
1.0
2.0
2.5
0400
200 600 800
INTERNAL OSCILLATOR
WAVEFORM AT OSC (PIN 19 OR 21)
MAX6953 toc03
TIMELINE (ns)
VOLTAGE AT OSC (V)
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
_______________________________________________________________________________________ 5
80
85
95
90
100
105
2.5 3.53.0 4.0 4.5 5.0 5.5
DEAD CLOCK OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX6953 toc04
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (kHz)
0.95
0.97
0.96
0.99
0.98
1.00
1.01
2.5 3.5 4.03.0 4.5 5.0 5.5
OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE
MAX6953 toc05
SUPPLY VOLTAGE (V)
CURRENT NORMALIZED TO 40mA
WAVEFORMS AT O2 (PIN 3) AND O14
(PIN 28) V+ = 3.3V, 8/16 INTENSITY
GROUND FOR
ANODE
(PIN 014)
MAX6953 toc06
GROUND FOR
CATHODE
(PIN 03) 200µs/div
Typical Operating Characteristics (continued)
(Typical application circuit, V+ = 3.3V, LED forward voltage = 2.4V, scan limit set to 4 digits, TA= +25°C, unless otherwise noted.)
Pin Description
PIN
SSOP PDIP NAME FUNCTION
1, 2, 3, 6–14, 23, 24 1, 2, 3, 7–15, 26, 27 O0 to O13 LED Cathode Drivers. O0 to O13 outputs sink current from
the display’s cathode rows.
4, 5, 17 4, 5, 6, 19 GND Ground
15 17 ISET Segment Current Setting. Connect ISET to GND through
series resistor RSET to set the peak current.
16 18 AD1 Address Input 1. Sets device slave address. Connect to
either GND, V+, SCL, SDA to give four logic combinations.
See Table 3.
—16, 25 N.C. Not Connected
18 20 BLINK Blink Output. Output is open drain.
19 21 OSC Multiplex Clock Input. To use internal oscillator, connect
capacitor CSET from OSC to GND. To use external clock,
drive OSC with a 1MHz to 8MHz CMOS clock.
20 22 AD0 Address Input 0. Sets device slave address. Connect to
either GND, V+, SCL, SDA to give four logic combinations.
See Table 3.
21 23 SDA I2C-Compatible Serial Data I/O
22 24 SCL I2C-Compatible Serial Clock Input
25–31, 34, 35, 36 28–34, 38, 39, 40
O14 to O23
LED Anode Drivers. O14 to O23 outputs source current to
the display’s anode columns.
32, 33 35, 36, 37 V+ Positive Supply Voltage. Bypass V+ to GND with a 47µF
bulk capacitor and a 0.1µF ceramic capacitor.
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
6_______________________________________________________________________________________
DIGIT
O0–O6 O7–O13 O14–O18 O19-–O23
1
Digit 0 rows (cathodes) R1 to R7
Digit 1 rows (cathodes) R1 to R7
—Digit 0 columns (anodes)
C1 to C5 Digit 1 columns
(anodes) C6 to C10
2—
Digit 2 rows (cathodes) R1 to R7
Digit 3 rows (cathodes) R1 to R7 Digit 2 columns (anodes)
C1 to C5 Digit 3 columns
(anodes) C6 to C10
Table 1. Connection Scheme for Four Monocolor Digits
DIGIT
O0–O6 O7–O13 O14–023
Digit 0 columns (anodes) C1 to C10
1Digit 0 rows (cathodes)
R1 to R14 —
- the 5 green anodes -
- the 5 red anodes -
Digit 1 columns (anodes) C1 to C10
2— Digit 1 rows (cathodes)
R1 to R14
- the 5 green columns -
- the 5 red anodes -
Table 2. Connection Scheme for Two Bicolor Digits
Detailed Description
The MAX6953 is a serially interfaced display driver that
can drive four digits of 5 ✕7 cathode-row dot-matrix dis-
plays. The MAX6953 can drive either four monocolor
digits (Table 1) or two bicolor digits (Table 2). The
MAX6953 includes a 128-character font map compris-
ing 104 predefined characters and 24 user-definable
characters. The predefined characters follow the Arial
font, with the addition of the following common symbols:
£, <, ¥, °, µ, ±, ↑, and ↓. The 24 user-definable charac-
ters are uploaded by the user into on-chip RAM through
the serial interface and are lost when the device is pow-
ered down. Figure 1 is the MAX6953 functional diagram.
Serial Interface
Serial Addressing
The MAX6953 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6953, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6953 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX6953 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6953
7-bit slave address plus R/Wbit (Figure 6), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
ISET
OSC
BLINK
SCL
SDA
AD0
AD1
SERIAL INTERFACE
RAM
BLINK
SPEED
SELECT
CONFIGURATION
REGISTERS
CHARACTER
GENERATOR
ROM
CHARACTER
GENERATOR
RAM
CURRENT
SOURCE
DIVIDER/
COUNTER
NETWORK
ROW
MULTIPLEXER
PWM
BRIGHTNESS
CONTROL LED
DRIVERS O0 TO O23
Figure 1. MAX6953 Functional Diagram
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
_______________________________________________________________________________________ 7
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX6953, the
MAX6953 generates the acknowledge bit because the
MAX6953 is the recipient. When the MAX6953 is trans-
mitting to the master, the master generates the
acknowledge bit because the master is the recipient.
Slave Address
The MAX6953 has a 7-bit-long slave address (Figure
6). The eighth bit following the 7-bit slave address is
the R/Wbit. It is low for a write command, high for a
read command.
The first 3 bits (MSBs) of the MAX6953 slave address
are always 101. Slave address bits A3, A2, A1, and A0
are selected by the address input pins AD1 and AD0.
These two input pins may be connected to GND, V+,
SDA, or SCL. The MAX6953 has 16 possible slave
addresses (Table 3) and therefore a maximum of 16
MAX6953 devices may share the same interface.
Message Format for Writing
A write to the MAX6953 comprises the transmission of
the MAX6953's slave address with the R/Wbit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte, which deter-
mines which register of the MAX6953 is to be written by
the next byte, if received. If a STOP condition is detect-
ed after the command byte is received, then the
MAX6953 takes no further action (Figure 7) beyond
storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX6953 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX6953 internal registers because the
command byte address generally autoincrements
(Table 4) (Figure 9).
Message Format for Reading
The MAX6953 is read using the MAX6953's internally
stored command byte as address pointer, the same
way the stored command byte is used as address
pointer for a write. The pointer generally autoincre-
ments after each data byte is read using the same rules
as for a write (Table 4). Thus, a read is initiated by first
configuring the MAX6953's command byte by perform-
ing a write (Figure 7). The master can now read n con-
secutive bytes from the MAX6953, with the first data
byte being read from the register addressed by the ini-
tialized command byte (Figure 9). When performing
STOP
CONDITION START
CONDITION
tBUF
tSU, STO
tHD, STA
REPEATED START
CONDITION
tSU, STA
tHD, DAT
tSU, DAT
tLOW
SDA
SCL
tHIGH
START
CONDITION
tHD, STA tRtF
Figure 2. 2-Wire Serial Interface Timing Details
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
8_______________________________________________________________________________________
SDA
SCL START MSB
101A3 A2 A1 A0 R/W
LSB
ACK
Figure 6. Slave Address
SDA
SCL S
START CONDITION STOP CONDITION
P
Figure 3. Start and Stop Conditions
DATA LINE STABLE,
DATA VALID CHANGE OF DATA
ALLOWED
SDA
SCL
Figure 4. Bit Transfer
START CONDITION
1
SCL
SDA
BY TRANSMITTER
SDA
BY RECEIVER
S
289
CLOCK PULSE FOR ACKNOWLEDGMENT
Figure 5. Acknowledge
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
_______________________________________________________________________________________ 9
read-after-write verification, reset the command byte's
address because the stored byte address generally is
autoincremented after the write (Table 4).
Operation with Multiple Masters
If the MAX6953 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6953
should use a repeated start between the write, which
sets the MAX6953's address pointer, and the read(s)
that takes the data from the location(s). This is because
it is possible for master 2 to take over the bus after
master 1 has set up the MAX6953's address pointer but
before master 1 has read the data. If master 2 subse-
quently changes the MAX6953's address pointer, then
master 1's delayed read may be from an unexpected
location.
Command Address Autoincrementing
Address autoincrementing allows the MAX6953 to be
configured with the shortest number of transmissions
by minimizing the number of times the command byte
needs to be sent. The command address or the font
pointer address stored in the MAX6953 generally incre-
ments after each data byte is written or read (Table 4).
Digit Registers
The MAX6953 uses eight digit registers to store the char-
acters that the user wishes to display on the four 5 ✕7
LED digits. These digit registers are implemented with
two planes of 4 bytes, called P0 and P1. Each LED digit
is represented by 2 bytes of memory, 1 byte in plane P0
and the other in plane P1. The digit registers are mapped
so that a digit’s data can be updated in plane P0, or
plane P1, or both planes at the same time (Table 5).
If the blink function is disabled through the Blink Enable
Bit E (Table 10) in the configuration register, then the
digit register data in plane P0 is used to multiplex the
display. The digit register data in P1 is not used. If the
blink function is enabled, then the digit register data in
both plane P0 and plane P1 are alternately used to mul-
tiplex the display. Blinking is achieved by multiplexing
the LED display using data planes P0 and P1 on alter-
nate phases of the blink clock (Table 11).
The data in the digit registers does not control the digit
segments directly. Instead, the register data is used to
address a character generator, which stores the data of
a 128-character font (Table 15). The lower 7 bits of the
digit data (D6 to D0) select the character from the font.
The most-significant bit of the register data (D7) selects
whether the font data is used directly (D7 = 0) or
whether the font data is inverted (D7 = 1). The inversion
feature can be used to enhance the appearance of
bicolor displays by displaying, for example, a red char-
acter on a green background.
Display Blink Mode
The display blinking facility, when enabled, makes the
driver flip automatically between displaying the digit
register data in planes P0 and P1. If the digit register
data for any digit is different in the two planes, then that
SA AP0
SLAVE ADDRESS COMMAND BYTE
ACKNOWLEDGE FROM MAX6953
R/W ACKNOWLEDGE FROM MAX6953
D15 D14 D13 D12 D11 D10 D9 D8
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
Figure 7. Command Byte Received
AAAP
0
SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE FROM MAX6953
R/W 1 BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6953 ACKNOWLEDGE FROM MAX6953
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6953's REGISTERS
S
Figure 8. Command and Single Data Byte Received
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
10 ______________________________________________________________________________________
PIN DEVICE ADDRESS
AD1
AD0 A6 A5 A4 A3 A2 A1
A0
GND
GND 1 01000
0
GND
V+
101000
1
GND
SDA 1 01001
0
GND
SCL 1 01001
1
V+
GND 1 01010
0
V+ V+
101010
1
V+
SDA 1 01011
0
V+
SCL 1 01011
1
SDA
GND 1 01100
0
SDA
V+
101100
1
SDA
SDA 1 01101
0
SDA
SCL 1 01101
1
SCL
GND 1 01110
0
SCL
V+
101110
1
SCL
SDA 1 01111
0
SCL
SCL 1 01111
1
Table 3. MAX6953 Address Map
SAAAP0
SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE FROM MAX6953
R/W n BYTES
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6953 ACKNOWLEDGE FROM MAX6953
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX6953'S REGISTERS
Figure 9. n Data Bytes Received
digit appears to flip between two characters. To make a
character appear to blink on or off, write the character
to one plane, and use the blank character (0x20) for the
other plane. Once blinking has been configured, it con-
tinues automatically without further intervention.
Blink Speed
The blink speed is determined by frequency of the mul-
tiplex clock, OSC, and by setting the Blink Rate
Selection Bit B (Table 9) in the configuration register.
The Blink Rate Selection Bit B sets either fast or slow
blink speed for the whole display.
Initial Power-Up
On initial power-up, all control registers are reset, the
display is blanked, intensities are set to minimum, and
shutdown is enabled (Table 6).
Configuration Register
The configuration register is used to enter and exit shut-
down, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, and
reset the blink timing (Table 7).
Shutdown Mode (S Data Bit D0) Format
The S bit in the configuration register selects shutdown
or normal operation. The display driver can be pro-
grammed while in shutdown mode, and shutdown mode
is overridden when in the display test mode. For normal
operation, the S bit should be set to 1 (Table 8).
Blink Rate Selection (B Data Bit D2) Format
The B bit in the configuration register selects the blink
rate. This is the speed that the segments alternate
between plane P0 and plane P1 refresh data. The blink
rate is determined by the frequency of the multiplex clock
OSC, in addition to the setting of the B bit (Table 9).
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 11
COMMAND ADDRESS HEX
CODE
REGISTER
D15
D14 D13 D12 D11 D10 D9 D8
—
No-Op X 0 0 0 0 0 0 0 0x00
Intensity10 X 0 0 0 0 0 0 1 0x01
Intensity32 X 0 0 0 0 0 1 0 0x02
Scan Limit X 0 0 0 0 0 1 1 0x03
Configuration X 0 0 0 0 1 0 0 0x04
User-Defined Fonts X 0 0 0 0 1 0 1 0x05
Factory Reserved. Do not write to this. X 0 0 0 0 1 1 0 0x06
Display Test X 0 0 0 0 1 1 1 0x07
Digit 0 Plane P0 X 0 1 0 0 0 0 0 0x20
Digit 1 Plane P0 X 0 1 0 0 0 0 1 0x21
Digit 2 Plane P0 X 0 1 0 0 0 1 0 0x22
Digit 3 Plane P0 X 0 1 0 0 0 1 1 0x23
Digit 0 Plane P1 X 1 0 0 0 0 0 0 0x40
Digit 1 Plane P1 X 1 0 0 0 0 0 1 0x41
Digit 2 Plane P1 X 1 0 0 0 0 1 0 0x42
Digit 3 Plane P1 X 1 0 0 0 0 1 1 0x43
Write Digit 0 Planes P0 and P1 with Same Data
(Reads as 0x00) X11000000x60
Write Digit 1 Planes P0 and P1 with Same Data
(Reads as 0x00) X11000010x61
Write Digit 2 Planes P0 and P1 with Same Data
(Reads as 0x00) X11000100x62
Write Digit 3 Planes P0 and P1 with Same Data
(Reads as 0x00) X11000110x63
Table 5. Register Address Map
COMMAND BYTE
ADDRESS RANGE AUTOINCREMENT BEHAVIOR
x0000000 to x0000100 Command byte address autoincrements after byte read or written.
x0000101 Command byte address remains at x0000101 after byte read or written, but the font
address pointer autoincrements.
x0000110 Factory reserved; do not write to this register.
x000111 to x1111110 Command byte address autoincrements after byte read or written.
x1111111 Command byte address remains at x1111111 after byte read or written.
Table 4. Command Address Autoincrement Rules
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
12 ______________________________________________________________________________________
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1
D0
Slow blinking (segments are refreshed using plane P0 for 1s,
plane P1 for 1s, for OSC = 4MHz). PXRTE0XS
Fast blinking (segments are refreshed using plane P0 for 0.5s,
plane P1 for 0.5s, for OSC = 4MHz). PXRTE1XS
Table 9. Blink Rate Selection (B Data Bit D2) Format
REGISTER DATA
D7 D6 D5 D4 D3 D2 D1 D0
Configuration Register P X R T E B X S
Table 7. Configuration Register Format
REGISTER DATA
MODE D7 D6 D5 D4 D3 D2 D1 D0
Shutdown Mode P X R T E B X 0
Normal Operation P X R T E B X 1
Table 8. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
REGISTER POWER-UP CONDITION ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
Intensity10 1/16 (min on) 0x01 0 0 000000
Intensity32 1/16 (min on) 0x02 0 0 000000
Scan Limit Display 4 digits: 0 1 2 3 0x03 X X XXXXX1
Configuration Shutdown enabled,
blink speed is slow,
blink disabled 0x04 0 X 0000X0
User-Defined Font
Address Pointer
Address 0x80; pointing to
the first user-defined font
location 0x05 1 0 000000
Display Test Normal operation 0x07 X X XXXXX0
Digit 0 Plane P0 Blank digit (0x20) 0x20 0 0 100000
Digit 1 Plane P0 Blank digit (0x20) 0x21 0 0 100000
Digit 2 Plane P0 Blank digit (0x20) 0x22 0 0 100000
Digit 3 Plane P0 Blank digit (0x20) 0x23 0 0 100000
Digit 0 Plane P1 Blank digit (0x20) 0x40 0 0 100000
Digit 1 Plane P1 Blank digit (0x20) 0x41 0 0 100000
Digit 2 Plane P1 Blank digit (0x20) 0x42 0 0 100000
Digit 3 Plane P1 Blank digit (0x20) 0x43 0 0 100000
Table 6. Initial Power-Up Register Status
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 13
Global Blink Enable/Disable (E Data Bit D3) Format
The E bit globally enables or disables the blink feature
of the device (Table 10). When blink is globally
enabled, then the digit data in both planes P0 and P1
are used to control the display (Table 11).
When blink is globally disabled, then only the digit data
in plane P0 is used to control the display. The digit data
in plane P1 is ignored.
Global Blink Timing Synchronization (T Data Bit D4)
Format
By setting the T bit in multiple MAX6953s at the same
time (or in quick succession), the blink timing can be
synchronized across all the devices (Table 12). Note
that the display multiplexing sequence is also reset,
which might give rise to a one-time display flicker when
the register is written.
REGISTER DATA
MODE D7 D6 D5 D4 D3 D2 D1 D0
Blink function is disabled. P X R T 0 B X S
Blink function is enabled. P X R T 1 B X S
Table 10. Global Blink Enable/Disable (E Data Bit D3) Format
SEGMENT’S
BIT SETTING
IN PLANE P1
SEGMENT’S
BIT SETTING
IN PLANE P0
SEGMENT
BEHAVIOR
00Segment off
01
Segment on only
during the 1st half of
each blink period
10
Segment on only
during the 2nd half of
each blink period
11Segment on
Table 11. Digit Register Mapping with
Blink Globally Enabled
REGISTER DATA
MODE D7 D6 D5 D4 D3 D2 D1 D0
Blink timing counters are unaffected. P X R 0 E B X S
Blink timing counters are reset during the I2C
acknowledge. PXR1EBXS
Table 12. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATA
MODE D7 D6 D5 D4 D3 D2 D1
D0
Digit data for both planes P0 and P1 are unaffected. P X 0 T E B X S
Digit data for both planes P0 and P1 are cleared during
I2C acknowledge. PX1TEBXS
Table 13. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
MODE D7 D6 D5 D4 D3 D2 D1 D0
P1 blink phase 0 X R T E B X S
P0 blink phase 1 X R T E B X S
Table 14. Blink Phase Readback (P Data Bit D7) Format
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
14 ______________________________________________________________________________________
Global Clear Digit Data (R Data Bit D5) Format
When global digit data clear is set, the digit data for
both planes P0 and P1 for all digits are cleared during
the acknowledge (Table 13).
Blink Phase Readback (P Data Bit D7) Format
When the configuration register is read, the P bit
reflects the state of the blink output pin at that time
(Table 14).
Character Generator Font Mapping
The font is a 5 ✕7 matrix comprising 104 characters in
ROM, and 24 user-definable characters. The selection
from the total of 128 characters is represented by the
lower 7 bits of the 8-bit digit registers. The most-signifi-
cant bit, shown as x in the ROM map, is zero to light
LEDs as shown by the black segments in Table 15, and
1 to display the inverse.
The character map follows the Arial font for 96 charac-
ters in the range 0x0101000 through x1111111. The
first 32 characters map the 24 user-definable positions
(RAM00 to RAM23), plus eight extra common charac-
ters in ROM.
User-Defined Fonts
The 24 user-definable characters are represented by
120 entries of 7-bit data, five entries per character, and
are stored in MAX6953's internal RAM.
The 120 user-definable font data entries are written and
read through a single register, address 0x05. An
autoincrementing font address pointer in the MAX6953
indirectly accesses the font data. The font address
pointer can be written, setting one of 120 addresses
between 0x00 and 0xF7, but cannot be read back. The
font data is written to and read from MAX6953 indirect-
ly, using this font address pointer. Unused font loca-
tions can be used as general-purpose scratch RAM,
bearing in mind that the font registers are only 7 bits
wide, not 8.
Table 16 shows how the single user-defined font regis-
ter 0x05 is used to set the font address pointer, write
font data, and read font data. A read action always
returns font data from the font address pointer position.
A write action sets the 7-bit font address pointer if the
MSB is set, or writes 7-bit font data to the font address
pointer position if the MSB is clear.
The font address pointer autoincrements after a valid
access to the user-definable font data. Auto-
incrementing allows the 120 font data entries to be writ-
ten and read back very quickly because the font point-
er address need only be set once. When the last data
location 0xF7 is written, the font address pointer autoin-
crements to address 0x80. If the font address pointer is
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
x000 x001 x010 x011 x100 x101 x110 x111
RAM00
RAM01
RAM02
RAM03
RAM04
RAM05
RAM06
RAM07
MSB
LSB
RAM08
RAM09
RAM10
RAM11
RAM12
RAM13
RAM14
RAM15
RAM16
RAM17
RAM18
RAM19
RAM20
RAM21
RAM22
RAM23
Table 15. Character Map
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 15
set to an out-of-range address by writing data in the 0xF8
to 0xFF range, then address 0x80 is set instead (Table
17).
Table 18 shows the user-definable font pointer base
addresses.
Table 19 shows an example of data (characters 0, 1,
and 2) being stored in the first three user-defined font
locations, illustrating the orientation of the data bits.
Table 20 shows the six sequential write commands
required to set a MAX6953's font character RAM02 with
the data to display character 2 given in the font RAM
illustration above.
Multiplex Clock and Blink Timing
The OSC pin can be fitted with capacitor CSET to GND
(to use the internal RC multiplex oscillator), or driven by
an external clock. The multiplex clock frequency deter-
mines the multiplex scan rate and the blink timing. The
display scan rate (the frequency that the complete four-
digit display is updated) is calculated by dividing the
frequency at OSC by 5600. With OSC at 4MHz, each
digit row is enabled for 100µs, and the display scan
rate is 714.29Hz.
The on-chip oscillator may be accurate enough for
applications using a single device. If an exact blink rate
is required, use an external clock ranging between
1MHz and 8MHz to drive OSC. The OSC inputs of mul-
tiple MAX6953s can be tied together to a common
external clock to make the devices blink at the same
rate. The relative blink phasing of multiple MAX6953s
can be synchronized by setting the T bit in the configu-
ration register for all the devices in quick succession
(Table 12).
Blink Output
The blink output pin indicates the blink phase, and is
high during the P0 period and low during the P1 period.
Blink phase status can also be read back as the P bit in
the configuration register (Table 14). Typical uses for
this output are:
•To provide an interrupt to the processor so that seg-
ment data can be changed synchronous to the
blinking. For example, a clock application may have
colon segments blinking every second between
hours and minute digits, and the minute display is
best changed in step with the colon segments. Also,
if the rising edge of blink is detected, there is half a
blink period to change the P1 digit data. Similarly, if
the falling edge of blink is detected, the user has
half a blink period to change the P0 digit data.
•If OSC is driven with an accurate frequency, blink
can be used as a seconds counter or similar.
Scan-Limit Register
The scan-limit register sets how many monocolor digits
are displayed, either two or four. A bicolor digit is con-
nected as two monocolor digits (Table 21).
ADDRESS CODE
(HEX) REGISTER
DATA I2C READ
OR WRITE FUNCTION
0x05 0x00–0x7F Read Read 7-bit user-definable font data entry from current font
address. MSB of the register data is clear. Font address
pointer is incremented after the read.
0x05 0x00–0x7F Write Write 7-bit user-definable font data entry to current font
address. Font address pointer is incremented after the write.
0x05 0x80–0xFF Write Write font address pointer with the register data.
Table 16. Memory Mapping of User-Defined Font Register 0x05
FONT POINTER ADDRESS ACTION
0x80 to 0xF6 Valid range to set the font address pointer. Pointer autoincrements after a font data read or
write, while pointer address remains in this range.
0xF7 Font address resets to 0x80 after a font data read or write to this pointer address.
0xF8 to 0xFF Invalid range to set the font address pointer. Pointer is set to 0x80 if address.
Table 17. Font Pointer Address Behavior
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
16 ______________________________________________________________________________________
DIGIT 1
ROW 1 DIGIT 1
ROW 2 DIGIT 1
ROW 3 DIGIT 1
ROW 4 DIGIT 1
ROW 5 DIGIT 1
ROW 6 DIGIT 1
ROW 7 DIGIT 3
ROW 1 DIGIT 3
ROW 2 DIGIT 3
ROW 3 DIGIT 3
ROW 4 DIGIT 3
ROW 5 DIGIT 3
ROW 6 DIGIT 3
ROW 7 DIGIT 1
ROW 1
COLUMN DRIVER
PINS O19-O23
DIGIT 0
ROW 1 DIGIT 0
ROW 2 DIGIT 0
ROW 3 DIGIT 0
ROW 4 DIGIT 0
ROW 5 DIGIT 0
ROW 6 DIGIT 0
ROW 7 DIGIT 2
ROW 1 DIGIT 2
ROW 2 DIGIT 2
ROW 3 DIGIT 2
ROW 4 DIGIT 2
ROW 5 DIGIT 2
ROW 6 DIGIT 2
ROW 7 DIGIT 0
ROW 1
COLUMN DRIVER
PINS O14-O18
DIGIT 1 ROW 1's 100µs MULTIPLEX TIMESLOT
CURRENT SOURCE
1/16TH
2/16TH
(MIN ON)
3/16TH
4/16TH
5/16TH
6/16TH
7/16TH
8/16TH
9/16TH
10/16TH
11/16TH
12/16TH
13/16TH
14/16TH
15/16TH
16/16TH
(MAX ON)
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
CURRENT SOURCE
ONE COMPLETE 1.4ms MULTIPLEX CYCLE AROUND 14 ROWS
100µs
DIGIT 1 COLUMN
DRIVER OUTPUTS
PINS O19-O23
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DIGITS 0 AND 1
ROW OUTPUTS
PINS O0–06
HIGH-Z
LOW
DIGITS 2 AND 3
ROW OUTPUTS
PINS O7–O13
HIGH-Z HIGH-Z
HIGH-Z
MINIMUM 6.25µs INTERDIGIT BLANKING INTERVAL
START OF
NEXT CYCLE
Figure 10. Multiplex Timing Diagram (OSC = 4MHz)
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 17
The multiplexing scheme drives digits 0 and 1 at the
same time, then digits 2 and 3 at the same time. To
increase the effective brightness of the displays, drive
only two digits instead of four. By doing this, the aver-
age segment current doubles, but also doubles the
number of MAX6953s required to drive a given number
of digits.
Because digit 1 is driven at the same time as digit 0
(and digit 3 is driven at the same time as digit 2), only 1
bit is used to set the scan limit. The bit is clear if one or
two digits are to be driven, and set if three or four digits
are to be driven (Table 21).
Intensity Registers
Display brightness is controlled digitally by four pulse-
width modulators, one for each display digit. Each digit
is controlled by a nibble of one of the two intensity reg-
isters, Intensity10 and Intensity32. The modulator
scales the average segment current in 16 steps from a
maximum of 15/16 down to 1/16 of the peak current.
The minimum interdigit blanking time is therefore 1/16
of a cycle. The maximum duty cycle is 15/16 (Tables 23
and 24).
No-Op Register
A write to the No-Op register is ignored.
Selecting External Components RSET and
CSET to Set Oscillator Frequency and
Segment Current
The RC oscillator uses an external resistor RSET and an
external capacitor CSET to set the oscillator frequency,
fOSC. The allowed range of fOSC is 1MHz to 8MHz.
RSET also sets the peak segment current. The recom-
mended values of RSET and CSET set the oscillator to
REGISTER DATA
FONT
CHARACTER ADDRESS
CODE (HEX) REGISTER
DATA (HEX) D7
D6 D5 D4 D3
D2
D1
D0
RAM00 0x05 0x80 1 0 0 0 0 0 0 0
RAM01 0x05 0x85 1 0 0 0 0 1 0 1
RAM02 0x05 0x8A 1 0 0 0 1 0 1 0
RAM03 0x05 0x8F 1 0 0 0 1 1 1 1
RAM04 0x05 0x94 1 0 0 1 0 1 0 0
RAM05 0x05 0x99 1 0 0 1 1 0 0 1
RAM06 0x05 0x9E 1 0 0 1 1 1 1 0
RAM07 0x05 0xA3 1 0 1 0 0 0 1 1
RAM08 0x05 0xA8 1 0 1 0 1 0 0 0
RAM09 0x05 0xAD 1 0 1 0 1 1 0 1
RAM10 0x05 0xB2 1 0 1 1 0 0 1 0
RAM11 0x05 0xB7 1 0 1 1 0 1 1 1
RAM12 0x05 0xBC 1 0 1 1 1 1 0 0
RAM13 0x05 0xC1 1 1 0 0 0 0 0 1
RAM14 0x05 0xC6 1 1 0 0 0 1 1 0
RAM15 0x05 0xCB 1 1 0 0 1 0 1 1
RAM16 0x05 0xD0 1 1 0 1 0 0 0 0
RAM17 0x05 0xD5 1 1 0 1 0 1 0 1
RAM18 0x05 0xDA 1 1 0 1 1 0 1 0
RAM19 0x05 0xDF 1 1 0 1 1 1 1 1
RAM20 0x05 0xE4 1 1 1 0 0 1 0 0
RAM21 0x05 0xE9 1 1 1 0 1 0 0 1
RAM22 0x05 0xEE 1 1 1 0 1 1 1 0
RAM23 0x05 0xF3 1 1 1 1 0 0 1 1
Table 18. User-Definable Font Pointer Base Address Table
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
18 ______________________________________________________________________________________
REGISTER DATA
SCAN
LIMIT ADDRESS CODE
(HEX) D7
D6 D5 D4 D3 D2
D1
D0
HEX
CODE
Display Digits 0 and 1 Only 0x03 X X X X X
X
X0
0xX0
Display Digits 0, 1, 2, and 3 0x03 X X X X X
X
X1
0xX1
Table 21. Scan-Limit Register Format
REGISTER DATA
FONT
CHARACTER
FONT
ADDRESS
POINTER
ADDRESS
CODE (HEX)
FONT
POINTER
ADDRESS
(HEX)
D7 D6 D5 D4 D3 D2 D1
D0
RAM00 0x00 0x05 0x80 0 0 1 1 1 1 1 0
RAM00 0x01 0x05 0x81 0 1010001
RAM00 0x02 0x05 0x82 0 1001001
RAM00 0x03 0x05 0x83 0 10001 0 1
RAM00 0x04 0x05 0x84 0 0 1 1 1 1 1 0
RAM01 0x05 0x05 0x85 0 0 0 0 0 0 0 0
RAM01 0x06 0x05 0x86 0 1 0 0001 0
RAM01 0x07 0x05 0x87 0 1 1 1 1 1 1 1
RAM01 0x08 0x05 0x88 0 1 0 00000
RAM01 0x09 0x05 0x89 0 0 0 0 0 0 0 0
RAM02 0x0A 0x05 0x8A 0 1 0 0001 0
RAM02 0x0B 0x05 0x8B 0 1 1 00001
RAM02 0x0C 0x05 0x8C 0 1010001
RAM02 0x0D 0x05 0x8D 0 1001001
RAM02 0x0E 0x05 0x8E 0 10001 1 0
Table 19. User-Definable Character Storage Example
ADDRESS CODE
(HEX) REGISTER DATA
(HEX) ACTION BEING PERFORMED
0x05 0x8A Set font address pointer to the base address of font character RAM02.
0x05 0x42 1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements
to address 0x8B.
0x05 0x61 2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then
autoincrements to address 0x8C.
0x05 0x51 3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then
autoincrements to address 0x8D.
0x05 0x49 4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then
autoincrements to address 0x8E.
0x05 0x46 5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements
to address 0x8F.
Table 20. Setting a Font Character to RAM Example
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 19
4MHz, which makes the blink frequencies 0.5Hz selec-
table between 1Hz. The recommended value of RSET
also sets the peak current to 40mA, which makes the
segment current adjustable from 2.5mA to 37.5mA in
2.5mA steps:
ISEG = KI/ RSET mA
fOSC = KF/ (RSET ✕(CSET + CSTRAY)) MHz
where:
KI= 2144
KF= 6003
RSET = external resistor in kΩ
CSET = external capacitor in pF
CSTRAY = stray capacitance from OSC pin to GND in
pF, typically 2pF
The recommended value of RSET is 53.6kΩand the
recommended value of CSET is 26pF.
The recommended value of RSET is the minimum
allowed value since it sets the display driver to the
maximum allowed segment current. RSET can be set to
a higher value to set the segment current to a lower
peak value where desired. The user must also ensure
that the peak current specifications of the LEDs con-
nected to the driver are not exceeded.
The effective value of CSET includes not only the actual
external capacitor used, but also the stray capacitance
from OSC to GND. This capacitance is usually in the
1pF to 5pF range, depending on the layout used.
Display-Test Register
The display-test register switches the drivers between
one of two modes: normal and display test. Display-test
mode turns all LEDs on by overriding, but not altering,
all control and digit registers (including the shutdown
register). In display-test mode, eight digits are scanned
and the duty cycle is 7/16 (half power). Table 22 lists
the display-test register format.
Applications Information
Choosing Supply Voltage to Minimize
Power Dissipation
The MAX6953 drives a peak current of 40mA into LEDs
with a 2.4V forward-voltage drop when operated from a
supply voltage of at least 3.0V. The minimum voltage
drop across the internal LED drivers is therefore (3.0V -
2.4V) = 0.6V. If a higher supply voltage is used, the dri-
ver absorbs a higher voltage, and the driver’s power
dissipation increases accordingly. However, if the LEDs
used have a higher forward voltage drop than 2.4V, the
supply voltage must be raised accordingly to ensure
that the driver always has at least 0.6V headroom.
The voltage drop across the drivers with a nominal 5V
supply (5.0V - 2.4V) = 2.6V is nearly 3 times the drop
across the drivers with a nominal 3.3V supply (3.3V -
2.4V) = 0.9V. In most systems, consumption is an
important design criterion, and the MAX6953 should be
operated from the system’s 3.3V nominal supply. In
other designs, the lowest supply voltage may be 5V.
The issue now is to ensure that the dissipation limit for
the MAX6953 is not exceeded. This can be achieved
by inserting a series resistor in the supply to the
MAX6953, ensuring that the supply decoupling capaci-
tors are still on the MAX6953 side of the resistor. For
example, consider the requirement that the minimum
supply voltage to a MAX6953 must be 3.0V, and the
input supply range is 5V ±5%. Maximum supply current
is: 15mA + (40mA ✕10) = 415mA
Minimum input supply voltage is 4.75V. Maximum
series resistor value is:
(4.75V - 3.0V) / 0.415A = 4.22Ω
We choose 3.3Ω±5%. Worst-case resistor dissipation
is at maximum toleranced resistance, i.e., (0.415A)2✕
(3.3Ωx 1.05) = 0.577W. We choose a 1W resistor rat-
ing. The maximum MAX6953 supply voltage is at maxi-
mum input supply voltage and minimum toleranced
resistance, i.e., 5.25V - (0.415A ✕3.3Ω✕0.95) = 3.95V.
REGISTER DATA
MODE ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Normal operation 0x07 X X X X X X X 0
Display test 0x07 X X X X X X X 1
Table 22. Display-Test Register Format
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
20 ______________________________________________________________________________________
DUTY
CYCLE
TYPICAL
SEGMENT
CURRENT (mA)
ADDRESS
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
1/16 (min on) 2.5 0x01, 0x02 0000
0xX0
2/16 5 0x01, 0x02 0001
0xX1
3/16 7.5 0x01, 0x02 0010
0xX2
4/16 10 0x01, 0x02 0011
0xX3
5/16 12.5 0x01, 0x02 0100
0xX4
6/16 15 0x01, 0x02 0101
0xX5
7/16 17.5 0x01, 0x02 0110
0xX6
8/16 20 0x01, 0x02 0111
0xX7
9/16 22.5 0x01, 0x02 1000
0xX8
10/16 25 0x01, 0x02 1001
0xX9
11/16 27.5 0x01, 0x02 1010
0xXA
12/16 30 0x01, 0x02 1011
0xXB
13/16 32.5 0x01, 0x02 1100
0xXC
14/16 35 0x01, 0x02 1101
0xXD
15/16 37.5 0x01, 0x02 1110
0xXE
15/16 (max on) 37.5 0x01, 0x02
See Table 24.
1111
0xXF
Table 23. Intensity Register Format for Digit 0 (Address 0x01) and Digit 2 (Address 0x02)
DUTY
CYCLE
TYPICAL
SEGMENT
CURRENT
(mA)
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
1/16 (min on) 2.5 0x01, 0x02 0000
0x0X
2/16 5 0x01, 0x02 0001
0x1X
3/16 7.5 0x01, 0x02 0010
0x2X
4/16 10 0x01, 0x02 0011
0x3X
5/16 12.5 0x01, 0x02 0100
0x4X
6/16 15 0x01, 0x02 0101
0x5X
7/16 17.5 0x01, 0x02 0110
0x6X
8/16 20 0x01, 0x02 0111
0x7X
9/16 22.5 0x01, 0x02 1000
0x8X
10/16 25 0x01, 0x02 1001
0x9X
11/16 27.5 0x01, 0x02 1010
0xAX
12/16 30 0x01, 0x02 1011
0xBX
13/16 32.5 0x01, 0x02 1100
0xCX
14/16 35 0x01, 0x02 1101
0xDX
15/16 37.5 0x01, 0x02 1110
0xEX
15/16 (max on)
37.5 0x01, 0x02 1111
See Table 23.
0xFX
Table 24. Intensity Register Format for Digit 1 (Address 0x01) and Digit 3 (Address 0x02)
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
______________________________________________________________________________________ 21
Low-Voltage Operation
The MAX6953 works over the 2.7V to 5.5V supply
range. The minimum useful supply voltage is deter-
mined by the forward-voltage drop of the LEDs at the
peak current ISEG, plus the 0.6V headroom required by
the driver output stages. The MAX6953 correctly regu-
lates ISEG with a supply voltage above this minimum
voltage. If the supply drops below this minimum volt-
age, the driver output stages may brown out, and be
unable to regulate the current correctly. As the supply
voltage drops further, the LED segment drive current
becomes effectively limited by the output driver's on-
resistance, and the LED drive current drops. The char-
acteristics of each individual LED in a 5 ✕7 matrix digit
are well matched, so the result is that the display inten-
sity dims uniformly as supply voltage drops out of regu-
lation and beyond. The MAX6953 operates down to 2V
supply voltage (although most displays are very dim at
this voltage), providing that the MAX6953 is powered
up initially to at least 2.7V to trigger the device's internal
reset, and also that the I2C interface is constrained to
100kbps.
Computing Power Dissipation
The upper limit for power dissipation (PD) for the
MAX6953 is determined from the following equation:
PD= (V+ ✕15mA) + (V+ - VLED) (DUTY ✕ISEG ✕N)
where:
V+ = supply voltage
Duty = duty cycle set by intensity register
N = number of segments driven (worst case is 10)
VLED = LED forward voltage
ISEG = segment current set by RSET
PD= power dissipation, in mW if currents are in mA
Dissipation example:
ISEG = 40mA, N = 10, Duty = 15 / 16, VLED
= 2.4V at 40mA, V+ = 3.6V
PD= 3.6V (15mA) + (3.6V - 2.4V)
(15 / 16 ✕40mA ✕10) = 0.504W
Thus, for a 36-pin SSOP package (TJA = 1 / 0.0118 =
+85°C/W from operating ratings), the maximum allowed
ambient temperature TAis given by:
TJ(MAX) = TA+ (PD✕TJA) = +150°C =
TA+ (0.504 ✕+85°C/W)
So TA= +107°C. Thus, the part can be operated safely
at a maximum package temperature of +85°C.
Power Supplies
The MAX6953 operates from a single 2.7V to 5.5V
power supply. Bypass the power supply to GND with a
0.1µF capacitor as close to the device as possible. Add
a 47µF capacitor if the MAX6953 is not close to the
board's input bulk decoupling capacitor.
Board Layout
When designing a board, use the following guidelines:
1) The RSET connection to the ISET pin is a high-
impedance node, and sensitive to layout. Place
RSET right next to the ISET pin and route RSET
directly to these pins with very short tracks.
2) Ensure that the track from the ground end of RSET
routes directly to GND pin 19 (PDIP package) or
GND pin 17 (SSOP package), and that this track is
not used as part of any other ground connection.
Chip Information
TRANSISTOR COUNT: 44,078
PROCESS: CMOS
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
22 ______________________________________________________________________________________
Pin Configurations
40 O23
O22
O21
V+
V+
V+
O20
O19
O18
O17
O16
O15
O14
O13
O12
N.C.
SCL
SDA
AD0
OSC
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
O0
O1
O2
GND
GND
GND
O3
O4
O5
O6
O7
O8
O9
O10
O11
N.C.
ISET
AD1
GND
BLINK
TOP VIEW
MAX6953
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
PDIP
20
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
O23
O22
O21
V+
V+
O20
O12
O19
O18
O17
O16
O15
O14
O13
O11
O10
O9
O8
O7
O6
O5
O4
O3
GND
GND
O2
O1
O0
SSOP
MAX6953
22
21
20
19
15
16
17
18 OSC
SCL
SDA
AD0
BLINK
GND
AD1
ISET
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
✕
7
Matrix LED Display Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SSOP.EPS
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
1
1
21-0040 E
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
FRONT VIEW
MAX
0.011
0.104
0.017
0.299
0.013
INCHES
0.291
0.009
E
C
DIM
0.012
0.004
B
A1
MIN
0.096A
0.23
7.40 7.60
0.32
MILLIMETERS
0.10
0.30
2.44
MIN
0.44
0.29
MAX
2.65
0.040
0.020L0.51 1.02
H0.4140.398 10.11 10.51
e0.0315 BSC 0.80 BSC
D0.6120.598 15.20 15.55
HE
A1 A
D
eB0∞-8∞
L
C
TOP VIEW
SIDE VIEW
1
36
