LM4925
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LM4925 Boomer™ Audio Power Amplifier Series 2 Cell, Single Ended Output, 40mW
Stereo Headphone Audio Amplifier
Check for Samples: LM4925
1FEATURES DESCRIPTION
The unity gain stable LM4925 is both a mono
23• BTL Mode for Mono Speaker differential output (for BTL operation) audio amplifier
• 2-Cell 1.5V to 3.6V Battery Operation and a Single Ended (SE) stereo headphone amplifier.
• Single Ended Headphone Operation with Operating on a single 3V supply, the mono-BTL
Output Coupling Capacitors mode delivers 410mW into an 8Ωload at 1% THD+N.
In Single Ended stereo headphone mode, the
• Unity-Gain Stable amplifier delivers 40mW per channel into a 16Ωload
• “Click and Pop” Suppression Circuitry for at 1% THD+N.
Both Shutdown and Mute With the LM4925 packaged in the VSSOP and SON
• Active Low Micro-Power Shutdown packages, the customer benefits include low profile
• Active-Low Mute Mode and small size. This package minimizes PCB area
and maximizes output power.
• Thermal Shutdown Protection Circuitry The LM4925 features circuitry that reduces output
APPLICATIONS transients (“clicks” and “pops”) during device turn-on
and turn-off, an externally controlled, low-power
• Portable Two-Cell Audio Products consumption, active-low shutdown mode, and thermal
• Portable Two-Cell Electronic Devices shutdown. Boomer audio power amplifiers are
designed specifically to use few external components
KEY SPECIFICATIONS and provide high quality output power in a surface
mount package.
• Mono-BTL Output Power
– (RL= 8Ω, VDD = 3.0V, THD+N = 1%),
410mW (Typ)
• Single Ended Output Power Per Channel,
– (RL= 16Ω, VDD = 3.0V, THD+N = 1%),
40mW (Typ)
• Micropower Shutdown Current, 0.1µA (Typ)
• Supply Voltage Operating Range,
1.5V < VDD < 3.6V
• PSRR 100Hz, VDD = 3V, BTL, 70dB (Typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Boomer is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
5
In A VDD
SD VoA
Mute SE/BTL
Bypass VoB
IN B GND
10
9
8
7
6
-
+
-
+
IN A
CBYPASS
IN B
SD
MUTE
VoA
SE/BTL
VoB
Click-Pop
and
Mode Control
Logic
Bias
Generator
LM4925
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Typical Application
Figure 1. Block Diagram
Connection Diagrams
Figure 2. VSSOP Package
Top View
See Package Number DGS for VSSOP
Figure 3. SON Package
Top View
See Package Number DSC0010A
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Click-Pop
and
Mode Control
Logic
Bias
Generator
ShutDown and
Mute Controller
+
-
+
-
Cbypass
4.7 PF
IN B
Rf
20k
20k
Ri
20k
Rf
20k
VDD
VoA
Ci
0.47 PF
Vin 1 8:
-
+
-
+
Co
100 PF
RiCi
0.47 PF20k
Vin1
RiCi
0.47 PF20k
Vin2
Rf
50k
Rf
50k
Co
100 PF
+
16:
16:
ShutDown and
Mute Controller
Click-Pop
and
Mode Control
Logic
Bias
Generator
Cbypass
4.7 PF
LM4925
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SNAS273A –FEBRUARY 2005–REVISED APRIL 2013
Typical Connections
Figure 4. Typical Capacitive Couple (SE) Output Configuration Circuit
Figure 5. Typical BTL Speaker Configuration Circuit
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
Supply Voltage 3.8V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD
+0.3V
Power Dissipation(3) Internally limited
ESD Susceptibility(4) 2000V
ESD Susceptibility(5) 200V
Junction Temperature 150°C
Phase (60sec) 215°C
Solder Information Small Outline Package Vapor Infrared (15 sec) 220°C
θJA (typ) DGS 175°C/W
Thermal Resistance θJA (typ) DSC0010A 73°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation is dictated by TJMAX,θJA, and the ambient temperature TAand must be derated at elevated
temperatures. The maximum allowable power dissipation is PDMAX = (TJMAX −TA)/θJA. For the LM4925, TJMAX = 150°C. For the θJAs,
please see the Application Information section or the Absolute Maximum Ratings section.
(4) Human body model, 100pF discharged through a 1.5kΩresistor.
(5) Machine model, 220pF–240pF discharged through all pins.
Operating Ratings TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Temperature Range Supply Voltage 1.5V ≤VDD ≤3.6V
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Electrical Characteristics VDD = 3.0V(1)(2)
The following specifications apply for the circuit shown in Figure 4 for Single Ended Outputs (AV= 2.5V) and Figure 5 for BTL
Outputs (AV-BTL = 2), unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4925 Units
(Limits)
Typical(3) Limit(4)
IDD Quiescent Power Supply Current VIN = 0V, IO= 0A, RL=∞(5) 1.0 1.6 mA (max)
ISD Shutdown Current VSHUTDOWN = GND 0.1 1 μA (max)
VOS Output Offset Voltage 2 10 mV (max)
RL= 8Ω, BTL, Figure 5 410 350 mW (min)
THD+N = 1%, f = 1kHz
POOutput Power(6) RL= 16Ω,Figure 4, SE per Channel, 40 30 mW (min)
THD+N = 1%, f = 1kHz
RL= 8Ω, BTL, PO= 300mW, 0.1
Figure 5, f = 1kHz
THD+N Total Harmonic Distortion + Noise 0.5 % (max)
RL= 16Ω, SE, PO= 20mW per channel, 0.05
Figure 4, f = 1kHz
20Hz to 20kHz, A-weighted,
VNO Output Voltage Noise Input Referred, 10 µVRMS
Single Ended Output, Figure 4
Crosstalk RL= 16Ω,Figure 4 58 dB
VRIPPLE = 200mVP-P sine wave
CBYPASS = 4.7µF, RL= 8Ω70 dB
f = 100Hz, BTL, Figure 5
PSRR Power Supply Rejection Ratio VRIPPLE = 200mVP-P sine wave
CBYPASS = 4.7µF, RL= 16Ω68 dB
f = 100Hz, SE, Figure 4
VIH Control Logic High 1.5V ≤VDD ≤3.6V 0.7VDD V (min)
VIL Control Logic Low 1.5V ≤VDD ≤3.6V 0.3VDD V (max)
Mute 1VPP Reference, 70 dB (min)
Attenuation Ri= 20k, Rf= 50k
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the ground (GND) pins unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(5) The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.
(6) Output power is measured at the device terminals.
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Electrical Characteristics VDD = 1.8V (1) (2)
The following specifications apply for the circuit shown in Figure 4 for Single Ended Outputs (AV= 2.5V) and Figure 5 for BTL
Outputs (AV-BTL = 2), unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4925 Units
(Limits)
Typical(3) Limit(4)
IDD Quiescent Power Supply Current VIN = 0V, IO= 0A, RL=∞(5) 0.9 1.6 mA (max)
ISD Shutdown Current VSHUTDOWN = GND 0.05 1 μA (max)
VOS Output Offset Voltage 2 10 mV (max)
RL= 8Ω, BTL, Figure 5,120 90 mW (min)
THD+N = 1%, f = 1kHz
POOutput Power (6) RL= 16Ω,Figure 4, SE per Channel, 10 7 mW (min)
THD+N = 1%, f = 1kHz
RL= 8Ω, BTL, PO= 50mW, 0.15
Figure 5, f = 1kHz
THD+N Total Harmonic Distortion + Noise 0.5 % (max)
RL= 16Ω, SE, PO= 5mW per channel, 0.1
Figure 4, f = 1kHz
VNO Output Voltage Noise 20Hz to 20kHz, A-weighted, 10 µVRMS
Input Referred,
Single Ended Output, Figure 4
Crosstalk RL= 16Ω,Figure 4 58 dB
VRIPPLE = 200mVP-P sine wave
CBYPASS = 4.7µF, RL= 8Ω70 dB
f = 100Hz, BTL, Figure 5
PSRR Power Supply Rejection Ratio VRIPPLE = 200mVP-P sine wave
CBYPASS = 4.7µF, RL= 16Ω68 dB
f = 100Hz, SE, Figure 4
VIH Control Logic High 1.5V ≤VDD ≤3.6V 0.7VDD V (min)
VIL Control Logic Low 1.5V ≤VDD ≤3.6V 0.3VDD V (max)
Mute 1VPP Reference, 70 dB (min)
Attenuation Ri= 20k, Rf= 50k
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) All voltages are measured with respect to the ground (GND) pins unless otherwise specified.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(5) The quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier.
(6) Output power is measured at the device terminals.
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10 601
0.01
1
10
THD + N (%)
OUTPUT POWER (mW)
0.1
5
3
2 7 4030
20
10 60
1
0.01
1
10
THD + N (%)
OUTPUT POWER (mW)
0.1
5
3
2 7 40
30
20
100 1k 10k
0.001
0.01
1
10
THD + N (%)
FREQUENCY (Hz)
0.1
100 1k 10k
0.001
0.01
1
10
THD + N (%)
FREQUENCY (Hz)
0.1
100 1k 10k
0.01
1
10
THD + N (%)
FREQUENCY (Hz)
0.1
100 1k 10k
0.01
1
10
THD + N (%)
FREQUENCY (Hz)
0.1
LM4925
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Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDD = 1.8V, SE, RL= 16ΩVDD = 3V, SE, RL= 16Ω
PO= 5mW per channel PO= 20mW per channel
Figure 6. Figure 7.
THD+N vs Frequency THD+N vs Frequency
VDD = 1.8V, BTL, RL= 8ΩVDD = 3V, BTL, RL= 8Ω
PO= 50mW PO= 300mW
Figure 8. Figure 9.
THD+N vs Output Power THD+N vs Output Power
VDD = 1.8V, SE, RL= 16ΩVDD = 3V, SE, RL= 16Ω
f = 1kHz, Both channels f = 1kHz, Both channels
Figure 10. Figure 11.
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2.4 3.2
0
30
80
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
2.01.6 2.8
40
50
20
10
3.6
70
60
THD+N = 10%
THD+N = 1%
0
100
POWER DISSIPATION (mW)
LOAD RESISTANCE (:)
3216 12848 64
150
200
50
80 11296
THD+N = 1%
THD+N = 10%
10k 18k
1
10
100
OUTPUT NOISE LEVEL (PV)
FREQUENCY (Hz)
6k4k2k 8k 16k
14k12k
20
50
5
2
20k
2.4 3.2
0
300
800
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
2.01.6 2.8
400
500
200
100
3.6
700
600
THD+N = 10%
THD+N = 1%
10 1001
0.01
1
10
THD + N (%)
OUTPUT POWER (mW)
0.1
10 1001
0.01
1
10
THD + N (%)
OUTPUT POWER (mW)
0.1
LM4925
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDD = 1.8V, BTL, RL= 8ΩVDD = 3V, BTL, RL= 8Ω
f = 1kHz f = 1kHz
Figure 12. Figure 13.
Output Power vs Supply Voltage
Output Noise vs Frequency RL= 8Ω, BTL, f = 1kHz
Figure 14. Figure 15.
Output Power vs Supply Voltage Output Power vs Load Resistance
RL= 16Ω, SE, f = 1kHz VDD = 1.8V, BTL, f = 1kHz
Figure 16. Figure 17.
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8
0
30
60
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
4
2
06 1210
40
50
20
10
90
80
70
0
100
250
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
40
20
060 80
150
200
50
100 140120
2.4 3.2
0
300
800
OUTPUT POWER (mW)
SUPPLY VOLTAGE (V)
2.01.6 2.8
400
500
200
100
3.6
700
600 THD+N = 10%
THD+N = 1%
0
20
50
POWER DISSIPATION (mW)
LOAD RESISTANCE (:)
3216 12848 64
30
40
10
80 11296
60
THD+N = 10%
THD+N = 1%
0
200
POWER DISSIPATION (mW)
LOAD RESISTANCE (:)
3216 12848 64
300
400
100
80 11296
600
500
THD+N = 10%
THD+N = 1%
144
0
4
10
POWER DISSIPATION (mW)
LOAD RESISTANCE (:)
3216 12848 64
6
8
2
80 11296
14
12
THD+N = 10%
THD+N = 1%
LM4925
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SNAS273A –FEBRUARY 2005–REVISED APRIL 2013
Typical Performance Characteristics (continued)
Output Power vs Load Resistance Output Power vs Load Resistance
VDD = 1.8V, SE, f = 1kHz VDD = 3V, BTL, f = 1kHz
Figure 18. Figure 19.
Output Power vs Load Resistance Output Power vs Supply Voltage
VDD = 3V, SE, f = 1kHz RL= 8Ω, BTL, f = 1kHz
Figure 20. Figure 21.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 1.8V, RL= 8Ω, BTL, f = 1kHz VDD = 1.8V, RL= 16Ω, SE, f = 1kHz
Figure 22. Figure 23.
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20 200 2k
-80
-60
-40
-20
-100
0
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
20k
-10
-30
-50
-70
-90
20 200 2k
-80
-60
-40
-20
-100
0
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
20k
-10
-30
-50
-70
-90
20 200 2k
-80
-60
-40
-20
-100
0
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
20k
-10
-30
-50
-70
-90
20 200 2k
-80
-60
-40
-20
-100
0
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
20k
-10
-30
-50
-70
-90
16 32
0
60
120
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
840 12 282420
80
100
40
20
36 40
0
100
250
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
2001000 300 400
150
200
50
500
LM4925
SNAS273A –FEBRUARY 2005–REVISED APRIL 2013
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3V, RL= 8Ω, BTL, f = 1kHz VDD = 3V, RL= 16Ω, SE, f = 1kHz
Figure 24. Figure 25.
Power Supply Rejection vs Frequency Power Supply Rejection vs Frequency
VDD = 1.8V, RL= 8Ω, BTL VDD = 1.8V, RL= 16Ω, SE
VRIPPLE = 200mVp-p, AV-BTL = 2V/V VRIPPLE = 200mVp-p, AV= 2.5V/V
Figure 26. Figure 27.
Power Supply Rejection vs Frequency Power Supply Rejection vs Frequency
VDD = 3V, RL= 8Ω, BTL VDD = 3V, RL= 16Ω, SE
VRIPPLE = 200mVp-p, AV-BTL = 2V/V VRIPPLE = 200mVp-p, AV= 2.5V/V
Figure 28. Figure 29.
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APPLICATION INFORMATION
BRIDGE (BTL) CONFIGURATION EXPLANATION
The LM4925 is a stereo audio power amplifier capable of operating in bridged (BTL) mode. As shown in
Figure 5, the LM4925 has two internal operational amplifiers. The first amplifier’s gain is externally configurable,
while the second amplifier should be externally fixed in a unity-gain, inverting configuration. The closed-loop gain
of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier’s gain is fixed by the two
external 20kΩresistors. Figure 5 shows that the output of amplifier one serves as the input to amplifier two which
results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently, the
differential gain for the IC is
AVD = 2 * (Rf/ Ri) (1)
By driving the load differentially through outputs VoA and VoB, an amplifier configuration commonly referred to
as “bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground. A bridge amplifier design has a few distinct
advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output
swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended
amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not
current limited or clipped. In order to choose an amplifier’s closed-loop gain without causing excessive clipping,
please refer to the AUDIO POWER AMPLIFIER DESIGN section.
A bridge configuration, such as the one used in LM4925, also creates a second advantage over single-ended
amplifiers. Since the differential outputs, VoA and VoB, are biased at half-supply, no net DC voltage exists
across the load. This eliminates the need for an output coupling capacitor which is required in a single supply,
single-ended amplifier configuration.
MODE SELECT DETAIL
The LM4925 can be configured for either single ended (see Figure 4) or BTL mode (see Figure 5). When the
SE/BTL pin has a logic high (VDD) applied to it, the LM4925 is in BTL mode. If a logic low (GND) is applied to
SE/BTL, the LM4925 operates in single-ended mode. The slew rate of VDD must be greater than 2.5V/ms to
ensure reliable Power on reset (POR). The circuit shown in Figure 30 presents an applications solution to the
problem of using different supply voltages with different turn-on times in a system with the LM4925. This circuit
shows the LM4925 with a 25-50kΩ. Pull-up resistor connected from the shutdown pin to VDD. The shutdown pin
of the LM4925 is also being driven by an open drain output of an external microcontroller on a separate supply.
This circuit ensures that shutdown is disabled when powering up the LM4925 by either allowing shutdown to be
high before the LM4925 powers on (the microcontroller powers up first) or allows shutdown to ramp up with VDD
(the LM4925 powers up first). This will ensure the LM4925 powers up properly and enters the correct mode of
operation (BTL or SE). Please note that the SE/BTL pin should be tied to GND for single-ended (SE) mode, and
to Vdd for BTL mode.
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IN A
SD
MUTE
BYP
IN B
1
2
3
4
5VoB
VoA
SE/BT
9
8
7
6
10
GND
VDD
LM4925
4.7 mF
5V
25k to 50k
20k
0.47 PF
20k
0.47 PF
20k
20k
100 PF
SPEAKER
100 PF
SPEAKER
MOSFET N
3.3V
Controller
LM4925
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Figure 30. Recommended Circuit for Different Supply Turn-On Timing
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged
(BTL) or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is
an increase in internal power dissipation. Since the LM4925 has two operational amplifiers in one package, the
maximum internal power dissipation in BTL mode is 4 times that of a single-ended amplifier. The maximum
power dissipation for a given application can be derived from the power dissipation graphs or from Equation 2.
PDMAX = 4 * (VDD)2/ (2π2RL) (2)
When operating in single ended mode, Equation 3 states the maximum power dissipation point for a single-
ended amplifier operating at a given supply voltage and driving a specified output load.
PDMAX = (VDD)2/ (2π2RL) (3)
Since the LM4925 has two operational amplifiers in one package, the maximum internal power dissipation point
is twice that of the number that results from Equation 3.
The maximum power dissipation point obtained from either Equation 2 or Equation 3 must not be greater than
the power dissipation that results from Equation 4:
PDMAX = (TJMAX - TA) / θJA (4)
For package DGS, θJA = 175°C/W. TJMAX = 150°C for the LM4925. Depending on the ambient temperature, TA,
of the system surroundings, Equation 4 can be used to find the maximum internal power dissipation supported by
the IC packaging. If the result of Equation 2 or Equation 3 is greater than that of Equation 4, then either the
supply voltage must be decreased, the load impedance increased or TAreduced. For the typical application of a
3.0V power supply, with an 16Ωload, the maximum ambient temperature possible without violating the maximum
junction temperature is approximately 129°C provided that device operation is around the maximum power
dissipation point. Thus, for typical applications, power dissipation is not an issue. Power dissipation is a function
of output power and thus, if typical operation is not around the maximum power dissipation point, the ambient
temperature may be increased accordingly. Refer to the Typical Performance Characteristics curves for power
dissipation information for lower output powers.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is important for low noise performance and high power supply
rejection. The capacitor location on the power supply pins should be as close to the device as possible. Typical
applications employ a battery (or 3.0V regulator) with 10μF tantalum or electrolytic capacitor and a ceramic
bypass capacitor that aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM4925. A bypass capacitor value in the range of 0.1μF to 4.7μF is recommended.
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MICRO POWER SHUTDOWN
The voltage applied to the SHUTDOWN pin controls the LM4925’s shutdown function. Activate micro-power
shutdown by applying a logic-low voltage to the SHUTDOWN pin. When active, the LM4925’s micro-power
shutdown feature turns off the amplifier’s bias circuitry, reducing the supply current. A voltage that is higher than
ground may increase the shutdown current. There are a few ways to control the micro-power shutdown. These
include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. When using a switch,
connect an external 100kΩpull-up resistor between the SHUTDOWN pin and VDD. Connect the switch between
the SHUTDOWN pin and ground. Select normal amplifier operation by opening the switch. Closing the switch
connects the SHUTDOWN pin to ground, activating micro-power shutdown. The switch and resistor ensure that
the SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or
microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN
pin with active circuitry eliminates the pull-up resistor. Shutdown enable/disable times are controlled by a
combination of Cbypass and VDD. Larger values of Cbypass results in longer turn on/off times from Shutdown. Longer
shutdown times also improve the LM4925’s resistance to click and pop upon entering or returning from
shutdown. For a 3.0V supply and Cbypass = 4.7μF, the LM4925 requires about 2 seconds to enter or return from
shutdown. This longer shutdown time enables the LM4925 to have virtually zero pop and click transients upon
entering or release from shutdown. Smaller values of Cbypass will decrease turn-on time, but at the cost of
increased pop and click and reduced PSRR. When the LM4925 is in shutdown, the outputs become very low
impedance (less than 5Ωto GND).
MUTE
The LM4925 also features a mute function that enables extremely fast turn-on/turn-off with a minimum of output
pop and click. The mute function leaves the outputs at their bias level, thus resulting in higher power
consumption than shutdown mode, but also provides much faster turn on/off times. Providing a logic low signal
on the MUTE pin enables mute mode. Threshold voltages and activation techniques match those given for the
shutdown function as well.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical to optimize
device and system performance. While the LM4925 is tolerant of external component combinations,
consideration to component values must be used to maximize overall system quality. The LM4925 is unity-gain
stable that gives the designer maximum system flexibility. The LM4925 should be used in low gain configurations
to minimize THD+N values, and maximize the signal to noise ratio. Low gain configurations require large input
signals to obtain a given output power. Input signals equal to or greater than 1Vrms are available from sources
such as audio codecs. Very large values should not be used for the gain-setting resistors. Values for Ri and Rf
should be less than 1MΩ. Please refer to the section, AUDIO POWER AMPLIFIER DESIGN, for a more
complete explanation of proper gain selection. Besides gain, one of the major considerations is the closed-loop
bandwidth of the amplifier. To a large extent, the bandwidth is dictated by the choice of external components
shown in Figure 4 and Figure 5. The input coupling capacitor, Ci, forms a first order high pass filter that limits low
frequency response. This value should be chosen based on needed frequency response and turn-on time.
SELECTION OF INPUT CAPACITOR SIZE
Amplifying the lowest audio frequencies requires a high value input coupling capacitor, Ci. A high value capacitor
can be expensive and may compromise space efficiency in portable designs. In many cases, however, the
headphones used in portable systems have little ability to reproduce signals below 60Hz. Applications using
headphones with this limited frequency response reap little improvement by using a high value input capacitor. In
addition to system cost and size, turn on time is affected by the size of the input coupling capacitor Ci. A larger
input coupling capacitor requires more charge to reach its quiescent DC voltage. This charge comes from the
output via the feedback. Thus, by minimizing the capacitor size based on necessary low frequency response,
turn-on time can be minimized. A small value of Ci (in the range of 0.1μF to 0.47μF), is recommended.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM4925
LM4925
SNAS273A –FEBRUARY 2005–REVISED APRIL 2013
www.ti.com
AUDIO POWER AMPLIFIER DESIGN
A 25mW/32ΩAudio Amplifier
Given:
Power Output 10mWrms
Load Impedance 16Ω
Input Level 0.4Vrms
Input Impedance 20kΩ
A designer must first choose a mode of operation (SE or BTL) and determine the minimum supply rail to obtain
the specified output power. By extrapolating from the Output Power vs. Supply Voltage graphs in the Typical
Performance Characteristics section, the supply rail can be easily found. 3.0V is a standard voltage in most
applications, it is chosen for the supply rail. Extra supply voltage creates headroom that allows the LM4925 to
reproduce peak in excess of 10mW without producing audible distortion. At this time, the designer must make
sure that the power supply choice along with the output impedance does not violate the conditions explained in
the POWER DISSIPATION section. Once the power dissipation equations have been addressed, the required
gain can be determined from Equation 5.
(5)
From Equation 5, the minimum AV is 1; use AV= 1. Since the desired input impedance is 20k, and with a AVgain
of 1, a ratio of 1:1 results from Equation 1 for Rfto R. The values are chosen with Ri= 20k and Rf= 20k. The
final design step is to address the bandwidth requirements which must be stated as a pair of -3dB frequency
points. Five times away from a -3dB point is 0.17dB down from passband response which is better than the
required ± 0.25dB specified.
fL= 100Hz/5 = 20Hz
fH= 20kHz * 5 = 100kHz
As stated in the PROPER SELECTION OF EXTERNAL COMPONENTS section, Riin conjunction with Ci
creates a
Ci≥1 / (2π* 20kΩ* 20Hz) = 0.397µF; use 0.39µF.
The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AV. With an AVV= 1 and fH= 100kHz, the resulting GBWP = 100kHz which is much smaller than the
LM4925GBWP of 3MHz. This example displays that if a designer has a need to design an amplifier with higher
differential gain, the LM4925can still be used without running into bandwidth limitations.
14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4925
LM4925
SNAS273A –FEBRUARY 2005–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Original (April 2013) to Revision A Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4925
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM4925MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM GB8
LM4925SD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM L4925
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4925MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM4925SD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4925MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
LM4925SD/NOPB WSON DSC 10 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
www.ti.com
SDA10A (Rev A)
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