Semiconductor Components Industries, LLC, 2002
February, 2002 – Rev. 5 1Publication Order Number:
MC14511B/D
MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and N PN bipolar output drivers i n a s ingle m onolithic s tructure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and an output drive capability. Lamp
test (LT), b lanking ( BI), and l atch e nable ( LE) i nputs a re u sed t o t est t he
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven–segment
light–emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
•Low Logic Circuit Power Dissipation
•High–Current Sourcing Outputs (Up to 25 mA)
•Latch Storage of Code
•Blanking Input
•Lamp Test Provision
•Readout Blanking on all Illegal Input Combinations
•Lamp Intensity Modulation Capability
•Time Share (Multiplexing) Facility
•Supply Voltage Range = 3.0 V to 18 V
•Capable of Driving Two Low–power TTL Loads, One Low–power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
•Chip Complexity: 216 FETs or 54 Equivalent Gates
•Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range –0.5 to +18.0 V
Vin Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V
IDC Current Drain per Input Pin 10 mA
PDPower Dissipation,
per Package (Note 3) 500 mW
TAOperating Temperature Range –55 to +125 °C
Tstg Storage Temperature Range –65 to +150 °C
IOHmax Maximum Output Drive Current
(Source) per Output 25 mA
POHmax Maximum Continuous Output
Power (Source) per Output
(Note 4)
50 mA
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
4. POHmax = IOH (VDD – VOH)
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A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14511BCP PDIP–16 2000/Box
MC14511BD SOIC–16 48/Rail
MC14511BDW SOIC–16 47/Rail
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14511BCP
AWLYYWW
MC14511BDWR2 SOIC–16 1000/Tape & Reel
SOIC–16
DW SUFFIX
CASE 751G
1
16
14511B
AWLYYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14511B
ALYW
SOIC–16
D SUFFIX
CASE 751B 1
16
14511B
AWLYWW
MC14511BF SOEIAJ–16 See Note 1
MC14511BFEL SOEIAJ–16 See Note 1
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This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it i s advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages
to this high–impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range
VSS (Vin or Vout) VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted
to VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
b
a
g
f
VDD
e
d
c
BI
LT
C
B
VSS
A
D
LE
0123456789
DISPLAY
a
b
c
d
e
fg
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
XX0XXXX1111111 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
01100001111110 0
01100010110000 1
01100101111001 2
01100111111001 3
01101000110011 4
01101011011011 5
01101100011111 6
01101111110000 7
01110001111111 8
01110011110011 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
111XXXX * *
X = Don’t Care
*Depends upon the BCD code previously applied when LE = 0
TRUTH TABLE
MC14511B
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
– 55C 25C 125C
Characteristic Symbol VDD
Vdc Min Max Min Typ
(Note 5) Max Min Max Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.1
9.1
14.1
—
—
—
4.1
9.1
14.1
4.57
9.58
14.59
—
—
—
4.1
9.1
14.1
—
—
—
Vdc
Input Voltage # “0” Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Voltage
(IOH = 0 mA) Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
VOH 5.0 4.1
—
3.9
—
3.4
—
—
—
—
—
—
—
4.1
—
3.9
—
3.4
—
4.57
4.24
4.12
3.94
3.70
3.54
—
—
—
—
—
—
4.1
—
3.5
—
3.0
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10 9.1
—
9.0
—
8.6
—
—
—
—
—
—
—
9.1
—
9.0
—
8.6
—
9.58
9.26
9.17
9.04
8.90
8.70
—
—
—
—
—
—
9.1
—
8.6
—
8.2
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15 14.1
—
14
—
13.6
—
—
—
—
—
—
—
14.1
—
14
—
13.6
—
14.59
14.27
14.18
14.07
13.95
13.70
—
—
—
—
—
—
14.1
—
13.6
—
13.2
—
—
—
—
—
—
—
Vdc
Output Drive Current
(VOL = 0.4 V) Sink
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ± 0.1 —±0.00001 ± 0.1 —± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) Vin = 0 or VDD,
Iout = 0 µA
IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current (Notes 6 & 7)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.9 µA/kHz) f + IDD
IT = (3.8 µA/kHz) f + IDD
IT = (5.7 µA/kHz) f + IDD
µAdc
5. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
6. The formulas given are for the typical characteristics only at 25C.
7. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 8) (CL = 50 pF, TA = 25C)
Characteristic Symbol VDD
Vdc Min Typ Max Unit
Output Rise Time
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns
tTLH 5.0
10
15
—
—
—
40
30
25
80
60
50
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tTHL 5.0
10
15
—
—
—
125
75
65
250
150
130
ns
Data Propagation Delay Time
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH 5.0
10
15
—
—
—
640
250
175
1280
500
350
ns
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL 5.0
10
15
—
—
—
720
290
200
1440
580
400
Blank Propagation Delay Time
tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPLH 5.0
I0
15
—
—
—
600
200
150
750
300
220
ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL 5.0
10
15
—
—
—
485
200
160
970
400
320
Lamp Test Propagation Delay Time
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPLH 5.0
10
15
—
—
—
313
125
90
625
250
180
ns
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL 5.0
10
15
—
—
—
313
125
90
625
250
180
Setup Time tsu 5.0
10
15
100
40
30
—
—
—
—
—
—
ns
Hold Time th5.0
10
15
60
40
30
—
—
—
—
—
—
ns
Latch Enable Pulse Width tWL 5.0
10
15
520
220
130
260
110
65
—
—
—
ns
8. The formulas given are for the typical characteristics only.
MC14511B
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Figure 1. Dynamic Power Dissipation Signal Waveforms
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
VSS
VOH
VOL
90%
50%
10%
50%
A, B, AND C
ANY OUTPUT
50% DUTY CYCLE
1
2f
Figure 2. Dynamic Signal Waveforms
20 ns 20 ns
VDD
90%
INPUT C
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
VSS
VOH
VOL
50%
10%
OUTPUT g
tPLH tPHL
90%
10%
50%
tTLH tTHL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
10%
90%
50%
VDD
VSS
VDD
VSS
VOH
VOL
th
tsu
50%
INPUT C
OUTPUT g
LE
(c) Data DCBA strobed into latches.
20 ns 20 ns
VDD
VSS
LE
90%
50%
10%
tWL
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6
CONNECTIONS TO VARIOUS DISPLAY READOUTS
COMMON
CATHODE LED
≈ 1.7 V
VDD
VSS
VDD
COMMON
ANODE LED
VSS
≈ 1.7 V
LIGHT EMITTING DIODE (LED) READOUT
INCANDESCENT READOUT FLUORESCENT READOUT
GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT
VDD VDD
**
VSS
VDD
VSS
FILAMENT
SUPPLY
DIRECT
(LOW BRIGHTNESS)
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V )
VDD
APPROPRIATE
VOLTAGE
VSS VSS
VDD
EXCITATION
(SQUARE WAVE,
VSS TO VDD)
1/4 OF MC14070B
**A filament pre–warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
Direct dc drive of LCD’s not recommended for life of
LCD readouts.
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7
Figure 3. Logic Diagram
LE5
D6
C2
B1
A7
VDD = PIN 16
VSS = PIN 8
BI4
LT3
14g
15f
9e
10d
11c
12b
13a
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8
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
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PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019

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10
PACKAGE DIMENSIONS
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
0 7
MC14511B
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PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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12
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