UCC28019 www.ti.com SLUS755 - APRIL 2007 8-Pin Continuous Conduction Mode (CCM) PFC Controller FEATURES * * * * * * * * * DESCRIPTION 8-pin Solution Without Sensing Line Voltage Reduces External Components Wide-Range Universal AC Input Voltage Fixed 65-kHz Operating Frequency Maximum Duty Cycle of 97% Output Over/Under-Voltage Protection Input Brown-Out Protection Cycle-by-Cycle Peak Current Limiting Open Loop Detection Low-Power User Controlled Standby Mode APPLICATIONS * * * * * CCM Boost Power Factor Correction Power Converters in the 100 W to >2 kW Range Server and Desktop Power Supplies Telecom Rectifiers Industrial Electronics Home Electronics CONTENTS * * * * * Electrical Characteristics 3 Device Information 10 Application Information 12 Design Example 23 Additional References 43 The UCC28019 8-pin active Power Factor Correction (PFC) controller uses the boost topology operating in Continuous Conduction Mode (CCM). The controller is suitable for systems in the 100 W to >2 kW range over a wide-range universal AC line input. Startup current during under-voltage lockout is less than 200 A. The user can control low power standby mode by pulling the VSENSE pin below 0.77 V. Low-distortion wave-shaping of the input current using average current mode control is achieved without input line sensing, reducing the Bill of Materials component count. Simple external networks allow for flexible compensation of the current and voltage control loops. The switching frequency is internally fixed and trimmed to better than 5% accuracy at 25C. Fast 1.5-A gate peak current drives the external switch. Numerous system-level protection features include peak current limit, soft over-current, open-loop detection, input brown-out, output over/under-voltage, a no-power discharge path on VCOMP, and overload protection on ICOMP. Soft-Start limits boost current during start-up. A trimmed internal reference provides accurate protection thresholds and regulation set-point. An internal clamp limits the gate drive voltage to 12.5 V. TYPICAL APPLICATION DIAGRAM VOUT EMI Filter LINE INPUT - Bridge Rectifier + 1 GND 2 ICOMP 3 ISENSE 4 VINS GATE 8 VCC 7 VSENSE 6 VCOMP 5 Auxilary Supply Rload UCC28019 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007, Texas Instruments Incorporated UCC28019 www.ti.com SLUS755 - APRIL 2007 ORDERING INFORMATION (1) OPERATING TEMPERATURE RANGE, TA PART NUMBER PACKAGE (1) UCC28019D SOIC 8-Pin (D) ead (Pb)-Free/Green UCC28019P Plastic DIP 8 Pin (P) Lead (Pb)-Free/Green -40C to 125C SOIC (D) package is available taped and reeled by adding "R" suffix the the above part number, reeled quantities are 2500 devices per reel. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE Input voltage range Input current range Junction temperature, TJ Lead temperature, TSOL (1) VCC -0.3 to 22 GATE -0.3 to 16 VINS, VSENSE, VCOMP, ICOMP -0.3 to 7 ISENSE -24 to 7 VSENSE, ISENSE -1 to 1 Operating -55 to 150 Storage -65 to 150 Soldering, 10s UNIT V mA C 300 Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability. DISSIPATION RATINGS (1) (1) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT (C/W) TA = 25C POWER RATING (W) TA = 85C POWER RATING (W) SOIC-8 (D) 160 0.65 0.25 PDIP-8 (P) 110 1 0.36 Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a general guide. See TI document SPRA953 Thermal Metrics. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN VCC input voltage from a low-impedance source TJ MAX UNIT VCCOFF(max) + 1 V 21 V -40 125 C Operating junction temperature ELECTROSTATIC DISCHARGE (ESD) PROTECTION over operating free-air temperature range (unless otherwise noted) PARAMETER RATING Human Body Model (HBM) Charged Device Model (CDM) 2 Submit Documentation Feedback UNIT 2 kV 500 V UCC28019 www.ti.com SLUS755 - APRIL 2007 ELECTRICAL CHARACTERISTICS Unless otherwise noted, VCC = 15 VDC, 0.1 F from VCC to GND, -40C TJ = TA 125C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Bias Supply IVCC(start) Pre-start current VCC = VCCON- 0.1 V 25 100 200 IVCC(stby) Standby current VSENSE = 0.5 V 1.0 2.1 2.9 IVCC(on_load) Operating current VSENSE = 4.5 V, CGATE = 4.7 nF 4 7 10 10.0 10.5 11.0 A mA Under Voltage Lockout (UVLO) VCCON Turn on threshold VCCOFF Turn off threshold UVLO Hysteresis 9 9.5 10 0.8 1.0 1.2 61.7 65.0 68.3 59 65 71 V Oscillator fSW TA = 25C Switching frequency, - 40C TA 125C kHz PWM DMIN Minimum duty cycle VCOMP = 0 V, VSENSE = 5 V, ICOMP = 6.4 V DMAX Maximum duty cycle VSENSE = 4.95 V tOFF(min) Minimum off time VSENSE = 3 V, ICOMP = 1 V 0% 94% 97% 99.3% 100 250 600 ns System Protection VSOC ISENSE threshold, soft over current (SOC) , -0.66 -0.73 -0.79 VPCL ISENSE threshold, peak current Limit (PCL) , -1.00 -1.08 -1.15 VOLP VSENSE threshold, open loop protection (OLP), ICOMP = 1 V, ISENSE = 0 V, VCOMP = 1 V 0.77 0.82 0.86 Open loop protection (OLP) internal pull-down current VSENSE = 0.5 V 100 250 4.63 4.75 4.87 5.12 5.25 5.38 VUVD VSENSE threshold, output under-voltage detection (UVD), VOVP VSENSE threshold, output over-voltage protection (OVP), VINSBROWNOUT_th Input brown-out detection (IBOP) high-to-low threshold 0.76 0.82 0.88 VINSENABLE_th Input brown-out Detection (IBOP) low-to-high threshold 1.4 1.5 1.6 IVINS_0 VINS bias current 0 0.1 V ISENSE = -0.2 V V nA V VINS = 0 V ICOMP threshold, external overload protection Submit Documentation Feedback 0.6 A V 3 UCC28019 www.ti.com SLUS755 - APRIL 2007 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, VCC = 15 VDC, 0.1 F from VCC to GND, -40C TJ = TA 125C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current Loop gmi Transconductance gain TA = 25C 0.75 Output linear range 0.95 1.15 50 ICOMP voltage during OLP VSENSE = 0.5 V VREF Reference voltage -40C TA 125C gmv Transconductance gain mS A 3.7 4.0 4.3 V 4.90 5.00 5.10 V 31.5 42 52.5 S 21 30 38 Voltage Loop Maximum sink current under normal operation VSENSE = 6 V, VCOMP = 4 V Source current under soft start VSENSE = 4 V, VCOMP = 0 V -21 -30 -38 Maximum source current under EDR operation VSENSE = 4 V, VCOMP = 0 V -100 -170 -250 VSENSE = 4 V, VCOMP = 4 V -60 -100 -140 4.63 4.75 4.87 V 100 250 nA 0.2 0.4 V Enhanced dynamic response, VSENSE low threshold, falling VSENSE input bias current 1 V VSENSE 5 V VCOMP voltage during OLP VSENSE = 0.5 V, IVCOMP = 0.5 mA GATE current, peak, sinking (1) CGATE = 4.7 nF 2.0 CGATE = 4.7 nF -1.5 0 A GATE Driver GATE current, peak, (1) 4 sourcing (1) A GATE rise time CGATE = 4.7 nF, GATE = 2 V to 8 V 40 60 GATE fall time CGATE = 4.7 nF, GATE = 8 V to 2 V 25 40 GATE low voltage, no load GATE = 0 A 0 0.05 GATE low voltage, sinking GATE = 20 mA 0.3 0.8 GATE low voltage, sourcing GATE = -20 mA -0.3 -0.8 GATE low voltage, sinking VCC = 5 V, GATE = 5 mA 0.2 0.75 1.2 GATE low voltage, sinking VCC = 5 V, GATE = 20 mA 0.2 0.9 1.5 GATE high voltage VCC = 20 V, CGATE = 4.7 nF 11 12.5 14 GATE high voltage VCC = 11 V, CGATE = 4.7 nF 9.5 10.5 11.0 GATE high voltage VCC = VCCOFF + 0.2 V, CGATE = 4.7 nF 8.0 9.0 10.2 Not tested. Characterized by design. Submit Documentation Feedback ns V UCC28019 www.ti.com SLUS755 - APRIL 2007 TYPICAL CHARACTERISTICS Unless otherwise noted, VCC = 15 VDC, 0.1 F from VCC to GND, TJ = TA = 25C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal. SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE UVLO THRESHOLDS vs TEMPERATURE 4.0 12.0 VSENSE = VINS = 3V No Gate Load 11.0 VCC Turn ON (VCCON) 3.0 IVCC - Supply Current - mA VCCON/VCCOFF - UVLO Threshold - V 3.5 10.0 2.5 2.0 IVCC Turn OFF IVCC Turn ON 1.5 1.0 VCC Turn OFF (VCCOFF) 9.0 0.5 0 8.0 0 -60 -35 -10 15 40 65 90 115 5 140 10 15 20 VCC - Bias Supply Voltage - V TJ - Temperature - C Figure 1. Figure 2. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 10 0.5 VCC = VCCON - 0.1 V 9 7 IVCC(start) - Supply Current - mA IVCC - Supply Current - mA 8 Operating, GATE Load = 4.7 nF IVCC(on_load) 6 5 4 Standby IVCC(stby) 3 2 0.4 0.3 0.2 Pre-Start (IVCC(start)) 0.1 1 0 0 -60 -35 -10 15 40 65 90 115 140 -60 TJ - Temperature - C Figure 3. -35 -10 15 40 65 90 TJ - Temperature - C 115 140 Figure 4. Submit Documentation Feedback 5 UCC28019 www.ti.com SLUS755 - APRIL 2007 TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs BIAS SUPPLY VOLTAGE 75 75 73 73 71 71 fSW - Switching Frequency - kHz fSW - Switching Frequency - kHz OSCILLATOR FREQUENCY vs TEMPERATURE 69 Switching Frequency 67 65 63 61 59 69 67 Switching Frequency 65 63 61 59 57 57 55 55 -60 -35 -10 15 40 65 90 115 140 12 10 TJ - Temperature - C Figure 5. 50 1.8 48 1.6 46 1.4 44 gmv - Gain - A/V gmi - Gain - mA/V 20 VOLTAGE ERROR AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE Gain 1.2 1.0 0.8 Gain 42 40 38 0.6 36 0.4 34 0.2 32 0 30 -60 -35 -10 15 40 65 90 115 140 -60 TJ - Temperature - C -35 -10 15 40 65 TJ - Temperature - C Figure 7. 6 18 16 Figure 6. CURRENT AVERAGING AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE 2.0 14 VCC - Bias Supply Voltage - V Figure 8. Submit Documentation Feedback 90 115 140 UCC28019 www.ti.com SLUS755 - APRIL 2007 TYPICAL CHARACTERISTICS (continued) VSENSE THRESHOLD vs TEMPERATURE VSENSE THRESHOLD vs TEMPERATURE 5.50 2.0 VOVP / VUVD- VSENSE Threshold - V VOLP - VSENSE Threshold - V 1.8 1.6 1.4 1.2 1.0 Open Loop Protection (VOLP) 0.8 0.6 0.4 5.25 Over-Voltage Protection (VOVP) 5.00 4.75 Under-Voltage Protection (VUVD) 0.2 4.50 0 -60 -35 -10 15 40 65 90 TJ - Temperature - C 115 -60 140 -35 -10 Figure 9. 0 1.8 -0.1 1.6 -0.2 VSOC - ISENSE Threshold - V VINSENABLE_TH / VINSBROUWNOUT_TH - VINS Threshold - V 140 115 140 ISENSE THRESHOLD vs TEMPERATURE 2.0 VINS Enable (VINSENABLE_TH) 1.2 1.0 0.8 0.6 115 Figure 10. VINS THRESHOLD vs TEMPERATURE 1.4 15 40 65 90 TJ - Temperature - C Input Brown-Out Protection (VINSBROWNOUT_TH) -0.3 -0.4 -0.5 -0.6 Soft Over-Current Protection (SOC) -0.7 -0.8 0.4 -0.9 0.2 -1.0 0 -60 -35 -10 15 40 65 90 TJ - Temperature - C 115 140 -60 Figure 11. -35 -10 15 40 65 90 TJ - Temperature - C Figure 12. Submit Documentation Feedback 7 UCC28019 www.ti.com SLUS755 - APRIL 2007 TYPICAL CHARACTERISTICS (continued) MINIMUM OFF TIME vs TEMPERATURE GATE DRIVE SWITCHING vs TEMPERATURE 600 50 VSENSE = 3 V ICOMP = 1 V 500 40 450 35 400 30 350 300 CGATE = 4.7 nF VGATE = 2 V - 8 V 45 t - Time - ns t - Time - ns 550 tOFF(min) 25 20 250 15 200 10 105 5 100 Fall Time Rise Time 0 -60 -35 -10 15 40 65 90 115 -60 140 -35 -10 TJ - Temperature - C 15 Figure 13. 50 115 140 115 140 VCC = 5 V IVCC = 20 mA 1.8 VGATE - Gate Low Voltage - V 1.6 35 30 Rise Time 25 20 Fall Time 15 10 1.4 1.2 VGATE 1.0 0.8 0.6 0.4 5 0.2 0 10 12 14 16 18 VCC - Bias Supply Voltage - V 20 0 -60 -35 -10 15 40 65 TJ - Temperature - C Figure 15. 8 90 GATE LOW VOLTAGE WITH DEVICE OFF vs TEMPERATURE 2.0 CGATE = 4.7 nF VGATE = 2 V - 8 V 40 t - Time - ns 65 Figure 14. GATE DRIVE SWITCHING vs BIAS SUPPLY VOLTAGE 45 40 TJ - Temperature - C Figure 16. Submit Documentation Feedback 90 UCC28019 www.ti.com SLUS755 - APRIL 2007 TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE vs TEMPERATURE 5.50 VREF - Reference Voltage - V VCC = 15V 5.25 Reference Voltage 5.00 4.75 4.50 -60 -35 -10 15 40 65 90 TJ - Temperature - C 115 140 Figure 17. Submit Documentation Feedback 9 UCC28019 www.ti.com SLUS755 - APRIL 2007 DEVICE INFORMATION Connection Diagram UCC28019 Top View (SOIC-8, PDIP-8) GATE 8 2 ICOMP VCC 7 3 ISENSE VSENSE 6 VINS VCOMP 5 1 GND 4 Pin Descriptions Terminal Functions TERMINAL NAME # GATE 8 GND 1 ICOMP 2 ISENSE VCC VCOMP VINS VSENSE 10 3 I/O FUNCTION O Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. 2.0-A sink and 1.5-A source capability. Output voltage is clamped at 12.5 V. Ground: Device ground reference. O Current loop compensation: Transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.6 V. I Inductor current sense: An input for the voltage across the external current sense resistor, which represents the instantaneous current through the PFC boost inductor. This voltage is averaged to eliminate the effects of noise and ripple. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. Use a 220- resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin. 7 Device supply: External bias supply input. Under Voltage Lock Out (UVLO) disables the controller until VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off (UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 F minimum value should be connected from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage. 5 O Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE voltage reaches 95% of its nominal regulation level. When the Enhanced Dynamic Response (EDR) is engaged, additional current is applied to VCOMP to reduce the charge time. EDR additional current is inhibited during soft-start. Soft-start is programmed by the capacitance on this pin. I Input ac voltage sense: Input Brown Out Protection (IBOP) detects when the system ac-input voltage is above a user-defined normal operating level, or below a user-defined "brown-out" level. A filtered resistor-divider network connects from this pin to the rectified-mains node. At startup the controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft-start. The controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft-start. I Output voltage sense: An external resistor-divider network connected from this pin to the PFC output voltage provides feedback sensing for output voltage regulation. A small capacitor from this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8V. An internal 100nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin disconnection. Output over-voltage protection (OVP) disables the GATE output when VSENSE exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load step causes VSENSE to fall below 95% of the reference voltage. 4 6 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 EMI Filter LBST LINE INPUT - Bridge Rectifier DBST VOUT + RVINS1 QBST CIN RFB1 RGATE COUT RVINS2 RLOAD RFB2 10k RSENSE ICOMP 2 CICOMP Current Amplifier + FAULT gmi VCC PWM Comparator KPC(s) ICOMP Gate Driver S Q R Q + GAIN M1 Fault IBOP PWM RAMP M2 UVLO Fault Logic GATE OLP Min Off Time 65kHz Oscillator PCL 8 S Q R Q OVP Clock M2 M1 SOC RISENSE Pre-Drive and Clamp Circuit VCOMP UVLO EDR VCC + ISENSE 40k 40k 3 -1x CISENSE Q S Q R VCCON 10.5V Peak Current Limit (PCL) 300ns Leading Edge Blanking VPCL 1.08V PCL Auxilary Supply 7 CVCC GND UVLO + VCCOFF 9.5V 1 + + + OVERVOLTAGE 5.25V OVP Soft Over Current (SOC) SOC VSOC 0.73V + OLP/STANDBY 0.82V + UNDERVOLTAGE 4.75V + 5V OLP/STANDBY + VINS 20k EDR Input Brown-Out Protection (IBOP) 4 + CVINS S VINENABLE_th 1.5V 5V VINBROWNOUT_th 0.82V SS EDR Q IBOP + R VSENSE gmv Q FAULT Voltage Error Amplifier 6 CVSENSE 100A VCOMP 5 RVCOMP CVCOMP-P CVCOMP Figure 18. Block Diagram Submit Documentation Feedback 11 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION UCC28019 Operation The UCC28019 is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28019 requires few external components to operate as an active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz, ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum are below the EN55022 conducted-band 150-kHz measurement limit. Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85 VAC to 265 VAC mains input range from zero to full output load. The usable system load ranges from 100 W to 2 kW and may be extended in special situations. Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under extremely light load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-D requirements of IEC 1000-3-2 despite the higher harmonics. The outer voltage loop regulates the output voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain parameters for maintaining a low-distortion steady-state input current waveshape. 12 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Power Supply The UCC28019 operates from an external bias supply. It is recommended that the device be powered from a regulated auxiliary supply. This device is not intended to be used from a bootstrap bias supply. A bootstrap bias supply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up the voltage on VCC until current can be supplied from a bias winding on the boost inductor. The minimal hysteresis on VCC would require an unreasonable value of hold-up capacitance. During normal operation, when the output is regulated, current drawn by the device includes the nominal run current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor with a minimum value of 0.1 F is recommended from VCC to GND with short, wide traces. VCC VCCON 10.5V VCCOFF 9.5V IVCC IVCC(ON) IVCC(stby) <2.9mA IVCC(start) <200A Controller State PWM State UVLO Soft-Start Run Fault/Standby OFF Ramp Regulated OFF SoftStart Run Ramp Regulated UVLO OFF Figure 19. Device Supply States The device bias operates in several states. During startup, VCC Under-Voltage LockOut (UVLO) sets the minimum operational dc input voltage of the PFC controller. There are two UVLO thresholds. When the UVLO turn-on threshold is exceeded, the controller turns ON. If VCC falls below the UVLO lower turn-off threshold, the controller turns OFF. During UVLO, current drawn by the device is minimal. After the device turns on, Soft Start (SS) is initiated and the output is ramped up in a controlled manner to reduce the stress on the external components and prevents output voltage overshoot. During soft start and after the output is in regulation, the device draws its normal run current. If any of several fault conditions is encountered or if the device is put in Standby with an external signal, the device draws a reduced standby current. Submit Documentation Feedback 13 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Soft Start VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO, IBOP, and OLP(Open-Loop Protection)/STANDBY. After the fault condition is released, soft start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a function of time. During soft start a constant 30 A of current is sourced into the compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85% of its final value. At this point, the sourcing current begins to decrease until the output voltage reaches 95% of its final rated voltage. The soft-start time is controlled by the voltage error amplifier compensation components selected, and is user-programmable based on desired loop crossover frequency. Once VOUT exceeds 95% of rate voltage, EDR is no longer inhibited. + VCOMP 5V gmv VSENSE FAULT VCOMP ISS = -30uA for VSENSE < 4.75V during Soft-Start Figure 20. Soft Start System Protection System level protection features keep the system in safe operating limits: OVP 105% VREF 100% VREF EDR 95% VREF Feedback Voltage OLP/SS 16% VREF Protection State OLP Soft-Start (No EDR) Run OVP (No Gate Output) Run Figure 21. Output Protection States 14 Submit Documentation Feedback UVD (EDR on) OLP UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) VCC Under-Voltage Lockout (UVLO) During startup, UVLO keeps the device in the off state until VCC rises above the 10.5-V enable threshold, VCCON. With a typical 1 V of hysteresis on UVLO to eliminate noise, the device turns off when VCC drops to the 9.5-V disable threshold, VCCOFF. VCC Auxilary Supply + S VCCON 10.5V CDECOUPLE UVLO R GND VCCOFF 9.5V Q Q + Figure 22. UVLO Input Brown-Out Protection (IBOP) The VINS, (sensed input line voltage), input provides a means for the designer to set the desired mains RMS voltage level at which the PFC pre-regulator should start-up, VAC(turnon), as well as the desired mains RMS level at which it should shut down, VAC(turnoff). This prevents unwanted sustained system operation at or below a "brown-out" voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC UVLO turn-off. RVINS1 VINS 20k Input Brown-Out Protection (IBOP) Rectified AC Line + CIN RVINS2 VINENABLE_th 1.5 V CVINS 5V VINBROWNOUT_th 0.82 V S Q R Q IBOP + Figure 23. Input Brown-Out Protection (IBOP) Input line voltage is sensed directly from the rectified ac mains voltage through a resistor divider filter network providing a scaled and filtered value at the VINS input. IBOP puts the device in standby mode when VINS falls (high-to-low) below 0.8 V, VINSBROWNOUT_th. The device comes out of standby when VINS rises (low-to-high) above 1.5 V, VINSENABLE_th. IVINS_0 V , bias current sourced from VINS, is less than 0.1 A. With a bias current this low, there is little concern for any set-point error caused by this current flowing through the sensing network. The highest reasonable value resistance for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise pickup, but low noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used and its voltage rating, RVINS1 should be implemented with multiple resistors in series to reduce voltage stresses. Submit Documentation Feedback 15 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) First, select RVINS1 based on the the highest reasonable resistance value available for typical applications. Then select RVINS2 based on this value: RVINS 2 = RVINS 1 VINS ENABLE _ th(max) 2VAC( on ) - VINS ENABLE _ th(max) - VF _ BRIDGE Where VF_Bridge is the forward voltage drop across the ac rectifier bridge. Power dissipated in the resistor network is: PVINS = VIN _ RMS 2 RVINS 1 + RVINS 2 The filter capacitor, CVINS, has two functions. First, to attenuate the voltage ripple to levels between the enable and brown-out thresholds which will prevent the ripple on VINS from falsely triggering IBOP when the converter is operating at low line. Second, CVINS delays the brown-out protection operation for a desired number of line half-cycle periods while still having a good response to an actual brown-out event. The capacitor is chosen so that it will discharge to the VINSBROWNOUT_th level after N number of half line cycles of delay to accommodate line dropouts. -tCVIN _ dschg CVINS = e e VINS BROWNOUT _ th(min) RVINS 2 ln e RVINS 2 e 0 .9 V IN _ RMS (min) ( ee RVINS 1 + RVINS 2 u u u )u uu Where: tCVINS _ dschrg = N half _ cycles 2 f LINE(min) and VIN_RMS(min) is the lowest normal operating RMS input voltage. 16 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Output Over-Voltage Protection (OVP) VOUT(OVP) is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold (5-V reference voltage + 5%), VOVP. The normal voltage control loop is bypassed and the GATE output is disabled until VSENSE falls below 5.25 V. For example, VOUT(OVP) is 420 V in a system with a 400-V rated output. Open Loop Protection/Standby (OLP/Standby) If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage, causing VSENSE to fall below 0.8 V, the device is put in Standby, a state where the PWM switching is halted and the device is still on but draws standby current below 3 mA. This shutdown feature also gives the designer the option of pulling VSENSE low with an external switch. Output Under-Voltage Detection (UVD) / Enhanced Dynamic Response (EDR) During large changes in load, Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop. Output Voltage RFB1 Standby VSENSE RFB2 Optional + OVP OVERVOLTAGE 5.25V UNDERVOLTAGE 4.75V + UVD OPEN LOOP PROTECTION/ STANDBY 0.82V + OLP/STANDBY Figure 24. Over Voltage Protection, Open Loop Protection/Standby Submit Documentation Feedback 17 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Overcurrent Protection Inductor current is sensed by RSENSE, a low value resistor in the return path of input rectifier. The other side of the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is always negative. There are two over-current protection features; Peak Current Limit (PCL) protects against inductor saturation and Soft Over Current (SOC) protects against an overload on the output. Soft Over Current (SOC) LINE INPUT - SOC VSOC 0.73V + VOUT + RSENSE ISENSE CISENSE RISENSE 300ns Leading Edge Blanking VPCL 1.08V (Optional) PCL + + -1x Peak Current Limit (PCL) Figure 25. Soft Over Current (SOC) / Peak Current Limit (PCL) Soft Over-Current (SOC) SOC limits the input current. SOC is activated when the current sense voltage on ISENSE reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty cycle. Peak Current Limit (PCL) Peak current limit operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE reaches -1.08 V, PCL is activated terminating the active switch cycle. The voltage at ISENSE is amplified by a fixed gain of -1.0 and then leading-edge blanked to improve noise immunity against false triggering. 18 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Current Sense Resistor, RSENSE The current sense resistor, RSENSE, is sized using the minimum threshold value of Soft Over Current (SOC), VSOC(min) = 0.66 V. To avoid triggering this threshold during normal operation, taking into account the gain of the internal non-linear power limit, resulting in a decreased duty cycle, the resistor is typically sized for an overload current of 25% more than the peak inductor peak current. RSENSE VSOC(min) 1.25 I L _ PEAK (max) Since RSENSE sees the average input current, worst-case power dissipation occurs at input low line when input line current is at its maximum. Power dissipated by the sense resistor is: PRSENSE = ( I IN _ RMS (max) )2 R SENSE Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor reaches the PCL threshold, VPCL. The absolute maximum peak current, IPCL, is given as: I PCL = VPCL RSENSE Gate Driver The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to 12.5 V. An external gate drive resistor, RGATE, limits the rise time and dampens ringing caused by parasitic inductances and capacitances of the gate drive circuit thus reducing EMI. The final value of the resistor depends upon the parasitic elements associated with the layout and other considerations. A 10-k resistor close to the gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and protects against inadvertent dv/dt-triggered turn-on. VCC UVLO From PWM Latch Fault Logic OLP VCC Rectified AC L BST DBST VOUT QBST IBOP GATE COUT RGATE PCL OVP S 10k Q GND Clock R Q Pre-Drive and Clamp Circuit Figure 26. Gate Driver Submit Documentation Feedback 19 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Current Loop The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator (PWM) stage, the external boost inductor stage, and the external current sensing resistor. ISENSE and ICOMP Functions The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-line voltage range. ICOMP is connected to 4 V internally whenever the device is in a Fault or Standby condition. Pulse Width Modulator The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output signal which is high whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined by a non-linear function of the internal VCOMP voltage. The PWM output signal always starts low at the beginning of the cycle, triggered by the internal clock. The output stays low for a minimum off-time, tOFF(min), after which the ramp rises linearly to intersect the ICOMP voltage. The ramp-ICOMP intersection determines tOFF, and hence DOFF. Since DOFF = VIN/VOUT by the boost-topology equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor current, it follows that the control loop forces the inductor current to follow the input voltage wave-shape to maintain boost regulation. Therefore, the average input current is also sinusoidal in wave-shape. Control Logic The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various protection functions incorporated into the IC. The GATE output duty-cycle may be as high as 99%, but will always have a minimum off-time tOFF(min). Normal duty-cycle operation can be interrupted directly by OVP and PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and further inhibit output until the SS operation can begin. Voltage Loop The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing stage, the voltage error amplifier stage, and the non-linear gain generation. Output Sensing A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference voltage. Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves to filter the signal in a high-noise environment. This filter time constant should generally be less than 100 s. 20 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Voltage Error Amplifier The transconductance error amplifier (gmv) generates an output current proportional to the difference between the voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system operating conditions. Proper selection of the compensation network components leads to a stable PFC pre-regulator over the entire ac-line range and 0-100% load range. The total capacitance also determines the rate-of-rise of the VCOMP voltage at soft start, as discussed earlier. The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge the compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays complete discharge by their respective time constant (which may be several hundred milliseconds). If VCC bias voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large capacitor could be left with substantial voltage on it, negating the benefit of a subsequent Soft-Start. The UCC28019 incorporates a parallel discharge path which operates without VCC bias, to further discharge the compensation network after VCC is removed. When output voltage perturbations greater than 5% appear at the VSENSE input, the amplifier moves out of linear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSE returns within 5% of regulation. On an under-voltage, the UVD function invokes EDR which immediately increases the internal VCOMP voltage by 2 V and increases the external VCOMP charging current typically to 100 A to 170 A. This higher current facilitates faster charging of the compensation capacitors to the new operating level, improving transient response time. Non-linear Gain Generation The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is buffered internally and is then subject to modification by the EDR function and the SOC function, as discussed earlier. Together the current gain and the PWM slope adjust to the different system operating conditions (set by the ac-line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor input current wave-shape following that of the input voltage. Submit Documentation Feedback 21 UCC28019 www.ti.com SLUS755 - APRIL 2007 APPLICATION INFORMATION (continued) Layout Guidelines As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. The pinout of the UCC28019 is ideally suited for separating the high di/dt induced noise on the power ground from the low current quiet signal ground required for adequate noise immunity. A star point ground connection at the GND pin of the device can be achieved with a simple cut out in the ground plane of the printed circuit board. As shown in Figure 27, the capacitors on ISENSE, VINS, VCOMP, and VSENSE (C11, C12, C15, C17, and C16, respectively) must all be returned directly to the quiet portion of the ground plane, indicated by Signal GND, and not the high current return path of the converter, shown as the Power GND. Because the example circuit in Figure 27 uses surface mount components, the ICOMP capacitor, C10, has its own dedicated return to the GND pin. Power GND Cut out in ground plane GND GATE ICOMP VCC ISENSE VSENSE VINS VCOMP Signal GND Figure 27. Recommended Layout for the UCC28019 22 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 DESIGN EXAMPLE 350-W, Universal Input, 390-VDC Output, PFC Converter Design Goals This example illustrates the design process and component selection for a continuous conduction mode power factor correction boost converter utilizing the UCC28019. The target design is a universal input, 350W PFC designed for an ATX supply application. This design process is directly tied to the UCC28019 Design Calculator spreadsheet that can be found in the Tools section of the UCC28019 product folder on the Texas Instruments website. Table 1. Design Goal Parameters PARAMETER TEST CONDITION MIN TYP MAX UNIT Input characteristics Input voltage VIN 85 Input frequency fLINE 47 Brown out voltage 115 VAC(on) IOUT = 0.9 A 75 VAC(off) IOUT = 0.9 A 65 265 VAC 63 Hz VAC Output characteristics Output voltage VOUT 85 VAC VIN 265 VAC 47 Hz fLINE 63 Hz 0 A IOUT 0.9 A Line regulation 85 VAC VIN 65VAC IOUT = 0.440 A 5% VIN = 115 VAC, fLINE = 60 Hz 0 A IOUT 0.9 A 5% VIN = 230 VAC, fLINE = 50 Hz 0 A IOUT 0.9 A 5% VRIPPLE(SW) VIN = 115 VAC, fLINE = 60 Hz IOUT = 0.9 A 3.9 VRIPPLE(SW) VIN = 230 VAC , fLINE = 50 Hz IOUT = 0.9 A 3.9 VRIPPLE(f_LINE) VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A 19.5 VRIPPLE(f_LINE) VIN = 230 VAC, fLINE = 50 Hz IOUT = 0.9 A 19.5 Load regulation High frequency output voltage ripple Line frequency output voltage ripple 370 390 VDC Vpp Output load current IOUT 85 VAC VIN 265 VAC 47 Hz fLINE 63 Hz Output power POUT Output over voltage protection VOUT(OVP) 410 Output under voltage protection VOUT(UVP) 370 Submit Documentation Feedback 410 0.9 A 350 W V 23 UCC28019 www.ti.com SLUS755 - APRIL 2007 DESIGN EXAMPLE (continued) Table 1. Design Goal Parameters (continued) PARAMETER TEST CONDITION MIN TYP MAX UNIT Control loop characteristics Switching frequency fSW, TJ = 25C Control loop bandwidth f(CO) VIN = 162 VDC, IOUT = 0.45 A 10 Hz Phase margin VIN = 162 VDC, IOUT = 0.45 A 70 degrees Power factor PF VIN = 115 VAC, IOUT = 0.9 A Total harmonic distortion 61.7 68.3 4.13% 10% THD VIN = 230 VAC, fLINE = 50 Hz IOUT = 0.9 A 6.67% 10% VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A Ambient temperature TAMB 0.92 50 Submit Documentation Feedback kHz 0.99 THD VIN = 115 VAC, fLINE = 60 Hz IOUT = 0.9 A Full load efficiency 24 65 C UCC28019 www.ti.com SLUS755 - APRIL 2007 + + The following procedure refers to the schematic shown in Figure 28. Figure 28. Design Example Schematic Submit Documentation Feedback 25 UCC28019 www.ti.com SLUS755 - APRIL 2007 Current Calculations First, determine the maximum average output current, IOUT(max): I OUT (max) = I OUT (max) = POUT (max) VOUT 350 W @ 0 .9 A 390 V The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the efficiency and power factor initial assumptions: POUT (max) I IN _ RMS (max) = I IN _ RMS (max) = hVIN (min) PF 350W = 4.52 A 0.92 85V 0.99 Based upon the calculated RMS value, the maximum peak input current, IIN_PEAK(max), and the maximum average input current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined. I IN _ PEAK (max) = 2 I IN _ RMS (max) I IN _ PEAK (max) = 2 4.52 A = 6.39 A I IN _ AVG(max) = 2 I IN _ PEAK (max) p I IN _ AVG(max) = 2 6.39 A = 4.07 A p Bridge Rectifier Assuming a forward voltage drop, VF_BRIDGE, of 0.95 V across the rectifier diodes, BR1, the power loss in the input bridge, PBRIDGE, can be calculated: PBRIDGE = 2VF _ BRIDGE I IN _ AVG(max) PBRIDGE = 2 0.95V 4.07 A = 7.73W 26 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 Input Capacitor Note that the UCC28019 is a continuous conduction mode controller and as such the inductor ripple current should be sized accordingly. Allowing an inductor ripple current, IRIPPLE, of 20% and a high frequency voltage ripple factor, VRIPPLE_IN, of 6%, the maximum input capacitor value, CIN, is calculated by first determining the input ripple current, IRIPPLE, and the input voltage ripple, VIN_RIPPLE(max): I RIPPLE = DI RIPPLE I IN _ PEAK (max) DI RIPPLE = 0.2 I RIPPLE = 0.2 6.39 A = 1.28 A VIN _ RIPPLE(max) = DVRIPPLE _ INVIN _ RECTIFIED(max) DVRIPPLE _ IN = 0.06 VIN _ RECTIFIED = 2VIN VIN _ RECTIFIED(max) = 2 265V = 375V VIN _ RIPPLE(max) = 0.06 375V = 7.21V The value for the input x-capacitor can now be calculated: CIN = CIN = I RIPPLE 8 f SW VIN _ RIPPLE(max) 1.28 A = 0.341m F 8 65kHz 7.21V Submit Documentation Feedback 27 UCC28019 www.ti.com SLUS755 - APRIL 2007 Boost Inductor The boost inductor, LBST, is selected after determining the maximum inductor peak current, IL_PEAK(max): I L _ PEAK (max) = I IN _ PEAK (max) + I L _ PEAK (max) = 6.39 A + I RIPPLE 2 1.28 A = 7.03 A 2 The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5: LBST (min) VOUT D( 1 - D ) f SW ( typ ) I RIPPLE LBST (min) 390V 0.5( 1 - 0.5 ) 1.17 mH 65kHz 1.28 A The actual value of the boost inductor that will be used is 1.25 mH. The maximum duty cycle, DUTY(max), can be calculated and will occur at the minimum input voltage: DUTY(max) = VOUT - VIN _ RECTIFIED(min) VOUT VIN _ RECTIFIED(min) = 2 85V = 120V DUTY(max) = 390V - 120V = 0.692 390V Boost Diode The diode losses are estimated based upon the forward voltage drop, VF, at 125C and the reverse recovery charge, QRR, of the diode. Using a silicone carbide diode, although more expensive, will essentially eliminate the reverse recovery losses: PDIODE = VF _125C I OUT (max) + 0.5 f SW ( typ )VOUT QRR VF _125C = 1.5V QRR = 0nC PDIODE = 1.5V 0.897 A + 0.5 65kHz 390V 0nC = 1.35W 28 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 Switching Element The conduction losses of the switch are estimated using the RDS(on) of the FET at 125C , found in the FET data sheet, and the calculated drain to source RMS current, IDS_RMS: 2 PCOND = I DS _ RMS RDSon( 125C ) RDSon( 125C ) = 0.35W I DS _ RMS = I DS _ RMS = POUT (max) VIN _ RECTIFIED(min) 350W 120V 2- 2- 16VIN _ RECTIFIED(min) 3p VOUT 16 120V = 3.54 A 3p 390V PCOND = 3.54 A2 0.35W = 4.38W The switching losses are estimated using the rise time of the gate, tr, and the output capacitance losses. For the selected device: tr = 4.5ns COSS = 780 pF 2 PSW = f SW ( typ ) ( trVOUT I IN _ PEAK (max) + 0.5COSSVOUT ) PSW = 65kHz( 4.5ns 390V 6.39 A + 0.5 780 pF 390V 2 ) = 4.59W Total FET losses: PCOND + PSW = 4.38W + 4.59W = 8.97W Submit Documentation Feedback 29 UCC28019 www.ti.com SLUS755 - APRIL 2007 Sense Resistor To accommodate the gain of the internal non-linear power limit, RSENSE, is sized such that it will trigger the soft over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, VSOC, of ISENSE. RSENSE = RSENSE = VSOC I L _ PEAK (max) 1.25 0.66V = 0.075W 7.03 A 1.25 Using a parallel combination of available standard value resistors, the sense resistor is chosen. RSENSE = 0.067W The power dissipated across the sense resistor, PRsense, must be calculated: 2 PRsense = I IN _ RMS (max) RSENSE PRsense = 4.52 A2 0.067W = 1.36W The peak current limit, PCL, protection feature will be triggered when current through the sense resistor results in the voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL threshold is used: I PCL = VPCL RSENSE I PCL = 1.15V = 17.25 A 0.067W To protect the device from inrush current, a standard 220-m resistor, RISENSE, is placed in series with the ISENSE pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin. 30 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 Output Capacitor The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle, tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is: COUT (min) COUT (min) 2 OUT V 2 POUT t HOLDUP 2 - VOUT _ HOLDUP(min) 2 350W 21.28ms 240 m F 390V 2 - 300V 2 It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 F. Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor are calculated: VOUT _ RIPPLE( pp ) < 0.05VOUT VOUT _ RIPPLE( pp ) < 0.05 390V < 19.5VPP VOUT _ RIPPLE( pp ) = VOUT _ RIPPLE( pp ) = I OUT p ( 2 f LINE(min) )COUT 0 .9 A = 11.26V p ( 2 47 Hz ) 270 m F The required ripple current rating at twice the line frequency is equal to: I Cout _ 2 fline = I Cout _ 2 fline = I OUT (max) 2 0.9 A = 0.635 A 2 There will also be a high frequency ripple current through the output capacitor: I Cout _ HF = I OUT (max) I Cout _ HF = 0.9 A 16VOUT 3p VIN _ RECTIFIED(min) - 1 .5 16 390V - 1 . 5 = 1 .8 A 3p 120V The total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly: I Cout _ RMS ( total ) 2 2 = I Cout _ 2 fline + I Cout _ HF I Cout _ RMS ( total ) = 0.635 A2 + 1.8 A2 = 1.9 A Submit Documentation Feedback 31 UCC28019 www.ti.com SLUS755 - APRIL 2007 Output Voltage Set Point For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 M for the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum allowable voltage across each. Using the internal 5-V reference, VREF, select the bottom divider resistor, RFB2, to meet the output voltage design goals. RFB 2 = VREF RFB1 VOUT - VREF RFB 2 = 5V 1M W = 13.04k W 390V - 5V Using 13 k for RFB2 results in a nominal output voltage set point of 391 V. The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point: ae R + RFB 2 o VOUT ( OVP ) = VSENSEOVP c FB1 / RFB 2 e o ae 1M W + 13k W o VOUT ( OVP ) = 5.25V c / = 410.7V 13k W e o The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal set-point: ae R + RFB 2 o VOUT ( UVD ) = VSENSEUVD c FB1 / RFB 2 e o ae 1M W + 13k W o VOUT ( UVD ) = 4 .75V c / = 371 .6V 13k W e o A small capacitor on VSENSE must be added to filter out noise that would trigger the enhanced dynamic response in a no-load high-line configuration. Limit the value of the filter capacitor such that the RC time constant is less than 0.1ms so as not to significantly reduce the control response time to output voltage deviations. 32 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 Loop Compensation The selection of compensation components, for both the current loop and the voltage loop, is made easier by using the UCC28019 Design Calculator spreadsheet that can be found in the Tools section of the UCC28019 product folder on the Texas Instruments website. The current loop is compensated first by determining the product of the internal loop variables, M1M2, using the internal controller constants K1 and KFQ: M 1M 2 = K FQ = K FQ = 2 I OUT (max)VOUT RSENSE K1 h 2VIN2 _ RMS K FQ 1 f SW ( typ ) 1 = 15.385m s 65kHz K1 = 7 M 1M 2 = 0.9 A 390V 2 0.067W 7 V = 0.372 2 2 0.92 115V 15.385m s ms The VCOMP operating point is found on Figure 29. The Design Calculator spreadsheet enables the user to iteratively select the appropriate VCOMP value. M1M2 vs VCOMP 2.0 1.8 1.6 1.4 M1M2 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 VCOMP - V Figure 29. M1M2 vs. VCOMP For the given M1M2 of 0.372 V/s, the VCOMP, approximately equal to 4, as shown in Figure 29. Submit Documentation Feedback 33 UCC28019 www.ti.com SLUS755 - APRIL 2007 The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp slope, are calculated using the following conditions: The M1 current loop gain factor: if : 0 < VCOMP < 2 then : M 1 = 0.064 if : 2 VCOMP < 3 then : M 1 = 0.139 VCOMP - 0.214 if : 3 VCOMP < 5.5 then : M 1 = 0.279 VCOMP - 0.632 if : 5.5 VCOMP < 7 then : M 1 = 0.903 VCOMP = 4 M 1 = 0.279 4 - 0.632 = 0.484 The M2 PWM ramp slope: if : 0 < VCOMP < 1.5 V then : M 2 = 0 ms if : 1.5 VCOMP < 5.6 then : M 2 = 0.1223 (VCOMP - 1.5 )2 V ms if : 5.6 VCOMP < 7 then : M 2 = 2.056 V ms VCOMP = 4 M 2 = 0.1223 ( 4 - 1.5 )2 34 V V = 0.764 ms ms Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 Verify that the product of the individual gain factors is approximately equal to the M1M2 factor determined above, if not, reselect VCOMP and recalculate M1M2. M 1 M 2 = 0.484 0.764 0.37 V V = 0.37 ms ms V V @ M 1M 2 = 0.372 ms ms The non-linear gain variable, M3, can now be calculated: if : 0 < VCOMP < 3 then : M 3 = 0.0510 VCOMP 2 - 0.1543 VCOMP - 0.1167 if : 3 VCOMP < 7 then : M 3 = 0.1026 VCOMP 2 - 0.3596 VCOMP + 0.3085 VCOMP = 4 M 3 = 0.1026 42 - 0.3596 4 + 0.3085 = 0.512 The frequency of the current averaging pole, fIAVG, is chosen to be at 9.5 kHz. The required capacitor on ICOMP, CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier: CICOMP = gmiM 1 K1 2p f IAVG CICOMP = 0.95mS 0.484 = 1100 pF 7 2 p 9.5kHz Submit Documentation Feedback 35 UCC28019 www.ti.com SLUS755 - APRIL 2007 The transfer function of the current loop can be plotted: GCL ( f ) = K1 RSENSEVOUT K FQ M 1M 2 LBST 1 s( f )2 K1CICOMP s( f ) + gmiM 1 GCLdB ( f ) = 20 log ( GCL ( f ) ) CURRENT AVERAGING CIRCUIT 100 -80 80 60 -100 Phase 40 -120 0 qGCL(f) GCLdB(f) 20 Gain -20 -140 -40 -60 -160 -80 -100 -180 10 100 3 1*10 4 1*10 5 1*10 6 1*10 f - Hz Figure 30. Bode Plot of the Current Averaging Circuit. 36 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 The open loop of the voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and the gain from the pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator to power stage pole, fPWM_PS. The plotted result is shown in Figure 31. GFB = RFB 2 RFB1 + RFB 2 GFB = 13k W = 0.013 1M W + 13k W 1 f PWM _ PS = 2p f PWM _ PS = 3 K1 RSENSEVOUT COUT 2 K FQ M 1M 2VIN ( typ ) 1 = 1.589 Hz 7 0.067W 390V 3 270 m F 2p V 15.385m s 0.484 0.764 115V 2 ms M 3VOUT M 1M 2 1m s GPWM _ PS ( f ) = s( f ) 1+ 2p f PWM _ PS GVL ( f ) = GFB GPWM _ PS ( f ) GVLdB ( f ) = 20 log ( GVL ( f ) ) Submit Documentation Feedback 37 UCC28019 www.ti.com SLUS755 - APRIL 2007 OPEN LOOP VOLTAGE TRANSFER FUNCTION 0 20 -20 0 -40 qGVL(f) GVLdB(f) Gain Phase -20 -60 -40 -80 -60 -100 0.01 0.1 1 10 100 1*103 1*104 f - Hz Figure 31. Bode Plot of the Open Loop Voltage Transfer Function 38 Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20 Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly. f ZERO = 1 2p RVCOMP CVCOMP 1 RVCOMP CVCOMP CVCOMP _ P f POLE = 2p CVCOMP + CVCOMP _ P e e e 1 + s( f )RVCOMP CVCOMP GEA ( f ) = gmv e e ae RVCOMP CVCOMP CVCOMP _ P e 1 C C s( f ) s( f ) + + e c ( ) VCOMP VCOMP _ P e c CVCOMP + CVCOMP _ P e ee e u u u u ou u // u u o uu u fV = 10 Hz From Figure 31, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10 Hz is approximately 0.709 dB. Estimating that the parallel capacitor, CVCOMP_P, is much smaller than the series capacitor, CVCOMP, the unity gain will be at fV, and the zero will be at fPWM_PS, the series compensation capacitor is determined: gmv CVCOMP = 10 fV f PWM _ PS GVLdB ( f ) 20 2p fV 10 Hz 1.589 Hz = 3.88 m F = 0.709 dB 20 2 p 10 Hz 10 42 m S CVCOMP A 3.3-F capacitor is used for CVCOMP. RVCOMP = 1 2p f ZERO CVCOMP RVCOMP = 1 = 30.36k W 2 p 1.589 Hz 3.3m F A 33-k resistor is used for RVCOMP. CVCOMP _ P = CVCOMP 2p f POLE RVCOMP CVCOMP - 1 CVCOMP _ P = 3.3m F = 0.258m F 2 p 20 Hz 33k W 3.3m F - 1 A 0.22-F capacitor is used for CVCOMP_P. Submit Documentation Feedback 39 UCC28019 www.ti.com SLUS755 - APRIL 2007 The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 32. GVL _ total ( f ) = GFB ( f )GPWM _ PS ( f )GEA ( f ) GVL _ totaldB ( f ) = 20 log GVL _ total ( f ) ( ) 100 100 50 80 60 0 Gain 40 -50 Phase -100 20 -150 0 0.01 0.1 1 10 100 1*103 1*104 f - Hz Figure 32. Closed Loop Voltage Bode Plot 40 Submit Documentation Feedback qGVL_total(f) GVL_totaldB(f) CLOSED LOOP VOLTAGE TRANSFER FUNCTION UCC28019 www.ti.com SLUS755 - APRIL 2007 Brown Out Protection Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low bias current into VINS means the value of RVINS1 could be hundreds of megaohms. For practical purposes, a value less than 10 M is usually chosen. Assuming approximately 150 times the input bias current through the resistor dividers will result in an RVINS1 that is less than 10 M , so as to not contribute excessive noise, and still maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the user programmable minimum voltage, VAC(off), and turn on when the input rises above VAC(on). IVINS = 150 IVINS _ 0V IVINS = 150 0.1m A = 150 m A VAC( on ) = 75V V AC ( off ) = 65V RVINS 1 = RVINS 1 = 2 VAC( on ) - VF _ BRIDGE - VINS ENABLE _ th(max) IVINS 2 75V - 0.95V - 1.6V = 6.9 M W 150 m A A 6.5-M resistance is chosen. RVINS 2 = RVINS 2 = VINS ENABLE _ th(max)R VINS 1 2 VAC( on ) - VINS ENABLE _ th(max) - VF _ BRIDGE 1.6V 6.5M W = 100k W 2 75V - 1.6V - 0.95V Submit Documentation Feedback 41 UCC28019 www.ti.com SLUS755 - APRIL 2007 The capacitor on VINS, CVINS, is selected so that it's discharge time is greater than the output capacitor hold up time. COUT was chosen to meet one-cycle hold-up time so CVINS will be chosen to meet 2.5 half-line cycles. tCVINS _ dischrg = tCVINS _ dischrg = CVINS = C 42 VINS = N HALF _ CYCLES 2 f LINE (min) 2 .5 = 25 .6 ms 2 47 Hz -tCVINS _ dischrg e u e u VINS BROWNOUT _ th(min) e u RVINS 2 ln e ae ou RVINS 2 e 0.9 VIN _ RMS (min) c /u ee e RVINS 1 + RVINS 2 o uu -25.6ms e u e u 0.76V u 100k W ln e 100k W ou e 0.9 85V ae c / e 6.5M W + 100k W o uu ee = 0.63m F Submit Documentation Feedback UCC28019 www.ti.com SLUS755 - APRIL 2007 REFERENCES These references, additional design tools, and links to additional references, including design software and models may be found on the web at http://www.power.ti.com under Technical Documents. Evaluation Module, 350-W Universal Input, 390-VDC Output PFC Converter, Texas Instruments Literature No. SLUA272 Design Spreadsheet, UCC28019 Design Calculator, Texas Instruments RELATED PRODUCTS The following parts have characteristics similar to the UCC28019 and may be of interest. Related Products DEVICE DESCRIPTION UCC3817/18 Full-Feature PFC Controller UC2853A 8-Pin CCM PFC Controller Submit Documentation Feedback 43 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device UCC28019DR 17-May-2007 Package Pins D 8 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) FMX 330 0 6.4 5.2 2.1 8 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) UCC28019DR D 8 FMX 342.9 336.6 20.6 Pack Materials-Page 2 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P MECHANICAL DATA MPDI001A - JANUARY 1995 - REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. 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