GS6042 6G UHD-SDI/3G/HD/SD Adaptive Cable Equalizer Gennum Products Key Features Description * Supports data rates from 125Mb/s to 6.25Gb/s * SMPTE ST 2081 (proposed), SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259 compliant The GS6042 is a high-speed BiCMOS device designed to optimally equalize and restore signals received over 75 coaxial cable. * Automatic cable equalization * Typical equalized length of Belden 1694A cable: 80m at 5.94Gb/s The GS6042 features DC restoration to compensate for the DC content of SMPTE pathological signals. 210m at 2.97Gb/s 300m at 1.485Gb/s The Carrier Detect output pin (CD) indicates whether an input signal has been detected. It can be connected directly to the SLEEP pin to enable automatic sleep on loss of input. 500m at 270Mb/s * Supports DVB-ASI at 270Mb/s * Supports MADI at 125Mb/s * Manual bypass control * Programmable carrier detect with squelch threshold adjustment * Automatic power-down on loss of signal * Differential output supports DC-coupling from +1.2V to +3.3V CML logic * Optional 6dB flat band gain on input * Selectable output de-emphasis: 2dB, 6dB, and 8dB * Standard EIA/JEDEC logic for control/status signals * Single +3.3V power supply operation * 180mW power consumption (35mW in sleep) * Operating temperature range: -40C to +85C * Small footprint QFN package (4mm x 4mm) Footprint compatible with the GS2974A, GS2974B, GS2984, GS2994, and GS3440 * Pb-free and RoHS compliant A CD threshold is set via the SQ_ADJ pin, allowing the GS6042 to distinguish between small amplitude SDI signals and noise at the input of the device. The equalizing and DC restore stages are disengaged and no equalization occurs when the BYPASS pin is HIGH. This is useful for signals launched at the signal source with low data rates and/or slow rise/fall times. The GS6042 features a gain selection pin (GAIN_SEL) which can be used to compensate for 6dB flat attenuation prior to the input of the device. The differential output can be DC-coupled to Semtech's reclockers and cable drivers, as well as industry-standard CML logic by changing the voltage applied to the VCC_O pin. In general, DC-coupling to any termination voltage between +1.2V and +3.3V is supported. The GS6042 also features programmable output de-emphasis with three user-selectable operating levels to support long PCB traces at the output of the device. Power consumption of the GS6042 is typically 180mW when its output is DC-coupled at +1.2V. Applications * SMPTE ST 2081 (proposed), SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259 coaxial cable serial digital interfaces * Serialized 8b/10b encoded video streams up to 6.25Gb/s GS6042 Final Data Sheet PDS-060055 The device supports data rates up to 6.25Gb/s while being optimized for the proposed SMPTE ST 2081, as well as SMPTE ST 424, SMPTE ST 292, and SMPTE ST 259. The GS6042 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant. www.semtech.com Rev. 3 May 2014 1 of 21 Proprietary and Confidential SQ_ADJ BYPASS SLEEP CD Squelch Adjust Carrier Detect Mute VCC_A SDI VCC_O DC Restore Equalizer SDI DDO DDO Output GAIN_SEL VEE_O OP_CTL AGC VEE_A AGC AGC GS6042 Functional Block Diagram Revision History Version ECO PCN Date 3 019547 -- May 2014 2 017789 -- February 2014 1 016407 -- November 2013 0 012658 -- June 2013 GS6042 Final Data Sheet PDS-060055 Changes and/or Modifications Corrected the values for the de-emphasis levels Converted to Final Data Sheet. Modified Section 4.3. Included reference to 6G SMPTE standard. Converted to Final Data Sheet. Included information on 6.25G support. Updated Jitter characteristics. Updates throughout. New document www.semtech.com Rev. 3 May 2014 2 of 21 Proprietary and Confidential Contents Key Features...........................................................................................................................................................1 Applications ...........................................................................................................................................................1 Description .............................................................................................................................................................1 Revision History ....................................................................................................................................................2 1. Pin Out.................................................................................................................................................................4 1.1 GS6042 Pin Assignment ...................................................................................................................4 1.2 GS6042 Pin Descriptions ..................................................................................................................4 2. Electrical Characteristics................................................................................................................................6 2.1 Absolute Maximum Ratings ...........................................................................................................6 2.2 DC Electrical Characteristics ...........................................................................................................6 2.3 AC Electrical Characteristics ............................................................................................................8 3. Input/Output Circuits.................................................................................................................................. 10 4. Detailed Description.................................................................................................................................... 11 4.1 Serial Digital Inputs ......................................................................................................................... 11 4.2 Automatic (Adaptive) Cable Equalization .............................................................................. 11 4.3 Differential Digital Data Output ................................................................................................. 11 4.4 Programmable Squelch Adjust (SQ_ADJ) ............................................................................... 12 4.5 Carrier Detect, Sleep, and Auto-Sleep ...................................................................................... 13 4.6 GAIN_SEL ............................................................................................................................................ 13 4.7 Adjustable Output Swing, De-emphasis, and Mute ........................................................... 14 5. Application Information............................................................................................................................. 16 5.1 High-Gain Adaptive Cable Equalizers ...................................................................................... 16 5.2 PCB Layout ......................................................................................................................................... 16 5.3 Typical Application Circuit ........................................................................................................... 17 6. Package & Ordering Information ............................................................................................................ 18 6.1 Package Dimensions ...................................................................................................................... 18 6.2 Packaging Data ................................................................................................................................ 18 6.3 Recommended PCB Footprint .................................................................................................... 19 6.4 Marking Diagram ............................................................................................................................. 19 6.5 Solder Reflow Profiles .................................................................................................................... 20 6.6 Ordering Information ..................................................................................................................... 20 GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 3 of 21 Proprietary and Confidential 1. Pin Out 2 SDI 3 CD SLEEP VCC_O 14 13 GS6042 16-pin QFN (top view) 12 VEE_O 11 DDO 10 DDO OP_CTL 9 4 7 8 SQ_ADJ 6 BYPASS 5 AGC Ground Pad (bottom of package) 15 1 SDI GAIN_SEL 16 AGC VEE_A VCC_A 1.1 GS6042 Pin Assignment Figure 1-1: GS6042 Pin Out 1.2 GS6042 Pin Descriptions Table 1-1: GS6042 Pin Descriptions Pin Number Name Type Description 1 VEE_A Power Most negative power supply connection for the input buffer, core, and control circuits. Connect to ground. 2, 3 SDI, SDI Input Serial digital differential input. Flat Band Gain Control. 4 GAIN_SEL Input Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V input that is tolerant to +3.3V levels. When HIGH, the device compensates for an additional 6dB of loss across the entire operating band. This pin has an internal pull-down resistor. 5, 6 AGC, AGC -- External AGC capacitor connection. EQ Bypass Control. 7 BYPASS Input Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V input that is tolerant to +3.3V levels. Forces the equalizer and DC-restore stages into Bypass mode when HIGH. No equalization occurs in this mode. This pin has an internal pull-down resistor. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 4 of 21 Proprietary and Confidential Table 1-1: GS6042 Pin Descriptions (Continued) Pin Number Name Type Description Squelch Threshold Adjust. 8 SQ_ADJ Input Adjusts the input signal amplitude threshold of the carrier detect function. The serial data output of the device can be muted when the serial data input signal amplitude is too low by connecting the CD and OP_CTL pins using a suitable resistor network (see Figure 4-4 and Figure 4-5). This pin has an internal pull-down resistor. Note: The SQ_ADJ function is only available when the device is not configured for auto-sleep mode. Reference Section 4.5 for more detail. Output Swing, De-emphasis and Mute Control. When this pin is connected to GND, the output swing is 850mVppd with no de-emphasis applied to the output signal. 9 OP_CTL Input With this pin connected to +2.5V, the output is muted. Intermediate voltages and functions are shown in Table 4-5. These voltages can be achieved as shown in Figure 4-4 and Figure 4-5. This pin has an internal pull-down resistor. 10, 11 DDO, DDO Output 12 VEE_O Power 13 VCC_O Power Serial digital differential output. Most negative power supply connection for the output buffer. Connect to ground. Most positive power supply connection for the output buffer. Connect to 1.2V - 3.3V DC. SLEEP Control. Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V input that is tolerant to +3.3V levels. When HIGH the part is powered-down except for the Carrier Detect function. 14 SLEEP Input This pin can be connected directly to the CD pin to automatically put the device to sleep (low-power operation) on loss of carrier. This pin has an internal pull-down resistor. Note: When SLEEP is connected to CD for automatic power reduction on loss of carrier, the SQ_ADJ pin will not modify the CD threshold. The CD threshold will revert to the default value used when SQ_ADJ is pulled LOW. Carrier Detect Status Output. 15 CD Output Please refer to the DC Electrical Characteristics table for logic level threshold and compatibility. This pin is a +2.5V output. Indicates presence of an input signal. When the CD pin is LOW, a signal has been detected at the input. When this pin is HIGH, this indicates loss of input signal. 16 VCC_A Power Most positive power supply connection for the input buffer, core and control circuits. Connect to +3.3V DC. -- GS6042 Final Data Sheet PDS-060055 Center Pad Power Internally bonded to VEE_A. Connect to GND with at least 5 vias. www.semtech.com Rev. 3 May 2014 5 of 21 Proprietary and Confidential 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value Supply Voltage - Core/Output Driver -0.5V to +3.6V DC Input ESD Voltage (HBM) 5kV Storage Temperature Range (Ts) -50C to +125C Input Voltage Range (any input) -0.3 to (VCC_A +0.3)V Operating Temperature Range -40C to +85C Solder Reflow Temperature 260C Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation outside of the ranges shown in the AC and DC Electrical Characteristics is not guaranteed. 2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics VCC_A = +3.3V 5%, TA = -40C to +85C, unless otherwise shown. Parameter Symbol Supply Voltage - Core Supply Voltage - Output Driver GS6042 Final Data Sheet PDS-060055 VCC_A VCC_O Conditions Min Typ Max Units Notes -- 3.135 3.3 3.465 V -- -- 1.14 1.2 1.26 V 1 -- 2.375 2.5 2.625 V 1 -- 3.135 3.3 3.465 V 1 www.semtech.com Rev. 3 May 2014 6 of 21 Proprietary and Confidential Table 2-2: DC Electrical Characteristics (Continued) VCC_A = +3.3V 5%, TA = -40C to +85C, unless otherwise shown. Parameter Symbol Power Consumption Supply Current - Core Supply Current - Output Driver Input Common Mode Voltage Output Common Mode Voltage CD Output Voltage Logic Levels Input Voltage Logic Levels: GAIN_SEL, BYPASS, SLEEP PD Is IOut VCMIN Conditions Min Typ Max Units Notes VCC_O = 1.2V VDDO = 425mVppd -- 180 -- mW 2 VCC_O = 1.2V VDDO = 850mVppd -- 195 -- mW 2 VCC_O = 2.5V VDDO = 425mVppd -- 196 -- mW 2 VCC_O = 2.5V VDDO = 850mVppd -- 221 -- mW 2 VCC_O = 3.3V VDDO = 425mVppd -- 202 -- mW 2 VCC_O = 3.3V VDDO = 850mVppd -- 240 -- mW 2 Sleep Mode SLEEP = HIGH -- 35 -- mW -- -- -- 55 -- mA 2, 3 VDDO = 850mVppd -- 20 -- mA 2 VDDO = 425mVppd -- 10 -- mA 2 -- -- 1.7 -- V -- VCMOUT Refer to Section 4.3 VCD(OH) Signal not present 2.0 -- -- V -- VCD(OL) Signal present -- -- 0.4 V -- VIH Minimum to assert 1.7 -- -- V 4 VIL Maximum to de-assert -- -- 0.7 V 4 Notes: 1. 2. 3. 4. VCC_O operates from +1.2V through +3.3V (+/-5%). De-emphasis off. An additional 3mA when de-emphasis is enabled. GAIN_SEL, BYPASS, SLEEP pins are +2.5V, but +3.3V tolerant. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 7 of 21 Proprietary and Confidential 2.3 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics VCC_A = +3.3V 5%, TA = -40C to +85C, unless otherwise shown Parameter Symbol Serial input Data Rate Input Voltage Swing Output Voltage Swing Output Jitter at Various Cable Lengths and Data Rates GS6042 Final Data Sheet PDS-060055 DRDDO VSDI VDDO Conditions Min Typ Max Units Notes -- 125 -- 6250 Mb/s 1 Differential, 270Mb/s and 1.485Gb/s 720 800 950 mVppd 2 Differential, 2.97Gb/s and 5.94Gb/s 720 800 880 mVppd 2 100 differential load, OP_CTL set for high swing 700 850 1000 mVppd -- 100 differential load, OP_CTL set for low swing 350 425 500 mVppd -- 6.25Gb/s Belden 1694A: 0-50m -- 0.35 -- UI 4, 5 5.94Gb/s Belden 1694A: 0-80m -- 0.35 0.5 UI 4, 5 2.97Gb/s Belden 1694A: 0-100m -- -- 0.2 UI 3, 4, 5 2.97Gb/s Belden 1694A: 100-150m -- -- 0.3 UI 3, 4, 5 2.97Gb/s Belden 1694A: 150-170m -- -- 0.4 UI 3, 4, 5 2.97Gb/s Belden 1694A: 170-200m -- -- 0.5 UI 3, 4, 5 2.97Gb/s Belden 1694A: 210m -- 0.5 -- UI 4, 5 1.485Gb/s Belden 1694A: 0-200m -- -- 0.2 UI 3, 4, 5 1.485Gb/s Belden 1694A: 200-260m -- -- 0.3 UI 3, 4, 5 1.485Gb/s Belden 1694A: 260-300m -- 0.3 -- UI 4, 5 270Mb/s Belden 1694A: 0-300m -- 0.1 0.15 UI 3, 4, 5 270Mb/s Belden 1694A: 300-500m -- -- 0.25 UI 3, 4, 5 www.semtech.com Rev. 3 May 2014 8 of 21 Proprietary and Confidential Table 2-3: AC Electrical Characteristics (Continued) VCC_A = +3.3V 5%, TA = -40C to +85C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes -- 75 -- ps -- -- 150 -- ps -- -- -- -- 30 ps -- Duty Cycle Distortion -- -- -- 30 ps -- Overshoot -- -- -- 10 % -- 5MHz - 1.485GHz 15 -- -- dB -- 1.485GHz - 2.97GHz 10 -- -- dB -- Input Resistance single-ended -- 1.9 -- k -- Input Capacitance single-ended -- 1.3 -- pF -- Output Resistance single-ended -- 50 -- -- 5.94Gb/s, 2.97Gb/s, and 1.485Gb/s Output Rise/Fall time tr, tf 20% - 80% 270Mb/s 20% - 80% Mismatch in Rise/Fall time tr,, tf Input Return Loss Notes: 1. Device performance is optimized for standard data rates (SD = 270Mb/s, HD = 1.485Gb/s, 3G = 2.970Gb/s, 6G = 5.94Gb/s). 2. 0m cable length. 3. All parts are production tested. In order to guarantee maximum jitter over the full range of specification (VCC_A = +3.3V 5%, TA = -40C to +85C, and 720-880mVpp launch swing from the SDI cable driver), the recommended applications circuit must be used. 4. Based on validation data using the recommended applications circuit, with VCC_A = +3.3V, TA = -40C to +85C and 800mVpp launch swing from the SDI cable driver. 5. GAIN_SEL = 0. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 9 of 21 Proprietary and Confidential 3. Input/Output Circuits VCC_A VCC_A VCC_A VCC_A 2k 2k SDI 2k + SDI - SQ_ADJ RC RC 82.4k 2.625k Figure 3-1: Input Circuit VCC_O VCC_O 50 Figure 3-2: SQ_ADJ Circuit VCC_O VCC_A VCC_A 50 DDO SLEEP, BYPASS, GAIN_SEL DDO 100k Figure 3-4: SLEEP, BYPASS, and GAIN_SEL Circuits Figure 3-3: Output Circuit VCC_A VCC_A Internal 2.5V VCC_A Internal Reference Internal Circuitry OP_CTL CD 100k Figure 3-5: CD Circuit GS6042 Final Data Sheet PDS-060055 Figure 3-6: OP_CTL www.semtech.com Rev. 3 May 2014 Internal Reference 10 of 21 Proprietary and Confidential 4. Detailed Description The GS6042 is a high-speed BiCMOS IC designed to automatically equalize high-bandwidth serial digital video signals. The GS6042 can equalize data rates up to 6.25Gb/s including 6G UHD-SDI, 3G SDI, HD SDI, and SD SDI serial digital signals. The GS6042 is optimized to equalize up to 80m of Belden 1694A cable at 5.94Gb/s (UHD-SDI), 210m at 2.97Gb/s (3G-SDI), 300m at 1.485Gb/s (HD-SDI), and 500m at 270Mb/s (SD-SDI). The GS6042 can be powered from a single +3.3V DC power supply, and is footprint-compatible with Semtech's GS2974A, GS2974B, GS2984, GS2994, and GS3440 equalizers. 4.1 Serial Digital Inputs The received serial data signal is connected to the input pins (SDI/SDI) in either a differential or single-ended configuration. AC-coupling of the inputs is recommended because the SDI and SDI inputs are internally biased to approximately 1.71V. See Figure 5-1 for the recommended input applications circuit when using a single-ended 75 coax cable. 4.2 Automatic (Adaptive) Cable Equalization The input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse of the Belden 1694A cable loss characteristic for any given attached cable length within the supported ranges. The equalized signal is DC-restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC-coupling. 4.3 Differential Digital Data Output The digital data output signals (DDO/DDO) have a nominal output voltage swing of either 850mVppd or 425mVppd (VDDO), as set by the OP_CTL pin. Table 4-1 shows the typical output common mode voltage levels (VCMOUT) related to the two output swing options and the type of output transmission termination as shown in Figure 4-1 and Figure 4-2. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 11 of 21 Proprietary and Confidential Table 4-1: Typical Common Mode Output Voltage Levels (VCMOUT) Termination Type 1 (See Figure 4-1) (See 1) Supply Voltage (VCC_O) Termination Type 2 (See Figure 4-2) 425mVppd Swing 850mVppd Swing 425mVppd Swing 850mVppd Swing 3.3V 3.19V 3.09V 3.09V 2.88V 2.5V 2.39V 2.29V 2.29V 2.08V 1.8V 1.69V 1.59V 1.59V 1.38V 1.2V 1.09V 0.99V 0.99V 0.78V Note: 1. The values shown for termination type 1 only apply when V TERM = VCC_O GS6042 GS6042 VCC_O VCC_O VTERM VTERM 50 50 50 50 50 50 DDO 50 DDO 50 DDO 50 DDO 50 Figure 4-1: 50 Termination to VTERM 100 Figure 4-2: 100 Parallel Output Termination 4.4 Programmable Squelch Adjust (SQ_ADJ) The GS6042 features a programmable Squelch Adjust (SQ_ADJ) threshold. This feature can be useful in applications where there are multiple input channels using the GS6042 and the maximum gain of each device must be limited to avoid crosstalk. The SQ_ADJ pin acts to change the threshold of the Carrier Detect (CD) pin. When the input signal level drops below the threshold set by SQ_ADJ, the CD pin will be driven HIGH, indicating that there is not a valid input signal. This feature has been designed for use in applications such as routers, where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal-to-noise ratio on the circuit board could be significantly less than the default signal detection level set by the on-chip reference. In applications where programmable squelch adjust is not required, the SQ_ADJ pin can be left unconnected. Note: When using SQ_ADJ to limit the maximum gain of the GS6042, CD should not be connected to SLEEP. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 12 of 21 Proprietary and Confidential 4.5 Carrier Detect, Sleep, and Auto-Sleep The Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of the GS6042. When CD is LOW, the device has detected a valid input on SDI/SDI. When CD is HIGH, the device considers the input invalid. Note 1: CD will only detect loss of signal for data rates greater than 19Mb/s. Note 2: If SQ_ADJ is being used to limit the maximum gain of the device, and the maximum cable length is exceeded, the CD pin will be set to HIGH even if an input is present. Table 4-2: CD Output CD Input Status 0 Valid input on SDI/SDI pins 1 Input is not valid The GS6042 also includes a SLEEP input pin, which can be used to put the device into a low-power sleep mode. In this mode, the outputs are high impedance and will be pulled high by the on-chip termination. Set the SLEEP pin HIGH to place the chip in this low-power state. In this mode, the Carrier Detect output will still function to facilitate the detection of a valid serial input data signal. Auto-Sleep is enabled by connecting CD to SLEEP. When connected, the GS6042 will automatically go into low-power sleep mode when there is a loss of input signal. Note 3: If the CD pin is connected to the SLEEP pin, SQ_ADJ must be either left open, or connected to ground. Table 4-3: SLEEP Input SLEEP Function 0 Normal operation 1 Low-power sleep mode; CD output remains valid 4.6 GAIN_SEL The GS6042 provides the option of compensating for 6dB of flat attenuation prior to the equalizer. Table 4-4: GAIN_SEL Input Table GAIN_SEL Function 0 No flat band gain is applied 1 6dB of flat band gain applied to input signal GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 13 of 21 Proprietary and Confidential 4.7 Adjustable Output Swing, De-emphasis, and Mute The OP_CTL input pin determines the output swing and de-emphasis settings for DDO and DDO. The OP_CTL pin is an analog input, allowing different combinations of output swing, de-emphasis, and mute. The possible values are listed in Table 4-5. Table 4-5: OP_CTL Functions and Levels Level Swing De-emphasis Mute Voltage (V) 0 850mVppd Off N 0.000 - 0.083 1 850mVppd 2dB N 0.234 - 0.394 2 850mVppd 6dB N 0.545 - 0.704 3 850mVppd 8dB N 0.856 - 1.015 4 425mVppd Off N 1.166 - 1.333 5 425mVppd 2dB N 1.484 - 1.644 6 425mVppd 6dB N 1.795 - 1.954 7 425mVppd 8dB N 2.106 - 2.265 8 425mVppd N/A Y 2.416 - 2.500 When muted, the output swing is set to 425mVppd and the outputs are latched. Automatic muting of the output can be enabled by connecting the CD pin to the OP_CTL pin. OP_CTL CD If the connection is made directly, as shown in Figure 4-3, the output would be in its default mode (850mVppd swing with no de-emphasis) when there is signal present. Figure 4-3: Direct Loopback To enable automatic muting while the output is configured for other settings, a resistor network can be used between CD and VCC_A. The intermediate voltages of this resistor ladder can set the output to any one of the nine different settings as shown in the examples given in Figure 4-4 and Figure 4-5. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 14 of 21 Proprietary and Confidential 0 1 2 3 4 5 6 7 8 VCC_A Levels Taps 1 2 3 CD 1K 1K 1K 1K OP_CTL CD 1K 1K 1K 1K 1K 1K 1K 1K 2.6K 0 Figure 4-4: Resistor Divider Loopback Example #1 (Function Level 3 from Table 4-5) 4 5 6 7 8 VCC_A 1K 1K 1K 1K 2.6K OP_CTL Levels Taps Figure 4-5: Resistor Divider Loopback Example #2 (Function Level 4 from Table 4-5) In Figure 4-4, the automatic muting of the output is established by connecting node 3 to the OP_CTL pin. In this scenario, the output would be 850mVppd with 8dB of de-emphasis when there is a signal present. In Figure 4-5, the OP_CTL pin is connected to node 4. In this scenario, the output would be 425mVppd with no de-emphasis when there is a signal present. In both cases, the output would be muted when no carrier is detected. Note: When the device is in SLEEP mode, automatic muting and SQ_ADJ do not function. Asserting the SLEEP pin manually overrides all other functionality. GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 15 of 21 Proprietary and Confidential 5. Application Information 5.1 High-Gain Adaptive Cable Equalizers The GS6042 is a multi-rate Adaptive Cable Equalizer. In order to extend the cable lengths that the device can support, it is necessary to have high-gain in the equalizer. In particular, an SDI video cable equalizer must provide wide band gain over a range of frequencies in order to accommodate the range of data rates and signal patterns that are present in a SMPTE-compliant serial video stream. Small levels of signal or noise present at the input pins of the equalizer may cause chatter at the output. In order to prevent this from happening, particular attention must be paid to board layout. 5.2 PCB Layout Special attention must be paid to component layout when designing serial digital interfaces for HDTV and other high-speed video applications. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: * PCB trace width for high data rate signals should be closely matched to SMT component width to minimize reflections due to changes in trace impedance * High-speed traces should be curved to minimize impedance changes * Cutouts in the inner layers should be used under the GS6042 input and output components to minimize parasitic capacitance GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 16 of 21 Proprietary and Confidential 5.3 Typical Application Circuit VCC_A VCC_O 10nF 10nF 16 2 SDI DDO SDI DDO VCC_A VCC_O BYPASS 6.2nH* SDI 13 7 11 1F 75 4.7F 68.1 3 10 1F 4.7F 37.5 8 SQ_ADJ 9 4 GAIN_SEL 14 AGC VEE_O AGC 6 1 15 Center Pad 5 470nF CD SLEEP *Value dependent on layout **This is a placeholder to allow for flexibility in the termination circuit population. It can be populated with 0W by default. GS6042 OP_CTL VEE_A 0** 12 Figure 5-1: GS6042 Typical Application Circuit Recommended for Extended Cable Reach Applications VCC_O VCC_A 10nF 10nF 6.2nH 2 16 VCC_A BYPASS VCC_O 13 7 DDO SDI 11 4.7F 1F 75 75 10 3 DDO SDI 4.7F 1F 37.4 8 SQ_ADJ GS6042 9 OP_CTL 4 GAIN_SEL AGC 1 Center Pad AGC 6 VEE_O 5 470nF 15 CD SLEEP VEE_A 14 12 Figure 5-2: GS6042 Alternate Application Circuit Recommended for Drop in Replacement Applications GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 17 of 21 Proprietary and Confidential 6. Package & Ordering Information 6.1 Package Dimensions 4.00 A B 2.600.10 0.10 M C A B DATUM A 0.10 M C A B 4.00 2.600.10 0.30@45 PIN 1 AREA DETAIL A DATUM B 2X 0.15 C R0.30 (3x) 0.15 C 0.20 REF 0.10 C C 0.300.05 16X 0.10 0.05 16X M M C A B C DATUM A OR B +0.03 0.02 -0.02 0.65/2 0.900.10 0.08 C SEATING PLANE 0.65 2X 0.400.05 DETAIL A (SCALE 3:1) NOTES: 1. DIMENSIONING AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5-1994 ALL DIMENSIONS ARE IN MILLIMETERS IN DEGREES 2. DIMENSION OF LEAD WIDTH APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15mm AND 0.30mm FROM THE TERMINAL TIP (BOTH ROWS). IF THE TERMINAL HAS OPTIONAL RADIUS ON THE END OF THE TERMINAL, THE LEAD WIDTH DIMENSION SHOULD NOT BE MEASURED IN THAT RADIUS AREA 6.2 Packaging Data Parameter Value Package Type 4mm x 4mm 16-pin QFN Package Drawing Reference JEDEC M0220 Moisture Sensitivity Level 1 Junction to Case Thermal Resistance, j-c 31.0C/W Junction to Air Thermal Resistance, j-a (at zero airflow) 43.8C/W Psi, 11.0C/W Pb-free and RoHS compliant Yes GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 18 of 21 Proprietary and Confidential 6.3 Recommended PCB Footprint 0.30 0.65 0.55 3.70 2.60 Center Pad Note: All dimensions are in millimeters. 2.60 3.70 The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of 5 vias. Note: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 6.4 Marking Diagram Pin 1 ID GS6042 XXXXE3 YYWW GS6042 Final Data Sheet PDS-060055 XXXX - Last 4 digits (excluding decimal) of SAP Batch Assembly (FIN) as listed on Packing Slip. E3 - Pb-free & Green indicator YYWW - Date Code www.semtech.com Rev. 3 May 2014 19 of 21 Proprietary and Confidential 6.5 Solder Reflow Profiles The GS6042 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 6-1. Temperature 60-150 sec. 20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max 200C 150C 25C Time 60-180 sec. max 8 min. max Figure 6-1: Maximum Pb-free Solder Reflow Profile 6.6 Ordering Information Part Number Package Temperature Range GS6042-INE3 16-pin QFN -40C to +85C GS6042 Final Data Sheet PDS-060055 www.semtech.com Rev. 3 May 2014 20 of 21 Proprietary and Confidential DOCUMENT IDENTIFICATION CAUTION FINAL DATA SHEET ELECTROSTATIC SENSITIVE DEVICES The product is in production. Semtech reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION (c) Semtech 2013 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com GS6042 Final Data Sheet PDS-060055 Rev. 3 May 2014 21 of 21 21 Proprietary and Confidential