MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER Check for Samples: MSP430F2274-EP FEATURES 1 * * 2 * * * * * * Low Supply Voltage Range 1.8 V to 3.6 V Ultralow-Power Consumption - Active Mode: 270 A at 1 MHz, 2.2 V - Standby Mode: 0.7 A - Off Mode (RAM Retention): 0.1 A Ultrafast Wake-Up From Standby Mode in Less than 1 s 16-Bit RISC Architecture, 62.5 ns Instruction Cycle Time Basic Clock Module Configurations - Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to 1% - Internal Very Low Power LF Oscillator - 32-kHz Crystal (Available Only from -55C to 105C) - High-Frequency Crystal up to 16 MHz (Available Only from -55C to 125C) - Resonator - External Digital Clock Source - External Resistor 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Three Capture/Compare Registers Universal Serial Communication Interface - Enhanced UART Supporting Auto-Baud-Rate Detection (LIN) - IrDA Encoder and Decoder - Synchronous SPI - I2CTM * * * * * * * * * 10-Bit, 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, and Autoscan and Data Transfer Controller Two Configurable Operational Amplifiers Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Bootstrap Loader On-Chip Emulation Logic Family Members Include the MSP430F2274 With 32KB + 256B Flash Memory, 1KB RAM Available in 40-Pin QFN Package and 38-Pin Thin Shrink Small-Outline DA Package For Complete Module Descriptions, Refer to the MSP430x2xx Family User'sGuide SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS * * * * * * * (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (-55C/125C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Custom temperature ranges available DESCRIPTION The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430F2274M series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F2274M devices, and 32 I/O pins. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand-alone RF sensor front end is another area of application. Table 1. ORDERING INFORMATION (1) TA -55C to 125C (1) (2) PACKAGE (2) ORDERABLE PART NUMBER QFN (RHA) MSP430F2274MRHATEP DA (TSSOP) MSP430F2274MDATEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DEVICE PINOUTS DVSS 39 38 37 36 35 34 33 32 1 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK TEST/SBWTCK P1.7/TA2/TDO/TDI DVCC DVCC P2.5/Rosc RHA PACKAGE (TOP VIEW) 30 P1.1/TA 0 XOUT /P2.7 2 29 P1.0/TACLK /ADC 10 CLK XIN /P2.6 3 28 P2.4/TA 2/A4/VREF +/VeREF +/OA 1I0 DVSS 4 27 P2.3/TA 1/A3/VREF -/VeREF -/OA 1I1/OA 1O RST /NMI /SBWTDIO 5 26 P3.7/A7/OA 1I2 P2.0/ACLK /A0/OA 0I0 6 25 P3.6/A6/OA 0I2 P2.1/TAINCLK /SMCLK /A1/OA 0O 7 24 P3.5/UCA 0RXD /UCA 0SOMI P2.2/TA 0/A2/OA 0I1 8 23 P3.4/UCA 0TXD /UCA 0SIMO P3.0/UCB 0STE /UCA 0CLK/A5 9 22 P4.7/TBCLK 21 P4.6/TBOUTH /A15 /OA 1I3 P3.1/UCB 0SIMO /UCB 0SDA 10 M4F2274 MRHATEP TI YMS LLLLG4 2 P4.5/TB2/A14/OA0I3 P4.4/TB1/A13/OA1O P4.3/TB0/A12/OA0O P4.2/TB2 P4.1/TB1 P4.0/TB0 AVCC AVSS P3.3/UCB0CLK/UCA0STE P3.2/UCB0SOMI/UCB0SCL 12 13 14 15 16 17 18 19 TI = TI YM = YEAR/MONTH LLLL = LOT TRACE CODE S = ASSEMBLY SITE CODE G4 = RoHS with underscore O = PIN 1 indicator Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com DA PACKAGE (TOP VIEW) TEST/SBWTCK 1 38 P1.7/TA2/TDO/TDI DVCC 2 37 P1.6/TA1/TDI P2.5/Rosc 3 36 P1.5/TA0/TMS DVSS 4 35 P1.4/SMCLK/TCK XOUT/P2.7 5 34 P1.3/TA2 XIN/P2.6 6 33 P1.2/TA1 RST/NMI/SBWTDIO 7 32 P1.1/TA0 P2.0/ACLK/A0/OA0I0 8 31 P1.0/TACLK/ADC 10CLK P2.1/TAINCLK/SMCLK/A1/OA00 9 30 P2.4/TA2/A4/VREF+/VeREF+/OA1I0 P2.2/TA0/A2/OA0I1 10 29 P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA10 P3.0/UCB 0STE/UCA 0CLK/A5 11 28 P3.7/A7/OA1I2 P3.1/UCB 0SIMO/UCB 0SDA 12 27 P3.6/A6/OA0I2 P3.2/UCB 0SOMI/UCB 0SCL 13 26 P3.5/UCA0RXD/UCA0SOMI P3.3/UCB 0CLK/UCA 0STE 14 25 P3.4/UCA0TXD/UCA0SIMO AVSS 15 24 P4.7/TBCLK AVCC 16 23 P4.6/TBOUTH/A15/OA1I3 P4.0/TB0 17 22 P4.5/TB2/A14/OA1I3 P4.1/TB1 18 21 P4.4/TB1/A13/OA1O P4.2/TB2 19 20 P4.3/TB0/A12/OA0O FUNCTIONAL BLOCK DIAGRAM VCC P1.x/P2.x VSS 2x8 XIN P3.x/P4.x 2x8 XOUT Basic Clock System+ ACLK Flash ADC10 10-Bit Ports P1/P2 Ports P3/P4 OA0, OA1 32kB 16kB 8kB SMCLK MCLK 16MHz CPU incl. 16 Registers RAM 1kB 512B 512B 12 Channels, Autoscan, DTC 2 Op Amps 2x8 I/O pull-up/down resistors MAB MDB Emulation (2BP) JTAG Interface 2x8 I/O Interrupt capability, pull-up/down resistors Timer_B3 Brownout Protection Watchdog WDT+ 15/16-Bit Spy-Bi Wire Timer_A3 3 CC Registers 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C RST/NMI NOTE: See port schematics section for detailed I/O information. Copyright (c) 2008-2011, Texas Instruments Incorporated 3 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com TERMINAL FUNCTIONS (1) TERMINAL DA NO. RHA NO. I/O P1.0/TACLK/ADC10CLK 31 29 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock P1.1/TA0 32 30 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit P1.2/TA1 33 31 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA2 34 32 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/TCK 35 33 I/O General-purpose digital I/O pin/SMCLK signal output Test Clock input for device programming and test P1.5/TA0/TMS 36 34 I/O General-purpose digital I/O pin/Timer_A, compare: OUT0 output Test Mode Select input for device programming and test P1.6/TA1/TDI/TCLK 37 35 I/O General-purpose digital I/O pin/Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/TDO/TDI (2) 38 36 I/O General-purpose digital I/O pin/Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin/ACLK output ADC10, analog input A0 / OA0, analog input I0 P2.1/TAINCLK/SMCLK/A1/ OA0O 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1/OA0, analog output I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2/OA0, analog input I1 NAME P2.2/TA0/A2/OA0I1 10 8 DESCRIPTION P2.3/TA1/A3/VREF-/VeREF-/ OA1I1/OA1O 29 27 I/O General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1/OA1, analog output P2.4/TA2/A4/VREF+/VeREF+/OA1I0 30 28 I/O General-purpose digital I/O pin/Timer_A, compare: OUT2 output ADC10, analog input A4/positive reference voltage output/input OA1, analog input I0 P2.5/ROSC 3 40 I/O General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency XIN/P2.6 6 3 I/O Input terminal of crystal oscillator General-purpose digital I/O pin XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator General-purpose digital I/O pin P3.0/UCB0STE/UCA0CLK/A5 11 9 I/O General-purpose digital I/O pin USCI_B0 slave transmit enable/USCI_A0 clock input/output ADC10, analog input A5 P3.1/UCB0SIMO/UCB0SDA 12 10 I/O General-purpose digital I/O pin USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB01SOMI/UCB0SCL 13 11 I/O General-purpose digital I/O pin USCI_B0 slave out/master in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/UCA0STE 14 12 I/O General-purpose digital I/O pin USCI_B0 clock input/output/USCI_A0 slave transmit enable P3.4/UCA0TXD/UCA0SIMO 25 23 I/O General-purpose digital I/O pin USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode (1) (2) 4 If XOUT/P2.7ca7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. TDO or TDI is selected via JTAG instruction. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com TERMINAL FUNCTIONS(1) (continued) TERMINAL DA NO. RHA NO. I/O DESCRIPTION P3.5/UCA0RXD/UCA0SOMI 26 24 I/O General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode P3.6/A6/OA0I2 27 25 I/O General-purpose digital I/O pin ADC10 analog input A6/OA0 analog input I2 P3.7/A7/OA1I2 28 26 I/O General-purpose digital I/O pin ADC10 analog input A7/OA1 analog input I2 P4.0/TB0 17 15 I/O General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output P4.1/TB1 18 16 I/O General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output P4.2/TB2 19 17 I/O General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output P4.3/TB0/A12/OA0O 20 18 I/O General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12/OA0 analog output P4.4/TB1A13/OA1O 21 19 I/O General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13/OA1 analog output P4.5/TB2A14/OA0I3 22 20 I/O General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14/OA0 analog input I3 P4.6/TBOUTHA15/OA1I3 23 21 I/O General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15/OA1 analog input I3 P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin Timer_B, clock signal TBCLK input RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVCC 2 38, 39 Digital supply voltage AVCC 16 14 Analog supply voltage DVSS 4 1, 4 Digital ground reference AVSS 15 13 Analog ground reference NA Package Pad NAME QFN Pad Copyright (c) 2008-2011, Texas Instruments Incorporated NA QFN package pad connection to DVSS recommended. 5 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. General-Purpose Register R9 General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 2 shows examples of the three types of instruction formats; the address modes are listed in Table 3. General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Table 2. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 R5 Single operands, destination only e.g., CALL R8 PC (TOS), R8 PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0 Table 3. Address Mode Descriptions ADDRESS MODE (1) (2) 6 S (1) D (2) SYNTAX EXAMPLE Register * * MOV Rs,Rd MOV R10,R11 OPERATION R10 R11 Indexed * * MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6) Symbolic (PC relative) * * MOV EDE,TONI M(EDE) M(TONI) Absolute * * MOV &MEM,&TCDAT M(MEM) M(TCDAT) Indirect * MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) M(Tab+R6) Indirect autoincrement * MOV @Rn+,Rm MOV @R10+,R11 M(R10) R11 R10 + 2 R10 Immediate * MOV #X,TONI MOV #45,TONI #45 M(TONI) S = source D = destination Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP www.ti.com SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 Operating Modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: * Active mode ( AM) - All clocks are active. * Low-power mode 0 (LPM0) - CPU is disabled. ACLK and SMCLK remain active. MCLK is disabled. * Low-power mode 1 (LPM1) - CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. DCO's dc-generator is disabled if DCO not used in active mode. * Low-power mode 2 (LPM2) - CPU is disabled. MCLK and SMCLK are disabled. DCO's dc-generator remains enabled. ACLK remains active. * Low-power mode 3 (LPM3) - CPU is disabled. MCLK and SMCLK are disabled. DCO's dc-generator is disabled. ACLK remains active. * Low-power mode 4 (LPM4) - CPU is disabled. ACLK is disabled. MCLK and SMCLK are disabled. DCO's dc-generator is disabled. Crystal oscillator is stopped. Copyright (c) 2008-2011, Texas Instruments Incorporated 7 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed), the CPU goes into LPM4 immediately after power up. INTERRUPT SOURCE INTERRUPT FLAG Power up External reset Watchdog Flash key violation PC out-of-range (1) PORIFG RSTIFG WDTIFG KEYV NMI Oscillator fault Flash memory access violation (2) (3) (4) (5) (6) 8 WORD ADDRESS PRIORITY Reset 0FFFEh 31, highest (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 30 (2) NMIIFG OFIFG ACCVIFG (2) (3) Timer_B3 TBCCR0 CCIFG (4) maskable 0FFFAh 29 Timer_B3 TBCCR1 and TBCCR2 CCIFGs, TBIFG (2) (4) maskable 0FFF8h 28 0FFF6h 27 Watchdog Timer WDTIFG maskable 0FFF4h 26 Timer_A3 (1) SYSTEM INTERRUPT TACCR0 CCIFG (4) maskable 0FFF2h 25 Timer_A3 TACCR1 CCIFG, TACCR2 CCIFG, TAIFG (2) (4) maskable 0FFF0h 24 USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (2) maskable 0FFEEh 23 USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (2) maskable 0FFECh 22 ADC10 ADC10IFG (4) maskable 0FFEAh 21 0FFE8h 20 I/O Port P2 (eight flags) P2IFG.6 to P2IFG.7 (2) (4) maskable 0FFE6h 19 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (2) (4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 (5) 0FFDEh 15 (6) 0FFDCh ... 0FFC0h 14 ... 0, lowest A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh) or from within unused address range. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit disables an interrupt event. Interrupt flags are located in the module. This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if necessary. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Interrupt Enable 1 and 2 Address 7 6 00h 5 4 1 0 ACCVIE NMIIE 3 2 OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: (Non)maskable interrupt enable ACCVIE: Flash access violation interrupt enable Address 7 6 5 4 01h UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 Interrupt Flag Register 1 and 2 Address 7 6 5 02h 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault RSTIFG: External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. PORIFG: Power-On Reset interrupt flag. Set on VCC power up. NMIIFG: Address Set via RST/NMI-pin 7 6 5 03h 4 3 2 1 0 UCB0 TXIFG UCB0 RXIFG UCA0 TXIFG UCA0 RXIFG rw-1 rw-0 rw-1 rw-0 UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag xxx Copyright (c) 2008-2011, Texas Instruments Incorporated 9 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Legend: rw: Bit can be read and written. rw-0, 1: Bit can be read and written. It is Reset or Set by PUC. rw-(0), (1): Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device. Memory Organization MSP430F223x MSP430F225x MSP430F227x Memory Main: interrupt vector Main: code memory Size Flash Flash 8KB Flash 0FFFFh-0FFC0h 0FFFFh-0E000h 16KB Flash 0FFFFh-0FFC0h 0FFFFh-0C000h 32KB Flash 0FFFFh-0FFC0h 0FFFFh-08000h Information memory Size Flash 256 Byte 010FFh-01000h 256 Byte 010FFh-01000h 256 Byte 010FFh-01000h Boot memory Size ROM 1KB 0FFFh-0C00h 1KB 0FFFh-0C00h 1KB 0FFFh-0C00h Size 512 Byte 03FFh-0200h 512 Byte 03FFh-0200h 1KB 05FFh-0200h 16-bit 8-bit 8-bit SFR 01FFh-0100h 0FFh-010h 0Fh-00h 01FFh-0100h 0FFh-010h 0Fh-00h 01FFh-0100h 0FFh-010h 0Fh-00h RAM Peripherals Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report, Features of the MSP430 Bootstrap Loader, TI literature number SLAA089. BSL Function DA Package Pins RHA Package Pins Data Transmit 32 - P1.1 30 - P1.1 Data Receive 10 - P2.2 8 - P2.2 Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually, or as a group with segments 0-n. Segments A to D are also called information memory. * Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. 10 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x2xx Family User's Guide. Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: * Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator for -55C to 105C operation. For > 105C, use external clock source. * Main clock (MCLK), the system clock used by the CPU * Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules DCO Calibration Data (provided from factory in flash info memory segment A) DCO Frequency 1 MHz 8 MHz 12 MHz 16 MHz Calibration Register Size CALBC1_1MHZ byte Address 010FFh CALDCO_1MHZ byte 010FEh CALBC1_8MHZ byte 010FDh CALDCO_8MHZ byte 010FCh CALBC1_12MHZ byte 010FBh CALDCO_12MHZ byte 010FAh CALBC1_16MHZ byte 010F9h CALDCO_16MHZ byte 010F8h Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There are four 8-bit I/O ports implemented - ports P1, P2, P3, and P4: * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt condition is possible. * Edge-selectable interrupt input capability for all the eight bits of port P1 and P2. * Read/write access to port-control registers is supported by all instructions. * Each I/O has an individually programmable pullup/pulldown resistor. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Copyright (c) 2008-2011, Texas Instruments Incorporated 11 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number DA RHA Device Input Signal 31 - P1.0 29 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK 9 - P2.1 7 - P2.1 TAINCLK INCLK 32 - P1.1 30 - P1.1 TA0 CCI0A 10 - P2.2 8 - P2.2 TA0 CCI0B VSS GND VCC VCC Module Block Module Output Signal Timer NA CCR0 TA0 Output Pin Number DA RHA 32 - P1.1 30 - P1.1 10 - P2.2 8 - P2.2 36 - P1.5 34 - P1.5 33 - P1.2 31 - P1.2 TA1 CCI1A 33 - P1.2 31 - P1.2 29 - P2.3 27 - P2.3 TA1 CCI1B 29 - P2.3 27 - P2.3 VSS GND 37 - P1.6 35 - P1.6 34 - P1.3 32 - P1.3 30 - P2.4 28 - P2.4 38 - P1.7 36 - P1.7 34 - P1.3 12 Module Input Name 32 - P1.3 VCC VCC TA2 CCI2A ACLK (internal) CCI2B VSS GND VCC VCC CCR1 CCR2 TA1 TA2 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B3 Signal Connections Input Pin Number DA RHA Device Input Signal 24 - P4.7 22 - P4.7 TBCLK Module Input Name TBCLK ACLK ACLK SMCLK SMCLK 24 - P4.7 22 - P4.7 TBCLK INCLK 17 - P4.0 15 - P4.0 TB0 CCI0A 20 - P4.3 18 - P4.3 TB0 CCI0B VSS GND VCC VCC Module Block Module Output Signal Timer NA CCR0 TB0 Output Pin Number DA RHA 17 - P4.0 15 - P4.0 20 - P4.3 18 - P4.3 18 - P4.1 16 - P4.1 TB1 CCI1A 18 - P4.1 16 - P4.1 21 - P4.4 19 - P4.4 TB1 CCI1B 21 - P4.4 19 - P4.4 VSS GND 19 - P4.2 17 - P4.2 22 - P4.5 20 - P4.5 19 - P4.2 17 - P4.2 VCC VCC TB2 CCI2A ACLK (internal) CCI2B VSS GND VCC VCC CCR1 CCR2 TB1 TB2 USCI The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baud-rate detection (LIN), and IrDA. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. ADC10 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention. Copyright (c) 2008-2011, Texas Instruments Incorporated 13 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Operational Amplifier (OA) The MSP430F2274M has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion. OA0 Signal Connections Analog Input Pin Number Device Input Signal Module Input Name DA RHA 8 - A0 6 - A0 OA0I0 OAxI0 10 - A2 8 - A2 OA0I1 OA0I1 10 - A2 8 - A2 OA0I1 OAxI1 27 - A6 25 - A6 OA0I2 OAxIA 22 - A14 20 - A14 OA0I3 OAxIB xxxx OA1 Signal Connections Analog Input Pin Number 14 Device Input Signal Module Input Name 28 - A4 OA0I0 OAxI0 10 - A2 8 - A2 OA0I1 OA0I1 29 - A3 27 - A3 OA0I1 OAxI1 28 - A7 26 - A7 OA0I2 OAxIA 23 - A15 21 - A15 OA0I3 OAxIB DA RHA 30 - A4 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Peripheral File Map PERIPHERALS WITH WORD ACCESS ADC10 ADC ADC ADC ADC ADC ADC ADC ADC Timer_B ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 1BCh 1B4h 1B2h 1B0h 04Ah 04Bh 049h 048h Capture/compare register Capture/compare register Capture/compare register Timer_B register Capture/compare control Capture/compare control Capture/compare control Timer_B control Timer_B interrupt vector TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV 0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh Timer_A Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Timer+ Watchdog/timer control WDTCTL 0120h Copyright (c) 2008-2011, Texas Instruments Incorporated data transfer start address memory control register 1 control register 0 analog enable 0 analog enable 1 data transfer control register 1 data transfer control register 0 15 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com PERIPHERALS WITH BYTE ACCESS OA1 Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 1 OA1CTL1 OA1CTL0 0C3h 0C2h OA0 Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 1 OA0CTL1 OA0CTL0 0C1h 0C0h USI_B0 USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address UCB0TXBUF UCB0RXBUF UCB0STAT UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA 06Fh 06Eh 06Dh 06Bh 06Ah 069h 068h 011Ah 0118h USI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL 053h 058h 057h 056h Port P4 Port P4 resistor enable Port P4 selection Port P4 direction Port P4 output Port P4 input P4REN P4SEL P4DIR P4OUT P4IN 011h 01Fh 01Eh 01Dh 01Ch Port P3 Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input P3REN P3SEL P3DIR P3OUT P3IN 010h 01Bh 01Ah 019h 018h Port P2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 027h 026h 025h 024h 023h 022h 021h 020h Special Function SFR SFR SFR SFR IFG2 IFG1 IE2 IE1 003h 002h 001h 000h 16 interrupt flag 2 interrupt flag 1 interrupt enable 2 interrupt enable 1 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Absolute Maximum Ratings (1) VALUE UNIT Voltage applied at VCC to VSS -0.3 to 4.1 V Voltage applied to any pin (2) -0.3 to VCC + 0.3 V 2 mA -55 to 150 C -55 to 125 C Diode current at any device terminal Storage temperature, Tstg (unprogrammed device (3)) Storage temperature, Tstg (programmed device (1) (2) (3) (3) ) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Copyright (c) 2008-2011, Texas Instruments Incorporated 17 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Recommended Operating Conditions (1) (2) MIN VCC UNIT 3.6 V Supply voltage during program/erase flash memory 2.2 3.6 V Supply voltage TA Operating free-air temperature range 0 Processor frequency fSYSTEM (Maximum MCLK frequency) (1) (see Figure 1) (2) MAX 1.8 VSS (1) NOM Supply voltage during program execution (2) V -55 125 VCC = 1.8 V, Duty Cycle = 50% 10% dc 4.15 VCC = 2.7 V, Duty Cycle = 50% 10% dc 12 VCC 3.3 V, Duty Cycle = 50% 10% dc 16 C MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet. System Frequency -MHz 16 MHz 12 MHz 7.5 MHz 4.15 MHz 1.8 V IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII 2.2 V 2.7 V III III III III III III III III Legend: Supply voltage range, during flash memory programming Supply voltage range, during program execution 3.3 V 3.6 V Supply Voltage -V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 18 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Active-Mode Supply Current (Into DVCC + AVCC) Excluding External Current - Electrical Characteristics (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER IAM, IAM, IAM, TA VCC 1MHz 1MHz fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32,768 Hz, Program executes in RAM, Active-mode (AM) BCSCTL1 = CALBC1_1 MHZ, current (1 MHz) DCOCTL = CALDCO_1 MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -55C to 85C 4kHz fMCLK = fSMCLK = fACLK = 32,768 Hz/8 = 4,096 Hz, fDCO = 0 Hz, Active-mode (AM) Program executes in flash, current (4 kHz) SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = fDCO(0, 0) 100 kHz, fACLK = 0 Hz, Active-mode (AM) Program executes in flash, current (100 kHz) RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -55C to 85C IAM,100kHz (1) (2) TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32,768 Hz, Program executes in flash, Active-mode (AM) BCSCTL1 = CALBC1_1 MHZ, current (1 MHz) DCOCTL = CALDCO_1 MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -55C to 125C 125C MIN TYP MAX 2.2 V 270 390 3V 390 550 2.2 V 240 3V 340 5 2.2 V 6 3V 125C A 9 10 A 20 60 2.2 V 85 95 -55C to 85C 72 3V 125C A 18 -55C to 85C 125C UNIT A 95 125 All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. For TA < 105C, the currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. For TA > 105C, the currents are characterized using a 32-kHz external clock source for ACLK.. Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC) 5.0 8.0 fDCO = 16 MHz TA = 85 C Active Mode Current - mA Active Mode Current - mA 7.0 6.0 fDCO = 12 MHz 5.0 4.0 fDCO = 8 MHz 3.0 2.0 4.0 TA = 25 C 3.0 VCC = 3 V 2.0 TA = 85 C TA = 25 C 1.0 1.0 0.0 1.5 VCC = 2.2 V fDCO = 1 MHz 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 2. Active-Mode Current vs VCC, TA = 25C Copyright (c) 2008-2011, Texas Instruments Incorporated 0.0 0.0 4.0 8.0 12.0 16.0 fDCO - DCO Frequency - MHz Figure 3. Active-Mode Current vs DCO Frequency 19 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Low-Power-Mode Supply Currents (Into DVCC + AVCC) Excluding External Current - Electrical Characteristics (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0, 1MHz ILPM0, 100kHz ILPM2 ILPM3,LFXT1 TEST CONDITIONS Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32,768 Hz, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO(0, 0) 100 kHz, fACLK = 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 Low-power mode 2 (LPM2) current (4) fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32,768 Hz, BCSCTL1 = CALBC1_1 MHZ, DCOCTL = CALDCO_1 MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 Low-power mode 3 (LPM3) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32,768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 TA -55C to 125C -55C to 125C -55C to 85C 125C 125C ILPM3,VLO Low-power mode 3 current, (LPM3) (4) (1) (2) (3) (4) (5) 20 Low-power mode 4 (LPM4) current (5) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 TYP MAX 90 3V 90 120 2.2 V 37 60 3V 41 75 22 29 2.2 V 3V 32 0.7 1.4 0.7 1.4 2.8 4.5 85C 125C 6 18 -55C 0.9 1.5 0.9 1.5 3.0 5.0 125C 6.5 19 -55C 0.4 1.0 25C 0.5 1.0 2.2 4.2 125C 5.7 18 -55C 0.5 1.2 0.6 1.2 2.5 4.5 25C 85C 25C 3V 2.2 V 3V 125C 6.0 19 -55C 0.1 0.5 0.1 0.5 1.9 4.0 5.5 16 25C 85C 125C 2.2 V/ 3V A A A 45 25C 2.2 V UNIT 40 25 -55C 85C ILPM4 MIN 75 -55C to 85C 85C fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 VCC 2.2 V A A A All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. For TA < 105C, the currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. For TA > 105C, ACLK was sourced from an external clock source. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI (1)) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VIT+ Positive-going input threshold voltage -55C to 125C VIT- Negative-going input threshold voltage -55C to 125C Vhys Input voltage hysteresis (VIT+ - VIT-) -55C to 125C RPull Pullup/pulldown resistor For pullup: VIN = VSS; For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC (1) VCC MIN TYP MAX 2.2 V 1.00 1.65 3V 1.35 2.25 2.2 V .55 1.20 3V .75 1.65 2.2 V 0.2 1.0 3V 0.3 1.0 -55C to 125C 20 35 50 5 UNIT V V V k pF RST/NMI limit values specified for -55C to 125C. Inputs (Ports P1 and P2) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) External interrupt timing TEST CONDITIONS TA VCC Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag (1) -55C to 125C 2.2 V/3 V MIN MAX 20 UNIT ns An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals shorter than t(int). Leakage Current (Ports P1, P2, P3 and P4) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.x) (1) (2) High-impedance leakage current TEST CONDITIONS (1) (2) TA VCC -55C to 125C 2.2 V/3 V MIN MAX 100 UNIT nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Copyright (c) 2008-2011, Texas Instruments Incorporated 21 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Outputs (Ports P1, P2, P3, and P4) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA High-level output voltage VOH Low-level output voltage (1) (2) (2) IOH(max) = -6 mA TA VCC -55C to 125C -55C to 125C IOH(max) = -1.5 mA (1) -55C to 125C IOH(max) = -6 mA (2) -55C to 125C (1) -55C to 125C IOL(max) = 1.5 mA VOL (1) IOL(max) = 6 mA (2) -55C to 125C IOL(max) = 1.5 mA (1) -55C to 125C IOL(max) = 6 mA (2) -55C to 125C 2.2 V 3V MIN MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.25 VCC VCC - 0.6 VCC VSS VSS+0.25 2.2 V 3V VSS VSS+0.6 VSS VSS+0.25 VSS VSS+0.6 UNIT V V The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. Output Frequency (Ports P1, P2, P3, and P4) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA fPx.y Port output frequency (with load) P1.4/SMCLK, CL = 20 pF, RL = 1 k against VCC/2 (1) (2) -55C to 125C fPort_CLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2) -55C to 125C (1) (2) 22 VCC MIN MAX 2.2 V 10 3V 12 2.2 V 12 3V 16 UNIT MHz MHz A resistive divider with 2 times 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - Outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P4.5 TA = 25C 20.0 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 25.0 TA = 85C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P4.5 40.0 TA = 85C 30.0 20.0 10.0 0.0 0.0 2.5 TA = 25C VOL - Low-Level Output Voltage - V 0.5 1.0 Figure 4. 3.0 3.5 0.0 VCC = 2.2 V P4.5 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA 2.5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 -5.0 -10.0 -15.0 -25.0 0.0 2.0 Figure 5. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE -20.0 1.5 VOL - Low-Level Output Voltage - V TA = 85C TA = 25C 0.5 1.0 1.5 2.0 VOH - High-Level Output Voltage - V Figure 6. Copyright (c) 2008-2011, Texas Instruments Incorporated 2.5 VCC = 3 V P4.5 -10.0 -20.0 -30.0 TA = 85C -40.0 -50.0 0.0 TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH - High-Level Output Voltage - V Figure 7. 23 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com POR/Brownout Reset (BOR) - Electrical Characteristics (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER TA See Figure 8 dVCC/dt 3 V/s V(B_IT-) See Figure 8 through Figure 10 dVCC/dt 3 V/s -55C to 125C Vhys(B_IT-) See Figure 8 dVCC/dt 3 V/s -55C to 125C td(BOR) See Figure 8 -55C to 125C t(reset) Pulse length needed at RST/NMI pin to accepted reset internally -55C to 125C (2) MIN TYP MAX 0.7 x V(B_IT-) VCC(start) (1) VCC 70 2.2 V/3 V 2 130 UNIT V 1.71 V 210 mV 2000 s s The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT- ) is 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 24 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw - Pulse Width - s 1 ns tpw - Pulse Width - s Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 tpw - Pulse Width - s 1000 tf tr tpw - Pulse Width - s Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal Copyright (c) 2008-2011, Texas Instruments Incorporated 25 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Main DCO Characteristics * * * All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: 32 f DCO(RSEL,DCO) f DCO(RSEL,DCO ) 1) f average + MOD f DCO(RSEL,DCO) ) (32 * MOD) f DCO(RSEL,DCO ) 1) DCO Frequency - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage range MIN TYP MAX RSELx < 14 TEST CONDITIONS -55C to 125C TA VCC 1.8 3.6 UNIT RSELx = 14 -55C to 125C 2.2 3.6 RSELx = 15 -55C to 125C 3.0 3.6 -55C to 125C 2.2 V/3 V 0.06 0.14 MHz V fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.10 0.20 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.14 0.28 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.20 0.40 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.28 0.54 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.39 0.77 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 1.10 2.10 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 1.60 3.00 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 2.50 4.30 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 3.00 5.50 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 4.30 7.30 M Hz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 -55C to 125C 2.2 V/3 V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 -55C to 125C 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 -55C to 125C 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) -55C to 125C 2.2 V/3 V 1.55 ratio 26 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com DCO Frequency - Electrical Characteristics (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER SDCO Duty cycle Frequency step between tap DCO and DCO+1 TEST CONDITIONS TA VCC MIN TYP MAX UNIT SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) -55C to 125C 2.2 V/3 V 1.05 1.08 1.12 ratio Measured at P1.4/SMCLK -55C to 125C 2.2 V/3 V 40 50 60 Copyright (c) 2008-2011, Texas Instruments Incorporated % 27 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Calibrated DCO Frequencies (Tolerance at Calibration) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25C 3V -1 0.2 1 25C 3V 0.990 1 1.010 MHz % fCAL(1 MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms fCAL(8 MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 3V 7.920 8 8.080 MHz fCAL(12 MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 3V 11.88 12 12.12 MHz fCAL(16 MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3V 15.84 16 16.16 MHz Calibrated DCO Frequencies (Tolerance Over Temperature) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC MIN TYP MAX 1-MHz tolerance over temperature -55C to 125C 3V -2.5 0.5 2.5 % 8-MHz tolerance over temperature -55C to 125C 3V -2.5 1.0 2.5 % 12-MHz tolerance over temperature -55C to 125C 3V -2.5 1.0 2.5 % 16-MHz tolerance over temperature -55C to 125C % fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) 28 1-MHz calibration value 8-MHz calibration value 12-MHz calibration value 16-MHz calibration value TEST CONDITIONS BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms -55C to 125C BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms -55C to 125C BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms -55C to 125C BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms -55C to 125C 3V -3.0 2.0 3.0 2.2 V 0.970 1 1.030 3V 0.975 1 1.025 3.6 V 0.970 1 1.030 2.2 V 7.760 8 8.400 3V 7.800 8 8.200 3.6 V 7.600 8 8.240 2.2 V 11.70 12 12.30 3V 11.70 12 12.30 3.6 V 11.70 12 12.30 3V 15.52 16 16.48 3.6 V 15.00 16 16.48 UNIT MHz MHz MHz MHz Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Calibrated DCO Frequencies (Tolerance Over Supply Voltage VCC) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25C 8-MHz tolerance overVCC 25C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 2 3 % 1.8 V to 3.6 V -3 2 3 % 25C 2.2 V to 3.6 V -3 2 3 % 25C 3 V to 3.6 V -6 2 3 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 0.970 1 1.030 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 7.760 8 8.240 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 2.2 V to 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3 V to 3.6 V 15.00 16 16.48 MHz Calibrated DCO Frequencies (Overall Tolerance) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over temperature -55C to 125C 8-MHz tolerance over temperature UNIT 1.8 V to 3.6 V -5 2 +5 % -55C to 125C 1.8 V to 3.6 V -5 2 +5 % 12-MHz tolerance over temperature -55C to 125C 2.2 V to 3.6 V -5 2 +5 % 16-MHz tolerance over temperature -55C to 125C 3 V to 3.6 V -6 3 +6 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms -55C to 125C 1.8 V to 3.6 V .950 1 1.050 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms -55C to 125C 1.8 V to 3.6 V 7.6 8 8.4 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms -55C to 125C 2.2 V to 3.6 V 11.4 12 12.6 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms -55C to 125C 3 V to 3.6 V 15.00 16 17.00 MHz Copyright (c) 2008-2011, Texas Instruments Incorporated 29 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency 1.03 1.03 1.02 1.02 Frequency - MHz 1.00 VCC = 2.2 V VCC = 3.0 V 0.99 Frequency - MHz VCC = 1.8 V 1.01 TA = 125 C 1.01 TA = 85 C 1.00 TA = 25 C 0.99 TA = -40 C VCC = 3.6 V 0.98 0.98 0.97 -50.0 -25.0 0.0 25.0 50.0 75.0 100.0 0.97 1.5 2.0 TA - Temperature - C Figure 11. Calibrated 1-MHz Frequency vs Temperature 2.5 3.0 3.5 4.0 VCC - Suppl y Voltage - V Figure 12. Calibrated 1-MHz Frequency vs VCC Wake-Up From Lower-Power Modes (LPM3/4) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tDCO,LPM3/4 tCPU,LPM3/4 DCO clock wake-up time from LPM3/4 (1) CPU wake-up time from LPM3/4 (2) TA VCC BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, TEST CONDITIONS MIN TYP MAX -55C to 125C 2.2 V/3 V 2 BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, -55C to 125C 2.2 V/3 V 1.5 BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, -55C to 125C 3V 1 BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, -55C to 125C 3V 1 UNIT s 1/fMCL K+ tClock,L PM3/4 (1) (2) 30 The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 DCO Wake Time - us 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency - MHz Figure 13. Clock Wake-Up Time From LPM3 vs DCO Frequency DCO With External Resistor ROSC - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TYP 1.8 UNIT fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25C 2.2 V 3V 1.95 Dt Temperature drift DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.1 %/C DV Drift with VCC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 10 %/V (1) MHz ROSC = 100k. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = 50ppm/C Copyright (c) 2008-2011, Texas Instruments Incorporated 31 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - DCO With External Resistor ROSC 10.00 DCO Frequency - MHz DCO Frequency - MHz 10.00 1.00 0.10 RSELx = 4 0.01 10.00 100.00 1000.00 1.00 0.10 RSELx = 4 0.01 10.00 10000.00 ROSC - External Resistor - kW 2.50 2.25 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 DCO Frequency - MHz 2.25 DCO Frequency - MHz 10000.00 Figure 15. DCO Frequency vs ROSC, VCC = 3.0 V, TA = 25C 2.50 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 ROSC = 1M 0.25 -25.0 0.0 25.0 50.0 75.0 ROSC = 1M 0.25 100.0 TA - Temperature - 5C Figure 16. DCO Frequency vs Temperature, VCC = 3.0 V 32 1000.00 ROSC - External Resistor - kW Figure 14. DCO Frequency vs ROSC, VCC = 2.2 V, TA = 25C 0.00 -50.0 100.00 0.00 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 17. DCO Frequency vs VCC, TA = 25C Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Crystal Oscillator (LFXT1) Low-Frequency Modes - Electrical Characteristics (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 XTS = 0, LFXT1Sx = 0 or 1 -55C to 105C 1.8 V to 3.6 V fLFXT1,LF, LFXT1 oscillator logic-level square-wave input frequency, LF mode XTS = 0, LFXT1Sx = 3 -55C to 125C 1.8 V to 3.6 V XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 6 pF -55C to 105C 500 XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF -55C to 105C 200 logic OALF Oscillation allowance for LF crystals 32,768 10,000 1 XCAPx = 1 5.5 XTS = 0 Duty Cycle LF mode XTS = 0, Measured at P1.4/ACLK, fLFXT1,LF = 32,768 Hz -55C to 125C 2.2 V/3 V 30 fFault,LF Oscillator fault frequency threshold, LF mode (4) XTS = 0, LFXT1Sx = 3 (5) -55C to 125C 2.2 V/3 V 10 -55C to 105C (2) (3) (4) (5) 50,000 Hz pF 8.5 XCAPx = 3 (1) Hz 32,768 XCAPx = 0 XCAPx = 2 UNIT k Integrated effective load capacitance, LF mode (3) CL,eff MAX 11 50 70 % 10,000 Hz To improve EMI on the LFXT1 oscillator the following guidelines should be observed: (a) Keep as short of a trace as possible between the device and the crystal. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Use of the LFXT1 Crystal Oscillator with TA > 105C is not guaranteed. It is recommended that an external digital clock source or the internal DCO is used to provide clocking. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals with TA < 105C. Internal Very-Low-Power, Low-Frequency Oscillator (VLO) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER fVLO VLO frequency dfVLO/dT VLO frequency temperature drift dfVLO/dVCC VLO frequency supply voltage drift (1) (2) TA VCC -55C to 85C 2.2 V/3 V 125C 2.2 V/3 V (1) -55C to 125C 2.2 V/3 V (2) 25C 1.8 V - 3.6V MIN 4 TYP MAX 12 20 22 UNIT kHz 0.5 %/C 4 %/V Calculated using the box method: I Version: [MAX(-55...85C) - MIN(-55...85C)]/MIN(55-...85C)/[85C - (-55C)] T Version: [MAX(-55...125C) - MIN(-55...125C)]/MIN(-55...125C)/[125C - (-55C)] Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V) Copyright (c) 2008-2011, Texas Instruments Incorporated 33 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Crystal Oscillator (LFXT1) High Frequency Modes - Electrical Characteristics (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fLFXT1, HF0 fLFXT1, HF1 fLFXT1, HF2 fLFXT1, HF,logic TA VCC MIN TYP MAX UNIT XTS = 1, LFXT1Sx = 0 -55C to 125C 1.8 V to 3.6 V 0.4 1 MHz LFXT1 oscillator lcrystal frequency, XTS = 1, LFXT1Sx = 1 HF mode 1 -55C to 125C 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 LFXT1 oscillator crystal frequency, HF mode 2 -55C to 125C 2.2 V to 3.6 V 2 12 MHz 3 V to 3.6 V 2 16 1.8 V to 3.6 V 0.4 10 2.2 V to 3.6 V 0.4 12 MHz 3 V to 3.6 V 0.4 16 LFXT1 oscillator crystal frequency, HF mode 0 LFXT1 oscillator logic-level square-wave input frequency, HF mode TEST CONDITIONS XTS = 1, LFXT1Sx = 2 XTS = 1, LFXT1Sx = 3 -55C to 125C XTS = 0, LFXT1Sx = 0; fLFXT1,HF = 1 MHz, CL,eff = 15 pF OAHF Oscillation allowance for HF crystals (see Figure 18 and Figure 19) XTS = 0, LFXT1Sx = 1 fLFXT1,HF = 4 MHz, CL,eff = 15 pF 2700 -55C to 125C XTS = 0, LFXT1Sx = 2 fLFXT1,HF = 16 MHz, CL,eff = 15 pF CL,eff Duty Cycle fFault,HF (1) (2) (3) (4) (5) (6) 34 Integrated effective load capacitance, HF mode (3) HF mode Oscillator fault frequency, HF mode (5) 800 300 XTS = 1 (4) -55C to 125C XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 10 MHz -55C to 125C XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 16 MHz -55C to 125C XTS = 1, LFXT1Sx = 3 (6) -55C to 125C 1 40 50 pF 60 2.2 V/3 V % 40 2.2 V/3 V 30 50 60 300 kHz To improve EMI on the LFXT1 oscillator the following guidelines should be observed: (a) Keep as short of a trace as possible between the device and the crystal. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Use of the LFXT1 Crystal Oscillator with TA > 105C is not guaranteed. It is recommended that an external digital clock source or the internal DCO is used to provide clocking. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) 800.0 100000.00 Oscillation Allowance - W 10000.00 1000.00 LFXT1Sx = 3 100.00 LFXT1Sx = 1 LFXT1Sx = 2 XT Oscillator Supply Current - uA LFXT1Sx = 3 700.0 600.0 500.0 400.0 300.0 LFXT1Sx = 2 200.0 100.0 LFXT1Sx = 1 10.00 0.10 1.00 10.00 0.0 0.0 100.00 Crystal Frequency - MHz 4.0 8.0 12.0 16.0 20.0 Crystal Frequency - MHz Figure 18. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25C Figure 19. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25C Timer_A - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK, External: TACLK, INCLK, Duty cycle = 50% 10% tTA,cap Timer_A, capture timing TA0, TA1, TA2 TA -55C to 125C -55C to 125C VCC MIN MAX 2.2 V 10 3V 16 2.2 V/3 V 20 UNIT MHz ns Timer_B - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B clock frequency Internal: SMCLK, ACLK, External: TBCLK, Duty Cycle = 50% 10% tTB,cap Timer_B, capture timing TB0, TB1, TB2 Copyright (c) 2008-2011, Texas Instruments Incorporated TA -55C to 125C -55C to 125C VCC MIN MAX 2.2 V 10 3V 16 2.2 V/3 V 20 UNIT MHz ns 35 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com USCI (UART Mode) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Internal: SMCLK, ACLK, External: UCLK; Duty cycle = 50% 10% TA VCC TYP -55C to 125C fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) -55C to 125C t UART receive deglitch time (1) -55C to 125C (1) MIN MAX UNIT fSYSTE MHz M 2.2 V/3 V 1 2.2 V 50 150 600 3V 50 150 600 MHz ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their width should exceed the maximum specification of the deglitch time. USCI (SPI Master Mode) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20 and Figure 21) PARAMETER TEST CONDITIONS SMCLK, ACLK, Duty cycle = 50% 10% TA MIN -55C to 125C fUSCI USCI input clock frequency tSU,MI SOMI input data setup time -55C to 125C tHD,MI SOMI input data hold time -55C to 125C tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF VCC -55C to 125C 2.2 V 110 3V 75 2.2 V 0 3V 0 MAX UNIT fSYSTEM MHz ns ns 2.2 V 30 3V 20 ns USCI (SPI Slave Mode) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 22 and Figure 23) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT tSTE,LEAD STE lead time, STE low to clock tSTE,LAG STE lag time, Last clock to STE high tSTE,ACC STE access time, STE low to SOMI data out 2.2 V/3 V 50 ns tSTE,DIS STE disable time, STE high to SOMI high impedance 2.2 V/3 V 50 ns tSU,SI SIMO input data setup time -55C to 125C tHD,SI SIMO input data hold time -55C to 125C tVALID,SO SOMI output data valid time 36 2.2 V/3 V -55C to 125C UCLK edge to SOMI valid, CL = 20 pF -55C to 125C 2.2 V/3 V 50 ns 10 2.2 V 20 3V 15 2.2 V 10 3V 10 ns ns ns 2.2 V 75 110 3V 50 75 ns Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SCMI tVALID, MO SIMO Figure 20. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SCMI tVALID, MO SIMO Figure 21. SPI Master Mode, CKPH = 1 Copyright (c) 2008-2011, Texas Instruments Incorporated 37 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW,HIGH tLOW,HIGH tSU,SIMO tHD,SIMO SIMO tACC tVALID,SOMI tDIS SOMI Figure 22. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW,HIGH tLOW,HIGH tHD,SI , tSU,SI SIMO tACC tVALID,SO tDIS SOMI Figure 23. SPI Slave Mode, CKPH = 1 38 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com USCI (I2C Mode) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24) PARAMETER TEST CONDITIONS TA VCC MIN Internal: SMCLK, ACLK, External: UCLK, Duty cycle = 50% 10% TYP MAX fSYST UNIT fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Set-up time for a repeated START tHD,DAT Data hold time -55C to 125C 2.2 V/3 V 0 ns tSU,DAT Data set-up time -55C to 125C 2.2 V/3 V 250 ns tSU,STO Set-up time for STOP -55C to 125C 2.2 V/3 V 4.0 s tSP Pulse width of spikes suppressed by input filter -55C to 125C 2.2 V 50 150 600 3V 50 100 600 -55C to 125C fSCL 100 kHz -55C to 125C fSCL > 100 kHz -55C to 125C fSCL 100 kHz -55C to 125C fSCL > 100 kHz -55C to 125C tHD ,STA MHz EM 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 0 400 4.0 s 0.6 4.7 s 0.6 tSU ,STA tHD ,STA kHz ns tBUF SDA t LOW tHIGH tSP SCL tSU ,DAT tSU , STO tHD ,DAT Figure 24. I2C Mode Timing Copyright (c) 2008-2011, Texas Instruments Incorporated 39 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 10-Bit ADC, Power-Supply and Input Range Conditions - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC TEST CONDITIONS Analog supply voltage range VAx Analog input voltage range IADC10 IREF+ ADC10 supply current (2) (3) Reference supply current, reference buffer disabled (4) TA VCC UNIT -55C to125 C 2.2 3.6 V All Ax terminals, Analog inputs selected in ADC10AE register -55C to 125C 0 VCC V fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0 2.2 V 0.52 1.05 -55C to 125C 3V 0.6 1.2 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 -55C to 125C fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0 0.25 .4 -55C to 125C 3V 1.1 1.4 mA 2.2 V/3 V fADC10CLK = 5.0 MHz, ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR = 0 -55C to 85C 2.2 V/3 V Reference buffer supply current with ADC10SR = 0 (4) 125C 2.2 V/3 V 2.2 V/3 V Reference buffer supply current with ADC10SR = 1 (4) fADC10CLK = 5.0 MHz, ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR=1 -55C to 85C IREFB,1 125C 2.2 V/3 V CI Input capacitance Only one terminal Ax selected at a time RI Input MUX ON resistance 0 V VAx VCC 40 TYP MAX VSS = 0 V IREFB,0 (1) (2) (3) (4) MIN 2.2 V/3 V 1.8 0.5 mA mA .7 mA .8 mA 27 pF 2000 The leakage current is defined in the leakage current table with Px.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC10. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 10-Bit ADC, Built-In Voltage Reference - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC,REF+ Positive built-in reference analog supply voltage range VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VREF+ load regulation TEST CONDITIONS TA VCC MIN TYP MAX IVREF+ 1 mA, REF2_5V = 0 -55C to 125C 2.2 IVREF+ 0.5 mA, REF2_5V = 1 -55C to 125C 2.8 IVREF+ 1 mA, REF2_5V = 1 -55C to 125C 2.9 IVREF+ IVREF+max, REF2_5V = 0 -55C to 125C 2.2 V/3 V 1.41 1.5 1.59 IVREF+ IVREF+max, REF2_5V = 1 -55C to 125C 3V 2.35 2.5 2.65 -55C to 125C IVREF+ = 500 A 100 A, Analog input voltage VAx 0.75 V, REF2_5V = 0 -55C to 125C IVREF+ = 500 A 100 A, Analog input voltage VAx 1.25 V, REF2_5V = 1 -55C to 125C 2.2 V UNIT V 0.5 3V 1 2.2 V/3 V 2 V mA LSB VREF+ load regulation response time CVREF+ Maximum capacitance at pin VREF+ (1) IVREF+ = 1 mA, REFON = 1, REFOUT = 1 -55C to 125C 2.2 V/3 V 100 pF TCREF+ Temperature coefficient IVREF+ = const. with 0 mA IVREF+ 1 mA -55C to 125C 2.2 V/3 V 100 ppm/ C tREFON Settling time of internal IVREF+ = 0.5 mA, REF2_5V = 0 reference voltage (2) REFON = 0 1 -55C to 125C 3.6 V tREFBURST (1) (2) -55C to 125C ADC10SR = 1 -55C to 125C 2 IVREF+ = 100 A900 A, VAx 0.5 x VREF+, Error of conversion result 1 LSB Settling time of reference buffer (2) ADC10SR = 0 3V IVREF+ = 0.5 mA, REF2_5V = 0, REFON = 1, REFBURST = 1 ADC10SR = 0 -55C to 125C ADC10SR = 1 -55C to 125C IVREF+ = 0.5 mA, REF2_5V = 1, REFON = 1, REFBURST = 1 ADC10SR = 0 -55C to 125C ADC10SR = 1 -55C to 125C 400 3V 2000 30 ns s 1 2.2 V 2.5 2 3V s 4.5 The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT = 1), must be limited; the reference buffer may become unstable otherwise. The condition is that the error in a conversion started after tREFON or tRefBuf is less than 0.5 LSB. Copyright (c) 2008-2011, Texas Instruments Incorporated 41 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 10-Bit ADC, External Reference - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (2) VCC VeREF- VeREF+ VCC - 0.15 V,SREF1 = 1, SREF0 = 1 (3) -55C to 125C 1.4 3.0 -55C to 125C 0 1.2 V -55C to 125C 1.4 VCC V Differential external reference input voltage range, VeREF = VeREF+ - VeREF- (1) (2) (3) (4) (5) Static input current into VeREF- UNIT 1.4 VeREF IVeREF- MIN MAX -55C to 125C Negative external reference input VeREF+ > VeREF- voltage range (4) Static input current into VeREF+ VCC VeREF+ > VeREF-, SREF1 = 1, SREF0 = 0 VeREF- IVeREF+ TA VeREF+ > VeREF- V (5) 0 V VeREF+ VCC, SREF1 = 1, SREF0 = 0 -55C to 125C 2.2 V/3 V 1 0 V VeREF+ VCC - 0.15 V 3 V, SREF1 = 1, SREF0 = 1(3) -55C to 125C 2.2 V/3 V 0 0 V VeREF- VCC -55C to 125C 2.2 V/3 V 1 A A The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 10-Bit ADC, Timing Parameters - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN ADC10SR=0 -55C to 125C 2.2 V/3 V 0.45 TYP MAX 6.5 ADC10SR=1 -55C to 125C 2.2 V/3 V 0.45 1.5 fADC10CLK ADC10 input clock frequency For specified performance of ADC10 linearity parameters fADC10OSC ADC10 built-in oscillator frequency ADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK = fADC10OSC -55C to 125C 2.2 V/3 V 3.25 6.45 ADC10 built-in oscillator, ADC10SSELx = 0, fADC10CLK = fADC10OSC -55C to 125C 2.2 V/3 V 2.06 3.51 tCONVERT Conversion time fADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx 0 tADC10ON (1) 42 Turn-on settling time of the ADC -55C to 125C (1) -55C to 125C UNIT MHz MHz s 13 = ADC10DIVx 1/fADC10CLK 100 ns The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already settled. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 10-Bit ADC, Linearity Parameters - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT EI Integral linearity error -55C to 125C 2.2 V/3 V 1 LSB ED Differential linearity error -55C to 125C 2.2 V/3 V 1 LSB EO Offset error Source impedance RS < 100 -55C to 125C 2.2 V/3 V 1 LSB SREFx = 010, un-buffered external reference, VeREF+ = 1.5 V -55C to 125C 2.2 V 1.1 2 SREFx = 010; un-buffered external reference, VeREF+ = 2.5 V -55C to 125C 3V 1.1 2 SREFx = 011, buffered external reference (2), VeREF+ = 1.5 V -55C to 125C 2.2 V 1.1 4 SREFx = 011, buffered external reference (2), VeREF+ = 2.5 V -55C to 125C 3V 1.1 3 SREFx = 010, unbuffered external reference, VeREF+ = 1.5 V -55C to 125C 2.2 V 2 5 SREFx = 010, unbuffered external reference, VeREF+ = 2.5 V -55C to 125C 3V 2 5 SREFx = 011, buffered external reference (2), VeREF+ = 1.5 V -55C to 125C 2.2 V 2 7 SREFx = 011, buffered external reference (2), VeREF+ = 2.5 V -55C to 125C 3V 2 6 EG ET (1) (2) Gain error Total unadjusted error LSB LSB 2.2V Not Production Tested. The reference buffer's offset adds to the gain and total unadjusted error. Copyright (c) 2008-2011, Texas Instruments Incorporated 43 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com 10-Bit ADC, Temperature Sensor and Built-In VMID - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Temperature sensor supply current (1) ISENSOR TCSENSOR VOffset,Sensor Sensor offset voltage Sensor output voltage (3) VSensor TA VCC 40 120 3V 60 160 ADC10ON = 1, INCHx = 0Ah (2) -55C to 125C ADC10ON = 1, INCHx = 0Ah (2) -55C to 125C -100 100 Temperature sensor voltage at TA = 125C (T version only) -55C to 125C 1265 1365 1465 Temperature sensor voltage at TA = 85C -55C to 125C 1195 1295 1395 Temperature sensor voltage at TA = 25C -55C to 125C 985 1085 1185 Temperature sensor voltage at TA = 0C -55C to 125C 895 995 1095 ADC10ON = 1, INCHx = 0Ah, Error of conversion result 1 LSB -55C to 125C IVMID Current into divider at channel 11 (5) ADC10ON = 1, INCHx = 0Bh -55C to 125C VMID VCC divider at channel 11 ADC10ON = 1, INCHx = 0Bh, VMID is 0.5 x VCC -55C to 125C tVMID(sample) Sample time required if channel 11 is selected (6) ADC10ON = 1, INCHx = 0Bh, Error of conversion result 1 LSB -55C to 125C (3) (4) (5) (6) 2.2 V -55C to 125C Sample time required if channel 10 is selected (4) (2) TYP MAX REFON = 0, INCHx = 0Ah, TA = 25C tSensor(sample) (1) MIN 2.2 V/3 V 2.2 V/3 V 3.44 2.2 V/3 V 3.55 UNIT A 3.66 mV/C mV mV s 30 2.2 V NA 3V NA 2.2 V 1.06 1.1 1.14 3V 1.46 1.5 1.54 2.2 V 1400 3V 1220 A V ns The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor (273 + T [C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [C] + VSensor(TA = 0C) [mV] Results based on characterization and/or production test, not TCSensor or VOffset,sensor. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). No additional current is needed. The VMID is used during sampling. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. Operational Amplifier (OA) Supply Specifications - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply current (1) ICC PSSR (1) 44 TEST CONDITIONS Power-supply rejection ratio TA VCC -55C to 125C Supply voltage range Fast Mode -55C to 125C Medium Mode -55C to 125C Slow Mode -55C to 125C Noninverting MIN TYP 2.2 2.2 V/3 V 2.2 V/3 V MAX 3.6 180 290 110 190 50 80 70 UNIT V A dB Corresponding pins configured as OA inputs and outputs, respectively. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Operational Amplifier (OA) Input/Output Specifications - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VI/P Input voltage range Ilkg Input leakage current (1) (2) TA VCC -55C to 125C 2.2 V/3 V Medium Mode 15 20 VOL fV(I/P) = 1 kHz 140 fV(I/P) = 10 kHz 50 65 -55C to 125C See Offset voltage drift with supply, I/P 0.3 V VIN VCC - 1.0 V VCC 10%, TA = 25C -55C to 125C High-level output voltage, O/P Fast Mode, ISOURCE -500 A -55C to 125C Slow Mode, ISOURCE -150 A -55C to 125C Low-level output voltage, O/P Fast Mode, ISOURCE 500 A -55C to 125C (3) (1) (2) (3) (4) 10 2.2 V/3 V -55C to 125C 2.2 V/3 V mV V/C 1.5 2.2 V/3 V 2.2 V/3 V Slow Mode, ISOURCE 150 A Common-mode rejection ratio 10 2.2 V/3 V VCC - 0.2 VCC VCC - 0.1 VCC VSS 0.2 VSS 0.1 mV/V V V 150 RLoad = 3 k, CLoad = 50 pF, VO/P(OAx) > VCC - 1.2 V 2.2 V/3 V RLoad = 3 k, CLoad = 50 pF, 0.2 V VO/P(OAx) VCC - 0.2 V CMRR nV/Hz 30 Offset temperature drift, I/P Output resistance (4) (see Figure 25) 100 80 RLoad = 3 k, CLoad = 50 pF, VO/P(OAx) < 0.2 V RO/P(OAx) nA 50 Offset voltage, I/P VOH V 5 Slow Mode VIO VCC 1.2 0.5 Voltage noise density, Slow Mode I/P Fast Mode Vn UNIT -20 -100 85C to 125C MAX -15 Fast Mode Medium Mode TYP -0.1 -55C to 55C 55C to 85C MIN 150 0.1 Noninverting 2.2 V/3 V 70 dB ESD damage can degrade input current leakage. The input bias current is overridden by the input leakage current. Calculated using the box method Specification valid for voltage-follower OAx configuration ILoad RLoad AV CC OAx O/P(OAx) RO/P(OAx) Max 2 CLoad Min 0.2V AV CC-0.2V AV V CC OUT Figure 25. OAx Output Resistance Tests Copyright (c) 2008-2011, Texas Instruments Incorporated 45 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Operational Amplifier (OA) Dynamic Specifications - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER SR TEST CONDITIONS Slew rate TA VCC MIN TYP Fast Mode 1.2 Medium Mode 0.8 Slow Mode 0.3 Open-loop voltage gain m UNIT V/s 100 dB Phase margin CL = 50 pF 60 deg Gain margin CL = 50 pF 20 dB Noninverting, Fast Mode, RL = 47 k, CL = 50 pF 2.2 Gain-bandwidth product (see Figure 26 and Figure 27) GBW MAX Noninverting, Medium Mode, RL = 300 k, CL = 50 pF 2.2 V/3 V 1.4 Noninverting, Slow Mode, RL = 300 k, CL = 50 pF ten(on) Enable time on ten(off) Enable time off MHz 0.5 ton, noninverting, Gain = 1 -55C to 125C 2.2 V/3 V -55C to 125C 2.2 V/3 V TYPICAL OPEN-LOOP GAIN vs FREQUENCY 10 20 s 1 s TYPICAL PHASE vs FREQUENCY 140 0 120 100 -50 80 Fast Mode Fast Mode Phase - degrees Gain - dB 60 40 Medium Mode 20 0 Slow Mode -100 Medium Mode -150 -20 Slow Mode -40 -200 -60 -80 1 10 100 1000 10000 100000 Input Frequency - kHz -250 1 10 100 1000 10000 100000 Input Frequency - kHz Figure 26. Figure 27. Operational Amplifier OA Feedback Network, Resistor Network - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Rtotal Total resistance of resistor string Runit Unit resistor of resistor string (2) (1) (2) 46 TEST CONDITIONS TA MIN TYP MAX UNIT 96 k 6 k A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal. For the matching (i.e., the relative accuracy) of the unit resistors on a device, refer to the gain and level specifications of the respective configurations. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VLevel Comparator level MIN TYP MAX OAFBRx = 1, OARRIP = 0 TEST CONDITIONS -55C to 125C TA VCC 0.242 1/4 0.262 OAFBRx = 2, OARRIP = 0 -55C to 125C 0.492 1/2 0.512 OAFBRx = 3, OARRIP = 0 -55C to 125C 0.619 5/8 0.639 OAFBRx = 4, OARRIP = 0 N/A (1) OAFBRx = 5, OARRIP = 0 N/A (1) OAFBRx = 6, OARRIP = 0 N/A (1) OAFBRx = 7, OARRIP = 0 OAFBRx = 1, OARRIP = 1 -55C to 125C OAFBRx = 2, OARRIP = 1 -55C to 125C OAFBRx = 3, OARRIP = 1 -55C to 125C OAFBRx = 4, OARRIP = 1 2.2 V/3 V N/A (1) 0.057 1/16 0.071 0.122 1/8 0.128 0.182 3/16 0.197 -55C to 125C 0.242 1/4 0.262 OAFBRx = 5, OARRIP = 1 -55C to 125C 0.367 3/8 0.383 OAFBRx = 6, OARRIP = 1 -55C to 125C 0.492 1/2 0.512 Fast Mode, Overdrive 10 mV 40 Fast Mode, Overdrive 100 mV 4 Fast Mode, Overdrive 500 mV 3 Medium Mode, Overdrive 10 mV Propagation delay (low-high and high-low) 60 Medium Mode, Overdrive 100 mV 2.2 V/3 V s 6 Medium Mode, Overdrive 500 mV (1) VCC N/A (1) OAFBRx = 7, OARRIP = 1 tPLH, tPHL UNIT 5 Slow Mode, Overdrive 10 mV 160 Slow Mode, Overdrive 100 mV 20 Slow Mode, Overdrive 500 mV 15 The level is not available due to the analog input voltage range of the operational amplifier. Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER G Gain TEST CONDITIONS VCC MIN TYP MAX UNIT OAFBRx = 0 -55C to 125C 0.970 1.00 1.035 OAFBRx = 1 -55C to 125C 1.325 1.334 1.345 OAFBRx = 2 -55C to 125C 1.985 2.001 2.017 OAFBRx = 3 -55C to 125C 2.638 2.667 2.696 OAFBRx = 4 -55C to 125C 3.94 4.00 4.06 OAFBRx = 5 -55C to 125C 5.22 5.33 5.44 OAFBRx = 6 -55C to 125C 7.76 7.97 8.18 OAFBRx = 7 -55C to 125C 15.0 15.8 16.7 THD Total harmonic distortion/nonlinearity All gains tSettle Settling time (1) All power modes (1) TA -55C to 125C 2.2 V/3 V 2.2 V -60 3V -70 2.2 V/3 V 7 dB 12 s The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. Copyright (c) 2008-2011, Texas Instruments Incorporated 47 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6) - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER G Gain MIN TYP OAFBRx = 1 TEST CONDITIONS -55C to 125C -0.385 -0.335 -0.305 OAFBRx = 2 -55C to 125C -1.023 -1.002 -0.979 OAFBRx = 3 -55C to 125C -1.712 -1.668 -1.624 OAFBRx = 4 -55C to 125C -3.10 -3.00 -2.90 OAFBRx = 5 -55C to 125C -4.51 -4.33 -4.15 OAFBRx = 6 -55C to 125C -7.37 -6.97 -6.57 OAFBRx = 7 -55C to 125C -16.6 -14.8 -13.1 THD Total harmonic distortion/nonlinearity All gains tSettle Settling time (2) All power modes (1) (2) TA VCC -55C to 125C 2.2 V/3 V 2.2 V -60 3V -70 2.2 V/3 V MAX UNIT dB 7 s 12 This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. Flash Memory - Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIO NS TA VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage -55C to 125C 2.2 3.6 V fFTG Flash timing generator frequency -55C to 125C 257 476 kHz IPGM Supply current from VCC during program -55C to 125C 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase -55C to 125C 2.2 V/3.6 V 1 10.5 mA tCPT Cumulative program time (2) -55C to 125C 2.2 V/3.6 V 10 ms tCMErase Cumulative mass erase time -55C to 125C 2.2 V/3.6 V Program/Erase endurance -55C to 125C tRetention Data retention duration (3) TJ = 25C 20 104 ms 105 100 cycles years Word or byte program time (4) 30 tFTG 0 Block program time for 1st byte or word (4) 25 tFTG tBlock, 1-63 Block program time for each additional byte or word (4) 18 tFTG tBlock, End Block program end-sequence wait time (4) 6 tFTG tMass Erase Mass erase time (4) 1059 3 tFTG tSeg Erase Segment erase time (4) 4819 tFTG tWord tBlock, (1) (2) (3) (4) Additional Flash retention documentation located in application report (SLAA392). The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. To test the flash data retention at various temperatures we make use of accelerated tests on the flash with 500-Hours Baking Time at 250C. These tests are wholly based on Arrhenius law and equation. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). RAM - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) 48 RAM retention supply voltage TEST CONDITIONS (1) CPU halted TA -55C to 125C MIN MAX UNIT 1.6 V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com JTAG and Spy-Bi-Wire Interface - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fSBW TEST CONDITIONS Spy-Bi-Wire input frequency tSBW,Low Spy-Bi-Wire low clock pulse length TA VCC MIN TYP MAX UNIT -55C to 125C 2.2 V/3 V 0 20 MHz -55C to 125C 2.2 V/3 V 0.02 5 15 s 1 s 100 s tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) -55C to 125C 2.2 V/3 V tSBW,Ret Spy-Bi-Wire return to normal operation time -55C to 125C 2.2 V/3 V 15 fTCK TCK input frequency (2) -55C to 125C 2.2 V 0 5 MHz 3V 0 10 MHz RInternal Internal pulldown resistance on TEST -55C to 125C 2.2 V/3 V 25 90 k (1) (2) 60 Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (1) - Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TA = 25C 2.5 MAX UNIT VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow -55C to 125C IFB Supply current into TEST during fuse blow -55C to 125C 100 mA tFB Time to blow fuse -55C to 125C 1 ms (1) 6 V 7 V Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Copyright (c) 2008-2011, Texas Instruments Incorporated 49 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x Set Interrupt Edge Select P1SEL.x P1IES.x Port P1 (P1.0 to P1.3) Pin Functions PIN NAME (P1.X) FUNCTION (1) X P1.0 (3) P1.0/TACLK/ADC10CLK 0 Timer_A3.TACLK ADC10CLK P1.1 P1.1/TA0 1 (4) (I/O) Timer_A3.CCI0A Timer_A3.TA0 2 (1) (2) (3) (4) 50 3 P1SEL.x 0 0 1 1 1 I: 0; O: 1 0 0 1 1 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.3 P1.3/TA2 P1DIR.x I: 0; O: 1 I: 0; O: 1 P1.2 (4) (I/O) P1.2/TA1 CONTROL BITS/SIGNALS (2) (4) I/O I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Default after reset (PUC/POR) Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access Features Pad Logic P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x Interrupt Edge Select P1SEL.x P1IES.x To JTAG From JTAG Port P1 (P1.4 to P1.6) Pin Functions PIN NAME (P1.X) FUNCTION (1) X P1.4 (3) (I/O) P1.4/SMCLK/TCK 4 SMCLK TCK P1.5 (3) (I/O) P1.5/TA0/TMS 5 Timer_A3.TA0 TMS (1) (2) (3) (4) 6 P1DIR.x P1SEL.x 4-Wire JTAG I: 0; O: 1 0 0 1 1 0 X X 1 I: 0; O: 1 0 0 1 1 0 X X 1 I: 0; O: 1 0 0 Timer_A3.TA1 1 1 0 TDI/TCLK (4) X X 1 P1.6 (3) (I/O) P1.6/TA1/TDI/TCLK CONTROL BITS/SIGNALS (2) N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Function controlled by JTAG Copyright (c) 2008-2011, Texas Instruments Incorporated 51 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features Pad Logic P1REN.7 P1DIR.7 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.7 DVSS DVCC P1.7/TA2/TDO/TDI Bus Keeper P1SEL.7 EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q Set P1IFG.7 Interrupt Edge Select P1SEL.7 P1IES.7 To JTAG From JTAG From JTAG From JTAG (TDO) Port P1 (P1.7) Pin Functions PIN NAME (P1.X) FUNCTION (1) X P1.7 P1.7/TA2/TDO/TDI (1) (2) (3) (4) 52 7 (3) (I/O) CONTROL BITS/SIGNALS (2) P1DIR.x P1SEL.x 4-Wire JTAG I: 0; O: 1 0 0 Timer_A3.TA2 1 1 0 TDO/TDI (4) X X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Function controlled by JTAG Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P2REN.x P2DIR.x 0 P2OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1 Bus Keeper P2SEL.x EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x Set Interrupt Edge Select P2SEL.x P2IES.x + OA0 - Port P2 (P2.0, P2.2) Pin Functions Pin Name (P2.X) X FUNCTION (1) Y P2.0 P2.0/ACLK/A0/OA0I0 0 0 2 2 (I/O) P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 1 1 0 A0/OA0I0 (4) X X 1 (3) I: 0; O: 1 0 0 Timer_A3.CCI0B (I/O) 0 1 0 Timer_A3.TA0 1 1 0 X X 1 A2/OA0I1 (1) (2) (3) (4) P2DIR.x ACLK P2.2 P2.2/TA0/A2/OA0I1 (3) CONTROL BITS/SIGNALS (2) (4) N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated 53 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 1 ADC10AE0.1 P2REN.1 P2DIR.1 0 P2OUT.1 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.1/TAINCLK/SMCLK/ A1/OA0O Bus Keeper P2SEL.1 EN P2IN.1 EN Module X IN D P2IE.1 P2IRQ.1 EN Q P2IFG.1 Set + OA0 P2SEL.1 P2IES.1 OAADCx OAFCx OAPMx Interrupt Edge Select - (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA0 Feedback Network 54 1 1 Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger SREF2 VSS 0 To ADC 10 VR- Pad Logic 1 To ADC 10 INCHx = 3 ADC10AE0.3 P2REN.3 P2DIR.3 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.3 DVSS DVCC P2.3/TA1/ A3/VREF-/VeREF-/ OA1I1/OA1O Bus Keeper P2SEL.3 EN P2IN.3 EN Module X IN D P2IE.3 P2IRQ.3 P2IFG.3 P2SEL.3 P2IES.3 OAADCx OAFCx OAPMx EN Q Set Interrupt Edge Select + OA1 1 - (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA1 Feedback Network Copyright (c) 2008-2011, Texas Instruments Incorporated 1 55 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 (P2.1) Pin Functions PIN NAME (P2.X) X FUNCTION (1) Y P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 Timer_A3.INCLK 0 1 0 SMCLK 1 1 0 A1/OA0O (4) X X 1 P2.1 (3) (I/O) P2.1/TAINCLK/SMCLK/A1/OA0O (1) (2) (3) (4) 1 1 CONTROL BITS/SIGNALS (2) N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Port P2 (P2.3) Pin Functions PIN NAME (P2.X) X Y FUNCTION (1) P2.3 (3) (I/O) P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA1O (1) (2) (3) (4) 56 3 3 Timer_A3.CCI1B CONTROL BITS/SIGNALS (2) P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 0 1 0 Timer_A3.TA1 1 1 0 A3/VREF-/VeREF-/OA1I1/OA1O (4) X X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger Pad Logic To /from ADC10 positive reference To ADC 10 INCHx = 4 ADC10AE0.4 P2REN.4 P2DIR.4 0 P2OUT.4 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 Bus Keeper P2SEL.4 EN P2IN.4 EN Module X IN D P2IE.4 P2IRQ.4 EN Q P2IFG.4 Set Interrupt Edge Select P2SEL.4 P2IES.4 + OA1 - Port P2 (P2.4) Pin Functions PIN NAME (P2.X) X FUNCTION (1) Y P2.4 P2.4/TA2/A4/VREF+/VeREF+/OA1I0 (1) (2) (3) (4) 4 4 (3) (I/O) CONTROL BITS/SIGNALS (2) P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 Timer_A3.TA2 1 1 0 A4/VREF+/VeREF+/OA1I0 (4) X X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated 57 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO Pad Logic To DCO DCOR P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P2.5/ROSC Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x Set Interrupt Edge Select P1SEL.x P1IES.x Port P2 (P2.5) Pin Functions PIN NAME (P2.X) X FUNCTION P2.5 (2) (I/O) P2.5/ROSC (1) (2) (3) 58 5 N/A (3) CONTROL BITS/SIGNALS (1) P2DIR.x P2SEL.x DCOR 0/1 0 0 0 1 0 DVSS 1 1 0 ROSC X X 1 X: Don't care Default after reset (PUC/POR) N/A: Not available or not applicable Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 Pad Logic P2SEL.7 P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS DVCC P2.6/XIN Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q Set P2IFG.6 Interrupt Edge Select P2SEL.6 P2IES.6 Port P2 (P2.6) Pin Functions PIN NAME (P2.X) P2.6/XIN (1) (2) (3) FUNCTION (1) X 6 CONTROL BITS/SIGNALS (2) P2DIR.x P2SEL.x P2.6 (I/O) I: 0; O: 1 0 (3) X 1 XIN N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Copyright (c) 2008-2011, Texas Instruments Incorporated 59 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS DVCC P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 P2SEL.7 P2IES.7 Set Interrupt Edge Select Port P2 (P2.7) Pin Functions PIN NAME (P2.X) XOUT/P2.7 (1) (2) (3) (4) 60 FUNCTION (1) X 6 P2.7 (I/O) XOUT (3) (4) CONTROL BITS/SIGNALS (2) P2DIR.x P2SEL.x I: 0; O: 1 0 X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 5 ADC10AE0.5 P3REN.0 P3DIR.0 USCI Direction Control 0 P3OUT.0 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.0/UC1STE/UC0CLK/A5 Bus Keeper P3SEL.0 EN P3IN.0 EN Module X IN D Port P3 (P3.0) Pin Functions PIN NAME (P1.X) X FUNCTION (1) Y P3.0 P3.0/UC1STE/UC0CLK/A5 0 5 (3) A5 (6) (1) (2) (3) (4) (5) (6) (I/O) UC1STE/UC0CLK (4) (5) CONTROL BITS/SIGNALS (2) P3DIR.x P3SEL.x ADC10AE0.y I: 0; O: 1 0 0 X 1 0 X X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) The pin direction is controlled by the USCI module. UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated 61 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger Pad Logic DVSS P3REN.x P3DIR.x USCI Direction Control 0 P3OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.1/UC1SIMO/UC1SCL P3.2/UC1SOMI/UC1SDA P3.3/UC1CLK/UC0STE P3.4/UC0TXD/UC0SIMO P3.5/UC0RXD/UC0SOMI Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D Port P3 (P3.1 to P3.5) Pin Functions PIN NAME (P3.X) P3.1/UC1SIMO/UC1SDA P3.2/UC1SOMI/UC1SCL P3.3/UC1CLK/UC0STE P3.4/UC0TXD/UC0SIMO P3.5/UC0RXD/UC0SOMI (1) (2) (3) (4) (5) (6) (7) 62 FUNCTION (1) X 1 1 1 1 1 P3.1 (3) (I/O) UC1SIMO/UC1SDA (4) P3.2 (5) (I/O) UC1SOMI/UC1SCL (6) P3.3 (5) (I/O) UC1CLK/UC0STE (6) (7) P3.4 (5) (I/O) UC0TXD/UC0SIMO (6) P3.5 (5) (I/O) UC0RXD/UC0SOMI (6) CONTROL BITS/SIGNALS (2) P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) The pin direction is controlled by the USCI module. Default after reset (PUC/POR) The pin direction is controlled by the USCI module. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output, USCI0 is orced to 3-wire SPI mode even if 4-wire SPI mode is selected. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P3REN.x P3DIR.x 0 P3OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P3.6/A6/OA0I2 P3.7/A7/OA1I2 Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D + OA0/1 - Port P3 (P3.6, P3.7) Pin Functions PIN NAME (P3.X) P3.6/A6/OA0I2 P3.7/A7/OA1I2 (1) (2) (3) (4) (5) X 6 7 FUNCTION (1) Y 6 7 P3.6 (4) (I/O) CONTROL BITS/SIGNALS (3) (2) P3DIR.x P3SEL.x ADC10AE0.y I: 0; O: 1 0 0 A6/OA0I2 (5) X X 1 P3.7 (4) (I/O) I: 0; O: 1 0 0 A7/OA1I2 (5) X X 1 N/A: Not available or not applicable UC0CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output, USCI0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. X: Don't care Default after reset (PUC/POR) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated 63 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic P4REN.x P4DIR.x 0 P4OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.0/TB0 P4.1/TB1 P4.2/TB2 Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Port P4 (P4.0 to P4.2) Pin Functions PIN NAME (P4.X) FUNCTION (1) X P4.0 P4.0/TB0 0 (2) (I/O) 1 I: 0; O: 1 0 0 1 Timer_B3.TB0 1 1 I: 0; O: 1 0 Timer_B3.CCI1A 0 1 Timer_B3.TB1 1 1 I: 0; O: 1 0 Timer_B3.CCI2A 0 1 Timer_B3.TB2 1 1 P4.2 (2) (I/O) P4.2/TB2 (1) (2) 64 2 P4SEL.x Timer_B3.CCI0A P4.1 (2) (I/O) P4.1/TB1 CONTROL BITS/SIGNALS P4DIR.x N/A: Not available or not applicable. Default after reset (PUC/POR) Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 INCHx = 8+y ADC10AE1.y P4REN.x P4DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS DVCC P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D + OA0/1 - OAADCx OAPMx 1 OAADCx = 01 and OAPMx > 00 To OA0/1 Feedback Network 1 If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output, respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled. Copyright (c) 2008-2011, Texas Instruments Incorporated 65 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 (P4.3 to P4.4) Pin Functions PIN NAME (P4.X) X FUNCTION (1) Y P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 Timer_B3.CCI0B 0 1 0 Timer_B3.TB0 1 1 0 A12/OA0O (4) X X 1 P4.4 (3) (I/O) I: 0; O: 1 0 0 Timer_B3.CCI1B 0 1 0 Timer_B3.TB1 1 1 0 A13/OA1O (4) X X 1 P4.3 (3) (I/O) P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O (1) (2) (3) (4) 66 3 4 4 5 CONTROL BITS/SIGNALS (2) N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 INCHx = 14 ADC10AE1.6 P4REN.5 P4DIR.5 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.5 DVSS P4.5/TB3/A14/OA0I3 Bus Keeper P4SEL.5 EN P4IN.5 EN Module X IN D + OA0 - Port P4 (P4.5) Pin Functions PIN NAME (P4.X) X FUNCTION (1) Y P4.5 P4.5/TB3/A14/OA0I3 (1) (2) (3) (4) 5 6 (3) (I/O) CONTROL BITS/SIGNALS (2) P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 Timer_B3.TB2 1 1 0 A14/OA0I3 (4) X X 1 N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated 67 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger Pad Logic To ADC 10 INCHx = 15 ADC10AE1.7 P4REN.6 P4DIR.6 0 P4OUT.6 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.6/TBOUTH/ A15/OA1I3 Bus Keeper P4SEL.6 EN P4IN.6 EN Module X IN D + OA1 - Port P4 (P4.6) Pin Functions PIN NAME (P4.X) X FUNCTION (1) Y P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 TBOUTH 0 1 0 DVSS 1 1 0 A15/OA1I3 (4) X X 1 P4.6 (3) (I/O) P4.6/TBOUTH/A15/OA1I3 (1) (2) (3) (4) 68 6 7 CONTROL BITS/SIGNALS (2) N/A: Not available or not applicable X: Don't care Default after reset (PUC/POR) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright (c) 2008-2011, Texas Instruments Incorporated MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger Pad Logic DVSS P4REN.x P4DIR.x 0 P4OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.7/TBCLK Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Port P4 (Pr.7) Pin Functions PIN NAME (P4.X) FUNCTION (1) X P4.7 P4.7/TBCLK (1) (2) 7 (2) (I/O) CONTROL BITS/SIGNALS P4DIR.x P4SEL.x I: 0; O: 1 0 Timer_B3.TBCLK 0 1 DVSS 1 1 N/A: Not available or not applicable Default after reset (PUC/POR) Copyright (c) 2008-2011, Texas Instruments Incorporated 69 MSP430F2274-EP SLAS614D - SEPTEMBER 2008 - REVISED MAY 2011 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 28. Fuse Check Mode Current, MSP430F22xx NOTE The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information. 70 Copyright (c) 2008-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) MSP430F2274MDATEP ACTIVE TSSOP DA 38 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 M430F2274MEP MSP430F2274MRHATEP ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 M4F2274 MRHATEP V62/08631-01XE ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 M4F2274 MRHATEP V62/08631-01YE ACTIVE TSSOP DA 38 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 M430F2274MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF MSP430F2274-EP : * Catalog: MSP430F2274 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F2274MRHATEP Package Package Pins Type Drawing VQFN RHA 40 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.1 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2274MRHATEP VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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